[linux-2.6-block.git] / drivers / mfd / asic3.c

/*
 * driver/mfd/asic3.c
 *
 * Compaq ASIC3 support.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Copyright 2001 Compaq Computer Corporation.
 * Copyright 2004-2005 Phil Blundell
 * Copyright 2007-2008 OpenedHand Ltd.
 *
 * Authors: Phil Blundell <pb@handhelds.org>,
 *	    Samuel Ortiz <sameo@openedhand.com>
 *
 */

#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>

#include <linux/mfd/asic3.h>

struct asic3 {
	void __iomem *mapping;
	unsigned int bus_shift;
	unsigned int irq_nr;
	unsigned int irq_base;
	spinlock_t lock;
	u16 irq_bothedge[4];
	struct gpio_chip gpio;
	struct device *dev;
};

static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);

static inline void asic3_write_register(struct asic3 *asic,
				 unsigned int reg, u32 value)
{
	iowrite16(value, asic->mapping +
		  (reg >> asic->bus_shift));
}

static inline u32 asic3_read_register(struct asic3 *asic,
			       unsigned int reg)
{
	return ioread16(asic->mapping +
			(reg >> asic->bus_shift));
}

/* IRQs */
#define MAX_ASIC_ISR_LOOPS    20
#define ASIC3_GPIO_BASE_INCR \
	(ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)

static void asic3_irq_flip_edge(struct asic3 *asic,
				u32 base, int bit)
{
	u16 edge;
	unsigned long flags;

	spin_lock_irqsave(&asic->lock, flags);
	edge = asic3_read_register(asic,
				   base + ASIC3_GPIO_EDGE_TRIGGER);
	edge ^= bit;
	asic3_write_register(asic,
			     base + ASIC3_GPIO_EDGE_TRIGGER, edge);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
{
	int iter, i;
	unsigned long flags;
	struct asic3 *asic;

	desc->chip->ack(irq);

	asic = desc->handler_data;

	for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
		u32 status;
		int bank;

		spin_lock_irqsave(&asic->lock, flags);
		status = asic3_read_register(asic,
					     ASIC3_OFFSET(INTR, P_INT_STAT));
		spin_unlock_irqrestore(&asic->lock, flags);

		/* Check all ten register bits */
		if ((status & 0x3ff) == 0)
			break;

		/* Handle GPIO IRQs */
		for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
			if (status & (1 << bank)) {
				unsigned long base, istat;

				base = ASIC3_GPIO_A_BASE
				       + bank * ASIC3_GPIO_BASE_INCR;

				spin_lock_irqsave(&asic->lock, flags);
				istat = asic3_read_register(asic,
							    base +
							    ASIC3_GPIO_INT_STATUS);
				/* Clearing IntStatus */
				asic3_write_register(asic,
						     base +
						     ASIC3_GPIO_INT_STATUS, 0);
				spin_unlock_irqrestore(&asic->lock, flags);

				for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
					int bit = (1 << i);
					unsigned int irqnr;

					if (!(istat & bit))
						continue;

					irqnr = asic->irq_base +
						(ASIC3_GPIOS_PER_BANK * bank)
						+ i;
					desc = irq_to_desc(irqnr);
					desc->handle_irq(irqnr, desc);
					if (asic->irq_bothedge[bank] & bit)
						asic3_irq_flip_edge(asic, base,
								    bit);
				}
			}
		}

		/* Handle remaining IRQs in the status register */
		for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
			/* They start at bit 4 and go up */
			if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
				desc = irq_to_desc(asic->irq_base + i);
				desc->handle_irq(asic->irq_base + i,
						 desc);
			}
		}
	}

	if (iter >= MAX_ASIC_ISR_LOOPS)
		dev_err(asic->dev, "interrupt processing overrun\n");
}

static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
{
	int n;

	n = (irq - asic->irq_base) >> 4;

	return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
}

static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
{
	return (irq - asic->irq_base) & 0xf;
}

static void asic3_mask_gpio_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	u32 val, bank, index;
	unsigned long flags;

	bank = asic3_irq_to_bank(asic, irq);
	index = asic3_irq_to_index(asic, irq);

	spin_lock_irqsave(&asic->lock, flags);
	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
	val |= 1 << index;
	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_mask_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	int regval;
	unsigned long flags;

	spin_lock_irqsave(&asic->lock, flags);
	regval = asic3_read_register(asic,
				     ASIC3_INTR_BASE +
				     ASIC3_INTR_INT_MASK);

	regval &= ~(ASIC3_INTMASK_MASK0 <<
		    (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));

	asic3_write_register(asic,
			     ASIC3_INTR_BASE +
			     ASIC3_INTR_INT_MASK,
			     regval);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_unmask_gpio_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	u32 val, bank, index;
	unsigned long flags;

	bank = asic3_irq_to_bank(asic, irq);
	index = asic3_irq_to_index(asic, irq);

	spin_lock_irqsave(&asic->lock, flags);
	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
	val &= ~(1 << index);
	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_unmask_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	int regval;
	unsigned long flags;

	spin_lock_irqsave(&asic->lock, flags);
	regval = asic3_read_register(asic,
				     ASIC3_INTR_BASE +
				     ASIC3_INTR_INT_MASK);

	regval |= (ASIC3_INTMASK_MASK0 <<
		   (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));

	asic3_write_register(asic,
			     ASIC3_INTR_BASE +
			     ASIC3_INTR_INT_MASK,
			     regval);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	u32 bank, index;
	u16 trigger, level, edge, bit;
	unsigned long flags;

	bank = asic3_irq_to_bank(asic, irq);
	index = asic3_irq_to_index(asic, irq);
	bit = 1<<index;

	spin_lock_irqsave(&asic->lock, flags);
	level = asic3_read_register(asic,
				    bank + ASIC3_GPIO_LEVEL_TRIGGER);
	edge = asic3_read_register(asic,
				   bank + ASIC3_GPIO_EDGE_TRIGGER);
	trigger = asic3_read_register(asic,
				      bank + ASIC3_GPIO_TRIGGER_TYPE);
	asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;

	if (type == IRQ_TYPE_EDGE_RISING) {
		trigger |= bit;
		edge |= bit;
	} else if (type == IRQ_TYPE_EDGE_FALLING) {
		trigger |= bit;
		edge &= ~bit;
	} else if (type == IRQ_TYPE_EDGE_BOTH) {
		trigger |= bit;
		if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
			edge &= ~bit;
		else
			edge |= bit;
		asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
	} else if (type == IRQ_TYPE_LEVEL_LOW) {
		trigger &= ~bit;
		level &= ~bit;
	} else if (type == IRQ_TYPE_LEVEL_HIGH) {
		trigger &= ~bit;
		level |= bit;
	} else {
		/*
		 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
		 * be careful to not unmask them if mask was also called.
		 * Probably need internal state for mask.
		 */
		dev_notice(asic->dev, "irq type not changed\n");
	}
	asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
			     level);
	asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
			     edge);
	asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
			     trigger);
	spin_unlock_irqrestore(&asic->lock, flags);
	return 0;
}

static struct irq_chip asic3_gpio_irq_chip = {
	.name		= "ASIC3-GPIO",
	.ack		= asic3_mask_gpio_irq,
	.mask		= asic3_mask_gpio_irq,
	.unmask		= asic3_unmask_gpio_irq,
	.set_type	= asic3_gpio_irq_type,
};

static struct irq_chip asic3_irq_chip = {
	.name		= "ASIC3",
	.ack		= asic3_mask_irq,
	.mask		= asic3_mask_irq,
	.unmask		= asic3_unmask_irq,
};

static int __init asic3_irq_probe(struct platform_device *pdev)
{
	struct asic3 *asic = platform_get_drvdata(pdev);
	unsigned long clksel = 0;
	unsigned int irq, irq_base;
	int ret;

	ret = platform_get_irq(pdev, 0);
	if (ret < 0)
		return ret;
	asic->irq_nr = ret;

	/* turn on clock to IRQ controller */
	clksel |= CLOCK_SEL_CX;
	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
			     clksel);

	irq_base = asic->irq_base;

	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
		if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
			set_irq_chip(irq, &asic3_gpio_irq_chip);
		else
			set_irq_chip(irq, &asic3_irq_chip);

		set_irq_chip_data(irq, asic);
		set_irq_handler(irq, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
			     ASIC3_INTMASK_GINTMASK);

	set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
	set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
	set_irq_data(asic->irq_nr, asic);

	return 0;
}

static void asic3_irq_remove(struct platform_device *pdev)
{
	struct asic3 *asic = platform_get_drvdata(pdev);
	unsigned int irq, irq_base;

	irq_base = asic->irq_base;

	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
		set_irq_flags(irq, 0);
		set_irq_handler(irq, NULL);
		set_irq_chip(irq, NULL);
		set_irq_chip_data(irq, NULL);
	}
	set_irq_chained_handler(asic->irq_nr, NULL);
}

/* GPIOs */
static int asic3_gpio_direction(struct gpio_chip *chip,
				unsigned offset, int out)
{
	u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
	unsigned int gpio_base;
	unsigned long flags;
	struct asic3 *asic;

	asic = container_of(chip, struct asic3, gpio);
	gpio_base = ASIC3_GPIO_TO_BASE(offset);

	if (gpio_base > ASIC3_GPIO_D_BASE) {
		dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
			gpio_base, offset);
		return -EINVAL;
	}

	spin_lock_irqsave(&asic->lock, flags);

	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);

	/* Input is 0, Output is 1 */
	if (out)
		out_reg |= mask;
	else
		out_reg &= ~mask;

	asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);

	spin_unlock_irqrestore(&asic->lock, flags);

	return 0;

}

static int asic3_gpio_direction_input(struct gpio_chip *chip,
				      unsigned offset)
{
	return asic3_gpio_direction(chip, offset, 0);
}

static int asic3_gpio_direction_output(struct gpio_chip *chip,
				       unsigned offset, int value)
{
	return asic3_gpio_direction(chip, offset, 1);
}

static int asic3_gpio_get(struct gpio_chip *chip,
			  unsigned offset)
{
	unsigned int gpio_base;
	u32 mask = ASIC3_GPIO_TO_MASK(offset);
	struct asic3 *asic;

	asic = container_of(chip, struct asic3, gpio);
	gpio_base = ASIC3_GPIO_TO_BASE(offset);

	if (gpio_base > ASIC3_GPIO_D_BASE) {
		dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
			gpio_base, offset);
		return -EINVAL;
	}

	return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
}

static void asic3_gpio_set(struct gpio_chip *chip,
			   unsigned offset, int value)
{
	u32 mask, out_reg;
	unsigned int gpio_base;
	unsigned long flags;
	struct asic3 *asic;

	asic = container_of(chip, struct asic3, gpio);
	gpio_base = ASIC3_GPIO_TO_BASE(offset);

	if (gpio_base > ASIC3_GPIO_D_BASE) {
		dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
			gpio_base, offset);
		return;
	}

	mask = ASIC3_GPIO_TO_MASK(offset);

	spin_lock_irqsave(&asic->lock, flags);

	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);

	if (value)
		out_reg |= mask;
	else
		out_reg &= ~mask;

	asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);

	spin_unlock_irqrestore(&asic->lock, flags);

	return;
}

static __init int asic3_gpio_probe(struct platform_device *pdev,
				   u16 *gpio_config, int num)
{
	struct asic3 *asic = platform_get_drvdata(pdev);
	u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
	u16 out_reg[ASIC3_NUM_GPIO_BANKS];
	u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
	int i;

	memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
	memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
	memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));

	/* Enable all GPIOs */
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);

	for (i = 0; i < num; i++) {
		u8 alt, pin, dir, init, bank_num, bit_num;
		u16 config = gpio_config[i];

		pin = ASIC3_CONFIG_GPIO_PIN(config);
		alt = ASIC3_CONFIG_GPIO_ALT(config);
		dir = ASIC3_CONFIG_GPIO_DIR(config);
		init = ASIC3_CONFIG_GPIO_INIT(config);

		bank_num = ASIC3_GPIO_TO_BANK(pin);
		bit_num = ASIC3_GPIO_TO_BIT(pin);

		alt_reg[bank_num] |= (alt << bit_num);
		out_reg[bank_num] |= (init << bit_num);
		dir_reg[bank_num] |= (dir << bit_num);
	}

	for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
		asic3_write_register(asic,
				     ASIC3_BANK_TO_BASE(i) +
				     ASIC3_GPIO_DIRECTION,
				     dir_reg[i]);
		asic3_write_register(asic,
				     ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
				     out_reg[i]);
		asic3_write_register(asic,
				     ASIC3_BANK_TO_BASE(i) +
				     ASIC3_GPIO_ALT_FUNCTION,
				     alt_reg[i]);
	}

	return gpiochip_add(&asic->gpio);
}

static int asic3_gpio_remove(struct platform_device *pdev)
{
	struct asic3 *asic = platform_get_drvdata(pdev);

	return gpiochip_remove(&asic->gpio);
}


/* Core */
static int __init asic3_probe(struct platform_device *pdev)
{
	struct asic3_platform_data *pdata = pdev->dev.platform_data;
	struct asic3 *asic;
	struct resource *mem;
	unsigned long clksel;
	int map_size;
	int ret = 0;

	asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
	if (asic == NULL) {
		printk(KERN_ERR "kzalloc failed\n");
		return -ENOMEM;
	}

	spin_lock_init(&asic->lock);
	platform_set_drvdata(pdev, asic);
	asic->dev = &pdev->dev;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		ret = -ENOMEM;
		dev_err(asic->dev, "no MEM resource\n");
		goto out_free;
	}

	map_size = mem->end - mem->start + 1;
	asic->mapping = ioremap(mem->start, map_size);
	if (!asic->mapping) {
		ret = -ENOMEM;
		dev_err(asic->dev, "Couldn't ioremap\n");
		goto out_free;
	}

	asic->irq_base = pdata->irq_base;

	/* calculate bus shift from mem resource */
	asic->bus_shift = 2 - (map_size >> 12);

	clksel = 0;
	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);

	ret = asic3_irq_probe(pdev);
	if (ret < 0) {
		dev_err(asic->dev, "Couldn't probe IRQs\n");
		goto out_unmap;
	}

	asic->gpio.base = pdata->gpio_base;
	asic->gpio.ngpio = ASIC3_NUM_GPIOS;
	asic->gpio.get = asic3_gpio_get;
	asic->gpio.set = asic3_gpio_set;
	asic->gpio.direction_input = asic3_gpio_direction_input;
	asic->gpio.direction_output = asic3_gpio_direction_output;

	ret = asic3_gpio_probe(pdev,
			       pdata->gpio_config,
			       pdata->gpio_config_num);
	if (ret < 0) {
		dev_err(asic->dev, "GPIO probe failed\n");
		goto out_irq;
	}

	dev_info(asic->dev, "ASIC3 Core driver\n");

	return 0;

 out_irq:
	asic3_irq_remove(pdev);

 out_unmap:
	iounmap(asic->mapping);

 out_free:
	kfree(asic);

	return ret;
}

static int asic3_remove(struct platform_device *pdev)
{
	int ret;
	struct asic3 *asic = platform_get_drvdata(pdev);

	ret = asic3_gpio_remove(pdev);
	if (ret < 0)
		return ret;
	asic3_irq_remove(pdev);

	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);

	iounmap(asic->mapping);

	kfree(asic);

	return 0;
}

static void asic3_shutdown(struct platform_device *pdev)
{
}

static struct platform_driver asic3_device_driver = {
	.driver		= {
		.name	= "asic3",
	},
	.remove		= __devexit_p(asic3_remove),
	.shutdown	= asic3_shutdown,
};

static int __init asic3_init(void)
{
	int retval = 0;
	retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
	return retval;
}

subsys_initcall(asic3_init);
Commit	Line	Data
fa9ff4b1 SO	1	/*
	2	* driver/mfd/asic3.c
	3	*
	4	* Compaq ASIC3 support.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Copyright 2001 Compaq Computer Corporation.
	11	* Copyright 2004-2005 Phil Blundell
6f2384c4	12	* Copyright 2007-2008 OpenedHand Ltd.
fa9ff4b1 SO	13	*
	14	* Authors: Phil Blundell <pb@handhelds.org>,
	15	* Samuel Ortiz <sameo@openedhand.com>
	16	*
	17	*/
	18
fa9ff4b1 SO	19	#include <linux/kernel.h>
fa9ff4b1 SO	20	#include <linux/irq.h>
6f2384c4	21	#include <linux/gpio.h>
fa9ff4b1 SO	22	#include <linux/io.h>
	23	#include <linux/spinlock.h>
	24	#include <linux/platform_device.h>
	25
	26	#include <linux/mfd/asic3.h>
	27
6f2384c4 SO	28	struct asic3 {
	29	void __iomem *mapping;
	30	unsigned int bus_shift;
	31	unsigned int irq_nr;
	32	unsigned int irq_base;
	33	spinlock_t lock;
	34	u16 irq_bothedge[4];
	35	struct gpio_chip gpio;
	36	struct device *dev;
	37	};
	38
	39	static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
	40
fa9ff4b1 SO	41	static inline void asic3_write_register(struct asic3 *asic,
	42	unsigned int reg, u32 value)
	43	{
b32661e0	44	iowrite16(value, asic->mapping +
fa9ff4b1 SO	45	(reg >> asic->bus_shift));
	46	}
	47
	48	static inline u32 asic3_read_register(struct asic3 *asic,
	49	unsigned int reg)
	50	{
b32661e0	51	return ioread16(asic->mapping +
fa9ff4b1 SO	52	(reg >> asic->bus_shift));
	53	}
	54
	55	/* IRQs */
	56	#define MAX_ASIC_ISR_LOOPS 20
3b8139f8 SO	57	#define ASIC3_GPIO_BASE_INCR \
3b8139f8 SO	58	(ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
fa9ff4b1 SO	59
	60	static void asic3_irq_flip_edge(struct asic3 *asic,
	61	u32 base, int bit)
	62	{
	63	u16 edge;
	64	unsigned long flags;
	65
	66	spin_lock_irqsave(&asic->lock, flags);
	67	edge = asic3_read_register(asic,
3b8139f8	68	base + ASIC3_GPIO_EDGE_TRIGGER);
fa9ff4b1 SO	69	edge ^= bit;
fa9ff4b1 SO	70	asic3_write_register(asic,
3b8139f8	71	base + ASIC3_GPIO_EDGE_TRIGGER, edge);
fa9ff4b1 SO	72	spin_unlock_irqrestore(&asic->lock, flags);
	73	}
	74
	75	static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
	76	{
	77	int iter, i;
	78	unsigned long flags;
	79	struct asic3 *asic;
	80
	81	desc->chip->ack(irq);
	82
	83	asic = desc->handler_data;
	84
	85	for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
	86	u32 status;
	87	int bank;
	88
	89	spin_lock_irqsave(&asic->lock, flags);
	90	status = asic3_read_register(asic,
3b8139f8	91	ASIC3_OFFSET(INTR, P_INT_STAT));
fa9ff4b1 SO	92	spin_unlock_irqrestore(&asic->lock, flags);
	93
	94	/* Check all ten register bits */
	95	if ((status & 0x3ff) == 0)
	96	break;
	97
	98	/* Handle GPIO IRQs */
	99	for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
	100	if (status & (1 << bank)) {
	101	unsigned long base, istat;
	102
3b8139f8 SO	103	base = ASIC3_GPIO_A_BASE
3b8139f8 SO	104	+ bank * ASIC3_GPIO_BASE_INCR;
fa9ff4b1 SO	105
	106	spin_lock_irqsave(&asic->lock, flags);
	107	istat = asic3_read_register(asic,
	108	base +
3b8139f8	109	ASIC3_GPIO_INT_STATUS);
fa9ff4b1 SO	110	/* Clearing IntStatus */
	111	asic3_write_register(asic,
	112	base +
3b8139f8	113	ASIC3_GPIO_INT_STATUS, 0);
fa9ff4b1 SO	114	spin_unlock_irqrestore(&asic->lock, flags);
	115
	116	for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
	117	int bit = (1 << i);
	118	unsigned int irqnr;
	119
	120	if (!(istat & bit))
	121	continue;
	122
	123	irqnr = asic->irq_base +
	124	(ASIC3_GPIOS_PER_BANK * bank)
	125	+ i;
08678b08	126	desc = irq_to_desc(irqnr);
fa9ff4b1 SO	127	desc->handle_irq(irqnr, desc);
	128	if (asic->irq_bothedge[bank] & bit)
	129	asic3_irq_flip_edge(asic, base,
	130	bit);
	131	}
	132	}
	133	}
	134
	135	/* Handle remaining IRQs in the status register */
	136	for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
	137	/* They start at bit 4 and go up */
	138	if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
08678b08	139	desc = irq_to_desc(asic->irq_base + i);
fa9ff4b1 SO	140	desc->handle_irq(asic->irq_base + i,
	141	desc);
	142	}
	143	}
	144	}
	145
	146	if (iter >= MAX_ASIC_ISR_LOOPS)
24f4f2ee	147	dev_err(asic->dev, "interrupt processing overrun\n");
fa9ff4b1 SO	148	}
	149
	150	static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
	151	{
	152	int n;
	153
	154	n = (irq - asic->irq_base) >> 4;
	155
3b8139f8	156	return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
fa9ff4b1 SO	157	}
	158
	159	static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
	160	{
	161	return (irq - asic->irq_base) & 0xf;
	162	}
	163
	164	static void asic3_mask_gpio_irq(unsigned int irq)
	165	{
	166	struct asic3 *asic = get_irq_chip_data(irq);
	167	u32 val, bank, index;
	168	unsigned long flags;
	169
	170	bank = asic3_irq_to_bank(asic, irq);
	171	index = asic3_irq_to_index(asic, irq);
	172
	173	spin_lock_irqsave(&asic->lock, flags);
3b8139f8	174	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
fa9ff4b1	175	val \|= 1 << index;
3b8139f8	176	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
fa9ff4b1 SO	177	spin_unlock_irqrestore(&asic->lock, flags);
	178	}
	179
	180	static void asic3_mask_irq(unsigned int irq)
	181	{
	182	struct asic3 *asic = get_irq_chip_data(irq);
	183	int regval;
	184	unsigned long flags;
	185
	186	spin_lock_irqsave(&asic->lock, flags);
	187	regval = asic3_read_register(asic,
3b8139f8 SO	188	ASIC3_INTR_BASE +
3b8139f8 SO	189	ASIC3_INTR_INT_MASK);
fa9ff4b1 SO	190
	191	regval &= ~(ASIC3_INTMASK_MASK0 <<
	192	(irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
	193
	194	asic3_write_register(asic,
3b8139f8 SO	195	ASIC3_INTR_BASE +
3b8139f8 SO	196	ASIC3_INTR_INT_MASK,
fa9ff4b1 SO	197	regval);
	198	spin_unlock_irqrestore(&asic->lock, flags);
	199	}
	200
	201	static void asic3_unmask_gpio_irq(unsigned int irq)
	202	{
	203	struct asic3 *asic = get_irq_chip_data(irq);
	204	u32 val, bank, index;
	205	unsigned long flags;
	206
	207	bank = asic3_irq_to_bank(asic, irq);
	208	index = asic3_irq_to_index(asic, irq);
	209
	210	spin_lock_irqsave(&asic->lock, flags);
3b8139f8	211	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
fa9ff4b1	212	val &= ~(1 << index);
3b8139f8	213	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
fa9ff4b1 SO	214	spin_unlock_irqrestore(&asic->lock, flags);
	215	}
	216
	217	static void asic3_unmask_irq(unsigned int irq)
	218	{
	219	struct asic3 *asic = get_irq_chip_data(irq);
	220	int regval;
	221	unsigned long flags;
	222
	223	spin_lock_irqsave(&asic->lock, flags);
	224	regval = asic3_read_register(asic,
3b8139f8 SO	225	ASIC3_INTR_BASE +
3b8139f8 SO	226	ASIC3_INTR_INT_MASK);
fa9ff4b1 SO	227
	228	regval \|= (ASIC3_INTMASK_MASK0 <<
	229	(irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
	230
	231	asic3_write_register(asic,
3b8139f8 SO	232	ASIC3_INTR_BASE +
3b8139f8 SO	233	ASIC3_INTR_INT_MASK,
fa9ff4b1 SO	234	regval);
	235	spin_unlock_irqrestore(&asic->lock, flags);
	236	}
	237
	238	static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
	239	{
	240	struct asic3 *asic = get_irq_chip_data(irq);
	241	u32 bank, index;
	242	u16 trigger, level, edge, bit;
	243	unsigned long flags;
	244
	245	bank = asic3_irq_to_bank(asic, irq);
	246	index = asic3_irq_to_index(asic, irq);
	247	bit = 1<<index;
	248
	249	spin_lock_irqsave(&asic->lock, flags);
	250	level = asic3_read_register(asic,
3b8139f8	251	bank + ASIC3_GPIO_LEVEL_TRIGGER);
fa9ff4b1	252	edge = asic3_read_register(asic,
3b8139f8	253	bank + ASIC3_GPIO_EDGE_TRIGGER);
fa9ff4b1	254	trigger = asic3_read_register(asic,
3b8139f8	255	bank + ASIC3_GPIO_TRIGGER_TYPE);
fa9ff4b1 SO	256	asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
fa9ff4b1 SO	257
6cab4860	258	if (type == IRQ_TYPE_EDGE_RISING) {
fa9ff4b1 SO	259	trigger \|= bit;
fa9ff4b1 SO	260	edge \|= bit;
6cab4860	261	} else if (type == IRQ_TYPE_EDGE_FALLING) {
fa9ff4b1 SO	262	trigger \|= bit;
fa9ff4b1 SO	263	edge &= ~bit;
6cab4860	264	} else if (type == IRQ_TYPE_EDGE_BOTH) {
fa9ff4b1	265	trigger \|= bit;
6f2384c4	266	if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
fa9ff4b1 SO	267	edge &= ~bit;
	268	else
	269	edge \|= bit;
	270	asic->irq_bothedge[(irq - asic->irq_base) >> 4] \|= bit;
6cab4860	271	} else if (type == IRQ_TYPE_LEVEL_LOW) {
fa9ff4b1 SO	272	trigger &= ~bit;
fa9ff4b1 SO	273	level &= ~bit;
6cab4860	274	} else if (type == IRQ_TYPE_LEVEL_HIGH) {
fa9ff4b1 SO	275	trigger &= ~bit;
	276	level \|= bit;
	277	} else {
	278	/*
6cab4860	279	* if type == IRQ_TYPE_NONE, we should mask interrupts, but
fa9ff4b1 SO	280	* be careful to not unmask them if mask was also called.
	281	* Probably need internal state for mask.
	282	*/
24f4f2ee	283	dev_notice(asic->dev, "irq type not changed\n");
fa9ff4b1	284	}
3b8139f8	285	asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
fa9ff4b1	286	level);
3b8139f8	287	asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
fa9ff4b1	288	edge);
3b8139f8	289	asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
fa9ff4b1 SO	290	trigger);
	291	spin_unlock_irqrestore(&asic->lock, flags);
	292	return 0;
	293	}
	294
	295	static struct irq_chip asic3_gpio_irq_chip = {
	296	.name = "ASIC3-GPIO",
	297	.ack = asic3_mask_gpio_irq,
	298	.mask = asic3_mask_gpio_irq,
	299	.unmask = asic3_unmask_gpio_irq,
	300	.set_type = asic3_gpio_irq_type,
	301	};
	302
	303	static struct irq_chip asic3_irq_chip = {
	304	.name = "ASIC3",
	305	.ack = asic3_mask_irq,
	306	.mask = asic3_mask_irq,
	307	.unmask = asic3_unmask_irq,
	308	};
	309
065032f6	310	static int __init asic3_irq_probe(struct platform_device *pdev)
fa9ff4b1 SO	311	{
	312	struct asic3 *asic = platform_get_drvdata(pdev);
	313	unsigned long clksel = 0;
	314	unsigned int irq, irq_base;
c491b2ff	315	int ret;
fa9ff4b1	316
c491b2ff RK	317	ret = platform_get_irq(pdev, 0);
	318	if (ret < 0)
	319	return ret;
	320	asic->irq_nr = ret;
fa9ff4b1 SO	321
	322	/* turn on clock to IRQ controller */
	323	clksel \|= CLOCK_SEL_CX;
	324	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
	325	clksel);
	326
	327	irq_base = asic->irq_base;
	328
	329	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
	330	if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
	331	set_irq_chip(irq, &asic3_gpio_irq_chip);
	332	else
	333	set_irq_chip(irq, &asic3_irq_chip);
	334
	335	set_irq_chip_data(irq, asic);
	336	set_irq_handler(irq, handle_level_irq);
	337	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	338	}
	339
3b8139f8	340	asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
fa9ff4b1 SO	341	ASIC3_INTMASK_GINTMASK);
	342
	343	set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
6cab4860	344	set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
fa9ff4b1 SO	345	set_irq_data(asic->irq_nr, asic);
	346
	347	return 0;
	348	}
	349
	350	static void asic3_irq_remove(struct platform_device *pdev)
	351	{
	352	struct asic3 *asic = platform_get_drvdata(pdev);
	353	unsigned int irq, irq_base;
	354
	355	irq_base = asic->irq_base;
	356
	357	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
	358	set_irq_flags(irq, 0);
	359	set_irq_handler(irq, NULL);
	360	set_irq_chip(irq, NULL);
	361	set_irq_chip_data(irq, NULL);
	362	}
	363	set_irq_chained_handler(asic->irq_nr, NULL);
	364	}
	365
	366	/* GPIOs */
6f2384c4 SO	367	static int asic3_gpio_direction(struct gpio_chip *chip,
	368	unsigned offset, int out)
	369	{
	370	u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
	371	unsigned int gpio_base;
	372	unsigned long flags;
	373	struct asic3 *asic;
	374
	375	asic = container_of(chip, struct asic3, gpio);
	376	gpio_base = ASIC3_GPIO_TO_BASE(offset);
	377
3b8139f8	378	if (gpio_base > ASIC3_GPIO_D_BASE) {
24f4f2ee SO	379	dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
24f4f2ee SO	380	gpio_base, offset);
6f2384c4 SO	381	return -EINVAL;
	382	}
	383
	384	spin_lock_irqsave(&asic->lock, flags);
	385
3b8139f8	386	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
6f2384c4 SO	387
	388	/* Input is 0, Output is 1 */
	389	if (out)
	390	out_reg \|= mask;
	391	else
	392	out_reg &= ~mask;
	393
3b8139f8	394	asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
6f2384c4 SO	395
	396	spin_unlock_irqrestore(&asic->lock, flags);
	397
	398	return 0;
	399
	400	}
	401
	402	static int asic3_gpio_direction_input(struct gpio_chip *chip,
	403	unsigned offset)
	404	{
	405	return asic3_gpio_direction(chip, offset, 0);
	406	}
	407
	408	static int asic3_gpio_direction_output(struct gpio_chip *chip,
	409	unsigned offset, int value)
	410	{
	411	return asic3_gpio_direction(chip, offset, 1);
	412	}
	413
	414	static int asic3_gpio_get(struct gpio_chip *chip,
	415	unsigned offset)
	416	{
	417	unsigned int gpio_base;
	418	u32 mask = ASIC3_GPIO_TO_MASK(offset);
	419	struct asic3 *asic;
	420
	421	asic = container_of(chip, struct asic3, gpio);
	422	gpio_base = ASIC3_GPIO_TO_BASE(offset);
	423
3b8139f8	424	if (gpio_base > ASIC3_GPIO_D_BASE) {
24f4f2ee SO	425	dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
24f4f2ee SO	426	gpio_base, offset);
6f2384c4 SO	427	return -EINVAL;
	428	}
	429
3b8139f8	430	return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
6f2384c4 SO	431	}
	432
	433	static void asic3_gpio_set(struct gpio_chip *chip,
	434	unsigned offset, int value)
	435	{
	436	u32 mask, out_reg;
	437	unsigned int gpio_base;
	438	unsigned long flags;
	439	struct asic3 *asic;
	440
	441	asic = container_of(chip, struct asic3, gpio);
	442	gpio_base = ASIC3_GPIO_TO_BASE(offset);
	443
3b8139f8	444	if (gpio_base > ASIC3_GPIO_D_BASE) {
24f4f2ee SO	445	dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
24f4f2ee SO	446	gpio_base, offset);
6f2384c4 SO	447	return;
	448	}
	449
	450	mask = ASIC3_GPIO_TO_MASK(offset);
	451
	452	spin_lock_irqsave(&asic->lock, flags);
	453
3b8139f8	454	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
6f2384c4 SO	455
	456	if (value)
	457	out_reg \|= mask;
	458	else
	459	out_reg &= ~mask;
	460
3b8139f8	461	asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
6f2384c4 SO	462
	463	spin_unlock_irqrestore(&asic->lock, flags);
	464
	465	return;
	466	}
	467
065032f6 PZ	468	static __init int asic3_gpio_probe(struct platform_device *pdev,
065032f6 PZ	469	u16 *gpio_config, int num)
fa9ff4b1	470	{
fa9ff4b1	471	struct asic3 *asic = platform_get_drvdata(pdev);
3b26bf17 SO	472	u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
	473	u16 out_reg[ASIC3_NUM_GPIO_BANKS];
	474	u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
	475	int i;
fa9ff4b1	476
59f0cb0f RK	477	memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
	478	memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
	479	memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
3b26bf17 SO	480
3b26bf17 SO	481	/* Enable all GPIOs */
3b8139f8 SO	482	asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
	483	asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
	484	asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
	485	asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
fa9ff4b1	486
3b26bf17 SO	487	for (i = 0; i < num; i++) {
	488	u8 alt, pin, dir, init, bank_num, bit_num;
	489	u16 config = gpio_config[i];
	490
	491	pin = ASIC3_CONFIG_GPIO_PIN(config);
	492	alt = ASIC3_CONFIG_GPIO_ALT(config);
	493	dir = ASIC3_CONFIG_GPIO_DIR(config);
	494	init = ASIC3_CONFIG_GPIO_INIT(config);
	495
	496	bank_num = ASIC3_GPIO_TO_BANK(pin);
	497	bit_num = ASIC3_GPIO_TO_BIT(pin);
	498
	499	alt_reg[bank_num] \|= (alt << bit_num);
	500	out_reg[bank_num] \|= (init << bit_num);
	501	dir_reg[bank_num] \|= (dir << bit_num);
	502	}
	503
	504	for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
	505	asic3_write_register(asic,
	506	ASIC3_BANK_TO_BASE(i) +
3b8139f8	507	ASIC3_GPIO_DIRECTION,
3b26bf17 SO	508	dir_reg[i]);
3b26bf17 SO	509	asic3_write_register(asic,
3b8139f8	510	ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
3b26bf17 SO	511	out_reg[i]);
	512	asic3_write_register(asic,
	513	ASIC3_BANK_TO_BASE(i) +
3b8139f8	514	ASIC3_GPIO_ALT_FUNCTION,
3b26bf17	515	alt_reg[i]);
fa9ff4b1 SO	516	}
fa9ff4b1 SO	517
6f2384c4	518	return gpiochip_add(&asic->gpio);
fa9ff4b1 SO	519	}
fa9ff4b1 SO	520
6f2384c4	521	static int asic3_gpio_remove(struct platform_device *pdev)
fa9ff4b1	522	{
6f2384c4 SO	523	struct asic3 *asic = platform_get_drvdata(pdev);
	524
	525	return gpiochip_remove(&asic->gpio);
fa9ff4b1 SO	526	}
	527
	528
	529	/* Core */
065032f6	530	static int __init asic3_probe(struct platform_device *pdev)
fa9ff4b1 SO	531	{
	532	struct asic3_platform_data *pdata = pdev->dev.platform_data;
	533	struct asic3 *asic;
	534	struct resource *mem;
	535	unsigned long clksel;
6cac6e84	536	int map_size;
6f2384c4	537	int ret = 0;
fa9ff4b1 SO	538
fa9ff4b1 SO	539	asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
6f2384c4 SO	540	if (asic == NULL) {
6f2384c4 SO	541	printk(KERN_ERR "kzalloc failed\n");
fa9ff4b1	542	return -ENOMEM;
6f2384c4	543	}
fa9ff4b1 SO	544
	545	spin_lock_init(&asic->lock);
	546	platform_set_drvdata(pdev, asic);
	547	asic->dev = &pdev->dev;
	548
	549	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	550	if (!mem) {
	551	ret = -ENOMEM;
24f4f2ee	552	dev_err(asic->dev, "no MEM resource\n");
6f2384c4	553	goto out_free;
fa9ff4b1 SO	554	}
fa9ff4b1 SO	555
99cdb0c8 PZ	556	map_size = mem->end - mem->start + 1;
99cdb0c8 PZ	557	asic->mapping = ioremap(mem->start, map_size);
fa9ff4b1 SO	558	if (!asic->mapping) {
fa9ff4b1 SO	559	ret = -ENOMEM;
24f4f2ee	560	dev_err(asic->dev, "Couldn't ioremap\n");
6f2384c4	561	goto out_free;
fa9ff4b1 SO	562	}
	563
	564	asic->irq_base = pdata->irq_base;
	565
99cdb0c8 PZ	566	/* calculate bus shift from mem resource */
99cdb0c8 PZ	567	asic->bus_shift = 2 - (map_size >> 12);
fa9ff4b1 SO	568
	569	clksel = 0;
	570	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
	571
	572	ret = asic3_irq_probe(pdev);
	573	if (ret < 0) {
24f4f2ee	574	dev_err(asic->dev, "Couldn't probe IRQs\n");
6f2384c4 SO	575	goto out_unmap;
	576	}
	577
	578	asic->gpio.base = pdata->gpio_base;
	579	asic->gpio.ngpio = ASIC3_NUM_GPIOS;
	580	asic->gpio.get = asic3_gpio_get;
	581	asic->gpio.set = asic3_gpio_set;
	582	asic->gpio.direction_input = asic3_gpio_direction_input;
	583	asic->gpio.direction_output = asic3_gpio_direction_output;
	584
3b26bf17 SO	585	ret = asic3_gpio_probe(pdev,
	586	pdata->gpio_config,
	587	pdata->gpio_config_num);
6f2384c4	588	if (ret < 0) {
24f4f2ee	589	dev_err(asic->dev, "GPIO probe failed\n");
6f2384c4	590	goto out_irq;
fa9ff4b1	591	}
fa9ff4b1	592
24f4f2ee	593	dev_info(asic->dev, "ASIC3 Core driver\n");
fa9ff4b1 SO	594
	595	return 0;
	596
6f2384c4 SO	597	out_irq:
	598	asic3_irq_remove(pdev);
	599
	600	out_unmap:
fa9ff4b1	601	iounmap(asic->mapping);
6f2384c4 SO	602
6f2384c4 SO	603	out_free:
fa9ff4b1 SO	604	kfree(asic);
	605
	606	return ret;
	607	}
	608
	609	static int asic3_remove(struct platform_device *pdev)
	610	{
6f2384c4	611	int ret;
fa9ff4b1 SO	612	struct asic3 *asic = platform_get_drvdata(pdev);
fa9ff4b1 SO	613
6f2384c4 SO	614	ret = asic3_gpio_remove(pdev);
	615	if (ret < 0)
	616	return ret;
fa9ff4b1 SO	617	asic3_irq_remove(pdev);
	618
	619	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
	620
	621	iounmap(asic->mapping);
	622
	623	kfree(asic);
	624
	625	return 0;
	626	}
	627
	628	static void asic3_shutdown(struct platform_device *pdev)
	629	{
	630	}
	631
	632	static struct platform_driver asic3_device_driver = {
	633	.driver = {
	634	.name = "asic3",
	635	},
fa9ff4b1 SO	636	.remove = __devexit_p(asic3_remove),
	637	.shutdown = asic3_shutdown,
	638	};
	639
	640	static int __init asic3_init(void)
	641	{
	642	int retval = 0;
065032f6	643	retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
fa9ff4b1 SO	644	return retval;
	645	}
	646
	647	subsys_initcall(asic3_init);