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Merge tag 'char-misc-4.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[linux-2.6-block.git] / drivers / media / pci / ddbridge / ddbridge-core.c
CommitLineData
ccad0457
RM		 1/*
2 * ddbridge.c: Digital Devices PCIe bridge driver
3 *
4 * Copyright (C) 2010-2011 Digital Devices GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/delay.h>
28#include <linux/slab.h>
29#include <linux/poll.h>
28d45a5d 30#include <linux/io.h>
ccad0457
RM		 31#include <linux/pci.h>
32#include <linux/pci_ids.h>
33#include <linux/timer.h>
ccad0457
RM		 34#include <linux/i2c.h>
35#include <linux/swab.h>
36#include <linux/vmalloc.h>
37#include "ddbridge.h"
38
39#include "ddbridge-regs.h"
40
41#include "tda18271c2dd.h"
42#include "stv6110x.h"
43#include "stv090x.h"
44#include "lnbh24.h"
45#include "drxk.h"
46
47DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
48
49/* MSI had problems with lost interrupts, fixed but needs testing */
50#undef CONFIG_PCI_MSI
51
52/******************************************************************************/
53
54static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val)
55{
56 struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
4f1f3107 57 .buf = val, .len = 1 } };
ccad0457
RM		 58 return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
59}
60
61static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val)
62{
63 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
64 .buf = &reg, .len = 1 },
65 {.addr = adr, .flags = I2C_M_RD,
4f1f3107 66 .buf = val, .len = 1 } };
ccad0457
RM		 67 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
68}
69
70static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr,
71 u16 reg, u8 *val)
72{
73 u8 msg[2] = {reg>>8, reg&0xff};
74 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
75 .buf = msg, .len = 2},
76 {.addr = adr, .flags = I2C_M_RD,
4f1f3107 77 .buf = val, .len = 1} };
ccad0457
RM		 78 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
79}
80
81static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd)
82{
83 struct ddb *dev = i2c->dev;
4bdbcb31 84 long stat;
ccad0457
RM		 85 u32 val;
86
87 i2c->done = 0;
88 ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND);
89 stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ);
4bdbcb31 90 if (stat == 0) {
4f1f3107 91 printk(KERN_ERR "I2C timeout\n");
ccad0457
RM		 92 { /* MSI debugging*/
93 u32 istat = ddbreadl(INTERRUPT_STATUS);
4f1f3107 94 printk(KERN_ERR "IRS %08x\n", istat);
ccad0457
RM		 95 ddbwritel(istat, INTERRUPT_ACK);
96 }
97 return -EIO;
98 }
4f1f3107 99 val = ddbreadl(i2c->regs+I2C_COMMAND);
ccad0457
RM		 100 if (val & 0x70000)
101 return -EIO;
102 return 0;
103}
104
105static int ddb_i2c_master_xfer(struct i2c_adapter *adapter,
106 struct i2c_msg msg[], int num)
107{
108 struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter);
109 struct ddb *dev = i2c->dev;
4f1f3107 110 u8 addr = 0;
ccad0457
RM		 111
112 if (num)
113 addr = msg[0].addr;
114
115 if (num == 2 && msg[1].flags & I2C_M_RD &&
116 !(msg[0].flags & I2C_M_RD)) {
117 memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf,
4f1f3107 118 msg[0].buf, msg[0].len);
ccad0457
RM		 119 ddbwritel(msg[0].len|(msg[1].len << 16),
120 i2c->regs+I2C_TASKLENGTH);
121 if (!ddb_i2c_cmd(i2c, addr, 1)) {
122 memcpy_fromio(msg[1].buf,
123 dev->regs + I2C_TASKMEM_BASE + i2c->rbuf,
124 msg[1].len);
125 return num;
126 }
127 }
128
129 if (num == 1 && !(msg[0].flags & I2C_M_RD)) {
4f1f3107 130 ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len);
ccad0457
RM		 131 ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH);
132 if (!ddb_i2c_cmd(i2c, addr, 2))
133 return num;
134 }
135 if (num == 1 && (msg[0].flags & I2C_M_RD)) {
136 ddbwritel(msg[0].len << 16, i2c->regs + I2C_TASKLENGTH);
137 if (!ddb_i2c_cmd(i2c, addr, 3)) {
138 ddbcpyfrom(msg[0].buf,
139 I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len);
140 return num;
141 }
142 }
143 return -EIO;
144}
145
146
147static u32 ddb_i2c_functionality(struct i2c_adapter *adap)
148{
149 return I2C_FUNC_SMBUS_EMUL;
150}
151
b5c00cc5 152static struct i2c_algorithm ddb_i2c_algo = {
ccad0457
RM		 153 .master_xfer = ddb_i2c_master_xfer,
154 .functionality = ddb_i2c_functionality,
155};
156
157static void ddb_i2c_release(struct ddb *dev)
158{
159 int i;
160 struct ddb_i2c *i2c;
161 struct i2c_adapter *adap;
162
163 for (i = 0; i < dev->info->port_num; i++) {
164 i2c = &dev->i2c[i];
165 adap = &i2c->adap;
166 i2c_del_adapter(adap);
167 }
168}
169
170static int ddb_i2c_init(struct ddb *dev)
171{
172 int i, j, stat = 0;
173 struct ddb_i2c *i2c;
174 struct i2c_adapter *adap;
175
176 for (i = 0; i < dev->info->port_num; i++) {
177 i2c = &dev->i2c[i];
178 i2c->dev = dev;
179 i2c->nr = i;
180 i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4);
181 i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8);
182 i2c->regs = 0x80 + i * 0x20;
183 ddbwritel(I2C_SPEED_100, i2c->regs + I2C_TIMING);
184 ddbwritel((i2c->rbuf << 16) | i2c->wbuf,
185 i2c->regs + I2C_TASKADDRESS);
186 init_waitqueue_head(&i2c->wq);
187
188 adap = &i2c->adap;
189 i2c_set_adapdata(adap, i2c);
190#ifdef I2C_ADAP_CLASS_TV_DIGITAL
191 adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG;
192#else
193#ifdef I2C_CLASS_TV_ANALOG
194 adap->class = I2C_CLASS_TV_ANALOG;
195#endif
196#endif
197 strcpy(adap->name, "ddbridge");
198 adap->algo = &ddb_i2c_algo;
199 adap->algo_data = (void *)i2c;
200 adap->dev.parent = &dev->pdev->dev;
201 stat = i2c_add_adapter(adap);
202 if (stat)
203 break;
204 }
205 if (stat)
206 for (j = 0; j < i; j++) {
207 i2c = &dev->i2c[j];
208 adap = &i2c->adap;
209 i2c_del_adapter(adap);
210 }
211 return stat;
212}
213
214
215/******************************************************************************/
216/******************************************************************************/
217/******************************************************************************/
218
4f1f3107 219#if 0
ccad0457
RM		 220static void set_table(struct ddb *dev, u32 off,
221 dma_addr_t *pbuf, u32 num)
222{
223 u32 i, base;
224 u64 mem;
225
226 base = DMA_BASE_ADDRESS_TABLE + off;
227 for (i = 0; i < num; i++) {
228 mem = pbuf[i];
229 ddbwritel(mem & 0xffffffff, base + i * 8);
230 ddbwritel(mem >> 32, base + i * 8 + 4);
231 }
232}
4f1f3107 233#endif
ccad0457
RM		 234
235static void ddb_address_table(struct ddb *dev)
236{
237 u32 i, j, base;
238 u64 mem;
239 dma_addr_t *pbuf;
240
241 for (i = 0; i < dev->info->port_num * 2; i++) {
242 base = DMA_BASE_ADDRESS_TABLE + i * 0x100;
243 pbuf = dev->input[i].pbuf;
244 for (j = 0; j < dev->input[i].dma_buf_num; j++) {
245 mem = pbuf[j];
246 ddbwritel(mem & 0xffffffff, base + j * 8);
247 ddbwritel(mem >> 32, base + j * 8 + 4);
248 }
249 }
250 for (i = 0; i < dev->info->port_num; i++) {
251 base = DMA_BASE_ADDRESS_TABLE + 0x800 + i * 0x100;
252 pbuf = dev->output[i].pbuf;
253 for (j = 0; j < dev->output[i].dma_buf_num; j++) {
254 mem = pbuf[j];
255 ddbwritel(mem & 0xffffffff, base + j * 8);
256 ddbwritel(mem >> 32, base + j * 8 + 4);
257 }
258 }
259}
260
261static void io_free(struct pci_dev *pdev, u8 **vbuf,
262 dma_addr_t *pbuf, u32 size, int num)
263{
264 int i;
265
266 for (i = 0; i < num; i++) {
267 if (vbuf[i]) {
268 pci_free_consistent(pdev, size, vbuf[i], pbuf[i]);
b5c00cc5 269 vbuf[i] = NULL;
ccad0457
RM		 270 }
271 }
272}
273
274static int io_alloc(struct pci_dev *pdev, u8 **vbuf,
275 dma_addr_t *pbuf, u32 size, int num)
276{
277 int i;
278
279 for (i = 0; i < num; i++) {
280 vbuf[i] = pci_alloc_consistent(pdev, size, &pbuf[i]);
281 if (!vbuf[i])
282 return -ENOMEM;
283 }
284 return 0;
285}
286
287static int ddb_buffers_alloc(struct ddb *dev)
288{
289 int i;
290 struct ddb_port *port;
291
292 for (i = 0; i < dev->info->port_num; i++) {
293 port = &dev->port[i];
294 switch (port->class) {
295 case DDB_PORT_TUNER:
296 if (io_alloc(dev->pdev, port->input[0]->vbuf,
297 port->input[0]->pbuf,
298 port->input[0]->dma_buf_size,
299 port->input[0]->dma_buf_num) < 0)
300 return -1;
301 if (io_alloc(dev->pdev, port->input[1]->vbuf,
302 port->input[1]->pbuf,
303 port->input[1]->dma_buf_size,
304 port->input[1]->dma_buf_num) < 0)
305 return -1;
306 break;
307 case DDB_PORT_CI:
308 if (io_alloc(dev->pdev, port->input[0]->vbuf,
309 port->input[0]->pbuf,
310 port->input[0]->dma_buf_size,
311 port->input[0]->dma_buf_num) < 0)
312 return -1;
313 if (io_alloc(dev->pdev, port->output->vbuf,
314 port->output->pbuf,
315 port->output->dma_buf_size,
316 port->output->dma_buf_num) < 0)
317 return -1;
318 break;
319 default:
320 break;
321 }
322 }
323 ddb_address_table(dev);
324 return 0;
325}
326
327static void ddb_buffers_free(struct ddb *dev)
328{
329 int i;
330 struct ddb_port *port;
331
332 for (i = 0; i < dev->info->port_num; i++) {
333 port = &dev->port[i];
334 io_free(dev->pdev, port->input[0]->vbuf,
335 port->input[0]->pbuf,
336 port->input[0]->dma_buf_size,
337 port->input[0]->dma_buf_num);
338 io_free(dev->pdev, port->input[1]->vbuf,
339 port->input[1]->pbuf,
340 port->input[1]->dma_buf_size,
341 port->input[1]->dma_buf_num);
342 io_free(dev->pdev, port->output->vbuf,
343 port->output->pbuf,
344 port->output->dma_buf_size,
345 port->output->dma_buf_num);
346 }
347}
348
349static void ddb_input_start(struct ddb_input *input)
350{
351 struct ddb *dev = input->port->dev;
352
353 spin_lock_irq(&input->lock);
354 input->cbuf = 0;
355 input->coff = 0;
356
357 /* reset */
358 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
359 ddbwritel(2, TS_INPUT_CONTROL(input->nr));
360 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
361
362 ddbwritel((1 << 16) |
363 (input->dma_buf_num << 11) |
364 (input->dma_buf_size >> 7),
365 DMA_BUFFER_SIZE(input->nr));
366 ddbwritel(0, DMA_BUFFER_ACK(input->nr));
367
368 ddbwritel(1, DMA_BASE_WRITE);
369 ddbwritel(3, DMA_BUFFER_CONTROL(input->nr));
370 ddbwritel(9, TS_INPUT_CONTROL(input->nr));
371 input->running = 1;
372 spin_unlock_irq(&input->lock);
373}
374
375static void ddb_input_stop(struct ddb_input *input)
376{
377 struct ddb *dev = input->port->dev;
378
379 spin_lock_irq(&input->lock);
380 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
381 ddbwritel(0, DMA_BUFFER_CONTROL(input->nr));
382 input->running = 0;
383 spin_unlock_irq(&input->lock);
384}
385
386static void ddb_output_start(struct ddb_output *output)
387{
388 struct ddb *dev = output->port->dev;
389
390 spin_lock_irq(&output->lock);
391 output->cbuf = 0;
392 output->coff = 0;
393 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
394 ddbwritel(2, TS_OUTPUT_CONTROL(output->nr));
395 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
396 ddbwritel(0x3c, TS_OUTPUT_CONTROL(output->nr));
397 ddbwritel((1 << 16) |
398 (output->dma_buf_num << 11) |
399 (output->dma_buf_size >> 7),
400 DMA_BUFFER_SIZE(output->nr + 8));
401 ddbwritel(0, DMA_BUFFER_ACK(output->nr + 8));
402
403 ddbwritel(1, DMA_BASE_READ);
404 ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8));
4f1f3107 405 /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */
ccad0457
RM		 406 ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr));
407 output->running = 1;
408 spin_unlock_irq(&output->lock);
409}
410
411static void ddb_output_stop(struct ddb_output *output)
412{
413 struct ddb *dev = output->port->dev;
414
415 spin_lock_irq(&output->lock);
416 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
417 ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8));
418 output->running = 0;
419 spin_unlock_irq(&output->lock);
420}
421
422static u32 ddb_output_free(struct ddb_output *output)
423{
424 u32 idx, off, stat = output->stat;
425 s32 diff;
426
427 idx = (stat >> 11) & 0x1f;
428 off = (stat & 0x7ff) << 7;
429
430 if (output->cbuf != idx) {
431 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
432 (output->dma_buf_size - output->coff <= 188))
433 return 0;
434 return 188;
435 }
436 diff = off - output->coff;
437 if (diff <= 0 || diff > 188)
438 return 188;
439 return 0;
440}
441
4f1f3107 442static ssize_t ddb_output_write(struct ddb_output *output,
b5c00cc5 443 const __user u8 *buf, size_t count)
ccad0457
RM		 444{
445 struct ddb *dev = output->port->dev;
446 u32 idx, off, stat = output->stat;
447 u32 left = count, len;
448
449 idx = (stat >> 11) & 0x1f;
450 off = (stat & 0x7ff) << 7;
451
452 while (left) {
453 len = output->dma_buf_size - output->coff;
454 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
455 (off == 0)) {
4f1f3107 456 if (len <= 188)
ccad0457 457 break;
4f1f3107 458 len -= 188;
ccad0457
RM		 459 }
460 if (output->cbuf == idx) {
461 if (off > output->coff) {
462#if 1
463 len = off - output->coff;
464 len -= (len % 188);
465 if (len <= 188)
466
467#endif
468 break;
469 len -= 188;
470 }
471 }
472 if (len > left)
473 len = left;
474 if (copy_from_user(output->vbuf[output->cbuf] + output->coff,
475 buf, len))
476 return -EIO;
477 left -= len;
478 buf += len;
479 output->coff += len;
480 if (output->coff == output->dma_buf_size) {
481 output->coff = 0;
482 output->cbuf = ((output->cbuf + 1) % output->dma_buf_num);
483 }
484 ddbwritel((output->cbuf << 11) | (output->coff >> 7),
485 DMA_BUFFER_ACK(output->nr + 8));
486 }
487 return count - left;
488}
489
490static u32 ddb_input_avail(struct ddb_input *input)
491{
492 struct ddb *dev = input->port->dev;
493 u32 idx, off, stat = input->stat;
494 u32 ctrl = ddbreadl(DMA_BUFFER_CONTROL(input->nr));
495
496 idx = (stat >> 11) & 0x1f;
497 off = (stat & 0x7ff) << 7;
498
499 if (ctrl & 4) {
4f1f3107 500 printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl);
ccad0457
RM		 501 ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr));
502 return 0;
503 }
504 if (input->cbuf != idx)
505 return 188;
506 return 0;
507}
508
b5c00cc5 509static ssize_t ddb_input_read(struct ddb_input *input, __user u8 *buf, size_t count)
ccad0457
RM		 510{
511 struct ddb *dev = input->port->dev;
512 u32 left = count;
2122eaf6 513 u32 idx, free, stat = input->stat;
ccad0457
RM		 514 int ret;
515
516 idx = (stat >> 11) & 0x1f;
ccad0457
RM		 517
518 while (left) {
519 if (input->cbuf == idx)
520 return count - left;
521 free = input->dma_buf_size - input->coff;
522 if (free > left)
523 free = left;
524 ret = copy_to_user(buf, input->vbuf[input->cbuf] +
525 input->coff, free);
2122eaf6
HV		 526 if (ret)
527 return -EFAULT;
ccad0457
RM		 528 input->coff += free;
529 if (input->coff == input->dma_buf_size) {
530 input->coff = 0;
531 input->cbuf = (input->cbuf+1) % input->dma_buf_num;
532 }
533 left -= free;
534 ddbwritel((input->cbuf << 11) | (input->coff >> 7),
535 DMA_BUFFER_ACK(input->nr));
536 }
537 return count;
538}
539
540/******************************************************************************/
541/******************************************************************************/
542/******************************************************************************/
543
544#if 0
545static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe)
546{
547 int i;
548
549 for (i = 0; i < dev->info->port_num * 2; i++) {
4f1f3107 550 if (dev->input[i].fe == fe)
ccad0457
RM		 551 return &dev->input[i];
552 }
553 return NULL;
554}
555#endif
556
557static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
558{
559 struct ddb_input *input = fe->sec_priv;
560 struct ddb_port *port = input->port;
561 int status;
562
563 if (enable) {
564 mutex_lock(&port->i2c_gate_lock);
565 status = input->gate_ctrl(fe, 1);
566 } else {
567 status = input->gate_ctrl(fe, 0);
568 mutex_unlock(&port->i2c_gate_lock);
569 }
570 return status;
571}
572
573static int demod_attach_drxk(struct ddb_input *input)
574{
575 struct i2c_adapter *i2c = &input->port->i2c->adap;
576 struct dvb_frontend *fe;
0fc55e81 577 struct drxk_config config;
ccad0457 578
0fc55e81 579 memset(&config, 0, sizeof(config));
da989e0b 580 config.microcode_name = "drxk_a3.mc";
9e23f50a 581 config.qam_demod_parameter_count = 4;
0fc55e81
MCC		 582 config.adr = 0x29 + (input->nr & 1);
583
fa4b2a17 584 fe = input->fe = dvb_attach(drxk_attach, &config, i2c);
ccad0457 585 if (!input->fe) {
4f1f3107 586 printk(KERN_ERR "No DRXK found!\n");
ccad0457
RM		 587 return -ENODEV;
588 }
589 fe->sec_priv = input;
590 input->gate_ctrl = fe->ops.i2c_gate_ctrl;
591 fe->ops.i2c_gate_ctrl = drxk_gate_ctrl;
592 return 0;
593}
594
595static int tuner_attach_tda18271(struct ddb_input *input)
596{
597 struct i2c_adapter *i2c = &input->port->i2c->adap;
598 struct dvb_frontend *fe;
599
600 if (input->fe->ops.i2c_gate_ctrl)
601 input->fe->ops.i2c_gate_ctrl(input->fe, 1);
602 fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60);
603 if (!fe) {
4f1f3107 604 printk(KERN_ERR "No TDA18271 found!\n");
ccad0457
RM		 605 return -ENODEV;
606 }
607 if (input->fe->ops.i2c_gate_ctrl)
608 input->fe->ops.i2c_gate_ctrl(input->fe, 0);
609 return 0;
610}
611
612/******************************************************************************/
613/******************************************************************************/
614/******************************************************************************/
615
616static struct stv090x_config stv0900 = {
617 .device = STV0900,
618 .demod_mode = STV090x_DUAL,
619 .clk_mode = STV090x_CLK_EXT,
620
621 .xtal = 27000000,
622 .address = 0x69,
623
624 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
625 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
626
627 .repeater_level = STV090x_RPTLEVEL_16,
628
629 .adc1_range = STV090x_ADC_1Vpp,
630 .adc2_range = STV090x_ADC_1Vpp,
631
632 .diseqc_envelope_mode = true,
633};
634
635static struct stv090x_config stv0900_aa = {
636 .device = STV0900,
637 .demod_mode = STV090x_DUAL,
638 .clk_mode = STV090x_CLK_EXT,
639
640 .xtal = 27000000,
641 .address = 0x68,
642
643 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
644 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
645
646 .repeater_level = STV090x_RPTLEVEL_16,
647
648 .adc1_range = STV090x_ADC_1Vpp,
649 .adc2_range = STV090x_ADC_1Vpp,
650
651 .diseqc_envelope_mode = true,
652};
653
654static struct stv6110x_config stv6110a = {
655 .addr = 0x60,
656 .refclk = 27000000,
657 .clk_div = 1,
658};
659
660static struct stv6110x_config stv6110b = {
661 .addr = 0x63,
662 .refclk = 27000000,
663 .clk_div = 1,
664};
665
666static int demod_attach_stv0900(struct ddb_input *input, int type)
667{
668 struct i2c_adapter *i2c = &input->port->i2c->adap;
669 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
670
4f1f3107
OE		 671 input->fe = dvb_attach(stv090x_attach, feconf, i2c,
672 (input->nr & 1) ? STV090x_DEMODULATOR_1
673 : STV090x_DEMODULATOR_0);
ccad0457 674 if (!input->fe) {
4f1f3107 675 printk(KERN_ERR "No STV0900 found!\n");
ccad0457
RM		 676 return -ENODEV;
677 }
678 if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0,
679 0, (input->nr & 1) ?
680 (0x09 - type) : (0x0b - type))) {
4f1f3107 681 printk(KERN_ERR "No LNBH24 found!\n");
ccad0457
RM		 682 return -ENODEV;
683 }
684 return 0;
685}
686
687static int tuner_attach_stv6110(struct ddb_input *input, int type)
688{
689 struct i2c_adapter *i2c = &input->port->i2c->adap;
690 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
691 struct stv6110x_config *tunerconf = (input->nr & 1) ?
692 &stv6110b : &stv6110a;
242c5033 693 const struct stv6110x_devctl *ctl;
ccad0457
RM		 694
695 ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c);
696 if (!ctl) {
4f1f3107 697 printk(KERN_ERR "No STV6110X found!\n");
ccad0457
RM		 698 return -ENODEV;
699 }
4f1f3107
OE		 700 printk(KERN_INFO "attach tuner input %d adr %02x\n",
701 input->nr, tunerconf->addr);
ccad0457
RM		 702
703 feconf->tuner_init = ctl->tuner_init;
704 feconf->tuner_sleep = ctl->tuner_sleep;
705 feconf->tuner_set_mode = ctl->tuner_set_mode;
706 feconf->tuner_set_frequency = ctl->tuner_set_frequency;
707 feconf->tuner_get_frequency = ctl->tuner_get_frequency;
708 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
709 feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
710 feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
711 feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
712 feconf->tuner_set_refclk = ctl->tuner_set_refclk;
713 feconf->tuner_get_status = ctl->tuner_get_status;
714
715 return 0;
716}
717
805e6874 718static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
ccad0457
RM		 719 int (*start_feed)(struct dvb_demux_feed *),
720 int (*stop_feed)(struct dvb_demux_feed *),
721 void *priv)
722{
723 dvbdemux->priv = priv;
724
725 dvbdemux->filternum = 256;
726 dvbdemux->feednum = 256;
727 dvbdemux->start_feed = start_feed;
728 dvbdemux->stop_feed = stop_feed;
729 dvbdemux->write_to_decoder = NULL;
730 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
731 DMX_SECTION_FILTERING |
732 DMX_MEMORY_BASED_FILTERING);
733 return dvb_dmx_init(dvbdemux);
734}
735
805e6874 736static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
ccad0457
RM		 737 struct dvb_demux *dvbdemux,
738 struct dmx_frontend *hw_frontend,
739 struct dmx_frontend *mem_frontend,
740 struct dvb_adapter *dvb_adapter)
741{
742 int ret;
743
744 dmxdev->filternum = 256;
745 dmxdev->demux = &dvbdemux->dmx;
746 dmxdev->capabilities = 0;
747 ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
748 if (ret < 0)
749 return ret;
750
751 hw_frontend->source = DMX_FRONTEND_0;
752 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
753 mem_frontend->source = DMX_MEMORY_FE;
754 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
755 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
756}
757
758static int start_feed(struct dvb_demux_feed *dvbdmxfeed)
759{
760 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
761 struct ddb_input *input = dvbdmx->priv;
762
763 if (!input->users)
764 ddb_input_start(input);
765
766 return ++input->users;
767}
768
769static int stop_feed(struct dvb_demux_feed *dvbdmxfeed)
770{
771 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
772 struct ddb_input *input = dvbdmx->priv;
773
774 if (--input->users)
775 return input->users;
776
777 ddb_input_stop(input);
778 return 0;
779}
780
781
782static void dvb_input_detach(struct ddb_input *input)
783{
784 struct dvb_adapter *adap = &input->adap;
785 struct dvb_demux *dvbdemux = &input->demux;
786
787 switch (input->attached) {
788 case 5:
789 if (input->fe2)
790 dvb_unregister_frontend(input->fe2);
791 if (input->fe) {
792 dvb_unregister_frontend(input->fe);
793 dvb_frontend_detach(input->fe);
794 input->fe = NULL;
795 }
796 case 4:
797 dvb_net_release(&input->dvbnet);
798
799 case 3:
800 dvbdemux->dmx.close(&dvbdemux->dmx);
801 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
802 &input->hw_frontend);
803 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
804 &input->mem_frontend);
805 dvb_dmxdev_release(&input->dmxdev);
806
807 case 2:
808 dvb_dmx_release(&input->demux);
809
810 case 1:
811 dvb_unregister_adapter(adap);
812 }
813 input->attached = 0;
814}
815
816static int dvb_input_attach(struct ddb_input *input)
817{
818 int ret;
819 struct ddb_port *port = input->port;
820 struct dvb_adapter *adap = &input->adap;
821 struct dvb_demux *dvbdemux = &input->demux;
822
4f1f3107 823 ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE,
ccad0457
RM		 824 &input->port->dev->pdev->dev,
825 adapter_nr);
826 if (ret < 0) {
4f1f3107 827 printk(KERN_ERR "ddbridge: Could not register adapter."
ccad0457
RM		 828 "Check if you enabled enough adapters in dvb-core!\n");
829 return ret;
830 }
831 input->attached = 1;
832
833 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
834 start_feed,
835 stop_feed, input);
836 if (ret < 0)
837 return ret;
838 input->attached = 2;
839
840 ret = my_dvb_dmxdev_ts_card_init(&input->dmxdev, &input->demux,
841 &input->hw_frontend,
842 &input->mem_frontend, adap);
843 if (ret < 0)
844 return ret;
845 input->attached = 3;
846
847 ret = dvb_net_init(adap, &input->dvbnet, input->dmxdev.demux);
848 if (ret < 0)
849 return ret;
850 input->attached = 4;
851
b5c00cc5 852 input->fe = NULL;
ccad0457
RM		 853 switch (port->type) {
854 case DDB_TUNER_DVBS_ST:
855 if (demod_attach_stv0900(input, 0) < 0)
856 return -ENODEV;
857 if (tuner_attach_stv6110(input, 0) < 0)
858 return -ENODEV;
859 if (input->fe) {
860 if (dvb_register_frontend(adap, input->fe) < 0)
861 return -ENODEV;
862 }
863 break;
864 case DDB_TUNER_DVBS_ST_AA:
865 if (demod_attach_stv0900(input, 1) < 0)
866 return -ENODEV;
867 if (tuner_attach_stv6110(input, 1) < 0)
868 return -ENODEV;
869 if (input->fe) {
870 if (dvb_register_frontend(adap, input->fe) < 0)
871 return -ENODEV;
872 }
873 break;
874 case DDB_TUNER_DVBCT_TR:
875 if (demod_attach_drxk(input) < 0)
876 return -ENODEV;
877 if (tuner_attach_tda18271(input) < 0)
878 return -ENODEV;
cdcb12e7
DC		 879 if (dvb_register_frontend(adap, input->fe) < 0)
880 return -ENODEV;
ccad0457
RM		 881 if (input->fe2) {
882 if (dvb_register_frontend(adap, input->fe2) < 0)
883 return -ENODEV;
4f1f3107 884 input->fe2->tuner_priv = input->fe->tuner_priv;
ccad0457
RM		 885 memcpy(&input->fe2->ops.tuner_ops,
886 &input->fe->ops.tuner_ops,
887 sizeof(struct dvb_tuner_ops));
888 }
889 break;
890 }
891 input->attached = 5;
892 return 0;
893}
894
895/****************************************************************************/
896/****************************************************************************/
897
b5c00cc5 898static ssize_t ts_write(struct file *file, const __user char *buf,
ccad0457
RM		 899 size_t count, loff_t *ppos)
900{
901 struct dvb_device *dvbdev = file->private_data;
902 struct ddb_output *output = dvbdev->priv;
903 size_t left = count;
904 int stat;
905
906 while (left) {
907 if (ddb_output_free(output) < 188) {
908 if (file->f_flags & O_NONBLOCK)
909 break;
910 if (wait_event_interruptible(
911 output->wq, ddb_output_free(output) >= 188) < 0)
912 break;
913 }
914 stat = ddb_output_write(output, buf, left);
915 if (stat < 0)
916 break;
917 buf += stat;
918 left -= stat;
919 }
920 return (left == count) ? -EAGAIN : (count - left);
921}
922
b5c00cc5 923static ssize_t ts_read(struct file *file, __user char *buf,
ccad0457
RM		 924 size_t count, loff_t *ppos)
925{
926 struct dvb_device *dvbdev = file->private_data;
927 struct ddb_output *output = dvbdev->priv;
928 struct ddb_input *input = output->port->input[0];
929 int left, read;
930
931 count -= count % 188;
932 left = count;
933 while (left) {
934 if (ddb_input_avail(input) < 188) {
935 if (file->f_flags & O_NONBLOCK)
936 break;
937 if (wait_event_interruptible(
938 input->wq, ddb_input_avail(input) >= 188) < 0)
939 break;
940 }
941 read = ddb_input_read(input, buf, left);
2122eaf6
HV		 942 if (read < 0)
943 return read;
ccad0457
RM		 944 left -= read;
945 buf += read;
946 }
947 return (left == count) ? -EAGAIN : (count - left);
948}
949
950static unsigned int ts_poll(struct file *file, poll_table *wait)
951{
4f1f3107 952 /*
ccad0457
RM		 953 struct dvb_device *dvbdev = file->private_data;
954 struct ddb_output *output = dvbdev->priv;
955 struct ddb_input *input = output->port->input[0];
4f1f3107 956 */
ccad0457
RM		 957 unsigned int mask = 0;
958
959#if 0
960 if (data_avail_to_read)
961 mask |= POLLIN | POLLRDNORM;
962 if (data_avail_to_write)
963 mask |= POLLOUT | POLLWRNORM;
964
965 poll_wait(file, &read_queue, wait);
966 poll_wait(file, &write_queue, wait);
967#endif
968 return mask;
969}
970
4f1f3107 971static const struct file_operations ci_fops = {
ccad0457
RM		 972 .owner = THIS_MODULE,
973 .read = ts_read,
974 .write = ts_write,
975 .open = dvb_generic_open,
976 .release = dvb_generic_release,
977 .poll = ts_poll,
ccad0457
RM		 978};
979
980static struct dvb_device dvbdev_ci = {
ccad0457
RM		 981 .readers = -1,
982 .writers = -1,
983 .users = -1,
984 .fops = &ci_fops,
985};
986
987/****************************************************************************/
988/****************************************************************************/
989/****************************************************************************/
990
991static void input_tasklet(unsigned long data)
992{
993 struct ddb_input *input = (struct ddb_input *) data;
994 struct ddb *dev = input->port->dev;
995
996 spin_lock(&input->lock);
997 if (!input->running) {
998 spin_unlock(&input->lock);
999 return;
1000 }
1001 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
1002
1003 if (input->port->class == DDB_PORT_TUNER) {
1004 if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))
4f1f3107 1005 printk(KERN_ERR "Overflow input %d\n", input->nr);
ccad0457
RM		 1006 while (input->cbuf != ((input->stat >> 11) & 0x1f)
1007 || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) {
1008 dvb_dmx_swfilter_packets(&input->demux,
1009 input->vbuf[input->cbuf],
1010 input->dma_buf_size / 188);
1011
1012 input->cbuf = (input->cbuf + 1) % input->dma_buf_num;
1013 ddbwritel((input->cbuf << 11),
1014 DMA_BUFFER_ACK(input->nr));
1015 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
1016 }
1017 }
1018 if (input->port->class == DDB_PORT_CI)
1019 wake_up(&input->wq);
1020 spin_unlock(&input->lock);
1021}
1022
1023static void output_tasklet(unsigned long data)
1024{
1025 struct ddb_output *output = (struct ddb_output *) data;
1026 struct ddb *dev = output->port->dev;
1027
1028 spin_lock(&output->lock);
1029 if (!output->running) {
1030 spin_unlock(&output->lock);
1031 return;
1032 }
1033 output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8));
1034 wake_up(&output->wq);
1035 spin_unlock(&output->lock);
1036}
1037
1038
b5c00cc5 1039static struct cxd2099_cfg cxd_cfg = {
ccad0457
RM		 1040 .bitrate = 62000,
1041 .adr = 0x40,
1042 .polarity = 1,
1043 .clock_mode = 1,
1044};
1045
1046static int ddb_ci_attach(struct ddb_port *port)
1047{
1048 int ret;
1049
1050 ret = dvb_register_adapter(&port->output->adap,
1051 "DDBridge",
1052 THIS_MODULE,
1053 &port->dev->pdev->dev,
1054 adapter_nr);
1055 if (ret < 0)
1056 return ret;
1057 port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap);
1058 if (!port->en) {
1059 dvb_unregister_adapter(&port->output->adap);
1060 return -ENODEV;
1061 }
1062 ddb_input_start(port->input[0]);
1063 ddb_output_start(port->output);
1064 dvb_ca_en50221_init(&port->output->adap,
1065 port->en, 0, 1);
4f1f3107
OE		 1066 ret = dvb_register_device(&port->output->adap, &port->output->dev,
1067 &dvbdev_ci, (void *) port->output,
df2f94e5 1068 DVB_DEVICE_SEC, 0);
ccad0457
RM		 1069 return ret;
1070}
1071
1072static int ddb_port_attach(struct ddb_port *port)
1073{
1074 int ret = 0;
1075
1076 switch (port->class) {
1077 case DDB_PORT_TUNER:
1078 ret = dvb_input_attach(port->input[0]);
4f1f3107 1079 if (ret < 0)
ccad0457
RM		 1080 break;
1081 ret = dvb_input_attach(port->input[1]);
1082 break;
1083 case DDB_PORT_CI:
1084 ret = ddb_ci_attach(port);
1085 break;
1086 default:
1087 break;
1088 }
1089 if (ret < 0)
4f1f3107 1090 printk(KERN_ERR "port_attach on port %d failed\n", port->nr);
ccad0457
RM		 1091 return ret;
1092}
1093
1094static int ddb_ports_attach(struct ddb *dev)
1095{
1096 int i, ret = 0;
1097 struct ddb_port *port;
1098
1099 for (i = 0; i < dev->info->port_num; i++) {
1100 port = &dev->port[i];
1101 ret = ddb_port_attach(port);
1102 if (ret < 0)
1103 break;
1104 }
1105 return ret;
1106}
1107
1108static void ddb_ports_detach(struct ddb *dev)
1109{
1110 int i;
1111 struct ddb_port *port;
1112
1113 for (i = 0; i < dev->info->port_num; i++) {
1114 port = &dev->port[i];
1115 switch (port->class) {
1116 case DDB_PORT_TUNER:
1117 dvb_input_detach(port->input[0]);
1118 dvb_input_detach(port->input[1]);
1119 break;
1120 case DDB_PORT_CI:
ddc0085e 1121 dvb_unregister_device(port->output->dev);
ccad0457
RM		 1122 if (port->en) {
1123 ddb_input_stop(port->input[0]);
1124 ddb_output_stop(port->output);
1125 dvb_ca_en50221_release(port->en);
1126 kfree(port->en);
b5c00cc5 1127 port->en = NULL;
ccad0457
RM		 1128 dvb_unregister_adapter(&port->output->adap);
1129 }
1130 break;
1131 }
1132 }
1133}
1134
1135/****************************************************************************/
1136/****************************************************************************/
1137
1138static int port_has_ci(struct ddb_port *port)
1139{
1140 u8 val;
4f1f3107 1141 return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1;
ccad0457
RM		 1142}
1143
1144static int port_has_stv0900(struct ddb_port *port)
1145{
1146 u8 val;
1147 if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0)
1148 return 0;
1149 return 1;
1150}
1151
1152static int port_has_stv0900_aa(struct ddb_port *port)
1153{
1154 u8 val;
1155 if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0)
1156 return 0;
1157 return 1;
1158}
1159
1160static int port_has_drxks(struct ddb_port *port)
1161{
1162 u8 val;
1163 if (i2c_read(&port->i2c->adap, 0x29, &val) < 0)
1164 return 0;
1165 if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0)
1166 return 0;
1167 return 1;
1168}
1169
1170static void ddb_port_probe(struct ddb_port *port)
1171{
1172 struct ddb *dev = port->dev;
1173 char *modname = "NO MODULE";
1174
1175 port->class = DDB_PORT_NONE;
1176
1177 if (port_has_ci(port)) {
1178 modname = "CI";
1179 port->class = DDB_PORT_CI;
1180 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
1181 } else if (port_has_stv0900(port)) {
1182 modname = "DUAL DVB-S2";
1183 port->class = DDB_PORT_TUNER;
1184 port->type = DDB_TUNER_DVBS_ST;
1185 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
1186 } else if (port_has_stv0900_aa(port)) {
1187 modname = "DUAL DVB-S2";
1188 port->class = DDB_PORT_TUNER;
1189 port->type = DDB_TUNER_DVBS_ST_AA;
1190 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
1191 } else if (port_has_drxks(port)) {
1192 modname = "DUAL DVB-C/T";
1193 port->class = DDB_PORT_TUNER;
1194 port->type = DDB_TUNER_DVBCT_TR;
1195 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
1196 }
4f1f3107
OE		 1197 printk(KERN_INFO "Port %d (TAB %d): %s\n",
1198 port->nr, port->nr+1, modname);
ccad0457
RM		 1199}
1200
1201static void ddb_input_init(struct ddb_port *port, int nr)
1202{
1203 struct ddb *dev = port->dev;
1204 struct ddb_input *input = &dev->input[nr];
1205
1206 input->nr = nr;
1207 input->port = port;
1208 input->dma_buf_num = INPUT_DMA_BUFS;
1209 input->dma_buf_size = INPUT_DMA_SIZE;
1210 ddbwritel(0, TS_INPUT_CONTROL(nr));
1211 ddbwritel(2, TS_INPUT_CONTROL(nr));
1212 ddbwritel(0, TS_INPUT_CONTROL(nr));
1213 ddbwritel(0, DMA_BUFFER_ACK(nr));
1214 tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input);
1215 spin_lock_init(&input->lock);
1216 init_waitqueue_head(&input->wq);
1217}
1218
1219static void ddb_output_init(struct ddb_port *port, int nr)
1220{
1221 struct ddb *dev = port->dev;
1222 struct ddb_output *output = &dev->output[nr];
1223 output->nr = nr;
1224 output->port = port;
1225 output->dma_buf_num = OUTPUT_DMA_BUFS;
1226 output->dma_buf_size = OUTPUT_DMA_SIZE;
1227
1228 ddbwritel(0, TS_OUTPUT_CONTROL(nr));
1229 ddbwritel(2, TS_OUTPUT_CONTROL(nr));
1230 ddbwritel(0, TS_OUTPUT_CONTROL(nr));
1231 tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output);
1232 init_waitqueue_head(&output->wq);
1233}
1234
1235static void ddb_ports_init(struct ddb *dev)
1236{
1237 int i;
1238 struct ddb_port *port;
1239
1240 for (i = 0; i < dev->info->port_num; i++) {
1241 port = &dev->port[i];
1242 port->dev = dev;
1243 port->nr = i;
1244 port->i2c = &dev->i2c[i];
1245 port->input[0] = &dev->input[2 * i];
1246 port->input[1] = &dev->input[2 * i + 1];
1247 port->output = &dev->output[i];
1248
1249 mutex_init(&port->i2c_gate_lock);
1250 ddb_port_probe(port);
1251 ddb_input_init(port, 2 * i);
1252 ddb_input_init(port, 2 * i + 1);
1253 ddb_output_init(port, i);
1254 }
1255}
1256
1257static void ddb_ports_release(struct ddb *dev)
1258{
1259 int i;
1260 struct ddb_port *port;
1261
1262 for (i = 0; i < dev->info->port_num; i++) {
1263 port = &dev->port[i];
1264 port->dev = dev;
1265 tasklet_kill(&port->input[0]->tasklet);
1266 tasklet_kill(&port->input[1]->tasklet);
1267 tasklet_kill(&port->output->tasklet);
1268 }
1269}
1270
1271/****************************************************************************/
1272/****************************************************************************/
1273/****************************************************************************/
1274
1275static void irq_handle_i2c(struct ddb *dev, int n)
1276{
1277 struct ddb_i2c *i2c = &dev->i2c[n];
1278
1279 i2c->done = 1;
1280 wake_up(&i2c->wq);
1281}
1282
1283static irqreturn_t irq_handler(int irq, void *dev_id)
1284{
1285 struct ddb *dev = (struct ddb *) dev_id;
1286 u32 s = ddbreadl(INTERRUPT_STATUS);
1287
1288 if (!s)
1289 return IRQ_NONE;
1290
1291 do {
1292 ddbwritel(s, INTERRUPT_ACK);
1293
4f1f3107
OE		 1294 if (s & 0x00000001)
1295 irq_handle_i2c(dev, 0);
1296 if (s & 0x00000002)
1297 irq_handle_i2c(dev, 1);
1298 if (s & 0x00000004)
1299 irq_handle_i2c(dev, 2);
1300 if (s & 0x00000008)
1301 irq_handle_i2c(dev, 3);
1302
1303 if (s & 0x00000100)
1304 tasklet_schedule(&dev->input[0].tasklet);
1305 if (s & 0x00000200)
1306 tasklet_schedule(&dev->input[1].tasklet);
1307 if (s & 0x00000400)
1308 tasklet_schedule(&dev->input[2].tasklet);
1309 if (s & 0x00000800)
1310 tasklet_schedule(&dev->input[3].tasklet);
1311 if (s & 0x00001000)
1312 tasklet_schedule(&dev->input[4].tasklet);
1313 if (s & 0x00002000)
1314 tasklet_schedule(&dev->input[5].tasklet);
1315 if (s & 0x00004000)
1316 tasklet_schedule(&dev->input[6].tasklet);
1317 if (s & 0x00008000)
1318 tasklet_schedule(&dev->input[7].tasklet);
1319
1320 if (s & 0x00010000)
1321 tasklet_schedule(&dev->output[0].tasklet);
1322 if (s & 0x00020000)
1323 tasklet_schedule(&dev->output[1].tasklet);
1324 if (s & 0x00040000)
1325 tasklet_schedule(&dev->output[2].tasklet);
1326 if (s & 0x00080000)
1327 tasklet_schedule(&dev->output[3].tasklet);
1328
1329 /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */
ccad0457
RM		 1330 } while ((s = ddbreadl(INTERRUPT_STATUS)));
1331
1332 return IRQ_HANDLED;
1333}
1334
1335/******************************************************************************/
1336/******************************************************************************/
1337/******************************************************************************/
1338
1339static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen)
1340{
1341 u32 data, shift;
1342
1343 if (wlen > 4)
1344 ddbwritel(1, SPI_CONTROL);
1345 while (wlen > 4) {
1346 /* FIXME: check for big-endian */
1347 data = swab32(*(u32 *)wbuf);
1348 wbuf += 4;
1349 wlen -= 4;
1350 ddbwritel(data, SPI_DATA);
4f1f3107
OE		 1351 while (ddbreadl(SPI_CONTROL) & 0x0004)
1352 ;
ccad0457
RM		 1353 }
1354
1355 if (rlen)
1356 ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
1357 else
1358 ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
1359
4f1f3107 1360 data = 0;
ccad0457
RM		 1361 shift = ((4 - wlen) * 8);
1362 while (wlen) {
1363 data <<= 8;
1364 data |= *wbuf;
1365 wlen--;
1366 wbuf++;
1367 }
1368 if (shift)
1369 data <<= shift;
1370 ddbwritel(data, SPI_DATA);
4f1f3107
OE		 1371 while (ddbreadl(SPI_CONTROL) & 0x0004)
1372 ;
ccad0457
RM		 1373
1374 if (!rlen) {
1375 ddbwritel(0, SPI_CONTROL);
1376 return 0;
1377 }
1378 if (rlen > 4)
1379 ddbwritel(1, SPI_CONTROL);
1380
1381 while (rlen > 4) {
1382 ddbwritel(0xffffffff, SPI_DATA);
4f1f3107
OE		 1383 while (ddbreadl(SPI_CONTROL) & 0x0004)
1384 ;
ccad0457
RM		 1385 data = ddbreadl(SPI_DATA);
1386 *(u32 *) rbuf = swab32(data);
1387 rbuf += 4;
1388 rlen -= 4;
1389 }
1390 ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL);
1391 ddbwritel(0xffffffff, SPI_DATA);
4f1f3107
OE		 1392 while (ddbreadl(SPI_CONTROL) & 0x0004)
1393 ;
ccad0457
RM		 1394
1395 data = ddbreadl(SPI_DATA);
1396 ddbwritel(0, SPI_CONTROL);
1397
1398 if (rlen < 4)
1399 data <<= ((4 - rlen) * 8);
1400
1401 while (rlen > 0) {
1402 *rbuf = ((data >> 24) & 0xff);
1403 data <<= 8;
1404 rbuf++;
1405 rlen--;
1406 }
1407 return 0;
1408}
1409
1410#define DDB_MAGIC 'd'
1411
1412struct ddb_flashio {
b5c00cc5 1413 __user __u8 *write_buf;
ccad0457 1414 __u32 write_len;
b5c00cc5 1415 __user __u8 *read_buf;
ccad0457
RM		 1416 __u32 read_len;
1417};
1418
1419#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio)
1420
1421#define DDB_NAME "ddbridge"
1422
1423static u32 ddb_num;
1424static struct ddb *ddbs[32];
1425static struct class *ddb_class;
1426static int ddb_major;
1427
1428static int ddb_open(struct inode *inode, struct file *file)
1429{
1430 struct ddb *dev = ddbs[iminor(inode)];
1431
1432 file->private_data = dev;
1433 return 0;
1434}
1435
1436static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1437{
1438 struct ddb *dev = file->private_data;
b5c00cc5 1439 __user void *parg = (__user void *)arg;
e9013fb6 1440 int res;
ccad0457
RM		 1441
1442 switch (cmd) {
1443 case IOCTL_DDB_FLASHIO:
1444 {
1445 struct ddb_flashio fio;
1446 u8 *rbuf, *wbuf;
1447
1448 if (copy_from_user(&fio, parg, sizeof(fio)))
e9013fb6
DC		 1449 return -EFAULT;
1450
1451 if (fio.write_len > 1028 || fio.read_len > 1028)
1452 return -EINVAL;
1453 if (fio.write_len + fio.read_len > 1028)
1454 return -EINVAL;
1455
ccad0457 1456 wbuf = &dev->iobuf[0];
ccad0457 1457 rbuf = wbuf + fio.write_len;
e9013fb6
DC		 1458
1459 if (copy_from_user(wbuf, fio.write_buf, fio.write_len))
1460 return -EFAULT;
1461 res = flashio(dev, wbuf, fio.write_len, rbuf, fio.read_len);
1462 if (res)
1463 return res;
ccad0457 1464 if (copy_to_user(fio.read_buf, rbuf, fio.read_len))
e9013fb6 1465 return -EFAULT;
ccad0457
RM		 1466 break;
1467 }
1468 default:
e9013fb6 1469 return -ENOTTY;
ccad0457 1470 }
e9013fb6 1471 return 0;
ccad0457
RM		 1472}
1473
4f1f3107 1474static const struct file_operations ddb_fops = {
ccad0457
RM		 1475 .unlocked_ioctl = ddb_ioctl,
1476 .open = ddb_open,
1477};
1478
2c9ede55 1479static char *ddb_devnode(struct device *device, umode_t *mode)
ccad0457
RM		 1480{
1481 struct ddb *dev = dev_get_drvdata(device);
1482
1483 return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr);
1484}
1485
1486static int ddb_class_create(void)
1487{
4f1f3107
OE		 1488 ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops);
1489 if (ddb_major < 0)
ccad0457
RM		 1490 return ddb_major;
1491
1492 ddb_class = class_create(THIS_MODULE, DDB_NAME);
1493 if (IS_ERR(ddb_class)) {
1494 unregister_chrdev(ddb_major, DDB_NAME);
f4e4a67a 1495 return PTR_ERR(ddb_class);
ccad0457
RM		 1496 }
1497 ddb_class->devnode = ddb_devnode;
1498 return 0;
1499}
1500
1501static void ddb_class_destroy(void)
1502{
1503 class_destroy(ddb_class);
1504 unregister_chrdev(ddb_major, DDB_NAME);
1505}
1506
1507static int ddb_device_create(struct ddb *dev)
1508{
1509 dev->nr = ddb_num++;
1510 dev->ddb_dev = device_create(ddb_class, NULL,
1511 MKDEV(ddb_major, dev->nr),
1512 dev, "ddbridge%d", dev->nr);
1513 ddbs[dev->nr] = dev;
1514 if (IS_ERR(dev->ddb_dev))
1515 return -1;
1516 return 0;
1517}
1518
1519static void ddb_device_destroy(struct ddb *dev)
1520{
1521 ddb_num--;
1522 if (IS_ERR(dev->ddb_dev))
1523 return;
1524 device_destroy(ddb_class, MKDEV(ddb_major, 0));
1525}
1526
1527
1528/****************************************************************************/
1529/****************************************************************************/
1530/****************************************************************************/
1531
1532static void ddb_unmap(struct ddb *dev)
1533{
1534 if (dev->regs)
1535 iounmap(dev->regs);
1536 vfree(dev);
1537}
1538
1539
4c62e976 1540static void ddb_remove(struct pci_dev *pdev)
ccad0457 1541{
1fbf86a0 1542 struct ddb *dev = pci_get_drvdata(pdev);
ccad0457
RM		 1543
1544 ddb_ports_detach(dev);
1545 ddb_i2c_release(dev);
1546
1547 ddbwritel(0, INTERRUPT_ENABLE);
1548 free_irq(dev->pdev->irq, dev);
1549#ifdef CONFIG_PCI_MSI
1550 if (dev->msi)
1551 pci_disable_msi(dev->pdev);
1552#endif
1553 ddb_ports_release(dev);
1554 ddb_buffers_free(dev);
1555 ddb_device_destroy(dev);
1556
1557 ddb_unmap(dev);
b5c00cc5 1558 pci_set_drvdata(pdev, NULL);
ccad0457
RM		 1559 pci_disable_device(pdev);
1560}
1561
1562
4c62e976 1563static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
ccad0457
RM		 1564{
1565 struct ddb *dev;
4f1f3107 1566 int stat = 0;
ccad0457
RM		 1567 int irq_flag = IRQF_SHARED;
1568
4f1f3107 1569 if (pci_enable_device(pdev) < 0)
ccad0457
RM		 1570 return -ENODEV;
1571
1572 dev = vmalloc(sizeof(struct ddb));
1573 if (dev == NULL)
1574 return -ENOMEM;
1575 memset(dev, 0, sizeof(struct ddb));
1576
1577 dev->pdev = pdev;
1578 pci_set_drvdata(pdev, dev);
1579 dev->info = (struct ddb_info *) id->driver_data;
4f1f3107 1580 printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name);
ccad0457 1581
4f1f3107
OE		 1582 dev->regs = ioremap(pci_resource_start(dev->pdev, 0),
1583 pci_resource_len(dev->pdev, 0));
ccad0457
RM		 1584 if (!dev->regs) {
1585 stat = -ENOMEM;
1586 goto fail;
1587 }
4f1f3107 1588 printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4));
ccad0457
RM		 1589
1590#ifdef CONFIG_PCI_MSI
1591 if (pci_msi_enabled())
1592 stat = pci_enable_msi(dev->pdev);
1593 if (stat) {
1594 printk(KERN_INFO ": MSI not available.\n");
1595 } else {
1596 irq_flag = 0;
1597 dev->msi = 1;
1598 }
1599#endif
4f1f3107
OE		 1600 stat = request_irq(dev->pdev->irq, irq_handler,
1601 irq_flag, "DDBridge", (void *) dev);
1602 if (stat < 0)
ccad0457
RM		 1603 goto fail1;
1604 ddbwritel(0, DMA_BASE_WRITE);
1605 ddbwritel(0, DMA_BASE_READ);
1606 ddbwritel(0xffffffff, INTERRUPT_ACK);
1607 ddbwritel(0xfff0f, INTERRUPT_ENABLE);
1608 ddbwritel(0, MSI1_ENABLE);
1609
1610 if (ddb_i2c_init(dev) < 0)
1611 goto fail1;
1612 ddb_ports_init(dev);
1613 if (ddb_buffers_alloc(dev) < 0) {
1614 printk(KERN_INFO ": Could not allocate buffer memory\n");
1615 goto fail2;
1616 }
1617 if (ddb_ports_attach(dev) < 0)
1618 goto fail3;
1619 ddb_device_create(dev);
1620 return 0;
1621
1622fail3:
1623 ddb_ports_detach(dev);
4f1f3107 1624 printk(KERN_ERR "fail3\n");
ccad0457
RM		 1625 ddb_ports_release(dev);
1626fail2:
4f1f3107 1627 printk(KERN_ERR "fail2\n");
ccad0457
RM		 1628 ddb_buffers_free(dev);
1629fail1:
4f1f3107 1630 printk(KERN_ERR "fail1\n");
ccad0457
RM		 1631 if (dev->msi)
1632 pci_disable_msi(dev->pdev);
25e057fd
TY		 1633 if (stat == 0)
1634 free_irq(dev->pdev->irq, dev);
ccad0457 1635fail:
4f1f3107 1636 printk(KERN_ERR "fail\n");
ccad0457 1637 ddb_unmap(dev);
b5c00cc5 1638 pci_set_drvdata(pdev, NULL);
ccad0457
RM		 1639 pci_disable_device(pdev);
1640 return -1;
1641}
1642
1643/******************************************************************************/
1644/******************************************************************************/
1645/******************************************************************************/
1646
1647static struct ddb_info ddb_none = {
1648 .type = DDB_NONE,
1649 .name = "Digital Devices PCIe bridge",
1650};
1651
1652static struct ddb_info ddb_octopus = {
1653 .type = DDB_OCTOPUS,
1654 .name = "Digital Devices Octopus DVB adapter",
1655 .port_num = 4,
1656};
1657
1658static struct ddb_info ddb_octopus_le = {
1659 .type = DDB_OCTOPUS,
1660 .name = "Digital Devices Octopus LE DVB adapter",
1661 .port_num = 2,
1662};
1663
93961435
CR		 1664static struct ddb_info ddb_octopus_mini = {
1665 .type = DDB_OCTOPUS,
1666 .name = "Digital Devices Octopus Mini",
1667 .port_num = 4,
1668};
1669
ccad0457
RM		 1670static struct ddb_info ddb_v6 = {
1671 .type = DDB_OCTOPUS,
1672 .name = "Digital Devices Cine S2 V6 DVB adapter",
1673 .port_num = 3,
1674};
93961435
CR		 1675static struct ddb_info ddb_v6_5 = {
1676 .type = DDB_OCTOPUS,
1677 .name = "Digital Devices Cine S2 V6.5 DVB adapter",
1678 .port_num = 4,
1679};
1680
1681static struct ddb_info ddb_dvbct = {
1682 .type = DDB_OCTOPUS,
1683 .name = "Digital Devices DVBCT V6.1 DVB adapter",
1684 .port_num = 3,
1685};
1686
1687static struct ddb_info ddb_satixS2v3 = {
1688 .type = DDB_OCTOPUS,
1689 .name = "Mystique SaTiX-S2 V3 DVB adapter",
1690 .port_num = 3,
1691};
1692
1693static struct ddb_info ddb_octopusv3 = {
1694 .type = DDB_OCTOPUS,
1695 .name = "Digital Devices Octopus V3 DVB adapter",
1696 .port_num = 4,
1697};
ccad0457
RM		 1698
1699#define DDVID 0xdd01 /* Digital Devices Vendor ID */
1700
4f1f3107 1701#define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \
ccad0457
RM		 1702 .vendor = _vend, .device = _dev, \
1703 .subvendor = _subvend, .subdevice = _subdev, \
1704 .driver_data = (unsigned long)&_driverdata }
1705
4c62e976 1706static const struct pci_device_id ddb_id_tbl[] = {
ccad0457
RM		 1707 DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus),
1708 DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus),
1709 DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le),
93961435 1710 DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini),
ccad0457 1711 DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6),
93961435
CR		 1712 DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5),
1713 DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct),
1714 DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3),
1715 DDB_ID(DDVID, 0x0005, DDVID, 0x0004, ddb_octopusv3),
ccad0457
RM		 1716 /* in case sub-ids got deleted in flash */
1717 DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
1718 {0}
1719};
1720MODULE_DEVICE_TABLE(pci, ddb_id_tbl);
1721
1722
1723static struct pci_driver ddb_pci_driver = {
1724 .name = "DDBridge",
1725 .id_table = ddb_id_tbl,
1726 .probe = ddb_probe,
4c62e976 1727 .remove = ddb_remove,
ccad0457
RM		 1728};
1729
1730static __init int module_init_ddbridge(void)
1731{
f4e4a67a
AK		 1732 int ret;
1733
4f1f3107 1734 printk(KERN_INFO "Digital Devices PCIE bridge driver, "
ccad0457 1735 "Copyright (C) 2010-11 Digital Devices GmbH\n");
f4e4a67a
AK		 1736
1737 ret = ddb_class_create();
1738 if (ret < 0)
1739 return ret;
1740 ret = pci_register_driver(&ddb_pci_driver);
1741 if (ret < 0)
1742 ddb_class_destroy();
1743 return ret;
ccad0457
RM		 1744}
1745
1746static __exit void module_exit_ddbridge(void)
1747{
1748 pci_unregister_driver(&ddb_pci_driver);
1749 ddb_class_destroy();
1750}
1751
1752module_init(module_init_ddbridge);
1753module_exit(module_exit_ddbridge);
1754
1755MODULE_DESCRIPTION("Digital Devices PCIe Bridge");
1756MODULE_AUTHOR("Ralph Metzler");
1757MODULE_LICENSE("GPL");
1758MODULE_VERSION("0.5");
Linux 6.x block layer and io_uring tree(s)