[linux-2.6-block.git] / drivers / media / dvb-frontends / zl10353.c

/*
 * Driver for Zarlink DVB-T ZL10353 demodulator
 *
 * Copyright (C) 2006, 2007 Christopher Pascoe <c.pascoe@itee.uq.edu.au>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/div64.h>

#include "dvb_frontend.h"
#include "zl10353_priv.h"
#include "zl10353.h"

struct zl10353_state {
	struct i2c_adapter *i2c;
	struct dvb_frontend frontend;

	struct zl10353_config config;

	u32 bandwidth;
	u32 ucblocks;
	u32 frequency;
};

static int debug;
#define dprintk(args...) \
	do { \
		if (debug) printk(KERN_DEBUG "zl10353: " args); \
	} while (0)

static int debug_regs;

static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u8 buf[2] = { reg, val };
	struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
			       .buf = buf, .len = 2 };
	int err = i2c_transfer(state->i2c, &msg, 1);
	if (err != 1) {
		printk("zl10353: write to reg %x failed (err = %d)!\n", reg, err);
		return err;
	}
	return 0;
}

static int zl10353_write(struct dvb_frontend *fe, const u8 ibuf[], int ilen)
{
	int err, i;
	for (i = 0; i < ilen - 1; i++)
		if ((err = zl10353_single_write(fe, ibuf[0] + i, ibuf[i + 1])))
			return err;

	return 0;
}

static int zl10353_read_register(struct zl10353_state *state, u8 reg)
{
	int ret;
	u8 b0[1] = { reg };
	u8 b1[1] = { 0 };
	struct i2c_msg msg[2] = { { .addr = state->config.demod_address,
				    .flags = 0,
				    .buf = b0, .len = 1 },
				  { .addr = state->config.demod_address,
				    .flags = I2C_M_RD,
				    .buf = b1, .len = 1 } };

	ret = i2c_transfer(state->i2c, msg, 2);

	if (ret != 2) {
		printk("%s: readreg error (reg=%d, ret==%i)\n",
		       __func__, reg, ret);
		return ret;
	}

	return b1[0];
}

static void zl10353_dump_regs(struct dvb_frontend *fe)
{
	struct zl10353_state *state = fe->demodulator_priv;
	int ret;
	u8 reg;

	/* Dump all registers. */
	for (reg = 0; ; reg++) {
		if (reg % 16 == 0) {
			if (reg)
				printk(KERN_CONT "\n");
			printk(KERN_DEBUG "%02x:", reg);
		}
		ret = zl10353_read_register(state, reg);
		if (ret >= 0)
			printk(KERN_CONT " %02x", (u8)ret);
		else
			printk(KERN_CONT " --");
		if (reg == 0xff)
			break;
	}
	printk(KERN_CONT "\n");
}

static void zl10353_calc_nominal_rate(struct dvb_frontend *fe,
				      u32 bandwidth,
				      u16 *nominal_rate)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u32 adc_clock = 450560; /* 45.056 MHz */
	u64 value;
	u8 bw = bandwidth / 1000000;

	if (state->config.adc_clock)
		adc_clock = state->config.adc_clock;

	value = (u64)10 * (1 << 23) / 7 * 125;
	value = (bw * value) + adc_clock / 2;
	do_div(value, adc_clock);
	*nominal_rate = value;

	dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
		__func__, bw, adc_clock, *nominal_rate);
}

static void zl10353_calc_input_freq(struct dvb_frontend *fe,
				    u16 *input_freq)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u32 adc_clock = 450560;	/* 45.056  MHz */
	int if2 = 361667;	/* 36.1667 MHz */
	int ife;
	u64 value;

	if (state->config.adc_clock)
		adc_clock = state->config.adc_clock;
	if (state->config.if2)
		if2 = state->config.if2;

	if (adc_clock >= if2 * 2)
		ife = if2;
	else {
		ife = adc_clock - (if2 % adc_clock);
		if (ife > adc_clock / 2)
			ife = adc_clock - ife;
	}
	value = (u64)65536 * ife + adc_clock / 2;
	do_div(value, adc_clock);
	*input_freq = -value;

	dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
		__func__, if2, ife, adc_clock, -(int)value, *input_freq);
}

static int zl10353_sleep(struct dvb_frontend *fe)
{
	static u8 zl10353_softdown[] = { 0x50, 0x0C, 0x44 };

	zl10353_write(fe, zl10353_softdown, sizeof(zl10353_softdown));
	return 0;
}

static int zl10353_set_parameters(struct dvb_frontend *fe)
{
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	struct zl10353_state *state = fe->demodulator_priv;
	u16 nominal_rate, input_freq;
	u8 pllbuf[6] = { 0x67 }, acq_ctl = 0;
	u16 tps = 0;

	state->frequency = c->frequency;

	zl10353_single_write(fe, RESET, 0x80);
	udelay(200);
	zl10353_single_write(fe, 0xEA, 0x01);
	udelay(200);
	zl10353_single_write(fe, 0xEA, 0x00);

	zl10353_single_write(fe, AGC_TARGET, 0x28);

	if (c->transmission_mode != TRANSMISSION_MODE_AUTO)
		acq_ctl |= (1 << 0);
	if (c->guard_interval != GUARD_INTERVAL_AUTO)
		acq_ctl |= (1 << 1);
	zl10353_single_write(fe, ACQ_CTL, acq_ctl);

	switch (c->bandwidth_hz) {
	case 6000000:
		/* These are extrapolated from the 7 and 8MHz values */
		zl10353_single_write(fe, MCLK_RATIO, 0x97);
		zl10353_single_write(fe, 0x64, 0x34);
		zl10353_single_write(fe, 0xcc, 0xdd);
		break;
	case 7000000:
		zl10353_single_write(fe, MCLK_RATIO, 0x86);
		zl10353_single_write(fe, 0x64, 0x35);
		zl10353_single_write(fe, 0xcc, 0x73);
		break;
	default:
		c->bandwidth_hz = 8000000;
		/* fall though */
	case 8000000:
		zl10353_single_write(fe, MCLK_RATIO, 0x75);
		zl10353_single_write(fe, 0x64, 0x36);
		zl10353_single_write(fe, 0xcc, 0x73);
	}

	zl10353_calc_nominal_rate(fe, c->bandwidth_hz, &nominal_rate);
	zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate));
	zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate));
	state->bandwidth = c->bandwidth_hz;

	zl10353_calc_input_freq(fe, &input_freq);
	zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq));
	zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq));

	/* Hint at TPS settings */
	switch (c->code_rate_HP) {
	case FEC_2_3:
		tps |= (1 << 7);
		break;
	case FEC_3_4:
		tps |= (2 << 7);
		break;
	case FEC_5_6:
		tps |= (3 << 7);
		break;
	case FEC_7_8:
		tps |= (4 << 7);
		break;
	case FEC_1_2:
	case FEC_AUTO:
		break;
	default:
		return -EINVAL;
	}

	switch (c->code_rate_LP) {
	case FEC_2_3:
		tps |= (1 << 4);
		break;
	case FEC_3_4:
		tps |= (2 << 4);
		break;
	case FEC_5_6:
		tps |= (3 << 4);
		break;
	case FEC_7_8:
		tps |= (4 << 4);
		break;
	case FEC_1_2:
	case FEC_AUTO:
		break;
	case FEC_NONE:
		if (c->hierarchy == HIERARCHY_AUTO ||
		    c->hierarchy == HIERARCHY_NONE)
			break;
	default:
		return -EINVAL;
	}

	switch (c->modulation) {
	case QPSK:
		break;
	case QAM_AUTO:
	case QAM_16:
		tps |= (1 << 13);
		break;
	case QAM_64:
		tps |= (2 << 13);
		break;
	default:
		return -EINVAL;
	}

	switch (c->transmission_mode) {
	case TRANSMISSION_MODE_2K:
	case TRANSMISSION_MODE_AUTO:
		break;
	case TRANSMISSION_MODE_8K:
		tps |= (1 << 0);
		break;
	default:
		return -EINVAL;
	}

	switch (c->guard_interval) {
	case GUARD_INTERVAL_1_32:
	case GUARD_INTERVAL_AUTO:
		break;
	case GUARD_INTERVAL_1_16:
		tps |= (1 << 2);
		break;
	case GUARD_INTERVAL_1_8:
		tps |= (2 << 2);
		break;
	case GUARD_INTERVAL_1_4:
		tps |= (3 << 2);
		break;
	default:
		return -EINVAL;
	}

	switch (c->hierarchy) {
	case HIERARCHY_AUTO:
	case HIERARCHY_NONE:
		break;
	case HIERARCHY_1:
		tps |= (1 << 10);
		break;
	case HIERARCHY_2:
		tps |= (2 << 10);
		break;
	case HIERARCHY_4:
		tps |= (3 << 10);
		break;
	default:
		return -EINVAL;
	}

	zl10353_single_write(fe, TPS_GIVEN_1, msb(tps));
	zl10353_single_write(fe, TPS_GIVEN_0, lsb(tps));

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 0);

	/*
	 * If there is no tuner attached to the secondary I2C bus, we call
	 * set_params to program a potential tuner attached somewhere else.
	 * Otherwise, we update the PLL registers via calc_regs.
	 */
	if (state->config.no_tuner) {
		if (fe->ops.tuner_ops.set_params) {
			fe->ops.tuner_ops.set_params(fe);
			if (fe->ops.i2c_gate_ctrl)
				fe->ops.i2c_gate_ctrl(fe, 0);
		}
	} else if (fe->ops.tuner_ops.calc_regs) {
		fe->ops.tuner_ops.calc_regs(fe, pllbuf + 1, 5);
		pllbuf[1] <<= 1;
		zl10353_write(fe, pllbuf, sizeof(pllbuf));
	}

	zl10353_single_write(fe, 0x5F, 0x13);

	/* If no attached tuner or invalid PLL registers, just start the FSM. */
	if (state->config.no_tuner || fe->ops.tuner_ops.calc_regs == NULL)
		zl10353_single_write(fe, FSM_GO, 0x01);
	else
		zl10353_single_write(fe, TUNER_GO, 0x01);

	return 0;
}

static int zl10353_get_parameters(struct dvb_frontend *fe)
{
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	struct zl10353_state *state = fe->demodulator_priv;
	int s6, s9;
	u16 tps;
	static const u8 tps_fec_to_api[8] = {
		FEC_1_2,
		FEC_2_3,
		FEC_3_4,
		FEC_5_6,
		FEC_7_8,
		FEC_AUTO,
		FEC_AUTO,
		FEC_AUTO
	};

	s6 = zl10353_read_register(state, STATUS_6);
	s9 = zl10353_read_register(state, STATUS_9);
	if (s6 < 0 || s9 < 0)
		return -EREMOTEIO;
	if ((s6 & (1 << 5)) == 0 || (s9 & (1 << 4)) == 0)
		return -EINVAL;	/* no FE or TPS lock */

	tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 |
	      zl10353_read_register(state, TPS_RECEIVED_0);

	c->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
	c->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];

	switch ((tps >> 13) & 3) {
	case 0:
		c->modulation = QPSK;
		break;
	case 1:
		c->modulation = QAM_16;
		break;
	case 2:
		c->modulation = QAM_64;
		break;
	default:
		c->modulation = QAM_AUTO;
		break;
	}

	c->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K :
					       TRANSMISSION_MODE_2K;

	switch ((tps >> 2) & 3) {
	case 0:
		c->guard_interval = GUARD_INTERVAL_1_32;
		break;
	case 1:
		c->guard_interval = GUARD_INTERVAL_1_16;
		break;
	case 2:
		c->guard_interval = GUARD_INTERVAL_1_8;
		break;
	case 3:
		c->guard_interval = GUARD_INTERVAL_1_4;
		break;
	default:
		c->guard_interval = GUARD_INTERVAL_AUTO;
		break;
	}

	switch ((tps >> 10) & 7) {
	case 0:
		c->hierarchy = HIERARCHY_NONE;
		break;
	case 1:
		c->hierarchy = HIERARCHY_1;
		break;
	case 2:
		c->hierarchy = HIERARCHY_2;
		break;
	case 3:
		c->hierarchy = HIERARCHY_4;
		break;
	default:
		c->hierarchy = HIERARCHY_AUTO;
		break;
	}

	c->frequency = state->frequency;
	c->bandwidth_hz = state->bandwidth;
	c->inversion = INVERSION_AUTO;

	return 0;
}

static int zl10353_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
	struct zl10353_state *state = fe->demodulator_priv;
	int s6, s7, s8;

	if ((s6 = zl10353_read_register(state, STATUS_6)) < 0)
		return -EREMOTEIO;
	if ((s7 = zl10353_read_register(state, STATUS_7)) < 0)
		return -EREMOTEIO;
	if ((s8 = zl10353_read_register(state, STATUS_8)) < 0)
		return -EREMOTEIO;

	*status = 0;
	if (s6 & (1 << 2))
		*status |= FE_HAS_CARRIER;
	if (s6 & (1 << 1))
		*status |= FE_HAS_VITERBI;
	if (s6 & (1 << 5))
		*status |= FE_HAS_LOCK;
	if (s7 & (1 << 4))
		*status |= FE_HAS_SYNC;
	if (s8 & (1 << 6))
		*status |= FE_HAS_SIGNAL;

	if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
	    (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
		*status &= ~FE_HAS_LOCK;

	return 0;
}

static int zl10353_read_ber(struct dvb_frontend *fe, u32 *ber)
{
	struct zl10353_state *state = fe->demodulator_priv;

	*ber = zl10353_read_register(state, RS_ERR_CNT_2) << 16 |
	       zl10353_read_register(state, RS_ERR_CNT_1) << 8 |
	       zl10353_read_register(state, RS_ERR_CNT_0);

	return 0;
}

static int zl10353_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
	struct zl10353_state *state = fe->demodulator_priv;

	u16 signal = zl10353_read_register(state, AGC_GAIN_1) << 10 |
		     zl10353_read_register(state, AGC_GAIN_0) << 2 | 3;

	*strength = ~signal;

	return 0;
}

static int zl10353_read_snr(struct dvb_frontend *fe, u16 *snr)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u8 _snr;

	if (debug_regs)
		zl10353_dump_regs(fe);

	_snr = zl10353_read_register(state, SNR);
	*snr = 10 * _snr / 8;

	return 0;
}

static int zl10353_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u32 ubl = 0;

	ubl = zl10353_read_register(state, RS_UBC_1) << 8 |
	      zl10353_read_register(state, RS_UBC_0);

	state->ucblocks += ubl;
	*ucblocks = state->ucblocks;

	return 0;
}

static int zl10353_get_tune_settings(struct dvb_frontend *fe,
				     struct dvb_frontend_tune_settings
					 *fe_tune_settings)
{
	fe_tune_settings->min_delay_ms = 1000;
	fe_tune_settings->step_size = 0;
	fe_tune_settings->max_drift = 0;

	return 0;
}

static int zl10353_init(struct dvb_frontend *fe)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u8 zl10353_reset_attach[6] = { 0x50, 0x03, 0x64, 0x46, 0x15, 0x0F };

	if (debug_regs)
		zl10353_dump_regs(fe);
	if (state->config.parallel_ts)
		zl10353_reset_attach[2] &= ~0x20;
	if (state->config.clock_ctl_1)
		zl10353_reset_attach[3] = state->config.clock_ctl_1;
	if (state->config.pll_0)
		zl10353_reset_attach[4] = state->config.pll_0;

	/* Do a "hard" reset if not already done */
	if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] ||
	    zl10353_read_register(state, 0x51) != zl10353_reset_attach[2]) {
		zl10353_write(fe, zl10353_reset_attach,
				   sizeof(zl10353_reset_attach));
		if (debug_regs)
			zl10353_dump_regs(fe);
	}

	return 0;
}

static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u8 val = 0x0a;

	if (state->config.disable_i2c_gate_ctrl) {
		/* No tuner attached to the internal I2C bus */
		/* If set enable I2C bridge, the main I2C bus stopped hardly */
		return 0;
	}

	if (enable)
		val |= 0x10;

	return zl10353_single_write(fe, 0x62, val);
}

static void zl10353_release(struct dvb_frontend *fe)
{
	struct zl10353_state *state = fe->demodulator_priv;
	kfree(state);
}

static struct dvb_frontend_ops zl10353_ops;

struct dvb_frontend *zl10353_attach(const struct zl10353_config *config,
				    struct i2c_adapter *i2c)
{
	struct zl10353_state *state = NULL;
	int id;

	/* allocate memory for the internal state */
	state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL);
	if (state == NULL)
		goto error;

	/* setup the state */
	state->i2c = i2c;
	memcpy(&state->config, config, sizeof(struct zl10353_config));

	/* check if the demod is there */
	id = zl10353_read_register(state, CHIP_ID);
	if ((id != ID_ZL10353) && (id != ID_CE6230) && (id != ID_CE6231))
		goto error;

	/* create dvb_frontend */
	memcpy(&state->frontend.ops, &zl10353_ops, sizeof(struct dvb_frontend_ops));
	state->frontend.demodulator_priv = state;

	return &state->frontend;
error:
	kfree(state);
	return NULL;
}

static struct dvb_frontend_ops zl10353_ops = {
	.delsys = { SYS_DVBT },
	.info = {
		.name			= "Zarlink ZL10353 DVB-T",
		.frequency_min		= 174000000,
		.frequency_max		= 862000000,
		.frequency_stepsize	= 166667,
		.frequency_tolerance	= 0,
		.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
			FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
			FE_CAN_FEC_AUTO |
			FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
			FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
			FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
			FE_CAN_MUTE_TS
	},

	.release = zl10353_release,

	.init = zl10353_init,
	.sleep = zl10353_sleep,
	.i2c_gate_ctrl = zl10353_i2c_gate_ctrl,
	.write = zl10353_write,

	.set_frontend = zl10353_set_parameters,
	.get_frontend = zl10353_get_parameters,
	.get_tune_settings = zl10353_get_tune_settings,

	.read_status = zl10353_read_status,
	.read_ber = zl10353_read_ber,
	.read_signal_strength = zl10353_read_signal_strength,
	.read_snr = zl10353_read_snr,
	.read_ucblocks = zl10353_read_ucblocks,
};

module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");

module_param(debug_regs, int, 0644);
MODULE_PARM_DESC(debug_regs, "Turn on/off frontend register dumps (default:off).");

MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver");
MODULE_AUTHOR("Chris Pascoe");
MODULE_LICENSE("GPL");

EXPORT_SYMBOL(zl10353_attach);
Commit	Line	Data
780dfef3 CP	1	/*
	2	* Driver for Zarlink DVB-T ZL10353 demodulator
	3	*
794604c3	4	* Copyright (C) 2006, 2007 Christopher Pascoe <c.pascoe@itee.uq.edu.au>
780dfef3 CP	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	*
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
794604c3	19	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
780dfef3 CP	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
780dfef3 CP	24	#include <linux/init.h>
	25	#include <linux/delay.h>
	26	#include <linux/string.h>
	27	#include <linux/slab.h>
794604c3	28	#include <asm/div64.h>
780dfef3 CP	29
	30	#include "dvb_frontend.h"
	31	#include "zl10353_priv.h"
	32	#include "zl10353.h"
	33
	34	struct zl10353_state {
	35	struct i2c_adapter *i2c;
	36	struct dvb_frontend frontend;
780dfef3 CP	37
780dfef3 CP	38	struct zl10353_config config;
bc514710	39
4e4d2bcf MCC	40	u32 bandwidth;
	41	u32 ucblocks;
	42	u32 frequency;
780dfef3 CP	43	};
780dfef3 CP	44
f7f57770 AP	45	static int debug;
	46	#define dprintk(args...) \
	47	do { \
	48	if (debug) printk(KERN_DEBUG "zl10353: " args); \
	49	} while (0)
	50
ff699e6b	51	static int debug_regs;
780dfef3 CP	52
	53	static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
	54	{
	55	struct zl10353_state *state = fe->demodulator_priv;
	56	u8 buf[2] = { reg, val };
	57	struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
	58	.buf = buf, .len = 2 };
	59	int err = i2c_transfer(state->i2c, &msg, 1);
	60	if (err != 1) {
	61	printk("zl10353: write to reg %x failed (err = %d)!\n", reg, err);
	62	return err;
	63	}
	64	return 0;
	65	}
	66
2e4e98e7	67	static int zl10353_write(struct dvb_frontend *fe, const u8 ibuf[], int ilen)
780dfef3 CP	68	{
	69	int err, i;
	70	for (i = 0; i < ilen - 1; i++)
	71	if ((err = zl10353_single_write(fe, ibuf[0] + i, ibuf[i + 1])))
	72	return err;
	73
	74	return 0;
	75	}
	76
	77	static int zl10353_read_register(struct zl10353_state *state, u8 reg)
	78	{
	79	int ret;
	80	u8 b0[1] = { reg };
	81	u8 b1[1] = { 0 };
	82	struct i2c_msg msg[2] = { { .addr = state->config.demod_address,
	83	.flags = 0,
	84	.buf = b0, .len = 1 },
	85	{ .addr = state->config.demod_address,
	86	.flags = I2C_M_RD,
	87	.buf = b1, .len = 1 } };
	88
	89	ret = i2c_transfer(state->i2c, msg, 2);
	90
	91	if (ret != 2) {
	92	printk("%s: readreg error (reg=%d, ret==%i)\n",
271ddbf7	93	__func__, reg, ret);
780dfef3 CP	94	return ret;
	95	}
	96
	97	return b1[0];
	98	}
	99
c04e89b1	100	static void zl10353_dump_regs(struct dvb_frontend *fe)
780dfef3 CP	101	{
780dfef3 CP	102	struct zl10353_state *state = fe->demodulator_priv;
780dfef3 CP	103	int ret;
	104	u8 reg;
	105
	106	/* Dump all registers. */
	107	for (reg = 0; ; reg++) {
	108	if (reg % 16 == 0) {
	109	if (reg)
458f9aa3 JN	110	printk(KERN_CONT "\n");
458f9aa3 JN	111	printk(KERN_DEBUG "%02x:", reg);
780dfef3 CP	112	}
	113	ret = zl10353_read_register(state, reg);
	114	if (ret >= 0)
458f9aa3	115	printk(KERN_CONT " %02x", (u8)ret);
780dfef3	116	else
458f9aa3	117	printk(KERN_CONT " --");
780dfef3 CP	118	if (reg == 0xff)
	119	break;
	120	}
458f9aa3	121	printk(KERN_CONT "\n");
780dfef3 CP	122	}
780dfef3 CP	123
f7f57770	124	static void zl10353_calc_nominal_rate(struct dvb_frontend *fe,
4e4d2bcf	125	u32 bandwidth,
f7f57770 AP	126	u16 *nominal_rate)
f7f57770 AP	127	{
f7f57770	128	struct zl10353_state *state = fe->demodulator_priv;
a1dcd9de CP	129	u32 adc_clock = 450560; /* 45.056 MHz */
a1dcd9de CP	130	u64 value;
4e4d2bcf	131	u8 bw = bandwidth / 1000000;
f7f57770 AP	132
	133	if (state->config.adc_clock)
	134	adc_clock = state->config.adc_clock;
	135
18ff605a AM	136	value = (u64)10 * (1 << 23) / 7 * 125;
18ff605a AM	137	value = (bw * value) + adc_clock / 2;
a1dcd9de CP	138	do_div(value, adc_clock);
a1dcd9de CP	139	*nominal_rate = value;
f7f57770 AP	140
f7f57770 AP	141	dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
271ddbf7	142	__func__, bw, adc_clock, *nominal_rate);
f7f57770 AP	143	}
f7f57770 AP	144
794604c3 CP	145	static void zl10353_calc_input_freq(struct dvb_frontend *fe,
	146	u16 *input_freq)
	147	{
	148	struct zl10353_state *state = fe->demodulator_priv;
a1dcd9de CP	149	u32 adc_clock = 450560; /* 45.056 MHz */
a1dcd9de CP	150	int if2 = 361667; /* 36.1667 MHz */
794604c3 CP	151	int ife;
	152	u64 value;
	153
	154	if (state->config.adc_clock)
	155	adc_clock = state->config.adc_clock;
	156	if (state->config.if2)
	157	if2 = state->config.if2;
	158
	159	if (adc_clock >= if2 * 2)
	160	ife = if2;
	161	else {
	162	ife = adc_clock - (if2 % adc_clock);
	163	if (ife > adc_clock / 2)
	164	ife = adc_clock - ife;
	165	}
a1dcd9de	166	value = (u64)65536 * ife + adc_clock / 2;
794604c3 CP	167	do_div(value, adc_clock);
	168	*input_freq = -value;
	169
	170	dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
271ddbf7	171	__func__, if2, ife, adc_clock, -(int)value, *input_freq);
794604c3 CP	172	}
794604c3 CP	173
780dfef3 CP	174	static int zl10353_sleep(struct dvb_frontend *fe)
	175	{
	176	static u8 zl10353_softdown[] = { 0x50, 0x0C, 0x44 };
	177
	178	zl10353_write(fe, zl10353_softdown, sizeof(zl10353_softdown));
	179	return 0;
	180	}
	181
4e4d2bcf	182	static int zl10353_set_parameters(struct dvb_frontend *fe)
780dfef3	183	{
4e4d2bcf	184	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
8dec0732	185	struct zl10353_state *state = fe->demodulator_priv;
794604c3	186	u16 nominal_rate, input_freq;
bc514710 CP	187	u8 pllbuf[6] = { 0x67 }, acq_ctl = 0;
bc514710 CP	188	u16 tps = 0;
780dfef3	189
4e4d2bcf	190	state->frequency = c->frequency;
decee2e8	191
bc514710	192	zl10353_single_write(fe, RESET, 0x80);
780dfef3 CP	193	udelay(200);
	194	zl10353_single_write(fe, 0xEA, 0x01);
	195	udelay(200);
	196	zl10353_single_write(fe, 0xEA, 0x00);
	197
bc514710 CP	198	zl10353_single_write(fe, AGC_TARGET, 0x28);
bc514710 CP	199
4e4d2bcf	200	if (c->transmission_mode != TRANSMISSION_MODE_AUTO)
bc514710	201	acq_ctl \|= (1 << 0);
4e4d2bcf	202	if (c->guard_interval != GUARD_INTERVAL_AUTO)
bc514710 CP	203	acq_ctl \|= (1 << 1);
bc514710 CP	204	zl10353_single_write(fe, ACQ_CTL, acq_ctl);
f7f57770	205
4e4d2bcf MCC	206	switch (c->bandwidth_hz) {
4e4d2bcf MCC	207	case 6000000:
bc514710 CP	208	/* These are extrapolated from the 7 and 8MHz values */
	209	zl10353_single_write(fe, MCLK_RATIO, 0x97);
	210	zl10353_single_write(fe, 0x64, 0x34);
a9dbe5dc	211	zl10353_single_write(fe, 0xcc, 0xdd);
bc514710	212	break;
4e4d2bcf	213	case 7000000:
bc514710 CP	214	zl10353_single_write(fe, MCLK_RATIO, 0x86);
bc514710 CP	215	zl10353_single_write(fe, 0x64, 0x35);
a9dbe5dc	216	zl10353_single_write(fe, 0xcc, 0x73);
bc514710	217	break;
bc514710	218	default:
4e4d2bcf MCC	219	c->bandwidth_hz = 8000000;
	220	/* fall though */
	221	case 8000000:
bc514710 CP	222	zl10353_single_write(fe, MCLK_RATIO, 0x75);
bc514710 CP	223	zl10353_single_write(fe, 0x64, 0x36);
a9dbe5dc	224	zl10353_single_write(fe, 0xcc, 0x73);
bc514710 CP	225	}
bc514710 CP	226
4e4d2bcf	227	zl10353_calc_nominal_rate(fe, c->bandwidth_hz, &nominal_rate);
f7f57770 AP	228	zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate));
f7f57770 AP	229	zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate));
4e4d2bcf	230	state->bandwidth = c->bandwidth_hz;
f7f57770	231
794604c3 CP	232	zl10353_calc_input_freq(fe, &input_freq);
	233	zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq));
	234	zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq));
	235
bc514710	236	/* Hint at TPS settings */
4e4d2bcf	237	switch (c->code_rate_HP) {
bc514710 CP	238	case FEC_2_3:
	239	tps \|= (1 << 7);
	240	break;
	241	case FEC_3_4:
	242	tps \|= (2 << 7);
	243	break;
	244	case FEC_5_6:
	245	tps \|= (3 << 7);
	246	break;
	247	case FEC_7_8:
	248	tps \|= (4 << 7);
	249	break;
	250	case FEC_1_2:
	251	case FEC_AUTO:
	252	break;
	253	default:
	254	return -EINVAL;
	255	}
	256
4e4d2bcf	257	switch (c->code_rate_LP) {
bc514710 CP	258	case FEC_2_3:
	259	tps \|= (1 << 4);
	260	break;
	261	case FEC_3_4:
	262	tps \|= (2 << 4);
	263	break;
	264	case FEC_5_6:
	265	tps \|= (3 << 4);
	266	break;
	267	case FEC_7_8:
	268	tps \|= (4 << 4);
	269	break;
	270	case FEC_1_2:
	271	case FEC_AUTO:
	272	break;
	273	case FEC_NONE:
4e4d2bcf MCC	274	if (c->hierarchy == HIERARCHY_AUTO \|\|
4e4d2bcf MCC	275	c->hierarchy == HIERARCHY_NONE)
bc514710 CP	276	break;
	277	default:
	278	return -EINVAL;
	279	}
	280
4e4d2bcf	281	switch (c->modulation) {
bc514710 CP	282	case QPSK:
	283	break;
	284	case QAM_AUTO:
	285	case QAM_16:
	286	tps \|= (1 << 13);
	287	break;
	288	case QAM_64:
	289	tps \|= (2 << 13);
	290	break;
	291	default:
	292	return -EINVAL;
	293	}
	294
4e4d2bcf	295	switch (c->transmission_mode) {
bc514710 CP	296	case TRANSMISSION_MODE_2K:
	297	case TRANSMISSION_MODE_AUTO:
	298	break;
	299	case TRANSMISSION_MODE_8K:
	300	tps \|= (1 << 0);
	301	break;
	302	default:
	303	return -EINVAL;
	304	}
	305
4e4d2bcf	306	switch (c->guard_interval) {
bc514710 CP	307	case GUARD_INTERVAL_1_32:
	308	case GUARD_INTERVAL_AUTO:
	309	break;
	310	case GUARD_INTERVAL_1_16:
	311	tps \|= (1 << 2);
	312	break;
	313	case GUARD_INTERVAL_1_8:
	314	tps \|= (2 << 2);
	315	break;
	316	case GUARD_INTERVAL_1_4:
	317	tps \|= (3 << 2);
	318	break;
	319	default:
	320	return -EINVAL;
	321	}
	322
4e4d2bcf	323	switch (c->hierarchy) {
bc514710 CP	324	case HIERARCHY_AUTO:
	325	case HIERARCHY_NONE:
	326	break;
	327	case HIERARCHY_1:
	328	tps \|= (1 << 10);
	329	break;
	330	case HIERARCHY_2:
	331	tps \|= (2 << 10);
	332	break;
	333	case HIERARCHY_4:
	334	tps \|= (3 << 10);
	335	break;
	336	default:
	337	return -EINVAL;
	338	}
	339
	340	zl10353_single_write(fe, TPS_GIVEN_1, msb(tps));
	341	zl10353_single_write(fe, TPS_GIVEN_0, lsb(tps));
	342
0a11bb86 AP	343	if (fe->ops.i2c_gate_ctrl)
0a11bb86 AP	344	fe->ops.i2c_gate_ctrl(fe, 0);
780dfef3	345
58d834ea CP	346	/*
	347	* If there is no tuner attached to the secondary I2C bus, we call
	348	* set_params to program a potential tuner attached somewhere else.
	349	* Otherwise, we update the PLL registers via calc_regs.
	350	*/
8dec0732	351	if (state->config.no_tuner) {
dea74869	352	if (fe->ops.tuner_ops.set_params) {
14d24d14	353	fe->ops.tuner_ops.set_params(fe);
0a11bb86 AP	354	if (fe->ops.i2c_gate_ctrl)
0a11bb86 AP	355	fe->ops.i2c_gate_ctrl(fe, 0);
8dec0732	356	}
58d834ea	357	} else if (fe->ops.tuner_ops.calc_regs) {
249fa0b0	358	fe->ops.tuner_ops.calc_regs(fe, pllbuf + 1, 5);
e994b8d9	359	pllbuf[1] <<= 1;
58d834ea	360	zl10353_write(fe, pllbuf, sizeof(pllbuf));
e994b8d9	361	}
780dfef3	362
fc3398d8	363	zl10353_single_write(fe, 0x5F, 0x13);
58d834ea CP	364
	365	/* If no attached tuner or invalid PLL registers, just start the FSM. */
	366	if (state->config.no_tuner \|\| fe->ops.tuner_ops.calc_regs == NULL)
	367	zl10353_single_write(fe, FSM_GO, 0x01);
	368	else
	369	zl10353_single_write(fe, TUNER_GO, 0x01);
	370
bc514710 CP	371	return 0;
	372	}
	373
7c61d80a	374	static int zl10353_get_parameters(struct dvb_frontend *fe)
bc514710	375	{
7c61d80a	376	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
bc514710	377	struct zl10353_state *state = fe->demodulator_priv;
bc514710 CP	378	int s6, s9;
	379	u16 tps;
	380	static const u8 tps_fec_to_api[8] = {
	381	FEC_1_2,
	382	FEC_2_3,
	383	FEC_3_4,
	384	FEC_5_6,
	385	FEC_7_8,
	386	FEC_AUTO,
	387	FEC_AUTO,
	388	FEC_AUTO
	389	};
	390
	391	s6 = zl10353_read_register(state, STATUS_6);
	392	s9 = zl10353_read_register(state, STATUS_9);
	393	if (s6 < 0 \|\| s9 < 0)
	394	return -EREMOTEIO;
	395	if ((s6 & (1 << 5)) == 0 \|\| (s9 & (1 << 4)) == 0)
	396	return -EINVAL; /* no FE or TPS lock */
	397
	398	tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 \|
	399	zl10353_read_register(state, TPS_RECEIVED_0);
	400
4e4d2bcf MCC	401	c->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
4e4d2bcf MCC	402	c->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
bc514710 CP	403
	404	switch ((tps >> 13) & 3) {
	405	case 0:
4e4d2bcf	406	c->modulation = QPSK;
bc514710 CP	407	break;
bc514710 CP	408	case 1:
4e4d2bcf	409	c->modulation = QAM_16;
bc514710 CP	410	break;
bc514710 CP	411	case 2:
4e4d2bcf	412	c->modulation = QAM_64;
bc514710 CP	413	break;
bc514710 CP	414	default:
4e4d2bcf	415	c->modulation = QAM_AUTO;
bc514710 CP	416	break;
	417	}
	418
4e4d2bcf	419	c->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K :
bc514710 CP	420	TRANSMISSION_MODE_2K;
	421
	422	switch ((tps >> 2) & 3) {
	423	case 0:
4e4d2bcf	424	c->guard_interval = GUARD_INTERVAL_1_32;
bc514710 CP	425	break;
bc514710 CP	426	case 1:
4e4d2bcf	427	c->guard_interval = GUARD_INTERVAL_1_16;
bc514710 CP	428	break;
bc514710 CP	429	case 2:
4e4d2bcf	430	c->guard_interval = GUARD_INTERVAL_1_8;
bc514710 CP	431	break;
bc514710 CP	432	case 3:
4e4d2bcf	433	c->guard_interval = GUARD_INTERVAL_1_4;
bc514710 CP	434	break;
bc514710 CP	435	default:
4e4d2bcf	436	c->guard_interval = GUARD_INTERVAL_AUTO;
bc514710 CP	437	break;
	438	}
	439
	440	switch ((tps >> 10) & 7) {
	441	case 0:
4e4d2bcf	442	c->hierarchy = HIERARCHY_NONE;
bc514710 CP	443	break;
bc514710 CP	444	case 1:
4e4d2bcf	445	c->hierarchy = HIERARCHY_1;
bc514710 CP	446	break;
bc514710 CP	447	case 2:
4e4d2bcf	448	c->hierarchy = HIERARCHY_2;
bc514710 CP	449	break;
bc514710 CP	450	case 3:
4e4d2bcf	451	c->hierarchy = HIERARCHY_4;
bc514710 CP	452	break;
bc514710 CP	453	default:
4e4d2bcf	454	c->hierarchy = HIERARCHY_AUTO;
bc514710 CP	455	break;
	456	}
	457
4e4d2bcf MCC	458	c->frequency = state->frequency;
	459	c->bandwidth_hz = state->bandwidth;
	460	c->inversion = INVERSION_AUTO;
780dfef3 CP	461
	462	return 0;
	463	}
	464
0df289a2	465	static int zl10353_read_status(struct dvb_frontend fe, enum fe_status status)
780dfef3 CP	466	{
	467	struct zl10353_state *state = fe->demodulator_priv;
	468	int s6, s7, s8;
	469
	470	if ((s6 = zl10353_read_register(state, STATUS_6)) < 0)
	471	return -EREMOTEIO;
	472	if ((s7 = zl10353_read_register(state, STATUS_7)) < 0)
	473	return -EREMOTEIO;
	474	if ((s8 = zl10353_read_register(state, STATUS_8)) < 0)
	475	return -EREMOTEIO;
	476
	477	*status = 0;
	478	if (s6 & (1 << 2))
	479	*status \|= FE_HAS_CARRIER;
	480	if (s6 & (1 << 1))
	481	*status \|= FE_HAS_VITERBI;
	482	if (s6 & (1 << 5))
	483	*status \|= FE_HAS_LOCK;
	484	if (s7 & (1 << 4))
	485	*status \|= FE_HAS_SYNC;
	486	if (s8 & (1 << 6))
	487	*status \|= FE_HAS_SIGNAL;
	488
	489	if ((*status & (FE_HAS_CARRIER \| FE_HAS_VITERBI \| FE_HAS_SYNC)) !=
	490	(FE_HAS_CARRIER \| FE_HAS_VITERBI \| FE_HAS_SYNC))
	491	*status &= ~FE_HAS_LOCK;
	492
	493	return 0;
	494	}
	495
67b60aad CP	496	static int zl10353_read_ber(struct dvb_frontend fe, u32 ber)
	497	{
	498	struct zl10353_state *state = fe->demodulator_priv;
	499
6345f0f6 CP	500	*ber = zl10353_read_register(state, RS_ERR_CNT_2) << 16 \|
	501	zl10353_read_register(state, RS_ERR_CNT_1) << 8 \|
	502	zl10353_read_register(state, RS_ERR_CNT_0);
67b60aad CP	503
	504	return 0;
	505	}
	506
	507	static int zl10353_read_signal_strength(struct dvb_frontend fe, u16 strength)
	508	{
	509	struct zl10353_state *state = fe->demodulator_priv;
	510
6345f0f6 CP	511	u16 signal = zl10353_read_register(state, AGC_GAIN_1) << 10 \|
6345f0f6 CP	512	zl10353_read_register(state, AGC_GAIN_0) << 2 \| 3;
67b60aad CP	513
	514	*strength = ~signal;
	515
	516	return 0;
	517	}
	518
780dfef3 CP	519	static int zl10353_read_snr(struct dvb_frontend fe, u16 snr)
	520	{
	521	struct zl10353_state *state = fe->demodulator_priv;
	522	u8 _snr;
	523
	524	if (debug_regs)
	525	zl10353_dump_regs(fe);
	526
	527	_snr = zl10353_read_register(state, SNR);
13c6a9f7	528	snr = 10 _snr / 8;
780dfef3 CP	529
	530	return 0;
	531	}
	532
67b60aad CP	533	static int zl10353_read_ucblocks(struct dvb_frontend fe, u32 ucblocks)
	534	{
	535	struct zl10353_state *state = fe->demodulator_priv;
2267d2d7	536	u32 ubl = 0;
decee2e8	537
2267d2d7 MCC	538	ubl = zl10353_read_register(state, RS_UBC_1) << 8 \|
2267d2d7 MCC	539	zl10353_read_register(state, RS_UBC_0);
67b60aad	540
2267d2d7 MCC	541	state->ucblocks += ubl;
2267d2d7 MCC	542	*ucblocks = state->ucblocks;
67b60aad CP	543
	544	return 0;
	545	}
	546
780dfef3 CP	547	static int zl10353_get_tune_settings(struct dvb_frontend *fe,
	548	struct dvb_frontend_tune_settings
	549	*fe_tune_settings)
	550	{
	551	fe_tune_settings->min_delay_ms = 1000;
	552	fe_tune_settings->step_size = 0;
	553	fe_tune_settings->max_drift = 0;
	554
	555	return 0;
	556	}
	557
	558	static int zl10353_init(struct dvb_frontend *fe)
	559	{
	560	struct zl10353_state *state = fe->demodulator_priv;
	561	u8 zl10353_reset_attach[6] = { 0x50, 0x03, 0x64, 0x46, 0x15, 0x0F };
780dfef3 CP	562
	563	if (debug_regs)
	564	zl10353_dump_regs(fe);
8fb95784 CP	565	if (state->config.parallel_ts)
8fb95784 CP	566	zl10353_reset_attach[2] &= ~0x20;
378a2793 AP	567	if (state->config.clock_ctl_1)
	568	zl10353_reset_attach[3] = state->config.clock_ctl_1;
	569	if (state->config.pll_0)
	570	zl10353_reset_attach[4] = state->config.pll_0;
780dfef3 CP	571
780dfef3 CP	572	/* Do a "hard" reset if not already done */
8fb95784 CP	573	if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] \|\|
8fb95784 CP	574	zl10353_read_register(state, 0x51) != zl10353_reset_attach[2]) {
fdf07b02	575	zl10353_write(fe, zl10353_reset_attach,
780dfef3 CP	576	sizeof(zl10353_reset_attach));
	577	if (debug_regs)
	578	zl10353_dump_regs(fe);
	579	}
	580
	581	return 0;
	582	}
	583
0a11bb86 AP	584	static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
0a11bb86 AP	585	{
899a6f67	586	struct zl10353_state *state = fe->demodulator_priv;
0a11bb86 AP	587	u8 val = 0x0a;
0a11bb86 AP	588
5f77af93	589	if (state->config.disable_i2c_gate_ctrl) {
899a6f67 DB	590	/* No tuner attached to the internal I2C bus */
	591	/* If set enable I2C bridge, the main I2C bus stopped hardly */
	592	return 0;
	593	}
	594
0a11bb86 AP	595	if (enable)
	596	val \|= 0x10;
	597
	598	return zl10353_single_write(fe, 0x62, val);
	599	}
	600
780dfef3 CP	601	static void zl10353_release(struct dvb_frontend *fe)
	602	{
	603	struct zl10353_state *state = fe->demodulator_priv;
780dfef3 CP	604	kfree(state);
	605	}
	606
	607	static struct dvb_frontend_ops zl10353_ops;
	608
	609	struct dvb_frontend zl10353_attach(const struct zl10353_config config,
	610	struct i2c_adapter *i2c)
	611	{
	612	struct zl10353_state *state = NULL;
378a2793	613	int id;
780dfef3 CP	614
	615	/* allocate memory for the internal state */
	616	state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL);
	617	if (state == NULL)
	618	goto error;
	619
	620	/* setup the state */
	621	state->i2c = i2c;
	622	memcpy(&state->config, config, sizeof(struct zl10353_config));
780dfef3 CP	623
780dfef3 CP	624	/* check if the demod is there */
378a2793 AP	625	id = zl10353_read_register(state, CHIP_ID);
378a2793 AP	626	if ((id != ID_ZL10353) && (id != ID_CE6230) && (id != ID_CE6231))
780dfef3 CP	627	goto error;
	628
	629	/* create dvb_frontend */
dea74869	630	memcpy(&state->frontend.ops, &zl10353_ops, sizeof(struct dvb_frontend_ops));
780dfef3 CP	631	state->frontend.demodulator_priv = state;
	632
	633	return &state->frontend;
	634	error:
	635	kfree(state);
	636	return NULL;
	637	}
	638
	639	static struct dvb_frontend_ops zl10353_ops = {
4e4d2bcf	640	.delsys = { SYS_DVBT },
780dfef3 CP	641	.info = {
780dfef3 CP	642	.name = "Zarlink ZL10353 DVB-T",
780dfef3 CP	643	.frequency_min = 174000000,
	644	.frequency_max = 862000000,
	645	.frequency_stepsize = 166667,
	646	.frequency_tolerance = 0,
	647	.caps = FE_CAN_FEC_1_2 \| FE_CAN_FEC_2_3 \|
	648	FE_CAN_FEC_3_4 \| FE_CAN_FEC_5_6 \| FE_CAN_FEC_7_8 \|
	649	FE_CAN_FEC_AUTO \|
	650	FE_CAN_QPSK \| FE_CAN_QAM_16 \| FE_CAN_QAM_64 \| FE_CAN_QAM_AUTO \|
	651	FE_CAN_TRANSMISSION_MODE_AUTO \| FE_CAN_GUARD_INTERVAL_AUTO \|
	652	FE_CAN_HIERARCHY_AUTO \| FE_CAN_RECOVER \|
	653	FE_CAN_MUTE_TS
	654	},
	655
	656	.release = zl10353_release,
	657
	658	.init = zl10353_init,
	659	.sleep = zl10353_sleep,
0a11bb86	660	.i2c_gate_ctrl = zl10353_i2c_gate_ctrl,
c10d14d6	661	.write = zl10353_write,
780dfef3	662
4e4d2bcf MCC	663	.set_frontend = zl10353_set_parameters,
4e4d2bcf MCC	664	.get_frontend = zl10353_get_parameters,
780dfef3 CP	665	.get_tune_settings = zl10353_get_tune_settings,
	666
	667	.read_status = zl10353_read_status,
67b60aad CP	668	.read_ber = zl10353_read_ber,
67b60aad CP	669	.read_signal_strength = zl10353_read_signal_strength,
780dfef3	670	.read_snr = zl10353_read_snr,
67b60aad	671	.read_ucblocks = zl10353_read_ucblocks,
780dfef3 CP	672	};
780dfef3 CP	673
f7f57770 AP	674	module_param(debug, int, 0644);
	675	MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
	676
780dfef3 CP	677	module_param(debug_regs, int, 0644);
	678	MODULE_PARM_DESC(debug_regs, "Turn on/off frontend register dumps (default:off).");
	679
	680	MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver");
	681	MODULE_AUTHOR("Chris Pascoe");
	682	MODULE_LICENSE("GPL");
	683
	684	EXPORT_SYMBOL(zl10353_attach);