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[media] dvb: Get rid of typedev usage for enums
[linux-2.6-block.git] / drivers / media / dvb-frontends / m88ds3103.c
CommitLineData
395d00d1 1/*
f4df95bc 2 * Montage M88DS3103/M88RS6000 demodulator driver
395d00d1
AP		 3 *
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
395d00d1
AP		 15 */
16
17#include "m88ds3103_priv.h"
18
19static struct dvb_frontend_ops m88ds3103_ops;
20
21/* write multiple registers */
22static int m88ds3103_wr_regs(struct m88ds3103_priv *priv,
23 u8 reg, const u8 *val, int len)
24{
63c80f70
AP		 25#define MAX_WR_LEN 32
26#define MAX_WR_XFER_LEN (MAX_WR_LEN + 1)
395d00d1 27 int ret;
63c80f70 28 u8 buf[MAX_WR_XFER_LEN];
395d00d1
AP		 29 struct i2c_msg msg[1] = {
30 {
31 .addr = priv->cfg->i2c_addr,
32 .flags = 0,
63c80f70 33 .len = 1 + len,
395d00d1
AP		 34 .buf = buf,
35 }
36 };
37
63c80f70
AP		 38 if (WARN_ON(len > MAX_WR_LEN))
39 return -EINVAL;
40
395d00d1
AP		 41 buf[0] = reg;
42 memcpy(&buf[1], val, len);
43
44 mutex_lock(&priv->i2c_mutex);
45 ret = i2c_transfer(priv->i2c, msg, 1);
46 mutex_unlock(&priv->i2c_mutex);
47 if (ret == 1) {
48 ret = 0;
49 } else {
50 dev_warn(&priv->i2c->dev,
51 "%s: i2c wr failed=%d reg=%02x len=%d\n",
52 KBUILD_MODNAME, ret, reg, len);
53 ret = -EREMOTEIO;
54 }
55
56 return ret;
57}
58
59/* read multiple registers */
60static int m88ds3103_rd_regs(struct m88ds3103_priv *priv,
61 u8 reg, u8 *val, int len)
62{
63c80f70
AP		 63#define MAX_RD_LEN 3
64#define MAX_RD_XFER_LEN (MAX_RD_LEN)
395d00d1 65 int ret;
63c80f70 66 u8 buf[MAX_RD_XFER_LEN];
395d00d1
AP		 67 struct i2c_msg msg[2] = {
68 {
69 .addr = priv->cfg->i2c_addr,
70 .flags = 0,
71 .len = 1,
72 .buf = &reg,
73 }, {
74 .addr = priv->cfg->i2c_addr,
75 .flags = I2C_M_RD,
63c80f70 76 .len = len,
395d00d1
AP		 77 .buf = buf,
78 }
79 };
80
63c80f70
AP		 81 if (WARN_ON(len > MAX_RD_LEN))
82 return -EINVAL;
83
395d00d1
AP		 84 mutex_lock(&priv->i2c_mutex);
85 ret = i2c_transfer(priv->i2c, msg, 2);
86 mutex_unlock(&priv->i2c_mutex);
87 if (ret == 2) {
88 memcpy(val, buf, len);
89 ret = 0;
90 } else {
91 dev_warn(&priv->i2c->dev,
92 "%s: i2c rd failed=%d reg=%02x len=%d\n",
93 KBUILD_MODNAME, ret, reg, len);
94 ret = -EREMOTEIO;
95 }
96
97 return ret;
98}
99
100/* write single register */
101static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val)
102{
103 return m88ds3103_wr_regs(priv, reg, &val, 1);
104}
105
106/* read single register */
107static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val)
108{
109 return m88ds3103_rd_regs(priv, reg, val, 1);
110}
111
112/* write single register with mask */
113static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv,
114 u8 reg, u8 val, u8 mask)
115{
116 int ret;
117 u8 u8tmp;
118
119 /* no need for read if whole reg is written */
120 if (mask != 0xff) {
121 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
122 if (ret)
123 return ret;
124
125 val &= mask;
126 u8tmp &= ~mask;
127 val |= u8tmp;
128 }
129
130 return m88ds3103_wr_regs(priv, reg, &val, 1);
131}
132
133/* read single register with mask */
134static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv,
135 u8 reg, u8 *val, u8 mask)
136{
137 int ret, i;
138 u8 u8tmp;
139
140 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
141 if (ret)
142 return ret;
143
144 u8tmp &= mask;
145
146 /* find position of the first bit */
147 for (i = 0; i < 8; i++) {
148 if ((mask >> i) & 0x01)
149 break;
150 }
151 *val = u8tmp >> i;
152
153 return 0;
154}
155
06487dee
AP		 156/* write reg val table using reg addr auto increment */
157static int m88ds3103_wr_reg_val_tab(struct m88ds3103_priv *priv,
158 const struct m88ds3103_reg_val *tab, int tab_len)
159{
160 int ret, i, j;
161 u8 buf[83];
41b9aa00 162
06487dee
AP		 163 dev_dbg(&priv->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len);
164
f4df95bc 165 if (tab_len > 86) {
06487dee
AP		 166 ret = -EINVAL;
167 goto err;
168 }
169
170 for (i = 0, j = 0; i < tab_len; i++, j++) {
171 buf[j] = tab[i].val;
172
173 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
174 !((j + 1) % (priv->cfg->i2c_wr_max - 1))) {
175 ret = m88ds3103_wr_regs(priv, tab[i].reg - j, buf, j + 1);
176 if (ret)
177 goto err;
178
179 j = -1;
180 }
181 }
182
183 return 0;
184err:
185 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
186 return ret;
187}
188
0df289a2
MCC		 189static int m88ds3103_read_status(struct dvb_frontend *fe,
190 enum fe_status *status)
395d00d1
AP		 191{
192 struct m88ds3103_priv *priv = fe->demodulator_priv;
193 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
c1daf651 194 int ret, i, itmp;
395d00d1 195 u8 u8tmp;
c1daf651 196 u8 buf[3];
395d00d1
AP		 197
198 *status = 0;
199
200 if (!priv->warm) {
201 ret = -EAGAIN;
202 goto err;
203 }
204
205 switch (c->delivery_system) {
206 case SYS_DVBS:
207 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07);
208 if (ret)
209 goto err;
210
211 if (u8tmp == 0x07)
212 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
213 FE_HAS_VITERBI | FE_HAS_SYNC |
214 FE_HAS_LOCK;
215 break;
216 case SYS_DVBS2:
217 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f);
218 if (ret)
219 goto err;
220
221 if (u8tmp == 0x8f)
222 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
223 FE_HAS_VITERBI | FE_HAS_SYNC |
224 FE_HAS_LOCK;
225 break;
226 default:
227 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
228 __func__);
229 ret = -EINVAL;
230 goto err;
231 }
232
233 priv->fe_status = *status;
234
235 dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n",
236 __func__, u8tmp, *status);
237
c1daf651
AP		 238 /* CNR */
239 if (priv->fe_status & FE_HAS_VITERBI) {
240 unsigned int cnr, noise, signal, noise_tot, signal_tot;
241
242 cnr = 0;
243 /* more iterations for more accurate estimation */
244 #define M88DS3103_SNR_ITERATIONS 3
245
246 switch (c->delivery_system) {
247 case SYS_DVBS:
248 itmp = 0;
249
250 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
251 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]);
252 if (ret)
253 goto err;
254
255 itmp += buf[0];
256 }
257
258 /* use of single register limits max value to 15 dB */
259 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
260 itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS);
261 if (itmp)
262 cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10));
263 break;
264 case SYS_DVBS2:
265 noise_tot = 0;
266 signal_tot = 0;
267
268 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
269 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3);
270 if (ret)
271 goto err;
272
273 noise = buf[1] << 6; /* [13:6] */
274 noise |= buf[0] & 0x3f; /* [5:0] */
275 noise >>= 2;
276 signal = buf[2] * buf[2];
277 signal >>= 1;
278
279 noise_tot += noise;
280 signal_tot += signal;
281 }
282
283 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
284 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
285
286 /* SNR(X) dB = 10 * log10(X) dB */
287 if (signal > noise) {
288 itmp = signal / noise;
289 cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24));
290 }
291 break;
292 default:
293 dev_dbg(&priv->i2c->dev,
294 "%s: invalid delivery_system\n", __func__);
295 ret = -EINVAL;
296 goto err;
297 }
298
299 if (cnr) {
300 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
301 c->cnr.stat[0].svalue = cnr;
302 } else {
303 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
304 }
305 } else {
306 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
307 }
308
ce80d713
AP		 309 /* BER */
310 if (priv->fe_status & FE_HAS_LOCK) {
311 unsigned int utmp, post_bit_error, post_bit_count;
312
313 switch (c->delivery_system) {
314 case SYS_DVBS:
315 ret = m88ds3103_wr_reg(priv, 0xf9, 0x04);
316 if (ret)
317 goto err;
318
319 ret = m88ds3103_rd_reg(priv, 0xf8, &u8tmp);
320 if (ret)
321 goto err;
322
323 /* measurement ready? */
324 if (!(u8tmp & 0x10)) {
325 ret = m88ds3103_rd_regs(priv, 0xf6, buf, 2);
326 if (ret)
327 goto err;
328
329 post_bit_error = buf[1] << 8 | buf[0] << 0;
330 post_bit_count = 0x800000;
331 priv->post_bit_error += post_bit_error;
332 priv->post_bit_count += post_bit_count;
333 priv->dvbv3_ber = post_bit_error;
334
335 /* restart measurement */
336 u8tmp |= 0x10;
337 ret = m88ds3103_wr_reg(priv, 0xf8, u8tmp);
338 if (ret)
339 goto err;
340 }
341 break;
342 case SYS_DVBS2:
343 ret = m88ds3103_rd_regs(priv, 0xd5, buf, 3);
344 if (ret)
345 goto err;
346
347 utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
348
349 /* enough data? */
350 if (utmp > 4000) {
351 ret = m88ds3103_rd_regs(priv, 0xf7, buf, 2);
352 if (ret)
353 goto err;
354
355 post_bit_error = buf[1] << 8 | buf[0] << 0;
356 post_bit_count = 32 * utmp; /* TODO: FEC */
357 priv->post_bit_error += post_bit_error;
358 priv->post_bit_count += post_bit_count;
359 priv->dvbv3_ber = post_bit_error;
360
361 /* restart measurement */
362 ret = m88ds3103_wr_reg(priv, 0xd1, 0x01);
363 if (ret)
364 goto err;
365
366 ret = m88ds3103_wr_reg(priv, 0xf9, 0x01);
367 if (ret)
368 goto err;
369
370 ret = m88ds3103_wr_reg(priv, 0xf9, 0x00);
371 if (ret)
372 goto err;
373
374 ret = m88ds3103_wr_reg(priv, 0xd1, 0x00);
375 if (ret)
376 goto err;
377 }
378 break;
379 default:
380 dev_dbg(&priv->i2c->dev,
381 "%s: invalid delivery_system\n", __func__);
382 ret = -EINVAL;
383 goto err;
384 }
385
386 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
387 c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
388 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
389 c->post_bit_count.stat[0].uvalue = priv->post_bit_count;
390 } else {
391 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
392 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
393 }
394
395d00d1
AP		 395 return 0;
396err:
397 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
398 return ret;
399}
400
401static int m88ds3103_set_frontend(struct dvb_frontend *fe)
402{
403 struct m88ds3103_priv *priv = fe->demodulator_priv;
404 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
06487dee 405 int ret, len;
395d00d1 406 const struct m88ds3103_reg_val *init;
b6851419 407 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */
f4df95bc 408 u8 buf[3];
b6851419 409 u16 u16tmp, divide_ratio = 0;
79d09330 410 u32 tuner_frequency, target_mclk;
395d00d1 411 s32 s32tmp;
41b9aa00 412
395d00d1
AP		 413 dev_dbg(&priv->i2c->dev,
414 "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
415 __func__, c->delivery_system,
416 c->modulation, c->frequency, c->symbol_rate,
417 c->inversion, c->pilot, c->rolloff);
418
419 if (!priv->warm) {
420 ret = -EAGAIN;
421 goto err;
422 }
423
f4df95bc 424 /* reset */
425 ret = m88ds3103_wr_reg(priv, 0x07, 0x80);
426 if (ret)
427 goto err;
428
429 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
430 if (ret)
431 goto err;
432
433 /* Disable demod clock path */
434 if (priv->chip_id == M88RS6000_CHIP_ID) {
435 ret = m88ds3103_wr_reg(priv, 0x06, 0xe0);
436 if (ret)
437 goto err;
438 }
439
395d00d1
AP		 440 /* program tuner */
441 if (fe->ops.tuner_ops.set_params) {
442 ret = fe->ops.tuner_ops.set_params(fe);
443 if (ret)
444 goto err;
445 }
446
447 if (fe->ops.tuner_ops.get_frequency) {
448 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
449 if (ret)
450 goto err;
2f9dff3f
AP		 451 } else {
452 /*
453 * Use nominal target frequency as tuner driver does not provide
454 * actual frequency used. Carrier offset calculation is not
455 * valid.
456 */
457 tuner_frequency = c->frequency;
395d00d1
AP		 458 }
459
f4df95bc 460 /* select M88RS6000 demod main mclk and ts mclk from tuner die. */
461 if (priv->chip_id == M88RS6000_CHIP_ID) {
462 if (c->symbol_rate > 45010000)
463 priv->mclk_khz = 110250;
464 else
465 priv->mclk_khz = 96000;
395d00d1 466
f4df95bc 467 if (c->delivery_system == SYS_DVBS)
468 target_mclk = 96000;
469 else
470 target_mclk = 144000;
471
472 /* Enable demod clock path */
473 ret = m88ds3103_wr_reg(priv, 0x06, 0x00);
474 if (ret)
475 goto err;
476 usleep_range(10000, 20000);
477 } else {
478 /* set M88DS3103 mclk and ts mclk. */
479 priv->mclk_khz = 96000;
480
b6851419 481 switch (priv->cfg->ts_mode) {
482 case M88DS3103_TS_SERIAL:
483 case M88DS3103_TS_SERIAL_D7:
484 target_mclk = priv->cfg->ts_clk;
485 break;
486 case M88DS3103_TS_PARALLEL:
487 case M88DS3103_TS_CI:
488 if (c->delivery_system == SYS_DVBS)
489 target_mclk = 96000;
490 else {
f4df95bc 491 if (c->symbol_rate < 18000000)
492 target_mclk = 96000;
493 else if (c->symbol_rate < 28000000)
494 target_mclk = 144000;
495 else
496 target_mclk = 192000;
f4df95bc 497 }
b6851419 498 break;
499 default:
500 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n",
501 __func__);
502 ret = -EINVAL;
503 goto err;
f4df95bc 504 }
505
506 switch (target_mclk) {
507 case 96000:
508 u8tmp1 = 0x02; /* 0b10 */
509 u8tmp2 = 0x01; /* 0b01 */
510 break;
511 case 144000:
512 u8tmp1 = 0x00; /* 0b00 */
513 u8tmp2 = 0x01; /* 0b01 */
514 break;
515 case 192000:
516 u8tmp1 = 0x03; /* 0b11 */
517 u8tmp2 = 0x00; /* 0b00 */
518 break;
519 }
520 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0);
521 if (ret)
522 goto err;
523 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0);
524 if (ret)
525 goto err;
526 }
395d00d1
AP		 527
528 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
529 if (ret)
530 goto err;
531
532 ret = m88ds3103_wr_reg(priv, 0x00, 0x01);
533 if (ret)
534 goto err;
535
536 switch (c->delivery_system) {
537 case SYS_DVBS:
f4df95bc 538 if (priv->chip_id == M88RS6000_CHIP_ID) {
539 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals);
540 init = m88rs6000_dvbs_init_reg_vals;
541 } else {
542 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
543 init = m88ds3103_dvbs_init_reg_vals;
544 }
395d00d1
AP		 545 break;
546 case SYS_DVBS2:
f4df95bc 547 if (priv->chip_id == M88RS6000_CHIP_ID) {
548 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals);
549 init = m88rs6000_dvbs2_init_reg_vals;
550 } else {
551 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
552 init = m88ds3103_dvbs2_init_reg_vals;
395d00d1
AP		 553 }
554 break;
555 default:
556 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
557 __func__);
558 ret = -EINVAL;
559 goto err;
560 }
561
562 /* program init table */
563 if (c->delivery_system != priv->delivery_system) {
06487dee
AP		 564 ret = m88ds3103_wr_reg_val_tab(priv, init, len);
565 if (ret)
566 goto err;
395d00d1
AP		 567 }
568
f4df95bc 569 if (priv->chip_id == M88RS6000_CHIP_ID) {
570 if ((c->delivery_system == SYS_DVBS2)
571 && ((c->symbol_rate / 1000) <= 5000)) {
572 ret = m88ds3103_wr_reg(priv, 0xc0, 0x04);
573 if (ret)
574 goto err;
575 buf[0] = 0x09;
576 buf[1] = 0x22;
577 buf[2] = 0x88;
578 ret = m88ds3103_wr_regs(priv, 0x8a, buf, 3);
579 if (ret)
580 goto err;
581 }
582 ret = m88ds3103_wr_reg_mask(priv, 0x9d, 0x08, 0x08);
583 if (ret)
584 goto err;
585 ret = m88ds3103_wr_reg(priv, 0xf1, 0x01);
586 if (ret)
587 goto err;
588 ret = m88ds3103_wr_reg_mask(priv, 0x30, 0x80, 0x80);
589 if (ret)
590 goto err;
591 }
592
395d00d1
AP		 593 switch (priv->cfg->ts_mode) {
594 case M88DS3103_TS_SERIAL:
595 u8tmp1 = 0x00;
79d09330 596 u8tmp = 0x06;
395d00d1
AP		 597 break;
598 case M88DS3103_TS_SERIAL_D7:
599 u8tmp1 = 0x20;
79d09330 600 u8tmp = 0x06;
395d00d1
AP		 601 break;
602 case M88DS3103_TS_PARALLEL:
79d09330 603 u8tmp = 0x02;
395d00d1
AP		 604 break;
605 case M88DS3103_TS_CI:
79d09330 606 u8tmp = 0x03;
395d00d1
AP		 607 break;
608 default:
609 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__);
610 ret = -EINVAL;
611 goto err;
612 }
613
79d09330 614 if (priv->cfg->ts_clk_pol)
615 u8tmp |= 0x40;
616
395d00d1 617 /* TS mode */
92676ac9 618 ret = m88ds3103_wr_reg(priv, 0xfd, u8tmp);
395d00d1
AP		 619 if (ret)
620 goto err;
621
622 switch (priv->cfg->ts_mode) {
623 case M88DS3103_TS_SERIAL:
624 case M88DS3103_TS_SERIAL_D7:
625 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20);
626 if (ret)
627 goto err;
395d00d1
AP		 628 u8tmp1 = 0;
629 u8tmp2 = 0;
b6851419 630 break;
631 default:
632 if (priv->cfg->ts_clk) {
633 divide_ratio = DIV_ROUND_UP(target_mclk, priv->cfg->ts_clk);
634 u8tmp1 = divide_ratio / 2;
635 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
636 }
395d00d1
AP		 637 }
638
639 dev_dbg(&priv->i2c->dev,
640 "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n",
79d09330 641 __func__, target_mclk, priv->cfg->ts_clk, divide_ratio);
395d00d1
AP		 642
643 u8tmp1--;
644 u8tmp2--;
645 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
646 u8tmp1 &= 0x3f;
647 /* u8tmp2[5:0] => ea[5:0] */
648 u8tmp2 &= 0x3f;
649
650 ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp);
651 if (ret)
652 goto err;
653
654 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
655 ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp);
656 if (ret)
657 goto err;
658
659 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
660 ret = m88ds3103_wr_reg(priv, 0xea, u8tmp);
661 if (ret)
662 goto err;
663
395d00d1
AP		 664 if (c->symbol_rate <= 3000000)
665 u8tmp = 0x20;
666 else if (c->symbol_rate <= 10000000)
667 u8tmp = 0x10;
668 else
669 u8tmp = 0x06;
670
671 ret = m88ds3103_wr_reg(priv, 0xc3, 0x08);
672 if (ret)
673 goto err;
674
675 ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp);
676 if (ret)
677 goto err;
678
679 ret = m88ds3103_wr_reg(priv, 0xc4, 0x08);
680 if (ret)
681 goto err;
682
683 ret = m88ds3103_wr_reg(priv, 0xc7, 0x00);
684 if (ret)
685 goto err;
686
f4df95bc 687 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, priv->mclk_khz / 2);
395d00d1
AP		 688 buf[0] = (u16tmp >> 0) & 0xff;
689 buf[1] = (u16tmp >> 8) & 0xff;
690 ret = m88ds3103_wr_regs(priv, 0x61, buf, 2);
691 if (ret)
692 goto err;
693
694 ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02);
695 if (ret)
696 goto err;
697
698 ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10);
699 if (ret)
700 goto err;
701
702 ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc);
703 if (ret)
704 goto err;
705
706 dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__,
707 (tuner_frequency - c->frequency));
708
709 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
f4df95bc 710 s32tmp = DIV_ROUND_CLOSEST(s32tmp, priv->mclk_khz);
395d00d1
AP		 711 if (s32tmp < 0)
712 s32tmp += 0x10000;
713
714 buf[0] = (s32tmp >> 0) & 0xff;
715 buf[1] = (s32tmp >> 8) & 0xff;
716 ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2);
717 if (ret)
718 goto err;
719
720 ret = m88ds3103_wr_reg(priv, 0x00, 0x00);
721 if (ret)
722 goto err;
723
724 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
725 if (ret)
726 goto err;
727
728 priv->delivery_system = c->delivery_system;
729
730 return 0;
731err:
732 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
733 return ret;
734}
735
736static int m88ds3103_init(struct dvb_frontend *fe)
737{
738 struct m88ds3103_priv *priv = fe->demodulator_priv;
c1daf651 739 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
395d00d1
AP		 740 int ret, len, remaining;
741 const struct firmware *fw = NULL;
f4df95bc 742 u8 *fw_file;
395d00d1 743 u8 u8tmp;
41b9aa00 744
395d00d1
AP		 745 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
746
747 /* set cold state by default */
748 priv->warm = false;
749
750 /* wake up device from sleep */
751 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01);
752 if (ret)
753 goto err;
754
755 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01);
756 if (ret)
757 goto err;
758
759 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10);
760 if (ret)
761 goto err;
762
395d00d1
AP		 763 /* firmware status */
764 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
765 if (ret)
766 goto err;
767
768 dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp);
769
770 if (u8tmp)
771 goto skip_fw_download;
772
f4df95bc 773 /* global reset, global diseqc reset, golbal fec reset */
774 ret = m88ds3103_wr_reg(priv, 0x07, 0xe0);
775 if (ret)
776 goto err;
777
778 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
779 if (ret)
780 goto err;
781
395d00d1
AP		 782 /* cold state - try to download firmware */
783 dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n",
784 KBUILD_MODNAME, m88ds3103_ops.info.name);
785
f4df95bc 786 if (priv->chip_id == M88RS6000_CHIP_ID)
787 fw_file = M88RS6000_FIRMWARE;
788 else
789 fw_file = M88DS3103_FIRMWARE;
395d00d1
AP		 790 /* request the firmware, this will block and timeout */
791 ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent);
792 if (ret) {
a87a4d34 793 dev_err(&priv->i2c->dev, "%s: firmware file '%s' not found\n",
395d00d1
AP		 794 KBUILD_MODNAME, fw_file);
795 goto err;
796 }
797
798 dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n",
799 KBUILD_MODNAME, fw_file);
800
801 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
802 if (ret)
5ed0cf88 803 goto error_fw_release;
395d00d1
AP		 804
805 for (remaining = fw->size; remaining > 0;
806 remaining -= (priv->cfg->i2c_wr_max - 1)) {
807 len = remaining;
808 if (len > (priv->cfg->i2c_wr_max - 1))
809 len = (priv->cfg->i2c_wr_max - 1);
810
811 ret = m88ds3103_wr_regs(priv, 0xb0,
812 &fw->data[fw->size - remaining], len);
813 if (ret) {
814 dev_err(&priv->i2c->dev,
815 "%s: firmware download failed=%d\n",
816 KBUILD_MODNAME, ret);
5ed0cf88 817 goto error_fw_release;
395d00d1
AP		 818 }
819 }
820
821 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
822 if (ret)
5ed0cf88 823 goto error_fw_release;
395d00d1
AP		 824
825 release_firmware(fw);
826 fw = NULL;
827
828 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
829 if (ret)
830 goto err;
831
832 if (!u8tmp) {
833 dev_info(&priv->i2c->dev, "%s: firmware did not run\n",
834 KBUILD_MODNAME);
835 ret = -EFAULT;
836 goto err;
837 }
838
839 dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n",
840 KBUILD_MODNAME, m88ds3103_ops.info.name);
841 dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n",
842 KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf));
843
844skip_fw_download:
845 /* warm state */
846 priv->warm = true;
c1daf651
AP		 847 /* init stats here in order signal app which stats are supported */
848 c->cnr.len = 1;
849 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
ce80d713
AP		 850 c->post_bit_error.len = 1;
851 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
852 c->post_bit_count.len = 1;
853 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
395d00d1 854 return 0;
395d00d1 855
5ed0cf88
ME		 856error_fw_release:
857 release_firmware(fw);
858err:
395d00d1
AP		 859 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
860 return ret;
861}
862
863static int m88ds3103_sleep(struct dvb_frontend *fe)
864{
865 struct m88ds3103_priv *priv = fe->demodulator_priv;
866 int ret;
f4df95bc 867 u8 u8tmp;
41b9aa00 868
395d00d1
AP		 869 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
870
c1daf651 871 priv->fe_status = 0;
395d00d1
AP		 872 priv->delivery_system = SYS_UNDEFINED;
873
874 /* TS Hi-Z */
f4df95bc 875 if (priv->chip_id == M88RS6000_CHIP_ID)
876 u8tmp = 0x29;
877 else
878 u8tmp = 0x27;
879 ret = m88ds3103_wr_reg_mask(priv, u8tmp, 0x00, 0x01);
395d00d1
AP		 880 if (ret)
881 goto err;
882
883 /* sleep */
884 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
885 if (ret)
886 goto err;
887
888 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
889 if (ret)
890 goto err;
891
892 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
893 if (ret)
894 goto err;
895
896 return 0;
897err:
898 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
899 return ret;
900}
901
902static int m88ds3103_get_frontend(struct dvb_frontend *fe)
903{
904 struct m88ds3103_priv *priv = fe->demodulator_priv;
905 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
906 int ret;
907 u8 buf[3];
41b9aa00 908
395d00d1
AP		 909 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
910
911 if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) {
9240c384 912 ret = 0;
395d00d1
AP		 913 goto err;
914 }
915
916 switch (c->delivery_system) {
917 case SYS_DVBS:
918 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]);
919 if (ret)
920 goto err;
921
922 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]);
923 if (ret)
924 goto err;
925
926 switch ((buf[0] >> 2) & 0x01) {
927 case 0:
928 c->inversion = INVERSION_OFF;
929 break;
930 case 1:
931 c->inversion = INVERSION_ON;
932 break;
395d00d1
AP		 933 }
934
935 switch ((buf[1] >> 5) & 0x07) {
936 case 0:
937 c->fec_inner = FEC_7_8;
938 break;
939 case 1:
940 c->fec_inner = FEC_5_6;
941 break;
942 case 2:
943 c->fec_inner = FEC_3_4;
944 break;
945 case 3:
946 c->fec_inner = FEC_2_3;
947 break;
948 case 4:
949 c->fec_inner = FEC_1_2;
950 break;
951 default:
952 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
953 __func__);
954 }
955
956 c->modulation = QPSK;
957
958 break;
959 case SYS_DVBS2:
960 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]);
961 if (ret)
962 goto err;
963
964 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]);
965 if (ret)
966 goto err;
967
968 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]);
969 if (ret)
970 goto err;
971
972 switch ((buf[0] >> 0) & 0x0f) {
973 case 2:
974 c->fec_inner = FEC_2_5;
975 break;
976 case 3:
977 c->fec_inner = FEC_1_2;
978 break;
979 case 4:
980 c->fec_inner = FEC_3_5;
981 break;
982 case 5:
983 c->fec_inner = FEC_2_3;
984 break;
985 case 6:
986 c->fec_inner = FEC_3_4;
987 break;
988 case 7:
989 c->fec_inner = FEC_4_5;
990 break;
991 case 8:
992 c->fec_inner = FEC_5_6;
993 break;
994 case 9:
995 c->fec_inner = FEC_8_9;
996 break;
997 case 10:
998 c->fec_inner = FEC_9_10;
999 break;
1000 default:
1001 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
1002 __func__);
1003 }
1004
1005 switch ((buf[0] >> 5) & 0x01) {
1006 case 0:
1007 c->pilot = PILOT_OFF;
1008 break;
1009 case 1:
1010 c->pilot = PILOT_ON;
1011 break;
395d00d1
AP		 1012 }
1013
1014 switch ((buf[0] >> 6) & 0x07) {
1015 case 0:
1016 c->modulation = QPSK;
1017 break;
1018 case 1:
1019 c->modulation = PSK_8;
1020 break;
1021 case 2:
1022 c->modulation = APSK_16;
1023 break;
1024 case 3:
1025 c->modulation = APSK_32;
1026 break;
1027 default:
1028 dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n",
1029 __func__);
1030 }
1031
1032 switch ((buf[1] >> 7) & 0x01) {
1033 case 0:
1034 c->inversion = INVERSION_OFF;
1035 break;
1036 case 1:
1037 c->inversion = INVERSION_ON;
1038 break;
395d00d1
AP		 1039 }
1040
1041 switch ((buf[2] >> 0) & 0x03) {
1042 case 0:
1043 c->rolloff = ROLLOFF_35;
1044 break;
1045 case 1:
1046 c->rolloff = ROLLOFF_25;
1047 break;
1048 case 2:
1049 c->rolloff = ROLLOFF_20;
1050 break;
1051 default:
1052 dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n",
1053 __func__);
1054 }
1055 break;
1056 default:
1057 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
1058 __func__);
1059 ret = -EINVAL;
1060 goto err;
1061 }
1062
1063 ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2);
1064 if (ret)
1065 goto err;
1066
1067 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
f4df95bc 1068 priv->mclk_khz * 1000 / 0x10000;
395d00d1
AP		 1069
1070 return 0;
1071err:
1072 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1073 return ret;
1074}
1075
1076static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
1077{
395d00d1 1078 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
41b9aa00 1079
c1daf651
AP		 1080 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
1081 *snr = div_s64(c->cnr.stat[0].svalue, 100);
1082 else
1083 *snr = 0;
395d00d1
AP		 1084
1085 return 0;
395d00d1
AP		 1086}
1087
4423a2ba
AP		 1088static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
1089{
1090 struct m88ds3103_priv *priv = fe->demodulator_priv;
41b9aa00 1091
ce80d713 1092 *ber = priv->dvbv3_ber;
4423a2ba
AP		 1093
1094 return 0;
4423a2ba 1095}
395d00d1
AP		 1096
1097static int m88ds3103_set_tone(struct dvb_frontend *fe,
0df289a2 1098 enum fe_sec_tone_mode fe_sec_tone_mode)
395d00d1
AP		 1099{
1100 struct m88ds3103_priv *priv = fe->demodulator_priv;
1101 int ret;
1102 u8 u8tmp, tone, reg_a1_mask;
41b9aa00 1103
395d00d1
AP		 1104 dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__,
1105 fe_sec_tone_mode);
1106
1107 if (!priv->warm) {
1108 ret = -EAGAIN;
1109 goto err;
1110 }
1111
1112 switch (fe_sec_tone_mode) {
1113 case SEC_TONE_ON:
1114 tone = 0;
418a97cb 1115 reg_a1_mask = 0x47;
395d00d1
AP		 1116 break;
1117 case SEC_TONE_OFF:
1118 tone = 1;
1119 reg_a1_mask = 0x00;
1120 break;
1121 default:
1122 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n",
1123 __func__);
1124 ret = -EINVAL;
1125 goto err;
1126 }
1127
1128 u8tmp = tone << 7 | priv->cfg->envelope_mode << 5;
1129 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1130 if (ret)
1131 goto err;
1132
1133 u8tmp = 1 << 2;
1134 ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask);
1135 if (ret)
1136 goto err;
1137
1138 return 0;
1139err:
1140 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1141 return ret;
1142}
1143
79d09330 1144static int m88ds3103_set_voltage(struct dvb_frontend *fe,
0df289a2 1145 enum fe_sec_voltage fe_sec_voltage)
79d09330 1146{
1147 struct m88ds3103_priv *priv = fe->demodulator_priv;
d28677ff
AP		 1148 int ret;
1149 u8 u8tmp;
1150 bool voltage_sel, voltage_dis;
79d09330 1151
d28677ff
AP		 1152 dev_dbg(&priv->i2c->dev, "%s: fe_sec_voltage=%d\n", __func__,
1153 fe_sec_voltage);
79d09330 1154
d28677ff
AP		 1155 if (!priv->warm) {
1156 ret = -EAGAIN;
1157 goto err;
1158 }
79d09330 1159
d28677ff 1160 switch (fe_sec_voltage) {
79d09330 1161 case SEC_VOLTAGE_18:
afbd6eb4
MCC		 1162 voltage_sel = true;
1163 voltage_dis = false;
79d09330 1164 break;
1165 case SEC_VOLTAGE_13:
afbd6eb4
MCC		 1166 voltage_sel = false;
1167 voltage_dis = false;
79d09330 1168 break;
1169 case SEC_VOLTAGE_OFF:
afbd6eb4
MCC		 1170 voltage_sel = false;
1171 voltage_dis = true;
79d09330 1172 break;
d28677ff
AP		 1173 default:
1174 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_voltage\n",
1175 __func__);
1176 ret = -EINVAL;
1177 goto err;
79d09330 1178 }
d28677ff
AP		 1179
1180 /* output pin polarity */
1181 voltage_sel ^= priv->cfg->lnb_hv_pol;
1182 voltage_dis ^= priv->cfg->lnb_en_pol;
1183
1184 u8tmp = voltage_dis << 1 | voltage_sel << 0;
1185 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0x03);
1186 if (ret)
1187 goto err;
79d09330 1188
1189 return 0;
d28677ff
AP		 1190err:
1191 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1192 return ret;
79d09330 1193}
1194
395d00d1
AP		 1195static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1196 struct dvb_diseqc_master_cmd *diseqc_cmd)
1197{
1198 struct m88ds3103_priv *priv = fe->demodulator_priv;
befa0cc1
AP		 1199 int ret;
1200 unsigned long timeout;
395d00d1 1201 u8 u8tmp;
41b9aa00 1202
395d00d1
AP		 1203 dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__,
1204 diseqc_cmd->msg_len, diseqc_cmd->msg);
1205
1206 if (!priv->warm) {
1207 ret = -EAGAIN;
1208 goto err;
1209 }
1210
1211 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1212 ret = -EINVAL;
1213 goto err;
1214 }
1215
1216 u8tmp = priv->cfg->envelope_mode << 5;
1217 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1218 if (ret)
1219 goto err;
1220
1221 ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg,
1222 diseqc_cmd->msg_len);
1223 if (ret)
1224 goto err;
1225
1226 ret = m88ds3103_wr_reg(priv, 0xa1,
1227 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1228 if (ret)
1229 goto err;
1230
395d00d1 1231 /* wait DiSEqC TX ready */
befa0cc1
AP		 1232 #define SEND_MASTER_CMD_TIMEOUT 120
1233 timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT);
1234
1235 /* DiSEqC message typical period is 54 ms */
1236 usleep_range(50000, 54000);
395d00d1 1237
befa0cc1 1238 for (u8tmp = 1; !time_after(jiffies, timeout) && u8tmp;) {
395d00d1
AP		 1239 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1240 if (ret)
1241 goto err;
1242 }
1243
befa0cc1
AP		 1244 if (u8tmp == 0) {
1245 dev_dbg(&priv->i2c->dev, "%s: diseqc tx took %u ms\n", __func__,
1246 jiffies_to_msecs(jiffies) -
1247 (jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT));
1248 } else {
395d00d1
AP		 1249 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1250
1251 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0);
1252 if (ret)
1253 goto err;
1254 }
1255
1256 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1257 if (ret)
1258 goto err;
1259
befa0cc1 1260 if (u8tmp == 1) {
395d00d1
AP		 1261 ret = -ETIMEDOUT;
1262 goto err;
1263 }
1264
1265 return 0;
1266err:
1267 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1268 return ret;
1269}
1270
1271static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
0df289a2 1272 enum fe_sec_mini_cmd fe_sec_mini_cmd)
395d00d1
AP		 1273{
1274 struct m88ds3103_priv *priv = fe->demodulator_priv;
befa0cc1
AP		 1275 int ret;
1276 unsigned long timeout;
395d00d1 1277 u8 u8tmp, burst;
41b9aa00 1278
395d00d1
AP		 1279 dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__,
1280 fe_sec_mini_cmd);
1281
1282 if (!priv->warm) {
1283 ret = -EAGAIN;
1284 goto err;
1285 }
1286
1287 u8tmp = priv->cfg->envelope_mode << 5;
1288 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1289 if (ret)
1290 goto err;
1291
1292 switch (fe_sec_mini_cmd) {
1293 case SEC_MINI_A:
1294 burst = 0x02;
1295 break;
1296 case SEC_MINI_B:
1297 burst = 0x01;
1298 break;
1299 default:
1300 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n",
1301 __func__);
1302 ret = -EINVAL;
1303 goto err;
1304 }
1305
1306 ret = m88ds3103_wr_reg(priv, 0xa1, burst);
1307 if (ret)
1308 goto err;
1309
395d00d1 1310 /* wait DiSEqC TX ready */
befa0cc1
AP		 1311 #define SEND_BURST_TIMEOUT 40
1312 timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT);
1313
1314 /* DiSEqC ToneBurst period is 12.5 ms */
1315 usleep_range(8500, 12500);
395d00d1 1316
befa0cc1 1317 for (u8tmp = 1; !time_after(jiffies, timeout) && u8tmp;) {
395d00d1
AP		 1318 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1319 if (ret)
1320 goto err;
1321 }
1322
befa0cc1
AP		 1323 if (u8tmp == 0) {
1324 dev_dbg(&priv->i2c->dev, "%s: diseqc tx took %u ms\n", __func__,
1325 jiffies_to_msecs(jiffies) -
1326 (jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT));
1327 } else {
1328 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1329
1330 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0);
1331 if (ret)
1332 goto err;
1333 }
395d00d1
AP		 1334
1335 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1336 if (ret)
1337 goto err;
1338
befa0cc1 1339 if (u8tmp == 1) {
395d00d1
AP		 1340 ret = -ETIMEDOUT;
1341 goto err;
1342 }
1343
1344 return 0;
1345err:
1346 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1347 return ret;
1348}
1349
1350static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1351 struct dvb_frontend_tune_settings *s)
1352{
1353 s->min_delay_ms = 3000;
1354
1355 return 0;
1356}
1357
44b9055b 1358static void m88ds3103_release(struct dvb_frontend *fe)
395d00d1 1359{
44b9055b 1360 struct m88ds3103_priv *priv = fe->demodulator_priv;
f01919e8 1361 struct i2c_client *client = priv->client;
41b9aa00 1362
f01919e8 1363 i2c_unregister_device(client);
395d00d1
AP		 1364}
1365
44b9055b 1366static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
395d00d1 1367{
44b9055b 1368 struct m88ds3103_priv *priv = mux_priv;
395d00d1
AP		 1369 int ret;
1370 struct i2c_msg gate_open_msg[1] = {
1371 {
1372 .addr = priv->cfg->i2c_addr,
1373 .flags = 0,
1374 .len = 2,
1375 .buf = "\x03\x11",
1376 }
1377 };
395d00d1
AP		 1378
1379 mutex_lock(&priv->i2c_mutex);
1380
44b9055b 1381 /* open tuner I2C repeater for 1 xfer, closes automatically */
4fc57876 1382 ret = __i2c_transfer(priv->i2c, gate_open_msg, 1);
395d00d1 1383 if (ret != 1) {
44b9055b 1384 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d\n",
395d00d1 1385 KBUILD_MODNAME, ret);
44b9055b
AP		 1386 if (ret >= 0)
1387 ret = -EREMOTEIO;
395d00d1 1388
44b9055b
AP		 1389 return ret;
1390 }
395d00d1 1391
44b9055b 1392 return 0;
395d00d1
AP		 1393}
1394
44b9055b
AP		 1395static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv,
1396 u32 chan)
395d00d1 1397{
44b9055b
AP		 1398 struct m88ds3103_priv *priv = mux_priv;
1399
1400 mutex_unlock(&priv->i2c_mutex);
1401
1402 return 0;
395d00d1
AP		 1403}
1404
f01919e8
AP		 1405/*
1406 * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide
1407 * proper I2C client for legacy media attach binding.
1408 * New users must use I2C client binding directly!
1409 */
395d00d1
AP		 1410struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1411 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1412{
f01919e8
AP		 1413 struct i2c_client *client;
1414 struct i2c_board_info board_info;
1415 struct m88ds3103_platform_data pdata;
1416
1417 pdata.clk = cfg->clock;
1418 pdata.i2c_wr_max = cfg->i2c_wr_max;
1419 pdata.ts_mode = cfg->ts_mode;
1420 pdata.ts_clk = cfg->ts_clk;
1421 pdata.ts_clk_pol = cfg->ts_clk_pol;
1422 pdata.spec_inv = cfg->spec_inv;
1423 pdata.agc = cfg->agc;
1424 pdata.agc_inv = cfg->agc_inv;
1425 pdata.clk_out = cfg->clock_out;
1426 pdata.envelope_mode = cfg->envelope_mode;
1427 pdata.lnb_hv_pol = cfg->lnb_hv_pol;
1428 pdata.lnb_en_pol = cfg->lnb_en_pol;
1429 pdata.attach_in_use = true;
1430
1431 memset(&board_info, 0, sizeof(board_info));
1432 strlcpy(board_info.type, "m88ds3103", I2C_NAME_SIZE);
1433 board_info.addr = cfg->i2c_addr;
1434 board_info.platform_data = &pdata;
1435 client = i2c_new_device(i2c, &board_info);
1436 if (!client || !client->dev.driver)
1437 return NULL;
1438
1439 *tuner_i2c_adapter = pdata.get_i2c_adapter(client);
1440 return pdata.get_dvb_frontend(client);
1441}
1442EXPORT_SYMBOL(m88ds3103_attach);
1443
1444static struct dvb_frontend_ops m88ds3103_ops = {
1445 .delsys = { SYS_DVBS, SYS_DVBS2 },
1446 .info = {
1447 .name = "Montage M88DS3103",
1448 .frequency_min = 950000,
1449 .frequency_max = 2150000,
1450 .frequency_tolerance = 5000,
1451 .symbol_rate_min = 1000000,
1452 .symbol_rate_max = 45000000,
1453 .caps = FE_CAN_INVERSION_AUTO |
1454 FE_CAN_FEC_1_2 |
1455 FE_CAN_FEC_2_3 |
1456 FE_CAN_FEC_3_4 |
1457 FE_CAN_FEC_4_5 |
1458 FE_CAN_FEC_5_6 |
1459 FE_CAN_FEC_6_7 |
1460 FE_CAN_FEC_7_8 |
1461 FE_CAN_FEC_8_9 |
1462 FE_CAN_FEC_AUTO |
1463 FE_CAN_QPSK |
1464 FE_CAN_RECOVER |
1465 FE_CAN_2G_MODULATION
1466 },
1467
1468 .release = m88ds3103_release,
1469
1470 .get_tune_settings = m88ds3103_get_tune_settings,
1471
1472 .init = m88ds3103_init,
1473 .sleep = m88ds3103_sleep,
1474
1475 .set_frontend = m88ds3103_set_frontend,
1476 .get_frontend = m88ds3103_get_frontend,
1477
1478 .read_status = m88ds3103_read_status,
1479 .read_snr = m88ds3103_read_snr,
1480 .read_ber = m88ds3103_read_ber,
1481
1482 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1483 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1484
1485 .set_tone = m88ds3103_set_tone,
1486 .set_voltage = m88ds3103_set_voltage,
1487};
1488
1489static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client)
1490{
1491 struct m88ds3103_priv *dev = i2c_get_clientdata(client);
1492
1493 dev_dbg(&client->dev, "\n");
1494
1495 return &dev->fe;
1496}
1497
1498static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client)
1499{
1500 struct m88ds3103_priv *dev = i2c_get_clientdata(client);
1501
1502 dev_dbg(&client->dev, "\n");
1503
1504 return dev->i2c_adapter;
1505}
1506
1507static int m88ds3103_probe(struct i2c_client *client,
1508 const struct i2c_device_id *id)
1509{
1510 struct m88ds3103_priv *dev;
1511 struct m88ds3103_platform_data *pdata = client->dev.platform_data;
395d00d1 1512 int ret;
395d00d1
AP		 1513 u8 chip_id, u8tmp;
1514
f01919e8
AP		 1515 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1516 if (!dev) {
395d00d1 1517 ret = -ENOMEM;
395d00d1
AP		 1518 goto err;
1519 }
1520
f01919e8
AP		 1521 dev->client = client;
1522 dev->i2c = client->adapter;
1523 dev->config.i2c_addr = client->addr;
1524 dev->config.clock = pdata->clk;
1525 dev->config.i2c_wr_max = pdata->i2c_wr_max;
1526 dev->config.ts_mode = pdata->ts_mode;
1527 dev->config.ts_clk = pdata->ts_clk;
1528 dev->config.ts_clk_pol = pdata->ts_clk_pol;
1529 dev->config.spec_inv = pdata->spec_inv;
1530 dev->config.agc_inv = pdata->agc_inv;
1531 dev->config.clock_out = pdata->clk_out;
1532 dev->config.envelope_mode = pdata->envelope_mode;
1533 dev->config.agc = pdata->agc;
1534 dev->config.lnb_hv_pol = pdata->lnb_hv_pol;
1535 dev->config.lnb_en_pol = pdata->lnb_en_pol;
1536 dev->cfg = &dev->config;
1537 mutex_init(&dev->i2c_mutex);
395d00d1 1538
f4df95bc 1539 /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */
f01919e8 1540 ret = m88ds3103_rd_reg(dev, 0x00, &chip_id);
395d00d1 1541 if (ret)
f01919e8 1542 goto err_kfree;
395d00d1 1543
f4df95bc 1544 chip_id >>= 1;
f01919e8 1545 dev_dbg(&client->dev, "chip_id=%02x\n", chip_id);
395d00d1
AP		 1546
1547 switch (chip_id) {
f4df95bc 1548 case M88RS6000_CHIP_ID:
1549 case M88DS3103_CHIP_ID:
395d00d1
AP		 1550 break;
1551 default:
f01919e8 1552 goto err_kfree;
395d00d1 1553 }
f01919e8 1554 dev->chip_id = chip_id;
395d00d1 1555
f01919e8 1556 switch (dev->cfg->clock_out) {
395d00d1
AP		 1557 case M88DS3103_CLOCK_OUT_DISABLED:
1558 u8tmp = 0x80;
1559 break;
1560 case M88DS3103_CLOCK_OUT_ENABLED:
1561 u8tmp = 0x00;
1562 break;
1563 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1564 u8tmp = 0x10;
1565 break;
1566 default:
4347df6a 1567 ret = -EINVAL;
f01919e8 1568 goto err_kfree;
395d00d1
AP		 1569 }
1570
f4df95bc 1571 /* 0x29 register is defined differently for m88rs6000. */
1572 /* set internal tuner address to 0x21 */
1573 if (chip_id == M88RS6000_CHIP_ID)
1574 u8tmp = 0x00;
1575
f01919e8 1576 ret = m88ds3103_wr_reg(dev, 0x29, u8tmp);
395d00d1 1577 if (ret)
f01919e8 1578 goto err_kfree;
395d00d1
AP		 1579
1580 /* sleep */
f01919e8 1581 ret = m88ds3103_wr_reg_mask(dev, 0x08, 0x00, 0x01);
395d00d1 1582 if (ret)
f01919e8
AP		 1583 goto err_kfree;
1584 ret = m88ds3103_wr_reg_mask(dev, 0x04, 0x01, 0x01);
395d00d1 1585 if (ret)
f01919e8
AP		 1586 goto err_kfree;
1587 ret = m88ds3103_wr_reg_mask(dev, 0x23, 0x10, 0x10);
395d00d1 1588 if (ret)
f01919e8 1589 goto err_kfree;
395d00d1 1590
44b9055b 1591 /* create mux i2c adapter for tuner */
f01919e8
AP		 1592 dev->i2c_adapter = i2c_add_mux_adapter(client->adapter, &client->dev,
1593 dev, 0, 0, 0, m88ds3103_select,
1594 m88ds3103_deselect);
4347df6a
DC		 1595 if (dev->i2c_adapter == NULL) {
1596 ret = -ENOMEM;
f01919e8 1597 goto err_kfree;
4347df6a 1598 }
44b9055b 1599
395d00d1 1600 /* create dvb_frontend */
f01919e8
AP		 1601 memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1602 if (dev->chip_id == M88RS6000_CHIP_ID)
1603 strncpy(dev->fe.ops.info.name,
1604 "Montage M88RS6000", sizeof(dev->fe.ops.info.name));
1605 if (!pdata->attach_in_use)
1606 dev->fe.ops.release = NULL;
1607 dev->fe.demodulator_priv = dev;
1608 i2c_set_clientdata(client, dev);
1609
1610 /* setup callbacks */
1611 pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend;
1612 pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter;
1613 return 0;
1614err_kfree:
1615 kfree(dev);
395d00d1 1616err:
f01919e8
AP		 1617 dev_dbg(&client->dev, "failed=%d\n", ret);
1618 return ret;
395d00d1 1619}
395d00d1 1620
f01919e8
AP		 1621static int m88ds3103_remove(struct i2c_client *client)
1622{
1623 struct m88ds3103_priv *dev = i2c_get_clientdata(client);
395d00d1 1624
f01919e8 1625 dev_dbg(&client->dev, "\n");
395d00d1 1626
f01919e8 1627 i2c_del_mux_adapter(dev->i2c_adapter);
395d00d1 1628
f01919e8
AP		 1629 kfree(dev);
1630 return 0;
1631}
395d00d1 1632
f01919e8
AP		 1633static const struct i2c_device_id m88ds3103_id_table[] = {
1634 {"m88ds3103", 0},
1635 {}
1636};
1637MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table);
395d00d1 1638
f01919e8
AP		 1639static struct i2c_driver m88ds3103_driver = {
1640 .driver = {
1641 .owner = THIS_MODULE,
1642 .name = "m88ds3103",
1643 .suppress_bind_attrs = true,
1644 },
1645 .probe = m88ds3103_probe,
1646 .remove = m88ds3103_remove,
1647 .id_table = m88ds3103_id_table,
395d00d1
AP		 1648};
1649
f01919e8
AP		 1650module_i2c_driver(m88ds3103_driver);
1651
395d00d1
AP		 1652MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1653MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver");
1654MODULE_LICENSE("GPL");
1655MODULE_FIRMWARE(M88DS3103_FIRMWARE);
f4df95bc 1656MODULE_FIRMWARE(M88RS6000_FIRMWARE);
Linux 6.x block layer and io_uring tree(s)