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[media] dvb: Get rid of typedev usage for enums
[linux-2.6-block.git] / drivers / media / dvb-frontends / drxd_hard.c
CommitLineData
126f1e61
RM		 1/*
2 * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
3 *
4 * Copyright (C) 2003-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/firmware.h>
30#include <linux/i2c.h>
126f1e61
RM		 31#include <asm/div64.h>
32
33#include "dvb_frontend.h"
34#include "drxd.h"
35#include "drxd_firm.h"
36
8f19f27e
DH		 37#define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
38#define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
39
126f1e61
RM		 40#define CHUNK_SIZE 48
41
42#define DRX_I2C_RMW 0x10
43#define DRX_I2C_BROADCAST 0x20
44#define DRX_I2C_CLEARCRC 0x80
45#define DRX_I2C_SINGLE_MASTER 0xC0
46#define DRX_I2C_MODEFLAGS 0xC0
47#define DRX_I2C_FLAGS 0xF0
48
126f1e61
RM		 49#define DEFAULT_LOCK_TIMEOUT 1100
50
51#define DRX_CHANNEL_AUTO 0
52#define DRX_CHANNEL_HIGH 1
53#define DRX_CHANNEL_LOW 2
54
55#define DRX_LOCK_MPEG 1
56#define DRX_LOCK_FEC 2
57#define DRX_LOCK_DEMOD 4
58
126f1e61
RM		 59/****************************************************************************/
60
61enum CSCDState {
62 CSCD_INIT = 0,
63 CSCD_SET,
64 CSCD_SAVED
65};
66
67enum CDrxdState {
68 DRXD_UNINITIALIZED = 0,
69 DRXD_STOPPED,
70 DRXD_STARTED
71};
72
73enum AGC_CTRL_MODE {
74 AGC_CTRL_AUTO = 0,
75 AGC_CTRL_USER,
76 AGC_CTRL_OFF
77};
78
79enum OperationMode {
80 OM_Default,
81 OM_DVBT_Diversity_Front,
82 OM_DVBT_Diversity_End
83};
84
85struct SCfgAgc {
86 enum AGC_CTRL_MODE ctrlMode;
6cacdd46
DH		 87 u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
88 u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
89 u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
90 u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
91 u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
126f1e61
RM		 92
93 u16 R1;
94 u16 R2;
95 u16 R3;
96};
97
98struct SNoiseCal {
99 int cpOpt;
3caaa201
SN		 100 short cpNexpOfs;
101 short tdCal2k;
102 short tdCal8k;
126f1e61
RM		 103};
104
105enum app_env {
106 APPENV_STATIC = 0,
107 APPENV_PORTABLE = 1,
6cacdd46 108 APPENV_MOBILE = 2
126f1e61
RM		 109};
110
111enum EIFFilter {
112 IFFILTER_SAW = 0,
113 IFFILTER_DISCRETE = 1
114};
115
116struct drxd_state {
117 struct dvb_frontend frontend;
118 struct dvb_frontend_ops ops;
9f97c288 119 struct dtv_frontend_properties props;
126f1e61
RM		 120
121 const struct firmware *fw;
122 struct device *dev;
123
124 struct i2c_adapter *i2c;
125 void *priv;
126 struct drxd_config config;
127
128 int i2c_access;
129 int init_done;
834751d4 130 struct mutex mutex;
126f1e61 131
6cacdd46 132 u8 chip_adr;
126f1e61
RM		 133 u16 hi_cfg_timing_div;
134 u16 hi_cfg_bridge_delay;
135 u16 hi_cfg_wakeup_key;
136 u16 hi_cfg_ctrl;
137
138 u16 intermediate_freq;
139 u16 osc_clock_freq;
140
141 enum CSCDState cscd_state;
142 enum CDrxdState drxd_state;
143
144 u16 sys_clock_freq;
145 s16 osc_clock_deviation;
146 u16 expected_sys_clock_freq;
147
148 u16 insert_rs_byte;
149 u16 enable_parallel;
150
151 int operation_mode;
152
153 struct SCfgAgc if_agc_cfg;
154 struct SCfgAgc rf_agc_cfg;
155
156 struct SNoiseCal noise_cal;
157
158 u32 fe_fs_add_incr;
159 u32 org_fe_fs_add_incr;
160 u16 current_fe_if_incr;
161
162 u16 m_FeAgRegAgPwd;
163 u16 m_FeAgRegAgAgcSio;
164
165 u16 m_EcOcRegOcModeLop;
166 u16 m_EcOcRegSncSncLvl;
167 u8 *m_InitAtomicRead;
168 u8 *m_HiI2cPatch;
169
170 u8 *m_ResetCEFR;
171 u8 *m_InitFE_1;
172 u8 *m_InitFE_2;
173 u8 *m_InitCP;
174 u8 *m_InitCE;
175 u8 *m_InitEQ;
176 u8 *m_InitSC;
177 u8 *m_InitEC;
178 u8 *m_ResetECRAM;
179 u8 *m_InitDiversityFront;
180 u8 *m_InitDiversityEnd;
181 u8 *m_DisableDiversity;
182 u8 *m_StartDiversityFront;
183 u8 *m_StartDiversityEnd;
184
185 u8 *m_DiversityDelay8MHZ;
186 u8 *m_DiversityDelay6MHZ;
187
188 u8 *microcode;
189 u32 microcode_length;
190
191 int type_A;
192 int PGA;
193 int diversity;
194 int tuner_mirrors;
195
196 enum app_env app_env_default;
197 enum app_env app_env_diversity;
198
199};
200
126f1e61
RM		 201/****************************************************************************/
202/* I2C **********************************************************************/
203/****************************************************************************/
204
6cacdd46 205static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
126f1e61 206{
9999daf4 207 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
126f1e61
RM		 208
209 if (i2c_transfer(adap, &msg, 1) != 1)
210 return -1;
211 return 0;
212}
213
214static int i2c_read(struct i2c_adapter *adap,
9999daf4 215 u8 adr, u8 *msg, int len, u8 *answ, int alen)
126f1e61 216{
9999daf4
MCC		 217 struct i2c_msg msgs[2] = {
218 {
219 .addr = adr, .flags = 0,
220 .buf = msg, .len = len
221 }, {
222 .addr = adr, .flags = I2C_M_RD,
223 .buf = answ, .len = alen
224 }
6cacdd46 225 };
126f1e61
RM		 226 if (i2c_transfer(adap, msgs, 2) != 2)
227 return -1;
228 return 0;
229}
230
b01fbc10 231static inline u32 MulDiv32(u32 a, u32 b, u32 c)
126f1e61
RM		 232{
233 u64 tmp64;
234
9999daf4 235 tmp64 = (u64)a * (u64)b;
126f1e61
RM		 236 do_div(tmp64, c);
237
238 return (u32) tmp64;
239}
240
9999daf4 241static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
126f1e61 242{
6cacdd46
DH		 243 u8 adr = state->config.demod_address;
244 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
245 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
246 };
126f1e61 247 u8 mm2[2];
6cacdd46 248 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
126f1e61
RM		 249 return -1;
250 if (data)
6cacdd46
DH		 251 *data = mm2[0] | (mm2[1] << 8);
252 return mm2[0] | (mm2[1] << 8);
126f1e61
RM		 253}
254
9999daf4 255static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
126f1e61 256{
6cacdd46
DH		 257 u8 adr = state->config.demod_address;
258 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
259 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
260 };
126f1e61
RM		 261 u8 mm2[4];
262
6cacdd46 263 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
126f1e61
RM		 264 return -1;
265 if (data)
6cacdd46
DH		 266 *data =
267 mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
126f1e61
RM		 268 return 0;
269}
270
271static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
272{
6cacdd46
DH		 273 u8 adr = state->config.demod_address;
274 u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
275 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
276 data & 0xff, (data >> 8) & 0xff
277 };
126f1e61 278
6cacdd46 279 if (i2c_write(state->i2c, adr, mm, 6) < 0)
126f1e61
RM		 280 return -1;
281 return 0;
282}
283
284static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
285{
6cacdd46
DH		 286 u8 adr = state->config.demod_address;
287 u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
288 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
289 data & 0xff, (data >> 8) & 0xff,
290 (data >> 16) & 0xff, (data >> 24) & 0xff
291 };
126f1e61 292
6cacdd46 293 if (i2c_write(state->i2c, adr, mm, 8) < 0)
126f1e61
RM		 294 return -1;
295 return 0;
296}
297
298static int write_chunk(struct drxd_state *state,
9999daf4 299 u32 reg, u8 *data, u32 len, u8 flags)
126f1e61 300{
6cacdd46
DH		 301 u8 adr = state->config.demod_address;
302 u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
303 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
304 };
126f1e61
RM		 305 int i;
306
6cacdd46
DH		 307 for (i = 0; i < len; i++)
308 mm[4 + i] = data[i];
309 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
9999daf4 310 printk(KERN_ERR "error in write_chunk\n");
126f1e61
RM		 311 return -1;
312 }
313 return 0;
314}
315
316static int WriteBlock(struct drxd_state *state,
9999daf4 317 u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
126f1e61 318{
6cacdd46 319 while (BlockSize > 0) {
126f1e61
RM		 320 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
321
6cacdd46 322 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
126f1e61
RM		 323 return -1;
324 pBlock += Chunk;
325 Address += (Chunk >> 1);
326 BlockSize -= Chunk;
327 }
328 return 0;
329}
330
6cacdd46 331static int WriteTable(struct drxd_state *state, u8 * pTable)
126f1e61
RM		 332{
333 int status = 0;
334
6cacdd46 335 if (pTable == NULL)
126f1e61
RM		 336 return 0;
337
6cacdd46 338 while (!status) {
126f1e61 339 u16 Length;
6cacdd46
DH		 340 u32 Address = pTable[0] | (pTable[1] << 8) |
341 (pTable[2] << 16) | (pTable[3] << 24);
126f1e61 342
6cacdd46 343 if (Address == 0xFFFFFFFF)
126f1e61
RM		 344 break;
345 pTable += sizeof(u32);
346
6cacdd46 347 Length = pTable[0] | (pTable[1] << 8);
126f1e61
RM		 348 pTable += sizeof(u16);
349 if (!Length)
350 break;
6cacdd46
DH		 351 status = WriteBlock(state, Address, Length * 2, pTable, 0);
352 pTable += (Length * 2);
126f1e61
RM		 353 }
354 return status;
355}
356
126f1e61
RM		 357/****************************************************************************/
358/****************************************************************************/
359/****************************************************************************/
360
361static int ResetCEFR(struct drxd_state *state)
362{
363 return WriteTable(state, state->m_ResetCEFR);
364}
365
366static int InitCP(struct drxd_state *state)
367{
368 return WriteTable(state, state->m_InitCP);
369}
370
371static int InitCE(struct drxd_state *state)
372{
373 int status;
374 enum app_env AppEnv = state->app_env_default;
375
376 do {
58d5eaec
MCC		 377 status = WriteTable(state, state->m_InitCE);
378 if (status < 0)
379 break;
126f1e61
RM		 380
381 if (state->operation_mode == OM_DVBT_Diversity_Front ||
6cacdd46 382 state->operation_mode == OM_DVBT_Diversity_End) {
126f1e61
RM		 383 AppEnv = state->app_env_diversity;
384 }
6cacdd46 385 if (AppEnv == APPENV_STATIC) {
58d5eaec
MCC		 386 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
387 if (status < 0)
388 break;
6cacdd46 389 } else if (AppEnv == APPENV_PORTABLE) {
58d5eaec
MCC		 390 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
391 if (status < 0)
392 break;
6cacdd46 393 } else if (AppEnv == APPENV_MOBILE && state->type_A) {
58d5eaec
MCC		 394 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
395 if (status < 0)
396 break;
6cacdd46 397 } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
58d5eaec
MCC		 398 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
399 if (status < 0)
400 break;
126f1e61
RM		 401 }
402
403 /* start ce */
58d5eaec
MCC		 404 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
405 if (status < 0)
406 break;
6cacdd46 407 } while (0);
126f1e61
RM		 408 return status;
409}
410
411static int StopOC(struct drxd_state *state)
412{
413 int status = 0;
6cacdd46
DH		 414 u16 ocSyncLvl = 0;
415 u16 ocModeLop = state->m_EcOcRegOcModeLop;
416 u16 dtoIncLop = 0;
417 u16 dtoIncHip = 0;
126f1e61
RM		 418
419 do {
420 /* Store output configuration */
58d5eaec
MCC		 421 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
422 if (status < 0)
9999daf4 423 break;
58d5eaec 424 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
126f1e61
RM		 425 state->m_EcOcRegSncSncLvl = ocSyncLvl;
426 /* m_EcOcRegOcModeLop = ocModeLop; */
427
428 /* Flush FIFO (byte-boundary) at fixed rate */
58d5eaec
MCC		 429 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
430 if (status < 0)
431 break;
432 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
433 if (status < 0)
434 break;
435 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
436 if (status < 0)
437 break;
438 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
439 if (status < 0)
440 break;
126f1e61 441 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
6cacdd46 442 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
58d5eaec
MCC		 443 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
444 if (status < 0)
445 break;
446 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
447 if (status < 0)
448 break;
126f1e61
RM		 449
450 msleep(1);
451 /* Output pins to '0' */
58d5eaec
MCC		 452 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
453 if (status < 0)
454 break;
126f1e61
RM		 455
456 /* Force the OC out of sync */
457 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
58d5eaec
MCC		 458 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
459 if (status < 0)
460 break;
126f1e61 461 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
6cacdd46
DH		 462 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
463 ocModeLop |= 0x2; /* Magically-out-of-sync */
58d5eaec
MCC		 464 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
465 if (status < 0)
466 break;
467 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
468 if (status < 0)
469 break;
470 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
471 if (status < 0)
472 break;
6cacdd46 473 } while (0);
126f1e61
RM		 474
475 return status;
476}
477
478static int StartOC(struct drxd_state *state)
479{
6cacdd46 480 int status = 0;
126f1e61
RM		 481
482 do {
483 /* Stop OC */
58d5eaec
MCC		 484 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
485 if (status < 0)
486 break;
126f1e61
RM		 487
488 /* Restore output configuration */
58d5eaec
MCC		 489 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
490 if (status < 0)
491 break;
492 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
493 if (status < 0)
494 break;
126f1e61
RM		 495
496 /* Output pins active again */
58d5eaec
MCC		 497 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
498 if (status < 0)
499 break;
126f1e61
RM		 500
501 /* Start OC */
58d5eaec
MCC		 502 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
503 if (status < 0)
504 break;
6cacdd46 505 } while (0);
126f1e61
RM		 506 return status;
507}
508
509static int InitEQ(struct drxd_state *state)
510{
511 return WriteTable(state, state->m_InitEQ);
512}
513
514static int InitEC(struct drxd_state *state)
515{
516 return WriteTable(state, state->m_InitEC);
517}
518
519static int InitSC(struct drxd_state *state)
520{
521 return WriteTable(state, state->m_InitSC);
522}
523
524static int InitAtomicRead(struct drxd_state *state)
525{
526 return WriteTable(state, state->m_InitAtomicRead);
527}
528
529static int CorrectSysClockDeviation(struct drxd_state *state);
530
6cacdd46 531static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
126f1e61
RM		 532{
533 u16 ScRaRamLock = 0;
6cacdd46
DH		 534 const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
535 SC_RA_RAM_LOCK_FEC__M |
536 SC_RA_RAM_LOCK_DEMOD__M);
537 const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
538 SC_RA_RAM_LOCK_DEMOD__M);
539 const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
126f1e61
RM		 540
541 int status;
542
6cacdd46 543 *pLockStatus = 0;
126f1e61 544
6cacdd46
DH		 545 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
546 if (status < 0) {
9999daf4 547 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
126f1e61
RM		 548 return status;
549 }
550
6cacdd46 551 if (state->drxd_state != DRXD_STARTED)
126f1e61
RM		 552 return 0;
553
6cacdd46
DH		 554 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
555 *pLockStatus |= DRX_LOCK_MPEG;
126f1e61
RM		 556 CorrectSysClockDeviation(state);
557 }
558
6cacdd46
DH		 559 if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
560 *pLockStatus |= DRX_LOCK_FEC;
126f1e61 561
6cacdd46
DH		 562 if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
563 *pLockStatus |= DRX_LOCK_DEMOD;
126f1e61
RM		 564 return 0;
565}
566
567/****************************************************************************/
568
569static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
570{
571 int status;
572
6cacdd46
DH		 573 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
574 return -1;
126f1e61 575
6cacdd46 576 if (cfg->ctrlMode == AGC_CTRL_USER) {
126f1e61
RM		 577 do {
578 u16 FeAgRegPm1AgcWri;
579 u16 FeAgRegAgModeLop;
580
58d5eaec
MCC		 581 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
582 if (status < 0)
583 break;
6cacdd46
DH		 584 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
585 FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
58d5eaec
MCC		 586 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
587 if (status < 0)
588 break;
6cacdd46
DH		 589
590 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
591 FE_AG_REG_PM1_AGC_WRI__M);
58d5eaec
MCC		 592 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
593 if (status < 0)
594 break;
9999daf4 595 } while (0);
6cacdd46
DH		 596 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
597 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
598 ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
599 ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
600 ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
601 )
9999daf4 602 return -1;
126f1e61
RM		 603 do {
604 u16 FeAgRegAgModeLop;
605 u16 FeAgRegEgcSetLvl;
606 u16 slope, offset;
607
608 /* == Mode == */
609
58d5eaec
MCC		 610 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
611 if (status < 0)
612 break;
6cacdd46 613 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
126f1e61 614 FeAgRegAgModeLop |=
6cacdd46 615 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
58d5eaec
MCC		 616 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
617 if (status < 0)
618 break;
126f1e61
RM		 619
620 /* == Settle level == */
621
6cacdd46
DH		 622 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
623 FE_AG_REG_EGC_SET_LVL__M);
58d5eaec
MCC		 624 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
625 if (status < 0)
626 break;
126f1e61
RM		 627
628 /* == Min/Max == */
629
6cacdd46
DH		 630 slope = (u16) ((cfg->maxOutputLevel -
631 cfg->minOutputLevel) / 2);
632 offset = (u16) ((cfg->maxOutputLevel +
633 cfg->minOutputLevel) / 2 - 511);
126f1e61 634
58d5eaec
MCC		 635 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
636 if (status < 0)
637 break;
638 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
639 if (status < 0)
640 break;
126f1e61
RM		 641
642 /* == Speed == */
643 {
644 const u16 maxRur = 8;
6cacdd46
DH		 645 const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 };
646 const u16 fastIncrDecLUT[] = { 14, 15, 15, 16,
647 17, 18, 18, 19,
648 20, 21, 22, 23,
649 24, 26, 27, 28,
650 29, 31
651 };
652
653 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
654 (maxRur + 1);
655 u16 fineSpeed = (u16) (cfg->speed -
656 ((cfg->speed /
657 fineSteps) *
126f1e61 658 fineSteps));
6cacdd46
DH		 659 u16 invRurCount = (u16) (cfg->speed /
660 fineSteps);
126f1e61 661 u16 rurCount;
6cacdd46
DH		 662 if (invRurCount > maxRur) {
663 rurCount = 0;
126f1e61
RM		 664 fineSpeed += fineSteps;
665 } else {
6cacdd46 666 rurCount = maxRur - invRurCount;
126f1e61
RM		 667 }
668
669 /*
6cacdd46
DH		 670 fastInc = default *
671 (2^(fineSpeed/fineSteps))
672 => range[default...2*default>
673 slowInc = default *
674 (2^(fineSpeed/fineSteps))
675 */
126f1e61
RM		 676 {
677 u16 fastIncrDec =
6cacdd46
DH		 678 fastIncrDecLUT[fineSpeed /
679 ((fineSteps /
680 (14 + 1)) + 1)];
681 u16 slowIncrDec =
682 slowIncrDecLUT[fineSpeed /
683 (fineSteps /
684 (3 + 1))];
126f1e61 685
58d5eaec
MCC		 686 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
687 if (status < 0)
688 break;
689 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
690 if (status < 0)
691 break;
692 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
693 if (status < 0)
694 break;
695 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
696 if (status < 0)
697 break;
698 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
699 if (status < 0)
700 break;
126f1e61
RM		 701 }
702 }
6cacdd46 703 } while (0);
126f1e61
RM		 704
705 } else {
706 /* No OFF mode for IF control */
9999daf4 707 return -1;
126f1e61
RM		 708 }
709 return status;
710}
711
126f1e61
RM		 712static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
713{
714 int status = 0;
715
6cacdd46 716 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
126f1e61
RM		 717 return -1;
718
6cacdd46 719 if (cfg->ctrlMode == AGC_CTRL_USER) {
126f1e61 720 do {
6cacdd46
DH		 721 u16 AgModeLop = 0;
722 u16 level = (cfg->outputLevel);
126f1e61 723
6cacdd46 724 if (level == DRXD_FE_CTRL_MAX)
126f1e61
RM		 725 level++;
726
58d5eaec
MCC		 727 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
728 if (status < 0)
729 break;
126f1e61
RM		 730
731 /*==== Mode ====*/
732
733 /* Powerdown PD2, WRI source */
6cacdd46 734 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
126f1e61 735 state->m_FeAgRegAgPwd |=
6cacdd46 736 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
58d5eaec
MCC		 737 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
738 if (status < 0)
739 break;
126f1e61 740
58d5eaec
MCC		 741 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
742 if (status < 0)
743 break;
6cacdd46
DH		 744 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
745 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
746 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
747 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
58d5eaec
MCC		 748 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
749 if (status < 0)
750 break;
126f1e61
RM		 751
752 /* enable AGC2 pin */
753 {
754 u16 FeAgRegAgAgcSio = 0;
58d5eaec
MCC		 755 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
756 if (status < 0)
757 break;
126f1e61 758 FeAgRegAgAgcSio &=
6cacdd46 759 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
126f1e61 760 FeAgRegAgAgcSio |=
6cacdd46 761 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
58d5eaec
MCC		 762 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
763 if (status < 0)
764 break;
126f1e61
RM		 765 }
766
6cacdd46
DH		 767 } while (0);
768 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
769 u16 AgModeLop = 0;
126f1e61
RM		 770
771 do {
772 u16 level;
773 /* Automatic control */
774 /* Powerup PD2, AGC2 as output, TGC source */
775 (state->m_FeAgRegAgPwd) &=
6cacdd46 776 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
126f1e61 777 (state->m_FeAgRegAgPwd) |=
6cacdd46 778 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
58d5eaec
MCC		 779 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
780 if (status < 0)
781 break;
6cacdd46 782
58d5eaec
MCC		 783 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
784 if (status < 0)
785 break;
6cacdd46
DH		 786 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
787 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
788 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
789 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
58d5eaec
MCC		 790 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
791 if (status < 0)
792 break;
126f1e61 793 /* Settle level */
6cacdd46
DH		 794 level = (((cfg->settleLevel) >> 4) &
795 FE_AG_REG_TGC_SET_LVL__M);
58d5eaec
MCC		 796 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
797 if (status < 0)
798 break;
126f1e61
RM		 799
800 /* Min/max: don't care */
801
802 /* Speed: TODO */
803
804 /* enable AGC2 pin */
805 {
806 u16 FeAgRegAgAgcSio = 0;
58d5eaec
MCC		 807 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
808 if (status < 0)
809 break;
126f1e61 810 FeAgRegAgAgcSio &=
6cacdd46 811 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
126f1e61 812 FeAgRegAgAgcSio |=
6cacdd46 813 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
58d5eaec
MCC		 814 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
815 if (status < 0)
816 break;
126f1e61
RM		 817 }
818
6cacdd46 819 } while (0);
126f1e61 820 } else {
6cacdd46 821 u16 AgModeLop = 0;
126f1e61
RM		 822
823 do {
824 /* No RF AGC control */
825 /* Powerdown PD2, AGC2 as output, WRI source */
826 (state->m_FeAgRegAgPwd) &=
6cacdd46 827 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
126f1e61 828 (state->m_FeAgRegAgPwd) |=
6cacdd46 829 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
58d5eaec
MCC		 830 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
831 if (status < 0)
832 break;
126f1e61 833
58d5eaec
MCC		 834 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
835 if (status < 0)
836 break;
6cacdd46
DH		 837 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
838 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
839 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
840 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
58d5eaec
MCC		 841 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
842 if (status < 0)
843 break;
126f1e61
RM		 844
845 /* set FeAgRegAgAgcSio AGC2 (RF) as input */
846 {
847 u16 FeAgRegAgAgcSio = 0;
58d5eaec
MCC		 848 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
849 if (status < 0)
850 break;
126f1e61 851 FeAgRegAgAgcSio &=
6cacdd46 852 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
126f1e61 853 FeAgRegAgAgcSio |=
6cacdd46 854 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
58d5eaec
MCC		 855 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
856 if (status < 0)
857 break;
126f1e61 858 }
6cacdd46 859 } while (0);
126f1e61
RM		 860 }
861 return status;
862}
863
6cacdd46 864static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
126f1e61
RM		 865{
866 int status = 0;
867
868 *pValue = 0;
6cacdd46 869 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
126f1e61 870 u16 Value;
6cacdd46 871 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
126f1e61 872 Value &= FE_AG_REG_GC1_AGC_DAT__M;
6cacdd46 873 if (status >= 0) {
126f1e61 874 /* 3.3V
6cacdd46
DH		 875 |
876 R1
877 |
126f1e61 878 Vin - R3 - * -- Vout
6cacdd46
DH		 879 |
880 R2
881 |
882 GND
883 */
126f1e61
RM		 884 u32 R1 = state->if_agc_cfg.R1;
885 u32 R2 = state->if_agc_cfg.R2;
886 u32 R3 = state->if_agc_cfg.R3;
887
f8a26f05
ES		 888 u32 Vmax, Rpar, Vmin, Vout;
889
890 if (R2 == 0 && (R1 == 0 || R3 == 0))
891 return 0;
892
893 Vmax = (3300 * R2) / (R1 + R2);
894 Rpar = (R2 * R3) / (R3 + R2);
895 Vmin = (3300 * Rpar) / (R1 + Rpar);
896 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
126f1e61
RM		 897
898 *pValue = Vout;
899 }
900 }
901 return status;
902}
903
8f19f27e
DH		 904static int load_firmware(struct drxd_state *state, const char *fw_name)
905{
906 const struct firmware *fw;
907
908 if (request_firmware(&fw, fw_name, state->dev) < 0) {
909 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
910 return -EIO;
911 }
912
53090aad 913 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL);
8f19f27e 914 if (state->microcode == NULL) {
8afe9119
JJ		 915 release_firmware(fw);
916 printk(KERN_ERR "drxd: firmware load failure: no memory\n");
8f19f27e
DH		 917 return -ENOMEM;
918 }
919
8f19f27e 920 state->microcode_length = fw->size;
8afe9119 921 release_firmware(fw);
8f19f27e
DH		 922 return 0;
923}
924
126f1e61 925static int DownloadMicrocode(struct drxd_state *state,
9999daf4 926 const u8 *pMCImage, u32 Length)
126f1e61
RM		 927{
928 u8 *pSrc;
126f1e61
RM		 929 u32 Address;
930 u16 nBlocks;
931 u16 BlockSize;
6cacdd46
DH		 932 u32 offset = 0;
933 int i, status = 0;
126f1e61 934
6cacdd46 935 pSrc = (u8 *) pMCImage;
23aefb7e
HV		 936 /* We're not using Flags */
937 /* Flags = (pSrc[0] << 8) | pSrc[1]; */
6cacdd46
DH		 938 pSrc += sizeof(u16);
939 offset += sizeof(u16);
126f1e61 940 nBlocks = (pSrc[0] << 8) | pSrc[1];
6cacdd46
DH		 941 pSrc += sizeof(u16);
942 offset += sizeof(u16);
126f1e61 943
6cacdd46
DH		 944 for (i = 0; i < nBlocks; i++) {
945 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
946 (pSrc[2] << 8) | pSrc[3];
947 pSrc += sizeof(u32);
948 offset += sizeof(u32);
126f1e61 949
6cacdd46
DH		 950 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
951 pSrc += sizeof(u16);
952 offset += sizeof(u16);
126f1e61 953
23aefb7e
HV		 954 /* We're not using Flags */
955 /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */
6cacdd46
DH		 956 pSrc += sizeof(u16);
957 offset += sizeof(u16);
126f1e61 958
23aefb7e
HV		 959 /* We're not using BlockCRC */
960 /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */
6cacdd46
DH		 961 pSrc += sizeof(u16);
962 offset += sizeof(u16);
126f1e61 963
6cacdd46
DH		 964 status = WriteBlock(state, Address, BlockSize,
965 pSrc, DRX_I2C_CLEARCRC);
966 if (status < 0)
126f1e61
RM		 967 break;
968 pSrc += BlockSize;
969 offset += BlockSize;
970 }
971
972 return status;
973}
974
6cacdd46 975static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
126f1e61
RM		 976{
977 u32 nrRetries = 0;
978 u16 waitCmd;
979 int status;
980
9999daf4
MCC		 981 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
982 if (status < 0)
126f1e61
RM		 983 return status;
984
985 do {
6cacdd46
DH		 986 nrRetries += 1;
987 if (nrRetries > DRXD_MAX_RETRIES) {
988 status = -1;
126f1e61 989 break;
c2c1b415 990 }
6cacdd46
DH		 991 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
992 } while (waitCmd != 0);
126f1e61 993
6cacdd46
DH		 994 if (status >= 0)
995 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
126f1e61
RM		 996 return status;
997}
998
999static int HI_CfgCommand(struct drxd_state *state)
1000{
6cacdd46 1001 int status = 0;
126f1e61 1002
834751d4 1003 mutex_lock(&state->mutex);
6cacdd46 1004 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
126f1e61 1005 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
6cacdd46 1006 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
126f1e61
RM		 1007 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
1008 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
1009
6cacdd46 1010 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
126f1e61 1011
6cacdd46 1012 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
126f1e61 1013 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
6cacdd46
DH		 1014 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
1015 HI_RA_RAM_SRV_CMD_CONFIG, 0);
126f1e61 1016 else
843e44a1 1017 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL);
834751d4 1018 mutex_unlock(&state->mutex);
126f1e61
RM		 1019 return status;
1020}
1021
1022static int InitHI(struct drxd_state *state)
1023{
1024 state->hi_cfg_wakeup_key = (state->chip_adr);
1025 /* port/bridge/power down ctrl */
1026 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
6cacdd46 1027 return HI_CfgCommand(state);
126f1e61
RM		 1028}
1029
1030static int HI_ResetCommand(struct drxd_state *state)
1031{
1032 int status;
1033
834751d4 1034 mutex_lock(&state->mutex);
6cacdd46
DH		 1035 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1036 HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1037 if (status == 0)
843e44a1 1038 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL);
834751d4 1039 mutex_unlock(&state->mutex);
126f1e61
RM		 1040 msleep(1);
1041 return status;
1042}
1043
6cacdd46 1044static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
126f1e61
RM		 1045{
1046 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
6cacdd46 1047 if (bEnableBridge)
126f1e61
RM		 1048 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
1049 else
1050 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
1051
1052 return HI_CfgCommand(state);
1053}
1054
1055#define HI_TR_WRITE 0x9
1056#define HI_TR_READ 0xA
1057#define HI_TR_READ_WRITE 0xB
1058#define HI_TR_BROADCAST 0x4
1059
1060#if 0
1061static int AtomicReadBlock(struct drxd_state *state,
9999daf4 1062 u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
126f1e61
RM		 1063{
1064 int status;
6cacdd46 1065 int i = 0;
126f1e61
RM		 1066
1067 /* Parameter check */
6cacdd46 1068 if ((!pData) || ((DataSize & 1) != 0))
126f1e61
RM		 1069 return -1;
1070
834751d4 1071 mutex_lock(&state->mutex);
126f1e61
RM		 1072
1073 do {
1074 /* Instruct HI to read n bytes */
1075 /* TODO use proper names forthese egisters */
58d5eaec
MCC		 1076 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1077 if (status < 0)
1078 break;
1079 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1080 if (status < 0)
1081 break;
1082 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1083 if (status < 0)
1084 break;
1085 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1086 if (status < 0)
1087 break;
1088 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1089 if (status < 0)
1090 break;
1091
1092 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1093 if (status < 0)
1094 break;
6cacdd46
DH		 1095
1096 } while (0);
1097
1098 if (status >= 0) {
1099 for (i = 0; i < (DataSize / 2); i += 1) {
126f1e61
RM		 1100 u16 word;
1101
1102 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1103 &word, 0);
6cacdd46 1104 if (status < 0)
126f1e61 1105 break;
6cacdd46
DH		 1106 pData[2 * i] = (u8) (word & 0xFF);
1107 pData[(2 * i) + 1] = (u8) (word >> 8);
126f1e61
RM		 1108 }
1109 }
834751d4 1110 mutex_unlock(&state->mutex);
126f1e61
RM		 1111 return status;
1112}
1113
1114static int AtomicReadReg32(struct drxd_state *state,
9999daf4 1115 u32 Addr, u32 *pData, u8 Flags)
126f1e61 1116{
6cacdd46 1117 u8 buf[sizeof(u32)];
126f1e61
RM		 1118 int status;
1119
1120 if (!pData)
1121 return -1;
6cacdd46
DH		 1122 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1123 *pData = (((u32) buf[0]) << 0) +
1124 (((u32) buf[1]) << 8) +
1125 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
126f1e61
RM		 1126 return status;
1127}
1128#endif
1129
1130static int StopAllProcessors(struct drxd_state *state)
1131{
1132 return Write16(state, HI_COMM_EXEC__A,
1133 SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
1134}
1135
1136static int EnableAndResetMB(struct drxd_state *state)
1137{
1138 if (state->type_A) {
1139 /* disable? monitor bus observe @ EC_OC */
1140 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
1141 }
1142
1143 /* do inverse broadcast, followed by explicit write to HI */
1144 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
1145 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
1146 return 0;
1147}
1148
1149static int InitCC(struct drxd_state *state)
1150{
1151 if (state->osc_clock_freq == 0 ||
1152 state->osc_clock_freq > 20000 ||
6cacdd46 1153 (state->osc_clock_freq % 4000) != 0) {
9999daf4 1154 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
126f1e61
RM		 1155 return -1;
1156 }
1157
1158 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1159 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
1160 CC_REG_PLL_MODE_PUMP_CUR_12, 0);
6cacdd46 1161 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0);
126f1e61
RM		 1162 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
1163 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1164
1165 return 0;
1166}
1167
1168static int ResetECOD(struct drxd_state *state)
1169{
1170 int status = 0;
1171
6cacdd46 1172 if (state->type_A)
126f1e61
RM		 1173 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1174 else
1175 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1176
6cacdd46 1177 if (!(status < 0))
126f1e61 1178 status = WriteTable(state, state->m_ResetECRAM);
6cacdd46 1179 if (!(status < 0))
126f1e61
RM		 1180 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1181 return status;
1182}
1183
126f1e61
RM		 1184/* Configure PGA switch */
1185
1186static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1187{
1188 int status;
1189 u16 AgModeLop = 0;
1190 u16 AgModeHip = 0;
1191 do {
6cacdd46 1192 if (pgaSwitch) {
126f1e61
RM		 1193 /* PGA on */
1194 /* fine gain */
58d5eaec
MCC		 1195 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1196 if (status < 0)
1197 break;
6cacdd46
DH		 1198 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1199 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
58d5eaec
MCC		 1200 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1201 if (status < 0)
1202 break;
126f1e61
RM		 1203
1204 /* coarse gain */
58d5eaec
MCC		 1205 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1206 if (status < 0)
1207 break;
6cacdd46
DH		 1208 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1209 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
58d5eaec
MCC		 1210 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1211 if (status < 0)
1212 break;
126f1e61
RM		 1213
1214 /* enable fine and coarse gain, enable AAF,
1215 no ext resistor */
58d5eaec
MCC		 1216 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1217 if (status < 0)
1218 break;
126f1e61
RM		 1219 } else {
1220 /* PGA off, bypass */
1221
1222 /* fine gain */
58d5eaec
MCC		 1223 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1224 if (status < 0)
1225 break;
6cacdd46
DH		 1226 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1227 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
58d5eaec
MCC		 1228 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1229 if (status < 0)
1230 break;
126f1e61
RM		 1231
1232 /* coarse gain */
58d5eaec
MCC		 1233 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1234 if (status < 0)
1235 break;
6cacdd46
DH		 1236 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1237 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
58d5eaec
MCC		 1238 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1239 if (status < 0)
1240 break;
126f1e61
RM		 1241
1242 /* disable fine and coarse gain, enable AAF,
1243 no ext resistor */
58d5eaec
MCC		 1244 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1245 if (status < 0)
1246 break;
126f1e61 1247 }
9999daf4 1248 } while (0);
126f1e61
RM		 1249 return status;
1250}
1251
1252static int InitFE(struct drxd_state *state)
1253{
6cacdd46 1254 int status;
126f1e61 1255
6cacdd46 1256 do {
58d5eaec
MCC		 1257 status = WriteTable(state, state->m_InitFE_1);
1258 if (status < 0)
1259 break;
126f1e61 1260
6cacdd46
DH		 1261 if (state->type_A) {
1262 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1263 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1264 0);
1265 } else {
1266 if (state->PGA)
1267 status = SetCfgPga(state, 0);
1268 else
1269 status =
1270 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1271 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1272 0);
1273 }
126f1e61 1274
6cacdd46
DH		 1275 if (status < 0)
1276 break;
58d5eaec
MCC		 1277 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1278 if (status < 0)
1279 break;
1280 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1281 if (status < 0)
1282 break;
126f1e61 1283
58d5eaec
MCC		 1284 status = WriteTable(state, state->m_InitFE_2);
1285 if (status < 0)
1286 break;
126f1e61 1287
6cacdd46 1288 } while (0);
126f1e61 1289
6cacdd46 1290 return status;
126f1e61
RM		 1291}
1292
1293static int InitFT(struct drxd_state *state)
1294{
1295 /*
6cacdd46
DH		 1296 norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1297 SC stuff
1298 */
1299 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
126f1e61
RM		 1300}
1301
1302static int SC_WaitForReady(struct drxd_state *state)
1303{
1304 u16 curCmd;
1305 int i;
1306
6cacdd46
DH		 1307 for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
1308 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
1309 if (status == 0 || curCmd == 0)
126f1e61
RM		 1310 return status;
1311 }
1312 return -1;
1313}
1314
1315static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1316{
6cacdd46 1317 int status = 0;
126f1e61
RM		 1318 u16 errCode;
1319
6cacdd46 1320 Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
126f1e61
RM		 1321 SC_WaitForReady(state);
1322
6cacdd46 1323 Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
126f1e61 1324
6cacdd46 1325 if (errCode == 0xFFFF) {
9999daf4 1326 printk(KERN_ERR "Command Error\n");
6cacdd46 1327 status = -1;
126f1e61
RM		 1328 }
1329
1330 return status;
1331}
1332
1333static int SC_ProcStartCommand(struct drxd_state *state,
6cacdd46 1334 u16 subCmd, u16 param0, u16 param1)
126f1e61 1335{
6cacdd46 1336 int status = 0;
126f1e61
RM		 1337 u16 scExec;
1338
834751d4 1339 mutex_lock(&state->mutex);
126f1e61
RM		 1340 do {
1341 Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1342 if (scExec != 1) {
6cacdd46 1343 status = -1;
126f1e61
RM		 1344 break;
1345 }
1346 SC_WaitForReady(state);
6cacdd46
DH		 1347 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1348 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1349 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
126f1e61
RM		 1350
1351 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
6cacdd46 1352 } while (0);
834751d4 1353 mutex_unlock(&state->mutex);
126f1e61
RM		 1354 return status;
1355}
1356
126f1e61 1357static int SC_SetPrefParamCommand(struct drxd_state *state,
6cacdd46 1358 u16 subCmd, u16 param0, u16 param1)
126f1e61
RM		 1359{
1360 int status;
1361
834751d4 1362 mutex_lock(&state->mutex);
126f1e61 1363 do {
58d5eaec
MCC		 1364 status = SC_WaitForReady(state);
1365 if (status < 0)
1366 break;
1367 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1368 if (status < 0)
1369 break;
1370 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1371 if (status < 0)
1372 break;
1373 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1374 if (status < 0)
1375 break;
6cacdd46 1376
58d5eaec
MCC		 1377 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1378 if (status < 0)
1379 break;
6cacdd46 1380 } while (0);
834751d4 1381 mutex_unlock(&state->mutex);
126f1e61
RM		 1382 return status;
1383}
1384
1385#if 0
6cacdd46 1386static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
126f1e61 1387{
6cacdd46 1388 int status = 0;
126f1e61 1389
834751d4 1390 mutex_lock(&state->mutex);
126f1e61 1391 do {
58d5eaec
MCC		 1392 status = SC_WaitForReady(state);
1393 if (status < 0)
1394 break;
1395 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1396 if (status < 0)
1397 break;
1398 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1399 if (status < 0)
1400 break;
6cacdd46 1401 } while (0);
834751d4 1402 mutex_unlock(&state->mutex);
126f1e61
RM		 1403 return status;
1404}
1405#endif
1406
1407static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1408{
1409 int status;
1410
1411 do {
1412 u16 EcOcRegIprInvMpg = 0;
1413 u16 EcOcRegOcModeLop = 0;
1414 u16 EcOcRegOcModeHip = 0;
6cacdd46 1415 u16 EcOcRegOcMpgSio = 0;
126f1e61 1416
58d5eaec 1417 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
126f1e61 1418
6cacdd46
DH		 1419 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1420 if (bEnableOutput) {
126f1e61 1421 EcOcRegOcModeHip |=
6cacdd46
DH		 1422 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1423 } else
126f1e61
RM		 1424 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1425 EcOcRegOcModeLop |=
6cacdd46
DH		 1426 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1427 } else {
126f1e61
RM		 1428 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1429
1430 if (bEnableOutput)
6cacdd46 1431 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
126f1e61
RM		 1432 else
1433 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1434
1435 /* Don't Insert RS Byte */
6cacdd46 1436 if (state->insert_rs_byte) {
126f1e61 1437 EcOcRegOcModeLop &=
6cacdd46 1438 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
126f1e61 1439 EcOcRegOcModeHip &=
6cacdd46 1440 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
126f1e61
RM		 1441 EcOcRegOcModeHip |=
1442 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1443 } else {
1444 EcOcRegOcModeLop |=
6cacdd46 1445 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
126f1e61
RM		 1446 EcOcRegOcModeHip &=
1447 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1448 EcOcRegOcModeHip |=
1449 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
1450 }
1451
1452 /* Mode = Parallel */
6cacdd46 1453 if (state->enable_parallel)
126f1e61
RM		 1454 EcOcRegOcModeLop &=
1455 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1456 else
1457 EcOcRegOcModeLop |=
1458 EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
1459 }
1460 /* Invert Data */
1461 /* EcOcRegIprInvMpg |= 0x00FF; */
1462 EcOcRegIprInvMpg &= (~(0x00FF));
1463
1464 /* Invert Error ( we don't use the pin ) */
1465 /* EcOcRegIprInvMpg |= 0x0100; */
1466 EcOcRegIprInvMpg &= (~(0x0100));
1467
1468 /* Invert Start ( we don't use the pin ) */
1469 /* EcOcRegIprInvMpg |= 0x0200; */
1470 EcOcRegIprInvMpg &= (~(0x0200));
1471
1472 /* Invert Valid ( we don't use the pin ) */
1473 /* EcOcRegIprInvMpg |= 0x0400; */
1474 EcOcRegIprInvMpg &= (~(0x0400));
1475
1476 /* Invert Clock */
1477 /* EcOcRegIprInvMpg |= 0x0800; */
1478 EcOcRegIprInvMpg &= (~(0x0800));
1479
1480 /* EcOcRegOcModeLop =0x05; */
58d5eaec
MCC		 1481 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1482 if (status < 0)
1483 break;
1484 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1485 if (status < 0)
1486 break;
1487 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1488 if (status < 0)
1489 break;
1490 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1491 if (status < 0)
1492 break;
6cacdd46 1493 } while (0);
126f1e61
RM		 1494 return status;
1495}
1496
1497static int SetDeviceTypeId(struct drxd_state *state)
1498{
6cacdd46
DH		 1499 int status = 0;
1500 u16 deviceId = 0;
1501
1502 do {
58d5eaec
MCC		 1503 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1504 if (status < 0)
1505 break;
6cacdd46 1506 /* TODO: why twice? */
58d5eaec
MCC		 1507 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1508 if (status < 0)
1509 break;
9999daf4 1510 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
6cacdd46
DH		 1511
1512 state->type_A = 0;
1513 state->PGA = 0;
1514 state->diversity = 0;
1515 if (deviceId == 0) { /* on A2 only 3975 available */
1516 state->type_A = 1;
9999daf4 1517 printk(KERN_INFO "DRX3975D-A2\n");
6cacdd46
DH		 1518 } else {
1519 deviceId >>= 12;
9999daf4 1520 printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
6cacdd46
DH		 1521 switch (deviceId) {
1522 case 4:
1523 state->diversity = 1;
1524 case 3:
1525 case 7:
1526 state->PGA = 1;
1527 break;
1528 case 6:
1529 state->diversity = 1;
1530 case 5:
1531 case 8:
1532 break;
1533 default:
1534 status = -1;
1535 break;
1536 }
1537 }
1538 } while (0);
1539
1540 if (status < 0)
1541 return status;
1542
1543 /* Init Table selection */
1544 state->m_InitAtomicRead = DRXD_InitAtomicRead;
1545 state->m_InitSC = DRXD_InitSC;
1546 state->m_ResetECRAM = DRXD_ResetECRAM;
1547 if (state->type_A) {
1548 state->m_ResetCEFR = DRXD_ResetCEFR;
1549 state->m_InitFE_1 = DRXD_InitFEA2_1;
1550 state->m_InitFE_2 = DRXD_InitFEA2_2;
1551 state->m_InitCP = DRXD_InitCPA2;
1552 state->m_InitCE = DRXD_InitCEA2;
1553 state->m_InitEQ = DRXD_InitEQA2;
1554 state->m_InitEC = DRXD_InitECA2;
1555 if (load_firmware(state, DRX_FW_FILENAME_A2))
1556 return -EIO;
1557 } else {
1558 state->m_ResetCEFR = NULL;
1559 state->m_InitFE_1 = DRXD_InitFEB1_1;
1560 state->m_InitFE_2 = DRXD_InitFEB1_2;
1561 state->m_InitCP = DRXD_InitCPB1;
1562 state->m_InitCE = DRXD_InitCEB1;
1563 state->m_InitEQ = DRXD_InitEQB1;
1564 state->m_InitEC = DRXD_InitECB1;
1565 if (load_firmware(state, DRX_FW_FILENAME_B1))
1566 return -EIO;
1567 }
1568 if (state->diversity) {
1569 state->m_InitDiversityFront = DRXD_InitDiversityFront;
1570 state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1571 state->m_DisableDiversity = DRXD_DisableDiversity;
1572 state->m_StartDiversityFront = DRXD_StartDiversityFront;
1573 state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1574 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1575 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1576 } else {
1577 state->m_InitDiversityFront = NULL;
1578 state->m_InitDiversityEnd = NULL;
1579 state->m_DisableDiversity = NULL;
1580 state->m_StartDiversityFront = NULL;
1581 state->m_StartDiversityEnd = NULL;
1582 state->m_DiversityDelay8MHZ = NULL;
1583 state->m_DiversityDelay6MHZ = NULL;
1584 }
1585
1586 return status;
126f1e61
RM		 1587}
1588
1589static int CorrectSysClockDeviation(struct drxd_state *state)
1590{
1591 int status;
6cacdd46
DH		 1592 s32 incr = 0;
1593 s32 nomincr = 0;
1594 u32 bandwidth = 0;
1595 u32 sysClockInHz = 0;
1596 u32 sysClockFreq = 0; /* in kHz */
126f1e61
RM		 1597 s16 oscClockDeviation;
1598 s16 Diff;
1599
1600 do {
1601 /* Retrieve bandwidth and incr, sanity check */
1602
1603 /* These accesses should be AtomicReadReg32, but that
1604 causes trouble (at least for diversity */
9999daf4 1605 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
58d5eaec
MCC		 1606 if (status < 0)
1607 break;
9999daf4 1608 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
58d5eaec
MCC		 1609 if (status < 0)
1610 break;
6cacdd46
DH		 1611
1612 if (state->type_A) {
1613 if ((nomincr - incr < -500) || (nomincr - incr > 500))
126f1e61
RM		 1614 break;
1615 } else {
6cacdd46 1616 if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
126f1e61
RM		 1617 break;
1618 }
1619
9f97c288
MCC		 1620 switch (state->props.bandwidth_hz) {
1621 case 8000000:
126f1e61
RM		 1622 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1623 break;
9f97c288 1624 case 7000000:
126f1e61
RM		 1625 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1626 break;
9f97c288 1627 case 6000000:
126f1e61
RM		 1628 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1629 break;
6cacdd46 1630 default:
126f1e61
RM		 1631 return -1;
1632 break;
1633 }
1634
1635 /* Compute new sysclock value
1636 sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
6cacdd46
DH		 1637 incr += (1 << 23);
1638 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
1639 sysClockFreq = (u32) (sysClockInHz / 1000);
126f1e61 1640 /* rounding */
9999daf4 1641 if ((sysClockInHz % 1000) > 500)
126f1e61 1642 sysClockFreq++;
126f1e61
RM		 1643
1644 /* Compute clock deviation in ppm */
6cacdd46
DH		 1645 oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
1646 (s32)
1647 (state->expected_sys_clock_freq)) *
1648 1000000L) /
1649 (s32)
1650 (state->expected_sys_clock_freq));
126f1e61
RM		 1651
1652 Diff = oscClockDeviation - state->osc_clock_deviation;
9999daf4 1653 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
6cacdd46 1654 if (Diff >= -200 && Diff <= 200) {
126f1e61 1655 state->sys_clock_freq = (u16) sysClockFreq;
6cacdd46 1656 if (oscClockDeviation != state->osc_clock_deviation) {
126f1e61 1657 if (state->config.osc_deviation) {
6cacdd46
DH		 1658 state->config.osc_deviation(state->priv,
1659 oscClockDeviation,
1660 1);
1661 state->osc_clock_deviation =
1662 oscClockDeviation;
126f1e61
RM		 1663 }
1664 }
1665 /* switch OFF SRMM scan in SC */
58d5eaec
MCC		 1666 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1667 if (status < 0)
1668 break;
126f1e61
RM		 1669 /* overrule FE_IF internal value for
1670 proper re-locking */
58d5eaec
MCC		 1671 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1672 if (status < 0)
1673 break;
126f1e61
RM		 1674 state->cscd_state = CSCD_SAVED;
1675 }
6cacdd46 1676 } while (0);
126f1e61 1677
9999daf4 1678 return status;
126f1e61
RM		 1679}
1680
1681static int DRX_Stop(struct drxd_state *state)
1682{
1683 int status;
1684
6cacdd46 1685 if (state->drxd_state != DRXD_STARTED)
126f1e61
RM		 1686 return 0;
1687
1688 do {
6cacdd46 1689 if (state->cscd_state != CSCD_SAVED) {
126f1e61 1690 u32 lock;
58d5eaec
MCC		 1691 status = DRX_GetLockStatus(state, &lock);
1692 if (status < 0)
1693 break;
126f1e61
RM		 1694 }
1695
58d5eaec
MCC		 1696 status = StopOC(state);
1697 if (status < 0)
1698 break;
126f1e61
RM		 1699
1700 state->drxd_state = DRXD_STOPPED;
1701
58d5eaec
MCC		 1702 status = ConfigureMPEGOutput(state, 0);
1703 if (status < 0)
1704 break;
126f1e61 1705
6cacdd46 1706 if (state->type_A) {
126f1e61 1707 /* Stop relevant processors off the device */
58d5eaec
MCC		 1708 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1709 if (status < 0)
1710 break;
126f1e61 1711
58d5eaec
MCC		 1712 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1713 if (status < 0)
1714 break;
1715 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1716 if (status < 0)
1717 break;
126f1e61
RM		 1718 } else {
1719 /* Stop all processors except HI & CC & FE */
58d5eaec
MCC		 1720 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1721 if (status < 0)
1722 break;
1723 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1724 if (status < 0)
1725 break;
1726 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1727 if (status < 0)
1728 break;
1729 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1730 if (status < 0)
1731 break;
1732 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1733 if (status < 0)
1734 break;
1735 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1736 if (status < 0)
1737 break;
1738 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1739 if (status < 0)
1740 break;
126f1e61
RM		 1741 }
1742
6cacdd46 1743 } while (0);
126f1e61
RM		 1744 return status;
1745}
1746
8b35c2fe
MCC		 1747#if 0 /* Currently unused */
1748static int SetOperationMode(struct drxd_state *state, int oMode)
126f1e61
RM		 1749{
1750 int status;
1751
1752 do {
1753 if (state->drxd_state != DRXD_STOPPED) {
1754 status = -1;
1755 break;
1756 }
1757
1758 if (oMode == state->operation_mode) {
1759 status = 0;
1760 break;
1761 }
1762
1763 if (oMode != OM_Default && !state->diversity) {
1764 status = -1;
1765 break;
1766 }
1767
6cacdd46 1768 switch (oMode) {
126f1e61 1769 case OM_DVBT_Diversity_Front:
6cacdd46 1770 status = WriteTable(state, state->m_InitDiversityFront);
126f1e61
RM		 1771 break;
1772 case OM_DVBT_Diversity_End:
6cacdd46 1773 status = WriteTable(state, state->m_InitDiversityEnd);
126f1e61
RM		 1774 break;
1775 case OM_Default:
1776 /* We need to check how to
1777 get DRXD out of diversity */
1778 default:
1779 status = WriteTable(state, state->m_DisableDiversity);
1780 break;
1781 }
6cacdd46 1782 } while (0);
126f1e61
RM		 1783
1784 if (!status)
1785 state->operation_mode = oMode;
1786 return status;
1787}
8b35c2fe 1788#endif
126f1e61 1789
126f1e61
RM		 1790static int StartDiversity(struct drxd_state *state)
1791{
6cacdd46 1792 int status = 0;
126f1e61
RM		 1793 u16 rcControl;
1794
1795 do {
1796 if (state->operation_mode == OM_DVBT_Diversity_Front) {
58d5eaec
MCC		 1797 status = WriteTable(state, state->m_StartDiversityFront);
1798 if (status < 0)
1799 break;
6cacdd46 1800 } else if (state->operation_mode == OM_DVBT_Diversity_End) {
58d5eaec
MCC		 1801 status = WriteTable(state, state->m_StartDiversityEnd);
1802 if (status < 0)
1803 break;
9f97c288 1804 if (state->props.bandwidth_hz == 8000000) {
58d5eaec
MCC		 1805 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1806 if (status < 0)
1807 break;
126f1e61 1808 } else {
58d5eaec
MCC		 1809 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1810 if (status < 0)
1811 break;
126f1e61
RM		 1812 }
1813
58d5eaec
MCC		 1814 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1815 if (status < 0)
1816 break;
126f1e61
RM		 1817 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1818 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
6cacdd46
DH		 1819 /* combining enabled */
1820 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1821 B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1822 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
58d5eaec
MCC		 1823 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1824 if (status < 0)
1825 break;
126f1e61 1826 }
6cacdd46 1827 } while (0);
126f1e61
RM		 1828 return status;
1829}
1830
126f1e61
RM		 1831static int SetFrequencyShift(struct drxd_state *state,
1832 u32 offsetFreq, int channelMirrored)
1833{
1834 int negativeShift = (state->tuner_mirrors == channelMirrored);
1835
1836 /* Handle all mirroring
1837 *
1838 * Note: ADC mirroring (aliasing) is implictly handled by limiting
1839 * feFsRegAddInc to 28 bits below
1840 * (if the result before masking is more than 28 bits, this means
1841 * that the ADC is mirroring.
1842 * The masking is in fact the aliasing of the ADC)
1843 *
1844 */
1845
1846 /* Compute register value, unsigned computation */
6cacdd46 1847 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
126f1e61 1848 offsetFreq,
6cacdd46 1849 1 << 28, state->sys_clock_freq);
126f1e61
RM		 1850 /* Remove integer part */
1851 state->fe_fs_add_incr &= 0x0FFFFFFFL;
9999daf4 1852 if (negativeShift)
6cacdd46 1853 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
126f1e61
RM		 1854
1855 /* Save the frequency shift without tunerOffset compensation
1856 for CtrlGetChannel. */
6cacdd46
DH		 1857 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1858 1 << 28, state->sys_clock_freq);
126f1e61
RM		 1859 /* Remove integer part */
1860 state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1861 if (negativeShift)
6cacdd46 1862 state->org_fe_fs_add_incr = ((1L << 28) -
126f1e61
RM		 1863 state->org_fe_fs_add_incr);
1864
1865 return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1866 state->fe_fs_add_incr, 0);
1867}
1868
6cacdd46
DH		 1869static int SetCfgNoiseCalibration(struct drxd_state *state,
1870 struct SNoiseCal *noiseCal)
126f1e61
RM		 1871{
1872 u16 beOptEna;
6cacdd46 1873 int status = 0;
126f1e61
RM		 1874
1875 do {
58d5eaec
MCC		 1876 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1877 if (status < 0)
1878 break;
6cacdd46 1879 if (noiseCal->cpOpt) {
126f1e61
RM		 1880 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1881 } else {
1882 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
58d5eaec
MCC		 1883 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1884 if (status < 0)
1885 break;
126f1e61 1886 }
58d5eaec
MCC		 1887 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1888 if (status < 0)
1889 break;
126f1e61 1890
6cacdd46 1891 if (!state->type_A) {
58d5eaec
MCC		 1892 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1893 if (status < 0)
1894 break;
1895 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1896 if (status < 0)
1897 break;
126f1e61 1898 }
6cacdd46 1899 } while (0);
126f1e61
RM		 1900
1901 return status;
1902}
1903
1904static int DRX_Start(struct drxd_state *state, s32 off)
1905{
9f97c288 1906 struct dtv_frontend_properties *p = &state->props;
126f1e61
RM		 1907 int status;
1908
6cacdd46
DH		 1909 u16 transmissionParams = 0;
1910 u16 operationMode = 0;
1911 u16 qpskTdTpsPwr = 0;
1912 u16 qam16TdTpsPwr = 0;
1913 u16 qam64TdTpsPwr = 0;
1914 u32 feIfIncr = 0;
1915 u32 bandwidth = 0;
126f1e61
RM		 1916 int mirrorFreqSpect;
1917
6cacdd46
DH		 1918 u16 qpskSnCeGain = 0;
1919 u16 qam16SnCeGain = 0;
1920 u16 qam64SnCeGain = 0;
1921 u16 qpskIsGainMan = 0;
1922 u16 qam16IsGainMan = 0;
1923 u16 qam64IsGainMan = 0;
1924 u16 qpskIsGainExp = 0;
1925 u16 qam16IsGainExp = 0;
1926 u16 qam64IsGainExp = 0;
1927 u16 bandwidthParam = 0;
1928
1929 if (off < 0)
1930 off = (off - 500) / 1000;
126f1e61 1931 else
6cacdd46 1932 off = (off + 500) / 1000;
126f1e61
RM		 1933
1934 do {
1935 if (state->drxd_state != DRXD_STOPPED)
1936 return -1;
58d5eaec
MCC		 1937 status = ResetECOD(state);
1938 if (status < 0)
1939 break;
126f1e61 1940 if (state->type_A) {
58d5eaec
MCC		 1941 status = InitSC(state);
1942 if (status < 0)
1943 break;
126f1e61 1944 } else {
58d5eaec
MCC		 1945 status = InitFT(state);
1946 if (status < 0)
1947 break;
1948 status = InitCP(state);
1949 if (status < 0)
1950 break;
1951 status = InitCE(state);
1952 if (status < 0)
1953 break;
1954 status = InitEQ(state);
1955 if (status < 0)
1956 break;
1957 status = InitSC(state);
1958 if (status < 0)
1959 break;
126f1e61
RM		 1960 }
1961
1962 /* Restore current IF & RF AGC settings */
1963
58d5eaec
MCC		 1964 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1965 if (status < 0)
1966 break;
1967 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1968 if (status < 0)
1969 break;
126f1e61 1970
9f97c288 1971 mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
126f1e61
RM		 1972
1973 switch (p->transmission_mode) {
6cacdd46 1974 default: /* Not set, detect it automatically */
126f1e61
RM		 1975 operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1976 /* fall through , try first guess DRX_FFTMODE_8K */
6cacdd46 1977 case TRANSMISSION_MODE_8K:
126f1e61
RM		 1978 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1979 if (state->type_A) {
58d5eaec
MCC		 1980 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1981 if (status < 0)
1982 break;
6cacdd46 1983 qpskSnCeGain = 99;
126f1e61
RM		 1984 qam16SnCeGain = 83;
1985 qam64SnCeGain = 67;
1986 }
1987 break;
6cacdd46 1988 case TRANSMISSION_MODE_2K:
126f1e61
RM		 1989 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1990 if (state->type_A) {
58d5eaec
MCC		 1991 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1992 if (status < 0)
1993 break;
6cacdd46 1994 qpskSnCeGain = 97;
126f1e61
RM		 1995 qam16SnCeGain = 71;
1996 qam64SnCeGain = 65;
1997 }
1998 break;
1999 }
2000
6cacdd46 2001 switch (p->guard_interval) {
126f1e61
RM		 2002 case GUARD_INTERVAL_1_4:
2003 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2004 break;
2005 case GUARD_INTERVAL_1_8:
2006 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
2007 break;
2008 case GUARD_INTERVAL_1_16:
2009 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
2010 break;
2011 case GUARD_INTERVAL_1_32:
2012 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
2013 break;
6cacdd46 2014 default: /* Not set, detect it automatically */
126f1e61
RM		 2015 operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
2016 /* try first guess 1/4 */
2017 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2018 break;
2019 }
2020
9f97c288 2021 switch (p->hierarchy) {
126f1e61
RM		 2022 case HIERARCHY_1:
2023 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
2024 if (state->type_A) {
58d5eaec
MCC		 2025 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2026 if (status < 0)
2027 break;
2028 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2029 if (status < 0)
2030 break;
126f1e61 2031
6cacdd46 2032 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
126f1e61
RM		 2033 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
2034 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
2035
6cacdd46
DH		 2036 qpskIsGainMan =
2037 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
126f1e61 2038 qam16IsGainMan =
6cacdd46 2039 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
126f1e61 2040 qam64IsGainMan =
6cacdd46 2041 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
126f1e61 2042
6cacdd46
DH		 2043 qpskIsGainExp =
2044 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
126f1e61 2045 qam16IsGainExp =
6cacdd46 2046 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
126f1e61 2047 qam64IsGainExp =
6cacdd46 2048 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
126f1e61
RM		 2049 }
2050 break;
2051
2052 case HIERARCHY_2:
2053 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
2054 if (state->type_A) {
58d5eaec
MCC		 2055 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2056 if (status < 0)
2057 break;
2058 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2059 if (status < 0)
2060 break;
126f1e61 2061
6cacdd46 2062 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
126f1e61
RM		 2063 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
2064 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
2065
2066 qpskIsGainMan =
6cacdd46 2067 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
126f1e61 2068 qam16IsGainMan =
6cacdd46 2069 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
126f1e61 2070 qam64IsGainMan =
6cacdd46 2071 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
126f1e61 2072
6cacdd46
DH		 2073 qpskIsGainExp =
2074 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
126f1e61 2075 qam16IsGainExp =
6cacdd46 2076 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
126f1e61 2077 qam64IsGainExp =
6cacdd46 2078 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
126f1e61
RM		 2079 }
2080 break;
2081 case HIERARCHY_4:
2082 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
2083 if (state->type_A) {
58d5eaec
MCC		 2084 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2085 if (status < 0)
2086 break;
2087 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2088 if (status < 0)
2089 break;
126f1e61 2090
6cacdd46 2091 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
126f1e61
RM		 2092 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
2093 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
2094
6cacdd46
DH		 2095 qpskIsGainMan =
2096 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
126f1e61 2097 qam16IsGainMan =
6cacdd46 2098 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
126f1e61 2099 qam64IsGainMan =
6cacdd46 2100 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
126f1e61 2101
6cacdd46
DH		 2102 qpskIsGainExp =
2103 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
126f1e61 2104 qam16IsGainExp =
6cacdd46 2105 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
126f1e61 2106 qam64IsGainExp =
6cacdd46 2107 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
126f1e61
RM		 2108 }
2109 break;
2110 case HIERARCHY_AUTO:
2111 default:
2112 /* Not set, detect it automatically, start with none */
2113 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
2114 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
2115 if (state->type_A) {
58d5eaec
MCC		 2116 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2117 if (status < 0)
2118 break;
2119 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2120 if (status < 0)
2121 break;
126f1e61 2122
6cacdd46 2123 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
126f1e61
RM		 2124 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2125 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2126
6cacdd46
DH		 2127 qpskIsGainMan =
2128 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
126f1e61 2129 qam16IsGainMan =
6cacdd46 2130 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
126f1e61 2131 qam64IsGainMan =
6cacdd46 2132 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
126f1e61 2133
6cacdd46
DH		 2134 qpskIsGainExp =
2135 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
126f1e61 2136 qam16IsGainExp =
6cacdd46 2137 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
126f1e61 2138 qam64IsGainExp =
6cacdd46 2139 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
126f1e61
RM		 2140 }
2141 break;
2142 }
58d5eaec
MCC		 2143 status = status;
2144 if (status < 0)
2145 break;
126f1e61 2146
9f97c288 2147 switch (p->modulation) {
126f1e61
RM		 2148 default:
2149 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2150 /* fall through , try first guess
2151 DRX_CONSTELLATION_QAM64 */
2152 case QAM_64:
2153 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2154 if (state->type_A) {
58d5eaec
MCC		 2155 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2156 if (status < 0)
2157 break;
2158 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2159 if (status < 0)
2160 break;
2161 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2162 if (status < 0)
2163 break;
2164 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2165 if (status < 0)
2166 break;
2167 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2168 if (status < 0)
2169 break;
2170
2171 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2172 if (status < 0)
2173 break;
2174 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2175 if (status < 0)
2176 break;
2177 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2178 if (status < 0)
2179 break;
2180 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2181 if (status < 0)
2182 break;
126f1e61
RM		 2183 }
2184 break;
6cacdd46 2185 case QPSK:
126f1e61
RM		 2186 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2187 if (state->type_A) {
58d5eaec
MCC		 2188 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2189 if (status < 0)
2190 break;
2191 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2192 if (status < 0)
2193 break;
2194 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2195 if (status < 0)
2196 break;
2197 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2198 if (status < 0)
2199 break;
2200 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2201 if (status < 0)
2202 break;
2203
2204 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2205 if (status < 0)
2206 break;
2207 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2208 if (status < 0)
2209 break;
2210 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2211 if (status < 0)
2212 break;
2213 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2214 if (status < 0)
2215 break;
126f1e61
RM		 2216 }
2217 break;
2218
2219 case QAM_16:
2220 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2221 if (state->type_A) {
58d5eaec
MCC		 2222 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2223 if (status < 0)
2224 break;
2225 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2226 if (status < 0)
2227 break;
2228 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2229 if (status < 0)
2230 break;
2231 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2232 if (status < 0)
2233 break;
2234 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2235 if (status < 0)
2236 break;
2237
2238 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2239 if (status < 0)
2240 break;
2241 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2242 if (status < 0)
2243 break;
2244 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2245 if (status < 0)
2246 break;
2247 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2248 if (status < 0)
2249 break;
126f1e61
RM		 2250 }
2251 break;
2252
2253 }
58d5eaec
MCC		 2254 status = status;
2255 if (status < 0)
2256 break;
126f1e61
RM		 2257
2258 switch (DRX_CHANNEL_HIGH) {
2259 default:
2260 case DRX_CHANNEL_AUTO:
2261 case DRX_CHANNEL_LOW:
2262 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
58d5eaec
MCC		 2263 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2264 if (status < 0)
2265 break;
126f1e61
RM		 2266 break;
2267 case DRX_CHANNEL_HIGH:
2268 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
58d5eaec
MCC		 2269 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2270 if (status < 0)
2271 break;
126f1e61
RM		 2272 break;
2273
2274 }
2275
6cacdd46 2276 switch (p->code_rate_HP) {
126f1e61
RM		 2277 case FEC_1_2:
2278 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2279 if (state->type_A) {
58d5eaec
MCC		 2280 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2281 if (status < 0)
2282 break;
126f1e61
RM		 2283 }
2284 break;
2285 default:
2286 operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
6cacdd46 2287 case FEC_2_3:
126f1e61
RM		 2288 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2289 if (state->type_A) {
58d5eaec
MCC		 2290 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2291 if (status < 0)
2292 break;
126f1e61
RM		 2293 }
2294 break;
6cacdd46 2295 case FEC_3_4:
126f1e61
RM		 2296 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2297 if (state->type_A) {
58d5eaec
MCC		 2298 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2299 if (status < 0)
2300 break;
126f1e61
RM		 2301 }
2302 break;
6cacdd46 2303 case FEC_5_6:
126f1e61
RM		 2304 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2305 if (state->type_A) {
58d5eaec
MCC		 2306 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2307 if (status < 0)
2308 break;
126f1e61
RM		 2309 }
2310 break;
6cacdd46 2311 case FEC_7_8:
126f1e61
RM		 2312 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2313 if (state->type_A) {
58d5eaec
MCC		 2314 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2315 if (status < 0)
2316 break;
126f1e61
RM		 2317 }
2318 break;
2319 }
58d5eaec
MCC		 2320 status = status;
2321 if (status < 0)
2322 break;
126f1e61
RM		 2323
2324 /* First determine real bandwidth (Hz) */
2325 /* Also set delay for impulse noise cruncher (only A2) */
2326 /* Also set parameters for EC_OC fix, note
2327 EC_OC_REG_TMD_HIL_MAR is changed
2328 by SC for fix for some 8K,1/8 guard but is restored by
2329 InitEC and ResetEC
2330 functions */
9f97c288
MCC		 2331 switch (p->bandwidth_hz) {
2332 case 0:
2333 p->bandwidth_hz = 8000000;
2334 /* fall through */
2335 case 8000000:
126f1e61
RM		 2336 /* (64/7)*(8/8)*1000000 */
2337 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2338
2339 bandwidthParam = 0;
2340 status = Write16(state,
6cacdd46 2341 FE_AG_REG_IND_DEL__A, 50, 0x0000);
126f1e61 2342 break;
9f97c288 2343 case 7000000:
126f1e61
RM		 2344 /* (64/7)*(7/8)*1000000 */
2345 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
6cacdd46 2346 bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
126f1e61 2347 status = Write16(state,
6cacdd46 2348 FE_AG_REG_IND_DEL__A, 59, 0x0000);
126f1e61 2349 break;
9f97c288 2350 case 6000000:
126f1e61
RM		 2351 /* (64/7)*(6/8)*1000000 */
2352 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
6cacdd46 2353 bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
126f1e61 2354 status = Write16(state,
6cacdd46 2355 FE_AG_REG_IND_DEL__A, 71, 0x0000);
126f1e61 2356 break;
63952e8c
AO		 2357 default:
2358 status = -EINVAL;
126f1e61 2359 }
58d5eaec
MCC		 2360 if (status < 0)
2361 break;
126f1e61 2362
58d5eaec
MCC		 2363 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2364 if (status < 0)
2365 break;
126f1e61
RM		 2366
2367 {
2368 u16 sc_config;
58d5eaec
MCC		 2369 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2370 if (status < 0)
2371 break;
126f1e61
RM		 2372
2373 /* enable SLAVE mode in 2k 1/32 to
2374 prevent timing change glitches */
6cacdd46
DH		 2375 if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
2376 (p->guard_interval == GUARD_INTERVAL_1_32)) {
126f1e61
RM		 2377 /* enable slave */
2378 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2379 } else {
2380 /* disable slave */
2381 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2382 }
58d5eaec
MCC		 2383 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2384 if (status < 0)
2385 break;
126f1e61
RM		 2386 }
2387
58d5eaec
MCC		 2388 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2389 if (status < 0)
2390 break;
126f1e61 2391
6cacdd46 2392 if (state->cscd_state == CSCD_INIT) {
126f1e61 2393 /* switch on SRMM scan in SC */
58d5eaec
MCC		 2394 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2395 if (status < 0)
2396 break;
2397/* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
126f1e61
RM		 2398 state->cscd_state = CSCD_SET;
2399 }
2400
126f1e61
RM		 2401 /* Now compute FE_IF_REG_INCR */
2402 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
6cacdd46
DH		 2403 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2404 feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2405 (1ULL << 21), bandwidth) - (1 << 23);
58d5eaec
MCC		 2406 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2407 if (status < 0)
2408 break;
2409 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2410 if (status < 0)
2411 break;
126f1e61
RM		 2412 /* Bandwidth setting done */
2413
2414 /* Mirror & frequency offset */
2415 SetFrequencyShift(state, off, mirrorFreqSpect);
2416
2417 /* Start SC, write channel settings to SC */
2418
2419 /* Enable SC after setting all other parameters */
58d5eaec
MCC		 2420 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2421 if (status < 0)
2422 break;
2423 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2424 if (status < 0)
2425 break;
126f1e61
RM		 2426
2427 /* Write SC parameter registers, operation mode */
2428#if 1
6cacdd46
DH		 2429 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
2430 SC_RA_RAM_OP_AUTO_GUARD__M |
2431 SC_RA_RAM_OP_AUTO_CONST__M |
2432 SC_RA_RAM_OP_AUTO_HIER__M |
2433 SC_RA_RAM_OP_AUTO_RATE__M);
126f1e61 2434#endif
58d5eaec
MCC		 2435 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2436 if (status < 0)
2437 break;
126f1e61
RM		 2438
2439 /* Start correct processes to get in lock */
58d5eaec
MCC		 2440 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2441 if (status < 0)
2442 break;
126f1e61 2443
58d5eaec
MCC		 2444 status = StartOC(state);
2445 if (status < 0)
2446 break;
126f1e61 2447
6cacdd46 2448 if (state->operation_mode != OM_Default) {
58d5eaec
MCC		 2449 status = StartDiversity(state);
2450 if (status < 0)
2451 break;
126f1e61
RM		 2452 }
2453
2454 state->drxd_state = DRXD_STARTED;
6cacdd46 2455 } while (0);
126f1e61
RM		 2456
2457 return status;
2458}
2459
2460static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2461{
2462 u32 ulRfAgcOutputLevel = 0xffffffff;
6cacdd46
DH		 2463 u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */
2464 u32 ulRfAgcMinLevel = 0; /* Currently unused */
2465 u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
2466 u32 ulRfAgcSpeed = 0; /* Currently unused */
2467 u32 ulRfAgcMode = 0; /*2; Off */
2468 u32 ulRfAgcR1 = 820;
126f1e61 2469 u32 ulRfAgcR2 = 2200;
6cacdd46
DH		 2470 u32 ulRfAgcR3 = 150;
2471 u32 ulIfAgcMode = 0; /* Auto */
126f1e61
RM		 2472 u32 ulIfAgcOutputLevel = 0xffffffff;
2473 u32 ulIfAgcSettleLevel = 0xffffffff;
2474 u32 ulIfAgcMinLevel = 0xffffffff;
2475 u32 ulIfAgcMaxLevel = 0xffffffff;
2476 u32 ulIfAgcSpeed = 0xffffffff;
6cacdd46 2477 u32 ulIfAgcR1 = 820;
126f1e61 2478 u32 ulIfAgcR2 = 2200;
6cacdd46 2479 u32 ulIfAgcR3 = 150;
126f1e61
RM		 2480 u32 ulClock = state->config.clock;
2481 u32 ulSerialMode = 0;
6cacdd46 2482 u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */
126f1e61
RM		 2483 u32 ulHiI2cDelay = HI_I2C_DELAY;
2484 u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2485 u32 ulHiI2cPatch = 0;
6cacdd46 2486 u32 ulEnvironment = APPENV_PORTABLE;
126f1e61
RM		 2487 u32 ulEnvironmentDiversity = APPENV_MOBILE;
2488 u32 ulIFFilter = IFFILTER_SAW;
2489
6cacdd46 2490 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
126f1e61
RM		 2491 state->if_agc_cfg.outputLevel = 0;
2492 state->if_agc_cfg.settleLevel = 140;
2493 state->if_agc_cfg.minOutputLevel = 0;
2494 state->if_agc_cfg.maxOutputLevel = 1023;
2495 state->if_agc_cfg.speed = 904;
2496
6cacdd46
DH		 2497 if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2498 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2499 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
126f1e61
RM		 2500 }
2501
6cacdd46 2502 if (ulIfAgcMode == 0 &&
126f1e61
RM		 2503 ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2504 ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2505 ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
6cacdd46
DH		 2506 ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2507 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2508 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
2509 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
2510 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
2511 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
126f1e61
RM		 2512 }
2513
6cacdd46
DH		 2514 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
2515 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
2516 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
126f1e61 2517
6cacdd46
DH		 2518 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
2519 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
2520 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
126f1e61 2521
6cacdd46 2522 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
126f1e61 2523 /* rest of the RFAgcCfg structure currently unused */
6cacdd46
DH		 2524 if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2525 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2526 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
126f1e61
RM		 2527 }
2528
6cacdd46 2529 if (ulRfAgcMode == 0 &&
126f1e61
RM		 2530 ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2531 ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2532 ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
6cacdd46
DH		 2533 ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2534 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2535 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
2536 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
2537 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
2538 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
126f1e61
RM		 2539 }
2540
9999daf4 2541 if (ulRfAgcMode == 2)
6cacdd46 2542 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
126f1e61
RM		 2543
2544 if (ulEnvironment <= 2)
6cacdd46
DH		 2545 state->app_env_default = (enum app_env)
2546 (ulEnvironment);
126f1e61
RM		 2547 if (ulEnvironmentDiversity <= 2)
2548 state->app_env_diversity = (enum app_env)
6cacdd46 2549 (ulEnvironmentDiversity);
126f1e61 2550
6cacdd46 2551 if (ulIFFilter == IFFILTER_DISCRETE) {
126f1e61 2552 /* discrete filter */
6cacdd46
DH		 2553 state->noise_cal.cpOpt = 0;
2554 state->noise_cal.cpNexpOfs = 40;
2555 state->noise_cal.tdCal2k = -40;
2556 state->noise_cal.tdCal8k = -24;
126f1e61
RM		 2557 } else {
2558 /* SAW filter */
6cacdd46
DH		 2559 state->noise_cal.cpOpt = 1;
2560 state->noise_cal.cpNexpOfs = 0;
2561 state->noise_cal.tdCal2k = -21;
2562 state->noise_cal.tdCal8k = -24;
126f1e61 2563 }
6cacdd46
DH		 2564 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
2565
2566 state->chip_adr = (state->config.demod_address << 1) | 1;
2567 switch (ulHiI2cPatch) {
2568 case 1:
2569 state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
2570 break;
2571 case 3:
2572 state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
2573 break;
126f1e61
RM		 2574 default:
2575 state->m_HiI2cPatch = NULL;
2576 }
2577
2578 /* modify tuner and clock attributes */
6cacdd46 2579 state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
126f1e61
RM		 2580 /* expected system clock frequency in kHz */
2581 state->expected_sys_clock_freq = 48000;
2582 /* real system clock frequency in kHz */
2583 state->sys_clock_freq = 48000;
6cacdd46 2584 state->osc_clock_freq = (u16) ulClock;
126f1e61
RM		 2585 state->osc_clock_deviation = 0;
2586 state->cscd_state = CSCD_INIT;
2587 state->drxd_state = DRXD_UNINITIALIZED;
2588
6cacdd46
DH		 2589 state->PGA = 0;
2590 state->type_A = 0;
2591 state->tuner_mirrors = 0;
126f1e61
RM		 2592
2593 /* modify MPEG output attributes */
ba967965 2594 state->insert_rs_byte = state->config.insert_rs_byte;
126f1e61
RM		 2595 state->enable_parallel = (ulSerialMode != 1);
2596
2597 /* Timing div, 250ns/Psys */
2598 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2599
6cacdd46
DH		 2600 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
2601 ulHiI2cDelay) / 1000;
126f1e61
RM		 2602 /* Bridge delay, uses oscilator clock */
2603 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
6cacdd46
DH		 2604 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
2605 ulHiI2cBridgeDelay) / 1000;
126f1e61
RM		 2606
2607 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2608 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2609 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2610 return 0;
2611}
2612
8b35c2fe 2613static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
126f1e61 2614{
6cacdd46 2615 int status = 0;
126f1e61
RM		 2616 u32 driverVersion;
2617
2618 if (state->init_done)
2619 return 0;
2620
2621 CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2622
2623 do {
2624 state->operation_mode = OM_Default;
2625
58d5eaec
MCC		 2626 status = SetDeviceTypeId(state);
2627 if (status < 0)
2628 break;
126f1e61
RM		 2629
2630 /* Apply I2c address patch to B1 */
cea13002 2631 if (!state->type_A && state->m_HiI2cPatch != NULL) {
58d5eaec
MCC		 2632 status = WriteTable(state, state->m_HiI2cPatch);
2633 if (status < 0)
2634 break;
cea13002 2635 }
126f1e61
RM		 2636
2637 if (state->type_A) {
2638 /* HI firmware patch for UIO readout,
2639 avoid clearing of result register */
58d5eaec
MCC		 2640 status = Write16(state, 0x43012D, 0x047f, 0);
2641 if (status < 0)
2642 break;
126f1e61
RM		 2643 }
2644
58d5eaec
MCC		 2645 status = HI_ResetCommand(state);
2646 if (status < 0)
2647 break;
126f1e61 2648
58d5eaec
MCC		 2649 status = StopAllProcessors(state);
2650 if (status < 0)
2651 break;
2652 status = InitCC(state);
2653 if (status < 0)
2654 break;
126f1e61
RM		 2655
2656 state->osc_clock_deviation = 0;
2657
2658 if (state->config.osc_deviation)
2659 state->osc_clock_deviation =
6cacdd46 2660 state->config.osc_deviation(state->priv, 0, 0);
126f1e61
RM		 2661 {
2662 /* Handle clock deviation */
2663 s32 devB;
6cacdd46
DH		 2664 s32 devA = (s32) (state->osc_clock_deviation) *
2665 (s32) (state->expected_sys_clock_freq);
126f1e61 2666 /* deviation in kHz */
6cacdd46 2667 s32 deviation = (devA / (1000000L));
126f1e61 2668 /* rounding, signed */
6cacdd46
DH		 2669 if (devA > 0)
2670 devB = (2);
126f1e61 2671 else
6cacdd46
DH		 2672 devB = (-2);
2673 if ((devB * (devA % 1000000L) > 1000000L)) {
126f1e61 2674 /* add +1 or -1 */
6cacdd46 2675 deviation += (devB / 2);
126f1e61
RM		 2676 }
2677
6cacdd46
DH		 2678 state->sys_clock_freq =
2679 (u16) ((state->expected_sys_clock_freq) +
2680 deviation);
126f1e61 2681 }
58d5eaec
MCC		 2682 status = InitHI(state);
2683 if (status < 0)
2684 break;
2685 status = InitAtomicRead(state);
2686 if (status < 0)
2687 break;
126f1e61 2688
58d5eaec
MCC		 2689 status = EnableAndResetMB(state);
2690 if (status < 0)
2691 break;
73b8922f 2692 if (state->type_A) {
58d5eaec
MCC		 2693 status = ResetCEFR(state);
2694 if (status < 0)
2695 break;
73b8922f 2696 }
126f1e61 2697 if (fw) {
58d5eaec
MCC		 2698 status = DownloadMicrocode(state, fw, fw_size);
2699 if (status < 0)
2700 break;
126f1e61 2701 } else {
58d5eaec
MCC		 2702 status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2703 if (status < 0)
2704 break;
126f1e61
RM		 2705 }
2706
2707 if (state->PGA) {
2708 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
6cacdd46 2709 SetCfgPga(state, 0); /* PGA = 0 dB */
126f1e61
RM		 2710 } else {
2711 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2712 }
2713
2714 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2715
58d5eaec
MCC		 2716 status = InitFE(state);
2717 if (status < 0)
2718 break;
2719 status = InitFT(state);
2720 if (status < 0)
2721 break;
2722 status = InitCP(state);
2723 if (status < 0)
2724 break;
2725 status = InitCE(state);
2726 if (status < 0)
2727 break;
2728 status = InitEQ(state);
2729 if (status < 0)
2730 break;
2731 status = InitEC(state);
2732 if (status < 0)
2733 break;
2734 status = InitSC(state);
2735 if (status < 0)
2736 break;
126f1e61 2737
58d5eaec
MCC		 2738 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2739 if (status < 0)
2740 break;
2741 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2742 if (status < 0)
2743 break;
126f1e61
RM		 2744
2745 state->cscd_state = CSCD_INIT;
58d5eaec
MCC		 2746 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2747 if (status < 0)
2748 break;
2749 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2750 if (status < 0)
2751 break;
126f1e61 2752
6cacdd46
DH		 2753 driverVersion = (((VERSION_MAJOR / 10) << 4) +
2754 (VERSION_MAJOR % 10)) << 24;
2755 driverVersion += (((VERSION_MINOR / 10) << 4) +
2756 (VERSION_MINOR % 10)) << 16;
2757 driverVersion += ((VERSION_PATCH / 1000) << 12) +
2758 ((VERSION_PATCH / 100) << 8) +
2759 ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
126f1e61 2760
58d5eaec
MCC		 2761 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2762 if (status < 0)
2763 break;
126f1e61 2764
58d5eaec
MCC		 2765 status = StopOC(state);
2766 if (status < 0)
2767 break;
126f1e61
RM		 2768
2769 state->drxd_state = DRXD_STOPPED;
6cacdd46
DH		 2770 state->init_done = 1;
2771 status = 0;
126f1e61
RM		 2772 } while (0);
2773 return status;
2774}
2775
8b35c2fe 2776static int DRXD_status(struct drxd_state *state, u32 *pLockStatus)
126f1e61
RM		 2777{
2778 DRX_GetLockStatus(state, pLockStatus);
2779
6cacdd46
DH		 2780 /*if (*pLockStatus&DRX_LOCK_MPEG) */
2781 if (*pLockStatus & DRX_LOCK_FEC) {
126f1e61
RM		 2782 ConfigureMPEGOutput(state, 1);
2783 /* Get status again, in case we have MPEG lock now */
6cacdd46 2784 /*DRX_GetLockStatus(state, pLockStatus); */
126f1e61
RM		 2785 }
2786
2787 return 0;
2788}
2789
2790/****************************************************************************/
2791/****************************************************************************/
2792/****************************************************************************/
2793
6cacdd46 2794static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
126f1e61
RM		 2795{
2796 struct drxd_state *state = fe->demodulator_priv;
2797 u32 value;
2798 int res;
2799
6cacdd46
DH		 2800 res = ReadIFAgc(state, &value);
2801 if (res < 0)
2802 *strength = 0;
126f1e61 2803 else
6cacdd46 2804 *strength = 0xffff - (value << 4);
126f1e61
RM		 2805 return 0;
2806}
2807
0df289a2 2808static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status)
126f1e61
RM		 2809{
2810 struct drxd_state *state = fe->demodulator_priv;
2811 u32 lock;
2812
2813 DRXD_status(state, &lock);
6cacdd46 2814 *status = 0;
126f1e61
RM		 2815 /* No MPEG lock in V255 firmware, bug ? */
2816#if 1
6cacdd46
DH		 2817 if (lock & DRX_LOCK_MPEG)
2818 *status |= FE_HAS_LOCK;
126f1e61 2819#else
6cacdd46
DH		 2820 if (lock & DRX_LOCK_FEC)
2821 *status |= FE_HAS_LOCK;
126f1e61 2822#endif
6cacdd46
DH		 2823 if (lock & DRX_LOCK_FEC)
2824 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2825 if (lock & DRX_LOCK_DEMOD)
2826 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
126f1e61
RM		 2827
2828 return 0;
2829}
2830
2831static int drxd_init(struct dvb_frontend *fe)
2832{
6cacdd46 2833 struct drxd_state *state = fe->demodulator_priv;
126f1e61 2834
843e44a1 2835 return DRXD_init(state, NULL, 0);
126f1e61
RM		 2836}
2837
619c027d 2838static int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
126f1e61 2839{
6cacdd46 2840 struct drxd_state *state = fe->demodulator_priv;
126f1e61 2841
6b142b3c
DH		 2842 if (state->config.disable_i2c_gate_ctrl == 1)
2843 return 0;
2844
126f1e61
RM		 2845 return DRX_ConfigureI2CBridge(state, onoff);
2846}
2847
2848static int drxd_get_tune_settings(struct dvb_frontend *fe,
6cacdd46 2849 struct dvb_frontend_tune_settings *sets)
126f1e61 2850{
6cacdd46
DH		 2851 sets->min_delay_ms = 10000;
2852 sets->max_drift = 0;
2853 sets->step_size = 0;
126f1e61
RM		 2854 return 0;
2855}
2856
6cacdd46 2857static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
126f1e61
RM		 2858{
2859 *ber = 0;
2860 return 0;
2861}
2862
6cacdd46 2863static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
126f1e61 2864{
6cacdd46 2865 *snr = 0;
126f1e61
RM		 2866 return 0;
2867}
2868
6cacdd46 2869static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
126f1e61 2870{
6cacdd46 2871 *ucblocks = 0;
126f1e61
RM		 2872 return 0;
2873}
2874
6cacdd46 2875static int drxd_sleep(struct dvb_frontend *fe)
126f1e61 2876{
6cacdd46 2877 struct drxd_state *state = fe->demodulator_priv;
126f1e61
RM		 2878
2879 ConfigureMPEGOutput(state, 0);
2880 return 0;
2881}
2882
6cacdd46 2883static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
126f1e61
RM		 2884{
2885 return drxd_config_i2c(fe, enable);
2886}
2887
9f97c288 2888static int drxd_set_frontend(struct dvb_frontend *fe)
126f1e61 2889{
9f97c288 2890 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6cacdd46
DH		 2891 struct drxd_state *state = fe->demodulator_priv;
2892 s32 off = 0;
126f1e61 2893
9f97c288 2894 state->props = *p;
126f1e61
RM		 2895 DRX_Stop(state);
2896
2897 if (fe->ops.tuner_ops.set_params) {
14d24d14 2898 fe->ops.tuner_ops.set_params(fe);
126f1e61
RM		 2899 if (fe->ops.i2c_gate_ctrl)
2900 fe->ops.i2c_gate_ctrl(fe, 0);
2901 }
2902
126f1e61
RM		 2903 msleep(200);
2904
2905 return DRX_Start(state, off);
2906}
2907
126f1e61
RM		 2908static void drxd_release(struct dvb_frontend *fe)
2909{
2910 struct drxd_state *state = fe->demodulator_priv;
2911
2912 kfree(state);
2913}
2914
2915static struct dvb_frontend_ops drxd_ops = {
9f97c288 2916 .delsys = { SYS_DVBT},
126f1e61 2917 .info = {
6cacdd46 2918 .name = "Micronas DRXD DVB-T",
6cacdd46
DH		 2919 .frequency_min = 47125000,
2920 .frequency_max = 855250000,
2921 .frequency_stepsize = 166667,
2922 .frequency_tolerance = 0,
2923 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2924 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2925 FE_CAN_FEC_AUTO |
2926 FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2927 FE_CAN_QAM_AUTO |
2928 FE_CAN_TRANSMISSION_MODE_AUTO |
2929 FE_CAN_GUARD_INTERVAL_AUTO |
2930 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
126f1e61
RM		 2931
2932 .release = drxd_release,
2933 .init = drxd_init,
2934 .sleep = drxd_sleep,
2935 .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2936
9f97c288 2937 .set_frontend = drxd_set_frontend,
126f1e61
RM		 2938 .get_tune_settings = drxd_get_tune_settings,
2939
2940 .read_status = drxd_read_status,
2941 .read_ber = drxd_read_ber,
2942 .read_signal_strength = drxd_read_signal_strength,
2943 .read_snr = drxd_read_snr,
2944 .read_ucblocks = drxd_read_ucblocks,
2945};
2946
2947struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2948 void *priv, struct i2c_adapter *i2c,
2949 struct device *dev)
2950{
2951 struct drxd_state *state = NULL;
2952
6cacdd46 2953 state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL);
126f1e61
RM		 2954 if (!state)
2955 return NULL;
2956 memset(state, 0, sizeof(*state));
2957
ee45ddc1 2958 state->ops = drxd_ops;
6cacdd46
DH		 2959 state->dev = dev;
2960 state->config = *config;
2961 state->i2c = i2c;
2962 state->priv = priv;
126f1e61 2963
834751d4 2964 mutex_init(&state->mutex);
126f1e61 2965
843e44a1 2966 if (Read16(state, 0, NULL, 0) < 0)
126f1e61
RM		 2967 goto error;
2968
ee45ddc1 2969 state->frontend.ops = drxd_ops;
6cacdd46 2970 state->frontend.demodulator_priv = state;
126f1e61 2971 ConfigureMPEGOutput(state, 0);
e7c953d2
PC		 2972 /* add few initialization to allow gate control */
2973 CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2974 InitHI(state);
2975
126f1e61
RM		 2976 return &state->frontend;
2977
2978error:
9999daf4 2979 printk(KERN_ERR "drxd: not found\n");
126f1e61
RM		 2980 kfree(state);
2981 return NULL;
2982}
9999daf4 2983EXPORT_SYMBOL(drxd_attach);
126f1e61
RM		 2984
2985MODULE_DESCRIPTION("DRXD driver");
2986MODULE_AUTHOR("Micronas");
2987MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)