Commit | Line | Data |
---|---|---|
2ad51576 | 1 | // SPDX-License-Identifier: GPL-2.0 |
340a614a HD |
2 | /* |
3 | * OMAP mailbox driver | |
4 | * | |
f48cca87 | 5 | * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved. |
4899f78a | 6 | * Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com |
340a614a | 7 | * |
f48cca87 | 8 | * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> |
5040f534 | 9 | * Suman Anna <s-anna@ti.com> |
340a614a HD |
10 | */ |
11 | ||
340a614a | 12 | #include <linux/interrupt.h> |
b3e69146 FC |
13 | #include <linux/spinlock.h> |
14 | #include <linux/mutex.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
b5bebe41 OBC |
16 | #include <linux/kfifo.h> |
17 | #include <linux/err.h> | |
73017a54 | 18 | #include <linux/module.h> |
75288cc6 | 19 | #include <linux/of_device.h> |
5040f534 SA |
20 | #include <linux/platform_device.h> |
21 | #include <linux/pm_runtime.h> | |
5040f534 | 22 | #include <linux/omap-mailbox.h> |
8841a66a SA |
23 | #include <linux/mailbox_controller.h> |
24 | #include <linux/mailbox_client.h> | |
5040f534 | 25 | |
8e3c5952 DG |
26 | #include "mailbox.h" |
27 | ||
5040f534 SA |
28 | #define MAILBOX_REVISION 0x000 |
29 | #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) | |
30 | #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) | |
31 | #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) | |
32 | ||
33 | #define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u)) | |
34 | #define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u)) | |
35 | ||
36 | #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u)) | |
37 | #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u)) | |
38 | #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u)) | |
39 | ||
40 | #define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \ | |
41 | OMAP2_MAILBOX_IRQSTATUS(u)) | |
42 | #define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \ | |
43 | OMAP2_MAILBOX_IRQENABLE(u)) | |
44 | #define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \ | |
45 | : OMAP2_MAILBOX_IRQENABLE(u)) | |
46 | ||
47 | #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m))) | |
48 | #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1)) | |
49 | ||
4899f78a SA |
50 | /* Interrupt register configuration types */ |
51 | #define MBOX_INTR_CFG_TYPE1 0 | |
52 | #define MBOX_INTR_CFG_TYPE2 1 | |
53 | ||
5040f534 SA |
54 | struct omap_mbox_fifo { |
55 | unsigned long msg; | |
56 | unsigned long fifo_stat; | |
57 | unsigned long msg_stat; | |
5040f534 SA |
58 | unsigned long irqenable; |
59 | unsigned long irqstatus; | |
5040f534 | 60 | unsigned long irqdisable; |
be3322eb | 61 | u32 intr_bit; |
5040f534 SA |
62 | }; |
63 | ||
64 | struct omap_mbox_queue { | |
65 | spinlock_t lock; | |
66 | struct kfifo fifo; | |
67 | struct work_struct work; | |
5040f534 SA |
68 | struct omap_mbox *mbox; |
69 | bool full; | |
70 | }; | |
71 | ||
ea2ec1e8 SA |
72 | struct omap_mbox_match_data { |
73 | u32 intr_type; | |
74 | }; | |
75 | ||
72c1c817 SA |
76 | struct omap_mbox_device { |
77 | struct device *dev; | |
78 | struct mutex cfg_lock; | |
79 | void __iomem *mbox_base; | |
af1d2f5c | 80 | u32 *irq_ctx; |
72c1c817 SA |
81 | u32 num_users; |
82 | u32 num_fifos; | |
2240f8ae | 83 | u32 intr_type; |
72c1c817 | 84 | struct omap_mbox **mboxes; |
8841a66a | 85 | struct mbox_controller controller; |
72c1c817 SA |
86 | struct list_head elem; |
87 | }; | |
88 | ||
75288cc6 SA |
89 | struct omap_mbox_fifo_info { |
90 | int tx_id; | |
91 | int tx_usr; | |
92 | int tx_irq; | |
93 | ||
94 | int rx_id; | |
95 | int rx_usr; | |
96 | int rx_irq; | |
97 | ||
98 | const char *name; | |
8e3c5952 | 99 | bool send_no_irq; |
75288cc6 SA |
100 | }; |
101 | ||
5040f534 SA |
102 | struct omap_mbox { |
103 | const char *name; | |
104 | int irq; | |
8841a66a | 105 | struct omap_mbox_queue *rxq; |
5040f534 | 106 | struct device *dev; |
72c1c817 | 107 | struct omap_mbox_device *parent; |
be3322eb SA |
108 | struct omap_mbox_fifo tx_fifo; |
109 | struct omap_mbox_fifo rx_fifo; | |
be3322eb | 110 | u32 intr_type; |
8841a66a | 111 | struct mbox_chan *chan; |
8e3c5952 | 112 | bool send_no_irq; |
5040f534 SA |
113 | }; |
114 | ||
72c1c817 SA |
115 | /* global variables for the mailbox devices */ |
116 | static DEFINE_MUTEX(omap_mbox_devices_lock); | |
117 | static LIST_HEAD(omap_mbox_devices); | |
5f00ec64 | 118 | |
b5bebe41 OBC |
119 | static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE; |
120 | module_param(mbox_kfifo_size, uint, S_IRUGO); | |
121 | MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)"); | |
122 | ||
8841a66a SA |
123 | static struct omap_mbox *mbox_chan_to_omap_mbox(struct mbox_chan *chan) |
124 | { | |
125 | if (!chan || !chan->con_priv) | |
126 | return NULL; | |
127 | ||
128 | return (struct omap_mbox *)chan->con_priv; | |
129 | } | |
130 | ||
72c1c817 SA |
131 | static inline |
132 | unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs) | |
5040f534 | 133 | { |
72c1c817 | 134 | return __raw_readl(mdev->mbox_base + ofs); |
5040f534 SA |
135 | } |
136 | ||
72c1c817 SA |
137 | static inline |
138 | void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs) | |
5040f534 | 139 | { |
72c1c817 | 140 | __raw_writel(val, mdev->mbox_base + ofs); |
5040f534 SA |
141 | } |
142 | ||
9ae0ee00 | 143 | /* Mailbox FIFO handle functions */ |
5040f534 | 144 | static mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox) |
9ae0ee00 | 145 | { |
be3322eb | 146 | struct omap_mbox_fifo *fifo = &mbox->rx_fifo; |
2665a4c1 SA |
147 | |
148 | return (mbox_msg_t)mbox_read_reg(mbox->parent, fifo->msg); | |
9ae0ee00 | 149 | } |
5040f534 SA |
150 | |
151 | static void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) | |
9ae0ee00 | 152 | { |
be3322eb | 153 | struct omap_mbox_fifo *fifo = &mbox->tx_fifo; |
2665a4c1 | 154 | |
72c1c817 | 155 | mbox_write_reg(mbox->parent, msg, fifo->msg); |
9ae0ee00 | 156 | } |
5040f534 SA |
157 | |
158 | static int mbox_fifo_empty(struct omap_mbox *mbox) | |
9ae0ee00 | 159 | { |
be3322eb | 160 | struct omap_mbox_fifo *fifo = &mbox->rx_fifo; |
2665a4c1 | 161 | |
72c1c817 | 162 | return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0); |
9ae0ee00 | 163 | } |
5040f534 SA |
164 | |
165 | static int mbox_fifo_full(struct omap_mbox *mbox) | |
9ae0ee00 | 166 | { |
be3322eb | 167 | struct omap_mbox_fifo *fifo = &mbox->tx_fifo; |
2665a4c1 | 168 | |
72c1c817 | 169 | return mbox_read_reg(mbox->parent, fifo->fifo_stat); |
9ae0ee00 HD |
170 | } |
171 | ||
172 | /* Mailbox IRQ handle functions */ | |
5040f534 | 173 | static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) |
9ae0ee00 | 174 | { |
be3322eb SA |
175 | struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? |
176 | &mbox->tx_fifo : &mbox->rx_fifo; | |
177 | u32 bit = fifo->intr_bit; | |
178 | u32 irqstatus = fifo->irqstatus; | |
5040f534 | 179 | |
72c1c817 | 180 | mbox_write_reg(mbox->parent, bit, irqstatus); |
5040f534 SA |
181 | |
182 | /* Flush posted write for irq status to avoid spurious interrupts */ | |
72c1c817 | 183 | mbox_read_reg(mbox->parent, irqstatus); |
9ae0ee00 | 184 | } |
5040f534 SA |
185 | |
186 | static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | |
9ae0ee00 | 187 | { |
be3322eb SA |
188 | struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? |
189 | &mbox->tx_fifo : &mbox->rx_fifo; | |
190 | u32 bit = fifo->intr_bit; | |
191 | u32 irqenable = fifo->irqenable; | |
192 | u32 irqstatus = fifo->irqstatus; | |
193 | ||
72c1c817 SA |
194 | u32 enable = mbox_read_reg(mbox->parent, irqenable); |
195 | u32 status = mbox_read_reg(mbox->parent, irqstatus); | |
5040f534 SA |
196 | |
197 | return (int)(enable & status & bit); | |
9ae0ee00 HD |
198 | } |
199 | ||
8841a66a | 200 | static void _omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) |
c869c75c | 201 | { |
be3322eb SA |
202 | u32 l; |
203 | struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? | |
204 | &mbox->tx_fifo : &mbox->rx_fifo; | |
205 | u32 bit = fifo->intr_bit; | |
206 | u32 irqenable = fifo->irqenable; | |
5040f534 | 207 | |
72c1c817 | 208 | l = mbox_read_reg(mbox->parent, irqenable); |
5040f534 | 209 | l |= bit; |
72c1c817 | 210 | mbox_write_reg(mbox->parent, l, irqenable); |
c869c75c | 211 | } |
c869c75c | 212 | |
8841a66a | 213 | static void _omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) |
c869c75c | 214 | { |
be3322eb SA |
215 | struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? |
216 | &mbox->tx_fifo : &mbox->rx_fifo; | |
217 | u32 bit = fifo->intr_bit; | |
218 | u32 irqdisable = fifo->irqdisable; | |
5040f534 SA |
219 | |
220 | /* | |
221 | * Read and update the interrupt configuration register for pre-OMAP4. | |
222 | * OMAP4 and later SoCs have a dedicated interrupt disabling register. | |
223 | */ | |
be3322eb | 224 | if (!mbox->intr_type) |
72c1c817 | 225 | bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit; |
5040f534 | 226 | |
72c1c817 | 227 | mbox_write_reg(mbox->parent, bit, irqdisable); |
c869c75c | 228 | } |
c869c75c | 229 | |
8841a66a | 230 | void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq) |
340a614a | 231 | { |
8841a66a | 232 | struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); |
340a614a | 233 | |
8841a66a SA |
234 | if (WARN_ON(!mbox)) |
235 | return; | |
b5bebe41 | 236 | |
8841a66a SA |
237 | _omap_mbox_enable_irq(mbox, irq); |
238 | } | |
239 | EXPORT_SYMBOL(omap_mbox_enable_irq); | |
b5bebe41 | 240 | |
8841a66a SA |
241 | void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq) |
242 | { | |
243 | struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); | |
244 | ||
245 | if (WARN_ON(!mbox)) | |
246 | return; | |
247 | ||
248 | _omap_mbox_disable_irq(mbox, irq); | |
340a614a | 249 | } |
8841a66a | 250 | EXPORT_SYMBOL(omap_mbox_disable_irq); |
340a614a HD |
251 | |
252 | /* | |
253 | * Message receiver(workqueue) | |
254 | */ | |
255 | static void mbox_rx_work(struct work_struct *work) | |
256 | { | |
257 | struct omap_mbox_queue *mq = | |
258 | container_of(work, struct omap_mbox_queue, work); | |
340a614a | 259 | mbox_msg_t msg; |
b5bebe41 OBC |
260 | int len; |
261 | ||
262 | while (kfifo_len(&mq->fifo) >= sizeof(msg)) { | |
263 | len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); | |
264 | WARN_ON(len != sizeof(msg)); | |
340a614a | 265 | |
8841a66a | 266 | mbox_chan_received_data(mq->mbox->chan, (void *)msg); |
d2295042 FGL |
267 | spin_lock_irq(&mq->lock); |
268 | if (mq->full) { | |
269 | mq->full = false; | |
8841a66a | 270 | _omap_mbox_enable_irq(mq->mbox, IRQ_RX); |
d2295042 FGL |
271 | } |
272 | spin_unlock_irq(&mq->lock); | |
340a614a HD |
273 | } |
274 | } | |
275 | ||
276 | /* | |
277 | * Mailbox interrupt handler | |
278 | */ | |
340a614a HD |
279 | static void __mbox_tx_interrupt(struct omap_mbox *mbox) |
280 | { | |
8841a66a | 281 | _omap_mbox_disable_irq(mbox, IRQ_TX); |
340a614a | 282 | ack_mbox_irq(mbox, IRQ_TX); |
8841a66a | 283 | mbox_chan_txdone(mbox->chan, 0); |
340a614a HD |
284 | } |
285 | ||
286 | static void __mbox_rx_interrupt(struct omap_mbox *mbox) | |
287 | { | |
b5bebe41 | 288 | struct omap_mbox_queue *mq = mbox->rxq; |
340a614a | 289 | mbox_msg_t msg; |
b5bebe41 | 290 | int len; |
340a614a | 291 | |
340a614a | 292 | while (!mbox_fifo_empty(mbox)) { |
b5bebe41 | 293 | if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) { |
8841a66a | 294 | _omap_mbox_disable_irq(mbox, IRQ_RX); |
d2295042 | 295 | mq->full = true; |
340a614a | 296 | goto nomem; |
1ea5d6d1 | 297 | } |
340a614a HD |
298 | |
299 | msg = mbox_fifo_read(mbox); | |
340a614a | 300 | |
b5bebe41 OBC |
301 | len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); |
302 | WARN_ON(len != sizeof(msg)); | |
340a614a HD |
303 | } |
304 | ||
305 | /* no more messages in the fifo. clear IRQ source. */ | |
306 | ack_mbox_irq(mbox, IRQ_RX); | |
f48cca87 | 307 | nomem: |
c4873005 | 308 | schedule_work(&mbox->rxq->work); |
340a614a HD |
309 | } |
310 | ||
311 | static irqreturn_t mbox_interrupt(int irq, void *p) | |
312 | { | |
2a7057e3 | 313 | struct omap_mbox *mbox = p; |
340a614a HD |
314 | |
315 | if (is_mbox_irq(mbox, IRQ_TX)) | |
316 | __mbox_tx_interrupt(mbox); | |
317 | ||
318 | if (is_mbox_irq(mbox, IRQ_RX)) | |
319 | __mbox_rx_interrupt(mbox); | |
320 | ||
321 | return IRQ_HANDLED; | |
322 | } | |
323 | ||
340a614a | 324 | static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, |
8841a66a | 325 | void (*work)(struct work_struct *)) |
340a614a | 326 | { |
340a614a HD |
327 | struct omap_mbox_queue *mq; |
328 | ||
8841a66a SA |
329 | if (!work) |
330 | return NULL; | |
331 | ||
86f6f5e2 | 332 | mq = kzalloc(sizeof(*mq), GFP_KERNEL); |
340a614a HD |
333 | if (!mq) |
334 | return NULL; | |
335 | ||
336 | spin_lock_init(&mq->lock); | |
337 | ||
b5bebe41 | 338 | if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL)) |
340a614a | 339 | goto error; |
340a614a | 340 | |
8841a66a | 341 | INIT_WORK(&mq->work, work); |
340a614a | 342 | return mq; |
8841a66a | 343 | |
340a614a HD |
344 | error: |
345 | kfree(mq); | |
346 | return NULL; | |
347 | } | |
348 | ||
349 | static void mbox_queue_free(struct omap_mbox_queue *q) | |
350 | { | |
b5bebe41 | 351 | kfifo_free(&q->fifo); |
340a614a HD |
352 | kfree(q); |
353 | } | |
354 | ||
c7c158e5 | 355 | static int omap_mbox_startup(struct omap_mbox *mbox) |
340a614a | 356 | { |
5f00ec64 | 357 | int ret = 0; |
340a614a HD |
358 | struct omap_mbox_queue *mq; |
359 | ||
8841a66a SA |
360 | mq = mbox_queue_alloc(mbox, mbox_rx_work); |
361 | if (!mq) | |
362 | return -ENOMEM; | |
363 | mbox->rxq = mq; | |
364 | mq->mbox = mbox; | |
365 | ||
366 | ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, | |
367 | mbox->name, mbox); | |
368 | if (unlikely(ret)) { | |
369 | pr_err("failed to register mailbox interrupt:%d\n", ret); | |
370 | goto fail_request_irq; | |
371 | } | |
340a614a | 372 | |
8e3c5952 DG |
373 | if (mbox->send_no_irq) |
374 | mbox->chan->txdone_method = TXDONE_BY_ACK; | |
375 | ||
8841a66a | 376 | _omap_mbox_enable_irq(mbox, IRQ_RX); |
1d8a0e96 | 377 | |
340a614a HD |
378 | return 0; |
379 | ||
ecf305cf SA |
380 | fail_request_irq: |
381 | mbox_queue_free(mbox->rxq); | |
340a614a HD |
382 | return ret; |
383 | } | |
384 | ||
385 | static void omap_mbox_fini(struct omap_mbox *mbox) | |
386 | { | |
8841a66a SA |
387 | _omap_mbox_disable_irq(mbox, IRQ_RX); |
388 | free_irq(mbox->irq, mbox); | |
389 | flush_work(&mbox->rxq->work); | |
390 | mbox_queue_free(mbox->rxq); | |
340a614a HD |
391 | } |
392 | ||
72c1c817 SA |
393 | static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev, |
394 | const char *mbox_name) | |
340a614a | 395 | { |
c0377320 | 396 | struct omap_mbox *_mbox, *mbox = NULL; |
72c1c817 SA |
397 | struct omap_mbox **mboxes = mdev->mboxes; |
398 | int i; | |
340a614a | 399 | |
9c80c8cd | 400 | if (!mboxes) |
72c1c817 | 401 | return NULL; |
340a614a | 402 | |
c0377320 | 403 | for (i = 0; (_mbox = mboxes[i]); i++) { |
72c1c817 | 404 | if (!strcmp(_mbox->name, mbox_name)) { |
c0377320 | 405 | mbox = _mbox; |
9c80c8cd | 406 | break; |
c0377320 KH |
407 | } |
408 | } | |
72c1c817 SA |
409 | return mbox; |
410 | } | |
411 | ||
8841a66a SA |
412 | struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl, |
413 | const char *chan_name) | |
72c1c817 | 414 | { |
8841a66a | 415 | struct device *dev = cl->dev; |
72c1c817 SA |
416 | struct omap_mbox *mbox = NULL; |
417 | struct omap_mbox_device *mdev; | |
8841a66a SA |
418 | struct mbox_chan *chan; |
419 | unsigned long flags; | |
72c1c817 SA |
420 | int ret; |
421 | ||
8841a66a SA |
422 | if (!dev) |
423 | return ERR_PTR(-ENODEV); | |
424 | ||
425 | if (dev->of_node) { | |
426 | pr_err("%s: please use mbox_request_channel(), this API is supported only for OMAP non-DT usage\n", | |
427 | __func__); | |
428 | return ERR_PTR(-ENODEV); | |
429 | } | |
430 | ||
72c1c817 SA |
431 | mutex_lock(&omap_mbox_devices_lock); |
432 | list_for_each_entry(mdev, &omap_mbox_devices, elem) { | |
8841a66a | 433 | mbox = omap_mbox_device_find(mdev, chan_name); |
72c1c817 SA |
434 | if (mbox) |
435 | break; | |
436 | } | |
437 | mutex_unlock(&omap_mbox_devices_lock); | |
9c80c8cd | 438 | |
8841a66a | 439 | if (!mbox || !mbox->chan) |
9c80c8cd | 440 | return ERR_PTR(-ENOENT); |
340a614a | 441 | |
8841a66a SA |
442 | chan = mbox->chan; |
443 | spin_lock_irqsave(&chan->lock, flags); | |
444 | chan->msg_free = 0; | |
445 | chan->msg_count = 0; | |
446 | chan->active_req = NULL; | |
447 | chan->cl = cl; | |
448 | init_completion(&chan->tx_complete); | |
449 | spin_unlock_irqrestore(&chan->lock, flags); | |
58256307 | 450 | |
8841a66a | 451 | ret = chan->mbox->ops->startup(chan); |
1d8a0e96 | 452 | if (ret) { |
8841a66a SA |
453 | pr_err("Unable to startup the chan (%d)\n", ret); |
454 | mbox_free_channel(chan); | |
455 | chan = ERR_PTR(ret); | |
1d8a0e96 JG |
456 | } |
457 | ||
8841a66a | 458 | return chan; |
340a614a | 459 | } |
8841a66a | 460 | EXPORT_SYMBOL(omap_mbox_request_channel); |
340a614a | 461 | |
6b233985 HD |
462 | static struct class omap_mbox_class = { .name = "mbox", }; |
463 | ||
72c1c817 | 464 | static int omap_mbox_register(struct omap_mbox_device *mdev) |
340a614a | 465 | { |
9c80c8cd FC |
466 | int ret; |
467 | int i; | |
72c1c817 | 468 | struct omap_mbox **mboxes; |
340a614a | 469 | |
72c1c817 | 470 | if (!mdev || !mdev->mboxes) |
340a614a | 471 | return -EINVAL; |
340a614a | 472 | |
72c1c817 | 473 | mboxes = mdev->mboxes; |
9c80c8cd FC |
474 | for (i = 0; mboxes[i]; i++) { |
475 | struct omap_mbox *mbox = mboxes[i]; | |
2665a4c1 | 476 | |
8841a66a SA |
477 | mbox->dev = device_create(&omap_mbox_class, mdev->dev, |
478 | 0, mbox, "%s", mbox->name); | |
9c80c8cd FC |
479 | if (IS_ERR(mbox->dev)) { |
480 | ret = PTR_ERR(mbox->dev); | |
481 | goto err_out; | |
482 | } | |
483 | } | |
72c1c817 SA |
484 | |
485 | mutex_lock(&omap_mbox_devices_lock); | |
486 | list_add(&mdev->elem, &omap_mbox_devices); | |
487 | mutex_unlock(&omap_mbox_devices_lock); | |
488 | ||
a3abf436 | 489 | ret = devm_mbox_controller_register(mdev->dev, &mdev->controller); |
f48cca87 | 490 | |
9c80c8cd | 491 | err_out: |
8841a66a SA |
492 | if (ret) { |
493 | while (i--) | |
494 | device_unregister(mboxes[i]->dev); | |
495 | } | |
340a614a HD |
496 | return ret; |
497 | } | |
340a614a | 498 | |
72c1c817 | 499 | static int omap_mbox_unregister(struct omap_mbox_device *mdev) |
340a614a | 500 | { |
9c80c8cd | 501 | int i; |
72c1c817 | 502 | struct omap_mbox **mboxes; |
340a614a | 503 | |
72c1c817 | 504 | if (!mdev || !mdev->mboxes) |
9c80c8cd FC |
505 | return -EINVAL; |
506 | ||
72c1c817 SA |
507 | mutex_lock(&omap_mbox_devices_lock); |
508 | list_del(&mdev->elem); | |
509 | mutex_unlock(&omap_mbox_devices_lock); | |
510 | ||
511 | mboxes = mdev->mboxes; | |
9c80c8cd FC |
512 | for (i = 0; mboxes[i]; i++) |
513 | device_unregister(mboxes[i]->dev); | |
9c80c8cd | 514 | return 0; |
340a614a | 515 | } |
5040f534 | 516 | |
8841a66a SA |
517 | static int omap_mbox_chan_startup(struct mbox_chan *chan) |
518 | { | |
519 | struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); | |
520 | struct omap_mbox_device *mdev = mbox->parent; | |
521 | int ret = 0; | |
522 | ||
523 | mutex_lock(&mdev->cfg_lock); | |
524 | pm_runtime_get_sync(mdev->dev); | |
525 | ret = omap_mbox_startup(mbox); | |
526 | if (ret) | |
527 | pm_runtime_put_sync(mdev->dev); | |
528 | mutex_unlock(&mdev->cfg_lock); | |
529 | return ret; | |
530 | } | |
531 | ||
532 | static void omap_mbox_chan_shutdown(struct mbox_chan *chan) | |
533 | { | |
534 | struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); | |
535 | struct omap_mbox_device *mdev = mbox->parent; | |
536 | ||
537 | mutex_lock(&mdev->cfg_lock); | |
538 | omap_mbox_fini(mbox); | |
539 | pm_runtime_put_sync(mdev->dev); | |
540 | mutex_unlock(&mdev->cfg_lock); | |
541 | } | |
542 | ||
8e3c5952 | 543 | static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data) |
8841a66a | 544 | { |
8841a66a SA |
545 | int ret = -EBUSY; |
546 | ||
8e3c5952 DG |
547 | if (!mbox_fifo_full(mbox)) { |
548 | _omap_mbox_enable_irq(mbox, IRQ_RX); | |
549 | mbox_fifo_write(mbox, (mbox_msg_t)data); | |
550 | ret = 0; | |
551 | _omap_mbox_disable_irq(mbox, IRQ_RX); | |
552 | ||
553 | /* we must read and ack the interrupt directly from here */ | |
554 | mbox_fifo_read(mbox); | |
555 | ack_mbox_irq(mbox, IRQ_RX); | |
556 | } | |
557 | ||
558 | return ret; | |
559 | } | |
560 | ||
561 | static int omap_mbox_chan_send(struct omap_mbox *mbox, void *data) | |
562 | { | |
563 | int ret = -EBUSY; | |
8841a66a SA |
564 | |
565 | if (!mbox_fifo_full(mbox)) { | |
566 | mbox_fifo_write(mbox, (mbox_msg_t)data); | |
567 | ret = 0; | |
568 | } | |
569 | ||
570 | /* always enable the interrupt */ | |
571 | _omap_mbox_enable_irq(mbox, IRQ_TX); | |
572 | return ret; | |
573 | } | |
574 | ||
8e3c5952 DG |
575 | static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data) |
576 | { | |
577 | struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); | |
578 | int ret; | |
579 | ||
580 | if (!mbox) | |
581 | return -EINVAL; | |
582 | ||
583 | if (mbox->send_no_irq) | |
584 | ret = omap_mbox_chan_send_noirq(mbox, data); | |
585 | else | |
586 | ret = omap_mbox_chan_send(mbox, data); | |
587 | ||
588 | return ret; | |
589 | } | |
590 | ||
05ae7975 | 591 | static const struct mbox_chan_ops omap_mbox_chan_ops = { |
8841a66a SA |
592 | .startup = omap_mbox_chan_startup, |
593 | .send_data = omap_mbox_chan_send_data, | |
594 | .shutdown = omap_mbox_chan_shutdown, | |
595 | }; | |
596 | ||
af1d2f5c SA |
597 | #ifdef CONFIG_PM_SLEEP |
598 | static int omap_mbox_suspend(struct device *dev) | |
599 | { | |
600 | struct omap_mbox_device *mdev = dev_get_drvdata(dev); | |
9f0cee98 | 601 | u32 usr, fifo, reg; |
af1d2f5c SA |
602 | |
603 | if (pm_runtime_status_suspended(dev)) | |
604 | return 0; | |
605 | ||
9f0cee98 SA |
606 | for (fifo = 0; fifo < mdev->num_fifos; fifo++) { |
607 | if (mbox_read_reg(mdev, MAILBOX_MSGSTATUS(fifo))) { | |
608 | dev_err(mdev->dev, "fifo %d has unexpected unread messages\n", | |
609 | fifo); | |
610 | return -EBUSY; | |
611 | } | |
612 | } | |
613 | ||
af1d2f5c SA |
614 | for (usr = 0; usr < mdev->num_users; usr++) { |
615 | reg = MAILBOX_IRQENABLE(mdev->intr_type, usr); | |
616 | mdev->irq_ctx[usr] = mbox_read_reg(mdev, reg); | |
617 | } | |
618 | ||
619 | return 0; | |
620 | } | |
621 | ||
622 | static int omap_mbox_resume(struct device *dev) | |
623 | { | |
624 | struct omap_mbox_device *mdev = dev_get_drvdata(dev); | |
625 | u32 usr, reg; | |
626 | ||
627 | if (pm_runtime_status_suspended(dev)) | |
628 | return 0; | |
629 | ||
630 | for (usr = 0; usr < mdev->num_users; usr++) { | |
631 | reg = MAILBOX_IRQENABLE(mdev->intr_type, usr); | |
632 | mbox_write_reg(mdev, mdev->irq_ctx[usr], reg); | |
633 | } | |
634 | ||
635 | return 0; | |
636 | } | |
637 | #endif | |
638 | ||
639 | static const struct dev_pm_ops omap_mbox_pm_ops = { | |
640 | SET_SYSTEM_SLEEP_PM_OPS(omap_mbox_suspend, omap_mbox_resume) | |
641 | }; | |
642 | ||
ea2ec1e8 SA |
643 | static const struct omap_mbox_match_data omap2_data = { MBOX_INTR_CFG_TYPE1 }; |
644 | static const struct omap_mbox_match_data omap4_data = { MBOX_INTR_CFG_TYPE2 }; | |
645 | ||
75288cc6 SA |
646 | static const struct of_device_id omap_mailbox_of_match[] = { |
647 | { | |
648 | .compatible = "ti,omap2-mailbox", | |
ea2ec1e8 | 649 | .data = &omap2_data, |
75288cc6 SA |
650 | }, |
651 | { | |
652 | .compatible = "ti,omap3-mailbox", | |
ea2ec1e8 | 653 | .data = &omap2_data, |
75288cc6 SA |
654 | }, |
655 | { | |
656 | .compatible = "ti,omap4-mailbox", | |
ea2ec1e8 | 657 | .data = &omap4_data, |
75288cc6 SA |
658 | }, |
659 | { | |
660 | /* end */ | |
661 | }, | |
662 | }; | |
663 | MODULE_DEVICE_TABLE(of, omap_mailbox_of_match); | |
664 | ||
8841a66a SA |
665 | static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller, |
666 | const struct of_phandle_args *sp) | |
667 | { | |
668 | phandle phandle = sp->args[0]; | |
669 | struct device_node *node; | |
670 | struct omap_mbox_device *mdev; | |
671 | struct omap_mbox *mbox; | |
672 | ||
673 | mdev = container_of(controller, struct omap_mbox_device, controller); | |
674 | if (WARN_ON(!mdev)) | |
2d805fc1 | 675 | return ERR_PTR(-EINVAL); |
8841a66a SA |
676 | |
677 | node = of_find_node_by_phandle(phandle); | |
678 | if (!node) { | |
679 | pr_err("%s: could not find node phandle 0x%x\n", | |
680 | __func__, phandle); | |
2d805fc1 | 681 | return ERR_PTR(-ENODEV); |
8841a66a SA |
682 | } |
683 | ||
684 | mbox = omap_mbox_device_find(mdev, node->name); | |
685 | of_node_put(node); | |
2d805fc1 | 686 | return mbox ? mbox->chan : ERR_PTR(-ENOENT); |
8841a66a SA |
687 | } |
688 | ||
5040f534 SA |
689 | static int omap_mbox_probe(struct platform_device *pdev) |
690 | { | |
691 | struct resource *mem; | |
692 | int ret; | |
8841a66a | 693 | struct mbox_chan *chnls; |
5040f534 | 694 | struct omap_mbox **list, *mbox, *mboxblk; |
75288cc6 | 695 | struct omap_mbox_fifo_info *finfo, *finfoblk; |
72c1c817 | 696 | struct omap_mbox_device *mdev; |
be3322eb | 697 | struct omap_mbox_fifo *fifo; |
75288cc6 SA |
698 | struct device_node *node = pdev->dev.of_node; |
699 | struct device_node *child; | |
ea2ec1e8 | 700 | const struct omap_mbox_match_data *match_data; |
75288cc6 SA |
701 | u32 intr_type, info_count; |
702 | u32 num_users, num_fifos; | |
703 | u32 tmp[3]; | |
5040f534 SA |
704 | u32 l; |
705 | int i; | |
706 | ||
4899f78a SA |
707 | if (!node) { |
708 | pr_err("%s: only DT-based devices are supported\n", __func__); | |
5040f534 SA |
709 | return -ENODEV; |
710 | } | |
711 | ||
ea2ec1e8 SA |
712 | match_data = of_device_get_match_data(&pdev->dev); |
713 | if (!match_data) | |
4899f78a | 714 | return -ENODEV; |
ea2ec1e8 | 715 | intr_type = match_data->intr_type; |
75288cc6 | 716 | |
4899f78a SA |
717 | if (of_property_read_u32(node, "ti,mbox-num-users", &num_users)) |
718 | return -ENODEV; | |
75288cc6 | 719 | |
4899f78a SA |
720 | if (of_property_read_u32(node, "ti,mbox-num-fifos", &num_fifos)) |
721 | return -ENODEV; | |
75288cc6 | 722 | |
4899f78a SA |
723 | info_count = of_get_available_child_count(node); |
724 | if (!info_count) { | |
725 | dev_err(&pdev->dev, "no available mbox devices found\n"); | |
726 | return -ENODEV; | |
75288cc6 SA |
727 | } |
728 | ||
a86854d0 | 729 | finfoblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*finfoblk), |
75288cc6 SA |
730 | GFP_KERNEL); |
731 | if (!finfoblk) | |
732 | return -ENOMEM; | |
733 | ||
734 | finfo = finfoblk; | |
735 | child = NULL; | |
736 | for (i = 0; i < info_count; i++, finfo++) { | |
4899f78a SA |
737 | child = of_get_next_available_child(node, child); |
738 | ret = of_property_read_u32_array(child, "ti,mbox-tx", tmp, | |
739 | ARRAY_SIZE(tmp)); | |
740 | if (ret) | |
741 | return ret; | |
742 | finfo->tx_id = tmp[0]; | |
743 | finfo->tx_irq = tmp[1]; | |
744 | finfo->tx_usr = tmp[2]; | |
745 | ||
746 | ret = of_property_read_u32_array(child, "ti,mbox-rx", tmp, | |
747 | ARRAY_SIZE(tmp)); | |
748 | if (ret) | |
749 | return ret; | |
750 | finfo->rx_id = tmp[0]; | |
751 | finfo->rx_irq = tmp[1]; | |
752 | finfo->rx_usr = tmp[2]; | |
753 | ||
754 | finfo->name = child->name; | |
755 | ||
756 | if (of_find_property(child, "ti,mbox-send-noirq", NULL)) | |
757 | finfo->send_no_irq = true; | |
758 | ||
75288cc6 SA |
759 | if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos || |
760 | finfo->tx_usr >= num_users || finfo->rx_usr >= num_users) | |
761 | return -EINVAL; | |
762 | } | |
763 | ||
72c1c817 SA |
764 | mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL); |
765 | if (!mdev) | |
766 | return -ENOMEM; | |
767 | ||
768 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
769 | mdev->mbox_base = devm_ioremap_resource(&pdev->dev, mem); | |
770 | if (IS_ERR(mdev->mbox_base)) | |
771 | return PTR_ERR(mdev->mbox_base); | |
772 | ||
a86854d0 | 773 | mdev->irq_ctx = devm_kcalloc(&pdev->dev, num_users, sizeof(u32), |
af1d2f5c SA |
774 | GFP_KERNEL); |
775 | if (!mdev->irq_ctx) | |
776 | return -ENOMEM; | |
777 | ||
5040f534 | 778 | /* allocate one extra for marking end of list */ |
a86854d0 | 779 | list = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*list), |
5040f534 SA |
780 | GFP_KERNEL); |
781 | if (!list) | |
782 | return -ENOMEM; | |
783 | ||
a86854d0 | 784 | chnls = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*chnls), |
8841a66a SA |
785 | GFP_KERNEL); |
786 | if (!chnls) | |
787 | return -ENOMEM; | |
788 | ||
a86854d0 | 789 | mboxblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*mbox), |
5040f534 SA |
790 | GFP_KERNEL); |
791 | if (!mboxblk) | |
792 | return -ENOMEM; | |
793 | ||
5040f534 | 794 | mbox = mboxblk; |
75288cc6 SA |
795 | finfo = finfoblk; |
796 | for (i = 0; i < info_count; i++, finfo++) { | |
be3322eb | 797 | fifo = &mbox->tx_fifo; |
75288cc6 SA |
798 | fifo->msg = MAILBOX_MESSAGE(finfo->tx_id); |
799 | fifo->fifo_stat = MAILBOX_FIFOSTATUS(finfo->tx_id); | |
800 | fifo->intr_bit = MAILBOX_IRQ_NOTFULL(finfo->tx_id); | |
801 | fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->tx_usr); | |
802 | fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->tx_usr); | |
803 | fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->tx_usr); | |
be3322eb SA |
804 | |
805 | fifo = &mbox->rx_fifo; | |
75288cc6 SA |
806 | fifo->msg = MAILBOX_MESSAGE(finfo->rx_id); |
807 | fifo->msg_stat = MAILBOX_MSGSTATUS(finfo->rx_id); | |
808 | fifo->intr_bit = MAILBOX_IRQ_NEWMSG(finfo->rx_id); | |
809 | fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->rx_usr); | |
810 | fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->rx_usr); | |
811 | fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->rx_usr); | |
be3322eb | 812 | |
8e3c5952 | 813 | mbox->send_no_irq = finfo->send_no_irq; |
be3322eb SA |
814 | mbox->intr_type = intr_type; |
815 | ||
72c1c817 | 816 | mbox->parent = mdev; |
75288cc6 SA |
817 | mbox->name = finfo->name; |
818 | mbox->irq = platform_get_irq(pdev, finfo->tx_irq); | |
5040f534 SA |
819 | if (mbox->irq < 0) |
820 | return mbox->irq; | |
8841a66a SA |
821 | mbox->chan = &chnls[i]; |
822 | chnls[i].con_priv = mbox; | |
5040f534 SA |
823 | list[i] = mbox++; |
824 | } | |
825 | ||
72c1c817 SA |
826 | mutex_init(&mdev->cfg_lock); |
827 | mdev->dev = &pdev->dev; | |
75288cc6 SA |
828 | mdev->num_users = num_users; |
829 | mdev->num_fifos = num_fifos; | |
2240f8ae | 830 | mdev->intr_type = intr_type; |
72c1c817 | 831 | mdev->mboxes = list; |
8841a66a SA |
832 | |
833 | /* OMAP does not have a Tx-Done IRQ, but rather a Tx-Ready IRQ */ | |
834 | mdev->controller.txdone_irq = true; | |
835 | mdev->controller.dev = mdev->dev; | |
836 | mdev->controller.ops = &omap_mbox_chan_ops; | |
837 | mdev->controller.chans = chnls; | |
838 | mdev->controller.num_chans = info_count; | |
839 | mdev->controller.of_xlate = omap_mbox_of_xlate; | |
72c1c817 | 840 | ret = omap_mbox_register(mdev); |
5040f534 SA |
841 | if (ret) |
842 | return ret; | |
843 | ||
72c1c817 SA |
844 | platform_set_drvdata(pdev, mdev); |
845 | pm_runtime_enable(mdev->dev); | |
5040f534 | 846 | |
72c1c817 | 847 | ret = pm_runtime_get_sync(mdev->dev); |
5040f534 | 848 | if (ret < 0) { |
72c1c817 | 849 | pm_runtime_put_noidle(mdev->dev); |
5040f534 SA |
850 | goto unregister; |
851 | } | |
852 | ||
853 | /* | |
854 | * just print the raw revision register, the format is not | |
855 | * uniform across all SoCs | |
856 | */ | |
72c1c817 SA |
857 | l = mbox_read_reg(mdev, MAILBOX_REVISION); |
858 | dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l); | |
5040f534 | 859 | |
72c1c817 | 860 | ret = pm_runtime_put_sync(mdev->dev); |
5040f534 SA |
861 | if (ret < 0) |
862 | goto unregister; | |
863 | ||
75288cc6 | 864 | devm_kfree(&pdev->dev, finfoblk); |
5040f534 SA |
865 | return 0; |
866 | ||
867 | unregister: | |
72c1c817 SA |
868 | pm_runtime_disable(mdev->dev); |
869 | omap_mbox_unregister(mdev); | |
5040f534 SA |
870 | return ret; |
871 | } | |
872 | ||
873 | static int omap_mbox_remove(struct platform_device *pdev) | |
874 | { | |
72c1c817 SA |
875 | struct omap_mbox_device *mdev = platform_get_drvdata(pdev); |
876 | ||
877 | pm_runtime_disable(mdev->dev); | |
878 | omap_mbox_unregister(mdev); | |
5040f534 SA |
879 | |
880 | return 0; | |
881 | } | |
882 | ||
883 | static struct platform_driver omap_mbox_driver = { | |
884 | .probe = omap_mbox_probe, | |
885 | .remove = omap_mbox_remove, | |
886 | .driver = { | |
887 | .name = "omap-mailbox", | |
af1d2f5c | 888 | .pm = &omap_mbox_pm_ops, |
75288cc6 | 889 | .of_match_table = of_match_ptr(omap_mailbox_of_match), |
5040f534 SA |
890 | }, |
891 | }; | |
340a614a | 892 | |
c7c158e5 | 893 | static int __init omap_mbox_init(void) |
340a614a | 894 | { |
6b233985 HD |
895 | int err; |
896 | ||
897 | err = class_register(&omap_mbox_class); | |
898 | if (err) | |
899 | return err; | |
900 | ||
b5bebe41 OBC |
901 | /* kfifo size sanity check: alignment and minimal size */ |
902 | mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t)); | |
ab66ac30 KH |
903 | mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, |
904 | sizeof(mbox_msg_t)); | |
b5bebe41 | 905 | |
1f90a216 AY |
906 | err = platform_driver_register(&omap_mbox_driver); |
907 | if (err) | |
908 | class_unregister(&omap_mbox_class); | |
909 | ||
910 | return err; | |
340a614a | 911 | } |
6b233985 | 912 | subsys_initcall(omap_mbox_init); |
340a614a | 913 | |
c7c158e5 | 914 | static void __exit omap_mbox_exit(void) |
340a614a | 915 | { |
5040f534 | 916 | platform_driver_unregister(&omap_mbox_driver); |
6b233985 | 917 | class_unregister(&omap_mbox_class); |
340a614a | 918 | } |
c7c158e5 | 919 | module_exit(omap_mbox_exit); |
340a614a | 920 | |
f48cca87 HD |
921 | MODULE_LICENSE("GPL v2"); |
922 | MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging"); | |
f375325a OBC |
923 | MODULE_AUTHOR("Toshihiro Kobayashi"); |
924 | MODULE_AUTHOR("Hiroshi DOYU"); |