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Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / isdn / hardware / mISDN / hfcmulti.c
CommitLineData
de6cc651 1// SPDX-License-Identifier: GPL-2.0-or-later
af69fb3a
KK		 2/*
3 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
4 *
5 * Author Andreas Eversberg (jolly@eversberg.eu)
6 * ported to mqueue mechanism:
7 * Peter Sprenger (sprengermoving-bytes.de)
8 *
9 * inspired by existing hfc-pci driver:
10 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
11 * Copyright 2008 by Karsten Keil (kkeil@suse.de)
12 * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu)
13 *
af69fb3a
KK		 14 * Thanks to Cologne Chip AG for this great controller!
15 */
16
17/*
18 * module parameters:
19 * type:
20 * By default (0), the card is automatically detected.
21 * Or use the following combinations:
22 * Bit 0-7 = 0x00001 = HFC-E1 (1 port)
23 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports)
24 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports)
25 * Bit 8 = 0x00100 = uLaw (instead of aLaw)
26 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware
27 * Bit 10 = spare
28 * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
29 * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
30 * Bit 13 = spare
31 * Bit 14 = 0x04000 = Use external ram (128K)
32 * Bit 15 = 0x08000 = Use external ram (512K)
33 * Bit 16 = 0x10000 = Use 64 timeslots instead of 32
34 * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else
35 * Bit 18 = spare
36 * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
37 * (all other bits are reserved and shall be 0)
38 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
39 * bus (PCM master)
40 *
41 * port: (optional or required for all ports on all installed cards)
42 * HFC-4S/HFC-8S only bits:
43 * Bit 0 = 0x001 = Use master clock for this S/T interface
44 * (ony once per chip).
45 * Bit 1 = 0x002 = transmitter line setup (non capacitive mode)
46 * Don't use this unless you know what you are doing!
47 * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing)
48 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
49 * received from port 1
50 *
51 * HFC-E1 only bits:
52 * Bit 0 = 0x0001 = interface: 0=copper, 1=optical
53 * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode)
54 * Bit 2 = 0x0004 = Report LOS
55 * Bit 3 = 0x0008 = Report AIS
56 * Bit 4 = 0x0010 = Report SLIP
57 * Bit 5 = 0x0020 = Report RDI
58 * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
59 * mode instead.
60 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode.
61 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode.
62 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
63 * (E1 only)
64 * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
65 * for default.
66 * (all other bits are reserved and shall be 0)
67 *
68 * debug:
69 * NOTE: only one debug value must be given for all cards
70 * enable debugging (see hfc_multi.h for debug options)
71 *
72 * poll:
73 * NOTE: only one poll value must be given for all cards
74 * Give the number of samples for each fifo process.
75 * By default 128 is used. Decrease to reduce delay, increase to
76 * reduce cpu load. If unsure, don't mess with it!
77 * Valid is 8, 16, 32, 64, 128, 256.
78 *
79 * pcm:
80 * NOTE: only one pcm value must be given for every card.
81 * The PCM bus id tells the mISDNdsp module about the connected PCM bus.
82 * By default (0), the PCM bus id is 100 for the card that is PCM master.
83 * If multiple cards are PCM master (because they are not interconnected),
84 * each card with PCM master will have increasing PCM id.
85 * All PCM busses with the same ID are expected to be connected and have
86 * common time slots slots.
87 * Only one chip of the PCM bus must be master, the others slave.
88 * -1 means no support of PCM bus not even.
89 * Omit this value, if all cards are interconnected or none is connected.
90 * If unsure, don't give this parameter.
91 *
07003408
AE		 92 * dmask and bmask:
93 * NOTE: One dmask value must be given for every HFC-E1 card.
94 * If omitted, the E1 card has D-channel on time slot 16, which is default.
95 * dmask is a 32 bit mask. The bit must be set for an alternate time slot.
96 * If multiple bits are set, multiple virtual card fragments are created.
97 * For each bit set, a bmask value must be given. Each bit on the bmask
98 * value stands for a B-channel. The bmask may not overlap with dmask or
99 * with other bmask values for that card.
100 * Example: dmask=0x00020002 bmask=0x0000fffc,0xfffc0000
101 * This will create one fragment with D-channel on slot 1 with
102 * B-channels on slots 2..15, and a second fragment with D-channel
103 * on slot 17 with B-channels on slot 18..31. Slot 16 is unused.
104 * If bit 0 is set (dmask=0x00000001) the D-channel is on slot 0 and will
105 * not function.
106 * Example: dmask=0x00000001 bmask=0xfffffffe
107 * This will create a port with all 31 usable timeslots as
108 * B-channels.
109 * If no bits are set on bmask, no B-channel is created for that fragment.
110 * Example: dmask=0xfffffffe bmask=0,0,0,0.... (31 0-values for bmask)
111 * This will create 31 ports with one D-channel only.
af69fb3a
KK		 112 * If you don't know how to use it, you don't need it!
113 *
114 * iomode:
115 * NOTE: only one mode value must be given for every card.
116 * -> See hfc_multi.h for HFC_IO_MODE_* values
117 * By default, the IO mode is pci memory IO (MEMIO).
f77f13e2 118 * Some cards require specific IO mode, so it cannot be changed.
25985edc 119 * It may be useful to set IO mode to register io (REGIO) to solve
af69fb3a
KK		 120 * PCI bridge problems.
121 * If unsure, don't give this parameter.
122 *
123 * clockdelay_nt:
124 * NOTE: only one clockdelay_nt value must be given once for all cards.
125 * Give the value of the clock control register (A_ST_CLK_DLY)
126 * of the S/T interfaces in NT mode.
127 * This register is needed for the TBR3 certification, so don't change it.
128 *
129 * clockdelay_te:
130 * NOTE: only one clockdelay_te value must be given once
131 * Give the value of the clock control register (A_ST_CLK_DLY)
132 * of the S/T interfaces in TE mode.
133 * This register is needed for the TBR3 certification, so don't change it.
3bd69ad1
AE		 134 *
135 * clock:
1b36c78f 136 * NOTE: only one clock value must be given once
3bd69ad1
AE		 137 * Selects interface with clock source for mISDN and applications.
138 * Set to card number starting with 1. Set to -1 to disable.
139 * By default, the first card is used as clock source.
db9bb63a
KK		 140 *
141 * hwid:
142 * NOTE: only one hwid value must be given once
475be4d8 143 * Enable special embedded devices with XHFC controllers.
af69fb3a
KK		 144 */
145
146/*
147 * debug register access (never use this, it will flood your system log)
148 * #define HFC_REGISTER_DEBUG
149 */
150
69e656cc 151#define HFC_MULTI_VERSION "2.03"
af69fb3a 152
a6b7a407 153#include <linux/interrupt.h>
af69fb3a 154#include <linux/module.h>
5a0e3ad6 155#include <linux/slab.h>
af69fb3a
KK		 156#include <linux/pci.h>
157#include <linux/delay.h>
158#include <linux/mISDNhw.h>
159#include <linux/mISDNdsp.h>
160
161/*
475be4d8
JP		 162 #define IRQCOUNT_DEBUG
163 #define IRQ_DEBUG
af69fb3a
KK		 164*/
165
166#include "hfc_multi.h"
167#ifdef ECHOPREP
168#include "gaintab.h"
169#endif
170
171#define MAX_CARDS 8
172#define MAX_PORTS (8 * MAX_CARDS)
07003408 173#define MAX_FRAGS (32 * MAX_CARDS)
af69fb3a
KK		 174
175static LIST_HEAD(HFClist);
176static spinlock_t HFClock; /* global hfc list lock */
177
178static void ph_state_change(struct dchannel *);
af69fb3a
KK		 179
180static struct hfc_multi *syncmaster;
5b834354 181static int plxsd_master; /* if we have a master card (yet) */
af69fb3a 182static spinlock_t plx_lock; /* may not acquire other lock inside */
af69fb3a
KK		 183
184#define TYP_E1 1
185#define TYP_4S 4
186#define TYP_8S 8
187
188static int poll_timer = 6; /* default = 128 samples = 16ms */
189/* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
190static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 };
191#define CLKDEL_TE 0x0f /* CLKDEL in TE mode */
192#define CLKDEL_NT 0x6c /* CLKDEL in NT mode
193 (0x60 MUST be included!) */
af69fb3a
KK		 194
195#define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */
196#define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */
197#define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */
198
199/*
200 * module stuff
201 */
202
203static uint type[MAX_CARDS];
3bd69ad1 204static int pcm[MAX_CARDS];
07003408
AE		 205static uint dmask[MAX_CARDS];
206static uint bmask[MAX_FRAGS];
af69fb3a
KK		 207static uint iomode[MAX_CARDS];
208static uint port[MAX_PORTS];
209static uint debug;
210static uint poll;
3bd69ad1 211static int clock;
af69fb3a
KK		 212static uint timer;
213static uint clockdelay_te = CLKDEL_TE;
214static uint clockdelay_nt = CLKDEL_NT;
db9bb63a
KK		 215#define HWID_NONE 0
216#define HWID_MINIP4 1
217#define HWID_MINIP8 2
218#define HWID_MINIP16 3
219static uint hwid = HWID_NONE;
af69fb3a 220
07003408 221static int HFC_cnt, E1_cnt, bmask_cnt, Port_cnt, PCM_cnt = 99;
af69fb3a
KK		 222
223MODULE_AUTHOR("Andreas Eversberg");
224MODULE_LICENSE("GPL");
69e656cc 225MODULE_VERSION(HFC_MULTI_VERSION);
af69fb3a
KK		 226module_param(debug, uint, S_IRUGO | S_IWUSR);
227module_param(poll, uint, S_IRUGO | S_IWUSR);
3bd69ad1 228module_param(clock, int, S_IRUGO | S_IWUSR);
af69fb3a
KK		 229module_param(timer, uint, S_IRUGO | S_IWUSR);
230module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
231module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
232module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
3bd69ad1 233module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
07003408
AE		 234module_param_array(dmask, uint, NULL, S_IRUGO | S_IWUSR);
235module_param_array(bmask, uint, NULL, S_IRUGO | S_IWUSR);
af69fb3a
KK		 236module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
237module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
db9bb63a 238module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */
af69fb3a
KK		 239
240#ifdef HFC_REGISTER_DEBUG
475be4d8 241#define HFC_outb(hc, reg, val) \
af69fb3a 242 (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
475be4d8 243#define HFC_outb_nodebug(hc, reg, val) \
af69fb3a 244 (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
475be4d8 245#define HFC_inb(hc, reg) \
af69fb3a 246 (hc->HFC_inb(hc, reg, __func__, __LINE__))
475be4d8 247#define HFC_inb_nodebug(hc, reg) \
af69fb3a 248 (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
475be4d8 249#define HFC_inw(hc, reg) \
af69fb3a 250 (hc->HFC_inw(hc, reg, __func__, __LINE__))
475be4d8 251#define HFC_inw_nodebug(hc, reg) \
af69fb3a 252 (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
475be4d8 253#define HFC_wait(hc) \
af69fb3a 254 (hc->HFC_wait(hc, __func__, __LINE__))
475be4d8 255#define HFC_wait_nodebug(hc) \
af69fb3a
KK		 256 (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
257#else
258#define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val))
259#define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val))
260#define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg))
261#define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg))
262#define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg))
263#define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg))
264#define HFC_wait(hc) (hc->HFC_wait(hc))
265#define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc))
266#endif
267
db9bb63a
KK		 268#ifdef CONFIG_MISDN_HFCMULTI_8xx
269#include "hfc_multi_8xx.h"
270#endif
271
af69fb3a
KK		 272/* HFC_IO_MODE_PCIMEM */
273static void
274#ifdef HFC_REGISTER_DEBUG
275HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
276 const char *function, int line)
277#else
475be4d8 278 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
af69fb3a
KK		 279#endif
280{
eac74af9 281 writeb(val, hc->pci_membase + reg);
af69fb3a
KK		 282}
283static u_char
284#ifdef HFC_REGISTER_DEBUG
285HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
286#else
475be4d8 287 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
af69fb3a
KK		 288#endif
289{
eac74af9 290 return readb(hc->pci_membase + reg);
af69fb3a
KK		 291}
292static u_short
293#ifdef HFC_REGISTER_DEBUG
294HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
295#else
475be4d8 296 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
af69fb3a
KK		 297#endif
298{
eac74af9 299 return readw(hc->pci_membase + reg);
af69fb3a
KK		 300}
301static void
302#ifdef HFC_REGISTER_DEBUG
303HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
304#else
475be4d8 305 HFC_wait_pcimem(struct hfc_multi *hc)
af69fb3a
KK		 306#endif
307{
eac74af9
KK		 308 while (readb(hc->pci_membase + R_STATUS) & V_BUSY)
309 cpu_relax();
af69fb3a
KK		 310}
311
312/* HFC_IO_MODE_REGIO */
313static void
314#ifdef HFC_REGISTER_DEBUG
315HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
475be4d8 316 const char *function, int line)
af69fb3a 317#else
475be4d8 318 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
af69fb3a
KK		 319#endif
320{
eac74af9 321 outb(reg, hc->pci_iobase + 4);
af69fb3a
KK		 322 outb(val, hc->pci_iobase);
323}
324static u_char
325#ifdef HFC_REGISTER_DEBUG
326HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
327#else
475be4d8 328 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
af69fb3a
KK		 329#endif
330{
eac74af9 331 outb(reg, hc->pci_iobase + 4);
af69fb3a
KK		 332 return inb(hc->pci_iobase);
333}
334static u_short
335#ifdef HFC_REGISTER_DEBUG
336HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
337#else
475be4d8 338 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
af69fb3a
KK		 339#endif
340{
eac74af9 341 outb(reg, hc->pci_iobase + 4);
af69fb3a
KK		 342 return inw(hc->pci_iobase);
343}
344static void
345#ifdef HFC_REGISTER_DEBUG
346HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
347#else
475be4d8 348 HFC_wait_regio(struct hfc_multi *hc)
af69fb3a
KK		 349#endif
350{
eac74af9
KK		 351 outb(R_STATUS, hc->pci_iobase + 4);
352 while (inb(hc->pci_iobase) & V_BUSY)
353 cpu_relax();
af69fb3a
KK		 354}
355
356#ifdef HFC_REGISTER_DEBUG
357static void
358HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
475be4d8 359 const char *function, int line)
af69fb3a
KK		 360{
361 char regname[256] = "", bits[9] = "xxxxxxxx";
362 int i;
363
364 i = -1;
365 while (hfc_register_names[++i].name) {
366 if (hfc_register_names[i].reg == reg)
367 strcat(regname, hfc_register_names[i].name);
368 }
369 if (regname[0] == '\0')
370 strcpy(regname, "register");
371
eac74af9
KK		 372 bits[7] = '0' + (!!(val & 1));
373 bits[6] = '0' + (!!(val & 2));
374 bits[5] = '0' + (!!(val & 4));
375 bits[4] = '0' + (!!(val & 8));
376 bits[3] = '0' + (!!(val & 16));
377 bits[2] = '0' + (!!(val & 32));
378 bits[1] = '0' + (!!(val & 64));
379 bits[0] = '0' + (!!(val & 128));
af69fb3a 380 printk(KERN_DEBUG
475be4d8
JP		 381 "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
382 hc->id, reg, regname, val, bits, function, line);
af69fb3a
KK		 383 HFC_outb_nodebug(hc, reg, val);
384}
385static u_char
386HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
387{
388 char regname[256] = "", bits[9] = "xxxxxxxx";
389 u_char val = HFC_inb_nodebug(hc, reg);
390 int i;
391
392 i = 0;
393 while (hfc_register_names[i++].name)
394 ;
395 while (hfc_register_names[++i].name) {
396 if (hfc_register_names[i].reg == reg)
397 strcat(regname, hfc_register_names[i].name);
398 }
399 if (regname[0] == '\0')
400 strcpy(regname, "register");
401
eac74af9
KK		 402 bits[7] = '0' + (!!(val & 1));
403 bits[6] = '0' + (!!(val & 2));
404 bits[5] = '0' + (!!(val & 4));
405 bits[4] = '0' + (!!(val & 8));
406 bits[3] = '0' + (!!(val & 16));
407 bits[2] = '0' + (!!(val & 32));
408 bits[1] = '0' + (!!(val & 64));
409 bits[0] = '0' + (!!(val & 128));
af69fb3a 410 printk(KERN_DEBUG
475be4d8
JP		 411 "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
412 hc->id, reg, regname, val, bits, function, line);
af69fb3a
KK		 413 return val;
414}
415static u_short
416HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
417{
418 char regname[256] = "";
419 u_short val = HFC_inw_nodebug(hc, reg);
420 int i;
421
422 i = 0;
423 while (hfc_register_names[i++].name)
424 ;
425 while (hfc_register_names[++i].name) {
426 if (hfc_register_names[i].reg == reg)
427 strcat(regname, hfc_register_names[i].name);
428 }
429 if (regname[0] == '\0')
430 strcpy(regname, "register");
431
432 printk(KERN_DEBUG
475be4d8
JP		 433 "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
434 hc->id, reg, regname, val, function, line);
af69fb3a
KK		 435 return val;
436}
437static void
438HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
439{
440 printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
475be4d8 441 hc->id, function, line);
af69fb3a
KK		 442 HFC_wait_nodebug(hc);
443}
444#endif
445
446/* write fifo data (REGIO) */
5b834354 447static void
af69fb3a
KK		 448write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
449{
475be4d8
JP		 450 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
451 while (len >> 2) {
b3e0aeeb 452 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
af69fb3a
KK		 453 data += 4;
454 len -= 4;
455 }
475be4d8 456 while (len >> 1) {
b3e0aeeb 457 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
af69fb3a
KK		 458 data += 2;
459 len -= 2;
460 }
461 while (len) {
462 outb(*data, hc->pci_iobase);
463 data++;
464 len--;
465 }
466}
467/* write fifo data (PCIMEM) */
5b834354 468static void
af69fb3a
KK		 469write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
470{
475be4d8 471 while (len >> 2) {
b3e0aeeb 472 writel(cpu_to_le32(*(u32 *)data),
475be4d8 473 hc->pci_membase + A_FIFO_DATA0);
af69fb3a
KK		 474 data += 4;
475 len -= 4;
476 }
475be4d8 477 while (len >> 1) {
b3e0aeeb 478 writew(cpu_to_le16(*(u16 *)data),
475be4d8 479 hc->pci_membase + A_FIFO_DATA0);
af69fb3a
KK		 480 data += 2;
481 len -= 2;
482 }
483 while (len) {
b3e0aeeb 484 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
af69fb3a
KK		 485 data++;
486 len--;
487 }
488}
eac74af9 489
af69fb3a 490/* read fifo data (REGIO) */
5b834354 491static void
af69fb3a
KK		 492read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
493{
475be4d8
JP		 494 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
495 while (len >> 2) {
b3e0aeeb 496 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
af69fb3a
KK		 497 data += 4;
498 len -= 4;
499 }
475be4d8 500 while (len >> 1) {
b3e0aeeb 501 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
af69fb3a
KK		 502 data += 2;
503 len -= 2;
504 }
505 while (len) {
506 *data = inb(hc->pci_iobase);
507 data++;
508 len--;
509 }
510}
511
512/* read fifo data (PCIMEM) */
5b834354 513static void
af69fb3a
KK		 514read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
515{
475be4d8 516 while (len >> 2) {
af69fb3a 517 *(u32 *)data =
b3e0aeeb 518 le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
af69fb3a
KK		 519 data += 4;
520 len -= 4;
521 }
475be4d8 522 while (len >> 1) {
af69fb3a 523 *(u16 *)data =
b3e0aeeb 524 le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
af69fb3a
KK		 525 data += 2;
526 len -= 2;
527 }
528 while (len) {
b3e0aeeb 529 *data = readb(hc->pci_membase + A_FIFO_DATA0);
af69fb3a
KK		 530 data++;
531 len--;
532 }
533}
534
af69fb3a
KK		 535static void
536enable_hwirq(struct hfc_multi *hc)
537{
538 hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
539 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
540}
541
542static void
543disable_hwirq(struct hfc_multi *hc)
544{
545 hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
546 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
547}
548
549#define NUM_EC 2
550#define MAX_TDM_CHAN 32
551
552
569e937e 553static inline void
af69fb3a
KK		 554enablepcibridge(struct hfc_multi *c)
555{
556 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
557}
558
569e937e 559static inline void
af69fb3a
KK		 560disablepcibridge(struct hfc_multi *c)
561{
562 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
563}
564
569e937e 565static inline unsigned char
af69fb3a
KK		 566readpcibridge(struct hfc_multi *hc, unsigned char address)
567{
568 unsigned short cipv;
569 unsigned char data;
570
571 if (!hc->pci_iobase)
572 return 0;
573
574 /* slow down a PCI read access by 1 PCI clock cycle */
575 HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
576
577 if (address == 0)
578 cipv = 0x4000;
579 else
580 cipv = 0x5800;
581
582 /* select local bridge port address by writing to CIP port */
583 /* data = HFC_inb(c, cipv); * was _io before */
584 outw(cipv, hc->pci_iobase + 4);
585 data = inb(hc->pci_iobase);
586
587 /* restore R_CTRL for normal PCI read cycle speed */
588 HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
589
590 return data;
591}
592
569e937e 593static inline void
af69fb3a
KK		 594writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
595{
596 unsigned short cipv;
597 unsigned int datav;
598
599 if (!hc->pci_iobase)
600 return;
601
602 if (address == 0)
603 cipv = 0x4000;
604 else
605 cipv = 0x5800;
606
607 /* select local bridge port address by writing to CIP port */
608 outw(cipv, hc->pci_iobase + 4);
609 /* define a 32 bit dword with 4 identical bytes for write sequence */
610 datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
475be4d8 611 ((__u32) data << 24);
af69fb3a
KK		 612
613 /*
614 * write this 32 bit dword to the bridge data port
615 * this will initiate a write sequence of up to 4 writes to the same
616 * address on the local bus interface the number of write accesses
617 * is undefined but >=1 and depends on the next PCI transaction
618 * during write sequence on the local bus
619 */
620 outl(datav, hc->pci_iobase);
621}
622
569e937e 623static inline void
af69fb3a
KK		 624cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
625{
626 /* Do data pin read low byte */
627 HFC_outb(hc, R_GPIO_OUT1, reg);
628}
629
569e937e 630static inline void
af69fb3a
KK		 631cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
632{
633 cpld_set_reg(hc, reg);
634
635 enablepcibridge(hc);
636 writepcibridge(hc, 1, val);
637 disablepcibridge(hc);
638
639 return;
640}
641
569e937e 642static inline unsigned char
af69fb3a
KK		 643cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
644{
645 unsigned char bytein;
646
647 cpld_set_reg(hc, reg);
648
649 /* Do data pin read low byte */
650 HFC_outb(hc, R_GPIO_OUT1, reg);
651
652 enablepcibridge(hc);
653 bytein = readpcibridge(hc, 1);
654 disablepcibridge(hc);
655
656 return bytein;
657}
658
569e937e 659static inline void
af69fb3a
KK		 660vpm_write_address(struct hfc_multi *hc, unsigned short addr)
661{
662 cpld_write_reg(hc, 0, 0xff & addr);
663 cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
664}
665
569e937e 666static inline unsigned short
af69fb3a
KK		 667vpm_read_address(struct hfc_multi *c)
668{
669 unsigned short addr;
670 unsigned short highbit;
671
672 addr = cpld_read_reg(c, 0);
673 highbit = cpld_read_reg(c, 1);
674
675 addr = addr | (highbit << 8);
676
677 return addr & 0x1ff;
678}
679
569e937e 680static inline unsigned char
af69fb3a
KK		 681vpm_in(struct hfc_multi *c, int which, unsigned short addr)
682{
683 unsigned char res;
684
685 vpm_write_address(c, addr);
686
687 if (!which)
688 cpld_set_reg(c, 2);
689 else
690 cpld_set_reg(c, 3);
691
692 enablepcibridge(c);
693 res = readpcibridge(c, 1);
694 disablepcibridge(c);
695
696 cpld_set_reg(c, 0);
697
698 return res;
699}
700
569e937e 701static inline void
af69fb3a 702vpm_out(struct hfc_multi *c, int which, unsigned short addr,
475be4d8 703 unsigned char data)
af69fb3a
KK		 704{
705 vpm_write_address(c, addr);
706
707 enablepcibridge(c);
708
709 if (!which)
710 cpld_set_reg(c, 2);
711 else
712 cpld_set_reg(c, 3);
713
714 writepcibridge(c, 1, data);
715
716 cpld_set_reg(c, 0);
717
718 disablepcibridge(c);
719
720 {
475be4d8
JP		 721 unsigned char regin;
722 regin = vpm_in(c, which, addr);
723 if (regin != data)
724 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
725 "0x%x\n", data, addr, regin);
af69fb3a
KK		 726 }
727
728}
729
730
5b834354 731static void
af69fb3a
KK		 732vpm_init(struct hfc_multi *wc)
733{
734 unsigned char reg;
735 unsigned int mask;
736 unsigned int i, x, y;
737 unsigned int ver;
738
739 for (x = 0; x < NUM_EC; x++) {
740 /* Setup GPIO's */
741 if (!x) {
742 ver = vpm_in(wc, x, 0x1a0);
743 printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
744 }
745
746 for (y = 0; y < 4; y++) {
747 vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
748 vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
749 vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
750 }
751
752 /* Setup TDM path - sets fsync and tdm_clk as inputs */
753 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
754 vpm_out(wc, x, 0x1a3, reg & ~2);
755
756 /* Setup Echo length (256 taps) */
757 vpm_out(wc, x, 0x022, 1);
758 vpm_out(wc, x, 0x023, 0xff);
759
760 /* Setup timeslots */
761 vpm_out(wc, x, 0x02f, 0x00);
762 mask = 0x02020202 << (x * 4);
763
764 /* Setup the tdm channel masks for all chips */
765 for (i = 0; i < 4; i++)
766 vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
767
768 /* Setup convergence rate */
769 printk(KERN_DEBUG "VPM: A-law mode\n");
770 reg = 0x00 | 0x10 | 0x01;
771 vpm_out(wc, x, 0x20, reg);
772 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
773 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
774
775 vpm_out(wc, x, 0x24, 0x02);
776 reg = vpm_in(wc, x, 0x24);
777 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
778
779 /* Initialize echo cans */
780 for (i = 0; i < MAX_TDM_CHAN; i++) {
781 if (mask & (0x00000001 << i))
782 vpm_out(wc, x, i, 0x00);
783 }
784
785 /*
786 * ARM arch at least disallows a udelay of
787 * more than 2ms... it gives a fake "__bad_udelay"
788 * reference at link-time.
789 * long delays in kernel code are pretty sucky anyway
790 * for now work around it using 5 x 2ms instead of 1 x 10ms
791 */
792
793 udelay(2000);
794 udelay(2000);
795 udelay(2000);
796 udelay(2000);
797 udelay(2000);
798
799 /* Put in bypass mode */
800 for (i = 0; i < MAX_TDM_CHAN; i++) {
801 if (mask & (0x00000001 << i))
802 vpm_out(wc, x, i, 0x01);
803 }
804
805 /* Enable bypass */
806 for (i = 0; i < MAX_TDM_CHAN; i++) {
807 if (mask & (0x00000001 << i))
808 vpm_out(wc, x, 0x78 + i, 0x01);
809 }
810
811 }
812}
813
047ce8f2 814#ifdef UNUSED
5b834354 815static void
af69fb3a
KK		 816vpm_check(struct hfc_multi *hctmp)
817{
818 unsigned char gpi2;
819
820 gpi2 = HFC_inb(hctmp, R_GPI_IN2);
821
822 if ((gpi2 & 0x3) != 0x3)
823 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
824}
047ce8f2 825#endif /* UNUSED */
af69fb3a
KK		 826
827
828/*
829 * Interface to enable/disable the HW Echocan
830 *
831 * these functions are called within a spin_lock_irqsave on
832 * the channel instance lock, so we are not disturbed by irqs
833 *
834 * we can later easily change the interface to make other
835 * things configurable, for now we configure the taps
836 *
837 */
838
5b834354 839static void
af69fb3a
KK		 840vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
841{
842 unsigned int timeslot;
843 unsigned int unit;
844 struct bchannel *bch = hc->chan[ch].bch;
845#ifdef TXADJ
846 int txadj = -4;
847 struct sk_buff *skb;
848#endif
849 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
850 return;
851
852 if (!bch)
853 return;
854
855#ifdef TXADJ
856 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
475be4d8 857 sizeof(int), &txadj, GFP_ATOMIC);
af69fb3a
KK		 858 if (skb)
859 recv_Bchannel_skb(bch, skb);
860#endif
861
475be4d8 862 timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
af69fb3a
KK		 863 unit = ch % 4;
864
865 printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
475be4d8 866 taps, timeslot);
af69fb3a
KK		 867
868 vpm_out(hc, unit, timeslot, 0x7e);
869}
870
5b834354 871static void
af69fb3a
KK		 872vpm_echocan_off(struct hfc_multi *hc, int ch)
873{
874 unsigned int timeslot;
875 unsigned int unit;
876 struct bchannel *bch = hc->chan[ch].bch;
877#ifdef TXADJ
878 int txadj = 0;
879 struct sk_buff *skb;
880#endif
881
882 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
883 return;
884
885 if (!bch)
886 return;
887
888#ifdef TXADJ
889 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
475be4d8 890 sizeof(int), &txadj, GFP_ATOMIC);
af69fb3a
KK		 891 if (skb)
892 recv_Bchannel_skb(bch, skb);
893#endif
894
475be4d8 895 timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
af69fb3a
KK		 896 unit = ch % 4;
897
898 printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
475be4d8 899 timeslot);
af69fb3a
KK		 900 /* FILLME */
901 vpm_out(hc, unit, timeslot, 0x01);
902}
903
904
905/*
906 * Speech Design resync feature
907 * NOTE: This is called sometimes outside interrupt handler.
25985edc 908 * We must lock irqsave, so no other interrupt (other card) will occur!
af69fb3a
KK		 909 * Also multiple interrupts may nest, so must lock each access (lists, card)!
910 */
911static inline void
912hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
913{
bcf91745 914 struct hfc_multi *hc, *next, *pcmmaster = NULL;
c31655fc
HE		 915 void __iomem *plx_acc_32;
916 u_int pv;
af69fb3a
KK		 917 u_long flags;
918
919 spin_lock_irqsave(&HFClock, flags);
920 spin_lock(&plx_lock); /* must be locked inside other locks */
921
922 if (debug & DEBUG_HFCMULTI_PLXSD)
923 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
475be4d8 924 __func__, syncmaster);
af69fb3a
KK		 925
926 /* select new master */
927 if (newmaster) {
928 if (debug & DEBUG_HFCMULTI_PLXSD)
929 printk(KERN_DEBUG "using provided controller\n");
930 } else {
931 list_for_each_entry_safe(hc, next, &HFClist, list) {
932 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
933 if (hc->syncronized) {
934 newmaster = hc;
935 break;
936 }
937 }
938 }
939 }
940
941 /* Disable sync of all cards */
942 list_for_each_entry_safe(hc, next, &HFClist, list) {
943 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
c31655fc 944 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 945 pv = readl(plx_acc_32);
946 pv &= ~PLX_SYNC_O_EN;
947 writel(pv, plx_acc_32);
948 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
949 pcmmaster = hc;
db9bb63a 950 if (hc->ctype == HFC_TYPE_E1) {
af69fb3a
KK		 951 if (debug & DEBUG_HFCMULTI_PLXSD)
952 printk(KERN_DEBUG
475be4d8 953 "Schedule SYNC_I\n");
af69fb3a
KK		 954 hc->e1_resync |= 1; /* get SYNC_I */
955 }
956 }
957 }
958 }
959
960 if (newmaster) {
961 hc = newmaster;
962 if (debug & DEBUG_HFCMULTI_PLXSD)
963 printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
475be4d8 964 "interface.\n", hc->id, hc);
af69fb3a 965 /* Enable new sync master */
c31655fc 966 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 967 pv = readl(plx_acc_32);
968 pv |= PLX_SYNC_O_EN;
969 writel(pv, plx_acc_32);
970 /* switch to jatt PLL, if not disabled by RX_SYNC */
db9bb63a 971 if (hc->ctype == HFC_TYPE_E1
475be4d8 972 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
af69fb3a
KK		 973 if (debug & DEBUG_HFCMULTI_PLXSD)
974 printk(KERN_DEBUG "Schedule jatt PLL\n");
975 hc->e1_resync |= 2; /* switch to jatt */
976 }
977 } else {
978 if (pcmmaster) {
979 hc = pcmmaster;
980 if (debug & DEBUG_HFCMULTI_PLXSD)
981 printk(KERN_DEBUG
475be4d8
JP		 982 "id=%d (0x%p) = PCM master syncronized "
983 "with QUARTZ\n", hc->id, hc);
db9bb63a 984 if (hc->ctype == HFC_TYPE_E1) {
af69fb3a
KK		 985 /* Use the crystal clock for the PCM
986 master card */
987 if (debug & DEBUG_HFCMULTI_PLXSD)
988 printk(KERN_DEBUG
475be4d8 989 "Schedule QUARTZ for HFC-E1\n");
af69fb3a
KK		 990 hc->e1_resync |= 4; /* switch quartz */
991 } else {
992 if (debug & DEBUG_HFCMULTI_PLXSD)
993 printk(KERN_DEBUG
475be4d8
JP		 994 "QUARTZ is automatically "
995 "enabled by HFC-%dS\n", hc->ctype);
af69fb3a 996 }
c31655fc 997 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 998 pv = readl(plx_acc_32);
999 pv |= PLX_SYNC_O_EN;
1000 writel(pv, plx_acc_32);
1001 } else
1002 if (!rm)
1003 printk(KERN_ERR "%s no pcm master, this MUST "
475be4d8 1004 "not happen!\n", __func__);
af69fb3a
KK		 1005 }
1006 syncmaster = newmaster;
1007
1008 spin_unlock(&plx_lock);
1009 spin_unlock_irqrestore(&HFClock, flags);
1010}
1011
1012/* This must be called AND hc must be locked irqsave!!! */
569e937e 1013static inline void
af69fb3a
KK		 1014plxsd_checksync(struct hfc_multi *hc, int rm)
1015{
1016 if (hc->syncronized) {
1017 if (syncmaster == NULL) {
1018 if (debug & DEBUG_HFCMULTI_PLXSD)
eac74af9 1019 printk(KERN_DEBUG "%s: GOT sync on card %d"
475be4d8
JP		 1020 " (id=%d)\n", __func__, hc->id + 1,
1021 hc->id);
af69fb3a
KK		 1022 hfcmulti_resync(hc, hc, rm);
1023 }
1024 } else {
1025 if (syncmaster == hc) {
1026 if (debug & DEBUG_HFCMULTI_PLXSD)
eac74af9 1027 printk(KERN_DEBUG "%s: LOST sync on card %d"
475be4d8
JP		 1028 " (id=%d)\n", __func__, hc->id + 1,
1029 hc->id);
af69fb3a
KK		 1030 hfcmulti_resync(hc, NULL, rm);
1031 }
1032 }
1033}
1034
1035
1036/*
1037 * free hardware resources used by driver
1038 */
1039static void
1040release_io_hfcmulti(struct hfc_multi *hc)
1041{
c31655fc
HE		 1042 void __iomem *plx_acc_32;
1043 u_int pv;
af69fb3a
KK		 1044 u_long plx_flags;
1045
1046 if (debug & DEBUG_HFCMULTI_INIT)
1047 printk(KERN_DEBUG "%s: entered\n", __func__);
1048
1049 /* soft reset also masks all interrupts */
1050 hc->hw.r_cirm |= V_SRES;
1051 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1052 udelay(1000);
1053 hc->hw.r_cirm &= ~V_SRES;
1054 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1055 udelay(1000); /* instead of 'wait' that may cause locking */
1056
1057 /* release Speech Design card, if PLX was initialized */
1058 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1059 if (debug & DEBUG_HFCMULTI_PLXSD)
1060 printk(KERN_DEBUG "%s: release PLXSD card %d\n",
475be4d8 1061 __func__, hc->id + 1);
af69fb3a 1062 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 1063 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 1064 writel(PLX_GPIOC_INIT, plx_acc_32);
1065 pv = readl(plx_acc_32);
1066 /* Termination off */
1067 pv &= ~PLX_TERM_ON;
1068 /* Disconnect the PCM */
1069 pv |= PLX_SLAVE_EN_N;
1070 pv &= ~PLX_MASTER_EN;
1071 pv &= ~PLX_SYNC_O_EN;
1072 /* Put the DSP in Reset */
1073 pv &= ~PLX_DSP_RES_N;
1074 writel(pv, plx_acc_32);
1075 if (debug & DEBUG_HFCMULTI_INIT)
eac74af9 1076 printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n",
475be4d8 1077 __func__, pv);
af69fb3a
KK		 1078 spin_unlock_irqrestore(&plx_lock, plx_flags);
1079 }
1080
1081 /* disable memory mapped ports / io ports */
1082 test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
db9bb63a
KK		 1083 if (hc->pci_dev)
1084 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
af69fb3a 1085 if (hc->pci_membase)
c31655fc 1086 iounmap(hc->pci_membase);
af69fb3a 1087 if (hc->plx_membase)
c31655fc 1088 iounmap(hc->plx_membase);
af69fb3a
KK		 1089 if (hc->pci_iobase)
1090 release_region(hc->pci_iobase, 8);
db9bb63a
KK		 1091 if (hc->xhfc_membase)
1092 iounmap((void *)hc->xhfc_membase);
af69fb3a
KK		 1093
1094 if (hc->pci_dev) {
1095 pci_disable_device(hc->pci_dev);
1096 pci_set_drvdata(hc->pci_dev, NULL);
1097 }
1098 if (debug & DEBUG_HFCMULTI_INIT)
1099 printk(KERN_DEBUG "%s: done\n", __func__);
1100}
1101
1102/*
1103 * function called to reset the HFC chip. A complete software reset of chip
1104 * and fifos is done. All configuration of the chip is done.
1105 */
1106
1107static int
1108init_chip(struct hfc_multi *hc)
1109{
1110 u_long flags, val, val2 = 0, rev;
1111 int i, err = 0;
1112 u_char r_conf_en, rval;
c31655fc
HE		 1113 void __iomem *plx_acc_32;
1114 u_int pv;
af69fb3a
KK		 1115 u_long plx_flags, hfc_flags;
1116 int plx_count;
1117 struct hfc_multi *pos, *next, *plx_last_hc;
1118
1119 spin_lock_irqsave(&hc->lock, flags);
1120 /* reset all registers */
1121 memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1122
1123 /* revision check */
1124 if (debug & DEBUG_HFCMULTI_INIT)
1125 printk(KERN_DEBUG "%s: entered\n", __func__);
db9bb63a 1126 val = HFC_inb(hc, R_CHIP_ID);
eac74af9
KK		 1127 if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe &&
1128 (val >> 1) != 0x31) {
af69fb3a
KK		 1129 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1130 err = -EIO;
1131 goto out;
1132 }
1133 rev = HFC_inb(hc, R_CHIP_RV);
1134 printk(KERN_INFO
475be4d8
JP		 1135 "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1136 val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
1137 " (old FIFO handling)" : "");
db9bb63a 1138 if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
af69fb3a
KK		 1139 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1140 printk(KERN_WARNING
475be4d8
JP		 1141 "HFC_multi: NOTE: Your chip is revision 0, "
1142 "ask Cologne Chip for update. Newer chips "
1143 "have a better FIFO handling. Old chips "
1144 "still work but may have slightly lower "
1145 "HDLC transmit performance.\n");
af69fb3a
KK		 1146 }
1147 if (rev > 1) {
1148 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
475be4d8
JP		 1149 "consider chip revision = %ld. The chip / "
1150 "bridge may not work.\n", rev);
af69fb3a
KK		 1151 }
1152
1153 /* set s-ram size */
1154 hc->Flen = 0x10;
1155 hc->Zmin = 0x80;
1156 hc->Zlen = 384;
1157 hc->DTMFbase = 0x1000;
1158 if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1159 if (debug & DEBUG_HFCMULTI_INIT)
d584515f 1160 printk(KERN_DEBUG "%s: changing to 128K external RAM\n",
475be4d8 1161 __func__);
af69fb3a
KK		 1162 hc->hw.r_ctrl |= V_EXT_RAM;
1163 hc->hw.r_ram_sz = 1;
1164 hc->Flen = 0x20;
1165 hc->Zmin = 0xc0;
1166 hc->Zlen = 1856;
1167 hc->DTMFbase = 0x2000;
1168 }
1169 if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1170 if (debug & DEBUG_HFCMULTI_INIT)
d584515f 1171 printk(KERN_DEBUG "%s: changing to 512K external RAM\n",
475be4d8 1172 __func__);
af69fb3a
KK		 1173 hc->hw.r_ctrl |= V_EXT_RAM;
1174 hc->hw.r_ram_sz = 2;
1175 hc->Flen = 0x20;
1176 hc->Zmin = 0xc0;
1177 hc->Zlen = 8000;
1178 hc->DTMFbase = 0x2000;
1179 }
db9bb63a
KK		 1180 if (hc->ctype == HFC_TYPE_XHFC) {
1181 hc->Flen = 0x8;
1182 hc->Zmin = 0x0;
1183 hc->Zlen = 64;
1184 hc->DTMFbase = 0x0;
1185 }
af69fb3a
KK		 1186 hc->max_trans = poll << 1;
1187 if (hc->max_trans > hc->Zlen)
1188 hc->max_trans = hc->Zlen;
1189
1190 /* Speech Design PLX bridge */
1191 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1192 if (debug & DEBUG_HFCMULTI_PLXSD)
1193 printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
475be4d8 1194 __func__, hc->id + 1);
af69fb3a 1195 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 1196 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 1197 writel(PLX_GPIOC_INIT, plx_acc_32);
1198 pv = readl(plx_acc_32);
1199 /* The first and the last cards are terminating the PCM bus */
1200 pv |= PLX_TERM_ON; /* hc is currently the last */
1201 /* Disconnect the PCM */
1202 pv |= PLX_SLAVE_EN_N;
1203 pv &= ~PLX_MASTER_EN;
1204 pv &= ~PLX_SYNC_O_EN;
1205 /* Put the DSP in Reset */
1206 pv &= ~PLX_DSP_RES_N;
1207 writel(pv, plx_acc_32);
1208 spin_unlock_irqrestore(&plx_lock, plx_flags);
1209 if (debug & DEBUG_HFCMULTI_INIT)
eac74af9 1210 printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n",
475be4d8 1211 __func__, pv);
af69fb3a
KK		 1212 /*
1213 * If we are the 3rd PLXSD card or higher, we must turn
1214 * termination of last PLXSD card off.
1215 */
1216 spin_lock_irqsave(&HFClock, hfc_flags);
1217 plx_count = 0;
1218 plx_last_hc = NULL;
1219 list_for_each_entry_safe(pos, next, &HFClist, list) {
1220 if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1221 plx_count++;
1222 if (pos != hc)
1223 plx_last_hc = pos;
1224 }
1225 }
1226 if (plx_count >= 3) {
1227 if (debug & DEBUG_HFCMULTI_PLXSD)
1228 printk(KERN_DEBUG "%s: card %d is between, so "
475be4d8
JP		 1229 "we disable termination\n",
1230 __func__, plx_last_hc->id + 1);
af69fb3a 1231 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 1232 plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 1233 pv = readl(plx_acc_32);
1234 pv &= ~PLX_TERM_ON;
1235 writel(pv, plx_acc_32);
1236 spin_unlock_irqrestore(&plx_lock, plx_flags);
1237 if (debug & DEBUG_HFCMULTI_INIT)
eac74af9 1238 printk(KERN_DEBUG
475be4d8
JP		 1239 "%s: term off: PLX_GPIO=%x\n",
1240 __func__, pv);
af69fb3a
KK		 1241 }
1242 spin_unlock_irqrestore(&HFClock, hfc_flags);
1243 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1244 }
1245
db9bb63a
KK		 1246 if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1247 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1248
af69fb3a
KK		 1249 /* we only want the real Z2 read-pointer for revision > 0 */
1250 if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1251 hc->hw.r_ram_sz |= V_FZ_MD;
1252
1253 /* select pcm mode */
1254 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1255 if (debug & DEBUG_HFCMULTI_INIT)
1256 printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
475be4d8 1257 __func__);
af69fb3a 1258 } else
475be4d8
JP		 1259 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1260 if (debug & DEBUG_HFCMULTI_INIT)
1261 printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1262 __func__);
1263 hc->hw.r_pcm_md0 |= V_PCM_MD;
1264 } else {
1265 if (debug & DEBUG_HFCMULTI_INIT)
1266 printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1267 __func__);
1268 }
af69fb3a
KK		 1269
1270 /* soft reset */
1271 HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
db9bb63a
KK		 1272 if (hc->ctype == HFC_TYPE_XHFC)
1273 HFC_outb(hc, 0x0C /* R_FIFO_THRES */,
475be4d8 1274 0x11 /* 16 Bytes TX/RX */);
db9bb63a
KK		 1275 else
1276 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
af69fb3a 1277 HFC_outb(hc, R_FIFO_MD, 0);
db9bb63a
KK		 1278 if (hc->ctype == HFC_TYPE_XHFC)
1279 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
1280 else
1281 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
1282 | V_RLD_EPR;
af69fb3a
KK		 1283 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1284 udelay(100);
1285 hc->hw.r_cirm = 0;
1286 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1287 udelay(100);
db9bb63a
KK		 1288 if (hc->ctype != HFC_TYPE_XHFC)
1289 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
af69fb3a
KK		 1290
1291 /* Speech Design PLX bridge pcm and sync mode */
1292 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1293 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 1294 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 1295 pv = readl(plx_acc_32);
1296 /* Connect PCM */
1297 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1298 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1299 pv |= PLX_SYNC_O_EN;
1300 if (debug & DEBUG_HFCMULTI_INIT)
eac74af9 1301 printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n",
475be4d8 1302 __func__, pv);
af69fb3a
KK		 1303 } else {
1304 pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1305 pv &= ~PLX_SYNC_O_EN;
1306 if (debug & DEBUG_HFCMULTI_INIT)
eac74af9 1307 printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n",
475be4d8 1308 __func__, pv);
af69fb3a
KK		 1309 }
1310 writel(pv, plx_acc_32);
1311 spin_unlock_irqrestore(&plx_lock, plx_flags);
1312 }
1313
1314 /* PCM setup */
1315 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1316 if (hc->slots == 32)
1317 HFC_outb(hc, R_PCM_MD1, 0x00);
1318 if (hc->slots == 64)
1319 HFC_outb(hc, R_PCM_MD1, 0x10);
1320 if (hc->slots == 128)
1321 HFC_outb(hc, R_PCM_MD1, 0x20);
1322 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1323 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1324 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
db9bb63a
KK		 1325 else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1326 HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
af69fb3a
KK		 1327 else
1328 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1329 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1330 for (i = 0; i < 256; i++) {
1331 HFC_outb_nodebug(hc, R_SLOT, i);
1332 HFC_outb_nodebug(hc, A_SL_CFG, 0);
db9bb63a
KK		 1333 if (hc->ctype != HFC_TYPE_XHFC)
1334 HFC_outb_nodebug(hc, A_CONF, 0);
af69fb3a
KK		 1335 hc->slot_owner[i] = -1;
1336 }
1337
1338 /* set clock speed */
1339 if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1340 if (debug & DEBUG_HFCMULTI_INIT)
1341 printk(KERN_DEBUG
475be4d8 1342 "%s: setting double clock\n", __func__);
af69fb3a
KK		 1343 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1344 }
1345
db9bb63a
KK		 1346 if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1347 HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */);
1348
af69fb3a
KK		 1349 /* B410P GPIO */
1350 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1351 printk(KERN_NOTICE "Setting GPIOs\n");
1352 HFC_outb(hc, R_GPIO_SEL, 0x30);
1353 HFC_outb(hc, R_GPIO_EN1, 0x3);
1354 udelay(1000);
1355 printk(KERN_NOTICE "calling vpm_init\n");
1356 vpm_init(hc);
1357 }
1358
1359 /* check if R_F0_CNT counts (8 kHz frame count) */
1360 val = HFC_inb(hc, R_F0_CNTL);
1361 val += HFC_inb(hc, R_F0_CNTH) << 8;
1362 if (debug & DEBUG_HFCMULTI_INIT)
1363 printk(KERN_DEBUG
475be4d8 1364 "HFC_multi F0_CNT %ld after reset\n", val);
af69fb3a
KK		 1365 spin_unlock_irqrestore(&hc->lock, flags);
1366 set_current_state(TASK_UNINTERRUPTIBLE);
475be4d8 1367 schedule_timeout((HZ / 100) ? : 1); /* Timeout minimum 10ms */
af69fb3a
KK		 1368 spin_lock_irqsave(&hc->lock, flags);
1369 val2 = HFC_inb(hc, R_F0_CNTL);
1370 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1371 if (debug & DEBUG_HFCMULTI_INIT)
1372 printk(KERN_DEBUG
475be4d8
JP		 1373 "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1374 val2);
1375 if (val2 >= val + 8) { /* 1 ms */
af69fb3a
KK		 1376 /* it counts, so we keep the pcm mode */
1377 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1378 printk(KERN_INFO "controller is PCM bus MASTER\n");
1379 else
475be4d8
JP		 1380 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1381 printk(KERN_INFO "controller is PCM bus SLAVE\n");
1382 else {
1383 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1384 printk(KERN_INFO "controller is PCM bus SLAVE "
1385 "(auto detected)\n");
1386 }
af69fb3a
KK		 1387 } else {
1388 /* does not count */
1389 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
475be4d8 1390 controller_fail:
af69fb3a 1391 printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
475be4d8 1392 "pulse. Seems that controller fails.\n");
af69fb3a
KK		 1393 err = -EIO;
1394 goto out;
1395 }
1396 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1397 printk(KERN_INFO "controller is PCM bus SLAVE "
475be4d8 1398 "(ignoring missing PCM clock)\n");
af69fb3a
KK		 1399 } else {
1400 /* only one pcm master */
1401 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
475be4d8 1402 && plxsd_master) {
af69fb3a 1403 printk(KERN_ERR "HFC_multi ERROR, no clock "
475be4d8
JP		 1404 "on another Speech Design card found. "
1405 "Please be sure to connect PCM cable.\n");
af69fb3a
KK		 1406 err = -EIO;
1407 goto out;
1408 }
1409 /* retry with master clock */
1410 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1411 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 1412 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 1413 pv = readl(plx_acc_32);
1414 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1415 pv |= PLX_SYNC_O_EN;
1416 writel(pv, plx_acc_32);
1417 spin_unlock_irqrestore(&plx_lock, plx_flags);
1418 if (debug & DEBUG_HFCMULTI_INIT)
eac74af9 1419 printk(KERN_DEBUG "%s: master: "
475be4d8 1420 "PLX_GPIO=%x\n", __func__, pv);
af69fb3a
KK		 1421 }
1422 hc->hw.r_pcm_md0 |= V_PCM_MD;
1423 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1424 spin_unlock_irqrestore(&hc->lock, flags);
1425 set_current_state(TASK_UNINTERRUPTIBLE);
475be4d8 1426 schedule_timeout((HZ / 100) ?: 1); /* Timeout min. 10ms */
af69fb3a
KK		 1427 spin_lock_irqsave(&hc->lock, flags);
1428 val2 = HFC_inb(hc, R_F0_CNTL);
1429 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1430 if (debug & DEBUG_HFCMULTI_INIT)
1431 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
475be4d8
JP		 1432 "10 ms (2nd try)\n", val2);
1433 if (val2 >= val + 8) { /* 1 ms */
af69fb3a 1434 test_and_set_bit(HFC_CHIP_PCM_MASTER,
475be4d8 1435 &hc->chip);
af69fb3a 1436 printk(KERN_INFO "controller is PCM bus MASTER "
475be4d8 1437 "(auto detected)\n");
af69fb3a
KK		 1438 } else
1439 goto controller_fail;
1440 }
1441 }
1442
1443 /* Release the DSP Reset */
1444 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1445 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1446 plxsd_master = 1;
1447 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 1448 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 1449 pv = readl(plx_acc_32);
1450 pv |= PLX_DSP_RES_N;
1451 writel(pv, plx_acc_32);
1452 spin_unlock_irqrestore(&plx_lock, plx_flags);
1453 if (debug & DEBUG_HFCMULTI_INIT)
eac74af9 1454 printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n",
475be4d8 1455 __func__, pv);
af69fb3a
KK		 1456 }
1457
1458 /* pcm id */
1459 if (hc->pcm)
1460 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
475be4d8 1461 hc->pcm);
af69fb3a
KK		 1462 else {
1463 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
475be4d8 1464 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
af69fb3a
KK		 1465 PCM_cnt++; /* SD has proprietary bridging */
1466 }
1467 hc->pcm = PCM_cnt;
1468 printk(KERN_INFO "controller has PCM BUS ID %d "
475be4d8 1469 "(auto selected)\n", hc->pcm);
af69fb3a
KK		 1470 }
1471
1472 /* set up timer */
1473 HFC_outb(hc, R_TI_WD, poll_timer);
1474 hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1475
af69fb3a 1476 /* set E1 state machine IRQ */
db9bb63a 1477 if (hc->ctype == HFC_TYPE_E1)
af69fb3a
KK		 1478 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1479
1480 /* set DTMF detection */
1481 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1482 if (debug & DEBUG_HFCMULTI_INIT)
1483 printk(KERN_DEBUG "%s: enabling DTMF detection "
475be4d8 1484 "for all B-channel\n", __func__);
af69fb3a
KK		 1485 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1486 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1487 hc->hw.r_dtmf |= V_ULAW_SEL;
1488 HFC_outb(hc, R_DTMF_N, 102 - 1);
1489 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1490 }
1491
1492 /* conference engine */
1493 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1494 r_conf_en = V_CONF_EN | V_ULAW;
1495 else
1496 r_conf_en = V_CONF_EN;
db9bb63a
KK		 1497 if (hc->ctype != HFC_TYPE_XHFC)
1498 HFC_outb(hc, R_CONF_EN, r_conf_en);
af69fb3a
KK		 1499
1500 /* setting leds */
1501 switch (hc->leds) {
1502 case 1: /* HFC-E1 OEM */
1503 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1504 HFC_outb(hc, R_GPIO_SEL, 0x32);
1505 else
1506 HFC_outb(hc, R_GPIO_SEL, 0x30);
1507
1508 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1509 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1510
1511 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1512 break;
1513
1514 case 2: /* HFC-4S OEM */
1515 case 3:
1516 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1517 HFC_outb(hc, R_GPIO_EN1, 0xff);
1518 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1519 break;
1520 }
1521
db9bb63a
KK		 1522 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
1523 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
1524 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1525 }
1526
af69fb3a
KK		 1527 /* set master clock */
1528 if (hc->masterclk >= 0) {
1529 if (debug & DEBUG_HFCMULTI_INIT)
1530 printk(KERN_DEBUG "%s: setting ST master clock "
475be4d8
JP		 1531 "to port %d (0..%d)\n",
1532 __func__, hc->masterclk, hc->ports - 1);
db9bb63a 1533 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
af69fb3a
KK		 1534 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1535 }
1536
db9bb63a
KK		 1537
1538
af69fb3a
KK		 1539 /* setting misc irq */
1540 HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1541 if (debug & DEBUG_HFCMULTI_INIT)
1542 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
475be4d8 1543 hc->hw.r_irqmsk_misc);
af69fb3a
KK		 1544
1545 /* RAM access test */
1546 HFC_outb(hc, R_RAM_ADDR0, 0);
1547 HFC_outb(hc, R_RAM_ADDR1, 0);
1548 HFC_outb(hc, R_RAM_ADDR2, 0);
1549 for (i = 0; i < 256; i++) {
1550 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
475be4d8 1551 HFC_outb_nodebug(hc, R_RAM_DATA, ((i * 3) & 0xff));
af69fb3a
KK		 1552 }
1553 for (i = 0; i < 256; i++) {
1554 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1555 HFC_inb_nodebug(hc, R_RAM_DATA);
1556 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1557 if (rval != ((i * 3) & 0xff)) {
1558 printk(KERN_DEBUG
475be4d8
JP		 1559 "addr:%x val:%x should:%x\n", i, rval,
1560 (i * 3) & 0xff);
af69fb3a
KK		 1561 err++;
1562 }
1563 }
1564 if (err) {
1565 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1566 err = -EIO;
1567 goto out;
1568 }
1569
1570 if (debug & DEBUG_HFCMULTI_INIT)
1571 printk(KERN_DEBUG "%s: done\n", __func__);
1572out:
1573 spin_unlock_irqrestore(&hc->lock, flags);
1574 return err;
1575}
1576
1577
1578/*
1579 * control the watchdog
1580 */
1581static void
1582hfcmulti_watchdog(struct hfc_multi *hc)
1583{
1584 hc->wdcount++;
1585
1586 if (hc->wdcount > 10) {
1587 hc->wdcount = 0;
1588 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
475be4d8 1589 V_GPIO_OUT3 : V_GPIO_OUT2;
af69fb3a 1590
475be4d8 1591 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
af69fb3a
KK		 1592 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1593 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1594 }
1595}
1596
1597
1598
1599/*
1600 * output leds
1601 */
1602static void
1603hfcmulti_leds(struct hfc_multi *hc)
1604{
1605 unsigned long lled;
1606 unsigned long leddw;
1607 int i, state, active, leds;
1608 struct dchannel *dch;
1609 int led[4];
1610
af69fb3a
KK		 1611 switch (hc->leds) {
1612 case 1: /* HFC-E1 OEM */
864fd636
AE		 1613 /* 2 red steady: LOS
1614 * 1 red steady: L1 not active
1615 * 2 green steady: L1 active
1616 * 1st green flashing: activity on TX
1617 * 2nd green flashing: activity on RX
af69fb3a 1618 */
864fd636
AE		 1619 led[0] = 0;
1620 led[1] = 0;
1621 led[2] = 0;
1622 led[3] = 0;
07003408 1623 dch = hc->chan[hc->dnum[0]].dch;
864fd636 1624 if (dch) {
07003408 1625 if (hc->chan[hc->dnum[0]].los)
af69fb3a 1626 led[1] = 1;
864fd636 1627 if (hc->e1_state != 1) {
af69fb3a 1628 led[0] = 1;
864fd636
AE		 1629 hc->flash[2] = 0;
1630 hc->flash[3] = 0;
af69fb3a 1631 } else {
864fd636
AE		 1632 led[2] = 1;
1633 led[3] = 1;
1634 if (!hc->flash[2] && hc->activity_tx)
1635 hc->flash[2] = poll;
1636 if (!hc->flash[3] && hc->activity_rx)
1637 hc->flash[3] = poll;
1638 if (hc->flash[2] && hc->flash[2] < 1024)
1639 led[2] = 0;
1640 if (hc->flash[3] && hc->flash[3] < 1024)
1641 led[3] = 0;
1642 if (hc->flash[2] >= 2048)
1643 hc->flash[2] = 0;
1644 if (hc->flash[3] >= 2048)
1645 hc->flash[3] = 0;
1646 if (hc->flash[2])
1647 hc->flash[2] += poll;
1648 if (hc->flash[3])
1649 hc->flash[3] += poll;
af69fb3a 1650 }
af69fb3a
KK		 1651 }
1652 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
475be4d8 1653 /* leds are inverted */
af69fb3a
KK		 1654 if (leds != (int)hc->ledstate) {
1655 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1656 hc->ledstate = leds;
1657 }
1658 break;
1659
1660 case 2: /* HFC-4S OEM */
864fd636
AE		 1661 /* red steady: PH_DEACTIVATE
1662 * green steady: PH_ACTIVATE
1663 * green flashing: activity on TX
af69fb3a
KK		 1664 */
1665 for (i = 0; i < 4; i++) {
1666 state = 0;
1667 active = -1;
1668 dch = hc->chan[(i << 2) | 2].dch;
1669 if (dch) {
1670 state = dch->state;
1671 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1672 active = 3;
1673 else
1674 active = 7;
1675 }
1676 if (state) {
1677 if (state == active) {
1678 led[i] = 1; /* led green */
864fd636
AE		 1679 hc->activity_tx |= hc->activity_rx;
1680 if (!hc->flash[i] &&
1681 (hc->activity_tx & (1 << i)))
1682 hc->flash[i] = poll;
1683 if (hc->flash[i] && hc->flash[i] < 1024)
1684 led[i] = 0; /* led off */
1685 if (hc->flash[i] >= 2048)
1686 hc->flash[i] = 0;
1687 if (hc->flash[i])
1688 hc->flash[i] += poll;
1689 } else {
1690 led[i] = 2; /* led red */
1691 hc->flash[i] = 0;
1692 }
af69fb3a
KK		 1693 } else
1694 led[i] = 0; /* led off */
1695 }
1696 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1697 leds = 0;
1698 for (i = 0; i < 4; i++) {
1699 if (led[i] == 1) {
1700 /*green*/
1701 leds |= (0x2 << (i * 2));
1702 } else if (led[i] == 2) {
1703 /*red*/
1704 leds |= (0x1 << (i * 2));
1705 }
1706 }
1707 if (leds != (int)hc->ledstate) {
1708 vpm_out(hc, 0, 0x1a8 + 3, leds);
1709 hc->ledstate = leds;
1710 }
1711 } else {
1712 leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
475be4d8
JP		 1713 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1714 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1715 ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
af69fb3a
KK		 1716 if (leds != (int)hc->ledstate) {
1717 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1718 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1719 hc->ledstate = leds;
1720 }
1721 }
1722 break;
1723
1724 case 3: /* HFC 1S/2S Beronet */
864fd636
AE		 1725 /* red steady: PH_DEACTIVATE
1726 * green steady: PH_ACTIVATE
1727 * green flashing: activity on TX
af69fb3a
KK		 1728 */
1729 for (i = 0; i < 2; i++) {
1730 state = 0;
1731 active = -1;
1732 dch = hc->chan[(i << 2) | 2].dch;
1733 if (dch) {
1734 state = dch->state;
1735 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1736 active = 3;
1737 else
1738 active = 7;
1739 }
1740 if (state) {
1741 if (state == active) {
1742 led[i] = 1; /* led green */
864fd636
AE		 1743 hc->activity_tx |= hc->activity_rx;
1744 if (!hc->flash[i] &&
1745 (hc->activity_tx & (1 << i)))
1746 hc->flash[i] = poll;
1747 if (hc->flash[i] < 1024)
1748 led[i] = 0; /* led off */
1749 if (hc->flash[i] >= 2048)
1750 hc->flash[i] = 0;
1751 if (hc->flash[i])
1752 hc->flash[i] += poll;
1753 } else {
1754 led[i] = 2; /* led red */
1755 hc->flash[i] = 0;
1756 }
af69fb3a
KK		 1757 } else
1758 led[i] = 0; /* led off */
1759 }
475be4d8
JP		 1760 leds = (led[0] > 0) | ((led[1] > 0) << 1) | ((led[0]&1) << 2)
1761 | ((led[1]&1) << 3);
af69fb3a
KK		 1762 if (leds != (int)hc->ledstate) {
1763 HFC_outb_nodebug(hc, R_GPIO_EN1,
475be4d8 1764 ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
af69fb3a 1765 HFC_outb_nodebug(hc, R_GPIO_OUT1,
475be4d8 1766 ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
af69fb3a
KK		 1767 hc->ledstate = leds;
1768 }
1769 break;
1770 case 8: /* HFC 8S+ Beronet */
864fd636
AE		 1771 /* off: PH_DEACTIVATE
1772 * steady: PH_ACTIVATE
1773 * flashing: activity on TX
1774 */
1775 lled = 0xff; /* leds off */
af69fb3a
KK		 1776 for (i = 0; i < 8; i++) {
1777 state = 0;
1778 active = -1;
1779 dch = hc->chan[(i << 2) | 2].dch;
1780 if (dch) {
1781 state = dch->state;
1782 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1783 active = 3;
1784 else
1785 active = 7;
1786 }
1787 if (state) {
1788 if (state == active) {
864fd636
AE		 1789 lled &= ~(1 << i); /* led on */
1790 hc->activity_tx |= hc->activity_rx;
1791 if (!hc->flash[i] &&
1792 (hc->activity_tx & (1 << i)))
1793 hc->flash[i] = poll;
1794 if (hc->flash[i] < 1024)
1795 lled |= 1 << i; /* led off */
1796 if (hc->flash[i] >= 2048)
1797 hc->flash[i] = 0;
1798 if (hc->flash[i])
1799 hc->flash[i] += poll;
af69fb3a 1800 } else
864fd636
AE		 1801 hc->flash[i] = 0;
1802 }
af69fb3a
KK		 1803 }
1804 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1805 if (leddw != hc->ledstate) {
1806 /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
475be4d8 1807 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
af69fb3a
KK		 1808 /* was _io before */
1809 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1810 outw(0x4000, hc->pci_iobase + 4);
1811 outl(leddw, hc->pci_iobase);
1812 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1813 hc->ledstate = leddw;
1814 }
1815 break;
1816 }
864fd636
AE		 1817 hc->activity_tx = 0;
1818 hc->activity_rx = 0;
af69fb3a
KK		 1819}
1820/*
1821 * read dtmf coefficients
1822 */
1823
1824static void
1825hfcmulti_dtmf(struct hfc_multi *hc)
1826{
1827 s32 *coeff;
1828 u_int mantissa;
1829 int co, ch;
1830 struct bchannel *bch = NULL;
1831 u8 exponent;
1832 int dtmf = 0;
1833 int addr;
1834 u16 w_float;
1835 struct sk_buff *skb;
1836 struct mISDNhead *hh;
1837
1838 if (debug & DEBUG_HFCMULTI_DTMF)
1839 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1840 for (ch = 0; ch <= 31; ch++) {
1841 /* only process enabled B-channels */
1842 bch = hc->chan[ch].bch;
1843 if (!bch)
1844 continue;
1845 if (!hc->created[hc->chan[ch].port])
1846 continue;
1847 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1848 continue;
1849 if (debug & DEBUG_HFCMULTI_DTMF)
1850 printk(KERN_DEBUG "%s: dtmf channel %d:",
475be4d8 1851 __func__, ch);
af69fb3a
KK		 1852 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1853 dtmf = 1;
1854 for (co = 0; co < 8; co++) {
1855 /* read W(n-1) coefficient */
475be4d8 1856 addr = hc->DTMFbase + ((co << 7) | (ch << 2));
af69fb3a 1857 HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
475be4d8
JP		 1858 HFC_outb_nodebug(hc, R_RAM_ADDR1, addr >> 8);
1859 HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr >> 16)
1860 | V_ADDR_INC);
af69fb3a
KK		 1861 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1862 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1863 if (debug & DEBUG_HFCMULTI_DTMF)
1864 printk(" %04x", w_float);
1865
1866 /* decode float (see chip doc) */
1867 mantissa = w_float & 0x0fff;
1868 if (w_float & 0x8000)
1869 mantissa |= 0xfffff000;
475be4d8 1870 exponent = (w_float >> 12) & 0x7;
af69fb3a
KK		 1871 if (exponent) {
1872 mantissa ^= 0x1000;
475be4d8 1873 mantissa <<= (exponent - 1);
af69fb3a
KK		 1874 }
1875
1876 /* store coefficient */
475be4d8 1877 coeff[co << 1] = mantissa;
af69fb3a
KK		 1878
1879 /* read W(n) coefficient */
1880 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1881 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1882 if (debug & DEBUG_HFCMULTI_DTMF)
1883 printk(" %04x", w_float);
1884
1885 /* decode float (see chip doc) */
1886 mantissa = w_float & 0x0fff;
1887 if (w_float & 0x8000)
1888 mantissa |= 0xfffff000;
475be4d8 1889 exponent = (w_float >> 12) & 0x7;
af69fb3a
KK		 1890 if (exponent) {
1891 mantissa ^= 0x1000;
475be4d8 1892 mantissa <<= (exponent - 1);
af69fb3a
KK		 1893 }
1894
1895 /* store coefficient */
475be4d8 1896 coeff[(co << 1) | 1] = mantissa;
af69fb3a
KK		 1897 }
1898 if (debug & DEBUG_HFCMULTI_DTMF)
b5df5a5c 1899 printk(" DTMF ready %08x %08x %08x %08x "
475be4d8
JP		 1900 "%08x %08x %08x %08x\n",
1901 coeff[0], coeff[1], coeff[2], coeff[3],
1902 coeff[4], coeff[5], coeff[6], coeff[7]);
af69fb3a
KK		 1903 hc->chan[ch].coeff_count++;
1904 if (hc->chan[ch].coeff_count == 8) {
1905 hc->chan[ch].coeff_count = 0;
1906 skb = mI_alloc_skb(512, GFP_ATOMIC);
1907 if (!skb) {
eac74af9 1908 printk(KERN_DEBUG "%s: No memory for skb\n",
475be4d8 1909 __func__);
af69fb3a
KK		 1910 continue;
1911 }
1912 hh = mISDN_HEAD_P(skb);
1913 hh->prim = PH_CONTROL_IND;
1914 hh->id = DTMF_HFC_COEF;
59ae1d12 1915 skb_put_data(skb, hc->chan[ch].coeff, 512);
af69fb3a
KK		 1916 recv_Bchannel_skb(bch, skb);
1917 }
1918 }
1919
1920 /* restart DTMF processing */
1921 hc->dtmf = dtmf;
1922 if (dtmf)
1923 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1924}
1925
1926
1927/*
1928 * fill fifo as much as possible
1929 */
1930
1931static void
1932hfcmulti_tx(struct hfc_multi *hc, int ch)
1933{
1934 int i, ii, temp, len = 0;
1935 int Zspace, z1, z2; /* must be int for calculation */
1936 int Fspace, f1, f2;
1937 u_char *d;
1938 int *txpending, slot_tx;
1939 struct bchannel *bch;
1940 struct dchannel *dch;
1941 struct sk_buff **sp = NULL;
1942 int *idxp;
1943
1944 bch = hc->chan[ch].bch;
1945 dch = hc->chan[ch].dch;
1946 if ((!dch) && (!bch))
1947 return;
1948
1949 txpending = &hc->chan[ch].txpending;
1950 slot_tx = hc->chan[ch].slot_tx;
1951 if (dch) {
1952 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1953 return;
1954 sp = &dch->tx_skb;
1955 idxp = &dch->tx_idx;
1956 } else {
1957 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1958 return;
1959 sp = &bch->tx_skb;
1960 idxp = &bch->tx_idx;
1961 }
1962 if (*sp)
1963 len = (*sp)->len;
1964
1965 if ((!len) && *txpending != 1)
1966 return; /* no data */
1967
1968 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1969 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1970 (hc->chan[ch].slot_rx < 0) &&
1971 (hc->chan[ch].slot_tx < 0))
1972 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1973 else
1974 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1975 HFC_wait_nodebug(hc);
1976
1977 if (*txpending == 2) {
1978 /* reset fifo */
1979 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1980 HFC_wait_nodebug(hc);
1981 HFC_outb(hc, A_SUBCH_CFG, 0);
1982 *txpending = 1;
1983 }
1984next_frame:
1985 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1986 f1 = HFC_inb_nodebug(hc, A_F1);
1987 f2 = HFC_inb_nodebug(hc, A_F2);
1988 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1989 if (debug & DEBUG_HFCMULTI_FIFO)
1990 printk(KERN_DEBUG
475be4d8
JP		 1991 "%s(card %d): reread f2 because %d!=%d\n",
1992 __func__, hc->id + 1, temp, f2);
af69fb3a
KK		 1993 f2 = temp; /* repeat until F2 is equal */
1994 }
1995 Fspace = f2 - f1 - 1;
1996 if (Fspace < 0)
1997 Fspace += hc->Flen;
1998 /*
1999 * Old FIFO handling doesn't give us the current Z2 read
2000 * pointer, so we cannot send the next frame before the fifo
2001 * is empty. It makes no difference except for a slightly
2002 * lower performance.
2003 */
2004 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
2005 if (f1 != f2)
2006 Fspace = 0;
2007 else
2008 Fspace = 1;
2009 }
2010 /* one frame only for ST D-channels, to allow resending */
db9bb63a 2011 if (hc->ctype != HFC_TYPE_E1 && dch) {
af69fb3a
KK		 2012 if (f1 != f2)
2013 Fspace = 0;
2014 }
2015 /* F-counter full condition */
2016 if (Fspace == 0)
2017 return;
2018 }
2019 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2020 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2021 while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
2022 if (debug & DEBUG_HFCMULTI_FIFO)
2023 printk(KERN_DEBUG "%s(card %d): reread z2 because "
475be4d8 2024 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
af69fb3a
KK		 2025 z2 = temp; /* repeat unti Z2 is equal */
2026 }
7cfa153d
AE		 2027 hc->chan[ch].Zfill = z1 - z2;
2028 if (hc->chan[ch].Zfill < 0)
2029 hc->chan[ch].Zfill += hc->Zlen;
af69fb3a
KK		 2030 Zspace = z2 - z1;
2031 if (Zspace <= 0)
2032 Zspace += hc->Zlen;
2033 Zspace -= 4; /* keep not too full, so pointers will not overrun */
2034 /* fill transparent data only to maxinum transparent load (minus 4) */
2035 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2036 Zspace = Zspace - hc->Zlen + hc->max_trans;
2037 if (Zspace <= 0) /* no space of 4 bytes */
2038 return;
2039
2040 /* if no data */
2041 if (!len) {
2042 if (z1 == z2) { /* empty */
2043 /* if done with FIFO audio data during PCM connection */
2044 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
2045 *txpending && slot_tx >= 0) {
2046 if (debug & DEBUG_HFCMULTI_MODE)
2047 printk(KERN_DEBUG
475be4d8
JP		 2048 "%s: reconnecting PCM due to no "
2049 "more FIFO data: channel %d "
2050 "slot_tx %d\n",
2051 __func__, ch, slot_tx);
af69fb3a 2052 /* connect slot */
db9bb63a
KK		 2053 if (hc->ctype == HFC_TYPE_XHFC)
2054 HFC_outb(hc, A_CON_HDLC, 0xc0
475be4d8
JP		 2055 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2056 /* Enable FIFO, no interrupt */
db9bb63a
KK		 2057 else
2058 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
475be4d8
JP		 2059 V_HDLC_TRP | V_IFF);
2060 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
af69fb3a 2061 HFC_wait_nodebug(hc);
db9bb63a
KK		 2062 if (hc->ctype == HFC_TYPE_XHFC)
2063 HFC_outb(hc, A_CON_HDLC, 0xc0
475be4d8
JP		 2064 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2065 /* Enable FIFO, no interrupt */
db9bb63a
KK		 2066 else
2067 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
475be4d8
JP		 2068 V_HDLC_TRP | V_IFF);
2069 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
af69fb3a
KK		 2070 HFC_wait_nodebug(hc);
2071 }
2072 *txpending = 0;
2073 }
2074 return; /* no data */
2075 }
2076
8dd2f36f
AE		 2077 /* "fill fifo if empty" feature */
2078 if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
475be4d8 2079 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
8dd2f36f
AE		 2080 if (debug & DEBUG_HFCMULTI_FILL)
2081 printk(KERN_DEBUG "%s: buffer empty, so we have "
475be4d8 2082 "underrun\n", __func__);
8dd2f36f
AE		 2083 /* fill buffer, to prevent future underrun */
2084 hc->write_fifo(hc, hc->silence_data, poll >> 1);
2085 Zspace -= (poll >> 1);
2086 }
2087
af69fb3a
KK		 2088 /* if audio data and connected slot */
2089 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
475be4d8 2090 && slot_tx >= 0) {
af69fb3a
KK		 2091 if (debug & DEBUG_HFCMULTI_MODE)
2092 printk(KERN_DEBUG "%s: disconnecting PCM due to "
475be4d8
JP		 2093 "FIFO data: channel %d slot_tx %d\n",
2094 __func__, ch, slot_tx);
af69fb3a 2095 /* disconnect slot */
db9bb63a
KK		 2096 if (hc->ctype == HFC_TYPE_XHFC)
2097 HFC_outb(hc, A_CON_HDLC, 0x80
475be4d8
JP		 2098 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2099 /* Enable FIFO, no interrupt */
db9bb63a
KK		 2100 else
2101 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
475be4d8
JP		 2102 V_HDLC_TRP | V_IFF);
2103 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
af69fb3a 2104 HFC_wait_nodebug(hc);
db9bb63a
KK		 2105 if (hc->ctype == HFC_TYPE_XHFC)
2106 HFC_outb(hc, A_CON_HDLC, 0x80
475be4d8
JP		 2107 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2108 /* Enable FIFO, no interrupt */
db9bb63a
KK		 2109 else
2110 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
475be4d8
JP		 2111 V_HDLC_TRP | V_IFF);
2112 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
af69fb3a
KK		 2113 HFC_wait_nodebug(hc);
2114 }
2115 *txpending = 1;
2116
2117 /* show activity */
864fd636
AE		 2118 if (dch)
2119 hc->activity_tx |= 1 << hc->chan[ch].port;
af69fb3a
KK		 2120
2121 /* fill fifo to what we have left */
2122 ii = len;
2123 if (dch || test_bit(FLG_HDLC, &bch->Flags))
2124 temp = 1;
2125 else
2126 temp = 0;
2127 i = *idxp;
2128 d = (*sp)->data + i;
2129 if (ii - i > Zspace)
2130 ii = Zspace + i;
2131 if (debug & DEBUG_HFCMULTI_FIFO)
2132 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
475be4d8
JP		 2133 "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2134 __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2135 temp ? "HDLC" : "TRANS");
af69fb3a 2136
af69fb3a
KK		 2137 /* Have to prep the audio data */
2138 hc->write_fifo(hc, d, ii - i);
7cfa153d 2139 hc->chan[ch].Zfill += ii - i;
af69fb3a
KK		 2140 *idxp = ii;
2141
2142 /* if not all data has been written */
2143 if (ii != len) {
2144 /* NOTE: fifo is started by the calling function */
2145 return;
2146 }
2147
2148 /* if all data has been written, terminate frame */
2149 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2150 /* increment f-counter */
2151 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2152 HFC_wait_nodebug(hc);
2153 }
2154
af69fb3a 2155 dev_kfree_skb(*sp);
8bfddfbe
KK		 2156 /* check for next frame */
2157 if (bch && get_next_bframe(bch)) {
af69fb3a
KK		 2158 len = (*sp)->len;
2159 goto next_frame;
2160 }
2161 if (dch && get_next_dframe(dch)) {
2162 len = (*sp)->len;
2163 goto next_frame;
2164 }
2165
2166 /*
2167 * now we have no more data, so in case of transparent,
2168 * we set the last byte in fifo to 'silence' in case we will get
2169 * no more data at all. this prevents sending an undefined value.
2170 */
2171 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
8dd2f36f 2172 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
af69fb3a
KK		 2173}
2174
2175
2176/* NOTE: only called if E1 card is in active state */
2177static void
2178hfcmulti_rx(struct hfc_multi *hc, int ch)
2179{
2180 int temp;
2181 int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2182 int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2183 int again = 0;
2184 struct bchannel *bch;
7206e659 2185 struct dchannel *dch = NULL;
af69fb3a
KK		 2186 struct sk_buff *skb, **sp = NULL;
2187 int maxlen;
2188
2189 bch = hc->chan[ch].bch;
7206e659
KK		 2190 if (bch) {
2191 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2192 return;
2193 } else if (hc->chan[ch].dch) {
2194 dch = hc->chan[ch].dch;
af69fb3a
KK		 2195 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2196 return;
af69fb3a 2197 } else {
7206e659 2198 return;
af69fb3a
KK		 2199 }
2200next_frame:
2201 /* on first AND before getting next valid frame, R_FIFO must be written
2202 to. */
2203 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2204 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2205 (hc->chan[ch].slot_rx < 0) &&
2206 (hc->chan[ch].slot_tx < 0))
475be4d8 2207 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1) | 1);
af69fb3a 2208 else
475be4d8 2209 HFC_outb_nodebug(hc, R_FIFO, (ch << 1) | 1);
af69fb3a
KK		 2210 HFC_wait_nodebug(hc);
2211
2212 /* ignore if rx is off BUT change fifo (above) to start pending TX */
c27b46e7
KK		 2213 if (hc->chan[ch].rx_off) {
2214 if (bch)
2215 bch->dropcnt += poll; /* not exact but fair enough */
af69fb3a 2216 return;
c27b46e7 2217 }
af69fb3a
KK		 2218
2219 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2220 f1 = HFC_inb_nodebug(hc, A_F1);
2221 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2222 if (debug & DEBUG_HFCMULTI_FIFO)
2223 printk(KERN_DEBUG
475be4d8
JP		 2224 "%s(card %d): reread f1 because %d!=%d\n",
2225 __func__, hc->id + 1, temp, f1);
af69fb3a
KK		 2226 f1 = temp; /* repeat until F1 is equal */
2227 }
2228 f2 = HFC_inb_nodebug(hc, A_F2);
2229 }
2230 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2231 while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2232 if (debug & DEBUG_HFCMULTI_FIFO)
2233 printk(KERN_DEBUG "%s(card %d): reread z2 because "
475be4d8 2234 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
af69fb3a
KK		 2235 z1 = temp; /* repeat until Z1 is equal */
2236 }
2237 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2238 Zsize = z1 - z2;
2239 if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2240 /* complete hdlc frame */
2241 Zsize++;
2242 if (Zsize < 0)
2243 Zsize += hc->Zlen;
2244 /* if buffer is empty */
2245 if (Zsize <= 0)
2246 return;
2247
7206e659
KK		 2248 if (bch) {
2249 maxlen = bchannel_get_rxbuf(bch, Zsize);
2250 if (maxlen < 0) {
257daba4
KW		 2251 pr_warn("card%d.B%d: No bufferspace for %d bytes\n",
2252 hc->id + 1, bch->nr, Zsize);
af69fb3a
KK		 2253 return;
2254 }
7206e659
KK		 2255 sp = &bch->rx_skb;
2256 maxlen = bch->maxlen;
2257 } else { /* Dchannel */
2258 sp = &dch->rx_skb;
2259 maxlen = dch->maxlen + 3;
2260 if (*sp == NULL) {
2261 *sp = mI_alloc_skb(maxlen, GFP_ATOMIC);
2262 if (*sp == NULL) {
257daba4
KW		 2263 pr_warn("card%d: No mem for dch rx_skb\n",
2264 hc->id + 1);
7206e659
KK		 2265 return;
2266 }
2267 }
af69fb3a
KK		 2268 }
2269 /* show activity */
864fd636
AE		 2270 if (dch)
2271 hc->activity_rx |= 1 << hc->chan[ch].port;
af69fb3a
KK		 2272
2273 /* empty fifo with what we have */
2274 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2275 if (debug & DEBUG_HFCMULTI_FIFO)
2276 printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
475be4d8
JP		 2277 "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2278 "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2279 Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2280 f1, f2, Zsize + (*sp)->len, again);
af69fb3a 2281 /* HDLC */
7206e659 2282 if ((Zsize + (*sp)->len) > maxlen) {
af69fb3a
KK		 2283 if (debug & DEBUG_HFCMULTI_FIFO)
2284 printk(KERN_DEBUG
475be4d8
JP		 2285 "%s(card %d): hdlc-frame too large.\n",
2286 __func__, hc->id + 1);
af69fb3a
KK		 2287 skb_trim(*sp, 0);
2288 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2289 HFC_wait_nodebug(hc);
2290 return;
2291 }
2292
2293 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2294
2295 if (f1 != f2) {
2296 /* increment Z2,F2-counter */
2297 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2298 HFC_wait_nodebug(hc);
2299 /* check size */
2300 if ((*sp)->len < 4) {
2301 if (debug & DEBUG_HFCMULTI_FIFO)
2302 printk(KERN_DEBUG
475be4d8
JP		 2303 "%s(card %d): Frame below minimum "
2304 "size\n", __func__, hc->id + 1);
af69fb3a
KK		 2305 skb_trim(*sp, 0);
2306 goto next_frame;
2307 }
2308 /* there is at least one complete frame, check crc */
2309 if ((*sp)->data[(*sp)->len - 1]) {
2310 if (debug & DEBUG_HFCMULTI_CRC)
2311 printk(KERN_DEBUG
475be4d8 2312 "%s: CRC-error\n", __func__);
af69fb3a
KK		 2313 skb_trim(*sp, 0);
2314 goto next_frame;
2315 }
2316 skb_trim(*sp, (*sp)->len - 3);
2317 if ((*sp)->len < MISDN_COPY_SIZE) {
2318 skb = *sp;
2319 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2320 if (*sp) {
59ae1d12 2321 skb_put_data(*sp, skb->data, skb->len);
af69fb3a
KK		 2322 skb_trim(skb, 0);
2323 } else {
2324 printk(KERN_DEBUG "%s: No mem\n",
475be4d8 2325 __func__);
af69fb3a
KK		 2326 *sp = skb;
2327 skb = NULL;
2328 }
2329 } else {
2330 skb = NULL;
2331 }
2332 if (debug & DEBUG_HFCMULTI_FIFO) {
2333 printk(KERN_DEBUG "%s(card %d):",
475be4d8 2334 __func__, hc->id + 1);
af69fb3a
KK		 2335 temp = 0;
2336 while (temp < (*sp)->len)
2337 printk(" %02x", (*sp)->data[temp++]);
2338 printk("\n");
2339 }
2340 if (dch)
2341 recv_Dchannel(dch);
2342 else
034005a0 2343 recv_Bchannel(bch, MISDN_ID_ANY, false);
af69fb3a
KK		 2344 *sp = skb;
2345 again++;
2346 goto next_frame;
2347 }
2348 /* there is an incomplete frame */
2349 } else {
2350 /* transparent */
af69fb3a 2351 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
af69fb3a
KK		 2352 if (debug & DEBUG_HFCMULTI_FIFO)
2353 printk(KERN_DEBUG
475be4d8
JP		 2354 "%s(card %d): fifo(%d) reading %d bytes "
2355 "(z1=%04x, z2=%04x) TRANS\n",
2356 __func__, hc->id + 1, ch, Zsize, z1, z2);
af69fb3a 2357 /* only bch is transparent */
034005a0 2358 recv_Bchannel(bch, hc->chan[ch].Zfill, false);
af69fb3a
KK		 2359 }
2360}
2361
2362
2363/*
2364 * Interrupt handler
2365 */
2366static void
2367signal_state_up(struct dchannel *dch, int info, char *msg)
2368{
2369 struct sk_buff *skb;
2370 int id, data = info;
2371
2372 if (debug & DEBUG_HFCMULTI_STATE)
2373 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2374
2375 id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2376
2377 skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
475be4d8 2378 GFP_ATOMIC);
af69fb3a
KK		 2379 if (!skb)
2380 return;
2381 recv_Dchannel_skb(dch, skb);
2382}
2383
2384static inline void
2385handle_timer_irq(struct hfc_multi *hc)
2386{
2387 int ch, temp;
2388 struct dchannel *dch;
2389 u_long flags;
2390
2391 /* process queued resync jobs */
2392 if (hc->e1_resync) {
2393 /* lock, so e1_resync gets not changed */
2394 spin_lock_irqsave(&HFClock, flags);
2395 if (hc->e1_resync & 1) {
2396 if (debug & DEBUG_HFCMULTI_PLXSD)
2397 printk(KERN_DEBUG "Enable SYNC_I\n");
2398 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2399 /* disable JATT, if RX_SYNC is set */
2400 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2401 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2402 }
2403 if (hc->e1_resync & 2) {
2404 if (debug & DEBUG_HFCMULTI_PLXSD)
2405 printk(KERN_DEBUG "Enable jatt PLL\n");
2406 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2407 }
2408 if (hc->e1_resync & 4) {
2409 if (debug & DEBUG_HFCMULTI_PLXSD)
2410 printk(KERN_DEBUG
475be4d8 2411 "Enable QUARTZ for HFC-E1\n");
af69fb3a
KK		 2412 /* set jatt to quartz */
2413 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
475be4d8 2414 | V_JATT_OFF);
af69fb3a
KK		 2415 /* switch to JATT, in case it is not already */
2416 HFC_outb(hc, R_SYNC_OUT, 0);
2417 }
2418 hc->e1_resync = 0;
2419 spin_unlock_irqrestore(&HFClock, flags);
2420 }
2421
db9bb63a 2422 if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
af69fb3a
KK		 2423 for (ch = 0; ch <= 31; ch++) {
2424 if (hc->created[hc->chan[ch].port]) {
2425 hfcmulti_tx(hc, ch);
2426 /* fifo is started when switching to rx-fifo */
2427 hfcmulti_rx(hc, ch);
2428 if (hc->chan[ch].dch &&
2429 hc->chan[ch].nt_timer > -1) {
2430 dch = hc->chan[ch].dch;
2431 if (!(--hc->chan[ch].nt_timer)) {
2432 schedule_event(dch,
475be4d8 2433 FLG_PHCHANGE);
af69fb3a
KK		 2434 if (debug &
2435 DEBUG_HFCMULTI_STATE)
2436 printk(KERN_DEBUG
475be4d8
JP		 2437 "%s: nt_timer at "
2438 "state %x\n",
2439 __func__,
2440 dch->state);
af69fb3a
KK		 2441 }
2442 }
2443 }
2444 }
db9bb63a 2445 if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
07003408
AE		 2446 dch = hc->chan[hc->dnum[0]].dch;
2447 /* LOS */
2448 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2449 hc->chan[hc->dnum[0]].los = temp;
2450 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
2451 if (!temp && hc->chan[hc->dnum[0]].los)
af69fb3a 2452 signal_state_up(dch, L1_SIGNAL_LOS_ON,
475be4d8 2453 "LOS detected");
07003408 2454 if (temp && !hc->chan[hc->dnum[0]].los)
af69fb3a 2455 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
475be4d8 2456 "LOS gone");
af69fb3a 2457 }
07003408 2458 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dnum[0]].cfg)) {
af69fb3a
KK		 2459 /* AIS */
2460 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
07003408 2461 if (!temp && hc->chan[hc->dnum[0]].ais)
af69fb3a 2462 signal_state_up(dch, L1_SIGNAL_AIS_ON,
475be4d8 2463 "AIS detected");
07003408 2464 if (temp && !hc->chan[hc->dnum[0]].ais)
af69fb3a 2465 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
475be4d8 2466 "AIS gone");
07003408 2467 hc->chan[hc->dnum[0]].ais = temp;
af69fb3a 2468 }
07003408 2469 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dnum[0]].cfg)) {
af69fb3a
KK		 2470 /* SLIP */
2471 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
07003408 2472 if (!temp && hc->chan[hc->dnum[0]].slip_rx)
af69fb3a 2473 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
475be4d8 2474 " bit SLIP detected RX");
07003408 2475 hc->chan[hc->dnum[0]].slip_rx = temp;
af69fb3a 2476 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
07003408 2477 if (!temp && hc->chan[hc->dnum[0]].slip_tx)
af69fb3a 2478 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
475be4d8 2479 " bit SLIP detected TX");
07003408 2480 hc->chan[hc->dnum[0]].slip_tx = temp;
af69fb3a 2481 }
07003408 2482 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dnum[0]].cfg)) {
af69fb3a
KK		 2483 /* RDI */
2484 temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
07003408 2485 if (!temp && hc->chan[hc->dnum[0]].rdi)
af69fb3a 2486 signal_state_up(dch, L1_SIGNAL_RDI_ON,
475be4d8 2487 "RDI detected");
07003408 2488 if (temp && !hc->chan[hc->dnum[0]].rdi)
af69fb3a 2489 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
475be4d8 2490 "RDI gone");
07003408 2491 hc->chan[hc->dnum[0]].rdi = temp;
af69fb3a
KK		 2492 }
2493 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
07003408 2494 switch (hc->chan[hc->dnum[0]].sync) {
af69fb3a
KK		 2495 case 0:
2496 if ((temp & 0x60) == 0x60) {
2497 if (debug & DEBUG_HFCMULTI_SYNC)
2498 printk(KERN_DEBUG
475be4d8
JP		 2499 "%s: (id=%d) E1 now "
2500 "in clock sync\n",
2501 __func__, hc->id);
af69fb3a 2502 HFC_outb(hc, R_RX_OFF,
07003408 2503 hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
af69fb3a 2504 HFC_outb(hc, R_TX_OFF,
07003408
AE		 2505 hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2506 hc->chan[hc->dnum[0]].sync = 1;
af69fb3a
KK		 2507 goto check_framesync;
2508 }
2509 break;
2510 case 1:
2511 if ((temp & 0x60) != 0x60) {
2512 if (debug & DEBUG_HFCMULTI_SYNC)
2513 printk(KERN_DEBUG
475be4d8
JP		 2514 "%s: (id=%d) E1 "
2515 "lost clock sync\n",
2516 __func__, hc->id);
07003408 2517 hc->chan[hc->dnum[0]].sync = 0;
af69fb3a
KK		 2518 break;
2519 }
475be4d8 2520 check_framesync:
af69fb3a
KK		 2521 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2522 if (temp == 0x27) {
2523 if (debug & DEBUG_HFCMULTI_SYNC)
2524 printk(KERN_DEBUG
475be4d8
JP		 2525 "%s: (id=%d) E1 "
2526 "now in frame sync\n",
2527 __func__, hc->id);
07003408 2528 hc->chan[hc->dnum[0]].sync = 2;
af69fb3a
KK		 2529 }
2530 break;
2531 case 2:
2532 if ((temp & 0x60) != 0x60) {
2533 if (debug & DEBUG_HFCMULTI_SYNC)
2534 printk(KERN_DEBUG
475be4d8
JP		 2535 "%s: (id=%d) E1 lost "
2536 "clock & frame sync\n",
2537 __func__, hc->id);
07003408 2538 hc->chan[hc->dnum[0]].sync = 0;
af69fb3a
KK		 2539 break;
2540 }
2541 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2542 if (temp != 0x27) {
2543 if (debug & DEBUG_HFCMULTI_SYNC)
2544 printk(KERN_DEBUG
475be4d8
JP		 2545 "%s: (id=%d) E1 "
2546 "lost frame sync\n",
2547 __func__, hc->id);
07003408 2548 hc->chan[hc->dnum[0]].sync = 1;
af69fb3a
KK		 2549 }
2550 break;
2551 }
2552 }
2553
2554 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2555 hfcmulti_watchdog(hc);
2556
2557 if (hc->leds)
2558 hfcmulti_leds(hc);
2559}
2560
2561static void
2562ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2563{
2564 struct dchannel *dch;
2565 int ch;
2566 int active;
2567 u_char st_status, temp;
2568
2569 /* state machine */
2570 for (ch = 0; ch <= 31; ch++) {
2571 if (hc->chan[ch].dch) {
2572 dch = hc->chan[ch].dch;
2573 if (r_irq_statech & 1) {
2574 HFC_outb_nodebug(hc, R_ST_SEL,
475be4d8 2575 hc->chan[ch].port);
af69fb3a
KK		 2576 /* undocumented: delay after R_ST_SEL */
2577 udelay(1);
2578 /* undocumented: status changes during read */
2579 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2580 while (st_status != (temp =
475be4d8 2581 HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
af69fb3a
KK		 2582 if (debug & DEBUG_HFCMULTI_STATE)
2583 printk(KERN_DEBUG "%s: reread "
475be4d8
JP		 2584 "STATE because %d!=%d\n",
2585 __func__, temp,
2586 st_status);
af69fb3a
KK		 2587 st_status = temp; /* repeat */
2588 }
2589
2590 /* Speech Design TE-sync indication */
2591 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
475be4d8 2592 dch->dev.D.protocol == ISDN_P_TE_S0) {
af69fb3a
KK		 2593 if (st_status & V_FR_SYNC_ST)
2594 hc->syncronized |=
475be4d8 2595 (1 << hc->chan[ch].port);
af69fb3a
KK		 2596 else
2597 hc->syncronized &=
475be4d8 2598 ~(1 << hc->chan[ch].port);
af69fb3a
KK		 2599 }
2600 dch->state = st_status & 0x0f;
2601 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2602 active = 3;
2603 else
2604 active = 7;
2605 if (dch->state == active) {
2606 HFC_outb_nodebug(hc, R_FIFO,
475be4d8 2607 (ch << 1) | 1);
af69fb3a
KK		 2608 HFC_wait_nodebug(hc);
2609 HFC_outb_nodebug(hc,
475be4d8 2610 R_INC_RES_FIFO, V_RES_F);
af69fb3a
KK		 2611 HFC_wait_nodebug(hc);
2612 dch->tx_idx = 0;
2613 }
2614 schedule_event(dch, FLG_PHCHANGE);
2615 if (debug & DEBUG_HFCMULTI_STATE)
2616 printk(KERN_DEBUG
475be4d8
JP		 2617 "%s: S/T newstate %x port %d\n",
2618 __func__, dch->state,
2619 hc->chan[ch].port);
af69fb3a
KK		 2620 }
2621 r_irq_statech >>= 1;
2622 }
2623 }
2624 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2625 plxsd_checksync(hc, 0);
2626}
2627
2628static void
2629fifo_irq(struct hfc_multi *hc, int block)
2630{
2631 int ch, j;
2632 struct dchannel *dch;
2633 struct bchannel *bch;
2634 u_char r_irq_fifo_bl;
2635
2636 r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2637 j = 0;
2638 while (j < 8) {
2639 ch = (block << 2) + (j >> 1);
2640 dch = hc->chan[ch].dch;
2641 bch = hc->chan[ch].bch;
2642 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2643 j += 2;
2644 continue;
2645 }
2646 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2647 test_bit(FLG_ACTIVE, &dch->Flags)) {
2648 hfcmulti_tx(hc, ch);
2649 /* start fifo */
2650 HFC_outb_nodebug(hc, R_FIFO, 0);
2651 HFC_wait_nodebug(hc);
2652 }
2653 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2654 test_bit(FLG_ACTIVE, &bch->Flags)) {
2655 hfcmulti_tx(hc, ch);
2656 /* start fifo */
2657 HFC_outb_nodebug(hc, R_FIFO, 0);
2658 HFC_wait_nodebug(hc);
2659 }
2660 j++;
2661 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2662 test_bit(FLG_ACTIVE, &dch->Flags)) {
2663 hfcmulti_rx(hc, ch);
2664 }
2665 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2666 test_bit(FLG_ACTIVE, &bch->Flags)) {
2667 hfcmulti_rx(hc, ch);
2668 }
2669 j++;
2670 }
2671}
2672
2673#ifdef IRQ_DEBUG
2674int irqsem;
2675#endif
2676static irqreturn_t
2677hfcmulti_interrupt(int intno, void *dev_id)
2678{
2679#ifdef IRQCOUNT_DEBUG
2680 static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
475be4d8 2681 iq5 = 0, iq6 = 0, iqcnt = 0;
af69fb3a 2682#endif
af69fb3a
KK		 2683 struct hfc_multi *hc = dev_id;
2684 struct dchannel *dch;
2685 u_char r_irq_statech, status, r_irq_misc, r_irq_oview;
2686 int i;
c31655fc
HE		 2687 void __iomem *plx_acc;
2688 u_short wval;
07003408 2689 u_char e1_syncsta, temp, temp2;
af69fb3a
KK		 2690 u_long flags;
2691
2692 if (!hc) {
2693 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2694 return IRQ_NONE;
2695 }
2696
2697 spin_lock(&hc->lock);
2698
2699#ifdef IRQ_DEBUG
2700 if (irqsem)
2701 printk(KERN_ERR "irq for card %d during irq from "
475be4d8 2702 "card %d, this is no bug.\n", hc->id + 1, irqsem);
af69fb3a
KK		 2703 irqsem = hc->id + 1;
2704#endif
db9bb63a
KK		 2705#ifdef CONFIG_MISDN_HFCMULTI_8xx
2706 if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
2707 goto irq_notforus;
2708#endif
af69fb3a
KK		 2709 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2710 spin_lock_irqsave(&plx_lock, flags);
c31655fc 2711 plx_acc = hc->plx_membase + PLX_INTCSR;
af69fb3a
KK		 2712 wval = readw(plx_acc);
2713 spin_unlock_irqrestore(&plx_lock, flags);
2714 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2715 goto irq_notforus;
2716 }
2717
2718 status = HFC_inb_nodebug(hc, R_STATUS);
2719 r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2720#ifdef IRQCOUNT_DEBUG
2721 if (r_irq_statech)
2722 iq1++;
2723 if (status & V_DTMF_STA)
2724 iq2++;
2725 if (status & V_LOST_STA)
2726 iq3++;
2727 if (status & V_EXT_IRQSTA)
2728 iq4++;
2729 if (status & V_MISC_IRQSTA)
2730 iq5++;
2731 if (status & V_FR_IRQSTA)
2732 iq6++;
2733 if (iqcnt++ > 5000) {
2734 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
475be4d8 2735 iq1, iq2, iq3, iq4, iq5, iq6);
af69fb3a
KK		 2736 iqcnt = 0;
2737 }
2738#endif
3bd69ad1 2739
af69fb3a
KK		 2740 if (!r_irq_statech &&
2741 !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
475be4d8 2742 V_MISC_IRQSTA | V_FR_IRQSTA))) {
af69fb3a
KK		 2743 /* irq is not for us */
2744 goto irq_notforus;
2745 }
2746 hc->irqcnt++;
2747 if (r_irq_statech) {
db9bb63a 2748 if (hc->ctype != HFC_TYPE_E1)
af69fb3a
KK		 2749 ph_state_irq(hc, r_irq_statech);
2750 }
2751 if (status & V_EXT_IRQSTA)
2752 ; /* external IRQ */
2753 if (status & V_LOST_STA) {
2754 /* LOST IRQ */
2755 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2756 }
2757 if (status & V_MISC_IRQSTA) {
2758 /* misc IRQ */
2759 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
9e6115f2 2760 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
af69fb3a 2761 if (r_irq_misc & V_STA_IRQ) {
db9bb63a 2762 if (hc->ctype == HFC_TYPE_E1) {
af69fb3a 2763 /* state machine */
07003408 2764 dch = hc->chan[hc->dnum[0]].dch;
af69fb3a
KK		 2765 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2766 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
475be4d8 2767 && hc->e1_getclock) {
af69fb3a
KK		 2768 if (e1_syncsta & V_FR_SYNC_E1)
2769 hc->syncronized = 1;
2770 else
2771 hc->syncronized = 0;
2772 }
2773 /* undocumented: status changes during read */
07003408
AE		 2774 temp = HFC_inb_nodebug(hc, R_E1_RD_STA);
2775 while (temp != (temp2 =
475be4d8 2776 HFC_inb_nodebug(hc, R_E1_RD_STA))) {
af69fb3a
KK		 2777 if (debug & DEBUG_HFCMULTI_STATE)
2778 printk(KERN_DEBUG "%s: reread "
475be4d8 2779 "STATE because %d!=%d\n",
07003408
AE		 2780 __func__, temp, temp2);
2781 temp = temp2; /* repeat */
af69fb3a 2782 }
07003408 2783 /* broadcast state change to all fragments */
af69fb3a
KK		 2784 if (debug & DEBUG_HFCMULTI_STATE)
2785 printk(KERN_DEBUG
475be4d8 2786 "%s: E1 (id=%d) newstate %x\n",
07003408
AE		 2787 __func__, hc->id, temp & 0x7);
2788 for (i = 0; i < hc->ports; i++) {
2789 dch = hc->chan[hc->dnum[i]].dch;
2790 dch->state = temp & 0x7;
2791 schedule_event(dch, FLG_PHCHANGE);
2792 }
2793
af69fb3a
KK		 2794 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2795 plxsd_checksync(hc, 0);
2796 }
2797 }
3bd69ad1
AE		 2798 if (r_irq_misc & V_TI_IRQ) {
2799 if (hc->iclock_on)
2800 mISDN_clock_update(hc->iclock, poll, NULL);
af69fb3a 2801 handle_timer_irq(hc);
3bd69ad1 2802 }
af69fb3a 2803
eac74af9 2804 if (r_irq_misc & V_DTMF_IRQ)
af69fb3a 2805 hfcmulti_dtmf(hc);
eac74af9 2806
af69fb3a 2807 if (r_irq_misc & V_IRQ_PROC) {
69e656cc
KK		 2808 static int irq_proc_cnt;
2809 if (!irq_proc_cnt++)
eac74af9 2810 printk(KERN_DEBUG "%s: got V_IRQ_PROC -"
475be4d8 2811 " this should not happen\n", __func__);
af69fb3a
KK		 2812 }
2813
2814 }
2815 if (status & V_FR_IRQSTA) {
2816 /* FIFO IRQ */
2817 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2818 for (i = 0; i < 8; i++) {
2819 if (r_irq_oview & (1 << i))
2820 fifo_irq(hc, i);
2821 }
2822 }
2823
2824#ifdef IRQ_DEBUG
2825 irqsem = 0;
2826#endif
2827 spin_unlock(&hc->lock);
2828 return IRQ_HANDLED;
2829
2830irq_notforus:
2831#ifdef IRQ_DEBUG
2832 irqsem = 0;
2833#endif
2834 spin_unlock(&hc->lock);
2835 return IRQ_NONE;
2836}
2837
2838
2839/*
2840 * timer callback for D-chan busy resolution. Currently no function
2841 */
2842
2843static void
e99e88a9 2844hfcmulti_dbusy_timer(struct timer_list *t)
af69fb3a
KK		 2845{
2846}
2847
2848
2849/*
2850 * activate/deactivate hardware for selected channels and mode
2851 *
2852 * configure B-channel with the given protocol
2853 * ch eqals to the HFC-channel (0-31)
2854 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2855 * for S/T, 1-31 for E1)
2856 * the hdlc interrupts will be set/unset
2857 */
2858static int
2859mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
475be4d8 2860 int bank_tx, int slot_rx, int bank_rx)
af69fb3a
KK		 2861{
2862 int flow_tx = 0, flow_rx = 0, routing = 0;
2863 int oslot_tx, oslot_rx;
2864 int conf;
2865
2866 if (ch < 0 || ch > 31)
650b2ef5 2867 return -EINVAL;
af69fb3a
KK		 2868 oslot_tx = hc->chan[ch].slot_tx;
2869 oslot_rx = hc->chan[ch].slot_rx;
2870 conf = hc->chan[ch].conf;
2871
2872 if (debug & DEBUG_HFCMULTI_MODE)
2873 printk(KERN_DEBUG
475be4d8
JP		 2874 "%s: card %d channel %d protocol %x slot old=%d new=%d "
2875 "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2876 __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2877 bank_tx, oslot_rx, slot_rx, bank_rx);
af69fb3a
KK		 2878
2879 if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2880 /* remove from slot */
2881 if (debug & DEBUG_HFCMULTI_MODE)
2882 printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
475be4d8
JP		 2883 __func__, oslot_tx);
2884 if (hc->slot_owner[oslot_tx << 1] == ch) {
af69fb3a
KK		 2885 HFC_outb(hc, R_SLOT, oslot_tx << 1);
2886 HFC_outb(hc, A_SL_CFG, 0);
db9bb63a
KK		 2887 if (hc->ctype != HFC_TYPE_XHFC)
2888 HFC_outb(hc, A_CONF, 0);
475be4d8 2889 hc->slot_owner[oslot_tx << 1] = -1;
af69fb3a
KK		 2890 } else {
2891 if (debug & DEBUG_HFCMULTI_MODE)
2892 printk(KERN_DEBUG
475be4d8
JP		 2893 "%s: we are not owner of this tx slot "
2894 "anymore, channel %d is.\n",
2895 __func__, hc->slot_owner[oslot_tx << 1]);
af69fb3a
KK		 2896 }
2897 }
2898
2899 if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2900 /* remove from slot */
2901 if (debug & DEBUG_HFCMULTI_MODE)
2902 printk(KERN_DEBUG
475be4d8
JP		 2903 "%s: remove from slot %d (RX)\n",
2904 __func__, oslot_rx);
af69fb3a
KK		 2905 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2906 HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2907 HFC_outb(hc, A_SL_CFG, 0);
2908 hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2909 } else {
2910 if (debug & DEBUG_HFCMULTI_MODE)
2911 printk(KERN_DEBUG
475be4d8
JP		 2912 "%s: we are not owner of this rx slot "
2913 "anymore, channel %d is.\n",
2914 __func__,
2915 hc->slot_owner[(oslot_rx << 1) | 1]);
af69fb3a
KK		 2916 }
2917 }
2918
2919 if (slot_tx < 0) {
2920 flow_tx = 0x80; /* FIFO->ST */
2921 /* disable pcm slot */
2922 hc->chan[ch].slot_tx = -1;
2923 hc->chan[ch].bank_tx = 0;
2924 } else {
2925 /* set pcm slot */
2926 if (hc->chan[ch].txpending)
2927 flow_tx = 0x80; /* FIFO->ST */
2928 else
2929 flow_tx = 0xc0; /* PCM->ST */
2930 /* put on slot */
2931 routing = bank_tx ? 0xc0 : 0x80;
2932 if (conf >= 0 || bank_tx > 1)
2933 routing = 0x40; /* loop */
2934 if (debug & DEBUG_HFCMULTI_MODE)
2935 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
475be4d8
JP		 2936 " %d flow %02x routing %02x conf %d (TX)\n",
2937 __func__, ch, slot_tx, bank_tx,
2938 flow_tx, routing, conf);
af69fb3a 2939 HFC_outb(hc, R_SLOT, slot_tx << 1);
475be4d8 2940 HFC_outb(hc, A_SL_CFG, (ch << 1) | routing);
db9bb63a
KK		 2941 if (hc->ctype != HFC_TYPE_XHFC)
2942 HFC_outb(hc, A_CONF,
475be4d8 2943 (conf < 0) ? 0 : (conf | V_CONF_SL));
af69fb3a
KK		 2944 hc->slot_owner[slot_tx << 1] = ch;
2945 hc->chan[ch].slot_tx = slot_tx;
2946 hc->chan[ch].bank_tx = bank_tx;
2947 }
2948 if (slot_rx < 0) {
2949 /* disable pcm slot */
2950 flow_rx = 0x80; /* ST->FIFO */
2951 hc->chan[ch].slot_rx = -1;
2952 hc->chan[ch].bank_rx = 0;
2953 } else {
2954 /* set pcm slot */
2955 if (hc->chan[ch].txpending)
2956 flow_rx = 0x80; /* ST->FIFO */
2957 else
2958 flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2959 /* put on slot */
eac74af9 2960 routing = bank_rx ? 0x80 : 0xc0; /* reversed */
af69fb3a
KK		 2961 if (conf >= 0 || bank_rx > 1)
2962 routing = 0x40; /* loop */
2963 if (debug & DEBUG_HFCMULTI_MODE)
2964 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
475be4d8
JP		 2965 " %d flow %02x routing %02x conf %d (RX)\n",
2966 __func__, ch, slot_rx, bank_rx,
2967 flow_rx, routing, conf);
2968 HFC_outb(hc, R_SLOT, (slot_rx << 1) | V_SL_DIR);
2969 HFC_outb(hc, A_SL_CFG, (ch << 1) | V_CH_DIR | routing);
2970 hc->slot_owner[(slot_rx << 1) | 1] = ch;
af69fb3a
KK		 2971 hc->chan[ch].slot_rx = slot_rx;
2972 hc->chan[ch].bank_rx = bank_rx;
2973 }
2974
2975 switch (protocol) {
2976 case (ISDN_P_NONE):
2977 /* disable TX fifo */
2978 HFC_outb(hc, R_FIFO, ch << 1);
2979 HFC_wait(hc);
2980 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2981 HFC_outb(hc, A_SUBCH_CFG, 0);
2982 HFC_outb(hc, A_IRQ_MSK, 0);
2983 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2984 HFC_wait(hc);
2985 /* disable RX fifo */
475be4d8 2986 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
af69fb3a
KK		 2987 HFC_wait(hc);
2988 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2989 HFC_outb(hc, A_SUBCH_CFG, 0);
2990 HFC_outb(hc, A_IRQ_MSK, 0);
2991 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2992 HFC_wait(hc);
db9bb63a 2993 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
af69fb3a 2994 hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
475be4d8 2995 ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN;
af69fb3a
KK		 2996 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2997 /* undocumented: delay after R_ST_SEL */
2998 udelay(1);
2999 HFC_outb(hc, A_ST_CTRL0,
475be4d8 3000 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
af69fb3a
KK		 3001 }
3002 if (hc->chan[ch].bch) {
3003 test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3004 test_and_clear_bit(FLG_TRANSPARENT,
475be4d8 3005 &hc->chan[ch].bch->Flags);
af69fb3a
KK		 3006 }
3007 break;
3008 case (ISDN_P_B_RAW): /* B-channel */
3009
3010 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
3011 (hc->chan[ch].slot_rx < 0) &&
3012 (hc->chan[ch].slot_tx < 0)) {
3013
3014 printk(KERN_DEBUG
475be4d8
JP		 3015 "Setting B-channel %d to echo cancelable "
3016 "state on PCM slot %d\n", ch,
3017 ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
af69fb3a 3018 printk(KERN_DEBUG
475be4d8 3019 "Enabling pass through for channel\n");
af69fb3a 3020 vpm_out(hc, ch, ((ch / 4) * 8) +
475be4d8 3021 ((ch % 4) * 4) + 1, 0x01);
af69fb3a
KK		 3022 /* rx path */
3023 /* S/T -> PCM */
3024 HFC_outb(hc, R_FIFO, (ch << 1));
3025 HFC_wait(hc);
3026 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3027 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
475be4d8 3028 ((ch % 4) * 4) + 1) << 1);
af69fb3a
KK		 3029 HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
3030
3031 /* PCM -> FIFO */
3032 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
3033 HFC_wait(hc);
3034 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3035 HFC_outb(hc, A_SUBCH_CFG, 0);
3036 HFC_outb(hc, A_IRQ_MSK, 0);
a4d729d0
AE		 3037 if (hc->chan[ch].protocol != protocol) {
3038 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3039 HFC_wait(hc);
3040 }
af69fb3a 3041 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
475be4d8 3042 ((ch % 4) * 4) + 1) << 1) | 1);
af69fb3a
KK		 3043 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
3044
3045 /* tx path */
3046 /* PCM -> S/T */
3047 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3048 HFC_wait(hc);
3049 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3050 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
475be4d8 3051 ((ch % 4) * 4)) << 1) | 1);
af69fb3a
KK		 3052 HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
3053
3054 /* FIFO -> PCM */
3055 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
3056 HFC_wait(hc);
3057 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3058 HFC_outb(hc, A_SUBCH_CFG, 0);
3059 HFC_outb(hc, A_IRQ_MSK, 0);
a4d729d0
AE		 3060 if (hc->chan[ch].protocol != protocol) {
3061 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3062 HFC_wait(hc);
3063 }
af69fb3a 3064 /* tx silence */
8dd2f36f 3065 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
af69fb3a 3066 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
475be4d8 3067 ((ch % 4) * 4)) << 1);
af69fb3a
KK		 3068 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
3069 } else {
3070 /* enable TX fifo */
3071 HFC_outb(hc, R_FIFO, ch << 1);
3072 HFC_wait(hc);
db9bb63a
KK		 3073 if (hc->ctype == HFC_TYPE_XHFC)
3074 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 |
475be4d8
JP		 3075 V_HDLC_TRP | V_IFF);
3076 /* Enable FIFO, no interrupt */
db9bb63a
KK		 3077 else
3078 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
475be4d8 3079 V_HDLC_TRP | V_IFF);
af69fb3a
KK		 3080 HFC_outb(hc, A_SUBCH_CFG, 0);
3081 HFC_outb(hc, A_IRQ_MSK, 0);
a4d729d0
AE		 3082 if (hc->chan[ch].protocol != protocol) {
3083 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3084 HFC_wait(hc);
3085 }
af69fb3a 3086 /* tx silence */
8dd2f36f 3087 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
af69fb3a 3088 /* enable RX fifo */
475be4d8 3089 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
af69fb3a 3090 HFC_wait(hc);
db9bb63a
KK		 3091 if (hc->ctype == HFC_TYPE_XHFC)
3092 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 |
475be4d8
JP		 3093 V_HDLC_TRP);
3094 /* Enable FIFO, no interrupt*/
db9bb63a
KK		 3095 else
3096 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 |
475be4d8 3097 V_HDLC_TRP);
af69fb3a
KK		 3098 HFC_outb(hc, A_SUBCH_CFG, 0);
3099 HFC_outb(hc, A_IRQ_MSK, 0);
a4d729d0
AE		 3100 if (hc->chan[ch].protocol != protocol) {
3101 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3102 HFC_wait(hc);
3103 }
af69fb3a 3104 }
db9bb63a 3105 if (hc->ctype != HFC_TYPE_E1) {
af69fb3a 3106 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
475be4d8 3107 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
af69fb3a
KK		 3108 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3109 /* undocumented: delay after R_ST_SEL */
3110 udelay(1);
3111 HFC_outb(hc, A_ST_CTRL0,
475be4d8 3112 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
af69fb3a
KK		 3113 }
3114 if (hc->chan[ch].bch)
3115 test_and_set_bit(FLG_TRANSPARENT,
475be4d8 3116 &hc->chan[ch].bch->Flags);
af69fb3a
KK		 3117 break;
3118 case (ISDN_P_B_HDLC): /* B-channel */
3119 case (ISDN_P_TE_S0): /* D-channel */
3120 case (ISDN_P_NT_S0):
3121 case (ISDN_P_TE_E1):
3122 case (ISDN_P_NT_E1):
3123 /* enable TX fifo */
475be4d8 3124 HFC_outb(hc, R_FIFO, ch << 1);
af69fb3a 3125 HFC_wait(hc);
db9bb63a 3126 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) {
af69fb3a
KK		 3127 /* E1 or B-channel */
3128 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3129 HFC_outb(hc, A_SUBCH_CFG, 0);
3130 } else {
3131 /* D-Channel without HDLC fill flags */
3132 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3133 HFC_outb(hc, A_SUBCH_CFG, 2);
3134 }
3135 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3136 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3137 HFC_wait(hc);
3138 /* enable RX fifo */
475be4d8 3139 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
af69fb3a
KK		 3140 HFC_wait(hc);
3141 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
db9bb63a 3142 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch)
af69fb3a
KK		 3143 HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3144 else
3145 HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3146 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3147 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3148 HFC_wait(hc);
3149 if (hc->chan[ch].bch) {
3150 test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
db9bb63a 3151 if (hc->ctype != HFC_TYPE_E1) {
af69fb3a 3152 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
475be4d8 3153 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
af69fb3a
KK		 3154 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3155 /* undocumented: delay after R_ST_SEL */
3156 udelay(1);
3157 HFC_outb(hc, A_ST_CTRL0,
475be4d8 3158 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
af69fb3a
KK		 3159 }
3160 }
3161 break;
3162 default:
3163 printk(KERN_DEBUG "%s: protocol not known %x\n",
475be4d8 3164 __func__, protocol);
af69fb3a
KK		 3165 hc->chan[ch].protocol = ISDN_P_NONE;
3166 return -ENOPROTOOPT;
3167 }
3168 hc->chan[ch].protocol = protocol;
3169 return 0;
3170}
3171
3172
3173/*
3174 * connect/disconnect PCM
3175 */
3176
3177static void
3178hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
475be4d8 3179 int slot_rx, int bank_rx)
af69fb3a 3180{
073bd90f 3181 if (slot_tx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
af69fb3a
KK		 3182 /* disable PCM */
3183 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3184 return;
3185 }
3186
3187 /* enable pcm */
3188 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
475be4d8 3189 slot_rx, bank_rx);
af69fb3a
KK		 3190}
3191
3192/*
3193 * set/disable conference
3194 */
3195
3196static void
3197hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3198{
3199 if (num >= 0 && num <= 7)
3200 hc->chan[ch].conf = num;
3201 else
3202 hc->chan[ch].conf = -1;
3203 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
475be4d8
JP		 3204 hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3205 hc->chan[ch].bank_rx);
af69fb3a
KK		 3206}
3207
3208
3209/*
3210 * set/disable sample loop
3211 */
3212
3213/* NOTE: this function is experimental and therefore disabled */
3214
3215/*
3216 * Layer 1 callback function
3217 */
3218static int
3219hfcm_l1callback(struct dchannel *dch, u_int cmd)
3220{
3221 struct hfc_multi *hc = dch->hw;
3222 u_long flags;
3223
3224 switch (cmd) {
3225 case INFO3_P8:
3226 case INFO3_P10:
3227 break;
3228 case HW_RESET_REQ:
3229 /* start activation */
3230 spin_lock_irqsave(&hc->lock, flags);
db9bb63a 3231 if (hc->ctype == HFC_TYPE_E1) {
af69fb3a
KK		 3232 if (debug & DEBUG_HFCMULTI_MSG)
3233 printk(KERN_DEBUG
475be4d8
JP		 3234 "%s: HW_RESET_REQ no BRI\n",
3235 __func__);
af69fb3a
KK		 3236 } else {
3237 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3238 /* undocumented: delay after R_ST_SEL */
3239 udelay(1);
3240 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3241 udelay(6); /* wait at least 5,21us */
3242 HFC_outb(hc, A_ST_WR_STATE, 3);
475be4d8
JP		 3243 HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT * 3));
3244 /* activate */
af69fb3a
KK		 3245 }
3246 spin_unlock_irqrestore(&hc->lock, flags);
3247 l1_event(dch->l1, HW_POWERUP_IND);
3248 break;
3249 case HW_DEACT_REQ:
3250 /* start deactivation */
3251 spin_lock_irqsave(&hc->lock, flags);
db9bb63a 3252 if (hc->ctype == HFC_TYPE_E1) {
af69fb3a
KK		 3253 if (debug & DEBUG_HFCMULTI_MSG)
3254 printk(KERN_DEBUG
475be4d8
JP		 3255 "%s: HW_DEACT_REQ no BRI\n",
3256 __func__);
af69fb3a
KK		 3257 } else {
3258 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3259 /* undocumented: delay after R_ST_SEL */
3260 udelay(1);
475be4d8
JP		 3261 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3262 /* deactivate */
af69fb3a
KK		 3263 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3264 hc->syncronized &=
475be4d8 3265 ~(1 << hc->chan[dch->slot].port);
af69fb3a
KK		 3266 plxsd_checksync(hc, 0);
3267 }
3268 }
3269 skb_queue_purge(&dch->squeue);
3270 if (dch->tx_skb) {
3271 dev_kfree_skb(dch->tx_skb);
3272 dch->tx_skb = NULL;
3273 }
3274 dch->tx_idx = 0;
3275 if (dch->rx_skb) {
3276 dev_kfree_skb(dch->rx_skb);
3277 dch->rx_skb = NULL;
3278 }
3279 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3280 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3281 del_timer(&dch->timer);
3282 spin_unlock_irqrestore(&hc->lock, flags);
3283 break;
3284 case HW_POWERUP_REQ:
3285 spin_lock_irqsave(&hc->lock, flags);
db9bb63a 3286 if (hc->ctype == HFC_TYPE_E1) {
af69fb3a
KK		 3287 if (debug & DEBUG_HFCMULTI_MSG)
3288 printk(KERN_DEBUG
475be4d8
JP		 3289 "%s: HW_POWERUP_REQ no BRI\n",
3290 __func__);
af69fb3a
KK		 3291 } else {
3292 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3293 /* undocumented: delay after R_ST_SEL */
3294 udelay(1);
3295 HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3296 udelay(6); /* wait at least 5,21us */
3297 HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3298 }
3299 spin_unlock_irqrestore(&hc->lock, flags);
3300 break;
3301 case PH_ACTIVATE_IND:
3302 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3303 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
475be4d8 3304 GFP_ATOMIC);
af69fb3a
KK		 3305 break;
3306 case PH_DEACTIVATE_IND:
3307 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3308 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
475be4d8 3309 GFP_ATOMIC);
af69fb3a
KK		 3310 break;
3311 default:
3312 if (dch->debug & DEBUG_HW)
3313 printk(KERN_DEBUG "%s: unknown command %x\n",
475be4d8 3314 __func__, cmd);
af69fb3a
KK		 3315 return -1;
3316 }
3317 return 0;
3318}
3319
3320/*
3321 * Layer2 -> Layer 1 Transfer
3322 */
3323
3324static int
3325handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3326{
3327 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
3328 struct dchannel *dch = container_of(dev, struct dchannel, dev);
3329 struct hfc_multi *hc = dch->hw;
3330 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3331 int ret = -EINVAL;
3332 unsigned int id;
3333 u_long flags;
3334
3335 switch (hh->prim) {
3336 case PH_DATA_REQ:
3337 if (skb->len < 1)
3338 break;
3339 spin_lock_irqsave(&hc->lock, flags);
3340 ret = dchannel_senddata(dch, skb);
3341 if (ret > 0) { /* direct TX */
3342 id = hh->id; /* skb can be freed */
3343 hfcmulti_tx(hc, dch->slot);
3344 ret = 0;
3345 /* start fifo */
3346 HFC_outb(hc, R_FIFO, 0);
3347 HFC_wait(hc);
3348 spin_unlock_irqrestore(&hc->lock, flags);
3349 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3350 } else
3351 spin_unlock_irqrestore(&hc->lock, flags);
3352 return ret;
3353 case PH_ACTIVATE_REQ:
3354 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3355 spin_lock_irqsave(&hc->lock, flags);
3356 ret = 0;
3357 if (debug & DEBUG_HFCMULTI_MSG)
3358 printk(KERN_DEBUG
475be4d8
JP		 3359 "%s: PH_ACTIVATE port %d (0..%d)\n",
3360 __func__, hc->chan[dch->slot].port,
3361 hc->ports - 1);
af69fb3a 3362 /* start activation */
db9bb63a 3363 if (hc->ctype == HFC_TYPE_E1) {
af69fb3a
KK		 3364 ph_state_change(dch);
3365 if (debug & DEBUG_HFCMULTI_STATE)
3366 printk(KERN_DEBUG
475be4d8
JP		 3367 "%s: E1 report state %x \n",
3368 __func__, dch->state);
af69fb3a
KK		 3369 } else {
3370 HFC_outb(hc, R_ST_SEL,
475be4d8 3371 hc->chan[dch->slot].port);
af69fb3a
KK		 3372 /* undocumented: delay after R_ST_SEL */
3373 udelay(1);
3374 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
475be4d8 3375 /* G1 */
af69fb3a
KK		 3376 udelay(6); /* wait at least 5,21us */
3377 HFC_outb(hc, A_ST_WR_STATE, 1);
3378 HFC_outb(hc, A_ST_WR_STATE, 1 |
475be4d8 3379 (V_ST_ACT * 3)); /* activate */
af69fb3a
KK		 3380 dch->state = 1;
3381 }
3382 spin_unlock_irqrestore(&hc->lock, flags);
3383 } else
3384 ret = l1_event(dch->l1, hh->prim);
3385 break;
3386 case PH_DEACTIVATE_REQ:
3387 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3388 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3389 spin_lock_irqsave(&hc->lock, flags);
3390 if (debug & DEBUG_HFCMULTI_MSG)
3391 printk(KERN_DEBUG
475be4d8
JP		 3392 "%s: PH_DEACTIVATE port %d (0..%d)\n",
3393 __func__, hc->chan[dch->slot].port,
3394 hc->ports - 1);
af69fb3a 3395 /* start deactivation */
db9bb63a 3396 if (hc->ctype == HFC_TYPE_E1) {
af69fb3a
KK		 3397 if (debug & DEBUG_HFCMULTI_MSG)
3398 printk(KERN_DEBUG
475be4d8
JP		 3399 "%s: PH_DEACTIVATE no BRI\n",
3400 __func__);
af69fb3a
KK		 3401 } else {
3402 HFC_outb(hc, R_ST_SEL,
475be4d8 3403 hc->chan[dch->slot].port);
af69fb3a
KK		 3404 /* undocumented: delay after R_ST_SEL */
3405 udelay(1);
3406 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
475be4d8 3407 /* deactivate */
af69fb3a
KK		 3408 dch->state = 1;
3409 }
3410 skb_queue_purge(&dch->squeue);
3411 if (dch->tx_skb) {
3412 dev_kfree_skb(dch->tx_skb);
3413 dch->tx_skb = NULL;
3414 }
3415 dch->tx_idx = 0;
3416 if (dch->rx_skb) {
3417 dev_kfree_skb(dch->rx_skb);
3418 dch->rx_skb = NULL;
3419 }
3420 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3421 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3422 del_timer(&dch->timer);
3423#ifdef FIXME
3424 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3425 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3426#endif
3427 ret = 0;
3428 spin_unlock_irqrestore(&hc->lock, flags);
3429 } else
3430 ret = l1_event(dch->l1, hh->prim);
3431 break;
3432 }
3433 if (!ret)
3434 dev_kfree_skb(skb);
3435 return ret;
3436}
3437
3438static void
3439deactivate_bchannel(struct bchannel *bch)
3440{
3441 struct hfc_multi *hc = bch->hw;
3442 u_long flags;
3443
3444 spin_lock_irqsave(&hc->lock, flags);
fb286f04 3445 mISDN_clear_bchannel(bch);
af69fb3a 3446 hc->chan[bch->slot].coeff_count = 0;
af69fb3a
KK		 3447 hc->chan[bch->slot].rx_off = 0;
3448 hc->chan[bch->slot].conf = -1;
3449 mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3450 spin_unlock_irqrestore(&hc->lock, flags);
3451}
3452
3453static int
3454handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3455{
3456 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3457 struct hfc_multi *hc = bch->hw;
3458 int ret = -EINVAL;
3459 struct mISDNhead *hh = mISDN_HEAD_P(skb);
8bfddfbe 3460 unsigned long flags;
af69fb3a
KK		 3461
3462 switch (hh->prim) {
3463 case PH_DATA_REQ:
3464 if (!skb->len)
3465 break;
3466 spin_lock_irqsave(&hc->lock, flags);
3467 ret = bchannel_senddata(bch, skb);
3468 if (ret > 0) { /* direct TX */
af69fb3a
KK		 3469 hfcmulti_tx(hc, bch->slot);
3470 ret = 0;
3471 /* start fifo */
3472 HFC_outb_nodebug(hc, R_FIFO, 0);
3473 HFC_wait_nodebug(hc);
8bfddfbe
KK		 3474 }
3475 spin_unlock_irqrestore(&hc->lock, flags);
af69fb3a
KK		 3476 return ret;
3477 case PH_ACTIVATE_REQ:
3478 if (debug & DEBUG_HFCMULTI_MSG)
3479 printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
475be4d8 3480 __func__, bch->slot);
af69fb3a
KK		 3481 spin_lock_irqsave(&hc->lock, flags);
3482 /* activate B-channel if not already activated */
3483 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3484 hc->chan[bch->slot].txpending = 0;
3485 ret = mode_hfcmulti(hc, bch->slot,
475be4d8
JP		 3486 ch->protocol,
3487 hc->chan[bch->slot].slot_tx,
3488 hc->chan[bch->slot].bank_tx,
3489 hc->chan[bch->slot].slot_rx,
3490 hc->chan[bch->slot].bank_rx);
af69fb3a
KK		 3491 if (!ret) {
3492 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
475be4d8 3493 && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
af69fb3a
KK		 3494 /* start decoder */
3495 hc->dtmf = 1;
3496 if (debug & DEBUG_HFCMULTI_DTMF)
3497 printk(KERN_DEBUG
475be4d8
JP		 3498 "%s: start dtmf decoder\n",
3499 __func__);
af69fb3a 3500 HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
475be4d8 3501 V_RST_DTMF);
af69fb3a
KK		 3502 }
3503 }
3504 } else
3505 ret = 0;
3506 spin_unlock_irqrestore(&hc->lock, flags);
3507 if (!ret)
3508 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
475be4d8 3509 GFP_KERNEL);
af69fb3a
KK		 3510 break;
3511 case PH_CONTROL_REQ:
3512 spin_lock_irqsave(&hc->lock, flags);
3513 switch (hh->id) {
3514 case HFC_SPL_LOOP_ON: /* set sample loop */
3515 if (debug & DEBUG_HFCMULTI_MSG)
eac74af9 3516 printk(KERN_DEBUG
475be4d8
JP		 3517 "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3518 __func__, skb->len);
af69fb3a
KK		 3519 ret = 0;
3520 break;
3521 case HFC_SPL_LOOP_OFF: /* set silence */
3522 if (debug & DEBUG_HFCMULTI_MSG)
3523 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
475be4d8 3524 __func__);
af69fb3a
KK		 3525 ret = 0;
3526 break;
3527 default:
3528 printk(KERN_ERR
475be4d8
JP		 3529 "%s: unknown PH_CONTROL_REQ info %x\n",
3530 __func__, hh->id);
af69fb3a
KK		 3531 ret = -EINVAL;
3532 }
3533 spin_unlock_irqrestore(&hc->lock, flags);
3534 break;
3535 case PH_DEACTIVATE_REQ:
3536 deactivate_bchannel(bch); /* locked there */
3537 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
475be4d8 3538 GFP_KERNEL);
af69fb3a
KK		 3539 ret = 0;
3540 break;
3541 }
3542 if (!ret)
3543 dev_kfree_skb(skb);
3544 return ret;
3545}
3546
3547/*
3548 * bchannel control function
3549 */
3550static int
3551channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3552{
3553 int ret = 0;
3554 struct dsp_features *features =
3555 (struct dsp_features *)(*((u_long *)&cq->p1));
3556 struct hfc_multi *hc = bch->hw;
3557 int slot_tx;
3558 int bank_tx;
3559 int slot_rx;
3560 int bank_rx;
3561 int num;
3562
3563 switch (cq->op) {
3564 case MISDN_CTRL_GETOP:
034005a0 3565 ret = mISDN_ctrl_bchannel(bch, cq);
c27b46e7 3566 cq->op |= MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP;
af69fb3a
KK		 3567 break;
3568 case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
c27b46e7 3569 ret = mISDN_ctrl_bchannel(bch, cq);
af69fb3a
KK		 3570 hc->chan[bch->slot].rx_off = !!cq->p1;
3571 if (!hc->chan[bch->slot].rx_off) {
3572 /* reset fifo on rx on */
3573 HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3574 HFC_wait_nodebug(hc);
3575 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3576 HFC_wait_nodebug(hc);
3577 }
3578 if (debug & DEBUG_HFCMULTI_MSG)
3579 printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
475be4d8 3580 __func__, bch->nr, hc->chan[bch->slot].rx_off);
af69fb3a 3581 break;
6d1ee48f
KK		 3582 case MISDN_CTRL_FILL_EMPTY:
3583 ret = mISDN_ctrl_bchannel(bch, cq);
3584 hc->silence = bch->fill[0];
3585 memset(hc->silence_data, hc->silence, sizeof(hc->silence_data));
8dd2f36f 3586 break;
af69fb3a
KK		 3587 case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3588 if (debug & DEBUG_HFCMULTI_MSG)
3589 printk(KERN_DEBUG "%s: HW_FEATURE request\n",
475be4d8 3590 __func__);
af69fb3a
KK		 3591 /* create confirm */
3592 features->hfc_id = hc->id;
3593 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3594 features->hfc_dtmf = 1;
db9bb63a
KK		 3595 if (test_bit(HFC_CHIP_CONF, &hc->chip))
3596 features->hfc_conf = 1;
af69fb3a
KK		 3597 features->hfc_loops = 0;
3598 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3599 features->hfc_echocanhw = 1;
3600 } else {
3601 features->pcm_id = hc->pcm;
3602 features->pcm_slots = hc->slots;
3603 features->pcm_banks = 2;
3604 }
3605 break;
3606 case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3607 slot_tx = cq->p1 & 0xff;
3608 bank_tx = cq->p1 >> 8;
3609 slot_rx = cq->p2 & 0xff;
3610 bank_rx = cq->p2 >> 8;
3611 if (debug & DEBUG_HFCMULTI_MSG)
3612 printk(KERN_DEBUG
475be4d8
JP		 3613 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3614 "slot %d bank %d (RX)\n",
3615 __func__, slot_tx, bank_tx,
3616 slot_rx, bank_rx);
af69fb3a
KK		 3617 if (slot_tx < hc->slots && bank_tx <= 2 &&
3618 slot_rx < hc->slots && bank_rx <= 2)
3619 hfcmulti_pcm(hc, bch->slot,
475be4d8 3620 slot_tx, bank_tx, slot_rx, bank_rx);
af69fb3a
KK		 3621 else {
3622 printk(KERN_WARNING
475be4d8
JP		 3623 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3624 "slot %d bank %d (RX) out of range\n",
3625 __func__, slot_tx, bank_tx,
3626 slot_rx, bank_rx);
af69fb3a
KK		 3627 ret = -EINVAL;
3628 }
3629 break;
3630 case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3631 if (debug & DEBUG_HFCMULTI_MSG)
3632 printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
475be4d8 3633 __func__);
af69fb3a
KK		 3634 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3635 break;
3636 case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3637 num = cq->p1 & 0xff;
3638 if (debug & DEBUG_HFCMULTI_MSG)
3639 printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
475be4d8 3640 __func__, num);
af69fb3a
KK		 3641 if (num <= 7)
3642 hfcmulti_conf(hc, bch->slot, num);
3643 else {
3644 printk(KERN_WARNING
475be4d8
JP		 3645 "%s: HW_CONF_JOIN conf %d out of range\n",
3646 __func__, num);
af69fb3a
KK		 3647 ret = -EINVAL;
3648 }
3649 break;
3650 case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3651 if (debug & DEBUG_HFCMULTI_MSG)
3652 printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3653 hfcmulti_conf(hc, bch->slot, -1);
3654 break;
3655 case MISDN_CTRL_HFC_ECHOCAN_ON:
3656 if (debug & DEBUG_HFCMULTI_MSG)
3657 printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3658 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3659 vpm_echocan_on(hc, bch->slot, cq->p1);
3660 else
3661 ret = -EINVAL;
3662 break;
3663
3664 case MISDN_CTRL_HFC_ECHOCAN_OFF:
3665 if (debug & DEBUG_HFCMULTI_MSG)
3666 printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
475be4d8 3667 __func__);
af69fb3a
KK		 3668 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3669 vpm_echocan_off(hc, bch->slot);
3670 else
3671 ret = -EINVAL;
3672 break;
3673 default:
034005a0 3674 ret = mISDN_ctrl_bchannel(bch, cq);
af69fb3a
KK		 3675 break;
3676 }
3677 return ret;
3678}
3679
3680static int
3681hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3682{
3683 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3684 struct hfc_multi *hc = bch->hw;
3685 int err = -EINVAL;
3686 u_long flags;
3687
3688 if (bch->debug & DEBUG_HW)
3689 printk(KERN_DEBUG "%s: cmd:%x %p\n",
475be4d8 3690 __func__, cmd, arg);
af69fb3a
KK		 3691 switch (cmd) {
3692 case CLOSE_CHANNEL:
3693 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1368112c 3694 deactivate_bchannel(bch); /* locked there */
af69fb3a
KK		 3695 ch->protocol = ISDN_P_NONE;
3696 ch->peer = NULL;
3697 module_put(THIS_MODULE);
3698 err = 0;
3699 break;
3700 case CONTROL_CHANNEL:
3701 spin_lock_irqsave(&hc->lock, flags);
3702 err = channel_bctrl(bch, arg);
3703 spin_unlock_irqrestore(&hc->lock, flags);
3704 break;
3705 default:
3706 printk(KERN_WARNING "%s: unknown prim(%x)\n",
475be4d8 3707 __func__, cmd);
af69fb3a
KK		 3708 }
3709 return err;
3710}
3711
3712/*
3713 * handle D-channel events
3714 *
3715 * handle state change event
3716 */
3717static void
3718ph_state_change(struct dchannel *dch)
3719{
20b78804 3720 struct hfc_multi *hc;
af69fb3a
KK		 3721 int ch, i;
3722
3723 if (!dch) {
eac74af9 3724 printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__);
af69fb3a
KK		 3725 return;
3726 }
20b78804 3727 hc = dch->hw;
af69fb3a
KK		 3728 ch = dch->slot;
3729
db9bb63a 3730 if (hc->ctype == HFC_TYPE_E1) {
af69fb3a
KK		 3731 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3732 if (debug & DEBUG_HFCMULTI_STATE)
3733 printk(KERN_DEBUG
475be4d8
JP		 3734 "%s: E1 TE (id=%d) newstate %x\n",
3735 __func__, hc->id, dch->state);
af69fb3a
KK		 3736 } else {
3737 if (debug & DEBUG_HFCMULTI_STATE)
3738 printk(KERN_DEBUG
475be4d8
JP		 3739 "%s: E1 NT (id=%d) newstate %x\n",
3740 __func__, hc->id, dch->state);
af69fb3a
KK		 3741 }
3742 switch (dch->state) {
3743 case (1):
3744 if (hc->e1_state != 1) {
eac74af9
KK		 3745 for (i = 1; i <= 31; i++) {
3746 /* reset fifos on e1 activation */
3747 HFC_outb_nodebug(hc, R_FIFO,
475be4d8 3748 (i << 1) | 1);
eac74af9
KK		 3749 HFC_wait_nodebug(hc);
3750 HFC_outb_nodebug(hc, R_INC_RES_FIFO,
475be4d8 3751 V_RES_F);
eac74af9
KK		 3752 HFC_wait_nodebug(hc);
3753 }
af69fb3a
KK		 3754 }
3755 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3756 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
475be4d8 3757 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
af69fb3a
KK		 3758 break;
3759
3760 default:
3761 if (hc->e1_state != 1)
3762 return;
3763 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3764 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
475be4d8 3765 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
af69fb3a
KK		 3766 }
3767 hc->e1_state = dch->state;
3768 } else {
3769 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3770 if (debug & DEBUG_HFCMULTI_STATE)
3771 printk(KERN_DEBUG
475be4d8
JP		 3772 "%s: S/T TE newstate %x\n",
3773 __func__, dch->state);
af69fb3a
KK		 3774 switch (dch->state) {
3775 case (0):
3776 l1_event(dch->l1, HW_RESET_IND);
3777 break;
3778 case (3):
3779 l1_event(dch->l1, HW_DEACT_IND);
3780 break;
3781 case (5):
3782 case (8):
3783 l1_event(dch->l1, ANYSIGNAL);
3784 break;
3785 case (6):
3786 l1_event(dch->l1, INFO2);
3787 break;
3788 case (7):
3789 l1_event(dch->l1, INFO4_P8);
3790 break;
3791 }
3792 } else {
3793 if (debug & DEBUG_HFCMULTI_STATE)
3794 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
475be4d8 3795 __func__, dch->state);
af69fb3a
KK		 3796 switch (dch->state) {
3797 case (2):
3798 if (hc->chan[ch].nt_timer == 0) {
3799 hc->chan[ch].nt_timer = -1;
3800 HFC_outb(hc, R_ST_SEL,
475be4d8 3801 hc->chan[ch].port);
af69fb3a
KK		 3802 /* undocumented: delay after R_ST_SEL */
3803 udelay(1);
3804 HFC_outb(hc, A_ST_WR_STATE, 4 |
475be4d8 3805 V_ST_LD_STA); /* G4 */
af69fb3a
KK		 3806 udelay(6); /* wait at least 5,21us */
3807 HFC_outb(hc, A_ST_WR_STATE, 4);
3808 dch->state = 4;
3809 } else {
3810 /* one extra count for the next event */
3811 hc->chan[ch].nt_timer =
475be4d8 3812 nt_t1_count[poll_timer] + 1;
af69fb3a 3813 HFC_outb(hc, R_ST_SEL,
475be4d8 3814 hc->chan[ch].port);
af69fb3a
KK		 3815 /* undocumented: delay after R_ST_SEL */
3816 udelay(1);
3817 /* allow G2 -> G3 transition */
3818 HFC_outb(hc, A_ST_WR_STATE, 2 |
475be4d8 3819 V_SET_G2_G3);
af69fb3a
KK		 3820 }
3821 break;
3822 case (1):
3823 hc->chan[ch].nt_timer = -1;
3824 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3825 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
475be4d8 3826 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
af69fb3a
KK		 3827 break;
3828 case (4):
3829 hc->chan[ch].nt_timer = -1;
3830 break;
3831 case (3):
3832 hc->chan[ch].nt_timer = -1;
3833 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3834 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
475be4d8 3835 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
af69fb3a
KK		 3836 break;
3837 }
3838 }
3839 }
3840}
3841
3842/*
3843 * called for card mode init message
3844 */
3845
3846static void
3847hfcmulti_initmode(struct dchannel *dch)
3848{
3849 struct hfc_multi *hc = dch->hw;
3850 u_char a_st_wr_state, r_e1_wr_sta;
3851 int i, pt;
3852
3853 if (debug & DEBUG_HFCMULTI_INIT)
3854 printk(KERN_DEBUG "%s: entered\n", __func__);
3855
07003408
AE		 3856 i = dch->slot;
3857 pt = hc->chan[i].port;
db9bb63a 3858 if (hc->ctype == HFC_TYPE_E1) {
07003408
AE		 3859 /* E1 */
3860 hc->chan[hc->dnum[pt]].slot_tx = -1;
3861 hc->chan[hc->dnum[pt]].slot_rx = -1;
3862 hc->chan[hc->dnum[pt]].conf = -1;
3863 if (hc->dnum[pt]) {
3864 mode_hfcmulti(hc, dch->slot, dch->dev.D.protocol,
475be4d8 3865 -1, 0, -1, 0);
e99e88a9 3866 timer_setup(&dch->timer, hfcmulti_dbusy_timer, 0);
af69fb3a
KK		 3867 }
3868 for (i = 1; i <= 31; i++) {
07003408 3869 if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
af69fb3a
KK		 3870 continue;
3871 hc->chan[i].slot_tx = -1;
3872 hc->chan[i].slot_rx = -1;
3873 hc->chan[i].conf = -1;
3874 mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3875 }
07003408
AE		 3876 }
3877 if (hc->ctype == HFC_TYPE_E1 && pt == 0) {
3878 /* E1, port 0 */
3879 dch = hc->chan[hc->dnum[0]].dch;
3880 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
af69fb3a
KK		 3881 HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3882 HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3883 }
07003408 3884 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dnum[0]].cfg)) {
af69fb3a
KK		 3885 HFC_outb(hc, R_RX0, 0);
3886 hc->hw.r_tx0 = 0 | V_OUT_EN;
3887 } else {
3888 HFC_outb(hc, R_RX0, 1);
3889 hc->hw.r_tx0 = 1 | V_OUT_EN;
3890 }
3891 hc->hw.r_tx1 = V_ATX | V_NTRI;
3892 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3893 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3894 HFC_outb(hc, R_TX_FR0, 0x00);
3895 HFC_outb(hc, R_TX_FR1, 0xf8);
3896
07003408 3897 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
af69fb3a
KK		 3898 HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3899
3900 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3901
07003408 3902 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
af69fb3a
KK		 3903 HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3904
3905 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3906 if (debug & DEBUG_HFCMULTI_INIT)
3907 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
475be4d8 3908 __func__);
af69fb3a
KK		 3909 r_e1_wr_sta = 0; /* G0 */
3910 hc->e1_getclock = 0;
3911 } else {
3912 if (debug & DEBUG_HFCMULTI_INIT)
3913 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
475be4d8 3914 __func__);
af69fb3a
KK		 3915 r_e1_wr_sta = 0; /* F0 */
3916 hc->e1_getclock = 1;
3917 }
3918 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3919 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3920 else
3921 HFC_outb(hc, R_SYNC_OUT, 0);
3922 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3923 hc->e1_getclock = 1;
3924 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3925 hc->e1_getclock = 0;
3926 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3927 /* SLAVE (clock master) */
3928 if (debug & DEBUG_HFCMULTI_INIT)
3929 printk(KERN_DEBUG
475be4d8
JP		 3930 "%s: E1 port is clock master "
3931 "(clock from PCM)\n", __func__);
af69fb3a
KK		 3932 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3933 } else {
3934 if (hc->e1_getclock) {
3935 /* MASTER (clock slave) */
3936 if (debug & DEBUG_HFCMULTI_INIT)
3937 printk(KERN_DEBUG
475be4d8
JP		 3938 "%s: E1 port is clock slave "
3939 "(clock to PCM)\n", __func__);
af69fb3a
KK		 3940 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3941 } else {
3942 /* MASTER (clock master) */
3943 if (debug & DEBUG_HFCMULTI_INIT)
3944 printk(KERN_DEBUG "%s: E1 port is "
475be4d8
JP		 3945 "clock master "
3946 "(clock from QUARTZ)\n",
3947 __func__);
af69fb3a 3948 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
475be4d8 3949 V_PCM_SYNC | V_JATT_OFF);
af69fb3a
KK		 3950 HFC_outb(hc, R_SYNC_OUT, 0);
3951 }
3952 }
3953 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3954 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3955 HFC_outb(hc, R_PWM0, 0x50);
3956 HFC_outb(hc, R_PWM1, 0xff);
3957 /* state machine setup */
3958 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3959 udelay(6); /* wait at least 5,21us */
3960 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3961 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3962 hc->syncronized = 0;
3963 plxsd_checksync(hc, 0);
3964 }
07003408
AE		 3965 }
3966 if (hc->ctype != HFC_TYPE_E1) {
3967 /* ST */
af69fb3a
KK		 3968 hc->chan[i].slot_tx = -1;
3969 hc->chan[i].slot_rx = -1;
3970 hc->chan[i].conf = -1;
3971 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
e99e88a9 3972 timer_setup(&dch->timer, hfcmulti_dbusy_timer, 0);
af69fb3a
KK		 3973 hc->chan[i - 2].slot_tx = -1;
3974 hc->chan[i - 2].slot_rx = -1;
3975 hc->chan[i - 2].conf = -1;
3976 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3977 hc->chan[i - 1].slot_tx = -1;
3978 hc->chan[i - 1].slot_rx = -1;
3979 hc->chan[i - 1].conf = -1;
3980 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
af69fb3a
KK		 3981 /* select interface */
3982 HFC_outb(hc, R_ST_SEL, pt);
3983 /* undocumented: delay after R_ST_SEL */
3984 udelay(1);
3985 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3986 if (debug & DEBUG_HFCMULTI_INIT)
3987 printk(KERN_DEBUG
475be4d8
JP		 3988 "%s: ST port %d is NT-mode\n",
3989 __func__, pt);
af69fb3a
KK		 3990 /* clock delay */
3991 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3992 a_st_wr_state = 1; /* G1 */
3993 hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3994 } else {
3995 if (debug & DEBUG_HFCMULTI_INIT)
3996 printk(KERN_DEBUG
475be4d8
JP		 3997 "%s: ST port %d is TE-mode\n",
3998 __func__, pt);
af69fb3a
KK		 3999 /* clock delay */
4000 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
4001 a_st_wr_state = 2; /* F2 */
4002 hc->hw.a_st_ctrl0[pt] = 0;
4003 }
4004 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
4005 hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
db9bb63a
KK		 4006 if (hc->ctype == HFC_TYPE_XHFC) {
4007 hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */;
4008 HFC_outb(hc, 0x35 /* A_ST_CTRL3 */,
475be4d8 4009 0x7c << 1 /* V_ST_PULSE */);
db9bb63a 4010 }
af69fb3a
KK		 4011 /* line setup */
4012 HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]);
4013 /* disable E-channel */
4014 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
4015 test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
4016 HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
4017 else
4018 HFC_outb(hc, A_ST_CTRL1, 0);
4019 /* enable B-channel receive */
4020 HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN);
4021 /* state machine setup */
4022 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
4023 udelay(6); /* wait at least 5,21us */
4024 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
4025 hc->hw.r_sci_msk |= 1 << pt;
4026 /* state machine interrupts */
4027 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
4028 /* unset sync on port */
4029 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4030 hc->syncronized &=
475be4d8 4031 ~(1 << hc->chan[dch->slot].port);
af69fb3a
KK		 4032 plxsd_checksync(hc, 0);
4033 }
4034 }
4035 if (debug & DEBUG_HFCMULTI_INIT)
4036 printk("%s: done\n", __func__);
4037}
4038
4039
4040static int
4041open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
475be4d8 4042 struct channel_req *rq)
af69fb3a
KK		 4043{
4044 int err = 0;
4045 u_long flags;
4046
4047 if (debug & DEBUG_HW_OPEN)
4048 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
475be4d8 4049 dch->dev.id, __builtin_return_address(0));
af69fb3a
KK		 4050 if (rq->protocol == ISDN_P_NONE)
4051 return -EINVAL;
4052 if ((dch->dev.D.protocol != ISDN_P_NONE) &&
4053 (dch->dev.D.protocol != rq->protocol)) {
eac74af9
KK		 4054 if (debug & DEBUG_HFCMULTI_MODE)
4055 printk(KERN_DEBUG "%s: change protocol %x to %x\n",
475be4d8 4056 __func__, dch->dev.D.protocol, rq->protocol);
af69fb3a 4057 }
eac74af9
KK		 4058 if ((dch->dev.D.protocol == ISDN_P_TE_S0) &&
4059 (rq->protocol != ISDN_P_TE_S0))
af69fb3a
KK		 4060 l1_event(dch->l1, CLOSE_CHANNEL);
4061 if (dch->dev.D.protocol != rq->protocol) {
4062 if (rq->protocol == ISDN_P_TE_S0) {
4063 err = create_l1(dch, hfcm_l1callback);
4064 if (err)
4065 return err;
4066 }
4067 dch->dev.D.protocol = rq->protocol;
4068 spin_lock_irqsave(&hc->lock, flags);
4069 hfcmulti_initmode(dch);
4070 spin_unlock_irqrestore(&hc->lock, flags);
4071 }
d2fb5496 4072 if (test_bit(FLG_ACTIVE, &dch->Flags))
af69fb3a 4073 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
475be4d8 4074 0, NULL, GFP_KERNEL);
af69fb3a
KK		 4075 rq->ch = &dch->dev.D;
4076 if (!try_module_get(THIS_MODULE))
4077 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4078 return 0;
4079}
4080
4081static int
4082open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
475be4d8 4083 struct channel_req *rq)
af69fb3a
KK		 4084{
4085 struct bchannel *bch;
4086 int ch;
4087
ff4cc1de 4088 if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
af69fb3a
KK		 4089 return -EINVAL;
4090 if (rq->protocol == ISDN_P_NONE)
4091 return -EINVAL;
db9bb63a 4092 if (hc->ctype == HFC_TYPE_E1)
af69fb3a
KK		 4093 ch = rq->adr.channel;
4094 else
4095 ch = (rq->adr.channel - 1) + (dch->slot - 2);
4096 bch = hc->chan[ch].bch;
4097 if (!bch) {
4098 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
475be4d8 4099 __func__, ch);
af69fb3a
KK		 4100 return -EINVAL;
4101 }
4102 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
4103 return -EBUSY; /* b-channel can be only open once */
4104 bch->ch.protocol = rq->protocol;
4105 hc->chan[ch].rx_off = 0;
4106 rq->ch = &bch->ch;
4107 if (!try_module_get(THIS_MODULE))
4108 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4109 return 0;
4110}
4111
4112/*
4113 * device control function
4114 */
4115static int
4116channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4117{
7df3bb8f 4118 struct hfc_multi *hc = dch->hw;
af69fb3a 4119 int ret = 0;
7df3bb8f 4120 int wd_mode, wd_cnt;
af69fb3a
KK		 4121
4122 switch (cq->op) {
4123 case MISDN_CTRL_GETOP:
c626c127 4124 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_L1_TIMER3;
7df3bb8f
AE		 4125 break;
4126 case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */
4127 wd_cnt = cq->p1 & 0xf;
4128 wd_mode = !!(cq->p1 >> 4);
4129 if (debug & DEBUG_HFCMULTI_MSG)
eac74af9 4130 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s"
475be4d8
JP		 4131 ", counter 0x%x\n", __func__,
4132 wd_mode ? "AUTO" : "MANUAL", wd_cnt);
7df3bb8f
AE		 4133 /* set the watchdog timer */
4134 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4));
4135 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0);
4136 if (hc->ctype == HFC_TYPE_XHFC)
4137 hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */;
4138 /* init the watchdog register and reset the counter */
4139 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4140 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4141 /* enable the watchdog output for Speech-Design */
eac74af9
KK		 4142 HFC_outb(hc, R_GPIO_SEL, V_GPIO_SEL7);
4143 HFC_outb(hc, R_GPIO_EN1, V_GPIO_EN15);
7df3bb8f
AE		 4144 HFC_outb(hc, R_GPIO_OUT1, 0);
4145 HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15);
4146 }
4147 break;
4148 case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */
4149 if (debug & DEBUG_HFCMULTI_MSG)
4150 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n",
475be4d8 4151 __func__);
7df3bb8f 4152 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
af69fb3a 4153 break;
c626c127
KK		 4154 case MISDN_CTRL_L1_TIMER3:
4155 ret = l1_event(dch->l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
4156 break;
af69fb3a
KK		 4157 default:
4158 printk(KERN_WARNING "%s: unknown Op %x\n",
475be4d8 4159 __func__, cq->op);
af69fb3a
KK		 4160 ret = -EINVAL;
4161 break;
4162 }
4163 return ret;
4164}
4165
4166static int
4167hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4168{
4169 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
4170 struct dchannel *dch = container_of(dev, struct dchannel, dev);
4171 struct hfc_multi *hc = dch->hw;
4172 struct channel_req *rq;
4173 int err = 0;
4174 u_long flags;
4175
4176 if (dch->debug & DEBUG_HW)
4177 printk(KERN_DEBUG "%s: cmd:%x %p\n",
475be4d8 4178 __func__, cmd, arg);
af69fb3a
KK		 4179 switch (cmd) {
4180 case OPEN_CHANNEL:
4181 rq = arg;
4182 switch (rq->protocol) {
4183 case ISDN_P_TE_S0:
4184 case ISDN_P_NT_S0:
db9bb63a 4185 if (hc->ctype == HFC_TYPE_E1) {
af69fb3a
KK		 4186 err = -EINVAL;
4187 break;
4188 }
4189 err = open_dchannel(hc, dch, rq); /* locked there */
4190 break;
4191 case ISDN_P_TE_E1:
4192 case ISDN_P_NT_E1:
db9bb63a 4193 if (hc->ctype != HFC_TYPE_E1) {
af69fb3a
KK		 4194 err = -EINVAL;
4195 break;
4196 }
4197 err = open_dchannel(hc, dch, rq); /* locked there */
4198 break;
4199 default:
4200 spin_lock_irqsave(&hc->lock, flags);
4201 err = open_bchannel(hc, dch, rq);
4202 spin_unlock_irqrestore(&hc->lock, flags);
4203 }
4204 break;
4205 case CLOSE_CHANNEL:
4206 if (debug & DEBUG_HW_OPEN)
4207 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
475be4d8
JP		 4208 __func__, dch->dev.id,
4209 __builtin_return_address(0));
af69fb3a
KK		 4210 module_put(THIS_MODULE);
4211 break;
4212 case CONTROL_CHANNEL:
4213 spin_lock_irqsave(&hc->lock, flags);
4214 err = channel_dctrl(dch, arg);
4215 spin_unlock_irqrestore(&hc->lock, flags);
4216 break;
4217 default:
4218 if (dch->debug & DEBUG_HW)
4219 printk(KERN_DEBUG "%s: unknown command %x\n",
475be4d8 4220 __func__, cmd);
af69fb3a
KK		 4221 err = -EINVAL;
4222 }
4223 return err;
4224}
4225
3bd69ad1
AE		 4226static int
4227clockctl(void *priv, int enable)
4228{
4229 struct hfc_multi *hc = priv;
4230
4231 hc->iclock_on = enable;
4232 return 0;
4233}
4234
af69fb3a
KK		 4235/*
4236 * initialize the card
4237 */
4238
4239/*
4240 * start timer irq, wait some time and check if we have interrupts.
4241 * if not, reset chip and try again.
4242 */
4243static int
4244init_card(struct hfc_multi *hc)
4245{
4246 int err = -EIO;
4247 u_long flags;
c31655fc 4248 void __iomem *plx_acc;
af69fb3a
KK		 4249 u_long plx_flags;
4250
4251 if (debug & DEBUG_HFCMULTI_INIT)
4252 printk(KERN_DEBUG "%s: entered\n", __func__);
4253
4254 spin_lock_irqsave(&hc->lock, flags);
4255 /* set interrupts but leave global interrupt disabled */
4256 hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4257 disable_hwirq(hc);
4258 spin_unlock_irqrestore(&hc->lock, flags);
4259
db9bb63a 4260 if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED,
475be4d8 4261 "HFC-multi", hc)) {
af69fb3a 4262 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
475be4d8 4263 hc->irq);
db9bb63a 4264 hc->irq = 0;
af69fb3a
KK		 4265 return -EIO;
4266 }
af69fb3a
KK		 4267
4268 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4269 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 4270 plx_acc = hc->plx_membase + PLX_INTCSR;
af69fb3a 4271 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
475be4d8 4272 plx_acc); /* enable PCI & LINT1 irq */
af69fb3a
KK		 4273 spin_unlock_irqrestore(&plx_lock, plx_flags);
4274 }
4275
4276 if (debug & DEBUG_HFCMULTI_INIT)
4277 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
475be4d8 4278 __func__, hc->irq, hc->irqcnt);
af69fb3a
KK		 4279 err = init_chip(hc);
4280 if (err)
4281 goto error;
4282 /*
4283 * Finally enable IRQ output
698f9315 4284 * this is only allowed, if an IRQ routine is already
af69fb3a
KK		 4285 * established for this HFC, so don't do that earlier
4286 */
4287 spin_lock_irqsave(&hc->lock, flags);
4288 enable_hwirq(hc);
4289 spin_unlock_irqrestore(&hc->lock, flags);
4290 /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4291 set_current_state(TASK_UNINTERRUPTIBLE);
475be4d8 4292 schedule_timeout((100 * HZ) / 1000); /* Timeout 100ms */
af69fb3a
KK		 4293 /* turn IRQ off until chip is completely initialized */
4294 spin_lock_irqsave(&hc->lock, flags);
4295 disable_hwirq(hc);
4296 spin_unlock_irqrestore(&hc->lock, flags);
4297 if (debug & DEBUG_HFCMULTI_INIT)
4298 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
475be4d8 4299 __func__, hc->irq, hc->irqcnt);
af69fb3a
KK		 4300 if (hc->irqcnt) {
4301 if (debug & DEBUG_HFCMULTI_INIT)
4302 printk(KERN_DEBUG "%s: done\n", __func__);
4303
4304 return 0;
4305 }
4306 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4307 printk(KERN_INFO "ignoring missing interrupts\n");
4308 return 0;
4309 }
4310
4311 printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
475be4d8 4312 hc->irq);
af69fb3a
KK		 4313
4314 err = -EIO;
4315
4316error:
4317 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4318 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 4319 plx_acc = hc->plx_membase + PLX_INTCSR;
af69fb3a
KK		 4320 writew(0x00, plx_acc); /*disable IRQs*/
4321 spin_unlock_irqrestore(&plx_lock, plx_flags);
4322 }
4323
4324 if (debug & DEBUG_HFCMULTI_INIT)
eac74af9 4325 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq);
af69fb3a
KK		 4326 if (hc->irq) {
4327 free_irq(hc->irq, hc);
4328 hc->irq = 0;
4329 }
4330
4331 if (debug & DEBUG_HFCMULTI_INIT)
4332 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4333 return err;
4334}
4335
4336/*
4337 * find pci device and set it up
4338 */
4339
4340static int
4341setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
475be4d8 4342 const struct pci_device_id *ent)
af69fb3a
KK		 4343{
4344 struct hm_map *m = (struct hm_map *)ent->driver_data;
4345
4346 printk(KERN_INFO
475be4d8
JP		 4347 "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4348 m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
af69fb3a
KK		 4349
4350 hc->pci_dev = pdev;
4351 if (m->clock2)
4352 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4353
fae846e2
BH		 4354 if (ent->vendor == PCI_VENDOR_ID_DIGIUM &&
4355 ent->device == PCI_DEVICE_ID_DIGIUM_HFC4S) {
af69fb3a
KK		 4356 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4357 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4358 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4359 hc->slots = 32;
4360 }
4361
4362 if (hc->pci_dev->irq <= 0) {
4363 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4364 return -EIO;
4365 }
4366 if (pci_enable_device(hc->pci_dev)) {
4367 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4368 return -EIO;
4369 }
4370 hc->leds = m->leds;
4371 hc->ledstate = 0xAFFEAFFE;
4372 hc->opticalsupport = m->opticalsupport;
4373
db9bb63a
KK		 4374 hc->pci_iobase = 0;
4375 hc->pci_membase = NULL;
4376 hc->plx_membase = NULL;
4377
af69fb3a
KK		 4378 /* set memory access methods */
4379 if (m->io_mode) /* use mode from card config */
4380 hc->io_mode = m->io_mode;
4381 switch (hc->io_mode) {
4382 case HFC_IO_MODE_PLXSD:
4383 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4384 hc->slots = 128; /* required */
af69fb3a
KK		 4385 hc->HFC_outb = HFC_outb_pcimem;
4386 hc->HFC_inb = HFC_inb_pcimem;
4387 hc->HFC_inw = HFC_inw_pcimem;
4388 hc->HFC_wait = HFC_wait_pcimem;
4389 hc->read_fifo = read_fifo_pcimem;
4390 hc->write_fifo = write_fifo_pcimem;
af69fb3a
KK		 4391 hc->plx_origmembase = hc->pci_dev->resource[0].start;
4392 /* MEMBASE 1 is PLX PCI Bridge */
4393
4394 if (!hc->plx_origmembase) {
4395 printk(KERN_WARNING
475be4d8 4396 "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
af69fb3a
KK		 4397 pci_disable_device(hc->pci_dev);
4398 return -EIO;
4399 }
4400
4401 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4402 if (!hc->plx_membase) {
4403 printk(KERN_WARNING
475be4d8
JP		 4404 "HFC-multi: failed to remap plx address space. "
4405 "(internal error)\n");
af69fb3a
KK		 4406 pci_disable_device(hc->pci_dev);
4407 return -EIO;
4408 }
4409 printk(KERN_INFO
475be4d8
JP		 4410 "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4411 (u_long)hc->plx_membase, hc->plx_origmembase);
af69fb3a
KK		 4412
4413 hc->pci_origmembase = hc->pci_dev->resource[2].start;
475be4d8 4414 /* MEMBASE 1 is PLX PCI Bridge */
af69fb3a
KK		 4415 if (!hc->pci_origmembase) {
4416 printk(KERN_WARNING
475be4d8 4417 "HFC-multi: No IO-Memory for PCI card found\n");
af69fb3a
KK		 4418 pci_disable_device(hc->pci_dev);
4419 return -EIO;
4420 }
4421
4422 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4423 if (!hc->pci_membase) {
4424 printk(KERN_WARNING "HFC-multi: failed to remap io "
475be4d8 4425 "address space. (internal error)\n");
af69fb3a
KK		 4426 pci_disable_device(hc->pci_dev);
4427 return -EIO;
4428 }
4429
4430 printk(KERN_INFO
475be4d8
JP		 4431 "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4432 "leds-type %d\n",
4433 hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4434 hc->pci_dev->irq, HZ, hc->leds);
af69fb3a
KK		 4435 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4436 break;
4437 case HFC_IO_MODE_PCIMEM:
db9bb63a
KK		 4438 hc->HFC_outb = HFC_outb_pcimem;
4439 hc->HFC_inb = HFC_inb_pcimem;
4440 hc->HFC_inw = HFC_inw_pcimem;
4441 hc->HFC_wait = HFC_wait_pcimem;
4442 hc->read_fifo = read_fifo_pcimem;
4443 hc->write_fifo = write_fifo_pcimem;
af69fb3a
KK		 4444 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4445 if (!hc->pci_origmembase) {
4446 printk(KERN_WARNING
475be4d8 4447 "HFC-multi: No IO-Memory for PCI card found\n");
af69fb3a
KK		 4448 pci_disable_device(hc->pci_dev);
4449 return -EIO;
4450 }
4451
4452 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4453 if (!hc->pci_membase) {
4454 printk(KERN_WARNING
475be4d8
JP		 4455 "HFC-multi: failed to remap io address space. "
4456 "(internal error)\n");
af69fb3a
KK		 4457 pci_disable_device(hc->pci_dev);
4458 return -EIO;
4459 }
db9bb63a 4460 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ "
475be4d8
JP		 4461 "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4462 hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
af69fb3a
KK		 4463 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4464 break;
4465 case HFC_IO_MODE_REGIO:
db9bb63a
KK		 4466 hc->HFC_outb = HFC_outb_regio;
4467 hc->HFC_inb = HFC_inb_regio;
4468 hc->HFC_inw = HFC_inw_regio;
4469 hc->HFC_wait = HFC_wait_regio;
4470 hc->read_fifo = read_fifo_regio;
4471 hc->write_fifo = write_fifo_regio;
af69fb3a
KK		 4472 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4473 if (!hc->pci_iobase) {
4474 printk(KERN_WARNING
475be4d8 4475 "HFC-multi: No IO for PCI card found\n");
af69fb3a
KK		 4476 pci_disable_device(hc->pci_dev);
4477 return -EIO;
4478 }
4479
4480 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4481 printk(KERN_WARNING "HFC-multi: failed to request "
475be4d8
JP		 4482 "address space at 0x%08lx (internal error)\n",
4483 hc->pci_iobase);
af69fb3a
KK		 4484 pci_disable_device(hc->pci_dev);
4485 return -EIO;
4486 }
4487
4488 printk(KERN_INFO
475be4d8
JP		 4489 "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4490 m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4491 hc->pci_dev->irq, HZ, hc->leds);
af69fb3a
KK		 4492 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4493 break;
4494 default:
4495 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4496 pci_disable_device(hc->pci_dev);
4497 return -EIO;
4498 }
4499
4500 pci_set_drvdata(hc->pci_dev, hc);
4501
4502 /* At this point the needed PCI config is done */
4503 /* fifos are still not enabled */
4504 return 0;
4505}
4506
4507
4508/*
4509 * remove port
4510 */
4511
4512static void
4513release_port(struct hfc_multi *hc, struct dchannel *dch)
4514{
4515 int pt, ci, i = 0;
4516 u_long flags;
4517 struct bchannel *pb;
4518
4519 ci = dch->slot;
4520 pt = hc->chan[ci].port;
4521
4522 if (debug & DEBUG_HFCMULTI_INIT)
4523 printk(KERN_DEBUG "%s: entered for port %d\n",
475be4d8 4524 __func__, pt + 1);
af69fb3a
KK		 4525
4526 if (pt >= hc->ports) {
4527 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
475be4d8 4528 __func__, pt + 1);
af69fb3a
KK		 4529 return;
4530 }
4531
4532 if (debug & DEBUG_HFCMULTI_INIT)
4533 printk(KERN_DEBUG "%s: releasing port=%d\n",
475be4d8 4534 __func__, pt + 1);
af69fb3a
KK		 4535
4536 if (dch->dev.D.protocol == ISDN_P_TE_S0)
4537 l1_event(dch->l1, CLOSE_CHANNEL);
4538
4539 hc->chan[ci].dch = NULL;
4540
4541 if (hc->created[pt]) {
4542 hc->created[pt] = 0;
4543 mISDN_unregister_device(&dch->dev);
4544 }
4545
4546 spin_lock_irqsave(&hc->lock, flags);
4547
4548 if (dch->timer.function) {
4549 del_timer(&dch->timer);
4550 dch->timer.function = NULL;
4551 }
4552
db9bb63a 4553 if (hc->ctype == HFC_TYPE_E1) { /* E1 */
af69fb3a
KK		 4554 /* remove sync */
4555 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4556 hc->syncronized = 0;
4557 plxsd_checksync(hc, 1);
4558 }
4559 /* free channels */
4560 for (i = 0; i <= 31; i++) {
07003408
AE		 4561 if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
4562 continue;
af69fb3a
KK		 4563 if (hc->chan[i].bch) {
4564 if (debug & DEBUG_HFCMULTI_INIT)
4565 printk(KERN_DEBUG
475be4d8
JP		 4566 "%s: free port %d channel %d\n",
4567 __func__, hc->chan[i].port + 1, i);
af69fb3a
KK		 4568 pb = hc->chan[i].bch;
4569 hc->chan[i].bch = NULL;
4570 spin_unlock_irqrestore(&hc->lock, flags);
4571 mISDN_freebchannel(pb);
4572 kfree(pb);
4573 kfree(hc->chan[i].coeff);
4574 spin_lock_irqsave(&hc->lock, flags);
4575 }
4576 }
4577 } else {
4578 /* remove sync */
4579 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4580 hc->syncronized &=
475be4d8 4581 ~(1 << hc->chan[ci].port);
af69fb3a
KK		 4582 plxsd_checksync(hc, 1);
4583 }
4584 /* free channels */
4585 if (hc->chan[ci - 2].bch) {
4586 if (debug & DEBUG_HFCMULTI_INIT)
4587 printk(KERN_DEBUG
475be4d8
JP		 4588 "%s: free port %d channel %d\n",
4589 __func__, hc->chan[ci - 2].port + 1,
4590 ci - 2);
af69fb3a
KK		 4591 pb = hc->chan[ci - 2].bch;
4592 hc->chan[ci - 2].bch = NULL;
4593 spin_unlock_irqrestore(&hc->lock, flags);
4594 mISDN_freebchannel(pb);
4595 kfree(pb);
4596 kfree(hc->chan[ci - 2].coeff);
4597 spin_lock_irqsave(&hc->lock, flags);
4598 }
4599 if (hc->chan[ci - 1].bch) {
4600 if (debug & DEBUG_HFCMULTI_INIT)
4601 printk(KERN_DEBUG
475be4d8
JP		 4602 "%s: free port %d channel %d\n",
4603 __func__, hc->chan[ci - 1].port + 1,
4604 ci - 1);
af69fb3a
KK		 4605 pb = hc->chan[ci - 1].bch;
4606 hc->chan[ci - 1].bch = NULL;
4607 spin_unlock_irqrestore(&hc->lock, flags);
4608 mISDN_freebchannel(pb);
4609 kfree(pb);
4610 kfree(hc->chan[ci - 1].coeff);
4611 spin_lock_irqsave(&hc->lock, flags);
4612 }
4613 }
4614
4615 spin_unlock_irqrestore(&hc->lock, flags);
4616
4617 if (debug & DEBUG_HFCMULTI_INIT)
07003408
AE		 4618 printk(KERN_DEBUG "%s: free port %d channel D(%d)\n", __func__,
4619 pt+1, ci);
af69fb3a
KK		 4620 mISDN_freedchannel(dch);
4621 kfree(dch);
4622
4623 if (debug & DEBUG_HFCMULTI_INIT)
4624 printk(KERN_DEBUG "%s: done!\n", __func__);
4625}
4626
4627static void
4628release_card(struct hfc_multi *hc)
4629{
4630 u_long flags;
4631 int ch;
4632
4633 if (debug & DEBUG_HFCMULTI_INIT)
eac74af9 4634 printk(KERN_DEBUG "%s: release card (%d) entered\n",
475be4d8 4635 __func__, hc->id);
af69fb3a 4636
3bd69ad1
AE		 4637 /* unregister clock source */
4638 if (hc->iclock)
4639 mISDN_unregister_clock(hc->iclock);
4640
07003408 4641 /* disable and free irq */
af69fb3a
KK		 4642 spin_lock_irqsave(&hc->lock, flags);
4643 disable_hwirq(hc);
4644 spin_unlock_irqrestore(&hc->lock, flags);
af69fb3a 4645 udelay(1000);
07003408
AE		 4646 if (hc->irq) {
4647 if (debug & DEBUG_HFCMULTI_INIT)
4648 printk(KERN_DEBUG "%s: free irq %d (hc=%p)\n",
4649 __func__, hc->irq, hc);
4650 free_irq(hc->irq, hc);
4651 hc->irq = 0;
af69fb3a 4652
07003408 4653 }
af69fb3a
KK		 4654
4655 /* disable D-channels & B-channels */
4656 if (debug & DEBUG_HFCMULTI_INIT)
4657 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
475be4d8 4658 __func__);
af69fb3a
KK		 4659 for (ch = 0; ch <= 31; ch++) {
4660 if (hc->chan[ch].dch)
4661 release_port(hc, hc->chan[ch].dch);
4662 }
4663
07003408
AE		 4664 /* dimm leds */
4665 if (hc->leds)
4666 hfcmulti_leds(hc);
af69fb3a 4667
07003408 4668 /* release hardware */
af69fb3a
KK		 4669 release_io_hfcmulti(hc);
4670
4671 if (debug & DEBUG_HFCMULTI_INIT)
eac74af9 4672 printk(KERN_DEBUG "%s: remove instance from list\n",
475be4d8 4673 __func__);
af69fb3a
KK		 4674 list_del(&hc->list);
4675
4676 if (debug & DEBUG_HFCMULTI_INIT)
eac74af9 4677 printk(KERN_DEBUG "%s: delete instance\n", __func__);
af69fb3a
KK		 4678 if (hc == syncmaster)
4679 syncmaster = NULL;
4680 kfree(hc);
4681 if (debug & DEBUG_HFCMULTI_INIT)
eac74af9 4682 printk(KERN_DEBUG "%s: card successfully removed\n",
475be4d8 4683 __func__);
af69fb3a
KK		 4684}
4685
07003408
AE		 4686static void
4687init_e1_port_hw(struct hfc_multi *hc, struct hm_map *m)
af69fb3a 4688{
af69fb3a
KK		 4689 /* set optical line type */
4690 if (port[Port_cnt] & 0x001) {
4691 if (!m->opticalsupport) {
4692 printk(KERN_INFO
475be4d8
JP		 4693 "This board has no optical "
4694 "support\n");
af69fb3a
KK		 4695 } else {
4696 if (debug & DEBUG_HFCMULTI_INIT)
4697 printk(KERN_DEBUG
475be4d8
JP		 4698 "%s: PORT set optical "
4699 "interfacs: card(%d) "
4700 "port(%d)\n",
4701 __func__,
4702 HFC_cnt + 1, 1);
af69fb3a 4703 test_and_set_bit(HFC_CFG_OPTICAL,
07003408 4704 &hc->chan[hc->dnum[0]].cfg);
af69fb3a
KK		 4705 }
4706 }
4707 /* set LOS report */
4708 if (port[Port_cnt] & 0x004) {
4709 if (debug & DEBUG_HFCMULTI_INIT)
4710 printk(KERN_DEBUG "%s: PORT set "
475be4d8
JP		 4711 "LOS report: card(%d) port(%d)\n",
4712 __func__, HFC_cnt + 1, 1);
af69fb3a 4713 test_and_set_bit(HFC_CFG_REPORT_LOS,
07003408 4714 &hc->chan[hc->dnum[0]].cfg);
af69fb3a
KK		 4715 }
4716 /* set AIS report */
4717 if (port[Port_cnt] & 0x008) {
4718 if (debug & DEBUG_HFCMULTI_INIT)
4719 printk(KERN_DEBUG "%s: PORT set "
475be4d8
JP		 4720 "AIS report: card(%d) port(%d)\n",
4721 __func__, HFC_cnt + 1, 1);
af69fb3a 4722 test_and_set_bit(HFC_CFG_REPORT_AIS,
07003408 4723 &hc->chan[hc->dnum[0]].cfg);
af69fb3a
KK		 4724 }
4725 /* set SLIP report */
4726 if (port[Port_cnt] & 0x010) {
4727 if (debug & DEBUG_HFCMULTI_INIT)
4728 printk(KERN_DEBUG
475be4d8
JP		 4729 "%s: PORT set SLIP report: "
4730 "card(%d) port(%d)\n",
4731 __func__, HFC_cnt + 1, 1);
af69fb3a 4732 test_and_set_bit(HFC_CFG_REPORT_SLIP,
07003408 4733 &hc->chan[hc->dnum[0]].cfg);
af69fb3a
KK		 4734 }
4735 /* set RDI report */
4736 if (port[Port_cnt] & 0x020) {
4737 if (debug & DEBUG_HFCMULTI_INIT)
4738 printk(KERN_DEBUG
475be4d8
JP		 4739 "%s: PORT set RDI report: "
4740 "card(%d) port(%d)\n",
4741 __func__, HFC_cnt + 1, 1);
af69fb3a 4742 test_and_set_bit(HFC_CFG_REPORT_RDI,
07003408 4743 &hc->chan[hc->dnum[0]].cfg);
af69fb3a
KK		 4744 }
4745 /* set CRC-4 Mode */
4746 if (!(port[Port_cnt] & 0x100)) {
4747 if (debug & DEBUG_HFCMULTI_INIT)
4748 printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
475be4d8
JP		 4749 " card(%d) port(%d)\n",
4750 __func__, HFC_cnt + 1, 1);
af69fb3a 4751 test_and_set_bit(HFC_CFG_CRC4,
07003408 4752 &hc->chan[hc->dnum[0]].cfg);
af69fb3a
KK		 4753 } else {
4754 if (debug & DEBUG_HFCMULTI_INIT)
4755 printk(KERN_DEBUG "%s: PORT turn off CRC4"
475be4d8
JP		 4756 " report: card(%d) port(%d)\n",
4757 __func__, HFC_cnt + 1, 1);
af69fb3a
KK		 4758 }
4759 /* set forced clock */
4760 if (port[Port_cnt] & 0x0200) {
4761 if (debug & DEBUG_HFCMULTI_INIT)
4762 printk(KERN_DEBUG "%s: PORT force getting clock from "
475be4d8
JP		 4763 "E1: card(%d) port(%d)\n",
4764 __func__, HFC_cnt + 1, 1);
af69fb3a
KK		 4765 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4766 } else
475be4d8
JP		 4767 if (port[Port_cnt] & 0x0400) {
4768 if (debug & DEBUG_HFCMULTI_INIT)
4769 printk(KERN_DEBUG "%s: PORT force putting clock to "
4770 "E1: card(%d) port(%d)\n",
4771 __func__, HFC_cnt + 1, 1);
4772 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4773 }
af69fb3a
KK		 4774 /* set JATT PLL */
4775 if (port[Port_cnt] & 0x0800) {
4776 if (debug & DEBUG_HFCMULTI_INIT)
4777 printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
475be4d8
JP		 4778 "E1: card(%d) port(%d)\n",
4779 __func__, HFC_cnt + 1, 1);
af69fb3a
KK		 4780 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4781 }
4782 /* set elastic jitter buffer */
4783 if (port[Port_cnt] & 0x3000) {
07003408 4784 hc->chan[hc->dnum[0]].jitter = (port[Port_cnt]>>12) & 0x3;
af69fb3a
KK		 4785 if (debug & DEBUG_HFCMULTI_INIT)
4786 printk(KERN_DEBUG
475be4d8
JP		 4787 "%s: PORT set elastic "
4788 "buffer to %d: card(%d) port(%d)\n",
07003408 4789 __func__, hc->chan[hc->dnum[0]].jitter,
475be4d8 4790 HFC_cnt + 1, 1);
af69fb3a 4791 } else
07003408
AE		 4792 hc->chan[hc->dnum[0]].jitter = 2; /* default */
4793}
4794
4795static int
4796init_e1_port(struct hfc_multi *hc, struct hm_map *m, int pt)
4797{
4798 struct dchannel *dch;
4799 struct bchannel *bch;
4800 int ch, ret = 0;
4801 char name[MISDN_MAX_IDLEN];
4802 int bcount = 0;
4803
4804 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4805 if (!dch)
4806 return -ENOMEM;
4807 dch->debug = debug;
4808 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4809 dch->hw = hc;
4810 dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4811 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4812 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4813 dch->dev.D.send = handle_dmsg;
4814 dch->dev.D.ctrl = hfcm_dctrl;
4815 dch->slot = hc->dnum[pt];
4816 hc->chan[hc->dnum[pt]].dch = dch;
4817 hc->chan[hc->dnum[pt]].port = pt;
4818 hc->chan[hc->dnum[pt]].nt_timer = -1;
4819 for (ch = 1; ch <= 31; ch++) {
4820 if (!((1 << ch) & hc->bmask[pt])) /* skip unused channel */
4821 continue;
4822 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4823 if (!bch) {
4824 printk(KERN_ERR "%s: no memory for bchannel\n",
4825 __func__);
4826 ret = -ENOMEM;
4827 goto free_chan;
4828 }
4829 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4830 if (!hc->chan[ch].coeff) {
4831 printk(KERN_ERR "%s: no memory for coeffs\n",
4832 __func__);
4833 ret = -ENOMEM;
4834 kfree(bch);
4835 goto free_chan;
4836 }
4837 bch->nr = ch;
4838 bch->slot = ch;
4839 bch->debug = debug;
034005a0 4840 mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1);
07003408
AE		 4841 bch->hw = hc;
4842 bch->ch.send = handle_bmsg;
4843 bch->ch.ctrl = hfcm_bctrl;
4844 bch->ch.nr = ch;
4845 list_add(&bch->ch.list, &dch->dev.bchannels);
4846 hc->chan[ch].bch = bch;
4847 hc->chan[ch].port = pt;
4848 set_channelmap(bch->nr, dch->dev.channelmap);
4849 bcount++;
4850 }
4851 dch->dev.nrbchan = bcount;
4852 if (pt == 0)
4853 init_e1_port_hw(hc, m);
4854 if (hc->ports > 1)
4855 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d-%d",
4856 HFC_cnt + 1, pt+1);
4857 else
4858 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
b36b654a 4859 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
af69fb3a
KK		 4860 if (ret)
4861 goto free_chan;
07003408 4862 hc->created[pt] = 1;
af69fb3a
KK		 4863 return ret;
4864free_chan:
4865 release_port(hc, dch);
4866 return ret;
4867}
4868
4869static int
4870init_multi_port(struct hfc_multi *hc, int pt)
4871{
4872 struct dchannel *dch;
4873 struct bchannel *bch;
4874 int ch, i, ret = 0;
4875 char name[MISDN_MAX_IDLEN];
4876
4877 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4878 if (!dch)
4879 return -ENOMEM;
4880 dch->debug = debug;
4881 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4882 dch->hw = hc;
4883 dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4884 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
475be4d8 4885 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
af69fb3a
KK		 4886 dch->dev.D.send = handle_dmsg;
4887 dch->dev.D.ctrl = hfcm_dctrl;
4888 dch->dev.nrbchan = 2;
4889 i = pt << 2;
4890 dch->slot = i + 2;
4891 hc->chan[i + 2].dch = dch;
4892 hc->chan[i + 2].port = pt;
4893 hc->chan[i + 2].nt_timer = -1;
4894 for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4895 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4896 if (!bch) {
4897 printk(KERN_ERR "%s: no memory for bchannel\n",
475be4d8 4898 __func__);
af69fb3a
KK		 4899 ret = -ENOMEM;
4900 goto free_chan;
4901 }
4902 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4903 if (!hc->chan[i + ch].coeff) {
4904 printk(KERN_ERR "%s: no memory for coeffs\n",
475be4d8 4905 __func__);
af69fb3a 4906 ret = -ENOMEM;
23b904f3 4907 kfree(bch);
af69fb3a
KK		 4908 goto free_chan;
4909 }
4910 bch->nr = ch + 1;
4911 bch->slot = i + ch;
4912 bch->debug = debug;
034005a0 4913 mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1);
af69fb3a
KK		 4914 bch->hw = hc;
4915 bch->ch.send = handle_bmsg;
4916 bch->ch.ctrl = hfcm_bctrl;
4917 bch->ch.nr = ch + 1;
4918 list_add(&bch->ch.list, &dch->dev.bchannels);
4919 hc->chan[i + ch].bch = bch;
4920 hc->chan[i + ch].port = pt;
ff4cc1de 4921 set_channelmap(bch->nr, dch->dev.channelmap);
af69fb3a
KK		 4922 }
4923 /* set master clock */
4924 if (port[Port_cnt] & 0x001) {
4925 if (debug & DEBUG_HFCMULTI_INIT)
4926 printk(KERN_DEBUG
475be4d8
JP		 4927 "%s: PROTOCOL set master clock: "
4928 "card(%d) port(%d)\n",
4929 __func__, HFC_cnt + 1, pt + 1);
af69fb3a
KK		 4930 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4931 printk(KERN_ERR "Error: Master clock "
475be4d8
JP		 4932 "for port(%d) of card(%d) is only"
4933 " possible with TE-mode\n",
4934 pt + 1, HFC_cnt + 1);
af69fb3a
KK		 4935 ret = -EINVAL;
4936 goto free_chan;
4937 }
4938 if (hc->masterclk >= 0) {
4939 printk(KERN_ERR "Error: Master clock "
475be4d8
JP		 4940 "for port(%d) of card(%d) already "
4941 "defined for port(%d)\n",
4942 pt + 1, HFC_cnt + 1, hc->masterclk + 1);
af69fb3a
KK		 4943 ret = -EINVAL;
4944 goto free_chan;
4945 }
4946 hc->masterclk = pt;
4947 }
4948 /* set transmitter line to non capacitive */
4949 if (port[Port_cnt] & 0x002) {
4950 if (debug & DEBUG_HFCMULTI_INIT)
4951 printk(KERN_DEBUG
475be4d8
JP		 4952 "%s: PROTOCOL set non capacitive "
4953 "transmitter: card(%d) port(%d)\n",
4954 __func__, HFC_cnt + 1, pt + 1);
af69fb3a 4955 test_and_set_bit(HFC_CFG_NONCAP_TX,
475be4d8 4956 &hc->chan[i + 2].cfg);
af69fb3a
KK		 4957 }
4958 /* disable E-channel */
4959 if (port[Port_cnt] & 0x004) {
eac74af9 4960 if (debug & DEBUG_HFCMULTI_INIT)
af69fb3a 4961 printk(KERN_DEBUG
475be4d8
JP		 4962 "%s: PROTOCOL disable E-channel: "
4963 "card(%d) port(%d)\n",
4964 __func__, HFC_cnt + 1, pt + 1);
af69fb3a 4965 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
475be4d8 4966 &hc->chan[i + 2].cfg);
af69fb3a 4967 }
db9bb63a
KK		 4968 if (hc->ctype == HFC_TYPE_XHFC) {
4969 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d",
475be4d8 4970 HFC_cnt + 1, pt + 1);
db9bb63a
KK		 4971 ret = mISDN_register_device(&dch->dev, NULL, name);
4972 } else {
4973 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
475be4d8 4974 hc->ctype, HFC_cnt + 1, pt + 1);
db9bb63a
KK		 4975 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4976 }
af69fb3a
KK		 4977 if (ret)
4978 goto free_chan;
4979 hc->created[pt] = 1;
4980 return ret;
4981free_chan:
4982 release_port(hc, dch);
4983 return ret;
4984}
4985
4986static int
db9bb63a 4987hfcmulti_init(struct hm_map *m, struct pci_dev *pdev,
475be4d8 4988 const struct pci_device_id *ent)
af69fb3a 4989{
af69fb3a
KK		 4990 int ret_err = 0;
4991 int pt;
4992 struct hfc_multi *hc;
4993 u_long flags;
4994 u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
07003408
AE		 4995 int i, ch;
4996 u_int maskcheck;
af69fb3a
KK		 4997
4998 if (HFC_cnt >= MAX_CARDS) {
4999 printk(KERN_ERR "too many cards (max=%d).\n",
475be4d8 5000 MAX_CARDS);
af69fb3a
KK		 5001 return -EINVAL;
5002 }
5003 if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
5004 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
475be4d8
JP		 5005 "type[%d] %d was supplied as module parameter\n",
5006 m->vendor_name, m->card_name, m->type, HFC_cnt,
5007 type[HFC_cnt] & 0xff);
af69fb3a 5008 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
475be4d8 5009 "first, to see cards and their types.");
af69fb3a
KK		 5010 return -EINVAL;
5011 }
5012 if (debug & DEBUG_HFCMULTI_INIT)
5013 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
475be4d8
JP		 5014 __func__, m->vendor_name, m->card_name, m->type,
5015 type[HFC_cnt]);
af69fb3a
KK		 5016
5017 /* allocate card+fifo structure */
5018 hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
5019 if (!hc) {
5020 printk(KERN_ERR "No kmem for HFC-Multi card\n");
5021 return -ENOMEM;
5022 }
5023 spin_lock_init(&hc->lock);
5024 hc->mtyp = m;
db9bb63a 5025 hc->ctype = m->type;
af69fb3a
KK		 5026 hc->ports = m->ports;
5027 hc->id = HFC_cnt;
5028 hc->pcm = pcm[HFC_cnt];
5029 hc->io_mode = iomode[HFC_cnt];
07003408
AE		 5030 if (hc->ctype == HFC_TYPE_E1 && dmask[E1_cnt]) {
5031 /* fragment card */
5032 pt = 0;
5033 maskcheck = 0;
5034 for (ch = 0; ch <= 31; ch++) {
5035 if (!((1 << ch) & dmask[E1_cnt]))
5036 continue;
5037 hc->dnum[pt] = ch;
5038 hc->bmask[pt] = bmask[bmask_cnt++];
5039 if ((maskcheck & hc->bmask[pt])
5040 || (dmask[E1_cnt] & hc->bmask[pt])) {
5041 printk(KERN_INFO
5042 "HFC-E1 #%d has overlapping B-channels on fragment #%d\n",
5043 E1_cnt + 1, pt);
9fef7685 5044 kfree(hc);
07003408
AE		 5045 return -EINVAL;
5046 }
5047 maskcheck |= hc->bmask[pt];
5048 printk(KERN_INFO
5049 "HFC-E1 #%d uses D-channel on slot %d and a B-channel map of 0x%08x\n",
5050 E1_cnt + 1, ch, hc->bmask[pt]);
5051 pt++;
5052 }
5053 hc->ports = pt;
5054 }
5055 if (hc->ctype == HFC_TYPE_E1 && !dmask[E1_cnt]) {
5056 /* default card layout */
5057 hc->dnum[0] = 16;
5058 hc->bmask[0] = 0xfffefffe;
5059 hc->ports = 1;
5060 }
af69fb3a
KK		 5061
5062 /* set chip specific features */
5063 hc->masterclk = -1;
5064 if (type[HFC_cnt] & 0x100) {
5065 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
8dd2f36f 5066 hc->silence = 0xff; /* ulaw silence */
af69fb3a 5067 } else
8dd2f36f
AE		 5068 hc->silence = 0x2a; /* alaw silence */
5069 if ((poll >> 1) > sizeof(hc->silence_data)) {
5070 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
475be4d8 5071 "please fix\n");
9fef7685 5072 kfree(hc);
8dd2f36f
AE		 5073 return -EINVAL;
5074 }
5075 for (i = 0; i < (poll >> 1); i++)
5076 hc->silence_data[i] = hc->silence;
5077
db9bb63a
KK		 5078 if (hc->ctype != HFC_TYPE_XHFC) {
5079 if (!(type[HFC_cnt] & 0x200))
5080 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
5081 test_and_set_bit(HFC_CHIP_CONF, &hc->chip);
5082 }
af69fb3a
KK		 5083
5084 if (type[HFC_cnt] & 0x800)
5085 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5086 if (type[HFC_cnt] & 0x1000) {
5087 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
5088 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5089 }
5090 if (type[HFC_cnt] & 0x4000)
5091 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
5092 if (type[HFC_cnt] & 0x8000)
5093 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
5094 hc->slots = 32;
5095 if (type[HFC_cnt] & 0x10000)
5096 hc->slots = 64;
5097 if (type[HFC_cnt] & 0x20000)
5098 hc->slots = 128;
5099 if (type[HFC_cnt] & 0x80000) {
5100 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
5101 hc->wdcount = 0;
5102 hc->wdbyte = V_GPIO_OUT2;
5103 printk(KERN_NOTICE "Watchdog enabled\n");
5104 }
5105
db9bb63a
KK		 5106 if (pdev && ent)
5107 /* setup pci, hc->slots may change due to PLXSD */
5108 ret_err = setup_pci(hc, pdev, ent);
5109 else
5110#ifdef CONFIG_MISDN_HFCMULTI_8xx
5111 ret_err = setup_embedded(hc, m);
5112#else
5113 {
5114 printk(KERN_WARNING "Embedded IO Mode not selected\n");
5115 ret_err = -EIO;
5116 }
5117#endif
af69fb3a
KK		 5118 if (ret_err) {
5119 if (hc == syncmaster)
5120 syncmaster = NULL;
5121 kfree(hc);
5122 return ret_err;
5123 }
5124
db9bb63a
KK		 5125 hc->HFC_outb_nodebug = hc->HFC_outb;
5126 hc->HFC_inb_nodebug = hc->HFC_inb;
5127 hc->HFC_inw_nodebug = hc->HFC_inw;
5128 hc->HFC_wait_nodebug = hc->HFC_wait;
5129#ifdef HFC_REGISTER_DEBUG
5130 hc->HFC_outb = HFC_outb_debug;
5131 hc->HFC_inb = HFC_inb_debug;
5132 hc->HFC_inw = HFC_inw_debug;
5133 hc->HFC_wait = HFC_wait_debug;
5134#endif
5135 /* create channels */
af69fb3a
KK		 5136 for (pt = 0; pt < hc->ports; pt++) {
5137 if (Port_cnt >= MAX_PORTS) {
5138 printk(KERN_ERR "too many ports (max=%d).\n",
475be4d8 5139 MAX_PORTS);
af69fb3a
KK		 5140 ret_err = -EINVAL;
5141 goto free_card;
5142 }
db9bb63a 5143 if (hc->ctype == HFC_TYPE_E1)
07003408 5144 ret_err = init_e1_port(hc, m, pt);
af69fb3a
KK		 5145 else
5146 ret_err = init_multi_port(hc, pt);
5147 if (debug & DEBUG_HFCMULTI_INIT)
5148 printk(KERN_DEBUG
07003408 5149 "%s: Registering D-channel, card(%d) port(%d) "
475be4d8 5150 "result %d\n",
07003408 5151 __func__, HFC_cnt + 1, pt + 1, ret_err);
af69fb3a
KK		 5152
5153 if (ret_err) {
5154 while (pt) { /* release already registered ports */
5155 pt--;
07003408
AE		 5156 if (hc->ctype == HFC_TYPE_E1)
5157 release_port(hc,
5158 hc->chan[hc->dnum[pt]].dch);
5159 else
5160 release_port(hc,
5161 hc->chan[(pt << 2) + 2].dch);
af69fb3a
KK		 5162 }
5163 goto free_card;
5164 }
07003408
AE		 5165 if (hc->ctype != HFC_TYPE_E1)
5166 Port_cnt++; /* for each S0 port */
5167 }
5168 if (hc->ctype == HFC_TYPE_E1) {
5169 Port_cnt++; /* for each E1 port */
5170 E1_cnt++;
af69fb3a
KK		 5171 }
5172
5173 /* disp switches */
5174 switch (m->dip_type) {
5175 case DIP_4S:
5176 /*
69e656cc 5177 * Get DIP setting for beroNet 1S/2S/4S cards
af69fb3a
KK		 5178 * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
5179 * GPI 19/23 (R_GPI_IN2))
5180 */
5181 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
5182 ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
5183 (~HFC_inb(hc, R_GPI_IN2) & 0x08);
5184
5185 /* Port mode (TE/NT) jumpers */
5186 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf);
5187
5188 if (test_bit(HFC_CHIP_B410P, &hc->chip))
5189 pmj = ~pmj & 0xf;
5190
5191 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
475be4d8 5192 m->vendor_name, m->card_name, dips, pmj);
af69fb3a
KK		 5193 break;
5194 case DIP_8S:
5195 /*
69e656cc
KK		 5196 * Get DIP Setting for beroNet 8S0+ cards
5197 * Enable PCI auxbridge function
af69fb3a
KK		 5198 */
5199 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
5200 /* prepare access to auxport */
5201 outw(0x4000, hc->pci_iobase + 4);
5202 /*
5203 * some dummy reads are required to
5204 * read valid DIP switch data
5205 */
5206 dips = inb(hc->pci_iobase);
5207 dips = inb(hc->pci_iobase);
5208 dips = inb(hc->pci_iobase);
5209 dips = ~inb(hc->pci_iobase) & 0x3F;
5210 outw(0x0, hc->pci_iobase + 4);
5211 /* disable PCI auxbridge function */
5212 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
5213 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
475be4d8 5214 m->vendor_name, m->card_name, dips);
af69fb3a
KK		 5215 break;
5216 case DIP_E1:
5217 /*
5218 * get DIP Setting for beroNet E1 cards
5219 * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
5220 */
475be4d8 5221 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0) >> 4;
af69fb3a 5222 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
475be4d8 5223 m->vendor_name, m->card_name, dips);
af69fb3a
KK		 5224 break;
5225 }
5226
5227 /* add to list */
5228 spin_lock_irqsave(&HFClock, flags);
5229 list_add_tail(&hc->list, &HFClist);
5230 spin_unlock_irqrestore(&HFClock, flags);
5231
3bd69ad1
AE		 5232 /* use as clock source */
5233 if (clock == HFC_cnt + 1)
5234 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5235
af69fb3a 5236 /* initialize hardware */
db9bb63a 5237 hc->irq = (m->irq) ? : hc->pci_dev->irq;
af69fb3a
KK		 5238 ret_err = init_card(hc);
5239 if (ret_err) {
5240 printk(KERN_ERR "init card returns %d\n", ret_err);
5241 release_card(hc);
5242 return ret_err;
5243 }
5244
5245 /* start IRQ and return */
5246 spin_lock_irqsave(&hc->lock, flags);
5247 enable_hwirq(hc);
5248 spin_unlock_irqrestore(&hc->lock, flags);
5249 return 0;
5250
5251free_card:
5252 release_io_hfcmulti(hc);
5253 if (hc == syncmaster)
5254 syncmaster = NULL;
5255 kfree(hc);
5256 return ret_err;
5257}
5258
ed5a84cd 5259static void hfc_remove_pci(struct pci_dev *pdev)
af69fb3a
KK		 5260{
5261 struct hfc_multi *card = pci_get_drvdata(pdev);
5262 u_long flags;
5263
5264 if (debug)
5265 printk(KERN_INFO "removing hfc_multi card vendor:%x "
475be4d8
JP		 5266 "device:%x subvendor:%x subdevice:%x\n",
5267 pdev->vendor, pdev->device,
5268 pdev->subsystem_vendor, pdev->subsystem_device);
af69fb3a
KK		 5269
5270 if (card) {
5271 spin_lock_irqsave(&HFClock, flags);
5272 release_card(card);
5273 spin_unlock_irqrestore(&HFClock, flags);
5274 } else {
5275 if (debug)
698f9315 5276 printk(KERN_DEBUG "%s: drvdata already removed\n",
475be4d8 5277 __func__);
af69fb3a
KK		 5278 }
5279}
5280
5281#define VENDOR_CCD "Cologne Chip AG"
5282#define VENDOR_BN "beroNet GmbH"
5283#define VENDOR_DIG "Digium Inc."
5284#define VENDOR_JH "Junghanns.NET GmbH"
5285#define VENDOR_PRIM "PrimuX"
5286
5287static const struct hm_map hfcm_map[] = {
475be4d8
JP		 5288 /*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0},
5289 /*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5290 /*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5291 /*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5292 /*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0},
5293 /*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0},
5294 /*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5295 /*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0},
5296 /*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0},
5297 /*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0},
5298 /*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0},
5299 /*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0},
5300
5301 /*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0},
5302 /*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5303 HFC_IO_MODE_REGIO, 0},
5304 /*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0},
5305 /*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0},
5306
5307 /*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0},
5308 /*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5309 /*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5310
5311 /*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5312 /*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0},
5313 /*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5314 /*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5315
5316 /*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0},
5317 /*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0},
5318 /*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0},
5319
5320 /*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5321 HFC_IO_MODE_PLXSD, 0},
5322 /*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5323 HFC_IO_MODE_PLXSD, 0},
5324 /*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0},
5325 /*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0},
5326 /*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0},
5327 /*31*/ {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0,
5328 HFC_IO_MODE_EMBSD, XHFC_IRQ},
5329 /*32*/ {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0},
5330 /*33*/ {VENDOR_BN, "HFC-2S Beronet Card PCIe", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5331 /*34*/ {VENDOR_BN, "HFC-4S Beronet Card PCIe", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
af69fb3a
KK		 5332};
5333
5334#undef H
5335#define H(x) ((unsigned long)&hfcm_map[x])
e3b79fcf 5336static const struct pci_device_id hfmultipci_ids[] = {
af69fb3a
KK		 5337
5338 /* Cards with HFC-4S Chip */
5339 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5340 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
af69fb3a 5341 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5342 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
af69fb3a 5343 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5344 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
af69fb3a 5345 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5346 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
af69fb3a 5347 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5348 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
af69fb3a 5349 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5350 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
af69fb3a 5351 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5352 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
af69fb3a 5353 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5354 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
af69fb3a 5355 { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
475be4d8 5356 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
af69fb3a 5357 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5358 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
af69fb3a 5359 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5360 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
af69fb3a 5361 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5362 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
af69fb3a 5363 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5364 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
af69fb3a 5365 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5366 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
d00561a2 5367 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5368 0xb761, 0, 0, H(33)}, /* BN2S PCIe */
d00561a2 5369 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
475be4d8 5370 0xb762, 0, 0, H(34)}, /* BN4S PCIe */
af69fb3a
KK		 5371
5372 /* Cards with HFC-8S Chip */
5373 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
475be4d8 5374 PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
af69fb3a 5375 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
475be4d8 5376 PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
af69fb3a 5377 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
475be4d8 5378 PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
af69fb3a 5379 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
475be4d8 5380 PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
af69fb3a 5381 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
475be4d8 5382 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */
af69fb3a 5383 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
475be4d8 5384 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */
af69fb3a 5385 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
475be4d8 5386 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
af69fb3a 5387 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
475be4d8 5388 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
7245a2fe 5389 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
475be4d8 5390 PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S */
af69fb3a
KK		 5391
5392
5393 /* Cards with HFC-E1 Chip */
5394 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
475be4d8 5395 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
af69fb3a 5396 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
475be4d8 5397 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
af69fb3a 5398 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
475be4d8 5399 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
af69fb3a 5400 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
475be4d8 5401 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
af69fb3a
KK		 5402
5403 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
475be4d8 5404 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
af69fb3a 5405 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
475be4d8 5406 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
af69fb3a 5407 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
475be4d8 5408 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
af69fb3a
KK		 5409
5410 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
475be4d8 5411 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
af69fb3a 5412 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
475be4d8 5413 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
daebafed
AE		 5414
5415 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
475be4d8 5416 PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */
daebafed 5417
9db9f279
PH		 5418 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC4S), 0 },
5419 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC8S), 0 },
5420 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFCE1), 0 },
af69fb3a
KK		 5421 {0, }
5422};
5423#undef H
5424
5425MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5426
5427static int
5428hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5429{
5430 struct hm_map *m = (struct hm_map *)ent->driver_data;
5431 int ret;
5432
69e656cc 5433 if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
475be4d8
JP		 5434 ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5435 ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5436 ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
69e656cc 5437 printk(KERN_ERR
475be4d8
JP		 5438 "Unknown HFC multiport controller (vendor:%04x device:%04x "
5439 "subvendor:%04x subdevice:%04x)\n", pdev->vendor,
5440 pdev->device, pdev->subsystem_vendor,
5441 pdev->subsystem_device);
69e656cc 5442 printk(KERN_ERR
475be4d8 5443 "Please contact the driver maintainer for support.\n");
af69fb3a
KK		 5444 return -ENODEV;
5445 }
db9bb63a 5446 ret = hfcmulti_init(m, pdev, ent);
af69fb3a
KK		 5447 if (ret)
5448 return ret;
5449 HFC_cnt++;
5450 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5451 return 0;
5452}
5453
5454static struct pci_driver hfcmultipci_driver = {
5455 .name = "hfc_multi",
5456 .probe = hfcmulti_probe,
ed5a84cd 5457 .remove = hfc_remove_pci,
af69fb3a
KK		 5458 .id_table = hfmultipci_ids,
5459};
5460
5461static void __exit
5462HFCmulti_cleanup(void)
5463{
5464 struct hfc_multi *card, *next;
5465
69e656cc 5466 /* get rid of all devices of this driver */
af69fb3a
KK		 5467 list_for_each_entry_safe(card, next, &HFClist, list)
5468 release_card(card);
af69fb3a
KK		 5469 pci_unregister_driver(&hfcmultipci_driver);
5470}
5471
5472static int __init
5473HFCmulti_init(void)
5474{
5475 int err;
db9bb63a
KK		 5476 int i, xhfc = 0;
5477 struct hm_map m;
af69fb3a 5478
69e656cc
KK		 5479 printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5480
af69fb3a 5481#ifdef IRQ_DEBUG
69e656cc 5482 printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
af69fb3a
KK		 5483#endif
5484
5485 spin_lock_init(&HFClock);
5486 spin_lock_init(&plx_lock);
5487
5488 if (debug & DEBUG_HFCMULTI_INIT)
5489 printk(KERN_DEBUG "%s: init entered\n", __func__);
5490
af69fb3a
KK		 5491 switch (poll) {
5492 case 0:
5493 poll_timer = 6;
5494 poll = 128;
5495 break;
af69fb3a
KK		 5496 case 8:
5497 poll_timer = 2;
5498 break;
5499 case 16:
5500 poll_timer = 3;
5501 break;
5502 case 32:
5503 poll_timer = 4;
5504 break;
5505 case 64:
5506 poll_timer = 5;
5507 break;
5508 case 128:
5509 poll_timer = 6;
5510 break;
5511 case 256:
5512 poll_timer = 7;
5513 break;
5514 default:
5515 printk(KERN_ERR
475be4d8 5516 "%s: Wrong poll value (%d).\n", __func__, poll);
af69fb3a
KK		 5517 err = -EINVAL;
5518 return err;
5519
5520 }
5521
3bd69ad1
AE		 5522 if (!clock)
5523 clock = 1;
5524
db9bb63a
KK		 5525 /* Register the embedded devices.
5526 * This should be done before the PCI cards registration */
5527 switch (hwid) {
5528 case HWID_MINIP4:
5529 xhfc = 1;
5530 m = hfcm_map[31];
5531 break;
5532 case HWID_MINIP8:
5533 xhfc = 2;
5534 m = hfcm_map[31];
5535 break;
5536 case HWID_MINIP16:
5537 xhfc = 4;
5538 m = hfcm_map[31];
5539 break;
5540 default:
5541 xhfc = 0;
5542 }
5543
5544 for (i = 0; i < xhfc; ++i) {
5545 err = hfcmulti_init(&m, NULL, NULL);
5546 if (err) {
5547 printk(KERN_ERR "error registering embedded driver: "
475be4d8 5548 "%x\n", err);
2c554e10 5549 return err;
db9bb63a
KK		 5550 }
5551 HFC_cnt++;
5552 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5553 }
5554
5555 /* Register the PCI cards */
af69fb3a
KK		 5556 err = pci_register_driver(&hfcmultipci_driver);
5557 if (err < 0) {
5558 printk(KERN_ERR "error registering pci driver: %x\n", err);
af69fb3a
KK		 5559 return err;
5560 }
db9bb63a 5561
af69fb3a
KK		 5562 return 0;
5563}
5564
5565
5566module_init(HFCmulti_init);
5567module_exit(HFCmulti_cleanup);
Linux 6.x block layer and io_uring tree(s)