[linux-2.6-block.git] / drivers / irqchip / irq-vt8500.c

/*
 *  arch/arm/mach-vt8500/irq.c
 *
 *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/*
 * This file is copied and modified from the original irq.c provided by
 * Alexey Charkov. Minor changes have been made for Device Tree Support.
 */

#include <linux/slab.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>

#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>

#include <asm/irq.h>
#include <asm/exception.h>
#include <asm/mach/irq.h>

#define VT8500_ICPC_IRQ		0x20
#define VT8500_ICPC_FIQ		0x24
#define VT8500_ICDC		0x40		/* Destination Control 64*u32 */
#define VT8500_ICIS		0x80		/* Interrupt status, 16*u32 */

/* ICPC */
#define ICPC_MASK		0x3F
#define ICPC_ROTATE		BIT(6)

/* IC_DCTR */
#define ICDC_IRQ		0x00
#define ICDC_FIQ		0x01
#define ICDC_DSS0		0x02
#define ICDC_DSS1		0x03
#define ICDC_DSS2		0x04
#define ICDC_DSS3		0x05
#define ICDC_DSS4		0x06
#define ICDC_DSS5		0x07

#define VT8500_INT_DISABLE	0
#define VT8500_INT_ENABLE	BIT(3)

#define VT8500_TRIGGER_HIGH	0
#define VT8500_TRIGGER_RISING	BIT(5)
#define VT8500_TRIGGER_FALLING	BIT(6)
#define VT8500_EDGE		( VT8500_TRIGGER_RISING \
				| VT8500_TRIGGER_FALLING)

/* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
#define VT8500_INTC_MAX		2

struct vt8500_irq_data {
	void __iomem 		*base;		/* IO Memory base address */
	struct irq_domain	*domain;	/* Domain for this controller */
};

/* Global variable for accessing io-mem addresses */
static struct vt8500_irq_data intc[VT8500_INTC_MAX];
static u32 active_cnt = 0;

static void vt8500_irq_mask(struct irq_data *d)
{
	struct vt8500_irq_data *priv = d->domain->host_data;
	void __iomem *base = priv->base;
	void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
	u8 edge, dctr;
	u32 status;

	edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
	if (edge) {
		status = readl(stat_reg);

		status |= (1 << (d->hwirq & 0x1f));
		writel(status, stat_reg);
	} else {
		dctr = readb(base + VT8500_ICDC + d->hwirq);
		dctr &= ~VT8500_INT_ENABLE;
		writeb(dctr, base + VT8500_ICDC + d->hwirq);
	}
}

static void vt8500_irq_unmask(struct irq_data *d)
{
	struct vt8500_irq_data *priv = d->domain->host_data;
	void __iomem *base = priv->base;
	u8 dctr;

	dctr = readb(base + VT8500_ICDC + d->hwirq);
	dctr |= VT8500_INT_ENABLE;
	writeb(dctr, base + VT8500_ICDC + d->hwirq);
}

static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct vt8500_irq_data *priv = d->domain->host_data;
	void __iomem *base = priv->base;
	u8 dctr;

	dctr = readb(base + VT8500_ICDC + d->hwirq);
	dctr &= ~VT8500_EDGE;

	switch (flow_type) {
	case IRQF_TRIGGER_LOW:
		return -EINVAL;
	case IRQF_TRIGGER_HIGH:
		dctr |= VT8500_TRIGGER_HIGH;
		irq_set_handler_locked(d, handle_level_irq);
		break;
	case IRQF_TRIGGER_FALLING:
		dctr |= VT8500_TRIGGER_FALLING;
		irq_set_handler_locked(d, handle_edge_irq);
		break;
	case IRQF_TRIGGER_RISING:
		dctr |= VT8500_TRIGGER_RISING;
		irq_set_handler_locked(d, handle_edge_irq);
		break;
	}
	writeb(dctr, base + VT8500_ICDC + d->hwirq);

	return 0;
}

static struct irq_chip vt8500_irq_chip = {
	.name = "vt8500",
	.irq_ack = vt8500_irq_mask,
	.irq_mask = vt8500_irq_mask,
	.irq_unmask = vt8500_irq_unmask,
	.irq_set_type = vt8500_irq_set_type,
};

static void __init vt8500_init_irq_hw(void __iomem *base)
{
	u32 i;

	/* Enable rotating priority for IRQ */
	writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
	writel(0x00, base + VT8500_ICPC_FIQ);

	/* Disable all interrupts and route them to IRQ */
	for (i = 0; i < 64; i++)
		writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);
}

static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
							irq_hw_number_t hw)
{
	irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);

	return 0;
}

static const struct irq_domain_ops vt8500_irq_domain_ops = {
	.map = vt8500_irq_map,
	.xlate = irq_domain_xlate_onecell,
};

static void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
{
	u32 stat, i;
	int irqnr;
	void __iomem *base;

	/* Loop through each active controller */
	for (i=0; i<active_cnt; i++) {
		base = intc[i].base;
		irqnr = readl_relaxed(base) & 0x3F;
		/*
		  Highest Priority register default = 63, so check that this
		  is a real interrupt by checking the status register
		*/
		if (irqnr == 63) {
			stat = readl_relaxed(base + VT8500_ICIS + 4);
			if (!(stat & BIT(31)))
				continue;
		}

		handle_domain_irq(intc[i].domain, irqnr, regs);
	}
}

static int __init vt8500_irq_init(struct device_node *node,
				  struct device_node *parent)
{
	int irq, i;
	struct device_node *np = node;

	if (active_cnt == VT8500_INTC_MAX) {
		pr_err("%s: Interrupt controllers > VT8500_INTC_MAX\n",
								__func__);
		goto out;
	}

	intc[active_cnt].base = of_iomap(np, 0);
	intc[active_cnt].domain = irq_domain_add_linear(node, 64,
			&vt8500_irq_domain_ops,	&intc[active_cnt]);

	if (!intc[active_cnt].base) {
		pr_err("%s: Unable to map IO memory\n", __func__);
		goto out;
	}

	if (!intc[active_cnt].domain) {
		pr_err("%s: Unable to add irq domain!\n", __func__);
		goto out;
	}

	set_handle_irq(vt8500_handle_irq);

	vt8500_init_irq_hw(intc[active_cnt].base);

	pr_info("vt8500-irq: Added interrupt controller\n");

	active_cnt++;

	/* check if this is a slaved controller */
	if (of_irq_count(np) != 0) {
		/* check that we have the correct number of interrupts */
		if (of_irq_count(np) != 8) {
			pr_err("%s: Incorrect IRQ map for slaved controller\n",
					__func__);
			return -EINVAL;
		}

		for (i = 0; i < 8; i++) {
			irq = irq_of_parse_and_map(np, i);
			enable_irq(irq);
		}

		pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
	}
out:
	return 0;
}

IRQCHIP_DECLARE(vt8500_irq, "via,vt8500-intc", vt8500_irq_init);
Commit	Line	Data
21f47fbc AC	1	/*
	2	* arch/arm/mach-vt8500/irq.c
	3	*
e9a91de7	4	* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
21f47fbc AC	5	* Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
e9a91de7 TP	22	/*
	23	* This file is copied and modified from the original irq.c provided by
	24	* Alexey Charkov. Minor changes have been made for Device Tree Support.
	25	*/
	26
	27	#include <linux/slab.h>
21f47fbc AC	28	#include <linux/io.h>
21f47fbc AC	29	#include <linux/irq.h>
41a83e06	30	#include <linux/irqchip.h>
e9a91de7	31	#include <linux/irqdomain.h>
21f47fbc	32	#include <linux/interrupt.h>
e9a91de7 TP	33	#include <linux/bitops.h>
	34
	35	#include <linux/of.h>
	36	#include <linux/of_irq.h>
	37	#include <linux/of_address.h>
21f47fbc AC	38
21f47fbc AC	39	#include <asm/irq.h>
0c464d58	40	#include <asm/exception.h>
06ff14c0 TP	41	#include <asm/mach/irq.h>
06ff14c0 TP	42
e9a91de7 TP	43	#define VT8500_ICPC_IRQ 0x20
	44	#define VT8500_ICPC_FIQ 0x24
	45	#define VT8500_ICDC 0x40 /* Destination Control 64u32 /
	46	#define VT8500_ICIS 0x80 /* Interrupt status, 16u32 /
	47
	48	/* ICPC */
	49	#define ICPC_MASK 0x3F
	50	#define ICPC_ROTATE BIT(6)
	51
	52	/* IC_DCTR */
	53	#define ICDC_IRQ 0x00
	54	#define ICDC_FIQ 0x01
	55	#define ICDC_DSS0 0x02
	56	#define ICDC_DSS1 0x03
	57	#define ICDC_DSS2 0x04
	58	#define ICDC_DSS3 0x05
	59	#define ICDC_DSS4 0x06
	60	#define ICDC_DSS5 0x07
	61
	62	#define VT8500_INT_DISABLE 0
	63	#define VT8500_INT_ENABLE BIT(3)
	64
	65	#define VT8500_TRIGGER_HIGH 0
	66	#define VT8500_TRIGGER_RISING BIT(5)
	67	#define VT8500_TRIGGER_FALLING BIT(6)
21f47fbc AC	68	#define VT8500_EDGE ( VT8500_TRIGGER_RISING \
21f47fbc AC	69	\| VT8500_TRIGGER_FALLING)
21f47fbc	70
0c464d58 TP	71	/* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
0c464d58 TP	72	#define VT8500_INTC_MAX 2
e9a91de7	73
0c464d58 TP	74	struct vt8500_irq_data {
	75	void __iomem base; / IO Memory base address */
	76	struct irq_domain domain; / Domain for this controller */
e9a91de7	77	};
21f47fbc	78
0c464d58 TP	79	/* Global variable for accessing io-mem addresses */
	80	static struct vt8500_irq_data intc[VT8500_INTC_MAX];
	81	static u32 active_cnt = 0;
	82
2eb5af44	83	static void vt8500_irq_mask(struct irq_data *d)
21f47fbc	84	{
0c464d58	85	struct vt8500_irq_data *priv = d->domain->host_data;
e9a91de7	86	void __iomem *base = priv->base;
0c464d58 TP	87	void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
	88	u8 edge, dctr;
	89	u32 status;
21f47fbc	90
e9a91de7	91	edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
21f47fbc	92	if (edge) {
0c464d58	93	status = readl(stat_reg);
21f47fbc	94
e9a91de7	95	status \|= (1 << (d->hwirq & 0x1f));
21f47fbc AC	96	writel(status, stat_reg);
21f47fbc AC	97	} else {
0c464d58	98	dctr = readb(base + VT8500_ICDC + d->hwirq);
21f47fbc	99	dctr &= ~VT8500_INT_ENABLE;
e9a91de7	100	writeb(dctr, base + VT8500_ICDC + d->hwirq);
21f47fbc AC	101	}
	102	}
	103
2eb5af44	104	static void vt8500_irq_unmask(struct irq_data *d)
21f47fbc	105	{
0c464d58	106	struct vt8500_irq_data *priv = d->domain->host_data;
e9a91de7	107	void __iomem *base = priv->base;
21f47fbc AC	108	u8 dctr;
21f47fbc AC	109
e9a91de7	110	dctr = readb(base + VT8500_ICDC + d->hwirq);
21f47fbc	111	dctr \|= VT8500_INT_ENABLE;
e9a91de7	112	writeb(dctr, base + VT8500_ICDC + d->hwirq);
21f47fbc AC	113	}
21f47fbc AC	114
2eb5af44	115	static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
21f47fbc	116	{
0c464d58	117	struct vt8500_irq_data *priv = d->domain->host_data;
e9a91de7	118	void __iomem *base = priv->base;
21f47fbc AC	119	u8 dctr;
21f47fbc AC	120
e9a91de7	121	dctr = readb(base + VT8500_ICDC + d->hwirq);
21f47fbc AC	122	dctr &= ~VT8500_EDGE;
	123
	124	switch (flow_type) {
	125	case IRQF_TRIGGER_LOW:
	126	return -EINVAL;
	127	case IRQF_TRIGGER_HIGH:
	128	dctr \|= VT8500_TRIGGER_HIGH;
d2aa914d	129	irq_set_handler_locked(d, handle_level_irq);
21f47fbc AC	130	break;
	131	case IRQF_TRIGGER_FALLING:
	132	dctr \|= VT8500_TRIGGER_FALLING;
d2aa914d	133	irq_set_handler_locked(d, handle_edge_irq);
21f47fbc AC	134	break;
	135	case IRQF_TRIGGER_RISING:
	136	dctr \|= VT8500_TRIGGER_RISING;
d2aa914d	137	irq_set_handler_locked(d, handle_edge_irq);
21f47fbc AC	138	break;
21f47fbc AC	139	}
e9a91de7	140	writeb(dctr, base + VT8500_ICDC + d->hwirq);
21f47fbc AC	141
	142	return 0;
	143	}
	144
	145	static struct irq_chip vt8500_irq_chip = {
2eb5af44 WS	146	.name = "vt8500",
	147	.irq_ack = vt8500_irq_mask,
	148	.irq_mask = vt8500_irq_mask,
	149	.irq_unmask = vt8500_irq_unmask,
	150	.irq_set_type = vt8500_irq_set_type,
21f47fbc AC	151	};
21f47fbc AC	152
e9a91de7	153	static void __init vt8500_init_irq_hw(void __iomem *base)
21f47fbc	154	{
0c464d58	155	u32 i;
21f47fbc	156
e9a91de7 TP	157	/* Enable rotating priority for IRQ */
	158	writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
	159	writel(0x00, base + VT8500_ICPC_FIQ);
21f47fbc	160
0c464d58 TP	161	/* Disable all interrupts and route them to IRQ */
	162	for (i = 0; i < 64; i++)
	163	writeb(VT8500_INT_DISABLE \| ICDC_IRQ, base + VT8500_ICDC + i);
e9a91de7	164	}
21f47fbc	165
e9a91de7 TP	166	static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
	167	irq_hw_number_t hw)
	168	{
	169	irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
21f47fbc	170
e9a91de7	171	return 0;
21f47fbc AC	172	}
21f47fbc AC	173
96009736	174	static const struct irq_domain_ops vt8500_irq_domain_ops = {
e9a91de7 TP	175	.map = vt8500_irq_map,
	176	.xlate = irq_domain_xlate_onecell,
	177	};
	178
8783dd3a	179	static void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
0c464d58 TP	180	{
0c464d58 TP	181	u32 stat, i;
0beb6504	182	int irqnr;
0c464d58 TP	183	void __iomem *base;
	184
	185	/* Loop through each active controller */
	186	for (i=0; i<active_cnt; i++) {
	187	base = intc[i].base;
	188	irqnr = readl_relaxed(base) & 0x3F;
	189	/*
	190	Highest Priority register default = 63, so check that this
	191	is a real interrupt by checking the status register
	192	*/
	193	if (irqnr == 63) {
	194	stat = readl_relaxed(base + VT8500_ICIS + 4);
	195	if (!(stat & BIT(31)))
	196	continue;
	197	}
	198
0beb6504	199	handle_domain_irq(intc[i].domain, irqnr, regs);
0c464d58 TP	200	}
	201	}
	202
e658718e AL	203	static int __init vt8500_irq_init(struct device_node *node,
e658718e AL	204	struct device_node *parent)
21f47fbc	205	{
e9a91de7 TP	206	int irq, i;
	207	struct device_node *np = node;
	208
0c464d58 TP	209	if (active_cnt == VT8500_INTC_MAX) {
	210	pr_err("%s: Interrupt controllers > VT8500_INTC_MAX\n",
	211	__func__);
	212	goto out;
	213	}
	214
	215	intc[active_cnt].base = of_iomap(np, 0);
	216	intc[active_cnt].domain = irq_domain_add_linear(node, 64,
	217	&vt8500_irq_domain_ops, &intc[active_cnt]);
e9a91de7	218
0c464d58 TP	219	if (!intc[active_cnt].base) {
	220	pr_err("%s: Unable to map IO memory\n", __func__);
	221	goto out;
	222	}
	223
	224	if (!intc[active_cnt].domain) {
	225	pr_err("%s: Unable to add irq domain!\n", __func__);
	226	goto out;
	227	}
e9a91de7	228
06ff14c0 TP	229	set_handle_irq(vt8500_handle_irq);
06ff14c0 TP	230
0c464d58	231	vt8500_init_irq_hw(intc[active_cnt].base);
e9a91de7	232
0c464d58	233	pr_info("vt8500-irq: Added interrupt controller\n");
21f47fbc	234
0c464d58	235	active_cnt++;
e9a91de7 TP	236
	237	/* check if this is a slaved controller */
	238	if (of_irq_count(np) != 0) {
	239	/* check that we have the correct number of interrupts */
	240	if (of_irq_count(np) != 8) {
0c464d58	241	pr_err("%s: Incorrect IRQ map for slaved controller\n",
e9a91de7 TP	242	__func__);
e9a91de7 TP	243	return -EINVAL;
21f47fbc	244	}
e9a91de7 TP	245
	246	for (i = 0; i < 8; i++) {
	247	irq = irq_of_parse_and_map(np, i);
	248	enable_irq(irq);
	249	}
	250
	251	pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
21f47fbc	252	}
0c464d58	253	out:
e9a91de7	254	return 0;
21f47fbc	255	}
e9a91de7	256
06ff14c0	257	IRQCHIP_DECLARE(vt8500_irq, "via,vt8500-intc", vt8500_irq_init);