projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'pm-cpufreq'
[linux-2.6-block.git] / drivers / irqchip / irq-s3c24xx.c
CommitLineData
1f629b7a
HS		 1/*
2 * S3C24XX IRQ handling
a21765a7 3 *
e02f8664 4 * Copyright (c) 2003-2004 Simtec Electronics
a21765a7 5 * Ben Dooks <ben@simtec.co.uk>
1f629b7a 6 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
a21765a7
BD		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
a21765a7
BD		 17*/
18
19#include <linux/init.h>
1f629b7a 20#include <linux/slab.h>
a21765a7 21#include <linux/module.h>
1f629b7a
HS		 22#include <linux/io.h>
23#include <linux/err.h>
a21765a7
BD		 24#include <linux/interrupt.h>
25#include <linux/ioport.h>
edbaa603 26#include <linux/device.h>
1f629b7a 27#include <linux/irqdomain.h>
41a83e06 28#include <linux/irqchip.h>
de88cbb7 29#include <linux/irqchip/chained_irq.h>
f0774d41
HS		 30#include <linux/of.h>
31#include <linux/of_irq.h>
32#include <linux/of_address.h>
a21765a7 33
17453dd2 34#include <asm/exception.h>
a21765a7
BD		 35#include <asm/mach/irq.h>
36
1f629b7a
HS		 37#include <mach/regs-irq.h>
38#include <mach/regs-gpio.h>
a21765a7 39
a2b7ba9c 40#include <plat/cpu.h>
1f629b7a 41#include <plat/regs-irqtype.h>
a2b7ba9c 42#include <plat/pm.h>
a21765a7 43
1f629b7a
HS		 44#define S3C_IRQTYPE_NONE 0
45#define S3C_IRQTYPE_EINT 1
46#define S3C_IRQTYPE_EDGE 2
47#define S3C_IRQTYPE_LEVEL 3
a21765a7 48
1f629b7a
HS		 49struct s3c_irq_data {
50 unsigned int type;
f5a25524 51 unsigned long offset;
1f629b7a 52 unsigned long parent_irq;
a21765a7 53
1f629b7a
HS		 54 /* data gets filled during init */
55 struct s3c_irq_intc *intc;
56 unsigned long sub_bits;
57 struct s3c_irq_intc *sub_intc;
a21765a7
BD		 58};
59
1f629b7a
HS		 60/*
61 * Sructure holding the controller data
62 * @reg_pending register holding pending irqs
63 * @reg_intpnd special register intpnd in main intc
64 * @reg_mask mask register
65 * @domain irq_domain of the controller
66 * @parent parent controller for ext and sub irqs
67 * @irqs irq-data, always s3c_irq_data[32]
68 */
69struct s3c_irq_intc {
70 void __iomem *reg_pending;
71 void __iomem *reg_intpnd;
72 void __iomem *reg_mask;
73 struct irq_domain *domain;
74 struct s3c_irq_intc *parent;
75 struct s3c_irq_data *irqs;
a21765a7
BD		 76};
77
658dc8fb
HS		 78/*
79 * Array holding pointers to the global controller structs
80 * [0] ... main_intc
81 * [1] ... sub_intc
82 * [2] ... main_intc2 on s3c2416
83 */
84static struct s3c_irq_intc *s3c_intc[3];
85
1f629b7a 86static void s3c_irq_mask(struct irq_data *data)
a21765a7 87{
f5a25524
HS		 88 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
89 struct s3c_irq_intc *intc = irq_data->intc;
1f629b7a 90 struct s3c_irq_intc *parent_intc = intc->parent;
1f629b7a 91 struct s3c_irq_data *parent_data;
a21765a7 92 unsigned long mask;
1f629b7a
HS		 93 unsigned int irqno;
94
95 mask = __raw_readl(intc->reg_mask);
f5a25524 96 mask |= (1UL << irq_data->offset);
1f629b7a
HS		 97 __raw_writel(mask, intc->reg_mask);
98
0fe3cb1e 99 if (parent_intc) {
1f629b7a 100 parent_data = &parent_intc->irqs[irq_data->parent_irq];
a21765a7 101
f0774d41
HS		 102 /* check to see if we need to mask the parent IRQ
103 * The parent_irq is always in main_intc, so the hwirq
104 * for find_mapping does not need an offset in any case.
105 */
1f629b7a
HS		 106 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
107 irqno = irq_find_mapping(parent_intc->domain,
108 irq_data->parent_irq);
109 s3c_irq_mask(irq_get_irq_data(irqno));
110 }
111 }
a21765a7
BD		 112}
113
1f629b7a 114static void s3c_irq_unmask(struct irq_data *data)
a21765a7 115{
f5a25524
HS		 116 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
117 struct s3c_irq_intc *intc = irq_data->intc;
1f629b7a 118 struct s3c_irq_intc *parent_intc = intc->parent;
a21765a7 119 unsigned long mask;
1f629b7a 120 unsigned int irqno;
a21765a7 121
1f629b7a 122 mask = __raw_readl(intc->reg_mask);
f5a25524 123 mask &= ~(1UL << irq_data->offset);
1f629b7a 124 __raw_writel(mask, intc->reg_mask);
a21765a7 125
0fe3cb1e 126 if (parent_intc) {
1f629b7a
HS		 127 irqno = irq_find_mapping(parent_intc->domain,
128 irq_data->parent_irq);
129 s3c_irq_unmask(irq_get_irq_data(irqno));
a21765a7
BD		 130 }
131}
132
1f629b7a 133static inline void s3c_irq_ack(struct irq_data *data)
a21765a7 134{
f5a25524
HS		 135 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
136 struct s3c_irq_intc *intc = irq_data->intc;
137 unsigned long bitval = 1UL << irq_data->offset;
a21765a7 138
1f629b7a
HS		 139 __raw_writel(bitval, intc->reg_pending);
140 if (intc->reg_intpnd)
141 __raw_writel(bitval, intc->reg_intpnd);
a21765a7
BD		 142}
143
bd7c0da2
HS		 144static int s3c_irq_type(struct irq_data *data, unsigned int type)
145{
146 switch (type) {
147 case IRQ_TYPE_NONE:
148 break;
149 case IRQ_TYPE_EDGE_RISING:
150 case IRQ_TYPE_EDGE_FALLING:
151 case IRQ_TYPE_EDGE_BOTH:
152 irq_set_handler(data->irq, handle_edge_irq);
153 break;
154 case IRQ_TYPE_LEVEL_LOW:
155 case IRQ_TYPE_LEVEL_HIGH:
156 irq_set_handler(data->irq, handle_level_irq);
157 break;
158 default:
159 pr_err("No such irq type %d", type);
160 return -EINVAL;
161 }
162
163 return 0;
164}
165
1f629b7a
HS		 166static int s3c_irqext_type_set(void __iomem *gpcon_reg,
167 void __iomem *extint_reg,
168 unsigned long gpcon_offset,
169 unsigned long extint_offset,
170 unsigned int type)
a21765a7 171{
a21765a7
BD		 172 unsigned long newvalue = 0, value;
173
a21765a7
BD		 174 /* Set the GPIO to external interrupt mode */
175 value = __raw_readl(gpcon_reg);
176 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
177 __raw_writel(value, gpcon_reg);
178
179 /* Set the external interrupt to pointed trigger type */
180 switch (type)
181 {
6cab4860 182 case IRQ_TYPE_NONE:
1f629b7a 183 pr_warn("No edge setting!\n");
a21765a7
BD		 184 break;
185
6cab4860 186 case IRQ_TYPE_EDGE_RISING:
a21765a7
BD		 187 newvalue = S3C2410_EXTINT_RISEEDGE;
188 break;
189
6cab4860 190 case IRQ_TYPE_EDGE_FALLING:
a21765a7
BD		 191 newvalue = S3C2410_EXTINT_FALLEDGE;
192 break;
193
6cab4860 194 case IRQ_TYPE_EDGE_BOTH:
a21765a7
BD		 195 newvalue = S3C2410_EXTINT_BOTHEDGE;
196 break;
197
6cab4860 198 case IRQ_TYPE_LEVEL_LOW:
a21765a7
BD		 199 newvalue = S3C2410_EXTINT_LOWLEV;
200 break;
201
6cab4860 202 case IRQ_TYPE_LEVEL_HIGH:
a21765a7
BD		 203 newvalue = S3C2410_EXTINT_HILEV;
204 break;
205
206 default:
1f629b7a
HS		 207 pr_err("No such irq type %d", type);
208 return -EINVAL;
a21765a7
BD		 209 }
210
211 value = __raw_readl(extint_reg);
212 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
213 __raw_writel(value, extint_reg);
214
215 return 0;
216}
217
dc1a3538 218static int s3c_irqext_type(struct irq_data *data, unsigned int type)
a21765a7 219{
1f629b7a
HS		 220 void __iomem *extint_reg;
221 void __iomem *gpcon_reg;
222 unsigned long gpcon_offset, extint_offset;
a21765a7 223
1f629b7a
HS		 224 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
225 gpcon_reg = S3C2410_GPFCON;
226 extint_reg = S3C24XX_EXTINT0;
227 gpcon_offset = (data->hwirq) * 2;
228 extint_offset = (data->hwirq) * 4;
229 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
230 gpcon_reg = S3C2410_GPGCON;
231 extint_reg = S3C24XX_EXTINT1;
232 gpcon_offset = (data->hwirq - 8) * 2;
233 extint_offset = (data->hwirq - 8) * 4;
234 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
235 gpcon_reg = S3C2410_GPGCON;
236 extint_reg = S3C24XX_EXTINT2;
237 gpcon_offset = (data->hwirq - 8) * 2;
238 extint_offset = (data->hwirq - 16) * 4;
239 } else {
240 return -EINVAL;
241 }
a21765a7 242
1f629b7a
HS		 243 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
244 extint_offset, type);
a21765a7
BD		 245}
246
1f629b7a 247static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
a21765a7 248{
1f629b7a
HS		 249 void __iomem *extint_reg;
250 void __iomem *gpcon_reg;
251 unsigned long gpcon_offset, extint_offset;
a21765a7 252
1f629b7a
HS		 253 if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
254 gpcon_reg = S3C2410_GPFCON;
255 extint_reg = S3C24XX_EXTINT0;
256 gpcon_offset = (data->hwirq) * 2;
257 extint_offset = (data->hwirq) * 4;
258 } else {
259 return -EINVAL;
260 }
a21765a7 261
1f629b7a
HS		 262 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
263 extint_offset, type);
a21765a7
BD		 264}
265
dc1a3538 266static struct irq_chip s3c_irq_chip = {
1f629b7a
HS		 267 .name = "s3c",
268 .irq_ack = s3c_irq_ack,
269 .irq_mask = s3c_irq_mask,
270 .irq_unmask = s3c_irq_unmask,
bd7c0da2 271 .irq_set_type = s3c_irq_type,
1f629b7a 272 .irq_set_wake = s3c_irq_wake
a21765a7
BD		 273};
274
dc1a3538 275static struct irq_chip s3c_irq_level_chip = {
1f629b7a
HS		 276 .name = "s3c-level",
277 .irq_mask = s3c_irq_mask,
278 .irq_unmask = s3c_irq_unmask,
279 .irq_ack = s3c_irq_ack,
bd7c0da2 280 .irq_set_type = s3c_irq_type,
a21765a7
BD		 281};
282
1f629b7a
HS		 283static struct irq_chip s3c_irqext_chip = {
284 .name = "s3c-ext",
285 .irq_mask = s3c_irq_mask,
286 .irq_unmask = s3c_irq_unmask,
287 .irq_ack = s3c_irq_ack,
288 .irq_set_type = s3c_irqext_type,
289 .irq_set_wake = s3c_irqext_wake
a21765a7
BD		 290};
291
1f629b7a
HS		 292static struct irq_chip s3c_irq_eint0t4 = {
293 .name = "s3c-ext0",
294 .irq_ack = s3c_irq_ack,
295 .irq_mask = s3c_irq_mask,
296 .irq_unmask = s3c_irq_unmask,
297 .irq_set_wake = s3c_irq_wake,
298 .irq_set_type = s3c_irqext0_type,
299};
a21765a7 300
4df18a66 301static void s3c_irq_demux(unsigned int __irq, struct irq_desc *desc)
a21765a7 302{
1f629b7a 303 struct irq_chip *chip = irq_desc_get_chip(desc);
f5a25524 304 struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
f0774d41 305 struct s3c_irq_intc *intc = irq_data->intc;
1f629b7a 306 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
4df18a66
TG		 307 unsigned int n, offset, irq;
308 unsigned long src, msk;
f0774d41
HS		 309
310 /* we're using individual domains for the non-dt case
311 * and one big domain for the dt case where the subintc
312 * starts at hwirq number 32.
313 */
314 offset = (intc->domain->of_node) ? 32 : 0;
1f629b7a
HS		 315
316 chained_irq_enter(chip, desc);
317
318 src = __raw_readl(sub_intc->reg_pending);
319 msk = __raw_readl(sub_intc->reg_mask);
320
321 src &= ~msk;
322 src &= irq_data->sub_bits;
323
324 while (src) {
325 n = __ffs(src);
326 src &= ~(1 << n);
f0774d41
HS		 327 irq = irq_find_mapping(sub_intc->domain, offset + n);
328 generic_handle_irq(irq);
a21765a7
BD		 329 }
330
1f629b7a 331 chained_irq_exit(chip, desc);
a21765a7
BD		 332}
333
17453dd2 334static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
f0774d41 335 struct pt_regs *regs, int intc_offset)
17453dd2
HS		 336{
337 int pnd;
338 int offset;
17453dd2
HS		 339
340 pnd = __raw_readl(intc->reg_intpnd);
341 if (!pnd)
342 return false;
343
f0774d41
HS		 344 /* non-dt machines use individual domains */
345 if (!intc->domain->of_node)
346 intc_offset = 0;
347
17453dd2
HS		 348 /* We have a problem that the INTOFFSET register does not always
349 * show one interrupt. Occasionally we get two interrupts through
350 * the prioritiser, and this causes the INTOFFSET register to show
351 * what looks like the logical-or of the two interrupt numbers.
352 *
353 * Thanks to Klaus, Shannon, et al for helping to debug this problem
354 */
355 offset = __raw_readl(intc->reg_intpnd + 4);
356
357 /* Find the bit manually, when the offset is wrong.
358 * The pending register only ever contains the one bit of the next
359 * interrupt to handle.
360 */
361 if (!(pnd & (1 << offset)))
362 offset = __ffs(pnd);
363
cf86bfdd 364 handle_domain_irq(intc->domain, intc_offset + offset, regs);
17453dd2
HS		 365 return true;
366}
367
368asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
369{
370 do {
658dc8fb 371 if (likely(s3c_intc[0]))
f0774d41 372 if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
17453dd2
HS		 373 continue;
374
658dc8fb 375 if (s3c_intc[2])
f0774d41 376 if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
17453dd2
HS		 377 continue;
378
379 break;
380 } while (1);
381}
382
229fd8ff
BD		 383#ifdef CONFIG_FIQ
384/**
385 * s3c24xx_set_fiq - set the FIQ routing
386 * @irq: IRQ number to route to FIQ on processor.
387 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
388 *
389 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
390 * @on is true, the @irq is checked to see if it can be routed and the
391 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
392 * routing is cleared, regardless of which @irq is specified.
393 */
394int s3c24xx_set_fiq(unsigned int irq, bool on)
395{
396 u32 intmod;
397 unsigned offs;
398
399 if (on) {
400 offs = irq - FIQ_START;
401 if (offs > 31)
402 return -EINVAL;
403
404 intmod = 1 << offs;
405 } else {
406 intmod = 0;
407 }
408
409 __raw_writel(intmod, S3C2410_INTMOD);
410 return 0;
411}
0f13c824
BD		 412
413EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
229fd8ff
BD		 414#endif
415
1f629b7a
HS		 416static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
417 irq_hw_number_t hw)
a21765a7 418{
1f629b7a
HS		 419 struct s3c_irq_intc *intc = h->host_data;
420 struct s3c_irq_data *irq_data = &intc->irqs[hw];
421 struct s3c_irq_intc *parent_intc;
422 struct s3c_irq_data *parent_irq_data;
423 unsigned int irqno;
424
1f629b7a
HS		 425 /* attach controller pointer to irq_data */
426 irq_data->intc = intc;
f5a25524 427 irq_data->offset = hw;
a21765a7 428
0fe3cb1e 429 parent_intc = intc->parent;
a21765a7 430
1f629b7a
HS		 431 /* set handler and flags */
432 switch (irq_data->type) {
433 case S3C_IRQTYPE_NONE:
434 return 0;
435 case S3C_IRQTYPE_EINT:
1c8408e3
HS		 436 /* On the S3C2412, the EINT0to3 have a parent irq
437 * but need the s3c_irq_eint0t4 chip
438 */
0fe3cb1e 439 if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
1f629b7a
HS		 440 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
441 handle_edge_irq);
442 else
443 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
444 handle_edge_irq);
445 break;
446 case S3C_IRQTYPE_EDGE:
0fe3cb1e 447 if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
1f629b7a
HS		 448 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
449 handle_edge_irq);
450 else
451 irq_set_chip_and_handler(virq, &s3c_irq_chip,
452 handle_edge_irq);
453 break;
454 case S3C_IRQTYPE_LEVEL:
0fe3cb1e 455 if (parent_intc)
1f629b7a
HS		 456 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
457 handle_level_irq);
458 else
459 irq_set_chip_and_handler(virq, &s3c_irq_chip,
460 handle_level_irq);
461 break;
462 default:
463 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
464 return -EINVAL;
a21765a7 465 }
f5a25524
HS		 466
467 irq_set_chip_data(virq, irq_data);
468
1f629b7a
HS		 469 set_irq_flags(virq, IRQF_VALID);
470
0fe3cb1e 471 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
502a2989
HS		 472 if (irq_data->parent_irq > 31) {
473 pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
474 irq_data->parent_irq);
1f629b7a
HS		 475 goto err;
476 }
a21765a7 477
1f629b7a 478 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
1f629b7a
HS		 479 parent_irq_data->sub_intc = intc;
480 parent_irq_data->sub_bits |= (1UL << hw);
a21765a7 481
1f629b7a
HS		 482 /* attach the demuxer to the parent irq */
483 irqno = irq_find_mapping(parent_intc->domain,
484 irq_data->parent_irq);
485 if (!irqno) {
486 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
487 irq_data->parent_irq);
488 goto err;
489 }
490 irq_set_chained_handler(irqno, s3c_irq_demux);
a21765a7
BD		 491 }
492
1f629b7a 493 return 0;
a21765a7 494
1f629b7a
HS		 495err:
496 set_irq_flags(virq, 0);
a21765a7 497
1f629b7a
HS		 498 /* the only error can result from bad mapping data*/
499 return -EINVAL;
500}
a21765a7 501
96009736 502static const struct irq_domain_ops s3c24xx_irq_ops = {
1f629b7a
HS		 503 .map = s3c24xx_irq_map,
504 .xlate = irq_domain_xlate_twocell,
505};
a21765a7 506
1f629b7a
HS		 507static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
508{
509 void __iomem *reg_source;
510 unsigned long pend;
511 unsigned long last;
512 int i;
a21765a7 513
1f629b7a
HS		 514 /* if intpnd is set, read the next pending irq from there */
515 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
a21765a7 516
1f629b7a
HS		 517 last = 0;
518 for (i = 0; i < 4; i++) {
519 pend = __raw_readl(reg_source);
a21765a7 520
1f629b7a 521 if (pend == 0 || pend == last)
a21765a7
BD		 522 break;
523
1f629b7a
HS		 524 __raw_writel(pend, intc->reg_pending);
525 if (intc->reg_intpnd)
526 __raw_writel(pend, intc->reg_intpnd);
a21765a7 527
1f629b7a
HS		 528 pr_info("irq: clearing pending status %08x\n", (int)pend);
529 last = pend;
a21765a7 530 }
1f629b7a 531}
a21765a7 532
bc8fd900 533static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np,
1f629b7a
HS		 534 struct s3c_irq_data *irq_data,
535 struct s3c_irq_intc *parent,
536 unsigned long address)
537{
538 struct s3c_irq_intc *intc;
539 void __iomem *base = (void *)0xf6000000; /* static mapping */
540 int irq_num;
541 int irq_start;
1f629b7a
HS		 542 int ret;
543
544 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
545 if (!intc)
546 return ERR_PTR(-ENOMEM);
547
548 intc->irqs = irq_data;
549
550 if (parent)
551 intc->parent = parent;
552
553 /* select the correct data for the controller.
554 * Need to hard code the irq num start and offset
555 * to preserve the static mapping for now
556 */
557 switch (address) {
558 case 0x4a000000:
559 pr_debug("irq: found main intc\n");
560 intc->reg_pending = base;
561 intc->reg_mask = base + 0x08;
562 intc->reg_intpnd = base + 0x10;
563 irq_num = 32;
564 irq_start = S3C2410_IRQ(0);
1f629b7a
HS		 565 break;
566 case 0x4a000018:
567 pr_debug("irq: found subintc\n");
568 intc->reg_pending = base + 0x18;
569 intc->reg_mask = base + 0x1c;
570 irq_num = 29;
571 irq_start = S3C2410_IRQSUB(0);
1f629b7a
HS		 572 break;
573 case 0x4a000040:
574 pr_debug("irq: found intc2\n");
575 intc->reg_pending = base + 0x40;
576 intc->reg_mask = base + 0x48;
577 intc->reg_intpnd = base + 0x50;
578 irq_num = 8;
579 irq_start = S3C2416_IRQ(0);
1f629b7a
HS		 580 break;
581 case 0x560000a4:
582 pr_debug("irq: found eintc\n");
583 base = (void *)0xfd000000;
584
585 intc->reg_mask = base + 0xa4;
646dd2f0 586 intc->reg_pending = base + 0xa8;
5424f218 587 irq_num = 24;
1f629b7a 588 irq_start = S3C2410_IRQ(32);
1f629b7a
HS		 589 break;
590 default:
591 pr_err("irq: unsupported controller address\n");
592 ret = -EINVAL;
593 goto err;
594 }
a21765a7 595
1f629b7a
HS		 596 /* now that all the data is complete, init the irq-domain */
597 s3c24xx_clear_intc(intc);
598 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
5424f218 599 0, &s3c24xx_irq_ops,
1f629b7a
HS		 600 intc);
601 if (!intc->domain) {
602 pr_err("irq: could not create irq-domain\n");
603 ret = -EINVAL;
604 goto err;
605 }
a21765a7 606
17453dd2
HS		 607 set_handle_irq(s3c24xx_handle_irq);
608
1f629b7a 609 return intc;
a21765a7 610
1f629b7a
HS		 611err:
612 kfree(intc);
613 return ERR_PTR(ret);
614}
a21765a7 615
f182aa1d
HS		 616static struct s3c_irq_data init_eint[32] = {
617 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
618 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
619 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
620 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
621 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
622 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
623 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
624 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
625 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
626 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
627 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
628 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
629 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
630 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
631 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
632 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
633 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
634 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
635 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
636 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
637 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
638 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
639 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
640 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
641};
a21765a7 642
f182aa1d
HS		 643#ifdef CONFIG_CPU_S3C2410
644static struct s3c_irq_data init_s3c2410base[32] = {
1f629b7a
HS		 645 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
646 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
647 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
648 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
649 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
650 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
651 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
652 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
653 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
654 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
655 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
656 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
657 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
658 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
659 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
660 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
661 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
662 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
663 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
664 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
665 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
666 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
667 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
668 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
669 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
670 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
671 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
672 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
673 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
674 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
675 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
676 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
677};
a21765a7 678
f182aa1d 679static struct s3c_irq_data init_s3c2410subint[32] = {
1f629b7a
HS		 680 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
681 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
682 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
683 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
684 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
685 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
686 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
687 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
688 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
689 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
690 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
691};
a21765a7 692
f182aa1d 693void __init s3c2410_init_irq(void)
1f629b7a 694{
1f629b7a
HS		 695#ifdef CONFIG_FIQ
696 init_FIQ(FIQ_START);
697#endif
a21765a7 698
658dc8fb
HS		 699 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
700 0x4a000000);
701 if (IS_ERR(s3c_intc[0])) {
1f629b7a
HS		 702 pr_err("irq: could not create main interrupt controller\n");
703 return;
a21765a7
BD		 704 }
705
658dc8fb
HS		 706 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
707 s3c_intc[0], 0x4a000018);
708 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
a21765a7 709}
f182aa1d 710#endif
ef602eb5 711
d3d5a2c9 712#ifdef CONFIG_CPU_S3C2412
4245944c 713static struct s3c_irq_data init_s3c2412base[32] = {
1c8408e3
HS		 714 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
715 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
716 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
717 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
4245944c
HS		 718 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
719 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1f629b7a 720 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
4245944c
HS		 721 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
722 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
723 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
724 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
725 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
726 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
727 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
728 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
729 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
730 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
731 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
732 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
733 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
734 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
735 { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
736 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
737 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1f629b7a 738 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
4245944c
HS		 739 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
740 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
741 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
742 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
743 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
744 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
745 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
746};
d3d5a2c9 747
1c8408e3
HS		 748static struct s3c_irq_data init_s3c2412eint[32] = {
749 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
750 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
751 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
752 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
1f629b7a
HS		 753 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
754 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
755 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
756 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
757 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
758 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
759 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
760 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
761 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
762 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
763 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
764 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
765 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
766 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
767 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
768 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
769 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
770 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
771 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
772 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
773};
a21765a7 774
4245944c 775static struct s3c_irq_data init_s3c2412subint[32] = {
1f629b7a
HS		 776 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
777 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
778 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
779 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
780 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
781 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
782 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
783 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
784 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
785 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
786 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
4245944c
HS		 787 { .type = S3C_IRQTYPE_NONE, },
788 { .type = S3C_IRQTYPE_NONE, },
789 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
790 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
1f629b7a 791};
a21765a7 792
bc8fd900 793void __init s3c2412_init_irq(void)
1f629b7a 794{
4245944c 795 pr_info("S3C2412: IRQ Support\n");
a21765a7 796
1f629b7a
HS		 797#ifdef CONFIG_FIQ
798 init_FIQ(FIQ_START);
799#endif
a21765a7 800
658dc8fb
HS		 801 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
802 0x4a000000);
803 if (IS_ERR(s3c_intc[0])) {
1f629b7a
HS		 804 pr_err("irq: could not create main interrupt controller\n");
805 return;
a21765a7
BD		 806 }
807
658dc8fb
HS		 808 s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
809 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
810 s3c_intc[0], 0x4a000018);
a21765a7 811}
d3d5a2c9 812#endif
ef602eb5
HS		 813
814#ifdef CONFIG_CPU_S3C2416
20f6c781
HS		 815static struct s3c_irq_data init_s3c2416base[32] = {
816 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
817 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
818 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
819 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
820 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
821 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
822 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
823 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
824 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
825 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
826 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
827 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
828 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
829 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
830 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
831 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
832 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
833 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
834 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
835 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
836 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
837 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
838 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
839 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
840 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
841 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
842 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
843 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
844 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
845 { .type = S3C_IRQTYPE_NONE, },
846 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
847 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
ef602eb5
HS		 848};
849
20f6c781
HS		 850static struct s3c_irq_data init_s3c2416subint[32] = {
851 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
852 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
853 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
854 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
855 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
856 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
857 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
858 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
859 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
860 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
861 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
862 { .type = S3C_IRQTYPE_NONE }, /* reserved */
863 { .type = S3C_IRQTYPE_NONE }, /* reserved */
864 { .type = S3C_IRQTYPE_NONE }, /* reserved */
865 { .type = S3C_IRQTYPE_NONE }, /* reserved */
866 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
867 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
868 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
869 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
870 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
871 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
872 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
873 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
874 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
875 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
876 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
877 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
878 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
879 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
ef602eb5
HS		 880};
881
20f6c781
HS		 882static struct s3c_irq_data init_s3c2416_second[32] = {
883 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
1ebc7e83 884 { .type = S3C_IRQTYPE_NONE }, /* reserved */
20f6c781
HS		 885 { .type = S3C_IRQTYPE_NONE }, /* reserved */
886 { .type = S3C_IRQTYPE_NONE }, /* reserved */
887 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
1ebc7e83 888 { .type = S3C_IRQTYPE_NONE }, /* reserved */
20f6c781 889 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
ef602eb5
HS		 890};
891
4a282dd3 892void __init s3c2416_init_irq(void)
ef602eb5 893{
20f6c781 894 pr_info("S3C2416: IRQ Support\n");
ef602eb5 895
20f6c781
HS		 896#ifdef CONFIG_FIQ
897 init_FIQ(FIQ_START);
898#endif
ef602eb5 899
658dc8fb
HS		 900 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
901 0x4a000000);
902 if (IS_ERR(s3c_intc[0])) {
20f6c781
HS		 903 pr_err("irq: could not create main interrupt controller\n");
904 return;
905 }
ef602eb5 906
658dc8fb
HS		 907 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
908 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
909 s3c_intc[0], 0x4a000018);
ef602eb5 910
658dc8fb
HS		 911 s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
912 NULL, 0x4a000040);
ef602eb5
HS		 913}
914
ef602eb5 915#endif
6b628917 916
ce6c164b 917#ifdef CONFIG_CPU_S3C2440
f0301673
HS		 918static struct s3c_irq_data init_s3c2440base[32] = {
919 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
920 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
921 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
922 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
923 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
924 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
925 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
926 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
927 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
928 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
929 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
930 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
931 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
932 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
933 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
934 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
935 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
936 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
937 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
938 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
939 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
940 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
941 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
942 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
943 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
944 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
945 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
946 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
947 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
948 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
949 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
950 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
951};
2286cf46 952
f0301673
HS		 953static struct s3c_irq_data init_s3c2440subint[32] = {
954 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
955 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
956 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
957 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
958 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
959 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
960 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
961 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
962 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
963 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
964 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
e2714f79
HS		 965 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
966 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
f0301673
HS		 967 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
968 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
2286cf46
HS		 969};
970
7cefed5e 971void __init s3c2440_init_irq(void)
2286cf46 972{
f0301673 973 pr_info("S3C2440: IRQ Support\n");
ef602eb5 974
f0301673
HS		 975#ifdef CONFIG_FIQ
976 init_FIQ(FIQ_START);
977#endif
6f8d7ea2 978
658dc8fb
HS		 979 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
980 0x4a000000);
981 if (IS_ERR(s3c_intc[0])) {
f0301673
HS		 982 pr_err("irq: could not create main interrupt controller\n");
983 return;
6f8d7ea2 984 }
7cefed5e 985
658dc8fb
HS		 986 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
987 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
988 s3c_intc[0], 0x4a000018);
ef602eb5 989}
ce6c164b 990#endif
ef602eb5 991
ce6c164b 992#ifdef CONFIG_CPU_S3C2442
70644ade
HS		 993static struct s3c_irq_data init_s3c2442base[32] = {
994 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
995 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
996 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
997 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
998 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
999 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1000 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1001 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1002 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1003 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
1004 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1005 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1006 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1007 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1008 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1009 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1010 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
1011 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
1012 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
1013 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
1014 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
1015 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
1016 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1017 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1018 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
1019 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1020 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1021 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1022 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1023 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1024 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1025 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1026};
6f8d7ea2 1027
70644ade
HS		 1028static struct s3c_irq_data init_s3c2442subint[32] = {
1029 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1030 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1031 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1032 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1033 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1034 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1035 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1036 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1037 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1038 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1039 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
e2714f79
HS		 1040 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1041 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
70644ade 1042};
6f8d7ea2 1043
70644ade
HS		 1044void __init s3c2442_init_irq(void)
1045{
70644ade 1046 pr_info("S3C2442: IRQ Support\n");
6f8d7ea2 1047
70644ade
HS		 1048#ifdef CONFIG_FIQ
1049 init_FIQ(FIQ_START);
1050#endif
ce6c164b 1051
658dc8fb
HS		 1052 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
1053 0x4a000000);
1054 if (IS_ERR(s3c_intc[0])) {
70644ade
HS		 1055 pr_err("irq: could not create main interrupt controller\n");
1056 return;
ce6c164b 1057 }
70644ade 1058
658dc8fb
HS		 1059 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1060 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
1061 s3c_intc[0], 0x4a000018);
6f8d7ea2 1062}
ef602eb5 1063#endif
6b628917
HS		 1064
1065#ifdef CONFIG_CPU_S3C2443
f44ddba3
HS		 1066static struct s3c_irq_data init_s3c2443base[32] = {
1067 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1068 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1069 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1070 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1071 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1072 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1073 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1074 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1075 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1076 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
1077 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1078 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1079 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1080 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1081 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1082 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1083 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
1084 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
1085 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
1086 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
1087 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
1088 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
1089 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1090 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1091 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
1092 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1093 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1094 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1095 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1096 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1097 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1098 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
6b628917
HS		 1099};
1100
6b628917 1101
f44ddba3
HS		 1102static struct s3c_irq_data init_s3c2443subint[32] = {
1103 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1104 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1105 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1106 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1107 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1108 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1109 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1110 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1111 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1112 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1113 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1114 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1115 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1116 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1117 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1118 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1119 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1120 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1121 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1122 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1123 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1124 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1125 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1126 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1127 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1128 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1129 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1130 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1131 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
6b628917
HS		 1132};
1133
b499b7a8 1134void __init s3c2443_init_irq(void)
6b628917 1135{
f44ddba3 1136 pr_info("S3C2443: IRQ Support\n");
6b628917 1137
f44ddba3
HS		 1138#ifdef CONFIG_FIQ
1139 init_FIQ(FIQ_START);
1140#endif
6b628917 1141
658dc8fb
HS		 1142 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
1143 0x4a000000);
1144 if (IS_ERR(s3c_intc[0])) {
f44ddba3
HS		 1145 pr_err("irq: could not create main interrupt controller\n");
1146 return;
1147 }
6b628917 1148
658dc8fb
HS		 1149 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1150 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
1151 s3c_intc[0], 0x4a000018);
6b628917 1152}
6b628917 1153#endif
f0774d41
HS		 1154
1155#ifdef CONFIG_OF
1156static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
1157 irq_hw_number_t hw)
1158{
1159 unsigned int ctrl_num = hw / 32;
1160 unsigned int intc_hw = hw % 32;
1161 struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
1162 struct s3c_irq_intc *parent_intc = intc->parent;
1163 struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];
1164
1165 /* attach controller pointer to irq_data */
1166 irq_data->intc = intc;
1167 irq_data->offset = intc_hw;
1168
1169 if (!parent_intc)
1170 irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
1171 else
1172 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
1173 handle_edge_irq);
1174
1175 irq_set_chip_data(virq, irq_data);
1176
1177 set_irq_flags(virq, IRQF_VALID);
1178
1179 return 0;
1180}
1181
1182/* Translate our of irq notation
1183 * format: <ctrl_num ctrl_irq parent_irq type>
1184 */
1185static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
1186 const u32 *intspec, unsigned int intsize,
1187 irq_hw_number_t *out_hwirq, unsigned int *out_type)
1188{
1189 struct s3c_irq_intc *intc;
1190 struct s3c_irq_intc *parent_intc;
1191 struct s3c_irq_data *irq_data;
1192 struct s3c_irq_data *parent_irq_data;
1193 int irqno;
1194
1195 if (WARN_ON(intsize < 4))
1196 return -EINVAL;
1197
1198 if (intspec[0] > 2 || !s3c_intc[intspec[0]]) {
1199 pr_err("controller number %d invalid\n", intspec[0]);
1200 return -EINVAL;
1201 }
1202 intc = s3c_intc[intspec[0]];
1203
1204 *out_hwirq = intspec[0] * 32 + intspec[2];
1205 *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
1206
1207 parent_intc = intc->parent;
1208 if (parent_intc) {
1209 irq_data = &intc->irqs[intspec[2]];
1210 irq_data->parent_irq = intspec[1];
1211 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
1212 parent_irq_data->sub_intc = intc;
1213 parent_irq_data->sub_bits |= (1UL << intspec[2]);
1214
1215 /* parent_intc is always s3c_intc[0], so no offset */
1216 irqno = irq_create_mapping(parent_intc->domain, intspec[1]);
1217 if (irqno < 0) {
1218 pr_err("irq: could not map parent interrupt\n");
1219 return irqno;
1220 }
1221
1222 irq_set_chained_handler(irqno, s3c_irq_demux);
1223 }
1224
1225 return 0;
1226}
1227
96009736 1228static const struct irq_domain_ops s3c24xx_irq_ops_of = {
f0774d41
HS		 1229 .map = s3c24xx_irq_map_of,
1230 .xlate = s3c24xx_irq_xlate_of,
1231};
1232
1233struct s3c24xx_irq_of_ctrl {
1234 char *name;
1235 unsigned long offset;
1236 struct s3c_irq_intc **handle;
1237 struct s3c_irq_intc **parent;
1238 struct irq_domain_ops *ops;
1239};
1240
1241static int __init s3c_init_intc_of(struct device_node *np,
1242 struct device_node *interrupt_parent,
1243 struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl)
1244{
1245 struct s3c_irq_intc *intc;
1246 struct s3c24xx_irq_of_ctrl *ctrl;
1247 struct irq_domain *domain;
1248 void __iomem *reg_base;
1249 int i;
1250
1251 reg_base = of_iomap(np, 0);
1252 if (!reg_base) {
1253 pr_err("irq-s3c24xx: could not map irq registers\n");
1254 return -EINVAL;
1255 }
1256
1257 domain = irq_domain_add_linear(np, num_ctrl * 32,
1258 &s3c24xx_irq_ops_of, NULL);
1259 if (!domain) {
1260 pr_err("irq: could not create irq-domain\n");
1261 return -EINVAL;
1262 }
1263
1264 for (i = 0; i < num_ctrl; i++) {
1265 ctrl = &s3c_ctrl[i];
1266
1267 pr_debug("irq: found controller %s\n", ctrl->name);
1268
1269 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
1270 if (!intc)
1271 return -ENOMEM;
1272
1273 intc->domain = domain;
1274 intc->irqs = kzalloc(sizeof(struct s3c_irq_data) * 32,
1275 GFP_KERNEL);
1276 if (!intc->irqs) {
1277 kfree(intc);
1278 return -ENOMEM;
1279 }
1280
1281 if (ctrl->parent) {
1282 intc->reg_pending = reg_base + ctrl->offset;
1283 intc->reg_mask = reg_base + ctrl->offset + 0x4;
1284
1285 if (*(ctrl->parent)) {
1286 intc->parent = *(ctrl->parent);
1287 } else {
1288 pr_warn("irq: parent of %s missing\n",
1289 ctrl->name);
1290 kfree(intc->irqs);
1291 kfree(intc);
1292 continue;
1293 }
1294 } else {
1295 intc->reg_pending = reg_base + ctrl->offset;
1296 intc->reg_mask = reg_base + ctrl->offset + 0x08;
1297 intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
1298 }
1299
1300 s3c24xx_clear_intc(intc);
1301 s3c_intc[i] = intc;
1302 }
1303
1304 set_handle_irq(s3c24xx_handle_irq);
1305
1306 return 0;
1307}
1308
1309static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
1310 {
1311 .name = "intc",
1312 .offset = 0,
1313 }, {
1314 .name = "subintc",
1315 .offset = 0x18,
1316 .parent = &s3c_intc[0],
1317 }
1318};
1319
1320int __init s3c2410_init_intc_of(struct device_node *np,
4f41083b 1321 struct device_node *interrupt_parent)
f0774d41
HS		 1322{
1323 return s3c_init_intc_of(np, interrupt_parent,
1324 s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl));
1325}
1326IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
1327
1328static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
1329 {
1330 .name = "intc",
1331 .offset = 0,
1332 }, {
1333 .name = "subintc",
1334 .offset = 0x18,
1335 .parent = &s3c_intc[0],
1336 }, {
1337 .name = "intc2",
1338 .offset = 0x40,
1339 }
1340};
1341
1342int __init s3c2416_init_intc_of(struct device_node *np,
4f41083b 1343 struct device_node *interrupt_parent)
f0774d41
HS		 1344{
1345 return s3c_init_intc_of(np, interrupt_parent,
1346 s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl));
6b628917 1347}
f0774d41 1348IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);
6b628917 1349#endif
Linux 6.x block layer and io_uring tree(s)