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Merge branch 'acpica'
[linux-2.6-block.git] / drivers / irqchip / irq-s3c24xx.c
CommitLineData
1f629b7a
HS		 1/*
2 * S3C24XX IRQ handling
a21765a7 3 *
e02f8664 4 * Copyright (c) 2003-2004 Simtec Electronics
a21765a7 5 * Ben Dooks <ben@simtec.co.uk>
1f629b7a 6 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
a21765a7
BD		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
a21765a7
BD		 17*/
18
19#include <linux/init.h>
1f629b7a 20#include <linux/slab.h>
a21765a7 21#include <linux/module.h>
1f629b7a
HS		 22#include <linux/io.h>
23#include <linux/err.h>
a21765a7
BD		 24#include <linux/interrupt.h>
25#include <linux/ioport.h>
edbaa603 26#include <linux/device.h>
1f629b7a 27#include <linux/irqdomain.h>
41a83e06 28#include <linux/irqchip.h>
de88cbb7 29#include <linux/irqchip/chained_irq.h>
f0774d41
HS		 30#include <linux/of.h>
31#include <linux/of_irq.h>
32#include <linux/of_address.h>
a21765a7 33
17453dd2 34#include <asm/exception.h>
a21765a7
BD		 35#include <asm/mach/irq.h>
36
1f629b7a
HS		 37#include <mach/regs-irq.h>
38#include <mach/regs-gpio.h>
a21765a7 39
a2b7ba9c 40#include <plat/cpu.h>
1f629b7a 41#include <plat/regs-irqtype.h>
a2b7ba9c 42#include <plat/pm.h>
a21765a7 43
1f629b7a
HS		 44#define S3C_IRQTYPE_NONE 0
45#define S3C_IRQTYPE_EINT 1
46#define S3C_IRQTYPE_EDGE 2
47#define S3C_IRQTYPE_LEVEL 3
a21765a7 48
1f629b7a
HS		 49struct s3c_irq_data {
50 unsigned int type;
f5a25524 51 unsigned long offset;
1f629b7a 52 unsigned long parent_irq;
a21765a7 53
1f629b7a
HS		 54 /* data gets filled during init */
55 struct s3c_irq_intc *intc;
56 unsigned long sub_bits;
57 struct s3c_irq_intc *sub_intc;
a21765a7
BD		 58};
59
1f629b7a
HS		 60/*
61 * Sructure holding the controller data
62 * @reg_pending register holding pending irqs
63 * @reg_intpnd special register intpnd in main intc
64 * @reg_mask mask register
65 * @domain irq_domain of the controller
66 * @parent parent controller for ext and sub irqs
67 * @irqs irq-data, always s3c_irq_data[32]
68 */
69struct s3c_irq_intc {
70 void __iomem *reg_pending;
71 void __iomem *reg_intpnd;
72 void __iomem *reg_mask;
73 struct irq_domain *domain;
74 struct s3c_irq_intc *parent;
75 struct s3c_irq_data *irqs;
a21765a7
BD		 76};
77
658dc8fb
HS		 78/*
79 * Array holding pointers to the global controller structs
80 * [0] ... main_intc
81 * [1] ... sub_intc
82 * [2] ... main_intc2 on s3c2416
83 */
84static struct s3c_irq_intc *s3c_intc[3];
85
1f629b7a 86static void s3c_irq_mask(struct irq_data *data)
a21765a7 87{
f5a25524
HS		 88 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
89 struct s3c_irq_intc *intc = irq_data->intc;
1f629b7a 90 struct s3c_irq_intc *parent_intc = intc->parent;
1f629b7a 91 struct s3c_irq_data *parent_data;
a21765a7 92 unsigned long mask;
1f629b7a
HS		 93 unsigned int irqno;
94
95 mask = __raw_readl(intc->reg_mask);
f5a25524 96 mask |= (1UL << irq_data->offset);
1f629b7a
HS		 97 __raw_writel(mask, intc->reg_mask);
98
0fe3cb1e 99 if (parent_intc) {
1f629b7a 100 parent_data = &parent_intc->irqs[irq_data->parent_irq];
a21765a7 101
f0774d41
HS		 102 /* check to see if we need to mask the parent IRQ
103 * The parent_irq is always in main_intc, so the hwirq
104 * for find_mapping does not need an offset in any case.
105 */
1f629b7a
HS		 106 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
107 irqno = irq_find_mapping(parent_intc->domain,
108 irq_data->parent_irq);
109 s3c_irq_mask(irq_get_irq_data(irqno));
110 }
111 }
a21765a7
BD		 112}
113
1f629b7a 114static void s3c_irq_unmask(struct irq_data *data)
a21765a7 115{
f5a25524
HS		 116 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
117 struct s3c_irq_intc *intc = irq_data->intc;
1f629b7a 118 struct s3c_irq_intc *parent_intc = intc->parent;
a21765a7 119 unsigned long mask;
1f629b7a 120 unsigned int irqno;
a21765a7 121
1f629b7a 122 mask = __raw_readl(intc->reg_mask);
f5a25524 123 mask &= ~(1UL << irq_data->offset);
1f629b7a 124 __raw_writel(mask, intc->reg_mask);
a21765a7 125
0fe3cb1e 126 if (parent_intc) {
1f629b7a
HS		 127 irqno = irq_find_mapping(parent_intc->domain,
128 irq_data->parent_irq);
129 s3c_irq_unmask(irq_get_irq_data(irqno));
a21765a7
BD		 130 }
131}
132
1f629b7a 133static inline void s3c_irq_ack(struct irq_data *data)
a21765a7 134{
f5a25524
HS		 135 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
136 struct s3c_irq_intc *intc = irq_data->intc;
137 unsigned long bitval = 1UL << irq_data->offset;
a21765a7 138
1f629b7a
HS		 139 __raw_writel(bitval, intc->reg_pending);
140 if (intc->reg_intpnd)
141 __raw_writel(bitval, intc->reg_intpnd);
a21765a7
BD		 142}
143
bd7c0da2
HS		 144static int s3c_irq_type(struct irq_data *data, unsigned int type)
145{
146 switch (type) {
147 case IRQ_TYPE_NONE:
148 break;
149 case IRQ_TYPE_EDGE_RISING:
150 case IRQ_TYPE_EDGE_FALLING:
151 case IRQ_TYPE_EDGE_BOTH:
152 irq_set_handler(data->irq, handle_edge_irq);
153 break;
154 case IRQ_TYPE_LEVEL_LOW:
155 case IRQ_TYPE_LEVEL_HIGH:
156 irq_set_handler(data->irq, handle_level_irq);
157 break;
158 default:
159 pr_err("No such irq type %d", type);
160 return -EINVAL;
161 }
162
163 return 0;
164}
165
1f629b7a
HS		 166static int s3c_irqext_type_set(void __iomem *gpcon_reg,
167 void __iomem *extint_reg,
168 unsigned long gpcon_offset,
169 unsigned long extint_offset,
170 unsigned int type)
a21765a7 171{
a21765a7
BD		 172 unsigned long newvalue = 0, value;
173
a21765a7
BD		 174 /* Set the GPIO to external interrupt mode */
175 value = __raw_readl(gpcon_reg);
176 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
177 __raw_writel(value, gpcon_reg);
178
179 /* Set the external interrupt to pointed trigger type */
180 switch (type)
181 {
6cab4860 182 case IRQ_TYPE_NONE:
1f629b7a 183 pr_warn("No edge setting!\n");
a21765a7
BD		 184 break;
185
6cab4860 186 case IRQ_TYPE_EDGE_RISING:
a21765a7
BD		 187 newvalue = S3C2410_EXTINT_RISEEDGE;
188 break;
189
6cab4860 190 case IRQ_TYPE_EDGE_FALLING:
a21765a7
BD		 191 newvalue = S3C2410_EXTINT_FALLEDGE;
192 break;
193
6cab4860 194 case IRQ_TYPE_EDGE_BOTH:
a21765a7
BD		 195 newvalue = S3C2410_EXTINT_BOTHEDGE;
196 break;
197
6cab4860 198 case IRQ_TYPE_LEVEL_LOW:
a21765a7
BD		 199 newvalue = S3C2410_EXTINT_LOWLEV;
200 break;
201
6cab4860 202 case IRQ_TYPE_LEVEL_HIGH:
a21765a7
BD		 203 newvalue = S3C2410_EXTINT_HILEV;
204 break;
205
206 default:
1f629b7a
HS		 207 pr_err("No such irq type %d", type);
208 return -EINVAL;
a21765a7
BD		 209 }
210
211 value = __raw_readl(extint_reg);
212 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
213 __raw_writel(value, extint_reg);
214
215 return 0;
216}
217
dc1a3538 218static int s3c_irqext_type(struct irq_data *data, unsigned int type)
a21765a7 219{
1f629b7a
HS		 220 void __iomem *extint_reg;
221 void __iomem *gpcon_reg;
222 unsigned long gpcon_offset, extint_offset;
a21765a7 223
1f629b7a
HS		 224 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
225 gpcon_reg = S3C2410_GPFCON;
226 extint_reg = S3C24XX_EXTINT0;
227 gpcon_offset = (data->hwirq) * 2;
228 extint_offset = (data->hwirq) * 4;
229 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
230 gpcon_reg = S3C2410_GPGCON;
231 extint_reg = S3C24XX_EXTINT1;
232 gpcon_offset = (data->hwirq - 8) * 2;
233 extint_offset = (data->hwirq - 8) * 4;
234 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
235 gpcon_reg = S3C2410_GPGCON;
236 extint_reg = S3C24XX_EXTINT2;
237 gpcon_offset = (data->hwirq - 8) * 2;
238 extint_offset = (data->hwirq - 16) * 4;
239 } else {
240 return -EINVAL;
241 }
a21765a7 242
1f629b7a
HS		 243 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
244 extint_offset, type);
a21765a7
BD		 245}
246
1f629b7a 247static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
a21765a7 248{
1f629b7a
HS		 249 void __iomem *extint_reg;
250 void __iomem *gpcon_reg;
251 unsigned long gpcon_offset, extint_offset;
a21765a7 252
1f629b7a
HS		 253 if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
254 gpcon_reg = S3C2410_GPFCON;
255 extint_reg = S3C24XX_EXTINT0;
256 gpcon_offset = (data->hwirq) * 2;
257 extint_offset = (data->hwirq) * 4;
258 } else {
259 return -EINVAL;
260 }
a21765a7 261
1f629b7a
HS		 262 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
263 extint_offset, type);
a21765a7
BD		 264}
265
dc1a3538 266static struct irq_chip s3c_irq_chip = {
1f629b7a
HS		 267 .name = "s3c",
268 .irq_ack = s3c_irq_ack,
269 .irq_mask = s3c_irq_mask,
270 .irq_unmask = s3c_irq_unmask,
bd7c0da2 271 .irq_set_type = s3c_irq_type,
1f629b7a 272 .irq_set_wake = s3c_irq_wake
a21765a7
BD		 273};
274
dc1a3538 275static struct irq_chip s3c_irq_level_chip = {
1f629b7a
HS		 276 .name = "s3c-level",
277 .irq_mask = s3c_irq_mask,
278 .irq_unmask = s3c_irq_unmask,
279 .irq_ack = s3c_irq_ack,
bd7c0da2 280 .irq_set_type = s3c_irq_type,
a21765a7
BD		 281};
282
1f629b7a
HS		 283static struct irq_chip s3c_irqext_chip = {
284 .name = "s3c-ext",
285 .irq_mask = s3c_irq_mask,
286 .irq_unmask = s3c_irq_unmask,
287 .irq_ack = s3c_irq_ack,
288 .irq_set_type = s3c_irqext_type,
289 .irq_set_wake = s3c_irqext_wake
a21765a7
BD		 290};
291
1f629b7a
HS		 292static struct irq_chip s3c_irq_eint0t4 = {
293 .name = "s3c-ext0",
294 .irq_ack = s3c_irq_ack,
295 .irq_mask = s3c_irq_mask,
296 .irq_unmask = s3c_irq_unmask,
297 .irq_set_wake = s3c_irq_wake,
298 .irq_set_type = s3c_irqext0_type,
299};
a21765a7 300
bd0b9ac4 301static void s3c_irq_demux(struct irq_desc *desc)
a21765a7 302{
1f629b7a 303 struct irq_chip *chip = irq_desc_get_chip(desc);
f5a25524 304 struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
f0774d41 305 struct s3c_irq_intc *intc = irq_data->intc;
1f629b7a 306 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
4df18a66
TG		 307 unsigned int n, offset, irq;
308 unsigned long src, msk;
f0774d41
HS		 309
310 /* we're using individual domains for the non-dt case
311 * and one big domain for the dt case where the subintc
312 * starts at hwirq number 32.
313 */
5d4c9bc7 314 offset = irq_domain_get_of_node(intc->domain) ? 32 : 0;
1f629b7a
HS		 315
316 chained_irq_enter(chip, desc);
317
318 src = __raw_readl(sub_intc->reg_pending);
319 msk = __raw_readl(sub_intc->reg_mask);
320
321 src &= ~msk;
322 src &= irq_data->sub_bits;
323
324 while (src) {
325 n = __ffs(src);
326 src &= ~(1 << n);
f0774d41
HS		 327 irq = irq_find_mapping(sub_intc->domain, offset + n);
328 generic_handle_irq(irq);
a21765a7
BD		 329 }
330
1f629b7a 331 chained_irq_exit(chip, desc);
a21765a7
BD		 332}
333
17453dd2 334static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
f0774d41 335 struct pt_regs *regs, int intc_offset)
17453dd2
HS		 336{
337 int pnd;
338 int offset;
17453dd2
HS		 339
340 pnd = __raw_readl(intc->reg_intpnd);
341 if (!pnd)
342 return false;
343
f0774d41 344 /* non-dt machines use individual domains */
5d4c9bc7 345 if (!irq_domain_get_of_node(intc->domain))
f0774d41
HS		 346 intc_offset = 0;
347
17453dd2
HS		 348 /* We have a problem that the INTOFFSET register does not always
349 * show one interrupt. Occasionally we get two interrupts through
350 * the prioritiser, and this causes the INTOFFSET register to show
351 * what looks like the logical-or of the two interrupt numbers.
352 *
353 * Thanks to Klaus, Shannon, et al for helping to debug this problem
354 */
355 offset = __raw_readl(intc->reg_intpnd + 4);
356
357 /* Find the bit manually, when the offset is wrong.
358 * The pending register only ever contains the one bit of the next
359 * interrupt to handle.
360 */
361 if (!(pnd & (1 << offset)))
362 offset = __ffs(pnd);
363
cf86bfdd 364 handle_domain_irq(intc->domain, intc_offset + offset, regs);
17453dd2
HS		 365 return true;
366}
367
368asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
369{
370 do {
658dc8fb 371 if (likely(s3c_intc[0]))
f0774d41 372 if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
17453dd2
HS		 373 continue;
374
658dc8fb 375 if (s3c_intc[2])
f0774d41 376 if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
17453dd2
HS		 377 continue;
378
379 break;
380 } while (1);
381}
382
229fd8ff
BD		 383#ifdef CONFIG_FIQ
384/**
385 * s3c24xx_set_fiq - set the FIQ routing
386 * @irq: IRQ number to route to FIQ on processor.
387 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
388 *
389 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
390 * @on is true, the @irq is checked to see if it can be routed and the
391 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
392 * routing is cleared, regardless of which @irq is specified.
393 */
394int s3c24xx_set_fiq(unsigned int irq, bool on)
395{
396 u32 intmod;
397 unsigned offs;
398
399 if (on) {
400 offs = irq - FIQ_START;
401 if (offs > 31)
402 return -EINVAL;
403
404 intmod = 1 << offs;
405 } else {
406 intmod = 0;
407 }
408
409 __raw_writel(intmod, S3C2410_INTMOD);
410 return 0;
411}
0f13c824
BD		 412
413EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
229fd8ff
BD		 414#endif
415
1f629b7a
HS		 416static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
417 irq_hw_number_t hw)
a21765a7 418{
1f629b7a
HS		 419 struct s3c_irq_intc *intc = h->host_data;
420 struct s3c_irq_data *irq_data = &intc->irqs[hw];
421 struct s3c_irq_intc *parent_intc;
422 struct s3c_irq_data *parent_irq_data;
423 unsigned int irqno;
424
1f629b7a
HS		 425 /* attach controller pointer to irq_data */
426 irq_data->intc = intc;
f5a25524 427 irq_data->offset = hw;
a21765a7 428
0fe3cb1e 429 parent_intc = intc->parent;
a21765a7 430
1f629b7a
HS		 431 /* set handler and flags */
432 switch (irq_data->type) {
433 case S3C_IRQTYPE_NONE:
434 return 0;
435 case S3C_IRQTYPE_EINT:
1c8408e3
HS		 436 /* On the S3C2412, the EINT0to3 have a parent irq
437 * but need the s3c_irq_eint0t4 chip
438 */
0fe3cb1e 439 if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
1f629b7a
HS		 440 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
441 handle_edge_irq);
442 else
443 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
444 handle_edge_irq);
445 break;
446 case S3C_IRQTYPE_EDGE:
0fe3cb1e 447 if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
1f629b7a
HS		 448 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
449 handle_edge_irq);
450 else
451 irq_set_chip_and_handler(virq, &s3c_irq_chip,
452 handle_edge_irq);
453 break;
454 case S3C_IRQTYPE_LEVEL:
0fe3cb1e 455 if (parent_intc)
1f629b7a
HS		 456 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
457 handle_level_irq);
458 else
459 irq_set_chip_and_handler(virq, &s3c_irq_chip,
460 handle_level_irq);
461 break;
462 default:
463 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
464 return -EINVAL;
a21765a7 465 }
f5a25524
HS		 466
467 irq_set_chip_data(virq, irq_data);
468
0fe3cb1e 469 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
502a2989
HS		 470 if (irq_data->parent_irq > 31) {
471 pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
472 irq_data->parent_irq);
d17cab44 473 return -EINVAL;
1f629b7a 474 }
a21765a7 475
1f629b7a 476 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
1f629b7a
HS		 477 parent_irq_data->sub_intc = intc;
478 parent_irq_data->sub_bits |= (1UL << hw);
a21765a7 479
1f629b7a
HS		 480 /* attach the demuxer to the parent irq */
481 irqno = irq_find_mapping(parent_intc->domain,
482 irq_data->parent_irq);
483 if (!irqno) {
484 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
485 irq_data->parent_irq);
d17cab44 486 return -EINVAL;
1f629b7a
HS		 487 }
488 irq_set_chained_handler(irqno, s3c_irq_demux);
a21765a7
BD		 489 }
490
1f629b7a 491 return 0;
1f629b7a 492}
a21765a7 493
96009736 494static const struct irq_domain_ops s3c24xx_irq_ops = {
1f629b7a
HS		 495 .map = s3c24xx_irq_map,
496 .xlate = irq_domain_xlate_twocell,
497};
a21765a7 498
1f629b7a
HS		 499static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
500{
501 void __iomem *reg_source;
502 unsigned long pend;
503 unsigned long last;
504 int i;
a21765a7 505
1f629b7a
HS		 506 /* if intpnd is set, read the next pending irq from there */
507 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
a21765a7 508
1f629b7a
HS		 509 last = 0;
510 for (i = 0; i < 4; i++) {
511 pend = __raw_readl(reg_source);
a21765a7 512
1f629b7a 513 if (pend == 0 || pend == last)
a21765a7
BD		 514 break;
515
1f629b7a
HS		 516 __raw_writel(pend, intc->reg_pending);
517 if (intc->reg_intpnd)
518 __raw_writel(pend, intc->reg_intpnd);
a21765a7 519
1f629b7a
HS		 520 pr_info("irq: clearing pending status %08x\n", (int)pend);
521 last = pend;
a21765a7 522 }
1f629b7a 523}
a21765a7 524
bc8fd900 525static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np,
1f629b7a
HS		 526 struct s3c_irq_data *irq_data,
527 struct s3c_irq_intc *parent,
528 unsigned long address)
529{
530 struct s3c_irq_intc *intc;
531 void __iomem *base = (void *)0xf6000000; /* static mapping */
532 int irq_num;
533 int irq_start;
1f629b7a
HS		 534 int ret;
535
536 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
537 if (!intc)
538 return ERR_PTR(-ENOMEM);
539
540 intc->irqs = irq_data;
541
542 if (parent)
543 intc->parent = parent;
544
545 /* select the correct data for the controller.
546 * Need to hard code the irq num start and offset
547 * to preserve the static mapping for now
548 */
549 switch (address) {
550 case 0x4a000000:
551 pr_debug("irq: found main intc\n");
552 intc->reg_pending = base;
553 intc->reg_mask = base + 0x08;
554 intc->reg_intpnd = base + 0x10;
555 irq_num = 32;
556 irq_start = S3C2410_IRQ(0);
1f629b7a
HS		 557 break;
558 case 0x4a000018:
559 pr_debug("irq: found subintc\n");
560 intc->reg_pending = base + 0x18;
561 intc->reg_mask = base + 0x1c;
562 irq_num = 29;
563 irq_start = S3C2410_IRQSUB(0);
1f629b7a
HS		 564 break;
565 case 0x4a000040:
566 pr_debug("irq: found intc2\n");
567 intc->reg_pending = base + 0x40;
568 intc->reg_mask = base + 0x48;
569 intc->reg_intpnd = base + 0x50;
570 irq_num = 8;
571 irq_start = S3C2416_IRQ(0);
1f629b7a
HS		 572 break;
573 case 0x560000a4:
574 pr_debug("irq: found eintc\n");
575 base = (void *)0xfd000000;
576
577 intc->reg_mask = base + 0xa4;
646dd2f0 578 intc->reg_pending = base + 0xa8;
5424f218 579 irq_num = 24;
1f629b7a 580 irq_start = S3C2410_IRQ(32);
1f629b7a
HS		 581 break;
582 default:
583 pr_err("irq: unsupported controller address\n");
584 ret = -EINVAL;
585 goto err;
586 }
a21765a7 587
1f629b7a
HS		 588 /* now that all the data is complete, init the irq-domain */
589 s3c24xx_clear_intc(intc);
590 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
5424f218 591 0, &s3c24xx_irq_ops,
1f629b7a
HS		 592 intc);
593 if (!intc->domain) {
594 pr_err("irq: could not create irq-domain\n");
595 ret = -EINVAL;
596 goto err;
597 }
a21765a7 598
17453dd2
HS		 599 set_handle_irq(s3c24xx_handle_irq);
600
1f629b7a 601 return intc;
a21765a7 602
1f629b7a
HS		 603err:
604 kfree(intc);
605 return ERR_PTR(ret);
606}
a21765a7 607
eb249a11 608static struct s3c_irq_data __maybe_unused init_eint[32] = {
f182aa1d
HS		 609 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
610 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
611 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
612 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
613 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
614 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
615 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
616 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
617 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
618 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
619 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
620 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
621 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
622 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
623 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
624 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
625 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
626 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
627 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
628 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
629 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
630 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
631 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
632 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
633};
a21765a7 634
f182aa1d
HS		 635#ifdef CONFIG_CPU_S3C2410
636static struct s3c_irq_data init_s3c2410base[32] = {
1f629b7a
HS		 637 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
638 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
639 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
640 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
641 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
642 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
643 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
644 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
645 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
646 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
647 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
648 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
649 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
650 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
651 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
652 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
653 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
654 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
655 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
656 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
657 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
658 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
659 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
660 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
661 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
662 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
663 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
664 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
665 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
666 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
667 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
668 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
669};
a21765a7 670
f182aa1d 671static struct s3c_irq_data init_s3c2410subint[32] = {
1f629b7a
HS		 672 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
673 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
674 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
675 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
676 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
677 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
678 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
679 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
680 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
681 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
682 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
683};
a21765a7 684
f182aa1d 685void __init s3c2410_init_irq(void)
1f629b7a 686{
1f629b7a
HS		 687#ifdef CONFIG_FIQ
688 init_FIQ(FIQ_START);
689#endif
a21765a7 690
658dc8fb
HS		 691 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
692 0x4a000000);
693 if (IS_ERR(s3c_intc[0])) {
1f629b7a
HS		 694 pr_err("irq: could not create main interrupt controller\n");
695 return;
a21765a7
BD		 696 }
697
658dc8fb
HS		 698 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
699 s3c_intc[0], 0x4a000018);
700 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
a21765a7 701}
f182aa1d 702#endif
ef602eb5 703
d3d5a2c9 704#ifdef CONFIG_CPU_S3C2412
4245944c 705static struct s3c_irq_data init_s3c2412base[32] = {
1c8408e3
HS		 706 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
707 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
708 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
709 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
4245944c
HS		 710 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
711 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1f629b7a 712 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
4245944c
HS		 713 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
714 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
715 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
716 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
717 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
718 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
719 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
720 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
721 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
722 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
723 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
724 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
725 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
726 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
727 { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
728 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
729 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1f629b7a 730 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
4245944c
HS		 731 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
732 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
733 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
734 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
735 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
736 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
737 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
738};
d3d5a2c9 739
1c8408e3
HS		 740static struct s3c_irq_data init_s3c2412eint[32] = {
741 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
742 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
743 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
744 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
1f629b7a
HS		 745 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
746 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
747 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
748 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
749 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
750 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
751 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
752 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
753 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
754 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
755 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
756 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
757 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
758 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
759 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
760 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
761 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
762 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
763 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
764 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
765};
a21765a7 766
4245944c 767static struct s3c_irq_data init_s3c2412subint[32] = {
1f629b7a
HS		 768 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
769 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
770 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
771 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
772 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
773 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
774 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
775 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
776 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
777 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
778 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
4245944c
HS		 779 { .type = S3C_IRQTYPE_NONE, },
780 { .type = S3C_IRQTYPE_NONE, },
781 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
782 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
1f629b7a 783};
a21765a7 784
bc8fd900 785void __init s3c2412_init_irq(void)
1f629b7a 786{
4245944c 787 pr_info("S3C2412: IRQ Support\n");
a21765a7 788
1f629b7a
HS		 789#ifdef CONFIG_FIQ
790 init_FIQ(FIQ_START);
791#endif
a21765a7 792
658dc8fb
HS		 793 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
794 0x4a000000);
795 if (IS_ERR(s3c_intc[0])) {
1f629b7a
HS		 796 pr_err("irq: could not create main interrupt controller\n");
797 return;
a21765a7
BD		 798 }
799
658dc8fb
HS		 800 s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
801 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
802 s3c_intc[0], 0x4a000018);
a21765a7 803}
d3d5a2c9 804#endif
ef602eb5
HS		 805
806#ifdef CONFIG_CPU_S3C2416
20f6c781
HS		 807static struct s3c_irq_data init_s3c2416base[32] = {
808 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
809 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
810 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
811 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
812 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
813 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
814 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
815 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
816 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
817 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
818 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
819 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
820 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
821 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
822 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
823 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
824 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
825 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
826 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
827 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
828 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
829 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
830 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
831 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
832 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
833 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
834 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
835 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
836 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
837 { .type = S3C_IRQTYPE_NONE, },
838 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
839 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
ef602eb5
HS		 840};
841
20f6c781
HS		 842static struct s3c_irq_data init_s3c2416subint[32] = {
843 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
844 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
845 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
846 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
847 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
848 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
849 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
850 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
851 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
852 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
853 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
854 { .type = S3C_IRQTYPE_NONE }, /* reserved */
855 { .type = S3C_IRQTYPE_NONE }, /* reserved */
856 { .type = S3C_IRQTYPE_NONE }, /* reserved */
857 { .type = S3C_IRQTYPE_NONE }, /* reserved */
858 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
859 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
860 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
861 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
862 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
863 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
864 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
865 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
866 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
867 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
868 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
869 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
870 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
871 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
ef602eb5
HS		 872};
873
20f6c781
HS		 874static struct s3c_irq_data init_s3c2416_second[32] = {
875 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
1ebc7e83 876 { .type = S3C_IRQTYPE_NONE }, /* reserved */
20f6c781
HS		 877 { .type = S3C_IRQTYPE_NONE }, /* reserved */
878 { .type = S3C_IRQTYPE_NONE }, /* reserved */
879 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
1ebc7e83 880 { .type = S3C_IRQTYPE_NONE }, /* reserved */
20f6c781 881 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
ef602eb5
HS		 882};
883
4a282dd3 884void __init s3c2416_init_irq(void)
ef602eb5 885{
20f6c781 886 pr_info("S3C2416: IRQ Support\n");
ef602eb5 887
20f6c781
HS		 888#ifdef CONFIG_FIQ
889 init_FIQ(FIQ_START);
890#endif
ef602eb5 891
658dc8fb
HS		 892 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
893 0x4a000000);
894 if (IS_ERR(s3c_intc[0])) {
20f6c781
HS		 895 pr_err("irq: could not create main interrupt controller\n");
896 return;
897 }
ef602eb5 898
658dc8fb
HS		 899 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
900 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
901 s3c_intc[0], 0x4a000018);
ef602eb5 902
658dc8fb
HS		 903 s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
904 NULL, 0x4a000040);
ef602eb5
HS		 905}
906
ef602eb5 907#endif
6b628917 908
ce6c164b 909#ifdef CONFIG_CPU_S3C2440
f0301673
HS		 910static struct s3c_irq_data init_s3c2440base[32] = {
911 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
912 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
913 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
914 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
915 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
916 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
917 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
918 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
919 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
920 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
921 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
922 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
923 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
924 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
925 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
926 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
927 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
928 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
929 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
930 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
931 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
932 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
933 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
934 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
935 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
936 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
937 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
938 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
939 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
940 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
941 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
942 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
943};
2286cf46 944
f0301673
HS		 945static struct s3c_irq_data init_s3c2440subint[32] = {
946 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
947 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
948 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
949 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
950 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
951 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
952 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
953 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
954 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
955 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
956 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
e2714f79
HS		 957 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
958 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
f0301673
HS		 959 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
960 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
2286cf46
HS		 961};
962
7cefed5e 963void __init s3c2440_init_irq(void)
2286cf46 964{
f0301673 965 pr_info("S3C2440: IRQ Support\n");
ef602eb5 966
f0301673
HS		 967#ifdef CONFIG_FIQ
968 init_FIQ(FIQ_START);
969#endif
6f8d7ea2 970
658dc8fb
HS		 971 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
972 0x4a000000);
973 if (IS_ERR(s3c_intc[0])) {
f0301673
HS		 974 pr_err("irq: could not create main interrupt controller\n");
975 return;
6f8d7ea2 976 }
7cefed5e 977
658dc8fb
HS		 978 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
979 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
980 s3c_intc[0], 0x4a000018);
ef602eb5 981}
ce6c164b 982#endif
ef602eb5 983
ce6c164b 984#ifdef CONFIG_CPU_S3C2442
70644ade
HS		 985static struct s3c_irq_data init_s3c2442base[32] = {
986 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
987 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
988 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
989 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
990 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
991 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
992 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
993 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
994 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
995 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
996 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
997 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
998 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
999 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1000 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1001 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1002 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
1003 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
1004 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
1005 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
1006 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
1007 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
1008 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1009 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1010 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
1011 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1012 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1013 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1014 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1015 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1016 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1017 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1018};
6f8d7ea2 1019
70644ade
HS		 1020static struct s3c_irq_data init_s3c2442subint[32] = {
1021 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1022 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1023 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1024 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1025 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1026 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1027 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1028 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1029 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1030 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1031 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
e2714f79
HS		 1032 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1033 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
70644ade 1034};
6f8d7ea2 1035
70644ade
HS		 1036void __init s3c2442_init_irq(void)
1037{
70644ade 1038 pr_info("S3C2442: IRQ Support\n");
6f8d7ea2 1039
70644ade
HS		 1040#ifdef CONFIG_FIQ
1041 init_FIQ(FIQ_START);
1042#endif
ce6c164b 1043
658dc8fb
HS		 1044 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
1045 0x4a000000);
1046 if (IS_ERR(s3c_intc[0])) {
70644ade
HS		 1047 pr_err("irq: could not create main interrupt controller\n");
1048 return;
ce6c164b 1049 }
70644ade 1050
658dc8fb
HS		 1051 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1052 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
1053 s3c_intc[0], 0x4a000018);
6f8d7ea2 1054}
ef602eb5 1055#endif
6b628917
HS		 1056
1057#ifdef CONFIG_CPU_S3C2443
f44ddba3
HS		 1058static struct s3c_irq_data init_s3c2443base[32] = {
1059 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1060 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1061 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1062 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1063 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1064 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1065 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1066 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1067 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1068 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
1069 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1070 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1071 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1072 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1073 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1074 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1075 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
1076 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
1077 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
1078 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
1079 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
1080 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
1081 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1082 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1083 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
1084 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1085 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1086 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1087 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1088 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1089 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1090 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
6b628917
HS		 1091};
1092
6b628917 1093
f44ddba3
HS		 1094static struct s3c_irq_data init_s3c2443subint[32] = {
1095 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1096 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1097 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1098 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1099 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1100 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1101 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1102 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1103 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1104 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1105 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1106 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1107 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1108 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1109 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1110 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1111 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1112 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1113 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1114 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1115 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1116 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1117 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1118 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1119 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1120 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1121 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1122 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1123 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
6b628917
HS		 1124};
1125
b499b7a8 1126void __init s3c2443_init_irq(void)
6b628917 1127{
f44ddba3 1128 pr_info("S3C2443: IRQ Support\n");
6b628917 1129
f44ddba3
HS		 1130#ifdef CONFIG_FIQ
1131 init_FIQ(FIQ_START);
1132#endif
6b628917 1133
658dc8fb
HS		 1134 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
1135 0x4a000000);
1136 if (IS_ERR(s3c_intc[0])) {
f44ddba3
HS		 1137 pr_err("irq: could not create main interrupt controller\n");
1138 return;
1139 }
6b628917 1140
658dc8fb
HS		 1141 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1142 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
1143 s3c_intc[0], 0x4a000018);
6b628917 1144}
6b628917 1145#endif
f0774d41
HS		 1146
1147#ifdef CONFIG_OF
1148static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
1149 irq_hw_number_t hw)
1150{
1151 unsigned int ctrl_num = hw / 32;
1152 unsigned int intc_hw = hw % 32;
1153 struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
1154 struct s3c_irq_intc *parent_intc = intc->parent;
1155 struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];
1156
1157 /* attach controller pointer to irq_data */
1158 irq_data->intc = intc;
1159 irq_data->offset = intc_hw;
1160
1161 if (!parent_intc)
1162 irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
1163 else
1164 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
1165 handle_edge_irq);
1166
1167 irq_set_chip_data(virq, irq_data);
1168
f0774d41
HS		 1169 return 0;
1170}
1171
1172/* Translate our of irq notation
1173 * format: <ctrl_num ctrl_irq parent_irq type>
1174 */
1175static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
1176 const u32 *intspec, unsigned int intsize,
1177 irq_hw_number_t *out_hwirq, unsigned int *out_type)
1178{
1179 struct s3c_irq_intc *intc;
1180 struct s3c_irq_intc *parent_intc;
1181 struct s3c_irq_data *irq_data;
1182 struct s3c_irq_data *parent_irq_data;
1183 int irqno;
1184
1185 if (WARN_ON(intsize < 4))
1186 return -EINVAL;
1187
1188 if (intspec[0] > 2 || !s3c_intc[intspec[0]]) {
1189 pr_err("controller number %d invalid\n", intspec[0]);
1190 return -EINVAL;
1191 }
1192 intc = s3c_intc[intspec[0]];
1193
1194 *out_hwirq = intspec[0] * 32 + intspec[2];
1195 *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
1196
1197 parent_intc = intc->parent;
1198 if (parent_intc) {
1199 irq_data = &intc->irqs[intspec[2]];
1200 irq_data->parent_irq = intspec[1];
1201 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
1202 parent_irq_data->sub_intc = intc;
1203 parent_irq_data->sub_bits |= (1UL << intspec[2]);
1204
1205 /* parent_intc is always s3c_intc[0], so no offset */
1206 irqno = irq_create_mapping(parent_intc->domain, intspec[1]);
1207 if (irqno < 0) {
1208 pr_err("irq: could not map parent interrupt\n");
1209 return irqno;
1210 }
1211
1212 irq_set_chained_handler(irqno, s3c_irq_demux);
1213 }
1214
1215 return 0;
1216}
1217
96009736 1218static const struct irq_domain_ops s3c24xx_irq_ops_of = {
f0774d41
HS		 1219 .map = s3c24xx_irq_map_of,
1220 .xlate = s3c24xx_irq_xlate_of,
1221};
1222
1223struct s3c24xx_irq_of_ctrl {
1224 char *name;
1225 unsigned long offset;
1226 struct s3c_irq_intc **handle;
1227 struct s3c_irq_intc **parent;
1228 struct irq_domain_ops *ops;
1229};
1230
1231static int __init s3c_init_intc_of(struct device_node *np,
1232 struct device_node *interrupt_parent,
1233 struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl)
1234{
1235 struct s3c_irq_intc *intc;
1236 struct s3c24xx_irq_of_ctrl *ctrl;
1237 struct irq_domain *domain;
1238 void __iomem *reg_base;
1239 int i;
1240
1241 reg_base = of_iomap(np, 0);
1242 if (!reg_base) {
1243 pr_err("irq-s3c24xx: could not map irq registers\n");
1244 return -EINVAL;
1245 }
1246
1247 domain = irq_domain_add_linear(np, num_ctrl * 32,
1248 &s3c24xx_irq_ops_of, NULL);
1249 if (!domain) {
1250 pr_err("irq: could not create irq-domain\n");
1251 return -EINVAL;
1252 }
1253
1254 for (i = 0; i < num_ctrl; i++) {
1255 ctrl = &s3c_ctrl[i];
1256
1257 pr_debug("irq: found controller %s\n", ctrl->name);
1258
1259 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
1260 if (!intc)
1261 return -ENOMEM;
1262
1263 intc->domain = domain;
1264 intc->irqs = kzalloc(sizeof(struct s3c_irq_data) * 32,
1265 GFP_KERNEL);
1266 if (!intc->irqs) {
1267 kfree(intc);
1268 return -ENOMEM;
1269 }
1270
1271 if (ctrl->parent) {
1272 intc->reg_pending = reg_base + ctrl->offset;
1273 intc->reg_mask = reg_base + ctrl->offset + 0x4;
1274
1275 if (*(ctrl->parent)) {
1276 intc->parent = *(ctrl->parent);
1277 } else {
1278 pr_warn("irq: parent of %s missing\n",
1279 ctrl->name);
1280 kfree(intc->irqs);
1281 kfree(intc);
1282 continue;
1283 }
1284 } else {
1285 intc->reg_pending = reg_base + ctrl->offset;
1286 intc->reg_mask = reg_base + ctrl->offset + 0x08;
1287 intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
1288 }
1289
1290 s3c24xx_clear_intc(intc);
1291 s3c_intc[i] = intc;
1292 }
1293
1294 set_handle_irq(s3c24xx_handle_irq);
1295
1296 return 0;
1297}
1298
1299static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
1300 {
1301 .name = "intc",
1302 .offset = 0,
1303 }, {
1304 .name = "subintc",
1305 .offset = 0x18,
1306 .parent = &s3c_intc[0],
1307 }
1308};
1309
1310int __init s3c2410_init_intc_of(struct device_node *np,
4f41083b 1311 struct device_node *interrupt_parent)
f0774d41
HS		 1312{
1313 return s3c_init_intc_of(np, interrupt_parent,
1314 s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl));
1315}
1316IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
1317
1318static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
1319 {
1320 .name = "intc",
1321 .offset = 0,
1322 }, {
1323 .name = "subintc",
1324 .offset = 0x18,
1325 .parent = &s3c_intc[0],
1326 }, {
1327 .name = "intc2",
1328 .offset = 0x40,
1329 }
1330};
1331
1332int __init s3c2416_init_intc_of(struct device_node *np,
4f41083b 1333 struct device_node *interrupt_parent)
f0774d41
HS		 1334{
1335 return s3c_init_intc_of(np, interrupt_parent,
1336 s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl));
6b628917 1337}
f0774d41 1338IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);
6b628917 1339#endif
Linux 6.x block layer and io_uring tree(s)