[linux-2.6-block.git] / drivers / irqchip / irq-renesas-irqc.c

/*
 * Renesas IRQC Driver
 *
 *  Copyright (C) 2013 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/clk.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>

#define IRQC_IRQ_MAX	32	/* maximum 32 interrupts per driver instance */

#define IRQC_REQ_STS	0x00	/* Interrupt Request Status Register */
#define IRQC_EN_STS	0x04	/* Interrupt Enable Status Register */
#define IRQC_EN_SET	0x08	/* Interrupt Enable Set Register */
#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
				/* SYS-CPU vs. RT-CPU */
#define DETECT_STATUS	0x100	/* IRQn Detect Status Register */
#define MONITOR		0x104	/* IRQn Signal Level Monitor Register */
#define HLVL_STS	0x108	/* IRQn High Level Detect Status Register */
#define LLVL_STS	0x10c	/* IRQn Low Level Detect Status Register */
#define S_R_EDGE_STS	0x110	/* IRQn Sync Rising Edge Detect Status Reg. */
#define S_F_EDGE_STS	0x114	/* IRQn Sync Falling Edge Detect Status Reg. */
#define A_R_EDGE_STS	0x118	/* IRQn Async Rising Edge Detect Status Reg. */
#define A_F_EDGE_STS	0x11c	/* IRQn Async Falling Edge Detect Status Reg. */
#define CHTEN_STS	0x120	/* Chattering Reduction Status Register */
#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
				/* IRQn Configuration Register */

struct irqc_irq {
	int hw_irq;
	int requested_irq;
	int domain_irq;
	struct irqc_priv *p;
};

struct irqc_priv {
	void __iomem *iomem;
	void __iomem *cpu_int_base;
	struct irqc_irq irq[IRQC_IRQ_MAX];
	unsigned int number_of_irqs;
	struct platform_device *pdev;
	struct irq_chip irq_chip;
	struct irq_domain *irq_domain;
	struct clk *clk;
};

static void irqc_dbg(struct irqc_irq *i, char *str)
{
	dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
		str, i->requested_irq, i->hw_irq, i->domain_irq);
}

static void irqc_irq_enable(struct irq_data *d)
{
	struct irqc_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	irqc_dbg(&p->irq[hw_irq], "enable");
	iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET);
}

static void irqc_irq_disable(struct irq_data *d)
{
	struct irqc_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	irqc_dbg(&p->irq[hw_irq], "disable");
	iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
}

static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
	[IRQ_TYPE_LEVEL_LOW]	= 0x01,
	[IRQ_TYPE_LEVEL_HIGH]	= 0x02,
	[IRQ_TYPE_EDGE_FALLING]	= 0x04,	/* Synchronous */
	[IRQ_TYPE_EDGE_RISING]	= 0x08,	/* Synchronous */
	[IRQ_TYPE_EDGE_BOTH]	= 0x0c,	/* Synchronous */
};

static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct irqc_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);
	unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
	u32 tmp;

	irqc_dbg(&p->irq[hw_irq], "sense");

	if (!value)
		return -EINVAL;

	tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
	tmp &= ~0x3f;
	tmp |= value;
	iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
	return 0;
}

static int irqc_irq_set_wake(struct irq_data *d, unsigned int on)
{
	struct irqc_priv *p = irq_data_get_irq_chip_data(d);

	if (!p->clk)
		return 0;

	if (on)
		clk_enable(p->clk);
	else
		clk_disable(p->clk);

	return 0;
}

static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
{
	struct irqc_irq *i = dev_id;
	struct irqc_priv *p = i->p;
	u32 bit = BIT(i->hw_irq);

	irqc_dbg(i, "demux1");

	if (ioread32(p->iomem + DETECT_STATUS) & bit) {
		iowrite32(bit, p->iomem + DETECT_STATUS);
		irqc_dbg(i, "demux2");
		generic_handle_irq(i->domain_irq);
		return IRQ_HANDLED;
	}
	return IRQ_NONE;
}

static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
			       irq_hw_number_t hw)
{
	struct irqc_priv *p = h->host_data;

	p->irq[hw].domain_irq = virq;
	p->irq[hw].hw_irq = hw;

	irqc_dbg(&p->irq[hw], "map");
	irq_set_chip_data(virq, h->host_data);
	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
	set_irq_flags(virq, IRQF_VALID); /* kill me now */
	return 0;
}

static const struct irq_domain_ops irqc_irq_domain_ops = {
	.map	= irqc_irq_domain_map,
	.xlate  = irq_domain_xlate_twocell,
};

static int irqc_probe(struct platform_device *pdev)
{
	struct irqc_priv *p;
	struct resource *io;
	struct resource *irq;
	struct irq_chip *irq_chip;
	const char *name = dev_name(&pdev->dev);
	int ret;
	int k;

	p = kzalloc(sizeof(*p), GFP_KERNEL);
	if (!p) {
		dev_err(&pdev->dev, "failed to allocate driver data\n");
		ret = -ENOMEM;
		goto err0;
	}

	p->pdev = pdev;
	platform_set_drvdata(pdev, p);

	p->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(p->clk)) {
		dev_warn(&pdev->dev, "unable to get clock\n");
		p->clk = NULL;
	}

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

	/* get hold of manadatory IOMEM */
	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!io) {
		dev_err(&pdev->dev, "not enough IOMEM resources\n");
		ret = -EINVAL;
		goto err1;
	}

	/* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
	for (k = 0; k < IRQC_IRQ_MAX; k++) {
		irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
		if (!irq)
			break;

		p->irq[k].p = p;
		p->irq[k].requested_irq = irq->start;
	}

	p->number_of_irqs = k;
	if (p->number_of_irqs < 1) {
		dev_err(&pdev->dev, "not enough IRQ resources\n");
		ret = -EINVAL;
		goto err1;
	}

	/* ioremap IOMEM and setup read/write callbacks */
	p->iomem = ioremap_nocache(io->start, resource_size(io));
	if (!p->iomem) {
		dev_err(&pdev->dev, "failed to remap IOMEM\n");
		ret = -ENXIO;
		goto err2;
	}

	p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */

	irq_chip = &p->irq_chip;
	irq_chip->name = name;
	irq_chip->irq_mask = irqc_irq_disable;
	irq_chip->irq_unmask = irqc_irq_enable;
	irq_chip->irq_set_type = irqc_irq_set_type;
	irq_chip->irq_set_wake = irqc_irq_set_wake;
	irq_chip->flags	= IRQCHIP_MASK_ON_SUSPEND;

	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
					      p->number_of_irqs, 0,
					      &irqc_irq_domain_ops, p);
	if (!p->irq_domain) {
		ret = -ENXIO;
		dev_err(&pdev->dev, "cannot initialize irq domain\n");
		goto err2;
	}

	/* request interrupts one by one */
	for (k = 0; k < p->number_of_irqs; k++) {
		if (request_irq(p->irq[k].requested_irq, irqc_irq_handler,
				0, name, &p->irq[k])) {
			dev_err(&pdev->dev, "failed to request IRQ\n");
			ret = -ENOENT;
			goto err3;
		}
	}

	dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);

	return 0;
err3:
	while (--k >= 0)
		free_irq(p->irq[k].requested_irq, &p->irq[k]);

	irq_domain_remove(p->irq_domain);
err2:
	iounmap(p->iomem);
err1:
	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	kfree(p);
err0:
	return ret;
}

static int irqc_remove(struct platform_device *pdev)
{
	struct irqc_priv *p = platform_get_drvdata(pdev);
	int k;

	for (k = 0; k < p->number_of_irqs; k++)
		free_irq(p->irq[k].requested_irq, &p->irq[k]);

	irq_domain_remove(p->irq_domain);
	iounmap(p->iomem);
	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	kfree(p);
	return 0;
}

static const struct of_device_id irqc_dt_ids[] = {
	{ .compatible = "renesas,irqc", },
	{},
};
MODULE_DEVICE_TABLE(of, irqc_dt_ids);

static struct platform_driver irqc_device_driver = {
	.probe		= irqc_probe,
	.remove		= irqc_remove,
	.driver		= {
		.name	= "renesas_irqc",
		.of_match_table	= irqc_dt_ids,
	}
};

static int __init irqc_init(void)
{
	return platform_driver_register(&irqc_device_driver);
}
postcore_initcall(irqc_init);

static void __exit irqc_exit(void)
{
	platform_driver_unregister(&irqc_device_driver);
}
module_exit(irqc_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas IRQC Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
fbc83b7f MD	1	/*
	2	* Renesas IRQC Driver
	3	*
	4	* Copyright (C) 2013 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
6f46aedb	20	#include <linux/clk.h>
fbc83b7f MD	21	#include <linux/init.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/spinlock.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/ioport.h>
	26	#include <linux/io.h>
	27	#include <linux/irq.h>
	28	#include <linux/irqdomain.h>
	29	#include <linux/err.h>
	30	#include <linux/slab.h>
	31	#include <linux/module.h>
51b05f6b	32	#include <linux/pm_runtime.h>
fbc83b7f	33
1cd5ec73	34	#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
fbc83b7f	35
1cd5ec73 GU	36	#define IRQC_REQ_STS 0x00 /* Interrupt Request Status Register */
	37	#define IRQC_EN_STS 0x04 /* Interrupt Enable Status Register */
	38	#define IRQC_EN_SET 0x08 /* Interrupt Enable Set Register */
fbc83b7f	39	#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
1cd5ec73 GU	40	/* SYS-CPU vs. RT-CPU */
	41	#define DETECT_STATUS 0x100 /* IRQn Detect Status Register */
	42	#define MONITOR 0x104 /* IRQn Signal Level Monitor Register */
	43	#define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */
	44	#define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */
	45	#define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */
	46	#define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */
	47	#define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */
	48	#define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */
	49	#define CHTEN_STS 0x120 /* Chattering Reduction Status Register */
fbc83b7f	50	#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
1cd5ec73	51	/* IRQn Configuration Register */
fbc83b7f MD	52
	53	struct irqc_irq {
	54	int hw_irq;
	55	int requested_irq;
	56	int domain_irq;
	57	struct irqc_priv *p;
	58	};
	59
	60	struct irqc_priv {
	61	void __iomem *iomem;
	62	void __iomem *cpu_int_base;
	63	struct irqc_irq irq[IRQC_IRQ_MAX];
fbc83b7f MD	64	unsigned int number_of_irqs;
	65	struct platform_device *pdev;
	66	struct irq_chip irq_chip;
	67	struct irq_domain *irq_domain;
6f46aedb	68	struct clk *clk;
fbc83b7f MD	69	};
	70
	71	static void irqc_dbg(struct irqc_irq i, char str)
	72	{
	73	dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
	74	str, i->requested_irq, i->hw_irq, i->domain_irq);
	75	}
	76
	77	static void irqc_irq_enable(struct irq_data *d)
	78	{
	79	struct irqc_priv *p = irq_data_get_irq_chip_data(d);
	80	int hw_irq = irqd_to_hwirq(d);
	81
	82	irqc_dbg(&p->irq[hw_irq], "enable");
	83	iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET);
	84	}
	85
	86	static void irqc_irq_disable(struct irq_data *d)
	87	{
	88	struct irqc_priv *p = irq_data_get_irq_chip_data(d);
	89	int hw_irq = irqd_to_hwirq(d);
	90
	91	irqc_dbg(&p->irq[hw_irq], "disable");
	92	iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
	93	}
	94
fbc83b7f	95	static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
ce70af18 SS	96	[IRQ_TYPE_LEVEL_LOW] = 0x01,
	97	[IRQ_TYPE_LEVEL_HIGH] = 0x02,
	98	[IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */
	99	[IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */
	100	[IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */
fbc83b7f MD	101	};
	102
	103	static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
	104	{
	105	struct irqc_priv *p = irq_data_get_irq_chip_data(d);
	106	int hw_irq = irqd_to_hwirq(d);
	107	unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
f791e3c1	108	u32 tmp;
fbc83b7f MD	109
	110	irqc_dbg(&p->irq[hw_irq], "sense");
	111
ce70af18	112	if (!value)
fbc83b7f MD	113	return -EINVAL;
	114
	115	tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
	116	tmp &= ~0x3f;
ce70af18	117	tmp \|= value;
fbc83b7f MD	118	iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
	119	return 0;
	120	}
	121
6f46aedb GU	122	static int irqc_irq_set_wake(struct irq_data *d, unsigned int on)
	123	{
	124	struct irqc_priv *p = irq_data_get_irq_chip_data(d);
	125
	126	if (!p->clk)
	127	return 0;
	128
	129	if (on)
	130	clk_enable(p->clk);
	131	else
	132	clk_disable(p->clk);
	133
	134	return 0;
	135	}
	136
fbc83b7f MD	137	static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
	138	{
	139	struct irqc_irq *i = dev_id;
	140	struct irqc_priv *p = i->p;
f791e3c1	141	u32 bit = BIT(i->hw_irq);
fbc83b7f MD	142
	143	irqc_dbg(i, "demux1");
	144
	145	if (ioread32(p->iomem + DETECT_STATUS) & bit) {
	146	iowrite32(bit, p->iomem + DETECT_STATUS);
	147	irqc_dbg(i, "demux2");
	148	generic_handle_irq(i->domain_irq);
	149	return IRQ_HANDLED;
	150	}
	151	return IRQ_NONE;
	152	}
	153
	154	static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
	155	irq_hw_number_t hw)
	156	{
	157	struct irqc_priv *p = h->host_data;
	158
	159	p->irq[hw].domain_irq = virq;
	160	p->irq[hw].hw_irq = hw;
	161
	162	irqc_dbg(&p->irq[hw], "map");
	163	irq_set_chip_data(virq, h->host_data);
	164	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
	165	set_irq_flags(virq, IRQF_VALID); /* kill me now */
	166	return 0;
	167	}
	168
96009736	169	static const struct irq_domain_ops irqc_irq_domain_ops = {
fbc83b7f	170	.map = irqc_irq_domain_map,
3b8dfa7c	171	.xlate = irq_domain_xlate_twocell,
fbc83b7f MD	172	};
	173
	174	static int irqc_probe(struct platform_device *pdev)
	175	{
fbc83b7f MD	176	struct irqc_priv *p;
	177	struct resource *io;
	178	struct resource *irq;
	179	struct irq_chip *irq_chip;
	180	const char *name = dev_name(&pdev->dev);
	181	int ret;
	182	int k;
	183
	184	p = kzalloc(sizeof(*p), GFP_KERNEL);
	185	if (!p) {
	186	dev_err(&pdev->dev, "failed to allocate driver data\n");
	187	ret = -ENOMEM;
	188	goto err0;
	189	}
	190
fbc83b7f MD	191	p->pdev = pdev;
	192	platform_set_drvdata(pdev, p);
	193
6f46aedb GU	194	p->clk = devm_clk_get(&pdev->dev, NULL);
	195	if (IS_ERR(p->clk)) {
	196	dev_warn(&pdev->dev, "unable to get clock\n");
	197	p->clk = NULL;
	198	}
	199
51b05f6b GU	200	pm_runtime_enable(&pdev->dev);
	201	pm_runtime_get_sync(&pdev->dev);
	202
fbc83b7f MD	203	/* get hold of manadatory IOMEM */
	204	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	205	if (!io) {
	206	dev_err(&pdev->dev, "not enough IOMEM resources\n");
	207	ret = -EINVAL;
	208	goto err1;
	209	}
	210
	211	/* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
	212	for (k = 0; k < IRQC_IRQ_MAX; k++) {
	213	irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
	214	if (!irq)
	215	break;
	216
	217	p->irq[k].p = p;
	218	p->irq[k].requested_irq = irq->start;
	219	}
	220
	221	p->number_of_irqs = k;
	222	if (p->number_of_irqs < 1) {
	223	dev_err(&pdev->dev, "not enough IRQ resources\n");
	224	ret = -EINVAL;
	225	goto err1;
	226	}
	227
	228	/* ioremap IOMEM and setup read/write callbacks */
	229	p->iomem = ioremap_nocache(io->start, resource_size(io));
	230	if (!p->iomem) {
	231	dev_err(&pdev->dev, "failed to remap IOMEM\n");
	232	ret = -ENXIO;
	233	goto err2;
	234	}
	235
	236	p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */
	237
	238	irq_chip = &p->irq_chip;
	239	irq_chip->name = name;
	240	irq_chip->irq_mask = irqc_irq_disable;
	241	irq_chip->irq_unmask = irqc_irq_enable;
fbc83b7f	242	irq_chip->irq_set_type = irqc_irq_set_type;
6f46aedb GU	243	irq_chip->irq_set_wake = irqc_irq_set_wake;
6f46aedb GU	244	irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
fbc83b7f MD	245
fbc83b7f MD	246	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
f3110534	247	p->number_of_irqs, 0,
fbc83b7f MD	248	&irqc_irq_domain_ops, p);
	249	if (!p->irq_domain) {
	250	ret = -ENXIO;
	251	dev_err(&pdev->dev, "cannot initialize irq domain\n");
	252	goto err2;
	253	}
	254
	255	/* request interrupts one by one */
	256	for (k = 0; k < p->number_of_irqs; k++) {
	257	if (request_irq(p->irq[k].requested_irq, irqc_irq_handler,
	258	0, name, &p->irq[k])) {
	259	dev_err(&pdev->dev, "failed to request IRQ\n");
	260	ret = -ENOENT;
	261	goto err3;
	262	}
	263	}
	264
	265	dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
	266
fbc83b7f MD	267	return 0;
fbc83b7f MD	268	err3:
dfaf820a AL	269	while (--k >= 0)
dfaf820a AL	270	free_irq(p->irq[k].requested_irq, &p->irq[k]);
fbc83b7f MD	271
	272	irq_domain_remove(p->irq_domain);
	273	err2:
	274	iounmap(p->iomem);
	275	err1:
51b05f6b GU	276	pm_runtime_put(&pdev->dev);
51b05f6b GU	277	pm_runtime_disable(&pdev->dev);
fbc83b7f MD	278	kfree(p);
	279	err0:
	280	return ret;
	281	}
	282
	283	static int irqc_remove(struct platform_device *pdev)
	284	{
	285	struct irqc_priv *p = platform_get_drvdata(pdev);
	286	int k;
	287
	288	for (k = 0; k < p->number_of_irqs; k++)
	289	free_irq(p->irq[k].requested_irq, &p->irq[k]);
	290
	291	irq_domain_remove(p->irq_domain);
	292	iounmap(p->iomem);
51b05f6b GU	293	pm_runtime_put(&pdev->dev);
51b05f6b GU	294	pm_runtime_disable(&pdev->dev);
fbc83b7f MD	295	kfree(p);
	296	return 0;
	297	}
	298
3b8dfa7c MD	299	static const struct of_device_id irqc_dt_ids[] = {
	300	{ .compatible = "renesas,irqc", },
	301	{},
	302	};
	303	MODULE_DEVICE_TABLE(of, irqc_dt_ids);
	304
fbc83b7f MD	305	static struct platform_driver irqc_device_driver = {
	306	.probe = irqc_probe,
	307	.remove = irqc_remove,
	308	.driver = {
	309	.name = "renesas_irqc",
3b8dfa7c	310	.of_match_table = irqc_dt_ids,
fbc83b7f MD	311	}
	312	};
	313
	314	static int __init irqc_init(void)
	315	{
	316	return platform_driver_register(&irqc_device_driver);
	317	}
	318	postcore_initcall(irqc_init);
	319
	320	static void __exit irqc_exit(void)
	321	{
	322	platform_driver_unregister(&irqc_device_driver);
	323	}
	324	module_exit(irqc_exit);
	325
	326	MODULE_AUTHOR("Magnus Damm");
	327	MODULE_DESCRIPTION("Renesas IRQC Driver");
	328	MODULE_LICENSE("GPL v2");