[linux-2.6-block.git] / drivers / irqchip / irq-imgpdc.c

/*
 * IMG PowerDown Controller (PDC)
 *
 * Copyright 2010-2013 Imagination Technologies Ltd.
 *
 * Exposes the syswake and PDC peripheral wake interrupts to the system.
 *
 */

#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>

/* PDC interrupt register numbers */

#define PDC_IRQ_STATUS			0x310
#define PDC_IRQ_ENABLE			0x314
#define PDC_IRQ_CLEAR			0x318
#define PDC_IRQ_ROUTE			0x31c
#define PDC_SYS_WAKE_BASE		0x330
#define PDC_SYS_WAKE_STRIDE		0x8
#define PDC_SYS_WAKE_CONFIG_BASE	0x334
#define PDC_SYS_WAKE_CONFIG_STRIDE	0x8

/* PDC interrupt register field masks */

#define PDC_IRQ_SYS3			0x08
#define PDC_IRQ_SYS2			0x04
#define PDC_IRQ_SYS1			0x02
#define PDC_IRQ_SYS0			0x01
#define PDC_IRQ_ROUTE_WU_EN_SYS3	0x08000000
#define PDC_IRQ_ROUTE_WU_EN_SYS2	0x04000000
#define PDC_IRQ_ROUTE_WU_EN_SYS1	0x02000000
#define PDC_IRQ_ROUTE_WU_EN_SYS0	0x01000000
#define PDC_IRQ_ROUTE_WU_EN_WD		0x00040000
#define PDC_IRQ_ROUTE_WU_EN_IR		0x00020000
#define PDC_IRQ_ROUTE_WU_EN_RTC		0x00010000
#define PDC_IRQ_ROUTE_EXT_EN_SYS3	0x00000800
#define PDC_IRQ_ROUTE_EXT_EN_SYS2	0x00000400
#define PDC_IRQ_ROUTE_EXT_EN_SYS1	0x00000200
#define PDC_IRQ_ROUTE_EXT_EN_SYS0	0x00000100
#define PDC_IRQ_ROUTE_EXT_EN_WD		0x00000004
#define PDC_IRQ_ROUTE_EXT_EN_IR		0x00000002
#define PDC_IRQ_ROUTE_EXT_EN_RTC	0x00000001
#define PDC_SYS_WAKE_RESET		0x00000010
#define PDC_SYS_WAKE_INT_MODE		0x0000000e
#define PDC_SYS_WAKE_INT_MODE_SHIFT	1
#define PDC_SYS_WAKE_PIN_VAL		0x00000001

/* PDC interrupt constants */

#define PDC_SYS_WAKE_INT_LOW		0x0
#define PDC_SYS_WAKE_INT_HIGH		0x1
#define PDC_SYS_WAKE_INT_DOWN		0x2
#define PDC_SYS_WAKE_INT_UP		0x3
#define PDC_SYS_WAKE_INT_CHANGE		0x6
#define PDC_SYS_WAKE_INT_NONE		0x4

/**
 * struct pdc_intc_priv - private pdc interrupt data.
 * @nr_perips:		Number of peripheral interrupt signals.
 * @nr_syswakes:	Number of syswake signals.
 * @perip_irqs:		List of peripheral IRQ numbers handled.
 * @syswake_irq:	Shared PDC syswake IRQ number.
 * @domain:		IRQ domain for PDC peripheral and syswake IRQs.
 * @pdc_base:		Base of PDC registers.
 * @irq_route:		Cached version of PDC_IRQ_ROUTE register.
 * @lock:		Lock to protect the PDC syswake registers and the cached
 *			values of those registers in this struct.
 */
struct pdc_intc_priv {
	unsigned int		nr_perips;
	unsigned int		nr_syswakes;
	unsigned int		*perip_irqs;
	unsigned int		syswake_irq;
	struct irq_domain	*domain;
	void __iomem		*pdc_base;

	u32			irq_route;
	raw_spinlock_t		lock;
};

static void pdc_write(struct pdc_intc_priv *priv, unsigned int reg_offs,
		      unsigned int data)
{
	iowrite32(data, priv->pdc_base + reg_offs);
}

static unsigned int pdc_read(struct pdc_intc_priv *priv,
			     unsigned int reg_offs)
{
	return ioread32(priv->pdc_base + reg_offs);
}

/* Generic IRQ callbacks */

#define SYS0_HWIRQ	8

static unsigned int hwirq_is_syswake(irq_hw_number_t hw)
{
	return hw >= SYS0_HWIRQ;
}

static unsigned int hwirq_to_syswake(irq_hw_number_t hw)
{
	return hw - SYS0_HWIRQ;
}

static irq_hw_number_t syswake_to_hwirq(unsigned int syswake)
{
	return SYS0_HWIRQ + syswake;
}

static struct pdc_intc_priv *irqd_to_priv(struct irq_data *data)
{
	return (struct pdc_intc_priv *)data->domain->host_data;
}

/*
 * perip_irq_mask() and perip_irq_unmask() use IRQ_ROUTE which also contains
 * wake bits, therefore we cannot use the generic irqchip mask callbacks as they
 * cache the mask.
 */

static void perip_irq_mask(struct irq_data *data)
{
	struct pdc_intc_priv *priv = irqd_to_priv(data);

	raw_spin_lock(&priv->lock);
	priv->irq_route &= ~data->mask;
	pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
	raw_spin_unlock(&priv->lock);
}

static void perip_irq_unmask(struct irq_data *data)
{
	struct pdc_intc_priv *priv = irqd_to_priv(data);

	raw_spin_lock(&priv->lock);
	priv->irq_route |= data->mask;
	pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
	raw_spin_unlock(&priv->lock);
}

static int syswake_irq_set_type(struct irq_data *data, unsigned int flow_type)
{
	struct pdc_intc_priv *priv = irqd_to_priv(data);
	unsigned int syswake = hwirq_to_syswake(data->hwirq);
	unsigned int irq_mode;
	unsigned int soc_sys_wake_regoff, soc_sys_wake;

	/* translate to syswake IRQ mode */
	switch (flow_type) {
	case IRQ_TYPE_EDGE_BOTH:
		irq_mode = PDC_SYS_WAKE_INT_CHANGE;
		break;
	case IRQ_TYPE_EDGE_RISING:
		irq_mode = PDC_SYS_WAKE_INT_UP;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		irq_mode = PDC_SYS_WAKE_INT_DOWN;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		irq_mode = PDC_SYS_WAKE_INT_HIGH;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		irq_mode = PDC_SYS_WAKE_INT_LOW;
		break;
	default:
		return -EINVAL;
	}

	raw_spin_lock(&priv->lock);

	/* set the IRQ mode */
	soc_sys_wake_regoff = PDC_SYS_WAKE_BASE + syswake*PDC_SYS_WAKE_STRIDE;
	soc_sys_wake = pdc_read(priv, soc_sys_wake_regoff);
	soc_sys_wake &= ~PDC_SYS_WAKE_INT_MODE;
	soc_sys_wake |= irq_mode << PDC_SYS_WAKE_INT_MODE_SHIFT;
	pdc_write(priv, soc_sys_wake_regoff, soc_sys_wake);

	/* and update the handler */
	irq_setup_alt_chip(data, flow_type);

	raw_spin_unlock(&priv->lock);

	return 0;
}

/* applies to both peripheral and syswake interrupts */
static int pdc_irq_set_wake(struct irq_data *data, unsigned int on)
{
	struct pdc_intc_priv *priv = irqd_to_priv(data);
	irq_hw_number_t hw = data->hwirq;
	unsigned int mask = (1 << 16) << hw;
	unsigned int dst_irq;

	raw_spin_lock(&priv->lock);
	if (on)
		priv->irq_route |= mask;
	else
		priv->irq_route &= ~mask;
	pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
	raw_spin_unlock(&priv->lock);

	/* control the destination IRQ wakeup too for standby mode */
	if (hwirq_is_syswake(hw))
		dst_irq = priv->syswake_irq;
	else
		dst_irq = priv->perip_irqs[hw];
	irq_set_irq_wake(dst_irq, on);

	return 0;
}

static void pdc_intc_perip_isr(struct irq_desc *desc)
{
	unsigned int irq = irq_desc_get_irq(desc);
	struct pdc_intc_priv *priv;
	unsigned int i, irq_no;

	priv = (struct pdc_intc_priv *)irq_desc_get_handler_data(desc);

	/* find the peripheral number */
	for (i = 0; i < priv->nr_perips; ++i)
		if (irq == priv->perip_irqs[i])
			goto found;

	/* should never get here */
	return;
found:

	/* pass on the interrupt */
	irq_no = irq_linear_revmap(priv->domain, i);
	generic_handle_irq(irq_no);
}

static void pdc_intc_syswake_isr(struct irq_desc *desc)
{
	struct pdc_intc_priv *priv;
	unsigned int syswake, irq_no;
	unsigned int status;

	priv = (struct pdc_intc_priv *)irq_desc_get_handler_data(desc);

	status = pdc_read(priv, PDC_IRQ_STATUS) &
		 pdc_read(priv, PDC_IRQ_ENABLE);
	status &= (1 << priv->nr_syswakes) - 1;

	for (syswake = 0; status; status >>= 1, ++syswake) {
		/* Has this sys_wake triggered? */
		if (!(status & 1))
			continue;

		irq_no = irq_linear_revmap(priv->domain,
					   syswake_to_hwirq(syswake));
		generic_handle_irq(irq_no);
	}
}

static void pdc_intc_setup(struct pdc_intc_priv *priv)
{
	int i;
	unsigned int soc_sys_wake_regoff;
	unsigned int soc_sys_wake;

	/*
	 * Mask all syswake interrupts before routing, or we could receive an
	 * interrupt before we're ready to handle it.
	 */
	pdc_write(priv, PDC_IRQ_ENABLE, 0);

	/*
	 * Enable routing of all syswakes
	 * Disable all wake sources
	 */
	priv->irq_route = ((PDC_IRQ_ROUTE_EXT_EN_SYS0 << priv->nr_syswakes) -
				PDC_IRQ_ROUTE_EXT_EN_SYS0);
	pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);

	/* Initialise syswake IRQ */
	for (i = 0; i < priv->nr_syswakes; ++i) {
		/* set the IRQ mode to none */
		soc_sys_wake_regoff = PDC_SYS_WAKE_BASE + i*PDC_SYS_WAKE_STRIDE;
		soc_sys_wake = PDC_SYS_WAKE_INT_NONE
				<< PDC_SYS_WAKE_INT_MODE_SHIFT;
		pdc_write(priv, soc_sys_wake_regoff, soc_sys_wake);
	}
}

static int pdc_intc_probe(struct platform_device *pdev)
{
	struct pdc_intc_priv *priv;
	struct device_node *node = pdev->dev.of_node;
	struct resource *res_regs;
	struct irq_chip_generic *gc;
	unsigned int i;
	int irq, ret;
	u32 val;

	if (!node)
		return -ENOENT;

	/* Get registers */
	res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res_regs == NULL) {
		dev_err(&pdev->dev, "cannot find registers resource\n");
		return -ENOENT;
	}

	/* Allocate driver data */
	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		dev_err(&pdev->dev, "cannot allocate device data\n");
		return -ENOMEM;
	}
	raw_spin_lock_init(&priv->lock);
	platform_set_drvdata(pdev, priv);

	/* Ioremap the registers */
	priv->pdc_base = devm_ioremap(&pdev->dev, res_regs->start,
				      res_regs->end - res_regs->start);
	if (!priv->pdc_base)
		return -EIO;

	/* Get number of peripherals */
	ret = of_property_read_u32(node, "num-perips", &val);
	if (ret) {
		dev_err(&pdev->dev, "No num-perips node property found\n");
		return -EINVAL;
	}
	if (val > SYS0_HWIRQ) {
		dev_err(&pdev->dev, "num-perips (%u) out of range\n", val);
		return -EINVAL;
	}
	priv->nr_perips = val;

	/* Get number of syswakes */
	ret = of_property_read_u32(node, "num-syswakes", &val);
	if (ret) {
		dev_err(&pdev->dev, "No num-syswakes node property found\n");
		return -EINVAL;
	}
	if (val > SYS0_HWIRQ) {
		dev_err(&pdev->dev, "num-syswakes (%u) out of range\n", val);
		return -EINVAL;
	}
	priv->nr_syswakes = val;

	/* Get peripheral IRQ numbers */
	priv->perip_irqs = devm_kzalloc(&pdev->dev, 4 * priv->nr_perips,
					GFP_KERNEL);
	if (!priv->perip_irqs) {
		dev_err(&pdev->dev, "cannot allocate perip IRQ list\n");
		return -ENOMEM;
	}
	for (i = 0; i < priv->nr_perips; ++i) {
		irq = platform_get_irq(pdev, 1 + i);
		if (irq < 0) {
			dev_err(&pdev->dev, "cannot find perip IRQ #%u\n", i);
			return irq;
		}
		priv->perip_irqs[i] = irq;
	}
	/* check if too many were provided */
	if (platform_get_irq(pdev, 1 + i) >= 0) {
		dev_err(&pdev->dev, "surplus perip IRQs detected\n");
		return -EINVAL;
	}

	/* Get syswake IRQ number */
	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "cannot find syswake IRQ\n");
		return irq;
	}
	priv->syswake_irq = irq;

	/* Set up an IRQ domain */
	priv->domain = irq_domain_add_linear(node, 16, &irq_generic_chip_ops,
					     priv);
	if (unlikely(!priv->domain)) {
		dev_err(&pdev->dev, "cannot add IRQ domain\n");
		return -ENOMEM;
	}

	/*
	 * Set up 2 generic irq chips with 2 chip types.
	 * The first one for peripheral irqs (only 1 chip type used)
	 * The second one for syswake irqs (edge and level chip types)
	 */
	ret = irq_alloc_domain_generic_chips(priv->domain, 8, 2, "pdc",
					     handle_level_irq, 0, 0,
					     IRQ_GC_INIT_NESTED_LOCK);
	if (ret)
		goto err_generic;

	/* peripheral interrupt chip */

	gc = irq_get_domain_generic_chip(priv->domain, 0);
	gc->unused	= ~(BIT(priv->nr_perips) - 1);
	gc->reg_base	= priv->pdc_base;
	/*
	 * IRQ_ROUTE contains wake bits, so we can't use the generic versions as
	 * they cache the mask
	 */
	gc->chip_types[0].regs.mask		= PDC_IRQ_ROUTE;
	gc->chip_types[0].chip.irq_mask		= perip_irq_mask;
	gc->chip_types[0].chip.irq_unmask	= perip_irq_unmask;
	gc->chip_types[0].chip.irq_set_wake	= pdc_irq_set_wake;

	/* syswake interrupt chip */

	gc = irq_get_domain_generic_chip(priv->domain, 8);
	gc->unused	= ~(BIT(priv->nr_syswakes) - 1);
	gc->reg_base	= priv->pdc_base;

	/* edge interrupts */
	gc->chip_types[0].type			= IRQ_TYPE_EDGE_BOTH;
	gc->chip_types[0].handler		= handle_edge_irq;
	gc->chip_types[0].regs.ack		= PDC_IRQ_CLEAR;
	gc->chip_types[0].regs.mask		= PDC_IRQ_ENABLE;
	gc->chip_types[0].chip.irq_ack		= irq_gc_ack_set_bit;
	gc->chip_types[0].chip.irq_mask		= irq_gc_mask_clr_bit;
	gc->chip_types[0].chip.irq_unmask	= irq_gc_mask_set_bit;
	gc->chip_types[0].chip.irq_set_type	= syswake_irq_set_type;
	gc->chip_types[0].chip.irq_set_wake	= pdc_irq_set_wake;
	/* for standby we pass on to the shared syswake IRQ */
	gc->chip_types[0].chip.flags		= IRQCHIP_MASK_ON_SUSPEND;

	/* level interrupts */
	gc->chip_types[1].type			= IRQ_TYPE_LEVEL_MASK;
	gc->chip_types[1].handler		= handle_level_irq;
	gc->chip_types[1].regs.ack		= PDC_IRQ_CLEAR;
	gc->chip_types[1].regs.mask		= PDC_IRQ_ENABLE;
	gc->chip_types[1].chip.irq_ack		= irq_gc_ack_set_bit;
	gc->chip_types[1].chip.irq_mask		= irq_gc_mask_clr_bit;
	gc->chip_types[1].chip.irq_unmask	= irq_gc_mask_set_bit;
	gc->chip_types[1].chip.irq_set_type	= syswake_irq_set_type;
	gc->chip_types[1].chip.irq_set_wake	= pdc_irq_set_wake;
	/* for standby we pass on to the shared syswake IRQ */
	gc->chip_types[1].chip.flags		= IRQCHIP_MASK_ON_SUSPEND;

	/* Set up the hardware to enable interrupt routing */
	pdc_intc_setup(priv);

	/* Setup chained handlers for the peripheral IRQs */
	for (i = 0; i < priv->nr_perips; ++i) {
		irq = priv->perip_irqs[i];
		irq_set_chained_handler_and_data(irq, pdc_intc_perip_isr,
						 priv);
	}

	/* Setup chained handler for the syswake IRQ */
	irq_set_chained_handler_and_data(priv->syswake_irq,
					 pdc_intc_syswake_isr, priv);

	dev_info(&pdev->dev,
		 "PDC IRQ controller initialised (%u perip IRQs, %u syswake IRQs)\n",
		 priv->nr_perips,
		 priv->nr_syswakes);

	return 0;
err_generic:
	irq_domain_remove(priv->domain);
	return ret;
}

static int pdc_intc_remove(struct platform_device *pdev)
{
	struct pdc_intc_priv *priv = platform_get_drvdata(pdev);

	irq_domain_remove(priv->domain);
	return 0;
}

static const struct of_device_id pdc_intc_match[] = {
	{ .compatible = "img,pdc-intc" },
	{}
};

static struct platform_driver pdc_intc_driver = {
	.driver = {
		.name		= "pdc-intc",
		.of_match_table	= pdc_intc_match,
	},
	.probe = pdc_intc_probe,
	.remove = pdc_intc_remove,
};

static int __init pdc_intc_init(void)
{
	return platform_driver_register(&pdc_intc_driver);
}
core_initcall(pdc_intc_init);
Commit	Line	Data
b6ef9161 JH	1	/*
	2	* IMG PowerDown Controller (PDC)
	3	*
	4	* Copyright 2010-2013 Imagination Technologies Ltd.
	5	*
	6	* Exposes the syswake and PDC peripheral wake interrupts to the system.
	7	*
	8	*/
	9
	10	#include <linux/bitops.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/irqdomain.h>
	13	#include <linux/io.h>
	14	#include <linux/kernel.h>
	15	#include <linux/of.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/spinlock.h>
	18
	19	/* PDC interrupt register numbers */
	20
	21	#define PDC_IRQ_STATUS 0x310
	22	#define PDC_IRQ_ENABLE 0x314
	23	#define PDC_IRQ_CLEAR 0x318
	24	#define PDC_IRQ_ROUTE 0x31c
	25	#define PDC_SYS_WAKE_BASE 0x330
	26	#define PDC_SYS_WAKE_STRIDE 0x8
	27	#define PDC_SYS_WAKE_CONFIG_BASE 0x334
	28	#define PDC_SYS_WAKE_CONFIG_STRIDE 0x8
	29
	30	/* PDC interrupt register field masks */
	31
	32	#define PDC_IRQ_SYS3 0x08
	33	#define PDC_IRQ_SYS2 0x04
	34	#define PDC_IRQ_SYS1 0x02
	35	#define PDC_IRQ_SYS0 0x01
	36	#define PDC_IRQ_ROUTE_WU_EN_SYS3 0x08000000
	37	#define PDC_IRQ_ROUTE_WU_EN_SYS2 0x04000000
	38	#define PDC_IRQ_ROUTE_WU_EN_SYS1 0x02000000
	39	#define PDC_IRQ_ROUTE_WU_EN_SYS0 0x01000000
	40	#define PDC_IRQ_ROUTE_WU_EN_WD 0x00040000
	41	#define PDC_IRQ_ROUTE_WU_EN_IR 0x00020000
	42	#define PDC_IRQ_ROUTE_WU_EN_RTC 0x00010000
	43	#define PDC_IRQ_ROUTE_EXT_EN_SYS3 0x00000800
	44	#define PDC_IRQ_ROUTE_EXT_EN_SYS2 0x00000400
	45	#define PDC_IRQ_ROUTE_EXT_EN_SYS1 0x00000200
	46	#define PDC_IRQ_ROUTE_EXT_EN_SYS0 0x00000100
	47	#define PDC_IRQ_ROUTE_EXT_EN_WD 0x00000004
	48	#define PDC_IRQ_ROUTE_EXT_EN_IR 0x00000002
	49	#define PDC_IRQ_ROUTE_EXT_EN_RTC 0x00000001
	50	#define PDC_SYS_WAKE_RESET 0x00000010
	51	#define PDC_SYS_WAKE_INT_MODE 0x0000000e
	52	#define PDC_SYS_WAKE_INT_MODE_SHIFT 1
	53	#define PDC_SYS_WAKE_PIN_VAL 0x00000001
	54
	55	/* PDC interrupt constants */
	56
	57	#define PDC_SYS_WAKE_INT_LOW 0x0
	58	#define PDC_SYS_WAKE_INT_HIGH 0x1
	59	#define PDC_SYS_WAKE_INT_DOWN 0x2
	60	#define PDC_SYS_WAKE_INT_UP 0x3
	61	#define PDC_SYS_WAKE_INT_CHANGE 0x6
	62	#define PDC_SYS_WAKE_INT_NONE 0x4
	63
	64	/**
65	* struct pdc_intc_priv - private pdc interrupt data.
66	* @nr_perips: Number of peripheral interrupt signals.
67	* @nr_syswakes: Number of syswake signals.
68	* @perip_irqs: List of peripheral IRQ numbers handled.
69	* @syswake_irq: Shared PDC syswake IRQ number.
70	* @domain: IRQ domain for PDC peripheral and syswake IRQs.
71	* @pdc_base: Base of PDC registers.
72	* @irq_route: Cached version of PDC_IRQ_ROUTE register.
73	* @lock: Lock to protect the PDC syswake registers and the cached
74	* values of those registers in this struct.
75	*/
76	struct pdc_intc_priv {
77	unsigned int nr_perips;
78	unsigned int nr_syswakes;
79	unsigned int *perip_irqs;
80	unsigned int syswake_irq;
81	struct irq_domain *domain;
82	void __iomem *pdc_base;
83
84	u32 irq_route;
85	raw_spinlock_t lock;
86	};
87
88	static void pdc_write(struct pdc_intc_priv *priv, unsigned int reg_offs,
89	unsigned int data)
90	{
91	iowrite32(data, priv->pdc_base + reg_offs);
92	}
93
94	static unsigned int pdc_read(struct pdc_intc_priv *priv,
95	unsigned int reg_offs)
96	{
97	return ioread32(priv->pdc_base + reg_offs);
98	}
99
100	/* Generic IRQ callbacks */
101
102	#define SYS0_HWIRQ 8
103
104	static unsigned int hwirq_is_syswake(irq_hw_number_t hw)
105	{
106	return hw >= SYS0_HWIRQ;
107	}
108
109	static unsigned int hwirq_to_syswake(irq_hw_number_t hw)
110	{
111	return hw - SYS0_HWIRQ;
112	}
113
114	static irq_hw_number_t syswake_to_hwirq(unsigned int syswake)
115	{
116	return SYS0_HWIRQ + syswake;
117	}
118
119	static struct pdc_intc_priv irqd_to_priv(struct irq_data data)
120	{
121	return (struct pdc_intc_priv *)data->domain->host_data;
122	}
123
124	/*
125	* perip_irq_mask() and perip_irq_unmask() use IRQ_ROUTE which also contains
126	* wake bits, therefore we cannot use the generic irqchip mask callbacks as they
127	* cache the mask.
128	*/
129
130	static void perip_irq_mask(struct irq_data *data)
131	{
132	struct pdc_intc_priv *priv = irqd_to_priv(data);
133
134	raw_spin_lock(&priv->lock);
135	priv->irq_route &= ~data->mask;
136	pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
137	raw_spin_unlock(&priv->lock);
138	}
139
140	static void perip_irq_unmask(struct irq_data *data)
141	{
142	struct pdc_intc_priv *priv = irqd_to_priv(data);
143
144	raw_spin_lock(&priv->lock);
145	priv->irq_route \|= data->mask;
146	pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
147	raw_spin_unlock(&priv->lock);
148	}
149
150	static int syswake_irq_set_type(struct irq_data *data, unsigned int flow_type)
151	{
152	struct pdc_intc_priv *priv = irqd_to_priv(data);
153	unsigned int syswake = hwirq_to_syswake(data->hwirq);
154	unsigned int irq_mode;
155	unsigned int soc_sys_wake_regoff, soc_sys_wake;
156
157	/* translate to syswake IRQ mode */
158	switch (flow_type) {
159	case IRQ_TYPE_EDGE_BOTH:
160	irq_mode = PDC_SYS_WAKE_INT_CHANGE;
161	break;
162	case IRQ_TYPE_EDGE_RISING:
163	irq_mode = PDC_SYS_WAKE_INT_UP;
164	break;
165	case IRQ_TYPE_EDGE_FALLING:
166	irq_mode = PDC_SYS_WAKE_INT_DOWN;
167	break;
168	case IRQ_TYPE_LEVEL_HIGH:
169	irq_mode = PDC_SYS_WAKE_INT_HIGH;
170	break;
171	case IRQ_TYPE_LEVEL_LOW:
172	irq_mode = PDC_SYS_WAKE_INT_LOW;
173	break;
174	default:
175	return -EINVAL;
176	}
177
178	raw_spin_lock(&priv->lock);
179
180	/* set the IRQ mode */
181	soc_sys_wake_regoff = PDC_SYS_WAKE_BASE + syswake*PDC_SYS_WAKE_STRIDE;
182	soc_sys_wake = pdc_read(priv, soc_sys_wake_regoff);
183	soc_sys_wake &= ~PDC_SYS_WAKE_INT_MODE;
184	soc_sys_wake \|= irq_mode << PDC_SYS_WAKE_INT_MODE_SHIFT;
185	pdc_write(priv, soc_sys_wake_regoff, soc_sys_wake);
186
187	/* and update the handler */
188	irq_setup_alt_chip(data, flow_type);
189
190	raw_spin_unlock(&priv->lock);
191
192	return 0;
193	}
194
195	/* applies to both peripheral and syswake interrupts */
196	static int pdc_irq_set_wake(struct irq_data *data, unsigned int on)
197	{
198	struct pdc_intc_priv *priv = irqd_to_priv(data);
199	irq_hw_number_t hw = data->hwirq;
200	unsigned int mask = (1 << 16) << hw;
201	unsigned int dst_irq;
202
203	raw_spin_lock(&priv->lock);
204	if (on)
205	priv->irq_route \|= mask;
206	else
207	priv->irq_route &= ~mask;
208	pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
209	raw_spin_unlock(&priv->lock);
210
211	/* control the destination IRQ wakeup too for standby mode */
212	if (hwirq_is_syswake(hw))
213	dst_irq = priv->syswake_irq;
214	else
215	dst_irq = priv->perip_irqs[hw];
216	irq_set_irq_wake(dst_irq, on);
217
218	return 0;
219	}
220
bd0b9ac4	221	static void pdc_intc_perip_isr(struct irq_desc *desc)
b6ef9161	222	{
99705f99	223	unsigned int irq = irq_desc_get_irq(desc);
b6ef9161 JH	224	struct pdc_intc_priv *priv;
	225	unsigned int i, irq_no;
	226
	227	priv = (struct pdc_intc_priv *)irq_desc_get_handler_data(desc);
	228
	229	/* find the peripheral number */
	230	for (i = 0; i < priv->nr_perips; ++i)
	231	if (irq == priv->perip_irqs[i])
	232	goto found;
	233
	234	/* should never get here */
	235	return;
	236	found:
	237
	238	/* pass on the interrupt */
	239	irq_no = irq_linear_revmap(priv->domain, i);
	240	generic_handle_irq(irq_no);
	241	}
	242
bd0b9ac4	243	static void pdc_intc_syswake_isr(struct irq_desc *desc)
b6ef9161 JH	244	{
	245	struct pdc_intc_priv *priv;
	246	unsigned int syswake, irq_no;
	247	unsigned int status;
	248
	249	priv = (struct pdc_intc_priv *)irq_desc_get_handler_data(desc);
	250
	251	status = pdc_read(priv, PDC_IRQ_STATUS) &
	252	pdc_read(priv, PDC_IRQ_ENABLE);
	253	status &= (1 << priv->nr_syswakes) - 1;
	254
	255	for (syswake = 0; status; status >>= 1, ++syswake) {
	256	/* Has this sys_wake triggered? */
	257	if (!(status & 1))
	258	continue;
	259
	260	irq_no = irq_linear_revmap(priv->domain,
	261	syswake_to_hwirq(syswake));
	262	generic_handle_irq(irq_no);
	263	}
	264	}
	265
	266	static void pdc_intc_setup(struct pdc_intc_priv *priv)
	267	{
	268	int i;
	269	unsigned int soc_sys_wake_regoff;
	270	unsigned int soc_sys_wake;
	271
	272	/*
	273	* Mask all syswake interrupts before routing, or we could receive an
	274	* interrupt before we're ready to handle it.
	275	*/
	276	pdc_write(priv, PDC_IRQ_ENABLE, 0);
	277
	278	/*
	279	* Enable routing of all syswakes
	280	* Disable all wake sources
	281	*/
	282	priv->irq_route = ((PDC_IRQ_ROUTE_EXT_EN_SYS0 << priv->nr_syswakes) -
	283	PDC_IRQ_ROUTE_EXT_EN_SYS0);
	284	pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
	285
	286	/* Initialise syswake IRQ */
	287	for (i = 0; i < priv->nr_syswakes; ++i) {
	288	/* set the IRQ mode to none */
	289	soc_sys_wake_regoff = PDC_SYS_WAKE_BASE + i*PDC_SYS_WAKE_STRIDE;
	290	soc_sys_wake = PDC_SYS_WAKE_INT_NONE
	291	<< PDC_SYS_WAKE_INT_MODE_SHIFT;
	292	pdc_write(priv, soc_sys_wake_regoff, soc_sys_wake);
	293	}
	294	}
	295
	296	static int pdc_intc_probe(struct platform_device *pdev)
	297	{
	298	struct pdc_intc_priv *priv;
	299	struct device_node *node = pdev->dev.of_node;
	300	struct resource *res_regs;
	301	struct irq_chip_generic *gc;
	302	unsigned int i;
	303	int irq, ret;
	304	u32 val;
	305
	306	if (!node)
	307	return -ENOENT;
308
309	/* Get registers */
310	res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
311	if (res_regs == NULL) {
312	dev_err(&pdev->dev, "cannot find registers resource\n");
313	return -ENOENT;
314	}
315
316	/* Allocate driver data */
317	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
318	if (!priv) {
319	dev_err(&pdev->dev, "cannot allocate device data\n");
320	return -ENOMEM;
321	}
322	raw_spin_lock_init(&priv->lock);
323	platform_set_drvdata(pdev, priv);
324
325	/* Ioremap the registers */
326	priv->pdc_base = devm_ioremap(&pdev->dev, res_regs->start,
327	res_regs->end - res_regs->start);
328	if (!priv->pdc_base)
329	return -EIO;
330
331	/* Get number of peripherals */
332	ret = of_property_read_u32(node, "num-perips", &val);
333	if (ret) {
334	dev_err(&pdev->dev, "No num-perips node property found\n");
335	return -EINVAL;
336	}
337	if (val > SYS0_HWIRQ) {
338	dev_err(&pdev->dev, "num-perips (%u) out of range\n", val);
339	return -EINVAL;
340	}
341	priv->nr_perips = val;
342
343	/* Get number of syswakes */
344	ret = of_property_read_u32(node, "num-syswakes", &val);
345	if (ret) {
346	dev_err(&pdev->dev, "No num-syswakes node property found\n");
347	return -EINVAL;
348	}
349	if (val > SYS0_HWIRQ) {
350	dev_err(&pdev->dev, "num-syswakes (%u) out of range\n", val);
351	return -EINVAL;
352	}
353	priv->nr_syswakes = val;
354
355	/* Get peripheral IRQ numbers */
356	priv->perip_irqs = devm_kzalloc(&pdev->dev, 4 * priv->nr_perips,
357	GFP_KERNEL);
358	if (!priv->perip_irqs) {
359	dev_err(&pdev->dev, "cannot allocate perip IRQ list\n");
360	return -ENOMEM;
361	}
362	for (i = 0; i < priv->nr_perips; ++i) {
363	irq = platform_get_irq(pdev, 1 + i);
364	if (irq < 0) {
365	dev_err(&pdev->dev, "cannot find perip IRQ #%u\n", i);
366	return irq;
367	}
368	priv->perip_irqs[i] = irq;
369	}
370	/* check if too many were provided */
371	if (platform_get_irq(pdev, 1 + i) >= 0) {
372	dev_err(&pdev->dev, "surplus perip IRQs detected\n");
373	return -EINVAL;
374	}
375
376	/* Get syswake IRQ number */
377	irq = platform_get_irq(pdev, 0);
378	if (irq < 0) {
379	dev_err(&pdev->dev, "cannot find syswake IRQ\n");
380	return irq;
381	}
382	priv->syswake_irq = irq;
383
384	/* Set up an IRQ domain */
385	priv->domain = irq_domain_add_linear(node, 16, &irq_generic_chip_ops,
386	priv);
387	if (unlikely(!priv->domain)) {
388	dev_err(&pdev->dev, "cannot add IRQ domain\n");
389	return -ENOMEM;
390	}
391
392	/*
393	* Set up 2 generic irq chips with 2 chip types.
394	* The first one for peripheral irqs (only 1 chip type used)
395	* The second one for syswake irqs (edge and level chip types)
396	*/
397	ret = irq_alloc_domain_generic_chips(priv->domain, 8, 2, "pdc",
398	handle_level_irq, 0, 0,
399	IRQ_GC_INIT_NESTED_LOCK);
400	if (ret)
401	goto err_generic;
402
403	/* peripheral interrupt chip */
404
405	gc = irq_get_domain_generic_chip(priv->domain, 0);
406	gc->unused = ~(BIT(priv->nr_perips) - 1);
407	gc->reg_base = priv->pdc_base;
408	/*
409	* IRQ_ROUTE contains wake bits, so we can't use the generic versions as
410	* they cache the mask
411	*/
412	gc->chip_types[0].regs.mask = PDC_IRQ_ROUTE;
413	gc->chip_types[0].chip.irq_mask = perip_irq_mask;
414	gc->chip_types[0].chip.irq_unmask = perip_irq_unmask;
415	gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake;
416
417	/* syswake interrupt chip */
418
419	gc = irq_get_domain_generic_chip(priv->domain, 8);
420	gc->unused = ~(BIT(priv->nr_syswakes) - 1);
421	gc->reg_base = priv->pdc_base;
422
423	/* edge interrupts */
424	gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
425	gc->chip_types[0].handler = handle_edge_irq;
426	gc->chip_types[0].regs.ack = PDC_IRQ_CLEAR;
427	gc->chip_types[0].regs.mask = PDC_IRQ_ENABLE;
428	gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
429	gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
430	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
431	gc->chip_types[0].chip.irq_set_type = syswake_irq_set_type;
432	gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake;
433	/* for standby we pass on to the shared syswake IRQ */
434	gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
435
436	/* level interrupts */
437	gc->chip_types[1].type = IRQ_TYPE_LEVEL_MASK;
438	gc->chip_types[1].handler = handle_level_irq;
439	gc->chip_types[1].regs.ack = PDC_IRQ_CLEAR;
440	gc->chip_types[1].regs.mask = PDC_IRQ_ENABLE;
441	gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
442	gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
443	gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
444	gc->chip_types[1].chip.irq_set_type = syswake_irq_set_type;
445	gc->chip_types[1].chip.irq_set_wake = pdc_irq_set_wake;
446	/* for standby we pass on to the shared syswake IRQ */
447	gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
448
449	/* Set up the hardware to enable interrupt routing */
450	pdc_intc_setup(priv);
451
452	/* Setup chained handlers for the peripheral IRQs */
453	for (i = 0; i < priv->nr_perips; ++i) {
454	irq = priv->perip_irqs[i];
bc4d2c07 TG	455	irq_set_chained_handler_and_data(irq, pdc_intc_perip_isr,
bc4d2c07 TG	456	priv);
b6ef9161 JH	457	}
	458
	459	/* Setup chained handler for the syswake IRQ */
bc4d2c07 TG	460	irq_set_chained_handler_and_data(priv->syswake_irq,
bc4d2c07 TG	461	pdc_intc_syswake_isr, priv);
b6ef9161 JH	462
	463	dev_info(&pdev->dev,
	464	"PDC IRQ controller initialised (%u perip IRQs, %u syswake IRQs)\n",
	465	priv->nr_perips,
	466	priv->nr_syswakes);
	467
	468	return 0;
	469	err_generic:
	470	irq_domain_remove(priv->domain);
	471	return ret;
	472	}
	473
	474	static int pdc_intc_remove(struct platform_device *pdev)
	475	{
	476	struct pdc_intc_priv *priv = platform_get_drvdata(pdev);
	477
	478	irq_domain_remove(priv->domain);
	479	return 0;
	480	}
	481
	482	static const struct of_device_id pdc_intc_match[] = {
	483	{ .compatible = "img,pdc-intc" },
	484	{}
	485	};
	486
	487	static struct platform_driver pdc_intc_driver = {
	488	.driver = {
	489	.name = "pdc-intc",
	490	.of_match_table = pdc_intc_match,
	491	},
	492	.probe = pdc_intc_probe,
	493	.remove = pdc_intc_remove,
	494	};
	495
	496	static int __init pdc_intc_init(void)
	497	{
	498	return platform_driver_register(&pdc_intc_driver);
	499	}
	500	core_initcall(pdc_intc_init);