[linux-2.6-block.git] / drivers / irqchip / irq-gic-v2m.c

/*
 * ARM GIC v2m MSI(-X) support
 * Support for Message Signaled Interrupts for systems that
 * implement ARM Generic Interrupt Controller: GICv2m.
 *
 * Copyright (C) 2014 Advanced Micro Devices, Inc.
 * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
 *	    Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
 *	    Brandon Anderson <brandon.anderson@amd.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#define pr_fmt(fmt) "GICv2m: " fmt

#include <linux/acpi.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/msi.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

/*
* MSI_TYPER:
*     [31:26] Reserved
*     [25:16] lowest SPI assigned to MSI
*     [15:10] Reserved
*     [9:0]   Numer of SPIs assigned to MSI
*/
#define V2M_MSI_TYPER		       0x008
#define V2M_MSI_TYPER_BASE_SHIFT       16
#define V2M_MSI_TYPER_BASE_MASK	       0x3FF
#define V2M_MSI_TYPER_NUM_MASK	       0x3FF
#define V2M_MSI_SETSPI_NS	       0x040
#define V2M_MIN_SPI		       32
#define V2M_MAX_SPI		       1019
#define V2M_MSI_IIDR		       0xFCC

#define V2M_MSI_TYPER_BASE_SPI(x)      \
	       (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)

#define V2M_MSI_TYPER_NUM_SPI(x)       ((x) & V2M_MSI_TYPER_NUM_MASK)

/* APM X-Gene with GICv2m MSI_IIDR register value */
#define XGENE_GICV2M_MSI_IIDR		0x06000170

/* List of flags for specific v2m implementation */
#define GICV2M_NEEDS_SPI_OFFSET		0x00000001

static LIST_HEAD(v2m_nodes);
static DEFINE_SPINLOCK(v2m_lock);

struct v2m_data {
	struct list_head entry;
	struct fwnode_handle *fwnode;
	struct resource res;	/* GICv2m resource */
	void __iomem *base;	/* GICv2m virt address */
	u32 spi_start;		/* The SPI number that MSIs start */
	u32 nr_spis;		/* The number of SPIs for MSIs */
	unsigned long *bm;	/* MSI vector bitmap */
	u32 flags;		/* v2m flags for specific implementation */
};

static void gicv2m_mask_msi_irq(struct irq_data *d)
{
	pci_msi_mask_irq(d);
	irq_chip_mask_parent(d);
}

static void gicv2m_unmask_msi_irq(struct irq_data *d)
{
	pci_msi_unmask_irq(d);
	irq_chip_unmask_parent(d);
}

static struct irq_chip gicv2m_msi_irq_chip = {
	.name			= "MSI",
	.irq_mask		= gicv2m_mask_msi_irq,
	.irq_unmask		= gicv2m_unmask_msi_irq,
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_write_msi_msg	= pci_msi_domain_write_msg,
};

static struct msi_domain_info gicv2m_msi_domain_info = {
	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
		   MSI_FLAG_PCI_MSIX),
	.chip	= &gicv2m_msi_irq_chip,
};

static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
{
	struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
	phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;

	msg->address_hi = upper_32_bits(addr);
	msg->address_lo = lower_32_bits(addr);
	msg->data = data->hwirq;

	if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
		msg->data -= v2m->spi_start;
}

static struct irq_chip gicv2m_irq_chip = {
	.name			= "GICv2m",
	.irq_mask		= irq_chip_mask_parent,
	.irq_unmask		= irq_chip_unmask_parent,
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_set_affinity	= irq_chip_set_affinity_parent,
	.irq_compose_msi_msg	= gicv2m_compose_msi_msg,
};

static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
				       unsigned int virq,
				       irq_hw_number_t hwirq)
{
	struct irq_fwspec fwspec;
	struct irq_data *d;
	int err;

	if (is_of_node(domain->parent->fwnode)) {
		fwspec.fwnode = domain->parent->fwnode;
		fwspec.param_count = 3;
		fwspec.param[0] = 0;
		fwspec.param[1] = hwirq - 32;
		fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {
		fwspec.fwnode = domain->parent->fwnode;
		fwspec.param_count = 2;
		fwspec.param[0] = hwirq;
		fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
	} else {
		return -EINVAL;
	}

	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
	if (err)
		return err;

	/* Configure the interrupt line to be edge */
	d = irq_domain_get_irq_data(domain->parent, virq);
	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
	return 0;
}

static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq)
{
	int pos;

	pos = hwirq - v2m->spi_start;
	if (pos < 0 || pos >= v2m->nr_spis) {
		pr_err("Failed to teardown msi. Invalid hwirq %d\n", hwirq);
		return;
	}

	spin_lock(&v2m_lock);
	__clear_bit(pos, v2m->bm);
	spin_unlock(&v2m_lock);
}

static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				   unsigned int nr_irqs, void *args)
{
	struct v2m_data *v2m = NULL, *tmp;
	int hwirq, offset, err = 0;

	spin_lock(&v2m_lock);
	list_for_each_entry(tmp, &v2m_nodes, entry) {
		offset = find_first_zero_bit(tmp->bm, tmp->nr_spis);
		if (offset < tmp->nr_spis) {
			__set_bit(offset, tmp->bm);
			v2m = tmp;
			break;
		}
	}
	spin_unlock(&v2m_lock);

	if (!v2m)
		return -ENOSPC;

	hwirq = v2m->spi_start + offset;

	err = gicv2m_irq_gic_domain_alloc(domain, virq, hwirq);
	if (err) {
		gicv2m_unalloc_msi(v2m, hwirq);
		return err;
	}

	irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
				      &gicv2m_irq_chip, v2m);

	return 0;
}

static void gicv2m_irq_domain_free(struct irq_domain *domain,
				   unsigned int virq, unsigned int nr_irqs)
{
	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
	struct v2m_data *v2m = irq_data_get_irq_chip_data(d);

	BUG_ON(nr_irqs != 1);
	gicv2m_unalloc_msi(v2m, d->hwirq);
	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
}

static const struct irq_domain_ops gicv2m_domain_ops = {
	.alloc			= gicv2m_irq_domain_alloc,
	.free			= gicv2m_irq_domain_free,
};

static bool is_msi_spi_valid(u32 base, u32 num)
{
	if (base < V2M_MIN_SPI) {
		pr_err("Invalid MSI base SPI (base:%u)\n", base);
		return false;
	}

	if ((num == 0) || (base + num > V2M_MAX_SPI)) {
		pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
		       num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
		return false;
	}

	return true;
}

static struct irq_chip gicv2m_pmsi_irq_chip = {
	.name			= "pMSI",
};

static struct msi_domain_ops gicv2m_pmsi_ops = {
};

static struct msi_domain_info gicv2m_pmsi_domain_info = {
	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
	.ops	= &gicv2m_pmsi_ops,
	.chip	= &gicv2m_pmsi_irq_chip,
};

static void gicv2m_teardown(void)
{
	struct v2m_data *v2m, *tmp;

	list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
		list_del(&v2m->entry);
		kfree(v2m->bm);
		iounmap(v2m->base);
		of_node_put(to_of_node(v2m->fwnode));
		if (is_fwnode_irqchip(v2m->fwnode))
			irq_domain_free_fwnode(v2m->fwnode);
		kfree(v2m);
	}
}

static int gicv2m_allocate_domains(struct irq_domain *parent)
{
	struct irq_domain *inner_domain, *pci_domain, *plat_domain;
	struct v2m_data *v2m;

	v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
	if (!v2m)
		return 0;

	inner_domain = irq_domain_create_tree(v2m->fwnode,
					      &gicv2m_domain_ops, v2m);
	if (!inner_domain) {
		pr_err("Failed to create GICv2m domain\n");
		return -ENOMEM;
	}

	inner_domain->bus_token = DOMAIN_BUS_NEXUS;
	inner_domain->parent = parent;
	pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
					       &gicv2m_msi_domain_info,
					       inner_domain);
	plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
						     &gicv2m_pmsi_domain_info,
						     inner_domain);
	if (!pci_domain || !plat_domain) {
		pr_err("Failed to create MSI domains\n");
		if (plat_domain)
			irq_domain_remove(plat_domain);
		if (pci_domain)
			irq_domain_remove(pci_domain);
		irq_domain_remove(inner_domain);
		return -ENOMEM;
	}

	return 0;
}

static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
				  u32 spi_start, u32 nr_spis,
				  struct resource *res)
{
	int ret;
	struct v2m_data *v2m;

	v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
	if (!v2m) {
		pr_err("Failed to allocate struct v2m_data.\n");
		return -ENOMEM;
	}

	INIT_LIST_HEAD(&v2m->entry);
	v2m->fwnode = fwnode;

	memcpy(&v2m->res, res, sizeof(struct resource));

	v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
	if (!v2m->base) {
		pr_err("Failed to map GICv2m resource\n");
		ret = -ENOMEM;
		goto err_free_v2m;
	}

	if (spi_start && nr_spis) {
		v2m->spi_start = spi_start;
		v2m->nr_spis = nr_spis;
	} else {
		u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);

		v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
		v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
	}

	if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
		ret = -EINVAL;
		goto err_iounmap;
	}

	/*
	 * APM X-Gene GICv2m implementation has an erratum where
	 * the MSI data needs to be the offset from the spi_start
	 * in order to trigger the correct MSI interrupt. This is
	 * different from the standard GICv2m implementation where
	 * the MSI data is the absolute value within the range from
	 * spi_start to (spi_start + num_spis).
	 */
	if (readl_relaxed(v2m->base + V2M_MSI_IIDR) == XGENE_GICV2M_MSI_IIDR)
		v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;

	v2m->bm = kzalloc(sizeof(long) * BITS_TO_LONGS(v2m->nr_spis),
			  GFP_KERNEL);
	if (!v2m->bm) {
		ret = -ENOMEM;
		goto err_iounmap;
	}

	list_add_tail(&v2m->entry, &v2m_nodes);

	pr_info("range%pR, SPI[%d:%d]\n", res,
		v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
	return 0;

err_iounmap:
	iounmap(v2m->base);
err_free_v2m:
	kfree(v2m);
	return ret;
}

static struct of_device_id gicv2m_device_id[] = {
	{	.compatible	= "arm,gic-v2m-frame",	},
	{},
};

static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
				 struct irq_domain *parent)
{
	int ret = 0;
	struct device_node *node = to_of_node(parent_handle);
	struct device_node *child;

	for (child = of_find_matching_node(node, gicv2m_device_id); child;
	     child = of_find_matching_node(child, gicv2m_device_id)) {
		u32 spi_start = 0, nr_spis = 0;
		struct resource res;

		if (!of_find_property(child, "msi-controller", NULL))
			continue;

		ret = of_address_to_resource(child, 0, &res);
		if (ret) {
			pr_err("Failed to allocate v2m resource.\n");
			break;
		}

		if (!of_property_read_u32(child, "arm,msi-base-spi",
					  &spi_start) &&
		    !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
			pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
				spi_start, nr_spis);

		ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res);
		if (ret) {
			of_node_put(child);
			break;
		}
	}

	if (!ret)
		ret = gicv2m_allocate_domains(parent);
	if (ret)
		gicv2m_teardown();
	return ret;
}

#ifdef CONFIG_ACPI
static int acpi_num_msi;

static struct fwnode_handle *gicv2m_get_fwnode(struct device *dev)
{
	struct v2m_data *data;

	if (WARN_ON(acpi_num_msi <= 0))
		return NULL;

	/* We only return the fwnode of the first MSI frame. */
	data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
	if (!data)
		return NULL;

	return data->fwnode;
}

static int __init
acpi_parse_madt_msi(struct acpi_subtable_header *header,
		    const unsigned long end)
{
	int ret;
	struct resource res;
	u32 spi_start = 0, nr_spis = 0;
	struct acpi_madt_generic_msi_frame *m;
	struct fwnode_handle *fwnode;

	m = (struct acpi_madt_generic_msi_frame *)header;
	if (BAD_MADT_ENTRY(m, end))
		return -EINVAL;

	res.start = m->base_address;
	res.end = m->base_address + SZ_4K - 1;
	res.flags = IORESOURCE_MEM;

	if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
		spi_start = m->spi_base;
		nr_spis = m->spi_count;

		pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
			spi_start, nr_spis);
	}

	fwnode = irq_domain_alloc_fwnode((void *)m->base_address);
	if (!fwnode) {
		pr_err("Unable to allocate GICv2m domain token\n");
		return -EINVAL;
	}

	ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res);
	if (ret)
		irq_domain_free_fwnode(fwnode);

	return ret;
}

static int __init gicv2m_acpi_init(struct irq_domain *parent)
{
	int ret;

	if (acpi_num_msi > 0)
		return 0;

	acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
				      acpi_parse_madt_msi, 0);

	if (acpi_num_msi <= 0)
		goto err_out;

	ret = gicv2m_allocate_domains(parent);
	if (ret)
		goto err_out;

	pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);

	return 0;

err_out:
	gicv2m_teardown();
	return -EINVAL;
}
#else /* CONFIG_ACPI */
static int __init gicv2m_acpi_init(struct irq_domain *parent)
{
	return -EINVAL;
}
#endif /* CONFIG_ACPI */

int __init gicv2m_init(struct fwnode_handle *parent_handle,
		       struct irq_domain *parent)
{
	if (is_of_node(parent_handle))
		return gicv2m_of_init(parent_handle, parent);

	return gicv2m_acpi_init(parent);
}
Commit	Line	Data
853a33ce SS	1	/*
	2	* ARM GIC v2m MSI(-X) support
	3	* Support for Message Signaled Interrupts for systems that
	4	* implement ARM Generic Interrupt Controller: GICv2m.
	5	*
	6	* Copyright (C) 2014 Advanced Micro Devices, Inc.
	7	* Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
	8	* Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
	9	* Brandon Anderson <brandon.anderson@amd.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License version 2 as published
	13	* by the Free Software Foundation.
	14	*/
	15
	16	#define pr_fmt(fmt) "GICv2m: " fmt
	17
0644b3da	18	#include <linux/acpi.h>
853a33ce SS	19	#include <linux/irq.h>
	20	#include <linux/irqdomain.h>
	21	#include <linux/kernel.h>
0644b3da	22	#include <linux/msi.h>
853a33ce SS	23	#include <linux/of_address.h>
	24	#include <linux/of_pci.h>
	25	#include <linux/slab.h>
	26	#include <linux/spinlock.h>
	27
	28	/*
	29	* MSI_TYPER:
	30	* [31:26] Reserved
	31	* [25:16] lowest SPI assigned to MSI
	32	* [15:10] Reserved
	33	* [9:0] Numer of SPIs assigned to MSI
	34	*/
	35	#define V2M_MSI_TYPER 0x008
	36	#define V2M_MSI_TYPER_BASE_SHIFT 16
	37	#define V2M_MSI_TYPER_BASE_MASK 0x3FF
	38	#define V2M_MSI_TYPER_NUM_MASK 0x3FF
	39	#define V2M_MSI_SETSPI_NS 0x040
	40	#define V2M_MIN_SPI 32
	41	#define V2M_MAX_SPI 1019
ee5f7d64	42	#define V2M_MSI_IIDR 0xFCC
853a33ce SS	43
	44	#define V2M_MSI_TYPER_BASE_SPI(x) \
	45	(((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
	46
	47	#define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK)
	48
ee5f7d64 DD	49	/* APM X-Gene with GICv2m MSI_IIDR register value */
	50	#define XGENE_GICV2M_MSI_IIDR 0x06000170
	51
	52	/* List of flags for specific v2m implementation */
	53	#define GICV2M_NEEDS_SPI_OFFSET 0x00000001
	54
a71225e2 MZ	55	static LIST_HEAD(v2m_nodes);
	56	static DEFINE_SPINLOCK(v2m_lock);
	57
853a33ce	58	struct v2m_data {
a71225e2	59	struct list_head entry;
4266ab1a	60	struct fwnode_handle *fwnode;
853a33ce SS	61	struct resource res; /* GICv2m resource */
	62	void __iomem base; / GICv2m virt address */
	63	u32 spi_start; /* The SPI number that MSIs start */
	64	u32 nr_spis; /* The number of SPIs for MSIs */
	65	unsigned long bm; / MSI vector bitmap */
ee5f7d64	66	u32 flags; /* v2m flags for specific implementation */
853a33ce SS	67	};
	68
	69	static void gicv2m_mask_msi_irq(struct irq_data *d)
	70	{
	71	pci_msi_mask_irq(d);
	72	irq_chip_mask_parent(d);
	73	}
	74
	75	static void gicv2m_unmask_msi_irq(struct irq_data *d)
	76	{
	77	pci_msi_unmask_irq(d);
	78	irq_chip_unmask_parent(d);
	79	}
	80
	81	static struct irq_chip gicv2m_msi_irq_chip = {
	82	.name = "MSI",
	83	.irq_mask = gicv2m_mask_msi_irq,
	84	.irq_unmask = gicv2m_unmask_msi_irq,
	85	.irq_eoi = irq_chip_eoi_parent,
	86	.irq_write_msi_msg = pci_msi_domain_write_msg,
	87	};
	88
	89	static struct msi_domain_info gicv2m_msi_domain_info = {
	90	.flags = (MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS \|
	91	MSI_FLAG_PCI_MSIX),
	92	.chip = &gicv2m_msi_irq_chip,
	93	};
	94
853a33ce SS	95	static void gicv2m_compose_msi_msg(struct irq_data data, struct msi_msg msg)
	96	{
	97	struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
	98	phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;
	99
157add60 PF	100	msg->address_hi = upper_32_bits(addr);
157add60 PF	101	msg->address_lo = lower_32_bits(addr);
853a33ce	102	msg->data = data->hwirq;
ee5f7d64 DD	103
	104	if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
	105	msg->data -= v2m->spi_start;
853a33ce SS	106	}
	107
	108	static struct irq_chip gicv2m_irq_chip = {
	109	.name = "GICv2m",
	110	.irq_mask = irq_chip_mask_parent,
	111	.irq_unmask = irq_chip_unmask_parent,
	112	.irq_eoi = irq_chip_eoi_parent,
0407dace	113	.irq_set_affinity = irq_chip_set_affinity_parent,
853a33ce SS	114	.irq_compose_msi_msg = gicv2m_compose_msi_msg,
	115	};
	116
	117	static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
	118	unsigned int virq,
	119	irq_hw_number_t hwirq)
	120	{
f833f57f	121	struct irq_fwspec fwspec;
853a33ce SS	122	struct irq_data *d;
	123	int err;
	124
f833f57f MZ	125	if (is_of_node(domain->parent->fwnode)) {
	126	fwspec.fwnode = domain->parent->fwnode;
	127	fwspec.param_count = 3;
	128	fwspec.param[0] = 0;
	129	fwspec.param[1] = hwirq - 32;
	130	fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
0644b3da SS	131	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {
	132	fwspec.fwnode = domain->parent->fwnode;
	133	fwspec.param_count = 2;
	134	fwspec.param[0] = hwirq;
	135	fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
f833f57f MZ	136	} else {
	137	return -EINVAL;
	138	}
853a33ce	139
f833f57f	140	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
853a33ce SS	141	if (err)
	142	return err;
	143
	144	/* Configure the interrupt line to be edge */
	145	d = irq_domain_get_irq_data(domain->parent, virq);
	146	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
	147	return 0;
	148	}
	149
	150	static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq)
	151	{
	152	int pos;
	153
	154	pos = hwirq - v2m->spi_start;
	155	if (pos < 0 \|\| pos >= v2m->nr_spis) {
	156	pr_err("Failed to teardown msi. Invalid hwirq %d\n", hwirq);
	157	return;
	158	}
	159
a71225e2	160	spin_lock(&v2m_lock);
853a33ce	161	__clear_bit(pos, v2m->bm);
a71225e2	162	spin_unlock(&v2m_lock);
853a33ce SS	163	}
	164
	165	static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
	166	unsigned int nr_irqs, void *args)
	167	{
a71225e2	168	struct v2m_data v2m = NULL, tmp;
853a33ce SS	169	int hwirq, offset, err = 0;
853a33ce SS	170
a71225e2 MZ	171	spin_lock(&v2m_lock);
	172	list_for_each_entry(tmp, &v2m_nodes, entry) {
	173	offset = find_first_zero_bit(tmp->bm, tmp->nr_spis);
	174	if (offset < tmp->nr_spis) {
	175	__set_bit(offset, tmp->bm);
	176	v2m = tmp;
	177	break;
	178	}
	179	}
	180	spin_unlock(&v2m_lock);
853a33ce	181
a71225e2 MZ	182	if (!v2m)
a71225e2 MZ	183	return -ENOSPC;
853a33ce SS	184
	185	hwirq = v2m->spi_start + offset;
	186
	187	err = gicv2m_irq_gic_domain_alloc(domain, virq, hwirq);
	188	if (err) {
	189	gicv2m_unalloc_msi(v2m, hwirq);
	190	return err;
	191	}
	192
	193	irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
	194	&gicv2m_irq_chip, v2m);
	195
	196	return 0;
	197	}
	198
	199	static void gicv2m_irq_domain_free(struct irq_domain *domain,
	200	unsigned int virq, unsigned int nr_irqs)
	201	{
	202	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
	203	struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
	204
	205	BUG_ON(nr_irqs != 1);
	206	gicv2m_unalloc_msi(v2m, d->hwirq);
	207	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
	208	}
	209
	210	static const struct irq_domain_ops gicv2m_domain_ops = {
	211	.alloc = gicv2m_irq_domain_alloc,
	212	.free = gicv2m_irq_domain_free,
	213	};
	214
	215	static bool is_msi_spi_valid(u32 base, u32 num)
	216	{
	217	if (base < V2M_MIN_SPI) {
	218	pr_err("Invalid MSI base SPI (base:%u)\n", base);
	219	return false;
	220	}
	221
	222	if ((num == 0) \|\| (base + num > V2M_MAX_SPI)) {
	223	pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
	224	num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
	225	return false;
	226	}
	227
	228	return true;
	229	}
	230
ef50645a MZ	231	static struct irq_chip gicv2m_pmsi_irq_chip = {
	232	.name = "pMSI",
	233	};
	234
	235	static struct msi_domain_ops gicv2m_pmsi_ops = {
	236	};
	237
	238	static struct msi_domain_info gicv2m_pmsi_domain_info = {
	239	.flags = (MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS),
	240	.ops = &gicv2m_pmsi_ops,
	241	.chip = &gicv2m_pmsi_irq_chip,
	242	};
	243
a71225e2 MZ	244	static void gicv2m_teardown(void)
	245	{
	246	struct v2m_data v2m, tmp;
	247
	248	list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
	249	list_del(&v2m->entry);
	250	kfree(v2m->bm);
	251	iounmap(v2m->base);
4266ab1a	252	of_node_put(to_of_node(v2m->fwnode));
0644b3da SS	253	if (is_fwnode_irqchip(v2m->fwnode))
0644b3da SS	254	irq_domain_free_fwnode(v2m->fwnode);
a71225e2 MZ	255	kfree(v2m);
	256	}
	257	}
	258
	259	static int gicv2m_allocate_domains(struct irq_domain *parent)
	260	{
	261	struct irq_domain inner_domain, pci_domain, *plat_domain;
	262	struct v2m_data *v2m;
	263
	264	v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
	265	if (!v2m)
	266	return 0;
	267
4266ab1a	268	inner_domain = irq_domain_create_tree(v2m->fwnode,
a71225e2 MZ	269	&gicv2m_domain_ops, v2m);
	270	if (!inner_domain) {
	271	pr_err("Failed to create GICv2m domain\n");
	272	return -ENOMEM;
	273	}
	274
	275	inner_domain->bus_token = DOMAIN_BUS_NEXUS;
	276	inner_domain->parent = parent;
4266ab1a	277	pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
a71225e2 MZ	278	&gicv2m_msi_domain_info,
a71225e2 MZ	279	inner_domain);
4266ab1a	280	plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
a71225e2 MZ	281	&gicv2m_pmsi_domain_info,
	282	inner_domain);
	283	if (!pci_domain \|\| !plat_domain) {
	284	pr_err("Failed to create MSI domains\n");
	285	if (plat_domain)
	286	irq_domain_remove(plat_domain);
	287	if (pci_domain)
	288	irq_domain_remove(pci_domain);
	289	irq_domain_remove(inner_domain);
	290	return -ENOMEM;
	291	}
	292
	293	return 0;
	294	}
	295
4266ab1a SS	296	static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
	297	u32 spi_start, u32 nr_spis,
	298	struct resource *res)
853a33ce SS	299	{
	300	int ret;
	301	struct v2m_data *v2m;
	302
	303	v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
	304	if (!v2m) {
	305	pr_err("Failed to allocate struct v2m_data.\n");
	306	return -ENOMEM;
	307	}
	308
a71225e2	309	INIT_LIST_HEAD(&v2m->entry);
4266ab1a	310	v2m->fwnode = fwnode;
a71225e2	311
4266ab1a	312	memcpy(&v2m->res, res, sizeof(struct resource));
853a33ce SS	313
	314	v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
	315	if (!v2m->base) {
	316	pr_err("Failed to map GICv2m resource\n");
	317	ret = -ENOMEM;
	318	goto err_free_v2m;
	319	}
	320
4266ab1a SS	321	if (spi_start && nr_spis) {
	322	v2m->spi_start = spi_start;
	323	v2m->nr_spis = nr_spis;
853a33ce SS	324	} else {
	325	u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
	326
	327	v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
	328	v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
	329	}
	330
	331	if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
	332	ret = -EINVAL;
	333	goto err_iounmap;
	334	}
	335
ee5f7d64 DD	336	/*
	337	* APM X-Gene GICv2m implementation has an erratum where
	338	* the MSI data needs to be the offset from the spi_start
	339	* in order to trigger the correct MSI interrupt. This is
	340	* different from the standard GICv2m implementation where
	341	* the MSI data is the absolute value within the range from
	342	* spi_start to (spi_start + num_spis).
	343	*/
	344	if (readl_relaxed(v2m->base + V2M_MSI_IIDR) == XGENE_GICV2M_MSI_IIDR)
	345	v2m->flags \|= GICV2M_NEEDS_SPI_OFFSET;
	346
853a33ce SS	347	v2m->bm = kzalloc(sizeof(long) * BITS_TO_LONGS(v2m->nr_spis),
	348	GFP_KERNEL);
	349	if (!v2m->bm) {
	350	ret = -ENOMEM;
	351	goto err_iounmap;
	352	}
	353
a71225e2	354	list_add_tail(&v2m->entry, &v2m_nodes);
853a33ce	355
5a1ff480 SS	356	pr_info("range%pR, SPI[%d:%d]\n", res,
5a1ff480 SS	357	v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
853a33ce SS	358	return 0;
853a33ce SS	359
853a33ce SS	360	err_iounmap:
	361	iounmap(v2m->base);
	362	err_free_v2m:
	363	kfree(v2m);
	364	return ret;
	365	}
	366
	367	static struct of_device_id gicv2m_device_id[] = {
	368	{ .compatible = "arm,gic-v2m-frame", },
	369	{},
	370	};
	371
0644b3da SS	372	static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
0644b3da SS	373	struct irq_domain *parent)
853a33ce SS	374	{
853a33ce SS	375	int ret = 0;
0644b3da	376	struct device_node *node = to_of_node(parent_handle);
853a33ce SS	377	struct device_node *child;
	378
	379	for (child = of_find_matching_node(node, gicv2m_device_id); child;
	380	child = of_find_matching_node(child, gicv2m_device_id)) {
4266ab1a SS	381	u32 spi_start = 0, nr_spis = 0;
	382	struct resource res;
	383
853a33ce SS	384	if (!of_find_property(child, "msi-controller", NULL))
	385	continue;
	386
4266ab1a SS	387	ret = of_address_to_resource(child, 0, &res);
	388	if (ret) {
	389	pr_err("Failed to allocate v2m resource.\n");
	390	break;
	391	}
	392
	393	if (!of_property_read_u32(child, "arm,msi-base-spi",
	394	&spi_start) &&
	395	!of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
	396	pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
	397	spi_start, nr_spis);
	398
	399	ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res);
853a33ce	400	if (ret) {
86d14c72	401	of_node_put(child);
853a33ce SS	402	break;
	403	}
	404	}
	405
a71225e2 MZ	406	if (!ret)
	407	ret = gicv2m_allocate_domains(parent);
	408	if (ret)
	409	gicv2m_teardown();
853a33ce SS	410	return ret;
853a33ce SS	411	}
0644b3da SS	412
	413	#ifdef CONFIG_ACPI
	414	static int acpi_num_msi;
	415
	416	static struct fwnode_handle gicv2m_get_fwnode(struct device dev)
	417	{
	418	struct v2m_data *data;
	419
	420	if (WARN_ON(acpi_num_msi <= 0))
	421	return NULL;
	422
	423	/* We only return the fwnode of the first MSI frame. */
	424	data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
	425	if (!data)
	426	return NULL;
	427
	428	return data->fwnode;
	429	}
	430
	431	static int __init
	432	acpi_parse_madt_msi(struct acpi_subtable_header *header,
	433	const unsigned long end)
	434	{
	435	int ret;
	436	struct resource res;
	437	u32 spi_start = 0, nr_spis = 0;
	438	struct acpi_madt_generic_msi_frame *m;
	439	struct fwnode_handle *fwnode;
	440
	441	m = (struct acpi_madt_generic_msi_frame *)header;
	442	if (BAD_MADT_ENTRY(m, end))
	443	return -EINVAL;
	444
	445	res.start = m->base_address;
5a1ff480 SS	446	res.end = m->base_address + SZ_4K - 1;
5a1ff480 SS	447	res.flags = IORESOURCE_MEM;
0644b3da SS	448
	449	if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
	450	spi_start = m->spi_base;
	451	nr_spis = m->spi_count;
	452
	453	pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
	454	spi_start, nr_spis);
	455	}
	456
	457	fwnode = irq_domain_alloc_fwnode((void *)m->base_address);
	458	if (!fwnode) {
	459	pr_err("Unable to allocate GICv2m domain token\n");
	460	return -EINVAL;
	461	}
	462
	463	ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res);
	464	if (ret)
	465	irq_domain_free_fwnode(fwnode);
	466
	467	return ret;
	468	}
	469
	470	static int __init gicv2m_acpi_init(struct irq_domain *parent)
	471	{
	472	int ret;
	473
	474	if (acpi_num_msi > 0)
	475	return 0;
	476
	477	acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
	478	acpi_parse_madt_msi, 0);
	479
	480	if (acpi_num_msi <= 0)
	481	goto err_out;
	482
	483	ret = gicv2m_allocate_domains(parent);
	484	if (ret)
	485	goto err_out;
	486
	487	pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);
	488
	489	return 0;
	490
	491	err_out:
	492	gicv2m_teardown();
	493	return -EINVAL;
	494	}
	495	#else /* CONFIG_ACPI */
	496	static int __init gicv2m_acpi_init(struct irq_domain *parent)
	497	{
	498	return -EINVAL;
	499	}
	500	#endif /* CONFIG_ACPI */
	501
	502	int __init gicv2m_init(struct fwnode_handle *parent_handle,
	503	struct irq_domain *parent)
	504	{
	505	if (is_of_node(parent_handle))
	506	return gicv2m_of_init(parent_handle, parent);
	507
	508	return gicv2m_acpi_init(parent);
	509	}