[linux-2.6-block.git] / drivers / irqchip / irq-armada-370-xp.c

/*
 * Marvell Armada 370 and Armada XP SoC IRQ handling
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/cpu.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/irqdomain.h>
#include <linux/slab.h>
#include <linux/syscore_ops.h>
#include <linux/msi.h>
#include <asm/mach/arch.h>
#include <asm/exception.h>
#include <asm/smp_plat.h>
#include <asm/mach/irq.h>

/* Interrupt Controller Registers Map */
#define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)
#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS	(0x54)
#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)

#define ARMADA_370_XP_INT_CONTROL		(0x00)
#define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS	(0x34)
#define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	0xF
#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << cpuid)

#define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)
#define ARMADA_375_PPI_CAUSE			(0x10)

#define ARMADA_370_XP_SW_TRIG_INT_OFFS           (0x4)
#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS          (0xc)
#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS        (0x8)

#define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)

#define IPI_DOORBELL_START                      (0)
#define IPI_DOORBELL_END                        (8)
#define IPI_DOORBELL_MASK                       0xFF
#define PCI_MSI_DOORBELL_START                  (16)
#define PCI_MSI_DOORBELL_NR                     (16)
#define PCI_MSI_DOORBELL_END                    (32)
#define PCI_MSI_DOORBELL_MASK                   0xFFFF0000

static void __iomem *per_cpu_int_base;
static void __iomem *main_int_base;
static struct irq_domain *armada_370_xp_mpic_domain;
static u32 doorbell_mask_reg;
static int parent_irq;
#ifdef CONFIG_PCI_MSI
static struct irq_domain *armada_370_xp_msi_domain;
static struct irq_domain *armada_370_xp_msi_inner_domain;
static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
static DEFINE_MUTEX(msi_used_lock);
static phys_addr_t msi_doorbell_addr;
#endif

static inline bool is_percpu_irq(irq_hw_number_t irq)
{
	if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
		return true;

	return false;
}

/*
 * In SMP mode:
 * For shared global interrupts, mask/unmask global enable bit
 * For CPU interrupts, mask/unmask the calling CPU's bit
 */
static void armada_370_xp_irq_mask(struct irq_data *d)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	if (!is_percpu_irq(hwirq))
		writel(hwirq, main_int_base +
				ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
	else
		writel(hwirq, per_cpu_int_base +
				ARMADA_370_XP_INT_SET_MASK_OFFS);
}

static void armada_370_xp_irq_unmask(struct irq_data *d)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	if (!is_percpu_irq(hwirq))
		writel(hwirq, main_int_base +
				ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	else
		writel(hwirq, per_cpu_int_base +
				ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

#ifdef CONFIG_PCI_MSI

static struct irq_chip armada_370_xp_msi_irq_chip = {
	.name = "MPIC MSI",
	.irq_mask = pci_msi_mask_irq,
	.irq_unmask = pci_msi_unmask_irq,
};

static struct msi_domain_info armada_370_xp_msi_domain_info = {
	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
		   MSI_FLAG_MULTI_PCI_MSI),
	.chip	= &armada_370_xp_msi_irq_chip,
};

static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
{
	msg->address_lo = lower_32_bits(msi_doorbell_addr);
	msg->address_hi = upper_32_bits(msi_doorbell_addr);
	msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START);
}

static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
					  const struct cpumask *mask, bool force)
{
	 return -EINVAL;
}

static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
	.name			= "MPIC MSI",
	.irq_compose_msi_msg	= armada_370_xp_compose_msi_msg,
	.irq_set_affinity	= armada_370_xp_msi_set_affinity,
};

static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
				   unsigned int nr_irqs, void *args)
{
	int hwirq, i;

	mutex_lock(&msi_used_lock);

	hwirq = bitmap_find_next_zero_area(msi_used, PCI_MSI_DOORBELL_NR,
					   0, nr_irqs, 0);
	if (hwirq >= PCI_MSI_DOORBELL_NR) {
		mutex_unlock(&msi_used_lock);
		return -ENOSPC;
	}

	bitmap_set(msi_used, hwirq, nr_irqs);
	mutex_unlock(&msi_used_lock);

	for (i = 0; i < nr_irqs; i++) {
		irq_domain_set_info(domain, virq + i, hwirq + i,
				    &armada_370_xp_msi_bottom_irq_chip,
				    domain->host_data, handle_simple_irq,
				    NULL, NULL);
	}

	return hwirq;
}

static void armada_370_xp_msi_free(struct irq_domain *domain,
				   unsigned int virq, unsigned int nr_irqs)
{
	struct irq_data *d = irq_domain_get_irq_data(domain, virq);

	mutex_lock(&msi_used_lock);
	bitmap_clear(msi_used, d->hwirq, nr_irqs);
	mutex_unlock(&msi_used_lock);
}

static const struct irq_domain_ops armada_370_xp_msi_domain_ops = {
	.alloc	= armada_370_xp_msi_alloc,
	.free	= armada_370_xp_msi_free,
};

static int armada_370_xp_msi_init(struct device_node *node,
				  phys_addr_t main_int_phys_base)
{
	u32 reg;

	msi_doorbell_addr = main_int_phys_base +
		ARMADA_370_XP_SW_TRIG_INT_OFFS;

	armada_370_xp_msi_inner_domain =
		irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
				      &armada_370_xp_msi_domain_ops, NULL);
	if (!armada_370_xp_msi_inner_domain)
		return -ENOMEM;

	armada_370_xp_msi_domain =
		pci_msi_create_irq_domain(of_node_to_fwnode(node),
					  &armada_370_xp_msi_domain_info,
					  armada_370_xp_msi_inner_domain);
	if (!armada_370_xp_msi_domain) {
		irq_domain_remove(armada_370_xp_msi_inner_domain);
		return -ENOMEM;
	}

	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
		| PCI_MSI_DOORBELL_MASK;

	writel(reg, per_cpu_int_base +
	       ARMADA_370_XP_IN_DRBEL_MSK_OFFS);

	/* Unmask IPI interrupt */
	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);

	return 0;
}
#else
static inline int armada_370_xp_msi_init(struct device_node *node,
					 phys_addr_t main_int_phys_base)
{
	return 0;
}
#endif

#ifdef CONFIG_SMP
static DEFINE_RAW_SPINLOCK(irq_controller_lock);

static int armada_xp_set_affinity(struct irq_data *d,
				  const struct cpumask *mask_val, bool force)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);
	unsigned long reg, mask;
	int cpu;

	/* Select a single core from the affinity mask which is online */
	cpu = cpumask_any_and(mask_val, cpu_online_mask);
	mask = 1UL << cpu_logical_map(cpu);

	raw_spin_lock(&irq_controller_lock);
	reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
	reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
	writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
	raw_spin_unlock(&irq_controller_lock);

	return IRQ_SET_MASK_OK;
}
#endif

static struct irq_chip armada_370_xp_irq_chip = {
	.name		= "MPIC",
	.irq_mask       = armada_370_xp_irq_mask,
	.irq_mask_ack   = armada_370_xp_irq_mask,
	.irq_unmask     = armada_370_xp_irq_unmask,
#ifdef CONFIG_SMP
	.irq_set_affinity = armada_xp_set_affinity,
#endif
	.flags		= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
};

static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
				      unsigned int virq, irq_hw_number_t hw)
{
	armada_370_xp_irq_mask(irq_get_irq_data(virq));
	if (!is_percpu_irq(hw))
		writel(hw, per_cpu_int_base +
			ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	else
		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	irq_set_status_flags(virq, IRQ_LEVEL);

	if (is_percpu_irq(hw)) {
		irq_set_percpu_devid(virq);
		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
					handle_percpu_devid_irq);

	} else {
		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
					handle_level_irq);
	}
	irq_set_probe(virq);
	irq_clear_status_flags(virq, IRQ_NOAUTOEN);

	return 0;
}

static void armada_xp_mpic_smp_cpu_init(void)
{
	u32 control;
	int nr_irqs, i;

	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	nr_irqs = (control >> 2) & 0x3ff;

	for (i = 0; i < nr_irqs; i++)
		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);

	/* Clear pending IPIs */
	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

	/* Enable first 8 IPIs */
	writel(IPI_DOORBELL_MASK, per_cpu_int_base +
		ARMADA_370_XP_IN_DRBEL_MSK_OFFS);

	/* Unmask IPI interrupt */
	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

static void armada_xp_mpic_perf_init(void)
{
	unsigned long cpuid = cpu_logical_map(smp_processor_id());

	/* Enable Performance Counter Overflow interrupts */
	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
}

#ifdef CONFIG_SMP
static void armada_mpic_send_doorbell(const struct cpumask *mask,
				      unsigned int irq)
{
	int cpu;
	unsigned long map = 0;

	/* Convert our logical CPU mask into a physical one. */
	for_each_cpu(cpu, mask)
		map |= 1 << cpu_logical_map(cpu);

	/*
	 * Ensure that stores to Normal memory are visible to the
	 * other CPUs before issuing the IPI.
	 */
	dsb();

	/* submit softirq */
	writel((map << 8) | irq, main_int_base +
		ARMADA_370_XP_SW_TRIG_INT_OFFS);
}

static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
					 unsigned long action, void *hcpu)
{
	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
		armada_xp_mpic_perf_init();
		armada_xp_mpic_smp_cpu_init();
	}

	return NOTIFY_OK;
}

static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
	.notifier_call = armada_xp_mpic_secondary_init,
	.priority = 100,
};

static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
					unsigned long action, void *hcpu)
{
	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
		armada_xp_mpic_perf_init();
		enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
	}

	return NOTIFY_OK;
}

static struct notifier_block mpic_cascaded_cpu_notifier = {
	.notifier_call = mpic_cascaded_secondary_init,
	.priority = 100,
};
#endif /* CONFIG_SMP */

static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
	.map = armada_370_xp_mpic_irq_map,
	.xlate = irq_domain_xlate_onecell,
};

#ifdef CONFIG_PCI_MSI
static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
{
	u32 msimask, msinr;

	msimask = readl_relaxed(per_cpu_int_base +
				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
		& PCI_MSI_DOORBELL_MASK;

	writel(~msimask, per_cpu_int_base +
	       ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

	for (msinr = PCI_MSI_DOORBELL_START;
	     msinr < PCI_MSI_DOORBELL_END; msinr++) {
		int irq;

		if (!(msimask & BIT(msinr)))
			continue;

		if (is_chained) {
			irq = irq_find_mapping(armada_370_xp_msi_inner_domain,
					       msinr - PCI_MSI_DOORBELL_START);
			generic_handle_irq(irq);
		} else {
			irq = msinr - PCI_MSI_DOORBELL_START;
			handle_domain_irq(armada_370_xp_msi_inner_domain,
					  irq, regs);
		}
	}
}
#else
static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
#endif

static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned long irqmap, irqn, irqsrc, cpuid;
	unsigned int cascade_irq;

	chained_irq_enter(chip, desc);

	irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
	cpuid = cpu_logical_map(smp_processor_id());

	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
		irqsrc = readl_relaxed(main_int_base +
				       ARMADA_370_XP_INT_SOURCE_CTL(irqn));

		/* Check if the interrupt is not masked on current CPU.
		 * Test IRQ (0-1) and FIQ (8-9) mask bits.
		 */
		if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
			continue;

		if (irqn == 1) {
			armada_370_xp_handle_msi_irq(NULL, true);
			continue;
		}

		cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
		generic_handle_irq(cascade_irq);
	}

	chained_irq_exit(chip, desc);
}

static void __exception_irq_entry
armada_370_xp_handle_irq(struct pt_regs *regs)
{
	u32 irqstat, irqnr;

	do {
		irqstat = readl_relaxed(per_cpu_int_base +
					ARMADA_370_XP_CPU_INTACK_OFFS);
		irqnr = irqstat & 0x3FF;

		if (irqnr > 1022)
			break;

		if (irqnr > 1) {
			handle_domain_irq(armada_370_xp_mpic_domain,
					  irqnr, regs);
			continue;
		}

		/* MSI handling */
		if (irqnr == 1)
			armada_370_xp_handle_msi_irq(regs, false);

#ifdef CONFIG_SMP
		/* IPI Handling */
		if (irqnr == 0) {
			u32 ipimask, ipinr;

			ipimask = readl_relaxed(per_cpu_int_base +
						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
				& IPI_DOORBELL_MASK;

			writel(~ipimask, per_cpu_int_base +
				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

			/* Handle all pending doorbells */
			for (ipinr = IPI_DOORBELL_START;
			     ipinr < IPI_DOORBELL_END; ipinr++) {
				if (ipimask & (0x1 << ipinr))
					handle_IPI(ipinr, regs);
			}
			continue;
		}
#endif

	} while (1);
}

static int armada_370_xp_mpic_suspend(void)
{
	doorbell_mask_reg = readl(per_cpu_int_base +
				  ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	return 0;
}

static void armada_370_xp_mpic_resume(void)
{
	int nirqs;
	irq_hw_number_t irq;

	/* Re-enable interrupts */
	nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
	for (irq = 0; irq < nirqs; irq++) {
		struct irq_data *data;
		int virq;

		virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
		if (virq == 0)
			continue;

		if (!is_percpu_irq(irq))
			writel(irq, per_cpu_int_base +
			       ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
		else
			writel(irq, main_int_base +
			       ARMADA_370_XP_INT_SET_ENABLE_OFFS);

		data = irq_get_irq_data(virq);
		if (!irqd_irq_disabled(data))
			armada_370_xp_irq_unmask(data);
	}

	/* Reconfigure doorbells for IPIs and MSIs */
	writel(doorbell_mask_reg,
	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	if (doorbell_mask_reg & IPI_DOORBELL_MASK)
		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

struct syscore_ops armada_370_xp_mpic_syscore_ops = {
	.suspend	= armada_370_xp_mpic_suspend,
	.resume		= armada_370_xp_mpic_resume,
};

static int __init armada_370_xp_mpic_of_init(struct device_node *node,
					     struct device_node *parent)
{
	struct resource main_int_res, per_cpu_int_res;
	int nr_irqs, i;
	u32 control;

	BUG_ON(of_address_to_resource(node, 0, &main_int_res));
	BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));

	BUG_ON(!request_mem_region(main_int_res.start,
				   resource_size(&main_int_res),
				   node->full_name));
	BUG_ON(!request_mem_region(per_cpu_int_res.start,
				   resource_size(&per_cpu_int_res),
				   node->full_name));

	main_int_base = ioremap(main_int_res.start,
				resource_size(&main_int_res));
	BUG_ON(!main_int_base);

	per_cpu_int_base = ioremap(per_cpu_int_res.start,
				   resource_size(&per_cpu_int_res));
	BUG_ON(!per_cpu_int_base);

	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	nr_irqs = (control >> 2) & 0x3ff;

	for (i = 0; i < nr_irqs; i++)
		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);

	armada_370_xp_mpic_domain =
		irq_domain_add_linear(node, nr_irqs,
				&armada_370_xp_mpic_irq_ops, NULL);
	BUG_ON(!armada_370_xp_mpic_domain);
	armada_370_xp_mpic_domain->bus_token = DOMAIN_BUS_WIRED;

	/* Setup for the boot CPU */
	armada_xp_mpic_perf_init();
	armada_xp_mpic_smp_cpu_init();

	armada_370_xp_msi_init(node, main_int_res.start);

	parent_irq = irq_of_parse_and_map(node, 0);
	if (parent_irq <= 0) {
		irq_set_default_host(armada_370_xp_mpic_domain);
		set_handle_irq(armada_370_xp_handle_irq);
#ifdef CONFIG_SMP
		set_smp_cross_call(armada_mpic_send_doorbell);
		register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
#endif
	} else {
#ifdef CONFIG_SMP
		register_cpu_notifier(&mpic_cascaded_cpu_notifier);
#endif
		irq_set_chained_handler(parent_irq,
					armada_370_xp_mpic_handle_cascade_irq);
	}

	register_syscore_ops(&armada_370_xp_mpic_syscore_ops);

	return 0;
}

IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Marvell Armada 370 and Armada XP SoC IRQ handling
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	* Ben Dooks <ben.dooks@codethink.co.uk>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/init.h>
	19	#include <linux/irq.h>
	20	#include <linux/interrupt.h>
41a83e06	21	#include <linux/irqchip.h>
bc69b8ad	22	#include <linux/irqchip/chained_irq.h>
d7df84b3	23	#include <linux/cpu.h>
9ae6f740 TP	24	#include <linux/io.h>
	25	#include <linux/of_address.h>
	26	#include <linux/of_irq.h>
31f614ed	27	#include <linux/of_pci.h>
9ae6f740	28	#include <linux/irqdomain.h>
31f614ed	29	#include <linux/slab.h>
0f077eb5	30	#include <linux/syscore_ops.h>
31f614ed	31	#include <linux/msi.h>
9ae6f740 TP	32	#include <asm/mach/arch.h>
9ae6f740 TP	33	#include <asm/exception.h>
344e873e	34	#include <asm/smp_plat.h>
9339d432 TP	35	#include <asm/mach/irq.h>
9339d432 TP	36
9ae6f740 TP	37	/* Interrupt Controller Registers Map */
	38	#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
	39	#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
28da06df MR	40	#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
28da06df MR	41	#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
9ae6f740	42
f3e16ccd	43	#define ARMADA_370_XP_INT_CONTROL (0x00)
9ae6f740 TP	44	#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
9ae6f740 TP	45	#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
3202bf01	46	#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
8cc3cfc5	47	#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
758e8366	48	#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) \| BIT(8)) << cpuid)
9ae6f740 TP	49
9ae6f740 TP	50	#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
bc69b8ad	51	#define ARMADA_375_PPI_CAUSE (0x10)
9ae6f740	52
344e873e GC	53	#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
	54	#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
	55	#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
	56
3202bf01 GC	57	#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
3202bf01 GC	58
5ec69017 TP	59	#define IPI_DOORBELL_START (0)
	60	#define IPI_DOORBELL_END (8)
	61	#define IPI_DOORBELL_MASK 0xFF
31f614ed TP	62	#define PCI_MSI_DOORBELL_START (16)
	63	#define PCI_MSI_DOORBELL_NR (16)
	64	#define PCI_MSI_DOORBELL_END (32)
	65	#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
344e873e	66
9ae6f740 TP	67	static void __iomem *per_cpu_int_base;
	68	static void __iomem *main_int_base;
	69	static struct irq_domain *armada_370_xp_mpic_domain;
0f077eb5	70	static u32 doorbell_mask_reg;
5724be84	71	static int parent_irq;
31f614ed TP	72	#ifdef CONFIG_PCI_MSI
31f614ed TP	73	static struct irq_domain *armada_370_xp_msi_domain;
fcc392d5	74	static struct irq_domain *armada_370_xp_msi_inner_domain;
31f614ed TP	75	static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
	76	static DEFINE_MUTEX(msi_used_lock);
	77	static phys_addr_t msi_doorbell_addr;
	78	#endif
9ae6f740	79
2c299de5 EG	80	static inline bool is_percpu_irq(irq_hw_number_t irq)
2c299de5 EG	81	{
080481f9	82	if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
2c299de5	83	return true;
080481f9 MR	84
080481f9 MR	85	return false;
2c299de5 EG	86	}
2c299de5 EG	87
3202bf01 GC	88	/*
	89	* In SMP mode:
	90	* For shared global interrupts, mask/unmask global enable bit
097ef18d	91	* For CPU interrupts, mask/unmask the calling CPU's bit
3202bf01	92	*/
9ae6f740 TP	93	static void armada_370_xp_irq_mask(struct irq_data *d)
9ae6f740 TP	94	{
3202bf01 GC	95	irq_hw_number_t hwirq = irqd_to_hwirq(d);
3202bf01 GC	96
2c299de5	97	if (!is_percpu_irq(hwirq))
3202bf01 GC	98	writel(hwirq, main_int_base +
	99	ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
	100	else
	101	writel(hwirq, per_cpu_int_base +
	102	ARMADA_370_XP_INT_SET_MASK_OFFS);
9ae6f740 TP	103	}
	104
	105	static void armada_370_xp_irq_unmask(struct irq_data *d)
	106	{
3202bf01 GC	107	irq_hw_number_t hwirq = irqd_to_hwirq(d);
3202bf01 GC	108
2c299de5	109	if (!is_percpu_irq(hwirq))
3202bf01 GC	110	writel(hwirq, main_int_base +
	111	ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	112	else
	113	writel(hwirq, per_cpu_int_base +
	114	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
9ae6f740 TP	115	}
9ae6f740 TP	116
31f614ed TP	117	#ifdef CONFIG_PCI_MSI
31f614ed TP	118
fcc392d5	119	static struct irq_chip armada_370_xp_msi_irq_chip = {
f692a172	120	.name = "MPIC MSI",
fcc392d5 TP	121	.irq_mask = pci_msi_mask_irq,
	122	.irq_unmask = pci_msi_unmask_irq,
	123	};
31f614ed	124
fcc392d5	125	static struct msi_domain_info armada_370_xp_msi_domain_info = {
a71b9412 TP	126	.flags = (MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS \|
a71b9412 TP	127	MSI_FLAG_MULTI_PCI_MSI),
fcc392d5 TP	128	.chip = &armada_370_xp_msi_irq_chip,
fcc392d5 TP	129	};
31f614ed	130
fcc392d5	131	static void armada_370_xp_compose_msi_msg(struct irq_data data, struct msi_msg msg)
31f614ed	132	{
fcc392d5 TP	133	msg->address_lo = lower_32_bits(msi_doorbell_addr);
	134	msg->address_hi = upper_32_bits(msi_doorbell_addr);
	135	msg->data = 0xf00 \| (data->hwirq + PCI_MSI_DOORBELL_START);
31f614ed TP	136	}
31f614ed TP	137
fcc392d5 TP	138	static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
fcc392d5 TP	139	const struct cpumask *mask, bool force)
31f614ed	140	{
fcc392d5 TP	141	return -EINVAL;
fcc392d5 TP	142	}
31f614ed	143
fcc392d5	144	static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
f692a172	145	.name = "MPIC MSI",
fcc392d5 TP	146	.irq_compose_msi_msg = armada_370_xp_compose_msi_msg,
	147	.irq_set_affinity = armada_370_xp_msi_set_affinity,
	148	};
3930115e	149
fcc392d5 TP	150	static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
	151	unsigned int nr_irqs, void *args)
	152	{
a71b9412	153	int hwirq, i;
31f614ed	154
fcc392d5	155	mutex_lock(&msi_used_lock);
a71b9412 TP	156
	157	hwirq = bitmap_find_next_zero_area(msi_used, PCI_MSI_DOORBELL_NR,
	158	0, nr_irqs, 0);
fcc392d5 TP	159	if (hwirq >= PCI_MSI_DOORBELL_NR) {
	160	mutex_unlock(&msi_used_lock);
	161	return -ENOSPC;
31f614ed TP	162	}
31f614ed TP	163
a71b9412	164	bitmap_set(msi_used, hwirq, nr_irqs);
fcc392d5	165	mutex_unlock(&msi_used_lock);
31f614ed	166
a71b9412 TP	167	for (i = 0; i < nr_irqs; i++) {
	168	irq_domain_set_info(domain, virq + i, hwirq + i,
	169	&armada_370_xp_msi_bottom_irq_chip,
	170	domain->host_data, handle_simple_irq,
	171	NULL, NULL);
	172	}
31f614ed	173
fcc392d5	174	return hwirq;
31f614ed TP	175	}
31f614ed TP	176
fcc392d5 TP	177	static void armada_370_xp_msi_free(struct irq_domain *domain,
fcc392d5 TP	178	unsigned int virq, unsigned int nr_irqs)
31f614ed	179	{
fcc392d5	180	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
31f614ed	181
fcc392d5	182	mutex_lock(&msi_used_lock);
a71b9412	183	bitmap_clear(msi_used, d->hwirq, nr_irqs);
fcc392d5	184	mutex_unlock(&msi_used_lock);
31f614ed TP	185	}
31f614ed TP	186
fcc392d5 TP	187	static const struct irq_domain_ops armada_370_xp_msi_domain_ops = {
	188	.alloc = armada_370_xp_msi_alloc,
	189	.free = armada_370_xp_msi_free,
31f614ed TP	190	};
	191
	192	static int armada_370_xp_msi_init(struct device_node *node,
	193	phys_addr_t main_int_phys_base)
	194	{
31f614ed	195	u32 reg;
31f614ed TP	196
	197	msi_doorbell_addr = main_int_phys_base +
	198	ARMADA_370_XP_SW_TRIG_INT_OFFS;
	199
fcc392d5 TP	200	armada_370_xp_msi_inner_domain =
	201	irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
	202	&armada_370_xp_msi_domain_ops, NULL);
	203	if (!armada_370_xp_msi_inner_domain)
31f614ed TP	204	return -ENOMEM;
31f614ed TP	205
31f614ed	206	armada_370_xp_msi_domain =
fcc392d5 TP	207	pci_msi_create_irq_domain(of_node_to_fwnode(node),
	208	&armada_370_xp_msi_domain_info,
	209	armada_370_xp_msi_inner_domain);
31f614ed	210	if (!armada_370_xp_msi_domain) {
fcc392d5	211	irq_domain_remove(armada_370_xp_msi_inner_domain);
31f614ed TP	212	return -ENOMEM;
	213	}
	214
31f614ed TP	215	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
	216	\| PCI_MSI_DOORBELL_MASK;
	217
	218	writel(reg, per_cpu_int_base +
	219	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	220
	221	/* Unmask IPI interrupt */
	222	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	223
	224	return 0;
	225	}
	226	#else
	227	static inline int armada_370_xp_msi_init(struct device_node *node,
	228	phys_addr_t main_int_phys_base)
	229	{
	230	return 0;
	231	}
	232	#endif
	233
344e873e	234	#ifdef CONFIG_SMP
19e61d41 AE	235	static DEFINE_RAW_SPINLOCK(irq_controller_lock);
19e61d41 AE	236
344e873e GC	237	static int armada_xp_set_affinity(struct irq_data *d,
	238	const struct cpumask *mask_val, bool force)
	239	{
3202bf01	240	irq_hw_number_t hwirq = irqd_to_hwirq(d);
8cc3cfc5	241	unsigned long reg, mask;
3202bf01 GC	242	int cpu;
3202bf01 GC	243
8cc3cfc5 TG	244	/* Select a single core from the affinity mask which is online */
	245	cpu = cpumask_any_and(mask_val, cpu_online_mask);
	246	mask = 1UL << cpu_logical_map(cpu);
3202bf01 GC	247
3202bf01 GC	248	raw_spin_lock(&irq_controller_lock);
3202bf01	249	reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
8cc3cfc5	250	reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) \| mask;
3202bf01	251	writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
3202bf01 GC	252	raw_spin_unlock(&irq_controller_lock);
3202bf01 GC	253
1dacf194	254	return IRQ_SET_MASK_OK;
344e873e GC	255	}
	256	#endif
	257
9ae6f740	258	static struct irq_chip armada_370_xp_irq_chip = {
f692a172	259	.name = "MPIC",
9ae6f740 TP	260	.irq_mask = armada_370_xp_irq_mask,
	261	.irq_mask_ack = armada_370_xp_irq_mask,
	262	.irq_unmask = armada_370_xp_irq_unmask,
344e873e GC	263	#ifdef CONFIG_SMP
	264	.irq_set_affinity = armada_xp_set_affinity,
	265	#endif
0d8e1d80	266	.flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_MASK_ON_SUSPEND,
9ae6f740 TP	267	};
	268
	269	static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
	270	unsigned int virq, irq_hw_number_t hw)
	271	{
	272	armada_370_xp_irq_mask(irq_get_irq_data(virq));
2c299de5	273	if (!is_percpu_irq(hw))
600468d0 GC	274	writel(hw, per_cpu_int_base +
	275	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	276	else
	277	writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
9ae6f740	278	irq_set_status_flags(virq, IRQ_LEVEL);
3a6f08a3	279
2c299de5	280	if (is_percpu_irq(hw)) {
3a6f08a3 GC	281	irq_set_percpu_devid(virq);
	282	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
	283	handle_percpu_devid_irq);
	284
	285	} else {
	286	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
	287	handle_level_irq);
	288	}
d17cab44	289	irq_set_probe(virq);
353d6d6c	290	irq_clear_status_flags(virq, IRQ_NOAUTOEN);
9ae6f740 TP	291
	292	return 0;
	293	}
	294
d7df84b3	295	static void armada_xp_mpic_smp_cpu_init(void)
344e873e	296	{
b73842b7 TP	297	u32 control;
	298	int nr_irqs, i;
	299
	300	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	301	nr_irqs = (control >> 2) & 0x3ff;
	302
	303	for (i = 0; i < nr_irqs; i++)
	304	writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
	305
344e873e GC	306	/* Clear pending IPIs */
	307	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	308
	309	/* Enable first 8 IPIs */
5ec69017	310	writel(IPI_DOORBELL_MASK, per_cpu_int_base +
344e873e GC	311	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	312
	313	/* Unmask IPI interrupt */
	314	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	315	}
d7df84b3	316
28da06df MR	317	static void armada_xp_mpic_perf_init(void)
	318	{
	319	unsigned long cpuid = cpu_logical_map(smp_processor_id());
	320
	321	/* Enable Performance Counter Overflow interrupts */
	322	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
	323	per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
	324	}
	325
933a24b0 EG	326	#ifdef CONFIG_SMP
	327	static void armada_mpic_send_doorbell(const struct cpumask *mask,
	328	unsigned int irq)
	329	{
	330	int cpu;
	331	unsigned long map = 0;
	332
	333	/* Convert our logical CPU mask into a physical one. */
	334	for_each_cpu(cpu, mask)
	335	map \|= 1 << cpu_logical_map(cpu);
	336
	337	/*
	338	* Ensure that stores to Normal memory are visible to the
	339	* other CPUs before issuing the IPI.
	340	*/
	341	dsb();
	342
	343	/* submit softirq */
	344	writel((map << 8) \| irq, main_int_base +
	345	ARMADA_370_XP_SW_TRIG_INT_OFFS);
	346	}
	347
d7df84b3 TP	348	static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
	349	unsigned long action, void *hcpu)
	350	{
28da06df MR	351	if (action == CPU_STARTING \|\| action == CPU_STARTING_FROZEN) {
28da06df MR	352	armada_xp_mpic_perf_init();
d7df84b3	353	armada_xp_mpic_smp_cpu_init();
28da06df	354	}
5724be84	355
d7df84b3 TP	356	return NOTIFY_OK;
	357	}
	358
	359	static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
	360	.notifier_call = armada_xp_mpic_secondary_init,
	361	.priority = 100,
	362	};
	363
5724be84 MR	364	static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
	365	unsigned long action, void *hcpu)
	366	{
28da06df MR	367	if (action == CPU_STARTING \|\| action == CPU_STARTING_FROZEN) {
28da06df MR	368	armada_xp_mpic_perf_init();
5724be84	369	enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
28da06df	370	}
5724be84 MR	371
	372	return NOTIFY_OK;
	373	}
	374
	375	static struct notifier_block mpic_cascaded_cpu_notifier = {
	376	.notifier_call = mpic_cascaded_secondary_init,
	377	.priority = 100,
	378	};
344e873e GC	379	#endif /* CONFIG_SMP */
344e873e GC	380
96009736	381	static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
9ae6f740 TP	382	.map = armada_370_xp_mpic_irq_map,
	383	.xlate = irq_domain_xlate_onecell,
	384	};
	385
9b8cf779	386	#ifdef CONFIG_PCI_MSI
bc69b8ad	387	static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
9b8cf779 EG	388	{
	389	u32 msimask, msinr;
	390
	391	msimask = readl_relaxed(per_cpu_int_base +
	392	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
	393	& PCI_MSI_DOORBELL_MASK;
	394
	395	writel(~msimask, per_cpu_int_base +
	396	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	397
	398	for (msinr = PCI_MSI_DOORBELL_START;
	399	msinr < PCI_MSI_DOORBELL_END; msinr++) {
	400	int irq;
	401
	402	if (!(msimask & BIT(msinr)))
	403	continue;
	404
e89c6a06	405	if (is_chained) {
fcc392d5	406	irq = irq_find_mapping(armada_370_xp_msi_inner_domain,
0636bab6	407	msinr - PCI_MSI_DOORBELL_START);
bc69b8ad	408	generic_handle_irq(irq);
e89c6a06	409	} else {
0636bab6	410	irq = msinr - PCI_MSI_DOORBELL_START;
fcc392d5	411	handle_domain_irq(armada_370_xp_msi_inner_domain,
e89c6a06 MZ	412	irq, regs);
e89c6a06 MZ	413	}
9b8cf779 EG	414	}
	415	}
	416	#else
bc69b8ad	417	static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
9b8cf779 EG	418	#endif
9b8cf779 EG	419
bd0b9ac4	420	static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
bc69b8ad	421	{
5b29264c	422	struct irq_chip *chip = irq_desc_get_chip(desc);
758e8366	423	unsigned long irqmap, irqn, irqsrc, cpuid;
bc69b8ad EG	424	unsigned int cascade_irq;
	425
	426	chained_irq_enter(chip, desc);
	427
	428	irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
758e8366	429	cpuid = cpu_logical_map(smp_processor_id());
bc69b8ad EG	430
bc69b8ad EG	431	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
758e8366 GJ	432	irqsrc = readl_relaxed(main_int_base +
	433	ARMADA_370_XP_INT_SOURCE_CTL(irqn));
	434
	435	/* Check if the interrupt is not masked on current CPU.
	436	* Test IRQ (0-1) and FIQ (8-9) mask bits.
	437	*/
	438	if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
	439	continue;
	440
	441	if (irqn == 1) {
	442	armada_370_xp_handle_msi_irq(NULL, true);
	443	continue;
	444	}
	445
bc69b8ad EG	446	cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
	447	generic_handle_irq(cascade_irq);
	448	}
	449
	450	chained_irq_exit(chip, desc);
	451	}
	452
8783dd3a	453	static void __exception_irq_entry
9339d432	454	armada_370_xp_handle_irq(struct pt_regs *regs)
9ae6f740 TP	455	{
	456	u32 irqstat, irqnr;
	457
	458	do {
	459	irqstat = readl_relaxed(per_cpu_int_base +
	460	ARMADA_370_XP_CPU_INTACK_OFFS);
	461	irqnr = irqstat & 0x3FF;
	462
344e873e GC	463	if (irqnr > 1022)
	464	break;
	465
31f614ed	466	if (irqnr > 1) {
e89c6a06 MZ	467	handle_domain_irq(armada_370_xp_mpic_domain,
e89c6a06 MZ	468	irqnr, regs);
9ae6f740 TP	469	continue;
9ae6f740 TP	470	}
31f614ed	471
31f614ed	472	/* MSI handling */
9b8cf779	473	if (irqnr == 1)
bc69b8ad	474	armada_370_xp_handle_msi_irq(regs, false);
31f614ed	475
344e873e GC	476	#ifdef CONFIG_SMP
	477	/* IPI Handling */
	478	if (irqnr == 0) {
	479	u32 ipimask, ipinr;
	480
	481	ipimask = readl_relaxed(per_cpu_int_base +
	482	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
5ec69017	483	& IPI_DOORBELL_MASK;
344e873e	484
a6f089e9	485	writel(~ipimask, per_cpu_int_base +
344e873e GC	486	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	487
	488	/* Handle all pending doorbells */
5ec69017 TP	489	for (ipinr = IPI_DOORBELL_START;
5ec69017 TP	490	ipinr < IPI_DOORBELL_END; ipinr++) {
344e873e GC	491	if (ipimask & (0x1 << ipinr))
	492	handle_IPI(ipinr, regs);
	493	}
	494	continue;
	495	}
	496	#endif
9ae6f740	497
9ae6f740 TP	498	} while (1);
	499	}
	500
0f077eb5 TP	501	static int armada_370_xp_mpic_suspend(void)
	502	{
	503	doorbell_mask_reg = readl(per_cpu_int_base +
	504	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	505	return 0;
	506	}
	507
	508	static void armada_370_xp_mpic_resume(void)
	509	{
	510	int nirqs;
	511	irq_hw_number_t irq;
	512
	513	/* Re-enable interrupts */
	514	nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
	515	for (irq = 0; irq < nirqs; irq++) {
	516	struct irq_data *data;
	517	int virq;
	518
	519	virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
	520	if (virq == 0)
	521	continue;
	522
080481f9	523	if (!is_percpu_irq(irq))
0f077eb5 TP	524	writel(irq, per_cpu_int_base +
	525	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	526	else
	527	writel(irq, main_int_base +
	528	ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	529
	530	data = irq_get_irq_data(virq);
	531	if (!irqd_irq_disabled(data))
	532	armada_370_xp_irq_unmask(data);
	533	}
	534
	535	/* Reconfigure doorbells for IPIs and MSIs */
	536	writel(doorbell_mask_reg,
	537	per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	538	if (doorbell_mask_reg & IPI_DOORBELL_MASK)
	539	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	540	if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
	541	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	542	}
	543
	544	struct syscore_ops armada_370_xp_mpic_syscore_ops = {
	545	.suspend = armada_370_xp_mpic_suspend,
	546	.resume = armada_370_xp_mpic_resume,
	547	};
	548
b313ada8 TP	549	static int __init armada_370_xp_mpic_of_init(struct device_node *node,
b313ada8 TP	550	struct device_node *parent)
9ae6f740	551	{
627dfcc2	552	struct resource main_int_res, per_cpu_int_res;
5724be84	553	int nr_irqs, i;
b313ada8 TP	554	u32 control;
b313ada8 TP	555
627dfcc2 TP	556	BUG_ON(of_address_to_resource(node, 0, &main_int_res));
627dfcc2 TP	557	BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
b313ada8	558
627dfcc2 TP	559	BUG_ON(!request_mem_region(main_int_res.start,
	560	resource_size(&main_int_res),
	561	node->full_name));
	562	BUG_ON(!request_mem_region(per_cpu_int_res.start,
	563	resource_size(&per_cpu_int_res),
	564	node->full_name));
	565
	566	main_int_base = ioremap(main_int_res.start,
	567	resource_size(&main_int_res));
b313ada8	568	BUG_ON(!main_int_base);
627dfcc2 TP	569
	570	per_cpu_int_base = ioremap(per_cpu_int_res.start,
	571	resource_size(&per_cpu_int_res));
b313ada8 TP	572	BUG_ON(!per_cpu_int_base);
	573
	574	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
b73842b7 TP	575	nr_irqs = (control >> 2) & 0x3ff;
	576
	577	for (i = 0; i < nr_irqs; i++)
	578	writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
b313ada8 TP	579
b313ada8 TP	580	armada_370_xp_mpic_domain =
b73842b7	581	irq_domain_add_linear(node, nr_irqs,
b313ada8	582	&armada_370_xp_mpic_irq_ops, NULL);
627dfcc2	583	BUG_ON(!armada_370_xp_mpic_domain);
fcc392d5	584	armada_370_xp_mpic_domain->bus_token = DOMAIN_BUS_WIRED;
b313ada8	585
933a24b0	586	/* Setup for the boot CPU */
28da06df	587	armada_xp_mpic_perf_init();
b313ada8	588	armada_xp_mpic_smp_cpu_init();
b313ada8	589
31f614ed TP	590	armada_370_xp_msi_init(node, main_int_res.start);
31f614ed TP	591
bc69b8ad EG	592	parent_irq = irq_of_parse_and_map(node, 0);
	593	if (parent_irq <= 0) {
	594	irq_set_default_host(armada_370_xp_mpic_domain);
	595	set_handle_irq(armada_370_xp_handle_irq);
ef37d337 TP	596	#ifdef CONFIG_SMP
ef37d337 TP	597	set_smp_cross_call(armada_mpic_send_doorbell);
d7df84b3	598	register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
ef37d337	599	#endif
bc69b8ad	600	} else {
5724be84 MR	601	#ifdef CONFIG_SMP
	602	register_cpu_notifier(&mpic_cascaded_cpu_notifier);
	603	#endif
bc69b8ad EG	604	irq_set_chained_handler(parent_irq,
	605	armada_370_xp_mpic_handle_cascade_irq);
	606	}
b313ada8	607
0f077eb5 TP	608	register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
0f077eb5 TP	609
b313ada8	610	return 0;
9ae6f740	611	}
b313ada8	612
9339d432	613	IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);