projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iommu/io-pgtable-arm: Support IOMMU_MMIO flag
[linux-2.6-block.git] / drivers / iommu / io-pgtable-arm-v7s.c
CommitLineData
e5fc9753
RM		 1/*
2 * CPU-agnostic ARM page table allocator.
3 *
4 * ARMv7 Short-descriptor format, supporting
5 * - Basic memory attributes
6 * - Simplified access permissions (AP[2:1] model)
7 * - Backwards-compatible TEX remap
8 * - Large pages/supersections (if indicated by the caller)
9 *
10 * Not supporting:
11 * - Legacy access permissions (AP[2:0] model)
12 *
13 * Almost certainly never supporting:
14 * - PXN
15 * - Domains
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program. If not, see <http://www.gnu.org/licenses/>.
28 *
29 * Copyright (C) 2014-2015 ARM Limited
30 * Copyright (c) 2014-2015 MediaTek Inc.
31 */
32
33#define pr_fmt(fmt) "arm-v7s io-pgtable: " fmt
34
35#include <linux/dma-mapping.h>
36#include <linux/gfp.h>
37#include <linux/iommu.h>
38#include <linux/kernel.h>
39#include <linux/kmemleak.h>
40#include <linux/sizes.h>
41#include <linux/slab.h>
42#include <linux/types.h>
43
44#include <asm/barrier.h>
45
46#include "io-pgtable.h"
47
48/* Struct accessors */
49#define io_pgtable_to_data(x) \
50 container_of((x), struct arm_v7s_io_pgtable, iop)
51
52#define io_pgtable_ops_to_data(x) \
53 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
54
55/*
56 * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2,
57 * and 12 bits in a page. With some carefully-chosen coefficients we can
58 * hide the ugly inconsistencies behind these macros and at least let the
59 * rest of the code pretend to be somewhat sane.
60 */
61#define ARM_V7S_ADDR_BITS 32
62#define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
63#define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
64#define ARM_V7S_TABLE_SHIFT 10
65
66#define ARM_V7S_PTES_PER_LVL(lvl) (1 << _ARM_V7S_LVL_BITS(lvl))
67#define ARM_V7S_TABLE_SIZE(lvl) \
68 (ARM_V7S_PTES_PER_LVL(lvl) * sizeof(arm_v7s_iopte))
69
70#define ARM_V7S_BLOCK_SIZE(lvl) (1UL << ARM_V7S_LVL_SHIFT(lvl))
71#define ARM_V7S_LVL_MASK(lvl) ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl)))
72#define ARM_V7S_TABLE_MASK ((u32)(~0U << ARM_V7S_TABLE_SHIFT))
73#define _ARM_V7S_IDX_MASK(lvl) (ARM_V7S_PTES_PER_LVL(lvl) - 1)
74#define ARM_V7S_LVL_IDX(addr, lvl) ({ \
75 int _l = lvl; \
76 ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l); \
77})
78
79/*
80 * Large page/supersection entries are effectively a block of 16 page/section
81 * entries, along the lines of the LPAE contiguous hint, but all with the
82 * same output address. For want of a better common name we'll call them
83 * "contiguous" versions of their respective page/section entries here, but
84 * noting the distinction (WRT to TLB maintenance) that they represent *one*
85 * entry repeated 16 times, not 16 separate entries (as in the LPAE case).
86 */
87#define ARM_V7S_CONT_PAGES 16
88
89/* PTE type bits: these are all mixed up with XN/PXN bits in most cases */
90#define ARM_V7S_PTE_TYPE_TABLE 0x1
91#define ARM_V7S_PTE_TYPE_PAGE 0x2
92#define ARM_V7S_PTE_TYPE_CONT_PAGE 0x1
93
94#define ARM_V7S_PTE_IS_VALID(pte) (((pte) & 0x3) != 0)
95#define ARM_V7S_PTE_IS_TABLE(pte, lvl) (lvl == 1 && ((pte) & ARM_V7S_PTE_TYPE_TABLE))
96
97/* Page table bits */
98#define ARM_V7S_ATTR_XN(lvl) BIT(4 * (2 - (lvl)))
99#define ARM_V7S_ATTR_B BIT(2)
100#define ARM_V7S_ATTR_C BIT(3)
101#define ARM_V7S_ATTR_NS_TABLE BIT(3)
102#define ARM_V7S_ATTR_NS_SECTION BIT(19)
103
104#define ARM_V7S_CONT_SECTION BIT(18)
105#define ARM_V7S_CONT_PAGE_XN_SHIFT 15
106
107/*
108 * The attribute bits are consistently ordered*, but occupy bits [17:10] of
109 * a level 1 PTE vs. bits [11:4] at level 2. Thus we define the individual
110 * fields relative to that 8-bit block, plus a total shift relative to the PTE.
111 */
112#define ARM_V7S_ATTR_SHIFT(lvl) (16 - (lvl) * 6)
113
114#define ARM_V7S_ATTR_MASK 0xff
115#define ARM_V7S_ATTR_AP0 BIT(0)
116#define ARM_V7S_ATTR_AP1 BIT(1)
117#define ARM_V7S_ATTR_AP2 BIT(5)
118#define ARM_V7S_ATTR_S BIT(6)
119#define ARM_V7S_ATTR_NG BIT(7)
120#define ARM_V7S_TEX_SHIFT 2
121#define ARM_V7S_TEX_MASK 0x7
122#define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
123
1afe2319
YW		 124#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
125
e5fc9753
RM		 126/* *well, except for TEX on level 2 large pages, of course :( */
127#define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
128#define ARM_V7S_CONT_PAGE_TEX_MASK (ARM_V7S_TEX_MASK << ARM_V7S_CONT_PAGE_TEX_SHIFT)
129
130/* Simplified access permissions */
131#define ARM_V7S_PTE_AF ARM_V7S_ATTR_AP0
132#define ARM_V7S_PTE_AP_UNPRIV ARM_V7S_ATTR_AP1
133#define ARM_V7S_PTE_AP_RDONLY ARM_V7S_ATTR_AP2
134
135/* Register bits */
136#define ARM_V7S_RGN_NC 0
137#define ARM_V7S_RGN_WBWA 1
138#define ARM_V7S_RGN_WT 2
139#define ARM_V7S_RGN_WB 3
140
141#define ARM_V7S_PRRR_TYPE_DEVICE 1
142#define ARM_V7S_PRRR_TYPE_NORMAL 2
143#define ARM_V7S_PRRR_TR(n, type) (((type) & 0x3) << ((n) * 2))
144#define ARM_V7S_PRRR_DS0 BIT(16)
145#define ARM_V7S_PRRR_DS1 BIT(17)
146#define ARM_V7S_PRRR_NS0 BIT(18)
147#define ARM_V7S_PRRR_NS1 BIT(19)
148#define ARM_V7S_PRRR_NOS(n) BIT((n) + 24)
149
150#define ARM_V7S_NMRR_IR(n, attr) (((attr) & 0x3) << ((n) * 2))
151#define ARM_V7S_NMRR_OR(n, attr) (((attr) & 0x3) << ((n) * 2 + 16))
152
153#define ARM_V7S_TTBR_S BIT(1)
154#define ARM_V7S_TTBR_NOS BIT(5)
155#define ARM_V7S_TTBR_ORGN_ATTR(attr) (((attr) & 0x3) << 3)
156#define ARM_V7S_TTBR_IRGN_ATTR(attr) \
157 ((((attr) & 0x1) << 6) | (((attr) & 0x2) >> 1))
158
159#define ARM_V7S_TCR_PD1 BIT(5)
160
161typedef u32 arm_v7s_iopte;
162
163static bool selftest_running;
164
165struct arm_v7s_io_pgtable {
166 struct io_pgtable iop;
167
168 arm_v7s_iopte *pgd;
169 struct kmem_cache *l2_tables;
170};
171
172static dma_addr_t __arm_v7s_dma_addr(void *pages)
173{
174 return (dma_addr_t)virt_to_phys(pages);
175}
176
177static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl)
178{
179 if (ARM_V7S_PTE_IS_TABLE(pte, lvl))
180 pte &= ARM_V7S_TABLE_MASK;
181 else
182 pte &= ARM_V7S_LVL_MASK(lvl);
183 return phys_to_virt(pte);
184}
185
186static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
187 struct arm_v7s_io_pgtable *data)
188{
189 struct device *dev = data->iop.cfg.iommu_dev;
190 dma_addr_t dma;
191 size_t size = ARM_V7S_TABLE_SIZE(lvl);
192 void *table = NULL;
193
194 if (lvl == 1)
195 table = (void *)__get_dma_pages(__GFP_ZERO, get_order(size));
196 else if (lvl == 2)
048b31ca 197 table = kmem_cache_zalloc(data->l2_tables, gfp | GFP_DMA);
e5fc9753
RM		 198 if (table && !selftest_running) {
199 dma = dma_map_single(dev, table, size, DMA_TO_DEVICE);
200 if (dma_mapping_error(dev, dma))
201 goto out_free;
202 /*
203 * We depend on the IOMMU being able to work with any physical
204 * address directly, so if the DMA layer suggests otherwise by
205 * translating or truncating them, that bodes very badly...
206 */
207 if (dma != virt_to_phys(table))
208 goto out_unmap;
209 }
210 kmemleak_ignore(table);
211 return table;
212
213out_unmap:
214 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
215 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
216out_free:
217 if (lvl == 1)
218 free_pages((unsigned long)table, get_order(size));
219 else
220 kmem_cache_free(data->l2_tables, table);
221 return NULL;
222}
223
224static void __arm_v7s_free_table(void *table, int lvl,
225 struct arm_v7s_io_pgtable *data)
226{
227 struct device *dev = data->iop.cfg.iommu_dev;
228 size_t size = ARM_V7S_TABLE_SIZE(lvl);
229
230 if (!selftest_running)
231 dma_unmap_single(dev, __arm_v7s_dma_addr(table), size,
232 DMA_TO_DEVICE);
233 if (lvl == 1)
234 free_pages((unsigned long)table, get_order(size));
235 else
236 kmem_cache_free(data->l2_tables, table);
237}
238
239static void __arm_v7s_pte_sync(arm_v7s_iopte *ptep, int num_entries,
240 struct io_pgtable_cfg *cfg)
241{
242 if (selftest_running)
243 return;
244
245 dma_sync_single_for_device(cfg->iommu_dev, __arm_v7s_dma_addr(ptep),
246 num_entries * sizeof(*ptep), DMA_TO_DEVICE);
247}
248static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
249 int num_entries, struct io_pgtable_cfg *cfg)
250{
251 int i;
252
253 for (i = 0; i < num_entries; i++)
254 ptep[i] = pte;
255
256 __arm_v7s_pte_sync(ptep, num_entries, cfg);
257}
258
259static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
260 struct io_pgtable_cfg *cfg)
261{
262 bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
263 arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S |
264 ARM_V7S_ATTR_TEX(1);
265
266 if (ap) {
267 pte |= ARM_V7S_PTE_AF | ARM_V7S_PTE_AP_UNPRIV;
268 if (!(prot & IOMMU_WRITE))
269 pte |= ARM_V7S_PTE_AP_RDONLY;
270 }
271 pte <<= ARM_V7S_ATTR_SHIFT(lvl);
272
273 if ((prot & IOMMU_NOEXEC) && ap)
274 pte |= ARM_V7S_ATTR_XN(lvl);
275 if (prot & IOMMU_CACHE)
276 pte |= ARM_V7S_ATTR_B | ARM_V7S_ATTR_C;
277
278 return pte;
279}
280
281static int arm_v7s_pte_to_prot(arm_v7s_iopte pte, int lvl)
282{
283 int prot = IOMMU_READ;
284
285 if (pte & (ARM_V7S_PTE_AP_RDONLY << ARM_V7S_ATTR_SHIFT(lvl)))
286 prot |= IOMMU_WRITE;
287 if (pte & ARM_V7S_ATTR_C)
288 prot |= IOMMU_CACHE;
289
290 return prot;
291}
292
293static arm_v7s_iopte arm_v7s_pte_to_cont(arm_v7s_iopte pte, int lvl)
294{
295 if (lvl == 1) {
296 pte |= ARM_V7S_CONT_SECTION;
297 } else if (lvl == 2) {
298 arm_v7s_iopte xn = pte & ARM_V7S_ATTR_XN(lvl);
299 arm_v7s_iopte tex = pte & ARM_V7S_CONT_PAGE_TEX_MASK;
300
301 pte ^= xn | tex | ARM_V7S_PTE_TYPE_PAGE;
302 pte |= (xn << ARM_V7S_CONT_PAGE_XN_SHIFT) |
303 (tex << ARM_V7S_CONT_PAGE_TEX_SHIFT) |
304 ARM_V7S_PTE_TYPE_CONT_PAGE;
305 }
306 return pte;
307}
308
309static arm_v7s_iopte arm_v7s_cont_to_pte(arm_v7s_iopte pte, int lvl)
310{
311 if (lvl == 1) {
312 pte &= ~ARM_V7S_CONT_SECTION;
313 } else if (lvl == 2) {
314 arm_v7s_iopte xn = pte & BIT(ARM_V7S_CONT_PAGE_XN_SHIFT);
315 arm_v7s_iopte tex = pte & (ARM_V7S_CONT_PAGE_TEX_MASK <<
316 ARM_V7S_CONT_PAGE_TEX_SHIFT);
317
318 pte ^= xn | tex | ARM_V7S_PTE_TYPE_CONT_PAGE;
319 pte |= (xn >> ARM_V7S_CONT_PAGE_XN_SHIFT) |
320 (tex >> ARM_V7S_CONT_PAGE_TEX_SHIFT) |
321 ARM_V7S_PTE_TYPE_PAGE;
322 }
323 return pte;
324}
325
326static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl)
327{
328 if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte, lvl))
329 return pte & ARM_V7S_CONT_SECTION;
330 else if (lvl == 2)
331 return !(pte & ARM_V7S_PTE_TYPE_PAGE);
332 return false;
333}
334
335static int __arm_v7s_unmap(struct arm_v7s_io_pgtable *, unsigned long,
336 size_t, int, arm_v7s_iopte *);
337
338static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
339 unsigned long iova, phys_addr_t paddr, int prot,
340 int lvl, int num_entries, arm_v7s_iopte *ptep)
341{
342 struct io_pgtable_cfg *cfg = &data->iop.cfg;
343 arm_v7s_iopte pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
344 int i;
345
346 for (i = 0; i < num_entries; i++)
347 if (ARM_V7S_PTE_IS_TABLE(ptep[i], lvl)) {
348 /*
349 * We need to unmap and free the old table before
350 * overwriting it with a block entry.
351 */
352 arm_v7s_iopte *tblp;
353 size_t sz = ARM_V7S_BLOCK_SIZE(lvl);
354
355 tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl);
356 if (WARN_ON(__arm_v7s_unmap(data, iova + i * sz,
357 sz, lvl, tblp) != sz))
358 return -EINVAL;
359 } else if (ptep[i]) {
360 /* We require an unmap first */
361 WARN_ON(!selftest_running);
362 return -EEXIST;
363 }
364
365 pte |= ARM_V7S_PTE_TYPE_PAGE;
366 if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
367 pte |= ARM_V7S_ATTR_NS_SECTION;
368
1afe2319
YW		 369 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
370 pte |= ARM_V7S_ATTR_MTK_4GB;
371
e5fc9753
RM		 372 if (num_entries > 1)
373 pte = arm_v7s_pte_to_cont(pte, lvl);
374
375 pte |= paddr & ARM_V7S_LVL_MASK(lvl);
376
377 __arm_v7s_set_pte(ptep, pte, num_entries, cfg);
378 return 0;
379}
380
381static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova,
382 phys_addr_t paddr, size_t size, int prot,
383 int lvl, arm_v7s_iopte *ptep)
384{
385 struct io_pgtable_cfg *cfg = &data->iop.cfg;
386 arm_v7s_iopte pte, *cptep;
387 int num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
388
389 /* Find our entry at the current level */
390 ptep += ARM_V7S_LVL_IDX(iova, lvl);
391
392 /* If we can install a leaf entry at this level, then do so */
393 if (num_entries)
394 return arm_v7s_init_pte(data, iova, paddr, prot,
395 lvl, num_entries, ptep);
396
397 /* We can't allocate tables at the final level */
398 if (WARN_ON(lvl == 2))
399 return -EINVAL;
400
401 /* Grab a pointer to the next level */
402 pte = *ptep;
403 if (!pte) {
404 cptep = __arm_v7s_alloc_table(lvl + 1, GFP_ATOMIC, data);
405 if (!cptep)
406 return -ENOMEM;
407
408 pte = virt_to_phys(cptep) | ARM_V7S_PTE_TYPE_TABLE;
409 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
410 pte |= ARM_V7S_ATTR_NS_TABLE;
411
412 __arm_v7s_set_pte(ptep, pte, 1, cfg);
413 } else {
414 cptep = iopte_deref(pte, lvl);
415 }
416
417 /* Rinse, repeat */
418 return __arm_v7s_map(data, iova, paddr, size, prot, lvl + 1, cptep);
419}
420
421static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
422 phys_addr_t paddr, size_t size, int prot)
423{
424 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
507e4c9d 425 struct io_pgtable *iop = &data->iop;
e5fc9753
RM		 426 int ret;
427
428 /* If no access, then nothing to do */
429 if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
430 return 0;
431
432 ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
433 /*
434 * Synchronise all PTE updates for the new mapping before there's
435 * a chance for anything to kick off a table walk for the new iova.
436 */
507e4c9d
RM		 437 if (iop->cfg.quirks & IO_PGTABLE_QUIRK_TLBI_ON_MAP) {
438 io_pgtable_tlb_add_flush(iop, iova, size,
439 ARM_V7S_BLOCK_SIZE(2), false);
440 io_pgtable_tlb_sync(iop);
e5fc9753
RM		 441 } else {
442 wmb();
443 }
444
445 return ret;
446}
447
448static void arm_v7s_free_pgtable(struct io_pgtable *iop)
449{
450 struct arm_v7s_io_pgtable *data = io_pgtable_to_data(iop);
451 int i;
452
453 for (i = 0; i < ARM_V7S_PTES_PER_LVL(1); i++) {
454 arm_v7s_iopte pte = data->pgd[i];
455
456 if (ARM_V7S_PTE_IS_TABLE(pte, 1))
457 __arm_v7s_free_table(iopte_deref(pte, 1), 2, data);
458 }
459 __arm_v7s_free_table(data->pgd, 1, data);
460 kmem_cache_destroy(data->l2_tables);
461 kfree(data);
462}
463
464static void arm_v7s_split_cont(struct arm_v7s_io_pgtable *data,
465 unsigned long iova, int idx, int lvl,
466 arm_v7s_iopte *ptep)
467{
507e4c9d 468 struct io_pgtable *iop = &data->iop;
e5fc9753
RM		 469 arm_v7s_iopte pte;
470 size_t size = ARM_V7S_BLOCK_SIZE(lvl);
471 int i;
472
473 ptep -= idx & (ARM_V7S_CONT_PAGES - 1);
474 pte = arm_v7s_cont_to_pte(*ptep, lvl);
475 for (i = 0; i < ARM_V7S_CONT_PAGES; i++) {
476 ptep[i] = pte;
477 pte += size;
478 }
479
507e4c9d 480 __arm_v7s_pte_sync(ptep, ARM_V7S_CONT_PAGES, &iop->cfg);
e5fc9753
RM		 481
482 size *= ARM_V7S_CONT_PAGES;
507e4c9d
RM		 483 io_pgtable_tlb_add_flush(iop, iova, size, size, true);
484 io_pgtable_tlb_sync(iop);
e5fc9753
RM		 485}
486
487static int arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
488 unsigned long iova, size_t size,
489 arm_v7s_iopte *ptep)
490{
491 unsigned long blk_start, blk_end, blk_size;
492 phys_addr_t blk_paddr;
493 arm_v7s_iopte table = 0;
e5fc9753
RM		 494 int prot = arm_v7s_pte_to_prot(*ptep, 1);
495
496 blk_size = ARM_V7S_BLOCK_SIZE(1);
497 blk_start = iova & ARM_V7S_LVL_MASK(1);
498 blk_end = blk_start + ARM_V7S_BLOCK_SIZE(1);
499 blk_paddr = *ptep & ARM_V7S_LVL_MASK(1);
500
501 for (; blk_start < blk_end; blk_start += size, blk_paddr += size) {
502 arm_v7s_iopte *tablep;
503
504 /* Unmap! */
505 if (blk_start == iova)
506 continue;
507
508 /* __arm_v7s_map expects a pointer to the start of the table */
509 tablep = &table - ARM_V7S_LVL_IDX(blk_start, 1);
510 if (__arm_v7s_map(data, blk_start, blk_paddr, size, prot, 1,
511 tablep) < 0) {
512 if (table) {
513 /* Free the table we allocated */
514 tablep = iopte_deref(table, 1);
515 __arm_v7s_free_table(tablep, 2, data);
516 }
517 return 0; /* Bytes unmapped */
518 }
519 }
520
507e4c9d 521 __arm_v7s_set_pte(ptep, table, 1, &data->iop.cfg);
e5fc9753 522 iova &= ~(blk_size - 1);
507e4c9d 523 io_pgtable_tlb_add_flush(&data->iop, iova, blk_size, blk_size, true);
e5fc9753
RM		 524 return size;
525}
526
527static int __arm_v7s_unmap(struct arm_v7s_io_pgtable *data,
528 unsigned long iova, size_t size, int lvl,
529 arm_v7s_iopte *ptep)
530{
531 arm_v7s_iopte pte[ARM_V7S_CONT_PAGES];
507e4c9d 532 struct io_pgtable *iop = &data->iop;
e5fc9753
RM		 533 int idx, i = 0, num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
534
535 /* Something went horribly wrong and we ran out of page table */
536 if (WARN_ON(lvl > 2))
537 return 0;
538
539 idx = ARM_V7S_LVL_IDX(iova, lvl);
540 ptep += idx;
541 do {
542 if (WARN_ON(!ARM_V7S_PTE_IS_VALID(ptep[i])))
543 return 0;
544 pte[i] = ptep[i];
545 } while (++i < num_entries);
546
547 /*
548 * If we've hit a contiguous 'large page' entry at this level, it
549 * needs splitting first, unless we're unmapping the whole lot.
550 */
551 if (num_entries <= 1 && arm_v7s_pte_is_cont(pte[0], lvl))
552 arm_v7s_split_cont(data, iova, idx, lvl, ptep);
553
554 /* If the size matches this level, we're in the right place */
555 if (num_entries) {
556 size_t blk_size = ARM_V7S_BLOCK_SIZE(lvl);
557
507e4c9d 558 __arm_v7s_set_pte(ptep, 0, num_entries, &iop->cfg);
e5fc9753
RM		 559
560 for (i = 0; i < num_entries; i++) {
561 if (ARM_V7S_PTE_IS_TABLE(pte[i], lvl)) {
562 /* Also flush any partial walks */
507e4c9d
RM		 563 io_pgtable_tlb_add_flush(iop, iova, blk_size,
564 ARM_V7S_BLOCK_SIZE(lvl + 1), false);
565 io_pgtable_tlb_sync(iop);
e5fc9753
RM		 566 ptep = iopte_deref(pte[i], lvl);
567 __arm_v7s_free_table(ptep, lvl + 1, data);
568 } else {
507e4c9d
RM		 569 io_pgtable_tlb_add_flush(iop, iova, blk_size,
570 blk_size, true);
e5fc9753
RM		 571 }
572 iova += blk_size;
573 }
574 return size;
575 } else if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte[0], lvl)) {
576 /*
577 * Insert a table at the next level to map the old region,
578 * minus the part we want to unmap
579 */
580 return arm_v7s_split_blk_unmap(data, iova, size, ptep);
581 }
582
583 /* Keep on walkin' */
584 ptep = iopte_deref(pte[0], lvl);
585 return __arm_v7s_unmap(data, iova, size, lvl + 1, ptep);
586}
587
588static int arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova,
589 size_t size)
590{
e5fc9753 591 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
507e4c9d 592 size_t unmapped;
e5fc9753
RM		 593
594 unmapped = __arm_v7s_unmap(data, iova, size, 1, data->pgd);
595 if (unmapped)
507e4c9d 596 io_pgtable_tlb_sync(&data->iop);
e5fc9753
RM		 597
598 return unmapped;
599}
600
601static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
602 unsigned long iova)
603{
604 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
605 arm_v7s_iopte *ptep = data->pgd, pte;
606 int lvl = 0;
607 u32 mask;
608
609 do {
610 pte = ptep[ARM_V7S_LVL_IDX(iova, ++lvl)];
611 ptep = iopte_deref(pte, lvl);
612 } while (ARM_V7S_PTE_IS_TABLE(pte, lvl));
613
614 if (!ARM_V7S_PTE_IS_VALID(pte))
615 return 0;
616
617 mask = ARM_V7S_LVL_MASK(lvl);
618 if (arm_v7s_pte_is_cont(pte, lvl))
619 mask *= ARM_V7S_CONT_PAGES;
620 return (pte & mask) | (iova & ~mask);
621}
622
623static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
624 void *cookie)
625{
626 struct arm_v7s_io_pgtable *data;
627
628 if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS)
629 return NULL;
630
3850db49
RM		 631 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
632 IO_PGTABLE_QUIRK_NO_PERMS |
1afe2319
YW		 633 IO_PGTABLE_QUIRK_TLBI_ON_MAP |
634 IO_PGTABLE_QUIRK_ARM_MTK_4GB))
3850db49
RM		 635 return NULL;
636
1afe2319
YW		 637 /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
638 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB &&
639 !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
640 return NULL;
641
e5fc9753
RM		 642 data = kmalloc(sizeof(*data), GFP_KERNEL);
643 if (!data)
644 return NULL;
645
646 data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
647 ARM_V7S_TABLE_SIZE(2),
648 ARM_V7S_TABLE_SIZE(2),
649 SLAB_CACHE_DMA, NULL);
650 if (!data->l2_tables)
651 goto out_free_data;
652
653 data->iop.ops = (struct io_pgtable_ops) {
654 .map = arm_v7s_map,
655 .unmap = arm_v7s_unmap,
656 .iova_to_phys = arm_v7s_iova_to_phys,
657 };
658
659 /* We have to do this early for __arm_v7s_alloc_table to work... */
660 data->iop.cfg = *cfg;
661
662 /*
663 * Unless the IOMMU driver indicates supersection support by
664 * having SZ_16M set in the initial bitmap, they won't be used.
665 */
666 cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M;
667
668 /* TCR: T0SZ=0, disable TTBR1 */
669 cfg->arm_v7s_cfg.tcr = ARM_V7S_TCR_PD1;
670
671 /*
672 * TEX remap: the indices used map to the closest equivalent types
673 * under the non-TEX-remap interpretation of those attribute bits,
674 * excepting various implementation-defined aspects of shareability.
675 */
676 cfg->arm_v7s_cfg.prrr = ARM_V7S_PRRR_TR(1, ARM_V7S_PRRR_TYPE_DEVICE) |
677 ARM_V7S_PRRR_TR(4, ARM_V7S_PRRR_TYPE_NORMAL) |
678 ARM_V7S_PRRR_TR(7, ARM_V7S_PRRR_TYPE_NORMAL) |
679 ARM_V7S_PRRR_DS0 | ARM_V7S_PRRR_DS1 |
680 ARM_V7S_PRRR_NS1 | ARM_V7S_PRRR_NOS(7);
681 cfg->arm_v7s_cfg.nmrr = ARM_V7S_NMRR_IR(7, ARM_V7S_RGN_WBWA) |
682 ARM_V7S_NMRR_OR(7, ARM_V7S_RGN_WBWA);
683
684 /* Looking good; allocate a pgd */
685 data->pgd = __arm_v7s_alloc_table(1, GFP_KERNEL, data);
686 if (!data->pgd)
687 goto out_free_data;
688
689 /* Ensure the empty pgd is visible before any actual TTBR write */
690 wmb();
691
692 /* TTBRs */
693 cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) |
694 ARM_V7S_TTBR_S | ARM_V7S_TTBR_NOS |
695 ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
696 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA);
697 cfg->arm_v7s_cfg.ttbr[1] = 0;
698 return &data->iop;
699
700out_free_data:
701 kmem_cache_destroy(data->l2_tables);
702 kfree(data);
703 return NULL;
704}
705
706struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns = {
707 .alloc = arm_v7s_alloc_pgtable,
708 .free = arm_v7s_free_pgtable,
709};
710
711#ifdef CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST
712
713static struct io_pgtable_cfg *cfg_cookie;
714
715static void dummy_tlb_flush_all(void *cookie)
716{
717 WARN_ON(cookie != cfg_cookie);
718}
719
720static void dummy_tlb_add_flush(unsigned long iova, size_t size,
721 size_t granule, bool leaf, void *cookie)
722{
723 WARN_ON(cookie != cfg_cookie);
724 WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
725}
726
727static void dummy_tlb_sync(void *cookie)
728{
729 WARN_ON(cookie != cfg_cookie);
730}
731
732static struct iommu_gather_ops dummy_tlb_ops = {
733 .tlb_flush_all = dummy_tlb_flush_all,
734 .tlb_add_flush = dummy_tlb_add_flush,
735 .tlb_sync = dummy_tlb_sync,
736};
737
738#define __FAIL(ops) ({ \
739 WARN(1, "selftest: test failed\n"); \
740 selftest_running = false; \
741 -EFAULT; \
742})
743
744static int __init arm_v7s_do_selftests(void)
745{
746 struct io_pgtable_ops *ops;
747 struct io_pgtable_cfg cfg = {
748 .tlb = &dummy_tlb_ops,
749 .oas = 32,
750 .ias = 32,
751 .quirks = IO_PGTABLE_QUIRK_ARM_NS,
752 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
753 };
754 unsigned int iova, size, iova_start;
755 unsigned int i, loopnr = 0;
756
757 selftest_running = true;
758
759 cfg_cookie = &cfg;
760
761 ops = alloc_io_pgtable_ops(ARM_V7S, &cfg, &cfg);
762 if (!ops) {
763 pr_err("selftest: failed to allocate io pgtable ops\n");
764 return -EINVAL;
765 }
766
767 /*
768 * Initial sanity checks.
769 * Empty page tables shouldn't provide any translations.
770 */
771 if (ops->iova_to_phys(ops, 42))
772 return __FAIL(ops);
773
774 if (ops->iova_to_phys(ops, SZ_1G + 42))
775 return __FAIL(ops);
776
777 if (ops->iova_to_phys(ops, SZ_2G + 42))
778 return __FAIL(ops);
779
780 /*
781 * Distinct mappings of different granule sizes.
782 */
783 iova = 0;
784 i = find_first_bit(&cfg.pgsize_bitmap, BITS_PER_LONG);
785 while (i != BITS_PER_LONG) {
786 size = 1UL << i;
787 if (ops->map(ops, iova, iova, size, IOMMU_READ |
788 IOMMU_WRITE |
789 IOMMU_NOEXEC |
790 IOMMU_CACHE))
791 return __FAIL(ops);
792
793 /* Overlapping mappings */
794 if (!ops->map(ops, iova, iova + size, size,
795 IOMMU_READ | IOMMU_NOEXEC))
796 return __FAIL(ops);
797
798 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
799 return __FAIL(ops);
800
801 iova += SZ_16M;
802 i++;
803 i = find_next_bit(&cfg.pgsize_bitmap, BITS_PER_LONG, i);
804 loopnr++;
805 }
806
807 /* Partial unmap */
808 i = 1;
809 size = 1UL << __ffs(cfg.pgsize_bitmap);
810 while (i < loopnr) {
811 iova_start = i * SZ_16M;
812 if (ops->unmap(ops, iova_start + size, size) != size)
813 return __FAIL(ops);
814
815 /* Remap of partial unmap */
816 if (ops->map(ops, iova_start + size, size, size, IOMMU_READ))
817 return __FAIL(ops);
818
819 if (ops->iova_to_phys(ops, iova_start + size + 42)
820 != (size + 42))
821 return __FAIL(ops);
822 i++;
823 }
824
825 /* Full unmap */
826 iova = 0;
827 i = find_first_bit(&cfg.pgsize_bitmap, BITS_PER_LONG);
828 while (i != BITS_PER_LONG) {
829 size = 1UL << i;
830
831 if (ops->unmap(ops, iova, size) != size)
832 return __FAIL(ops);
833
834 if (ops->iova_to_phys(ops, iova + 42))
835 return __FAIL(ops);
836
837 /* Remap full block */
838 if (ops->map(ops, iova, iova, size, IOMMU_WRITE))
839 return __FAIL(ops);
840
841 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
842 return __FAIL(ops);
843
844 iova += SZ_16M;
845 i++;
846 i = find_next_bit(&cfg.pgsize_bitmap, BITS_PER_LONG, i);
847 }
848
849 free_io_pgtable_ops(ops);
850
851 selftest_running = false;
852
853 pr_info("self test ok\n");
854 return 0;
855}
856subsys_initcall(arm_v7s_do_selftests);
857#endif
Linux 6.x block layer and io_uring tree(s)