Commit | Line | Data |
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45ae7cff WD |
1 | /* |
2 | * IOMMU API for ARM architected SMMU implementations. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
16 | * | |
17 | * Copyright (C) 2013 ARM Limited | |
18 | * | |
19 | * Author: Will Deacon <will.deacon@arm.com> | |
20 | * | |
21 | * This driver currently supports: | |
22 | * - SMMUv1 and v2 implementations | |
23 | * - Stream-matching and stream-indexing | |
24 | * - v7/v8 long-descriptor format | |
25 | * - Non-secure access to the SMMU | |
26 | * - 4k and 64k pages, with contiguous pte hints. | |
06f983dd | 27 | * - Up to 42-bit addressing (dependent on VA_BITS) |
45ae7cff WD |
28 | * - Context fault reporting |
29 | */ | |
30 | ||
31 | #define pr_fmt(fmt) "arm-smmu: " fmt | |
32 | ||
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/err.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/iommu.h> | |
39 | #include <linux/mm.h> | |
40 | #include <linux/module.h> | |
41 | #include <linux/of.h> | |
a9a1b0b5 | 42 | #include <linux/pci.h> |
45ae7cff WD |
43 | #include <linux/platform_device.h> |
44 | #include <linux/slab.h> | |
45 | #include <linux/spinlock.h> | |
46 | ||
47 | #include <linux/amba/bus.h> | |
48 | ||
49 | #include <asm/pgalloc.h> | |
50 | ||
51 | /* Maximum number of stream IDs assigned to a single device */ | |
636e97b0 | 52 | #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS |
45ae7cff WD |
53 | |
54 | /* Maximum number of context banks per SMMU */ | |
55 | #define ARM_SMMU_MAX_CBS 128 | |
56 | ||
57 | /* Maximum number of mapping groups per SMMU */ | |
58 | #define ARM_SMMU_MAX_SMRS 128 | |
59 | ||
45ae7cff WD |
60 | /* SMMU global address space */ |
61 | #define ARM_SMMU_GR0(smmu) ((smmu)->base) | |
62 | #define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize) | |
63 | ||
3a5df8ff AH |
64 | /* |
65 | * SMMU global address space with conditional offset to access secure | |
66 | * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448, | |
67 | * nsGFSYNR0: 0x450) | |
68 | */ | |
69 | #define ARM_SMMU_GR0_NS(smmu) \ | |
70 | ((smmu)->base + \ | |
71 | ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \ | |
72 | ? 0x400 : 0)) | |
73 | ||
45ae7cff | 74 | /* Page table bits */ |
cf2d45b1 | 75 | #define ARM_SMMU_PTE_XN (((pteval_t)3) << 53) |
45ae7cff WD |
76 | #define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52) |
77 | #define ARM_SMMU_PTE_AF (((pteval_t)1) << 10) | |
78 | #define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8) | |
79 | #define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8) | |
80 | #define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8) | |
cf2d45b1 | 81 | #define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0) |
45ae7cff WD |
82 | |
83 | #if PAGE_SIZE == SZ_4K | |
84 | #define ARM_SMMU_PTE_CONT_ENTRIES 16 | |
85 | #elif PAGE_SIZE == SZ_64K | |
86 | #define ARM_SMMU_PTE_CONT_ENTRIES 32 | |
87 | #else | |
88 | #define ARM_SMMU_PTE_CONT_ENTRIES 1 | |
89 | #endif | |
90 | ||
91 | #define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES) | |
92 | #define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1)) | |
45ae7cff WD |
93 | |
94 | /* Stage-1 PTE */ | |
95 | #define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6) | |
96 | #define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6) | |
97 | #define ARM_SMMU_PTE_ATTRINDX_SHIFT 2 | |
1463fe44 | 98 | #define ARM_SMMU_PTE_nG (((pteval_t)1) << 11) |
45ae7cff WD |
99 | |
100 | /* Stage-2 PTE */ | |
101 | #define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6) | |
102 | #define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6) | |
103 | #define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6) | |
104 | #define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2) | |
105 | #define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2) | |
106 | #define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2) | |
107 | ||
108 | /* Configuration registers */ | |
109 | #define ARM_SMMU_GR0_sCR0 0x0 | |
110 | #define sCR0_CLIENTPD (1 << 0) | |
111 | #define sCR0_GFRE (1 << 1) | |
112 | #define sCR0_GFIE (1 << 2) | |
113 | #define sCR0_GCFGFRE (1 << 4) | |
114 | #define sCR0_GCFGFIE (1 << 5) | |
115 | #define sCR0_USFCFG (1 << 10) | |
116 | #define sCR0_VMIDPNE (1 << 11) | |
117 | #define sCR0_PTM (1 << 12) | |
118 | #define sCR0_FB (1 << 13) | |
119 | #define sCR0_BSU_SHIFT 14 | |
120 | #define sCR0_BSU_MASK 0x3 | |
121 | ||
122 | /* Identification registers */ | |
123 | #define ARM_SMMU_GR0_ID0 0x20 | |
124 | #define ARM_SMMU_GR0_ID1 0x24 | |
125 | #define ARM_SMMU_GR0_ID2 0x28 | |
126 | #define ARM_SMMU_GR0_ID3 0x2c | |
127 | #define ARM_SMMU_GR0_ID4 0x30 | |
128 | #define ARM_SMMU_GR0_ID5 0x34 | |
129 | #define ARM_SMMU_GR0_ID6 0x38 | |
130 | #define ARM_SMMU_GR0_ID7 0x3c | |
131 | #define ARM_SMMU_GR0_sGFSR 0x48 | |
132 | #define ARM_SMMU_GR0_sGFSYNR0 0x50 | |
133 | #define ARM_SMMU_GR0_sGFSYNR1 0x54 | |
134 | #define ARM_SMMU_GR0_sGFSYNR2 0x58 | |
135 | #define ARM_SMMU_GR0_PIDR0 0xfe0 | |
136 | #define ARM_SMMU_GR0_PIDR1 0xfe4 | |
137 | #define ARM_SMMU_GR0_PIDR2 0xfe8 | |
138 | ||
139 | #define ID0_S1TS (1 << 30) | |
140 | #define ID0_S2TS (1 << 29) | |
141 | #define ID0_NTS (1 << 28) | |
142 | #define ID0_SMS (1 << 27) | |
143 | #define ID0_PTFS_SHIFT 24 | |
144 | #define ID0_PTFS_MASK 0x2 | |
145 | #define ID0_PTFS_V8_ONLY 0x2 | |
146 | #define ID0_CTTW (1 << 14) | |
147 | #define ID0_NUMIRPT_SHIFT 16 | |
148 | #define ID0_NUMIRPT_MASK 0xff | |
3c8766d0 OH |
149 | #define ID0_NUMSIDB_SHIFT 9 |
150 | #define ID0_NUMSIDB_MASK 0xf | |
45ae7cff WD |
151 | #define ID0_NUMSMRG_SHIFT 0 |
152 | #define ID0_NUMSMRG_MASK 0xff | |
153 | ||
154 | #define ID1_PAGESIZE (1 << 31) | |
155 | #define ID1_NUMPAGENDXB_SHIFT 28 | |
156 | #define ID1_NUMPAGENDXB_MASK 7 | |
157 | #define ID1_NUMS2CB_SHIFT 16 | |
158 | #define ID1_NUMS2CB_MASK 0xff | |
159 | #define ID1_NUMCB_SHIFT 0 | |
160 | #define ID1_NUMCB_MASK 0xff | |
161 | ||
162 | #define ID2_OAS_SHIFT 4 | |
163 | #define ID2_OAS_MASK 0xf | |
164 | #define ID2_IAS_SHIFT 0 | |
165 | #define ID2_IAS_MASK 0xf | |
166 | #define ID2_UBS_SHIFT 8 | |
167 | #define ID2_UBS_MASK 0xf | |
168 | #define ID2_PTFS_4K (1 << 12) | |
169 | #define ID2_PTFS_16K (1 << 13) | |
170 | #define ID2_PTFS_64K (1 << 14) | |
171 | ||
172 | #define PIDR2_ARCH_SHIFT 4 | |
173 | #define PIDR2_ARCH_MASK 0xf | |
174 | ||
175 | /* Global TLB invalidation */ | |
176 | #define ARM_SMMU_GR0_STLBIALL 0x60 | |
177 | #define ARM_SMMU_GR0_TLBIVMID 0x64 | |
178 | #define ARM_SMMU_GR0_TLBIALLNSNH 0x68 | |
179 | #define ARM_SMMU_GR0_TLBIALLH 0x6c | |
180 | #define ARM_SMMU_GR0_sTLBGSYNC 0x70 | |
181 | #define ARM_SMMU_GR0_sTLBGSTATUS 0x74 | |
182 | #define sTLBGSTATUS_GSACTIVE (1 << 0) | |
183 | #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ | |
184 | ||
185 | /* Stream mapping registers */ | |
186 | #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) | |
187 | #define SMR_VALID (1 << 31) | |
188 | #define SMR_MASK_SHIFT 16 | |
189 | #define SMR_MASK_MASK 0x7fff | |
190 | #define SMR_ID_SHIFT 0 | |
191 | #define SMR_ID_MASK 0x7fff | |
192 | ||
193 | #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) | |
194 | #define S2CR_CBNDX_SHIFT 0 | |
195 | #define S2CR_CBNDX_MASK 0xff | |
196 | #define S2CR_TYPE_SHIFT 16 | |
197 | #define S2CR_TYPE_MASK 0x3 | |
198 | #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT) | |
199 | #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT) | |
200 | #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT) | |
201 | ||
202 | /* Context bank attribute registers */ | |
203 | #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) | |
204 | #define CBAR_VMID_SHIFT 0 | |
205 | #define CBAR_VMID_MASK 0xff | |
57ca90f6 WD |
206 | #define CBAR_S1_BPSHCFG_SHIFT 8 |
207 | #define CBAR_S1_BPSHCFG_MASK 3 | |
208 | #define CBAR_S1_BPSHCFG_NSH 3 | |
45ae7cff WD |
209 | #define CBAR_S1_MEMATTR_SHIFT 12 |
210 | #define CBAR_S1_MEMATTR_MASK 0xf | |
211 | #define CBAR_S1_MEMATTR_WB 0xf | |
212 | #define CBAR_TYPE_SHIFT 16 | |
213 | #define CBAR_TYPE_MASK 0x3 | |
214 | #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) | |
215 | #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) | |
216 | #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) | |
217 | #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) | |
218 | #define CBAR_IRPTNDX_SHIFT 24 | |
219 | #define CBAR_IRPTNDX_MASK 0xff | |
220 | ||
221 | #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) | |
222 | #define CBA2R_RW64_32BIT (0 << 0) | |
223 | #define CBA2R_RW64_64BIT (1 << 0) | |
224 | ||
225 | /* Translation context bank */ | |
226 | #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1)) | |
227 | #define ARM_SMMU_CB(smmu, n) ((n) * (smmu)->pagesize) | |
228 | ||
229 | #define ARM_SMMU_CB_SCTLR 0x0 | |
230 | #define ARM_SMMU_CB_RESUME 0x8 | |
231 | #define ARM_SMMU_CB_TTBCR2 0x10 | |
232 | #define ARM_SMMU_CB_TTBR0_LO 0x20 | |
233 | #define ARM_SMMU_CB_TTBR0_HI 0x24 | |
234 | #define ARM_SMMU_CB_TTBCR 0x30 | |
235 | #define ARM_SMMU_CB_S1_MAIR0 0x38 | |
236 | #define ARM_SMMU_CB_FSR 0x58 | |
237 | #define ARM_SMMU_CB_FAR_LO 0x60 | |
238 | #define ARM_SMMU_CB_FAR_HI 0x64 | |
239 | #define ARM_SMMU_CB_FSYNR0 0x68 | |
1463fe44 | 240 | #define ARM_SMMU_CB_S1_TLBIASID 0x610 |
45ae7cff WD |
241 | |
242 | #define SCTLR_S1_ASIDPNE (1 << 12) | |
243 | #define SCTLR_CFCFG (1 << 7) | |
244 | #define SCTLR_CFIE (1 << 6) | |
245 | #define SCTLR_CFRE (1 << 5) | |
246 | #define SCTLR_E (1 << 4) | |
247 | #define SCTLR_AFE (1 << 2) | |
248 | #define SCTLR_TRE (1 << 1) | |
249 | #define SCTLR_M (1 << 0) | |
250 | #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE) | |
251 | ||
252 | #define RESUME_RETRY (0 << 0) | |
253 | #define RESUME_TERMINATE (1 << 0) | |
254 | ||
255 | #define TTBCR_EAE (1 << 31) | |
256 | ||
257 | #define TTBCR_PASIZE_SHIFT 16 | |
258 | #define TTBCR_PASIZE_MASK 0x7 | |
259 | ||
260 | #define TTBCR_TG0_4K (0 << 14) | |
261 | #define TTBCR_TG0_64K (1 << 14) | |
262 | ||
263 | #define TTBCR_SH0_SHIFT 12 | |
264 | #define TTBCR_SH0_MASK 0x3 | |
265 | #define TTBCR_SH_NS 0 | |
266 | #define TTBCR_SH_OS 2 | |
267 | #define TTBCR_SH_IS 3 | |
268 | ||
269 | #define TTBCR_ORGN0_SHIFT 10 | |
270 | #define TTBCR_IRGN0_SHIFT 8 | |
271 | #define TTBCR_RGN_MASK 0x3 | |
272 | #define TTBCR_RGN_NC 0 | |
273 | #define TTBCR_RGN_WBWA 1 | |
274 | #define TTBCR_RGN_WT 2 | |
275 | #define TTBCR_RGN_WB 3 | |
276 | ||
277 | #define TTBCR_SL0_SHIFT 6 | |
278 | #define TTBCR_SL0_MASK 0x3 | |
279 | #define TTBCR_SL0_LVL_2 0 | |
280 | #define TTBCR_SL0_LVL_1 1 | |
281 | ||
282 | #define TTBCR_T1SZ_SHIFT 16 | |
283 | #define TTBCR_T0SZ_SHIFT 0 | |
284 | #define TTBCR_SZ_MASK 0xf | |
285 | ||
286 | #define TTBCR2_SEP_SHIFT 15 | |
287 | #define TTBCR2_SEP_MASK 0x7 | |
288 | ||
289 | #define TTBCR2_PASIZE_SHIFT 0 | |
290 | #define TTBCR2_PASIZE_MASK 0x7 | |
291 | ||
292 | /* Common definitions for PASize and SEP fields */ | |
293 | #define TTBCR2_ADDR_32 0 | |
294 | #define TTBCR2_ADDR_36 1 | |
295 | #define TTBCR2_ADDR_40 2 | |
296 | #define TTBCR2_ADDR_42 3 | |
297 | #define TTBCR2_ADDR_44 4 | |
298 | #define TTBCR2_ADDR_48 5 | |
299 | ||
1463fe44 WD |
300 | #define TTBRn_HI_ASID_SHIFT 16 |
301 | ||
45ae7cff WD |
302 | #define MAIR_ATTR_SHIFT(n) ((n) << 3) |
303 | #define MAIR_ATTR_MASK 0xff | |
304 | #define MAIR_ATTR_DEVICE 0x04 | |
305 | #define MAIR_ATTR_NC 0x44 | |
306 | #define MAIR_ATTR_WBRWA 0xff | |
307 | #define MAIR_ATTR_IDX_NC 0 | |
308 | #define MAIR_ATTR_IDX_CACHE 1 | |
309 | #define MAIR_ATTR_IDX_DEV 2 | |
310 | ||
311 | #define FSR_MULTI (1 << 31) | |
312 | #define FSR_SS (1 << 30) | |
313 | #define FSR_UUT (1 << 8) | |
314 | #define FSR_ASF (1 << 7) | |
315 | #define FSR_TLBLKF (1 << 6) | |
316 | #define FSR_TLBMCF (1 << 5) | |
317 | #define FSR_EF (1 << 4) | |
318 | #define FSR_PF (1 << 3) | |
319 | #define FSR_AFF (1 << 2) | |
320 | #define FSR_TF (1 << 1) | |
321 | ||
2907320d MH |
322 | #define FSR_IGN (FSR_AFF | FSR_ASF | \ |
323 | FSR_TLBMCF | FSR_TLBLKF) | |
324 | #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ | |
adaba320 | 325 | FSR_EF | FSR_PF | FSR_TF | FSR_IGN) |
45ae7cff WD |
326 | |
327 | #define FSYNR0_WNR (1 << 4) | |
328 | ||
4cf740b0 WD |
329 | static int force_stage; |
330 | module_param_named(force_stage, force_stage, int, S_IRUGO | S_IWUSR); | |
331 | MODULE_PARM_DESC(force_stage, | |
332 | "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation."); | |
333 | ||
45ae7cff WD |
334 | struct arm_smmu_smr { |
335 | u8 idx; | |
336 | u16 mask; | |
337 | u16 id; | |
338 | }; | |
339 | ||
a9a1b0b5 | 340 | struct arm_smmu_master_cfg { |
45ae7cff WD |
341 | int num_streamids; |
342 | u16 streamids[MAX_MASTER_STREAMIDS]; | |
45ae7cff WD |
343 | struct arm_smmu_smr *smrs; |
344 | }; | |
345 | ||
a9a1b0b5 WD |
346 | struct arm_smmu_master { |
347 | struct device_node *of_node; | |
a9a1b0b5 WD |
348 | struct rb_node node; |
349 | struct arm_smmu_master_cfg cfg; | |
350 | }; | |
351 | ||
45ae7cff WD |
352 | struct arm_smmu_device { |
353 | struct device *dev; | |
45ae7cff WD |
354 | |
355 | void __iomem *base; | |
356 | unsigned long size; | |
357 | unsigned long pagesize; | |
358 | ||
359 | #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) | |
360 | #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1) | |
361 | #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2) | |
362 | #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3) | |
363 | #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4) | |
364 | u32 features; | |
3a5df8ff AH |
365 | |
366 | #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) | |
367 | u32 options; | |
45ae7cff WD |
368 | int version; |
369 | ||
370 | u32 num_context_banks; | |
371 | u32 num_s2_context_banks; | |
372 | DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS); | |
373 | atomic_t irptndx; | |
374 | ||
375 | u32 num_mapping_groups; | |
376 | DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS); | |
377 | ||
378 | unsigned long input_size; | |
379 | unsigned long s1_output_size; | |
380 | unsigned long s2_output_size; | |
381 | ||
382 | u32 num_global_irqs; | |
383 | u32 num_context_irqs; | |
384 | unsigned int *irqs; | |
385 | ||
45ae7cff WD |
386 | struct list_head list; |
387 | struct rb_root masters; | |
388 | }; | |
389 | ||
390 | struct arm_smmu_cfg { | |
45ae7cff WD |
391 | u8 cbndx; |
392 | u8 irptndx; | |
393 | u32 cbar; | |
394 | pgd_t *pgd; | |
395 | }; | |
faea13b7 | 396 | #define INVALID_IRPTNDX 0xff |
45ae7cff | 397 | |
ecfadb6e WD |
398 | #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) |
399 | #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) | |
400 | ||
45ae7cff | 401 | struct arm_smmu_domain { |
44680eed WD |
402 | struct arm_smmu_device *smmu; |
403 | struct arm_smmu_cfg cfg; | |
c9d09e27 | 404 | spinlock_t lock; |
45ae7cff WD |
405 | }; |
406 | ||
407 | static DEFINE_SPINLOCK(arm_smmu_devices_lock); | |
408 | static LIST_HEAD(arm_smmu_devices); | |
409 | ||
3a5df8ff AH |
410 | struct arm_smmu_option_prop { |
411 | u32 opt; | |
412 | const char *prop; | |
413 | }; | |
414 | ||
2907320d | 415 | static struct arm_smmu_option_prop arm_smmu_options[] = { |
3a5df8ff AH |
416 | { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, |
417 | { 0, NULL}, | |
418 | }; | |
419 | ||
420 | static void parse_driver_options(struct arm_smmu_device *smmu) | |
421 | { | |
422 | int i = 0; | |
2907320d | 423 | |
3a5df8ff AH |
424 | do { |
425 | if (of_property_read_bool(smmu->dev->of_node, | |
426 | arm_smmu_options[i].prop)) { | |
427 | smmu->options |= arm_smmu_options[i].opt; | |
428 | dev_notice(smmu->dev, "option %s\n", | |
429 | arm_smmu_options[i].prop); | |
430 | } | |
431 | } while (arm_smmu_options[++i].opt); | |
432 | } | |
433 | ||
a9a1b0b5 WD |
434 | static struct device *dev_get_master_dev(struct device *dev) |
435 | { | |
436 | if (dev_is_pci(dev)) { | |
437 | struct pci_bus *bus = to_pci_dev(dev)->bus; | |
2907320d | 438 | |
a9a1b0b5 WD |
439 | while (!pci_is_root_bus(bus)) |
440 | bus = bus->parent; | |
441 | return bus->bridge->parent; | |
442 | } | |
443 | ||
444 | return dev; | |
445 | } | |
446 | ||
45ae7cff WD |
447 | static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu, |
448 | struct device_node *dev_node) | |
449 | { | |
450 | struct rb_node *node = smmu->masters.rb_node; | |
451 | ||
452 | while (node) { | |
453 | struct arm_smmu_master *master; | |
2907320d | 454 | |
45ae7cff WD |
455 | master = container_of(node, struct arm_smmu_master, node); |
456 | ||
457 | if (dev_node < master->of_node) | |
458 | node = node->rb_left; | |
459 | else if (dev_node > master->of_node) | |
460 | node = node->rb_right; | |
461 | else | |
462 | return master; | |
463 | } | |
464 | ||
465 | return NULL; | |
466 | } | |
467 | ||
a9a1b0b5 WD |
468 | static struct arm_smmu_master_cfg * |
469 | find_smmu_master_cfg(struct arm_smmu_device *smmu, struct device *dev) | |
470 | { | |
471 | struct arm_smmu_master *master; | |
472 | ||
473 | if (dev_is_pci(dev)) | |
474 | return dev->archdata.iommu; | |
475 | ||
476 | master = find_smmu_master(smmu, dev->of_node); | |
477 | return master ? &master->cfg : NULL; | |
478 | } | |
479 | ||
45ae7cff WD |
480 | static int insert_smmu_master(struct arm_smmu_device *smmu, |
481 | struct arm_smmu_master *master) | |
482 | { | |
483 | struct rb_node **new, *parent; | |
484 | ||
485 | new = &smmu->masters.rb_node; | |
486 | parent = NULL; | |
487 | while (*new) { | |
2907320d MH |
488 | struct arm_smmu_master *this |
489 | = container_of(*new, struct arm_smmu_master, node); | |
45ae7cff WD |
490 | |
491 | parent = *new; | |
492 | if (master->of_node < this->of_node) | |
493 | new = &((*new)->rb_left); | |
494 | else if (master->of_node > this->of_node) | |
495 | new = &((*new)->rb_right); | |
496 | else | |
497 | return -EEXIST; | |
498 | } | |
499 | ||
500 | rb_link_node(&master->node, parent, new); | |
501 | rb_insert_color(&master->node, &smmu->masters); | |
502 | return 0; | |
503 | } | |
504 | ||
505 | static int register_smmu_master(struct arm_smmu_device *smmu, | |
506 | struct device *dev, | |
507 | struct of_phandle_args *masterspec) | |
508 | { | |
509 | int i; | |
510 | struct arm_smmu_master *master; | |
511 | ||
512 | master = find_smmu_master(smmu, masterspec->np); | |
513 | if (master) { | |
514 | dev_err(dev, | |
515 | "rejecting multiple registrations for master device %s\n", | |
516 | masterspec->np->name); | |
517 | return -EBUSY; | |
518 | } | |
519 | ||
520 | if (masterspec->args_count > MAX_MASTER_STREAMIDS) { | |
521 | dev_err(dev, | |
522 | "reached maximum number (%d) of stream IDs for master device %s\n", | |
523 | MAX_MASTER_STREAMIDS, masterspec->np->name); | |
524 | return -ENOSPC; | |
525 | } | |
526 | ||
527 | master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); | |
528 | if (!master) | |
529 | return -ENOMEM; | |
530 | ||
a9a1b0b5 WD |
531 | master->of_node = masterspec->np; |
532 | master->cfg.num_streamids = masterspec->args_count; | |
45ae7cff | 533 | |
3c8766d0 OH |
534 | for (i = 0; i < master->cfg.num_streamids; ++i) { |
535 | u16 streamid = masterspec->args[i]; | |
45ae7cff | 536 | |
3c8766d0 OH |
537 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && |
538 | (streamid >= smmu->num_mapping_groups)) { | |
539 | dev_err(dev, | |
540 | "stream ID for master device %s greater than maximum allowed (%d)\n", | |
541 | masterspec->np->name, smmu->num_mapping_groups); | |
542 | return -ERANGE; | |
543 | } | |
544 | master->cfg.streamids[i] = streamid; | |
545 | } | |
45ae7cff WD |
546 | return insert_smmu_master(smmu, master); |
547 | } | |
548 | ||
44680eed | 549 | static struct arm_smmu_device *find_smmu_for_device(struct device *dev) |
45ae7cff | 550 | { |
44680eed | 551 | struct arm_smmu_device *smmu; |
a9a1b0b5 WD |
552 | struct arm_smmu_master *master = NULL; |
553 | struct device_node *dev_node = dev_get_master_dev(dev)->of_node; | |
45ae7cff WD |
554 | |
555 | spin_lock(&arm_smmu_devices_lock); | |
44680eed | 556 | list_for_each_entry(smmu, &arm_smmu_devices, list) { |
a9a1b0b5 WD |
557 | master = find_smmu_master(smmu, dev_node); |
558 | if (master) | |
559 | break; | |
560 | } | |
45ae7cff | 561 | spin_unlock(&arm_smmu_devices_lock); |
44680eed | 562 | |
a9a1b0b5 | 563 | return master ? smmu : NULL; |
45ae7cff WD |
564 | } |
565 | ||
566 | static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) | |
567 | { | |
568 | int idx; | |
569 | ||
570 | do { | |
571 | idx = find_next_zero_bit(map, end, start); | |
572 | if (idx == end) | |
573 | return -ENOSPC; | |
574 | } while (test_and_set_bit(idx, map)); | |
575 | ||
576 | return idx; | |
577 | } | |
578 | ||
579 | static void __arm_smmu_free_bitmap(unsigned long *map, int idx) | |
580 | { | |
581 | clear_bit(idx, map); | |
582 | } | |
583 | ||
584 | /* Wait for any pending TLB invalidations to complete */ | |
585 | static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu) | |
586 | { | |
587 | int count = 0; | |
588 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
589 | ||
590 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); | |
591 | while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) | |
592 | & sTLBGSTATUS_GSACTIVE) { | |
593 | cpu_relax(); | |
594 | if (++count == TLB_LOOP_TIMEOUT) { | |
595 | dev_err_ratelimited(smmu->dev, | |
596 | "TLB sync timed out -- SMMU may be deadlocked\n"); | |
597 | return; | |
598 | } | |
599 | udelay(1); | |
600 | } | |
601 | } | |
602 | ||
44680eed | 603 | static void arm_smmu_tlb_inv_context(struct arm_smmu_domain *smmu_domain) |
1463fe44 | 604 | { |
44680eed WD |
605 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
606 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
1463fe44 WD |
607 | void __iomem *base = ARM_SMMU_GR0(smmu); |
608 | bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; | |
609 | ||
610 | if (stage1) { | |
611 | base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
ecfadb6e WD |
612 | writel_relaxed(ARM_SMMU_CB_ASID(cfg), |
613 | base + ARM_SMMU_CB_S1_TLBIASID); | |
1463fe44 WD |
614 | } else { |
615 | base = ARM_SMMU_GR0(smmu); | |
ecfadb6e WD |
616 | writel_relaxed(ARM_SMMU_CB_VMID(cfg), |
617 | base + ARM_SMMU_GR0_TLBIVMID); | |
1463fe44 WD |
618 | } |
619 | ||
620 | arm_smmu_tlb_sync(smmu); | |
621 | } | |
622 | ||
45ae7cff WD |
623 | static irqreturn_t arm_smmu_context_fault(int irq, void *dev) |
624 | { | |
625 | int flags, ret; | |
626 | u32 fsr, far, fsynr, resume; | |
627 | unsigned long iova; | |
628 | struct iommu_domain *domain = dev; | |
629 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed WD |
630 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
631 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
45ae7cff WD |
632 | void __iomem *cb_base; |
633 | ||
44680eed | 634 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
45ae7cff WD |
635 | fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); |
636 | ||
637 | if (!(fsr & FSR_FAULT)) | |
638 | return IRQ_NONE; | |
639 | ||
640 | if (fsr & FSR_IGN) | |
641 | dev_err_ratelimited(smmu->dev, | |
70c9a7db | 642 | "Unexpected context fault (fsr 0x%x)\n", |
45ae7cff WD |
643 | fsr); |
644 | ||
645 | fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); | |
646 | flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; | |
647 | ||
648 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO); | |
649 | iova = far; | |
650 | #ifdef CONFIG_64BIT | |
651 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI); | |
652 | iova |= ((unsigned long)far << 32); | |
653 | #endif | |
654 | ||
655 | if (!report_iommu_fault(domain, smmu->dev, iova, flags)) { | |
656 | ret = IRQ_HANDLED; | |
657 | resume = RESUME_RETRY; | |
658 | } else { | |
2ef0f031 AH |
659 | dev_err_ratelimited(smmu->dev, |
660 | "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n", | |
44680eed | 661 | iova, fsynr, cfg->cbndx); |
45ae7cff WD |
662 | ret = IRQ_NONE; |
663 | resume = RESUME_TERMINATE; | |
664 | } | |
665 | ||
666 | /* Clear the faulting FSR */ | |
667 | writel(fsr, cb_base + ARM_SMMU_CB_FSR); | |
668 | ||
669 | /* Retry or terminate any stalled transactions */ | |
670 | if (fsr & FSR_SS) | |
671 | writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME); | |
672 | ||
673 | return ret; | |
674 | } | |
675 | ||
676 | static irqreturn_t arm_smmu_global_fault(int irq, void *dev) | |
677 | { | |
678 | u32 gfsr, gfsynr0, gfsynr1, gfsynr2; | |
679 | struct arm_smmu_device *smmu = dev; | |
3a5df8ff | 680 | void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu); |
45ae7cff WD |
681 | |
682 | gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); | |
683 | gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); | |
684 | gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); | |
685 | gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); | |
686 | ||
3a5df8ff AH |
687 | if (!gfsr) |
688 | return IRQ_NONE; | |
689 | ||
45ae7cff WD |
690 | dev_err_ratelimited(smmu->dev, |
691 | "Unexpected global fault, this could be serious\n"); | |
692 | dev_err_ratelimited(smmu->dev, | |
693 | "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n", | |
694 | gfsr, gfsynr0, gfsynr1, gfsynr2); | |
695 | ||
696 | writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); | |
adaba320 | 697 | return IRQ_HANDLED; |
45ae7cff WD |
698 | } |
699 | ||
6dd35f45 WD |
700 | static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, |
701 | size_t size) | |
702 | { | |
703 | unsigned long offset = (unsigned long)addr & ~PAGE_MASK; | |
704 | ||
705 | ||
706 | /* Ensure new page tables are visible to the hardware walker */ | |
707 | if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) { | |
3aa80ea4 | 708 | dsb(ishst); |
6dd35f45 WD |
709 | } else { |
710 | /* | |
711 | * If the SMMU can't walk tables in the CPU caches, treat them | |
712 | * like non-coherent DMA since we need to flush the new entries | |
713 | * all the way out to memory. There's no possibility of | |
714 | * recursion here as the SMMU table walker will not be wired | |
715 | * through another SMMU. | |
716 | */ | |
717 | dma_map_page(smmu->dev, virt_to_page(addr), offset, size, | |
718 | DMA_TO_DEVICE); | |
719 | } | |
720 | } | |
721 | ||
45ae7cff WD |
722 | static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) |
723 | { | |
724 | u32 reg; | |
725 | bool stage1; | |
44680eed WD |
726 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
727 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
45ae7cff WD |
728 | void __iomem *cb_base, *gr0_base, *gr1_base; |
729 | ||
730 | gr0_base = ARM_SMMU_GR0(smmu); | |
731 | gr1_base = ARM_SMMU_GR1(smmu); | |
44680eed WD |
732 | stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
733 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
45ae7cff WD |
734 | |
735 | /* CBAR */ | |
44680eed | 736 | reg = cfg->cbar; |
45ae7cff | 737 | if (smmu->version == 1) |
2907320d | 738 | reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT; |
45ae7cff | 739 | |
57ca90f6 WD |
740 | /* |
741 | * Use the weakest shareability/memory types, so they are | |
742 | * overridden by the ttbcr/pte. | |
743 | */ | |
744 | if (stage1) { | |
745 | reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) | | |
746 | (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); | |
747 | } else { | |
44680eed | 748 | reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT; |
57ca90f6 | 749 | } |
44680eed | 750 | writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); |
45ae7cff WD |
751 | |
752 | if (smmu->version > 1) { | |
753 | /* CBA2R */ | |
754 | #ifdef CONFIG_64BIT | |
755 | reg = CBA2R_RW64_64BIT; | |
756 | #else | |
757 | reg = CBA2R_RW64_32BIT; | |
758 | #endif | |
759 | writel_relaxed(reg, | |
44680eed | 760 | gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx)); |
45ae7cff WD |
761 | |
762 | /* TTBCR2 */ | |
763 | switch (smmu->input_size) { | |
764 | case 32: | |
765 | reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT); | |
766 | break; | |
767 | case 36: | |
768 | reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT); | |
769 | break; | |
770 | case 39: | |
4d09d99d | 771 | case 40: |
45ae7cff WD |
772 | reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT); |
773 | break; | |
774 | case 42: | |
775 | reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT); | |
776 | break; | |
777 | case 44: | |
778 | reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT); | |
779 | break; | |
780 | case 48: | |
781 | reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT); | |
782 | break; | |
783 | } | |
784 | ||
785 | switch (smmu->s1_output_size) { | |
786 | case 32: | |
787 | reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT); | |
788 | break; | |
789 | case 36: | |
790 | reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT); | |
791 | break; | |
792 | case 39: | |
4d09d99d | 793 | case 40: |
45ae7cff WD |
794 | reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT); |
795 | break; | |
796 | case 42: | |
797 | reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT); | |
798 | break; | |
799 | case 44: | |
800 | reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT); | |
801 | break; | |
802 | case 48: | |
803 | reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT); | |
804 | break; | |
805 | } | |
806 | ||
807 | if (stage1) | |
808 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2); | |
809 | } | |
810 | ||
811 | /* TTBR0 */ | |
44680eed | 812 | arm_smmu_flush_pgtable(smmu, cfg->pgd, |
6dd35f45 | 813 | PTRS_PER_PGD * sizeof(pgd_t)); |
44680eed | 814 | reg = __pa(cfg->pgd); |
45ae7cff | 815 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); |
44680eed | 816 | reg = (phys_addr_t)__pa(cfg->pgd) >> 32; |
1463fe44 | 817 | if (stage1) |
44680eed | 818 | reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; |
45ae7cff | 819 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); |
45ae7cff WD |
820 | |
821 | /* | |
822 | * TTBCR | |
823 | * We use long descriptor, with inner-shareable WBWA tables in TTBR0. | |
824 | */ | |
825 | if (smmu->version > 1) { | |
826 | if (PAGE_SIZE == SZ_4K) | |
827 | reg = TTBCR_TG0_4K; | |
828 | else | |
829 | reg = TTBCR_TG0_64K; | |
830 | ||
831 | if (!stage1) { | |
a65217a4 WD |
832 | reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT; |
833 | ||
45ae7cff WD |
834 | switch (smmu->s2_output_size) { |
835 | case 32: | |
836 | reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT); | |
837 | break; | |
838 | case 36: | |
839 | reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT); | |
840 | break; | |
841 | case 40: | |
842 | reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT); | |
843 | break; | |
844 | case 42: | |
845 | reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT); | |
846 | break; | |
847 | case 44: | |
848 | reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT); | |
849 | break; | |
850 | case 48: | |
851 | reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT); | |
852 | break; | |
853 | } | |
854 | } else { | |
a65217a4 | 855 | reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT; |
45ae7cff WD |
856 | } |
857 | } else { | |
858 | reg = 0; | |
859 | } | |
860 | ||
861 | reg |= TTBCR_EAE | | |
862 | (TTBCR_SH_IS << TTBCR_SH0_SHIFT) | | |
863 | (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) | | |
1fc870c7 OH |
864 | (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT); |
865 | ||
866 | if (!stage1) | |
867 | reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); | |
868 | ||
45ae7cff WD |
869 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); |
870 | ||
871 | /* MAIR0 (stage-1 only) */ | |
872 | if (stage1) { | |
873 | reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) | | |
874 | (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) | | |
875 | (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV)); | |
876 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0); | |
877 | } | |
878 | ||
45ae7cff WD |
879 | /* SCTLR */ |
880 | reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP; | |
881 | if (stage1) | |
882 | reg |= SCTLR_S1_ASIDPNE; | |
883 | #ifdef __BIG_ENDIAN | |
884 | reg |= SCTLR_E; | |
885 | #endif | |
25724841 | 886 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); |
45ae7cff WD |
887 | } |
888 | ||
889 | static int arm_smmu_init_domain_context(struct iommu_domain *domain, | |
44680eed | 890 | struct arm_smmu_device *smmu) |
45ae7cff | 891 | { |
a18037b2 MH |
892 | int irq, start, ret = 0; |
893 | unsigned long flags; | |
45ae7cff | 894 | struct arm_smmu_domain *smmu_domain = domain->priv; |
44680eed | 895 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
45ae7cff | 896 | |
a18037b2 MH |
897 | spin_lock_irqsave(&smmu_domain->lock, flags); |
898 | if (smmu_domain->smmu) | |
899 | goto out_unlock; | |
900 | ||
45ae7cff WD |
901 | if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) { |
902 | /* | |
903 | * We will likely want to change this if/when KVM gets | |
904 | * involved. | |
905 | */ | |
44680eed | 906 | cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; |
45ae7cff | 907 | start = smmu->num_s2_context_banks; |
9c5c92e3 | 908 | } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) { |
44680eed | 909 | cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; |
45ae7cff | 910 | start = smmu->num_s2_context_banks; |
9c5c92e3 WD |
911 | } else { |
912 | cfg->cbar = CBAR_TYPE_S2_TRANS; | |
913 | start = 0; | |
45ae7cff WD |
914 | } |
915 | ||
916 | ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, | |
917 | smmu->num_context_banks); | |
918 | if (IS_ERR_VALUE(ret)) | |
a18037b2 | 919 | goto out_unlock; |
45ae7cff | 920 | |
44680eed | 921 | cfg->cbndx = ret; |
45ae7cff | 922 | if (smmu->version == 1) { |
44680eed WD |
923 | cfg->irptndx = atomic_inc_return(&smmu->irptndx); |
924 | cfg->irptndx %= smmu->num_context_irqs; | |
45ae7cff | 925 | } else { |
44680eed | 926 | cfg->irptndx = cfg->cbndx; |
45ae7cff WD |
927 | } |
928 | ||
a18037b2 MH |
929 | ACCESS_ONCE(smmu_domain->smmu) = smmu; |
930 | arm_smmu_init_context_bank(smmu_domain); | |
931 | spin_unlock_irqrestore(&smmu_domain->lock, flags); | |
932 | ||
44680eed | 933 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; |
45ae7cff WD |
934 | ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED, |
935 | "arm-smmu-context-fault", domain); | |
936 | if (IS_ERR_VALUE(ret)) { | |
937 | dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", | |
44680eed WD |
938 | cfg->irptndx, irq); |
939 | cfg->irptndx = INVALID_IRPTNDX; | |
45ae7cff WD |
940 | } |
941 | ||
a9a1b0b5 | 942 | return 0; |
45ae7cff | 943 | |
a18037b2 MH |
944 | out_unlock: |
945 | spin_unlock_irqrestore(&smmu_domain->lock, flags); | |
45ae7cff WD |
946 | return ret; |
947 | } | |
948 | ||
949 | static void arm_smmu_destroy_domain_context(struct iommu_domain *domain) | |
950 | { | |
951 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed WD |
952 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
953 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
1463fe44 | 954 | void __iomem *cb_base; |
45ae7cff WD |
955 | int irq; |
956 | ||
957 | if (!smmu) | |
958 | return; | |
959 | ||
1463fe44 | 960 | /* Disable the context bank and nuke the TLB before freeing it. */ |
44680eed | 961 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
1463fe44 | 962 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); |
44680eed | 963 | arm_smmu_tlb_inv_context(smmu_domain); |
1463fe44 | 964 | |
44680eed WD |
965 | if (cfg->irptndx != INVALID_IRPTNDX) { |
966 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; | |
45ae7cff WD |
967 | free_irq(irq, domain); |
968 | } | |
969 | ||
44680eed | 970 | __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); |
45ae7cff WD |
971 | } |
972 | ||
973 | static int arm_smmu_domain_init(struct iommu_domain *domain) | |
974 | { | |
975 | struct arm_smmu_domain *smmu_domain; | |
976 | pgd_t *pgd; | |
977 | ||
978 | /* | |
979 | * Allocate the domain and initialise some of its data structures. | |
980 | * We can't really do anything meaningful until we've added a | |
981 | * master. | |
982 | */ | |
983 | smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); | |
984 | if (!smmu_domain) | |
985 | return -ENOMEM; | |
986 | ||
2907320d | 987 | pgd = kcalloc(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL); |
45ae7cff WD |
988 | if (!pgd) |
989 | goto out_free_domain; | |
44680eed | 990 | smmu_domain->cfg.pgd = pgd; |
45ae7cff | 991 | |
c9d09e27 | 992 | spin_lock_init(&smmu_domain->lock); |
45ae7cff WD |
993 | domain->priv = smmu_domain; |
994 | return 0; | |
995 | ||
996 | out_free_domain: | |
997 | kfree(smmu_domain); | |
998 | return -ENOMEM; | |
999 | } | |
1000 | ||
1001 | static void arm_smmu_free_ptes(pmd_t *pmd) | |
1002 | { | |
1003 | pgtable_t table = pmd_pgtable(*pmd); | |
2907320d | 1004 | |
45ae7cff WD |
1005 | __free_page(table); |
1006 | } | |
1007 | ||
1008 | static void arm_smmu_free_pmds(pud_t *pud) | |
1009 | { | |
1010 | int i; | |
1011 | pmd_t *pmd, *pmd_base = pmd_offset(pud, 0); | |
1012 | ||
1013 | pmd = pmd_base; | |
1014 | for (i = 0; i < PTRS_PER_PMD; ++i) { | |
1015 | if (pmd_none(*pmd)) | |
1016 | continue; | |
1017 | ||
1018 | arm_smmu_free_ptes(pmd); | |
1019 | pmd++; | |
1020 | } | |
1021 | ||
1022 | pmd_free(NULL, pmd_base); | |
1023 | } | |
1024 | ||
1025 | static void arm_smmu_free_puds(pgd_t *pgd) | |
1026 | { | |
1027 | int i; | |
1028 | pud_t *pud, *pud_base = pud_offset(pgd, 0); | |
1029 | ||
1030 | pud = pud_base; | |
1031 | for (i = 0; i < PTRS_PER_PUD; ++i) { | |
1032 | if (pud_none(*pud)) | |
1033 | continue; | |
1034 | ||
1035 | arm_smmu_free_pmds(pud); | |
1036 | pud++; | |
1037 | } | |
1038 | ||
1039 | pud_free(NULL, pud_base); | |
1040 | } | |
1041 | ||
1042 | static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain) | |
1043 | { | |
1044 | int i; | |
44680eed WD |
1045 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
1046 | pgd_t *pgd, *pgd_base = cfg->pgd; | |
45ae7cff WD |
1047 | |
1048 | /* | |
1049 | * Recursively free the page tables for this domain. We don't | |
34fb4b37 WD |
1050 | * care about speculative TLB filling because the tables should |
1051 | * not be active in any context bank at this point (SCTLR.M is 0). | |
45ae7cff WD |
1052 | */ |
1053 | pgd = pgd_base; | |
1054 | for (i = 0; i < PTRS_PER_PGD; ++i) { | |
1055 | if (pgd_none(*pgd)) | |
1056 | continue; | |
1057 | arm_smmu_free_puds(pgd); | |
1058 | pgd++; | |
1059 | } | |
1060 | ||
1061 | kfree(pgd_base); | |
1062 | } | |
1063 | ||
1064 | static void arm_smmu_domain_destroy(struct iommu_domain *domain) | |
1065 | { | |
1066 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
1463fe44 WD |
1067 | |
1068 | /* | |
1069 | * Free the domain resources. We assume that all devices have | |
1070 | * already been detached. | |
1071 | */ | |
45ae7cff WD |
1072 | arm_smmu_destroy_domain_context(domain); |
1073 | arm_smmu_free_pgtables(smmu_domain); | |
1074 | kfree(smmu_domain); | |
1075 | } | |
1076 | ||
1077 | static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1078 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1079 | { |
1080 | int i; | |
1081 | struct arm_smmu_smr *smrs; | |
1082 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1083 | ||
1084 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)) | |
1085 | return 0; | |
1086 | ||
a9a1b0b5 | 1087 | if (cfg->smrs) |
45ae7cff WD |
1088 | return -EEXIST; |
1089 | ||
2907320d | 1090 | smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL); |
45ae7cff | 1091 | if (!smrs) { |
a9a1b0b5 WD |
1092 | dev_err(smmu->dev, "failed to allocate %d SMRs\n", |
1093 | cfg->num_streamids); | |
45ae7cff WD |
1094 | return -ENOMEM; |
1095 | } | |
1096 | ||
44680eed | 1097 | /* Allocate the SMRs on the SMMU */ |
a9a1b0b5 | 1098 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1099 | int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0, |
1100 | smmu->num_mapping_groups); | |
1101 | if (IS_ERR_VALUE(idx)) { | |
1102 | dev_err(smmu->dev, "failed to allocate free SMR\n"); | |
1103 | goto err_free_smrs; | |
1104 | } | |
1105 | ||
1106 | smrs[i] = (struct arm_smmu_smr) { | |
1107 | .idx = idx, | |
1108 | .mask = 0, /* We don't currently share SMRs */ | |
a9a1b0b5 | 1109 | .id = cfg->streamids[i], |
45ae7cff WD |
1110 | }; |
1111 | } | |
1112 | ||
1113 | /* It worked! Now, poke the actual hardware */ | |
a9a1b0b5 | 1114 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1115 | u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT | |
1116 | smrs[i].mask << SMR_MASK_SHIFT; | |
1117 | writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx)); | |
1118 | } | |
1119 | ||
a9a1b0b5 | 1120 | cfg->smrs = smrs; |
45ae7cff WD |
1121 | return 0; |
1122 | ||
1123 | err_free_smrs: | |
1124 | while (--i >= 0) | |
1125 | __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx); | |
1126 | kfree(smrs); | |
1127 | return -ENOSPC; | |
1128 | } | |
1129 | ||
1130 | static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1131 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1132 | { |
1133 | int i; | |
1134 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
a9a1b0b5 | 1135 | struct arm_smmu_smr *smrs = cfg->smrs; |
45ae7cff | 1136 | |
43b412be WD |
1137 | if (!smrs) |
1138 | return; | |
1139 | ||
45ae7cff | 1140 | /* Invalidate the SMRs before freeing back to the allocator */ |
a9a1b0b5 | 1141 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff | 1142 | u8 idx = smrs[i].idx; |
2907320d | 1143 | |
45ae7cff WD |
1144 | writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); |
1145 | __arm_smmu_free_bitmap(smmu->smr_map, idx); | |
1146 | } | |
1147 | ||
a9a1b0b5 | 1148 | cfg->smrs = NULL; |
45ae7cff WD |
1149 | kfree(smrs); |
1150 | } | |
1151 | ||
45ae7cff | 1152 | static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, |
a9a1b0b5 | 1153 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1154 | { |
1155 | int i, ret; | |
44680eed | 1156 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
45ae7cff WD |
1157 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
1158 | ||
a9a1b0b5 | 1159 | ret = arm_smmu_master_configure_smrs(smmu, cfg); |
45ae7cff WD |
1160 | if (ret) |
1161 | return ret; | |
1162 | ||
a9a1b0b5 | 1163 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff | 1164 | u32 idx, s2cr; |
2907320d | 1165 | |
a9a1b0b5 | 1166 | idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; |
6069d23c | 1167 | s2cr = S2CR_TYPE_TRANS | |
44680eed | 1168 | (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT); |
45ae7cff WD |
1169 | writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx)); |
1170 | } | |
1171 | ||
1172 | return 0; | |
1173 | } | |
1174 | ||
1175 | static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain, | |
a9a1b0b5 | 1176 | struct arm_smmu_master_cfg *cfg) |
45ae7cff | 1177 | { |
43b412be | 1178 | int i; |
44680eed | 1179 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
43b412be | 1180 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
45ae7cff WD |
1181 | |
1182 | /* | |
1183 | * We *must* clear the S2CR first, because freeing the SMR means | |
1184 | * that it can be re-allocated immediately. | |
1185 | */ | |
43b412be WD |
1186 | for (i = 0; i < cfg->num_streamids; ++i) { |
1187 | u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; | |
1188 | ||
1189 | writel_relaxed(S2CR_TYPE_BYPASS, | |
1190 | gr0_base + ARM_SMMU_GR0_S2CR(idx)); | |
1191 | } | |
1192 | ||
a9a1b0b5 | 1193 | arm_smmu_master_free_smrs(smmu, cfg); |
45ae7cff WD |
1194 | } |
1195 | ||
1196 | static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1197 | { | |
a18037b2 | 1198 | int ret; |
45ae7cff | 1199 | struct arm_smmu_domain *smmu_domain = domain->priv; |
a18037b2 | 1200 | struct arm_smmu_device *smmu, *dom_smmu; |
a9a1b0b5 | 1201 | struct arm_smmu_master_cfg *cfg; |
45ae7cff | 1202 | |
44680eed WD |
1203 | smmu = dev_get_master_dev(dev)->archdata.iommu; |
1204 | if (!smmu) { | |
45ae7cff WD |
1205 | dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); |
1206 | return -ENXIO; | |
1207 | } | |
1208 | ||
1209 | /* | |
44680eed WD |
1210 | * Sanity check the domain. We don't support domains across |
1211 | * different SMMUs. | |
45ae7cff | 1212 | */ |
a18037b2 MH |
1213 | dom_smmu = ACCESS_ONCE(smmu_domain->smmu); |
1214 | if (!dom_smmu) { | |
45ae7cff | 1215 | /* Now that we have a master, we can finalise the domain */ |
44680eed | 1216 | ret = arm_smmu_init_domain_context(domain, smmu); |
45ae7cff | 1217 | if (IS_ERR_VALUE(ret)) |
a18037b2 MH |
1218 | return ret; |
1219 | ||
1220 | dom_smmu = smmu_domain->smmu; | |
1221 | } | |
1222 | ||
1223 | if (dom_smmu != smmu) { | |
45ae7cff WD |
1224 | dev_err(dev, |
1225 | "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", | |
a18037b2 MH |
1226 | dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev)); |
1227 | return -EINVAL; | |
45ae7cff | 1228 | } |
45ae7cff WD |
1229 | |
1230 | /* Looks ok, so add the device to the domain */ | |
44680eed | 1231 | cfg = find_smmu_master_cfg(smmu_domain->smmu, dev); |
a9a1b0b5 | 1232 | if (!cfg) |
45ae7cff WD |
1233 | return -ENODEV; |
1234 | ||
a9a1b0b5 | 1235 | return arm_smmu_domain_add_master(smmu_domain, cfg); |
45ae7cff WD |
1236 | } |
1237 | ||
1238 | static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) | |
1239 | { | |
1240 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
a9a1b0b5 | 1241 | struct arm_smmu_master_cfg *cfg; |
45ae7cff | 1242 | |
44680eed | 1243 | cfg = find_smmu_master_cfg(smmu_domain->smmu, dev); |
a9a1b0b5 WD |
1244 | if (cfg) |
1245 | arm_smmu_domain_remove_master(smmu_domain, cfg); | |
45ae7cff WD |
1246 | } |
1247 | ||
45ae7cff WD |
1248 | static bool arm_smmu_pte_is_contiguous_range(unsigned long addr, |
1249 | unsigned long end) | |
1250 | { | |
1251 | return !(addr & ~ARM_SMMU_PTE_CONT_MASK) && | |
1252 | (addr + ARM_SMMU_PTE_CONT_SIZE <= end); | |
1253 | } | |
1254 | ||
1255 | static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd, | |
1256 | unsigned long addr, unsigned long end, | |
b410aed9 | 1257 | unsigned long pfn, int prot, int stage) |
45ae7cff WD |
1258 | { |
1259 | pte_t *pte, *start; | |
cf2d45b1 | 1260 | pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN; |
45ae7cff WD |
1261 | |
1262 | if (pmd_none(*pmd)) { | |
1263 | /* Allocate a new set of tables */ | |
c9d09e27 | 1264 | pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO); |
2907320d | 1265 | |
45ae7cff WD |
1266 | if (!table) |
1267 | return -ENOMEM; | |
1268 | ||
6dd35f45 | 1269 | arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE); |
45ae7cff WD |
1270 | pmd_populate(NULL, pmd, table); |
1271 | arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd)); | |
1272 | } | |
1273 | ||
1274 | if (stage == 1) { | |
1463fe44 | 1275 | pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG; |
b410aed9 | 1276 | if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ)) |
45ae7cff WD |
1277 | pteval |= ARM_SMMU_PTE_AP_RDONLY; |
1278 | ||
b410aed9 | 1279 | if (prot & IOMMU_CACHE) |
45ae7cff WD |
1280 | pteval |= (MAIR_ATTR_IDX_CACHE << |
1281 | ARM_SMMU_PTE_ATTRINDX_SHIFT); | |
1282 | } else { | |
1283 | pteval |= ARM_SMMU_PTE_HAP_FAULT; | |
b410aed9 | 1284 | if (prot & IOMMU_READ) |
45ae7cff | 1285 | pteval |= ARM_SMMU_PTE_HAP_READ; |
b410aed9 | 1286 | if (prot & IOMMU_WRITE) |
45ae7cff | 1287 | pteval |= ARM_SMMU_PTE_HAP_WRITE; |
b410aed9 | 1288 | if (prot & IOMMU_CACHE) |
45ae7cff WD |
1289 | pteval |= ARM_SMMU_PTE_MEMATTR_OIWB; |
1290 | else | |
1291 | pteval |= ARM_SMMU_PTE_MEMATTR_NC; | |
1292 | } | |
1293 | ||
1294 | /* If no access, create a faulting entry to avoid TLB fills */ | |
b410aed9 | 1295 | if (prot & IOMMU_EXEC) |
cf2d45b1 | 1296 | pteval &= ~ARM_SMMU_PTE_XN; |
b410aed9 | 1297 | else if (!(prot & (IOMMU_READ | IOMMU_WRITE))) |
45ae7cff WD |
1298 | pteval &= ~ARM_SMMU_PTE_PAGE; |
1299 | ||
1300 | pteval |= ARM_SMMU_PTE_SH_IS; | |
1301 | start = pmd_page_vaddr(*pmd) + pte_index(addr); | |
1302 | pte = start; | |
1303 | ||
1304 | /* | |
1305 | * Install the page table entries. This is fairly complicated | |
1306 | * since we attempt to make use of the contiguous hint in the | |
1307 | * ptes where possible. The contiguous hint indicates a series | |
1308 | * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically | |
1309 | * contiguous region with the following constraints: | |
1310 | * | |
1311 | * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE | |
1312 | * - Each pte in the region has the contiguous hint bit set | |
1313 | * | |
1314 | * This complicates unmapping (also handled by this code, when | |
1315 | * neither IOMMU_READ or IOMMU_WRITE are set) because it is | |
1316 | * possible, yet highly unlikely, that a client may unmap only | |
1317 | * part of a contiguous range. This requires clearing of the | |
1318 | * contiguous hint bits in the range before installing the new | |
1319 | * faulting entries. | |
1320 | * | |
1321 | * Note that re-mapping an address range without first unmapping | |
1322 | * it is not supported, so TLB invalidation is not required here | |
1323 | * and is instead performed at unmap and domain-init time. | |
1324 | */ | |
1325 | do { | |
1326 | int i = 1; | |
2907320d | 1327 | |
45ae7cff WD |
1328 | pteval &= ~ARM_SMMU_PTE_CONT; |
1329 | ||
1330 | if (arm_smmu_pte_is_contiguous_range(addr, end)) { | |
1331 | i = ARM_SMMU_PTE_CONT_ENTRIES; | |
1332 | pteval |= ARM_SMMU_PTE_CONT; | |
1333 | } else if (pte_val(*pte) & | |
1334 | (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) { | |
1335 | int j; | |
1336 | pte_t *cont_start; | |
1337 | unsigned long idx = pte_index(addr); | |
1338 | ||
1339 | idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1); | |
1340 | cont_start = pmd_page_vaddr(*pmd) + idx; | |
1341 | for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j) | |
2907320d MH |
1342 | pte_val(*(cont_start + j)) &= |
1343 | ~ARM_SMMU_PTE_CONT; | |
45ae7cff WD |
1344 | |
1345 | arm_smmu_flush_pgtable(smmu, cont_start, | |
1346 | sizeof(*pte) * | |
1347 | ARM_SMMU_PTE_CONT_ENTRIES); | |
1348 | } | |
1349 | ||
1350 | do { | |
1351 | *pte = pfn_pte(pfn, __pgprot(pteval)); | |
1352 | } while (pte++, pfn++, addr += PAGE_SIZE, --i); | |
1353 | } while (addr != end); | |
1354 | ||
1355 | arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start)); | |
1356 | return 0; | |
1357 | } | |
1358 | ||
1359 | static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud, | |
1360 | unsigned long addr, unsigned long end, | |
b410aed9 | 1361 | phys_addr_t phys, int prot, int stage) |
45ae7cff WD |
1362 | { |
1363 | int ret; | |
1364 | pmd_t *pmd; | |
1365 | unsigned long next, pfn = __phys_to_pfn(phys); | |
1366 | ||
1367 | #ifndef __PAGETABLE_PMD_FOLDED | |
1368 | if (pud_none(*pud)) { | |
c9d09e27 | 1369 | pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC); |
45ae7cff WD |
1370 | if (!pmd) |
1371 | return -ENOMEM; | |
97a64420 | 1372 | |
6dd35f45 | 1373 | arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE); |
97a64420 YZ |
1374 | pud_populate(NULL, pud, pmd); |
1375 | arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud)); | |
1376 | ||
1377 | pmd += pmd_index(addr); | |
45ae7cff WD |
1378 | } else |
1379 | #endif | |
1380 | pmd = pmd_offset(pud, addr); | |
1381 | ||
1382 | do { | |
1383 | next = pmd_addr_end(addr, end); | |
aca1bc45 | 1384 | ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, next, pfn, |
b410aed9 | 1385 | prot, stage); |
45ae7cff WD |
1386 | phys += next - addr; |
1387 | } while (pmd++, addr = next, addr < end); | |
1388 | ||
1389 | return ret; | |
1390 | } | |
1391 | ||
1392 | static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd, | |
1393 | unsigned long addr, unsigned long end, | |
b410aed9 | 1394 | phys_addr_t phys, int prot, int stage) |
45ae7cff WD |
1395 | { |
1396 | int ret = 0; | |
1397 | pud_t *pud; | |
1398 | unsigned long next; | |
1399 | ||
1400 | #ifndef __PAGETABLE_PUD_FOLDED | |
1401 | if (pgd_none(*pgd)) { | |
c9d09e27 | 1402 | pud = (pud_t *)get_zeroed_page(GFP_ATOMIC); |
45ae7cff WD |
1403 | if (!pud) |
1404 | return -ENOMEM; | |
97a64420 | 1405 | |
6dd35f45 | 1406 | arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE); |
97a64420 YZ |
1407 | pgd_populate(NULL, pgd, pud); |
1408 | arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd)); | |
1409 | ||
1410 | pud += pud_index(addr); | |
45ae7cff WD |
1411 | } else |
1412 | #endif | |
1413 | pud = pud_offset(pgd, addr); | |
1414 | ||
1415 | do { | |
1416 | next = pud_addr_end(addr, end); | |
1417 | ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys, | |
b410aed9 | 1418 | prot, stage); |
45ae7cff WD |
1419 | phys += next - addr; |
1420 | } while (pud++, addr = next, addr < end); | |
1421 | ||
1422 | return ret; | |
1423 | } | |
1424 | ||
1425 | static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain, | |
1426 | unsigned long iova, phys_addr_t paddr, | |
b410aed9 | 1427 | size_t size, int prot) |
45ae7cff WD |
1428 | { |
1429 | int ret, stage; | |
1430 | unsigned long end; | |
1431 | phys_addr_t input_mask, output_mask; | |
44680eed WD |
1432 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
1433 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
1434 | pgd_t *pgd = cfg->pgd; | |
b410aed9 | 1435 | unsigned long flags; |
45ae7cff | 1436 | |
44680eed | 1437 | if (cfg->cbar == CBAR_TYPE_S2_TRANS) { |
45ae7cff WD |
1438 | stage = 2; |
1439 | output_mask = (1ULL << smmu->s2_output_size) - 1; | |
1440 | } else { | |
1441 | stage = 1; | |
1442 | output_mask = (1ULL << smmu->s1_output_size) - 1; | |
1443 | } | |
1444 | ||
1445 | if (!pgd) | |
1446 | return -EINVAL; | |
1447 | ||
1448 | if (size & ~PAGE_MASK) | |
1449 | return -EINVAL; | |
1450 | ||
1451 | input_mask = (1ULL << smmu->input_size) - 1; | |
1452 | if ((phys_addr_t)iova & ~input_mask) | |
1453 | return -ERANGE; | |
1454 | ||
1455 | if (paddr & ~output_mask) | |
1456 | return -ERANGE; | |
1457 | ||
b410aed9 | 1458 | spin_lock_irqsave(&smmu_domain->lock, flags); |
45ae7cff WD |
1459 | pgd += pgd_index(iova); |
1460 | end = iova + size; | |
1461 | do { | |
1462 | unsigned long next = pgd_addr_end(iova, end); | |
1463 | ||
1464 | ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr, | |
b410aed9 | 1465 | prot, stage); |
45ae7cff WD |
1466 | if (ret) |
1467 | goto out_unlock; | |
1468 | ||
1469 | paddr += next - iova; | |
1470 | iova = next; | |
1471 | } while (pgd++, iova != end); | |
1472 | ||
1473 | out_unlock: | |
b410aed9 | 1474 | spin_unlock_irqrestore(&smmu_domain->lock, flags); |
45ae7cff | 1475 | |
45ae7cff WD |
1476 | return ret; |
1477 | } | |
1478 | ||
1479 | static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, | |
b410aed9 | 1480 | phys_addr_t paddr, size_t size, int prot) |
45ae7cff WD |
1481 | { |
1482 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
45ae7cff | 1483 | |
5552ecdb | 1484 | if (!smmu_domain) |
45ae7cff WD |
1485 | return -ENODEV; |
1486 | ||
b410aed9 | 1487 | return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot); |
45ae7cff WD |
1488 | } |
1489 | ||
1490 | static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, | |
1491 | size_t size) | |
1492 | { | |
1493 | int ret; | |
1494 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
45ae7cff WD |
1495 | |
1496 | ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0); | |
44680eed | 1497 | arm_smmu_tlb_inv_context(smmu_domain); |
16c50dcf | 1498 | return ret ? 0 : size; |
45ae7cff WD |
1499 | } |
1500 | ||
1501 | static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, | |
1502 | dma_addr_t iova) | |
1503 | { | |
a44a9791 WD |
1504 | pgd_t *pgdp, pgd; |
1505 | pud_t pud; | |
1506 | pmd_t pmd; | |
1507 | pte_t pte; | |
45ae7cff | 1508 | struct arm_smmu_domain *smmu_domain = domain->priv; |
44680eed | 1509 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
45ae7cff | 1510 | |
44680eed | 1511 | pgdp = cfg->pgd; |
a44a9791 WD |
1512 | if (!pgdp) |
1513 | return 0; | |
45ae7cff | 1514 | |
a44a9791 WD |
1515 | pgd = *(pgdp + pgd_index(iova)); |
1516 | if (pgd_none(pgd)) | |
1517 | return 0; | |
45ae7cff | 1518 | |
a44a9791 WD |
1519 | pud = *pud_offset(&pgd, iova); |
1520 | if (pud_none(pud)) | |
1521 | return 0; | |
45ae7cff | 1522 | |
a44a9791 WD |
1523 | pmd = *pmd_offset(&pud, iova); |
1524 | if (pmd_none(pmd)) | |
1525 | return 0; | |
45ae7cff | 1526 | |
a44a9791 | 1527 | pte = *(pmd_page_vaddr(pmd) + pte_index(iova)); |
45ae7cff | 1528 | if (pte_none(pte)) |
a44a9791 | 1529 | return 0; |
45ae7cff | 1530 | |
a44a9791 | 1531 | return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK); |
45ae7cff WD |
1532 | } |
1533 | ||
1534 | static int arm_smmu_domain_has_cap(struct iommu_domain *domain, | |
1535 | unsigned long cap) | |
1536 | { | |
45ae7cff | 1537 | struct arm_smmu_domain *smmu_domain = domain->priv; |
d3bca166 WD |
1538 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
1539 | u32 features = smmu ? smmu->features : 0; | |
d0948945 WD |
1540 | |
1541 | switch (cap) { | |
1542 | case IOMMU_CAP_CACHE_COHERENCY: | |
1543 | return features & ARM_SMMU_FEAT_COHERENT_WALK; | |
1544 | case IOMMU_CAP_INTR_REMAP: | |
1545 | return 1; /* MSIs are just memory writes */ | |
1546 | default: | |
1547 | return 0; | |
1548 | } | |
45ae7cff | 1549 | } |
45ae7cff | 1550 | |
a9a1b0b5 WD |
1551 | static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data) |
1552 | { | |
1553 | *((u16 *)data) = alias; | |
1554 | return 0; /* Continue walking */ | |
45ae7cff WD |
1555 | } |
1556 | ||
1557 | static int arm_smmu_add_device(struct device *dev) | |
1558 | { | |
a9a1b0b5 | 1559 | struct arm_smmu_device *smmu; |
5fc63a7c AM |
1560 | struct iommu_group *group; |
1561 | int ret; | |
1562 | ||
1563 | if (dev->archdata.iommu) { | |
1564 | dev_warn(dev, "IOMMU driver already assigned to device\n"); | |
1565 | return -EINVAL; | |
1566 | } | |
45ae7cff | 1567 | |
44680eed | 1568 | smmu = find_smmu_for_device(dev); |
a9a1b0b5 | 1569 | if (!smmu) |
45ae7cff WD |
1570 | return -ENODEV; |
1571 | ||
5fc63a7c AM |
1572 | group = iommu_group_alloc(); |
1573 | if (IS_ERR(group)) { | |
1574 | dev_err(dev, "Failed to allocate IOMMU group\n"); | |
1575 | return PTR_ERR(group); | |
1576 | } | |
1577 | ||
a9a1b0b5 WD |
1578 | if (dev_is_pci(dev)) { |
1579 | struct arm_smmu_master_cfg *cfg; | |
1580 | struct pci_dev *pdev = to_pci_dev(dev); | |
1581 | ||
1582 | cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); | |
1583 | if (!cfg) { | |
1584 | ret = -ENOMEM; | |
1585 | goto out_put_group; | |
1586 | } | |
1587 | ||
1588 | cfg->num_streamids = 1; | |
1589 | /* | |
1590 | * Assume Stream ID == Requester ID for now. | |
1591 | * We need a way to describe the ID mappings in FDT. | |
1592 | */ | |
1593 | pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, | |
1594 | &cfg->streamids[0]); | |
1595 | dev->archdata.iommu = cfg; | |
1596 | } else { | |
1597 | dev->archdata.iommu = smmu; | |
1598 | } | |
1599 | ||
5fc63a7c | 1600 | ret = iommu_group_add_device(group, dev); |
5fc63a7c | 1601 | |
a9a1b0b5 WD |
1602 | out_put_group: |
1603 | iommu_group_put(group); | |
5fc63a7c | 1604 | return ret; |
45ae7cff WD |
1605 | } |
1606 | ||
1607 | static void arm_smmu_remove_device(struct device *dev) | |
1608 | { | |
a9a1b0b5 WD |
1609 | if (dev_is_pci(dev)) |
1610 | kfree(dev->archdata.iommu); | |
1611 | ||
45ae7cff | 1612 | dev->archdata.iommu = NULL; |
5fc63a7c | 1613 | iommu_group_remove_device(dev); |
45ae7cff WD |
1614 | } |
1615 | ||
b22f6434 | 1616 | static const struct iommu_ops arm_smmu_ops = { |
45ae7cff WD |
1617 | .domain_init = arm_smmu_domain_init, |
1618 | .domain_destroy = arm_smmu_domain_destroy, | |
1619 | .attach_dev = arm_smmu_attach_dev, | |
1620 | .detach_dev = arm_smmu_detach_dev, | |
1621 | .map = arm_smmu_map, | |
1622 | .unmap = arm_smmu_unmap, | |
1623 | .iova_to_phys = arm_smmu_iova_to_phys, | |
1624 | .domain_has_cap = arm_smmu_domain_has_cap, | |
1625 | .add_device = arm_smmu_add_device, | |
1626 | .remove_device = arm_smmu_remove_device, | |
1627 | .pgsize_bitmap = (SECTION_SIZE | | |
1628 | ARM_SMMU_PTE_CONT_SIZE | | |
1629 | PAGE_SIZE), | |
1630 | }; | |
1631 | ||
1632 | static void arm_smmu_device_reset(struct arm_smmu_device *smmu) | |
1633 | { | |
1634 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
659db6f6 | 1635 | void __iomem *cb_base; |
45ae7cff | 1636 | int i = 0; |
659db6f6 AH |
1637 | u32 reg; |
1638 | ||
3a5df8ff AH |
1639 | /* clear global FSR */ |
1640 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); | |
1641 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); | |
45ae7cff WD |
1642 | |
1643 | /* Mark all SMRn as invalid and all S2CRn as bypass */ | |
1644 | for (i = 0; i < smmu->num_mapping_groups; ++i) { | |
3c8766d0 | 1645 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i)); |
2907320d MH |
1646 | writel_relaxed(S2CR_TYPE_BYPASS, |
1647 | gr0_base + ARM_SMMU_GR0_S2CR(i)); | |
45ae7cff WD |
1648 | } |
1649 | ||
659db6f6 AH |
1650 | /* Make sure all context banks are disabled and clear CB_FSR */ |
1651 | for (i = 0; i < smmu->num_context_banks; ++i) { | |
1652 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i); | |
1653 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); | |
1654 | writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR); | |
1655 | } | |
1463fe44 | 1656 | |
45ae7cff WD |
1657 | /* Invalidate the TLB, just in case */ |
1658 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL); | |
1659 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); | |
1660 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH); | |
1661 | ||
3a5df8ff | 1662 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
659db6f6 | 1663 | |
45ae7cff | 1664 | /* Enable fault reporting */ |
659db6f6 | 1665 | reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE); |
45ae7cff WD |
1666 | |
1667 | /* Disable TLB broadcasting. */ | |
659db6f6 | 1668 | reg |= (sCR0_VMIDPNE | sCR0_PTM); |
45ae7cff WD |
1669 | |
1670 | /* Enable client access, but bypass when no mapping is found */ | |
659db6f6 | 1671 | reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG); |
45ae7cff WD |
1672 | |
1673 | /* Disable forced broadcasting */ | |
659db6f6 | 1674 | reg &= ~sCR0_FB; |
45ae7cff WD |
1675 | |
1676 | /* Don't upgrade barriers */ | |
659db6f6 | 1677 | reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT); |
45ae7cff WD |
1678 | |
1679 | /* Push the button */ | |
1680 | arm_smmu_tlb_sync(smmu); | |
3a5df8ff | 1681 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
45ae7cff WD |
1682 | } |
1683 | ||
1684 | static int arm_smmu_id_size_to_bits(int size) | |
1685 | { | |
1686 | switch (size) { | |
1687 | case 0: | |
1688 | return 32; | |
1689 | case 1: | |
1690 | return 36; | |
1691 | case 2: | |
1692 | return 40; | |
1693 | case 3: | |
1694 | return 42; | |
1695 | case 4: | |
1696 | return 44; | |
1697 | case 5: | |
1698 | default: | |
1699 | return 48; | |
1700 | } | |
1701 | } | |
1702 | ||
1703 | static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) | |
1704 | { | |
1705 | unsigned long size; | |
1706 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1707 | u32 id; | |
1708 | ||
1709 | dev_notice(smmu->dev, "probing hardware configuration...\n"); | |
1710 | ||
1711 | /* Primecell ID */ | |
1712 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2); | |
1713 | smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1; | |
1714 | dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version); | |
1715 | ||
1716 | /* ID0 */ | |
1717 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0); | |
1718 | #ifndef CONFIG_64BIT | |
1719 | if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) { | |
1720 | dev_err(smmu->dev, "\tno v7 descriptor support!\n"); | |
1721 | return -ENODEV; | |
1722 | } | |
1723 | #endif | |
4cf740b0 WD |
1724 | |
1725 | /* Restrict available stages based on module parameter */ | |
1726 | if (force_stage == 1) | |
1727 | id &= ~(ID0_S2TS | ID0_NTS); | |
1728 | else if (force_stage == 2) | |
1729 | id &= ~(ID0_S1TS | ID0_NTS); | |
1730 | ||
45ae7cff WD |
1731 | if (id & ID0_S1TS) { |
1732 | smmu->features |= ARM_SMMU_FEAT_TRANS_S1; | |
1733 | dev_notice(smmu->dev, "\tstage 1 translation\n"); | |
1734 | } | |
1735 | ||
1736 | if (id & ID0_S2TS) { | |
1737 | smmu->features |= ARM_SMMU_FEAT_TRANS_S2; | |
1738 | dev_notice(smmu->dev, "\tstage 2 translation\n"); | |
1739 | } | |
1740 | ||
1741 | if (id & ID0_NTS) { | |
1742 | smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; | |
1743 | dev_notice(smmu->dev, "\tnested translation\n"); | |
1744 | } | |
1745 | ||
1746 | if (!(smmu->features & | |
4cf740b0 | 1747 | (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) { |
45ae7cff WD |
1748 | dev_err(smmu->dev, "\tno translation support!\n"); |
1749 | return -ENODEV; | |
1750 | } | |
1751 | ||
1752 | if (id & ID0_CTTW) { | |
1753 | smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; | |
1754 | dev_notice(smmu->dev, "\tcoherent table walk\n"); | |
1755 | } | |
1756 | ||
1757 | if (id & ID0_SMS) { | |
1758 | u32 smr, sid, mask; | |
1759 | ||
1760 | smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; | |
1761 | smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) & | |
1762 | ID0_NUMSMRG_MASK; | |
1763 | if (smmu->num_mapping_groups == 0) { | |
1764 | dev_err(smmu->dev, | |
1765 | "stream-matching supported, but no SMRs present!\n"); | |
1766 | return -ENODEV; | |
1767 | } | |
1768 | ||
1769 | smr = SMR_MASK_MASK << SMR_MASK_SHIFT; | |
1770 | smr |= (SMR_ID_MASK << SMR_ID_SHIFT); | |
1771 | writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); | |
1772 | smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); | |
1773 | ||
1774 | mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK; | |
1775 | sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK; | |
1776 | if ((mask & sid) != sid) { | |
1777 | dev_err(smmu->dev, | |
1778 | "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n", | |
1779 | mask, sid); | |
1780 | return -ENODEV; | |
1781 | } | |
1782 | ||
1783 | dev_notice(smmu->dev, | |
1784 | "\tstream matching with %u register groups, mask 0x%x", | |
1785 | smmu->num_mapping_groups, mask); | |
3c8766d0 OH |
1786 | } else { |
1787 | smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) & | |
1788 | ID0_NUMSIDB_MASK; | |
45ae7cff WD |
1789 | } |
1790 | ||
1791 | /* ID1 */ | |
1792 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1); | |
1793 | smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K; | |
1794 | ||
c55af7f7 | 1795 | /* Check for size mismatch of SMMU address space from mapped region */ |
2907320d MH |
1796 | size = 1 << |
1797 | (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1); | |
45ae7cff | 1798 | size *= (smmu->pagesize << 1); |
c55af7f7 | 1799 | if (smmu->size != size) |
2907320d MH |
1800 | dev_warn(smmu->dev, |
1801 | "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n", | |
1802 | size, smmu->size); | |
45ae7cff WD |
1803 | |
1804 | smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & | |
1805 | ID1_NUMS2CB_MASK; | |
1806 | smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK; | |
1807 | if (smmu->num_s2_context_banks > smmu->num_context_banks) { | |
1808 | dev_err(smmu->dev, "impossible number of S2 context banks!\n"); | |
1809 | return -ENODEV; | |
1810 | } | |
1811 | dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", | |
1812 | smmu->num_context_banks, smmu->num_s2_context_banks); | |
1813 | ||
1814 | /* ID2 */ | |
1815 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); | |
1816 | size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); | |
1817 | ||
1818 | /* | |
1819 | * Stage-1 output limited by stage-2 input size due to pgd | |
1820 | * allocation (PTRS_PER_PGD). | |
1821 | */ | |
4d09d99d | 1822 | if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) { |
45ae7cff | 1823 | #ifdef CONFIG_64BIT |
4d09d99d | 1824 | smmu->s1_output_size = min_t(unsigned long, VA_BITS, size); |
45ae7cff | 1825 | #else |
4d09d99d | 1826 | smmu->s1_output_size = min(32UL, size); |
45ae7cff | 1827 | #endif |
4d09d99d WD |
1828 | } else { |
1829 | smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, | |
1830 | size); | |
1831 | } | |
45ae7cff WD |
1832 | |
1833 | /* The stage-2 output mask is also applied for bypass */ | |
1834 | size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); | |
2907320d | 1835 | smmu->s2_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size); |
45ae7cff WD |
1836 | |
1837 | if (smmu->version == 1) { | |
1838 | smmu->input_size = 32; | |
1839 | } else { | |
1840 | #ifdef CONFIG_64BIT | |
1841 | size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; | |
06f983dd | 1842 | size = min(VA_BITS, arm_smmu_id_size_to_bits(size)); |
45ae7cff WD |
1843 | #else |
1844 | size = 32; | |
1845 | #endif | |
1846 | smmu->input_size = size; | |
1847 | ||
1848 | if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) || | |
1849 | (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) || | |
1850 | (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) { | |
1851 | dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n", | |
1852 | PAGE_SIZE); | |
1853 | return -ENODEV; | |
1854 | } | |
1855 | } | |
1856 | ||
1857 | dev_notice(smmu->dev, | |
1858 | "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n", | |
2907320d MH |
1859 | smmu->input_size, smmu->s1_output_size, |
1860 | smmu->s2_output_size); | |
45ae7cff WD |
1861 | return 0; |
1862 | } | |
1863 | ||
1864 | static int arm_smmu_device_dt_probe(struct platform_device *pdev) | |
1865 | { | |
1866 | struct resource *res; | |
1867 | struct arm_smmu_device *smmu; | |
45ae7cff WD |
1868 | struct device *dev = &pdev->dev; |
1869 | struct rb_node *node; | |
1870 | struct of_phandle_args masterspec; | |
1871 | int num_irqs, i, err; | |
1872 | ||
1873 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); | |
1874 | if (!smmu) { | |
1875 | dev_err(dev, "failed to allocate arm_smmu_device\n"); | |
1876 | return -ENOMEM; | |
1877 | } | |
1878 | smmu->dev = dev; | |
1879 | ||
1880 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
8a7f4312 JL |
1881 | smmu->base = devm_ioremap_resource(dev, res); |
1882 | if (IS_ERR(smmu->base)) | |
1883 | return PTR_ERR(smmu->base); | |
45ae7cff | 1884 | smmu->size = resource_size(res); |
45ae7cff WD |
1885 | |
1886 | if (of_property_read_u32(dev->of_node, "#global-interrupts", | |
1887 | &smmu->num_global_irqs)) { | |
1888 | dev_err(dev, "missing #global-interrupts property\n"); | |
1889 | return -ENODEV; | |
1890 | } | |
1891 | ||
1892 | num_irqs = 0; | |
1893 | while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) { | |
1894 | num_irqs++; | |
1895 | if (num_irqs > smmu->num_global_irqs) | |
1896 | smmu->num_context_irqs++; | |
1897 | } | |
1898 | ||
44a08de2 AH |
1899 | if (!smmu->num_context_irqs) { |
1900 | dev_err(dev, "found %d interrupts but expected at least %d\n", | |
1901 | num_irqs, smmu->num_global_irqs + 1); | |
1902 | return -ENODEV; | |
45ae7cff | 1903 | } |
45ae7cff WD |
1904 | |
1905 | smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs, | |
1906 | GFP_KERNEL); | |
1907 | if (!smmu->irqs) { | |
1908 | dev_err(dev, "failed to allocate %d irqs\n", num_irqs); | |
1909 | return -ENOMEM; | |
1910 | } | |
1911 | ||
1912 | for (i = 0; i < num_irqs; ++i) { | |
1913 | int irq = platform_get_irq(pdev, i); | |
2907320d | 1914 | |
45ae7cff WD |
1915 | if (irq < 0) { |
1916 | dev_err(dev, "failed to get irq index %d\n", i); | |
1917 | return -ENODEV; | |
1918 | } | |
1919 | smmu->irqs[i] = irq; | |
1920 | } | |
1921 | ||
3c8766d0 OH |
1922 | err = arm_smmu_device_cfg_probe(smmu); |
1923 | if (err) | |
1924 | return err; | |
1925 | ||
45ae7cff WD |
1926 | i = 0; |
1927 | smmu->masters = RB_ROOT; | |
1928 | while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters", | |
1929 | "#stream-id-cells", i, | |
1930 | &masterspec)) { | |
1931 | err = register_smmu_master(smmu, dev, &masterspec); | |
1932 | if (err) { | |
1933 | dev_err(dev, "failed to add master %s\n", | |
1934 | masterspec.np->name); | |
1935 | goto out_put_masters; | |
1936 | } | |
1937 | ||
1938 | i++; | |
1939 | } | |
1940 | dev_notice(dev, "registered %d master devices\n", i); | |
1941 | ||
3a5df8ff AH |
1942 | parse_driver_options(smmu); |
1943 | ||
45ae7cff WD |
1944 | if (smmu->version > 1 && |
1945 | smmu->num_context_banks != smmu->num_context_irqs) { | |
1946 | dev_err(dev, | |
1947 | "found only %d context interrupt(s) but %d required\n", | |
1948 | smmu->num_context_irqs, smmu->num_context_banks); | |
89a23cde | 1949 | err = -ENODEV; |
44680eed | 1950 | goto out_put_masters; |
45ae7cff WD |
1951 | } |
1952 | ||
45ae7cff WD |
1953 | for (i = 0; i < smmu->num_global_irqs; ++i) { |
1954 | err = request_irq(smmu->irqs[i], | |
1955 | arm_smmu_global_fault, | |
1956 | IRQF_SHARED, | |
1957 | "arm-smmu global fault", | |
1958 | smmu); | |
1959 | if (err) { | |
1960 | dev_err(dev, "failed to request global IRQ %d (%u)\n", | |
1961 | i, smmu->irqs[i]); | |
1962 | goto out_free_irqs; | |
1963 | } | |
1964 | } | |
1965 | ||
1966 | INIT_LIST_HEAD(&smmu->list); | |
1967 | spin_lock(&arm_smmu_devices_lock); | |
1968 | list_add(&smmu->list, &arm_smmu_devices); | |
1969 | spin_unlock(&arm_smmu_devices_lock); | |
fd90cecb WD |
1970 | |
1971 | arm_smmu_device_reset(smmu); | |
45ae7cff WD |
1972 | return 0; |
1973 | ||
1974 | out_free_irqs: | |
1975 | while (i--) | |
1976 | free_irq(smmu->irqs[i], smmu); | |
1977 | ||
45ae7cff WD |
1978 | out_put_masters: |
1979 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { | |
2907320d MH |
1980 | struct arm_smmu_master *master |
1981 | = container_of(node, struct arm_smmu_master, node); | |
45ae7cff WD |
1982 | of_node_put(master->of_node); |
1983 | } | |
1984 | ||
1985 | return err; | |
1986 | } | |
1987 | ||
1988 | static int arm_smmu_device_remove(struct platform_device *pdev) | |
1989 | { | |
1990 | int i; | |
1991 | struct device *dev = &pdev->dev; | |
1992 | struct arm_smmu_device *curr, *smmu = NULL; | |
1993 | struct rb_node *node; | |
1994 | ||
1995 | spin_lock(&arm_smmu_devices_lock); | |
1996 | list_for_each_entry(curr, &arm_smmu_devices, list) { | |
1997 | if (curr->dev == dev) { | |
1998 | smmu = curr; | |
1999 | list_del(&smmu->list); | |
2000 | break; | |
2001 | } | |
2002 | } | |
2003 | spin_unlock(&arm_smmu_devices_lock); | |
2004 | ||
2005 | if (!smmu) | |
2006 | return -ENODEV; | |
2007 | ||
45ae7cff | 2008 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { |
2907320d MH |
2009 | struct arm_smmu_master *master |
2010 | = container_of(node, struct arm_smmu_master, node); | |
45ae7cff WD |
2011 | of_node_put(master->of_node); |
2012 | } | |
2013 | ||
ecfadb6e | 2014 | if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) |
45ae7cff WD |
2015 | dev_err(dev, "removing device with active domains!\n"); |
2016 | ||
2017 | for (i = 0; i < smmu->num_global_irqs; ++i) | |
2018 | free_irq(smmu->irqs[i], smmu); | |
2019 | ||
2020 | /* Turn the thing off */ | |
2907320d | 2021 | writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
45ae7cff WD |
2022 | return 0; |
2023 | } | |
2024 | ||
2025 | #ifdef CONFIG_OF | |
2026 | static struct of_device_id arm_smmu_of_match[] = { | |
2027 | { .compatible = "arm,smmu-v1", }, | |
2028 | { .compatible = "arm,smmu-v2", }, | |
2029 | { .compatible = "arm,mmu-400", }, | |
2030 | { .compatible = "arm,mmu-500", }, | |
2031 | { }, | |
2032 | }; | |
2033 | MODULE_DEVICE_TABLE(of, arm_smmu_of_match); | |
2034 | #endif | |
2035 | ||
2036 | static struct platform_driver arm_smmu_driver = { | |
2037 | .driver = { | |
2038 | .owner = THIS_MODULE, | |
2039 | .name = "arm-smmu", | |
2040 | .of_match_table = of_match_ptr(arm_smmu_of_match), | |
2041 | }, | |
2042 | .probe = arm_smmu_device_dt_probe, | |
2043 | .remove = arm_smmu_device_remove, | |
2044 | }; | |
2045 | ||
2046 | static int __init arm_smmu_init(void) | |
2047 | { | |
2048 | int ret; | |
2049 | ||
2050 | ret = platform_driver_register(&arm_smmu_driver); | |
2051 | if (ret) | |
2052 | return ret; | |
2053 | ||
2054 | /* Oh, for a proper bus abstraction */ | |
6614ee77 | 2055 | if (!iommu_present(&platform_bus_type)) |
45ae7cff WD |
2056 | bus_set_iommu(&platform_bus_type, &arm_smmu_ops); |
2057 | ||
d123cf82 | 2058 | #ifdef CONFIG_ARM_AMBA |
6614ee77 | 2059 | if (!iommu_present(&amba_bustype)) |
45ae7cff | 2060 | bus_set_iommu(&amba_bustype, &arm_smmu_ops); |
d123cf82 | 2061 | #endif |
45ae7cff | 2062 | |
a9a1b0b5 WD |
2063 | #ifdef CONFIG_PCI |
2064 | if (!iommu_present(&pci_bus_type)) | |
2065 | bus_set_iommu(&pci_bus_type, &arm_smmu_ops); | |
2066 | #endif | |
2067 | ||
45ae7cff WD |
2068 | return 0; |
2069 | } | |
2070 | ||
2071 | static void __exit arm_smmu_exit(void) | |
2072 | { | |
2073 | return platform_driver_unregister(&arm_smmu_driver); | |
2074 | } | |
2075 | ||
b1950b27 | 2076 | subsys_initcall(arm_smmu_init); |
45ae7cff WD |
2077 | module_exit(arm_smmu_exit); |
2078 | ||
2079 | MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations"); | |
2080 | MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); | |
2081 | MODULE_LICENSE("GPL v2"); |