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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc
[linux-2.6-block.git] / drivers / infiniband / hw / qib / qib_iba7322.c
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f931551b 1/*
1fb9fed6
MM		 2 * Copyright (c) 2012 Intel Corporation. All rights reserved.
3 * Copyright (c) 2008 - 2012 QLogic Corporation. All rights reserved.
f931551b
RC		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34/*
35 * This file contains all of the code that is specific to the
36 * InfiniPath 7322 chip
37 */
38
39#include <linux/interrupt.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <linux/io.h>
43#include <linux/jiffies.h>
e4dd23d7 44#include <linux/module.h>
f931551b
RC		 45#include <rdma/ib_verbs.h>
46#include <rdma/ib_smi.h>
8469ba39
MM		 47#ifdef CONFIG_INFINIBAND_QIB_DCA
48#include <linux/dca.h>
49#endif
f931551b
RC		 50
51#include "qib.h"
52#include "qib_7322_regs.h"
53#include "qib_qsfp.h"
54
55#include "qib_mad.h"
1fb9fed6 56#include "qib_verbs.h"
f931551b 57
7fac3301
MM		 58#undef pr_fmt
59#define pr_fmt(fmt) QIB_DRV_NAME " " fmt
60
f931551b
RC		 61static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
62static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
63static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
64static irqreturn_t qib_7322intr(int irq, void *data);
65static irqreturn_t qib_7322bufavail(int irq, void *data);
66static irqreturn_t sdma_intr(int irq, void *data);
67static irqreturn_t sdma_idle_intr(int irq, void *data);
68static irqreturn_t sdma_progress_intr(int irq, void *data);
69static irqreturn_t sdma_cleanup_intr(int irq, void *data);
70static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
71 struct qib_ctxtdata *rcd);
72static u8 qib_7322_phys_portstate(u64);
73static u32 qib_7322_iblink_state(u64);
74static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
75 u16 linitcmd);
76static void force_h1(struct qib_pportdata *);
77static void adj_tx_serdes(struct qib_pportdata *);
78static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
79static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
80
81static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
82static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
a0a234d4
MM		 83static void serdes_7322_los_enable(struct qib_pportdata *, int);
84static int serdes_7322_init_old(struct qib_pportdata *);
85static int serdes_7322_init_new(struct qib_pportdata *);
0b3ddf38 86static void dump_sdma_7322_state(struct qib_pportdata *);
f931551b
RC		 87
88#define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
89
90/* LE2 serdes values for different cases */
91#define LE2_DEFAULT 5
92#define LE2_5m 4
93#define LE2_QME 0
94
95/* Below is special-purpose, so only really works for the IB SerDes blocks. */
96#define IBSD(hw_pidx) (hw_pidx + 2)
97
98/* these are variables for documentation and experimentation purposes */
99static const unsigned rcv_int_timeout = 375;
100static const unsigned rcv_int_count = 16;
101static const unsigned sdma_idle_cnt = 64;
102
103/* Time to stop altering Rx Equalization parameters, after link up. */
104#define RXEQ_DISABLE_MSECS 2500
105
106/*
107 * Number of VLs we are configured to use (to allow for more
108 * credits per vl, etc.)
109 */
110ushort qib_num_cfg_vls = 2;
111module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
112MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
113
114static ushort qib_chase = 1;
115module_param_named(chase, qib_chase, ushort, S_IRUGO);
116MODULE_PARM_DESC(chase, "Enable state chase handling");
117
118static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
119module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
a46a2802 120MODULE_PARM_DESC(long_attenuation,
f931551b
RC		 121 "attenuation cutoff (dB) for long copper cable setup");
122
123static ushort qib_singleport;
124module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
125MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
126
e67306a3
MM		 127static ushort qib_krcvq01_no_msi;
128module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO);
129MODULE_PARM_DESC(krcvq01_no_msi, "No MSI for kctx < 2");
130
0a43e117
MM		 131/*
132 * Receive header queue sizes
133 */
134static unsigned qib_rcvhdrcnt;
135module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
136MODULE_PARM_DESC(rcvhdrcnt, "receive header count");
137
138static unsigned qib_rcvhdrsize;
139module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
140MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
141
142static unsigned qib_rcvhdrentsize;
143module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
144MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
145
f931551b
RC		 146#define MAX_ATTEN_LEN 64 /* plenty for any real system */
147/* for read back, default index is ~5m copper cable */
a77fcf89
RC		 148static char txselect_list[MAX_ATTEN_LEN] = "10";
149static struct kparam_string kp_txselect = {
150 .string = txselect_list,
f931551b
RC		 151 .maxlen = MAX_ATTEN_LEN
152};
a77fcf89
RC		 153static int setup_txselect(const char *, struct kernel_param *);
154module_param_call(txselect, setup_txselect, param_get_string,
155 &kp_txselect, S_IWUSR | S_IRUGO);
a46a2802 156MODULE_PARM_DESC(txselect,
a77fcf89 157 "Tx serdes indices (for no QSFP or invalid QSFP data)");
f931551b
RC		 158
159#define BOARD_QME7342 5
160#define BOARD_QMH7342 6
0e6bbba5 161#define BOARD_QMH7360 9
f931551b
RC		 162#define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
163 BOARD_QMH7342)
164#define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
165 BOARD_QME7342)
166
167#define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
168
169#define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
170
171#define MASK_ACROSS(lsb, msb) \
172 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
173
174#define SYM_RMASK(regname, fldname) ((u64) \
175 QIB_7322_##regname##_##fldname##_RMASK)
176
177#define SYM_MASK(regname, fldname) ((u64) \
178 QIB_7322_##regname##_##fldname##_RMASK << \
179 QIB_7322_##regname##_##fldname##_LSB)
180
181#define SYM_FIELD(value, regname, fldname) ((u64) \
182 (((value) >> SYM_LSB(regname, fldname)) & \
183 SYM_RMASK(regname, fldname)))
184
185/* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
186#define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
187 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
188
189#define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
190#define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
191#define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
192#define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
193#define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
194/* Below because most, but not all, fields of IntMask have that full suffix */
195#define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
196
197
198#define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
199
200/*
201 * the size bits give us 2^N, in KB units. 0 marks as invalid,
202 * and 7 is reserved. We currently use only 2KB and 4KB
203 */
204#define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
205#define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
206#define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
207#define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
208
209#define SendIBSLIDAssignMask \
210 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
211#define SendIBSLMCMask \
212 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
213
214#define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
215#define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
216#define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
217#define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
218#define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
219#define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
220
221#define _QIB_GPIO_SDA_NUM 1
222#define _QIB_GPIO_SCL_NUM 0
223#define QIB_EEPROM_WEN_NUM 14
224#define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */
225
226/* HW counter clock is at 4nsec */
227#define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
228
229/* full speed IB port 1 only */
230#define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
231#define PORT_SPD_CAP_SHIFT 3
232
233/* full speed featuremask, both ports */
234#define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
235
236/*
237 * This file contains almost all the chip-specific register information and
238 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
239 */
240
241/* Use defines to tie machine-generated names to lower-case names */
242#define kr_contextcnt KREG_IDX(ContextCnt)
243#define kr_control KREG_IDX(Control)
244#define kr_counterregbase KREG_IDX(CntrRegBase)
245#define kr_errclear KREG_IDX(ErrClear)
246#define kr_errmask KREG_IDX(ErrMask)
247#define kr_errstatus KREG_IDX(ErrStatus)
248#define kr_extctrl KREG_IDX(EXTCtrl)
249#define kr_extstatus KREG_IDX(EXTStatus)
250#define kr_gpio_clear KREG_IDX(GPIOClear)
251#define kr_gpio_mask KREG_IDX(GPIOMask)
252#define kr_gpio_out KREG_IDX(GPIOOut)
253#define kr_gpio_status KREG_IDX(GPIOStatus)
254#define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
255#define kr_debugportval KREG_IDX(DebugPortValueReg)
256#define kr_fmask KREG_IDX(feature_mask)
257#define kr_act_fmask KREG_IDX(active_feature_mask)
258#define kr_hwerrclear KREG_IDX(HwErrClear)
259#define kr_hwerrmask KREG_IDX(HwErrMask)
260#define kr_hwerrstatus KREG_IDX(HwErrStatus)
261#define kr_intclear KREG_IDX(IntClear)
262#define kr_intmask KREG_IDX(IntMask)
263#define kr_intredirect KREG_IDX(IntRedirect0)
264#define kr_intstatus KREG_IDX(IntStatus)
265#define kr_pagealign KREG_IDX(PageAlign)
266#define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
267#define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
268#define kr_rcvegrbase KREG_IDX(RcvEgrBase)
269#define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
270#define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
271#define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
272#define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
273#define kr_rcvtidbase KREG_IDX(RcvTIDBase)
274#define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
275#define kr_revision KREG_IDX(Revision)
276#define kr_scratch KREG_IDX(Scratch)
277#define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
278#define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
279#define kr_sendctrl KREG_IDX(SendCtrl)
280#define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
281#define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
282#define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
283#define kr_sendpiobufbase KREG_IDX(SendBufBase)
284#define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
285#define kr_sendpiosize KREG_IDX(SendBufSize)
286#define kr_sendregbase KREG_IDX(SendRegBase)
287#define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
288#define kr_userregbase KREG_IDX(UserRegBase)
289#define kr_intgranted KREG_IDX(Int_Granted)
290#define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
291#define kr_intblocked KREG_IDX(IntBlocked)
292#define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
293
294/*
295 * per-port kernel registers. Access only with qib_read_kreg_port()
296 * or qib_write_kreg_port()
297 */
298#define krp_errclear KREG_IBPORT_IDX(ErrClear)
299#define krp_errmask KREG_IBPORT_IDX(ErrMask)
300#define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
301#define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
302#define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
303#define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
304#define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
305#define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
306#define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
307#define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
308#define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
309#define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
310#define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
311#define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
312#define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
313#define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
314#define krp_psinterval KREG_IBPORT_IDX(PSInterval)
315#define krp_psstart KREG_IBPORT_IDX(PSStart)
316#define krp_psstat KREG_IBPORT_IDX(PSStat)
317#define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
318#define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
319#define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
320#define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
321#define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
322#define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
323#define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
324#define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
325#define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
326#define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
327#define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
328#define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
329#define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
330#define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
331#define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
332#define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
333#define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
334#define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
335#define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
336#define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
337#define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
338#define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
339#define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
340#define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
341#define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
342#define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
343#define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
344#define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
345#define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
346#define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
347#define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
348
349/*
b595076a 350 * Per-context kernel registers. Access only with qib_read_kreg_ctxt()
f931551b
RC		 351 * or qib_write_kreg_ctxt()
352 */
353#define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
354#define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
355
356/*
357 * TID Flow table, per context. Reduces
358 * number of hdrq updates to one per flow (or on errors).
359 * context 0 and 1 share same memory, but have distinct
360 * addresses. Since for now, we never use expected sends
361 * on kernel contexts, we don't worry about that (we initialize
362 * those entries for ctxt 0/1 on driver load twice, for example).
363 */
364#define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
365#define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
366
367/* these are the error bits in the tid flows, and are W1C */
368#define TIDFLOW_ERRBITS ( \
369 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
370 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
371 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
372 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
373
374/* Most (not all) Counters are per-IBport.
375 * Requires LBIntCnt is at offset 0 in the group
376 */
377#define CREG_IDX(regname) \
378((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
379
380#define crp_badformat CREG_IDX(RxVersionErrCnt)
381#define crp_err_rlen CREG_IDX(RxLenErrCnt)
382#define crp_erricrc CREG_IDX(RxICRCErrCnt)
383#define crp_errlink CREG_IDX(RxLinkMalformCnt)
384#define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
385#define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
386#define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
387#define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
388#define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
389#define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
390#define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
391#define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
392#define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
393#define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
394#define crp_pktrcv CREG_IDX(RxDataPktCnt)
395#define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
396#define crp_pktsend CREG_IDX(TxDataPktCnt)
397#define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
398#define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
399#define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
400#define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
401#define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
402#define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
403#define crp_rcvebp CREG_IDX(RxEBPCnt)
404#define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
405#define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
406#define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
407#define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
408#define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
409#define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
410#define crp_rxvlerr CREG_IDX(RxVlErrCnt)
411#define crp_sendstall CREG_IDX(TxFlowStallCnt)
412#define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
413#define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
414#define crp_txlenerr CREG_IDX(TxLenErrCnt)
f931551b
RC		 415#define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
416#define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
417#define crp_txunderrun CREG_IDX(TxUnderrunCnt)
418#define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
419#define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
420#define crp_wordrcv CREG_IDX(RxDwordCnt)
421#define crp_wordsend CREG_IDX(TxDwordCnt)
422#define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
423
424/* these are the (few) counters that are not port-specific */
425#define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
426 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
427#define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
428#define cr_lbint CREG_DEVIDX(LBIntCnt)
429#define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
430#define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
431#define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
432#define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
433#define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
434
435/* no chip register for # of IB ports supported, so define */
436#define NUM_IB_PORTS 2
437
438/* 1 VL15 buffer per hardware IB port, no register for this, so define */
439#define NUM_VL15_BUFS NUM_IB_PORTS
440
441/*
442 * context 0 and 1 are special, and there is no chip register that
443 * defines this value, so we have to define it here.
444 * These are all allocated to either 0 or 1 for single port
445 * hardware configuration, otherwise each gets half
446 */
447#define KCTXT0_EGRCNT 2048
448
449/* values for vl and port fields in PBC, 7322-specific */
450#define PBC_PORT_SEL_LSB 26
451#define PBC_PORT_SEL_RMASK 1
452#define PBC_VL_NUM_LSB 27
453#define PBC_VL_NUM_RMASK 7
454#define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
455#define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
456
457static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
458 [IB_RATE_2_5_GBPS] = 16,
459 [IB_RATE_5_GBPS] = 8,
460 [IB_RATE_10_GBPS] = 4,
461 [IB_RATE_20_GBPS] = 2,
462 [IB_RATE_30_GBPS] = 2,
463 [IB_RATE_40_GBPS] = 1
464};
465
466#define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
467#define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
468
469/* link training states, from IBC */
470#define IB_7322_LT_STATE_DISABLED 0x00
471#define IB_7322_LT_STATE_LINKUP 0x01
472#define IB_7322_LT_STATE_POLLACTIVE 0x02
473#define IB_7322_LT_STATE_POLLQUIET 0x03
474#define IB_7322_LT_STATE_SLEEPDELAY 0x04
475#define IB_7322_LT_STATE_SLEEPQUIET 0x05
476#define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
477#define IB_7322_LT_STATE_CFGRCVFCFG 0x09
478#define IB_7322_LT_STATE_CFGWAITRMT 0x0a
479#define IB_7322_LT_STATE_CFGIDLE 0x0b
480#define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
481#define IB_7322_LT_STATE_TXREVLANES 0x0d
482#define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
483#define IB_7322_LT_STATE_RECOVERIDLE 0x0f
484#define IB_7322_LT_STATE_CFGENH 0x10
485#define IB_7322_LT_STATE_CFGTEST 0x11
31264484
MH		 486#define IB_7322_LT_STATE_CFGWAITRMTTEST 0x12
487#define IB_7322_LT_STATE_CFGWAITENH 0x13
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RC		 488
489/* link state machine states from IBC */
490#define IB_7322_L_STATE_DOWN 0x0
491#define IB_7322_L_STATE_INIT 0x1
492#define IB_7322_L_STATE_ARM 0x2
493#define IB_7322_L_STATE_ACTIVE 0x3
494#define IB_7322_L_STATE_ACT_DEFER 0x4
495
496static const u8 qib_7322_physportstate[0x20] = {
497 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
498 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
499 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
500 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
501 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
502 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
503 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
504 [IB_7322_LT_STATE_CFGRCVFCFG] =
505 IB_PHYSPORTSTATE_CFG_TRAIN,
506 [IB_7322_LT_STATE_CFGWAITRMT] =
507 IB_PHYSPORTSTATE_CFG_TRAIN,
508 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
509 [IB_7322_LT_STATE_RECOVERRETRAIN] =
510 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
511 [IB_7322_LT_STATE_RECOVERWAITRMT] =
512 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
513 [IB_7322_LT_STATE_RECOVERIDLE] =
514 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
515 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
516 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
31264484
MH		 517 [IB_7322_LT_STATE_CFGWAITRMTTEST] =
518 IB_PHYSPORTSTATE_CFG_TRAIN,
519 [IB_7322_LT_STATE_CFGWAITENH] =
520 IB_PHYSPORTSTATE_CFG_WAIT_ENH,
f931551b
RC		 521 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
522 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
523 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
524 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
525};
526
8469ba39
MM		 527#ifdef CONFIG_INFINIBAND_QIB_DCA
528struct qib_irq_notify {
529 int rcv;
530 void *arg;
531 struct irq_affinity_notify notify;
532};
533#endif
534
f931551b
RC		 535struct qib_chip_specific {
536 u64 __iomem *cregbase;
537 u64 *cntrs;
538 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
539 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
540 u64 main_int_mask; /* clear bits which have dedicated handlers */
541 u64 int_enable_mask; /* for per port interrupts in single port mode */
542 u64 errormask;
543 u64 hwerrmask;
544 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
545 u64 gpio_mask; /* shadow the gpio mask register */
546 u64 extctrl; /* shadow the gpio output enable, etc... */
547 u32 ncntrs;
548 u32 nportcntrs;
549 u32 cntrnamelen;
550 u32 portcntrnamelen;
551 u32 numctxts;
552 u32 rcvegrcnt;
553 u32 updthresh; /* current AvailUpdThld */
554 u32 updthresh_dflt; /* default AvailUpdThld */
555 u32 r1;
556 int irq;
557 u32 num_msix_entries;
558 u32 sdmabufcnt;
559 u32 lastbuf_for_pio;
560 u32 stay_in_freeze;
561 u32 recovery_ports_initted;
8469ba39
MM		 562#ifdef CONFIG_INFINIBAND_QIB_DCA
563 u32 dca_ctrl;
564 int rhdr_cpu[18];
565 int sdma_cpu[2];
566 u64 dca_rcvhdr_ctrl[5]; /* B, C, D, E, F */
567#endif
a778f3fd 568 struct qib_msix_entry *msix_entries;
f931551b
RC		 569 unsigned long *sendchkenable;
570 unsigned long *sendgrhchk;
571 unsigned long *sendibchk;
572 u32 rcvavail_timeout[18];
573 char emsgbuf[128]; /* for device error interrupt msg buffer */
574};
575
576/* Table of entries in "human readable" form Tx Emphasis. */
577struct txdds_ent {
578 u8 amp;
579 u8 pre;
580 u8 main;
581 u8 post;
582};
583
584struct vendor_txdds_ent {
585 u8 oui[QSFP_VOUI_LEN];
586 u8 *partnum;
587 struct txdds_ent sdr;
588 struct txdds_ent ddr;
589 struct txdds_ent qdr;
590};
591
592static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
593
594#define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
22baa407 595#define TXDDS_EXTRA_SZ 18 /* number of extra tx settings entries */
e706203c 596#define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */
f931551b
RC		 597#define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
598
599#define H1_FORCE_VAL 8
a77fcf89
RC		 600#define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */
601#define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */
f931551b
RC		 602
603/* The static and dynamic registers are paired, and the pairs indexed by spd */
604#define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
605 + ((spd) * 2))
606
607#define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
608#define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
609#define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
610#define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
611#define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
612
f931551b
RC		 613struct qib_chippport_specific {
614 u64 __iomem *kpregbase;
615 u64 __iomem *cpregbase;
616 u64 *portcntrs;
617 struct qib_pportdata *ppd;
618 wait_queue_head_t autoneg_wait;
619 struct delayed_work autoneg_work;
620 struct delayed_work ipg_work;
621 struct timer_list chase_timer;
622 /*
623 * these 5 fields are used to establish deltas for IB symbol
624 * errors and linkrecovery errors. They can be reported on
625 * some chips during link negotiation prior to INIT, and with
626 * DDR when faking DDR negotiations with non-IBTA switches.
627 * The chip counters are adjusted at driver unload if there is
628 * a non-zero delta.
629 */
630 u64 ibdeltainprog;
631 u64 ibsymdelta;
632 u64 ibsymsnap;
633 u64 iblnkerrdelta;
634 u64 iblnkerrsnap;
635 u64 iblnkdownsnap;
636 u64 iblnkdowndelta;
637 u64 ibmalfdelta;
638 u64 ibmalfsnap;
639 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */
640 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */
8482d5d1
MM		 641 unsigned long qdr_dfe_time;
642 unsigned long chase_end;
f931551b
RC		 643 u32 autoneg_tries;
644 u32 recovery_init;
645 u32 qdr_dfe_on;
646 u32 qdr_reforce;
647 /*
648 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
649 * entry zero is unused, to simplify indexing
650 */
a77fcf89
RC		 651 u8 h1_val;
652 u8 no_eep; /* txselect table index to use if no qsfp info */
f931551b
RC		 653 u8 ipg_tries;
654 u8 ibmalfusesnap;
655 struct qib_qsfp_data qsfp_data;
656 char epmsgbuf[192]; /* for port error interrupt msg buffer */
0b3ddf38 657 char sdmamsgbuf[192]; /* for per-port sdma error messages */
f931551b
RC		 658};
659
660static struct {
661 const char *name;
662 irq_handler_t handler;
663 int lsb;
664 int port; /* 0 if not port-specific, else port # */
8469ba39 665 int dca;
f931551b 666} irq_table[] = {
8469ba39 667 { "", qib_7322intr, -1, 0, 0 },
a778f3fd 668 { " (buf avail)", qib_7322bufavail,
8469ba39 669 SYM_LSB(IntStatus, SendBufAvail), 0, 0},
a778f3fd 670 { " (sdma 0)", sdma_intr,
8469ba39 671 SYM_LSB(IntStatus, SDmaInt_0), 1, 1 },
a778f3fd 672 { " (sdma 1)", sdma_intr,
8469ba39 673 SYM_LSB(IntStatus, SDmaInt_1), 2, 1 },
a778f3fd 674 { " (sdmaI 0)", sdma_idle_intr,
8469ba39 675 SYM_LSB(IntStatus, SDmaIdleInt_0), 1, 1},
a778f3fd 676 { " (sdmaI 1)", sdma_idle_intr,
8469ba39 677 SYM_LSB(IntStatus, SDmaIdleInt_1), 2, 1},
a778f3fd 678 { " (sdmaP 0)", sdma_progress_intr,
8469ba39 679 SYM_LSB(IntStatus, SDmaProgressInt_0), 1, 1 },
a778f3fd 680 { " (sdmaP 1)", sdma_progress_intr,
8469ba39 681 SYM_LSB(IntStatus, SDmaProgressInt_1), 2, 1 },
a778f3fd 682 { " (sdmaC 0)", sdma_cleanup_intr,
8469ba39 683 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1, 0 },
a778f3fd 684 { " (sdmaC 1)", sdma_cleanup_intr,
8469ba39 685 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 , 0},
f931551b
RC		 686};
687
8469ba39
MM		 688#ifdef CONFIG_INFINIBAND_QIB_DCA
689
690static const struct dca_reg_map {
691 int shadow_inx;
692 int lsb;
693 u64 mask;
694 u16 regno;
695} dca_rcvhdr_reg_map[] = {
696 { 0, SYM_LSB(DCACtrlB, RcvHdrq0DCAOPH),
697 ~SYM_MASK(DCACtrlB, RcvHdrq0DCAOPH) , KREG_IDX(DCACtrlB) },
698 { 0, SYM_LSB(DCACtrlB, RcvHdrq1DCAOPH),
699 ~SYM_MASK(DCACtrlB, RcvHdrq1DCAOPH) , KREG_IDX(DCACtrlB) },
700 { 0, SYM_LSB(DCACtrlB, RcvHdrq2DCAOPH),
701 ~SYM_MASK(DCACtrlB, RcvHdrq2DCAOPH) , KREG_IDX(DCACtrlB) },
702 { 0, SYM_LSB(DCACtrlB, RcvHdrq3DCAOPH),
703 ~SYM_MASK(DCACtrlB, RcvHdrq3DCAOPH) , KREG_IDX(DCACtrlB) },
704 { 1, SYM_LSB(DCACtrlC, RcvHdrq4DCAOPH),
705 ~SYM_MASK(DCACtrlC, RcvHdrq4DCAOPH) , KREG_IDX(DCACtrlC) },
706 { 1, SYM_LSB(DCACtrlC, RcvHdrq5DCAOPH),
707 ~SYM_MASK(DCACtrlC, RcvHdrq5DCAOPH) , KREG_IDX(DCACtrlC) },
708 { 1, SYM_LSB(DCACtrlC, RcvHdrq6DCAOPH),
709 ~SYM_MASK(DCACtrlC, RcvHdrq6DCAOPH) , KREG_IDX(DCACtrlC) },
710 { 1, SYM_LSB(DCACtrlC, RcvHdrq7DCAOPH),
711 ~SYM_MASK(DCACtrlC, RcvHdrq7DCAOPH) , KREG_IDX(DCACtrlC) },
712 { 2, SYM_LSB(DCACtrlD, RcvHdrq8DCAOPH),
713 ~SYM_MASK(DCACtrlD, RcvHdrq8DCAOPH) , KREG_IDX(DCACtrlD) },
714 { 2, SYM_LSB(DCACtrlD, RcvHdrq9DCAOPH),
715 ~SYM_MASK(DCACtrlD, RcvHdrq9DCAOPH) , KREG_IDX(DCACtrlD) },
716 { 2, SYM_LSB(DCACtrlD, RcvHdrq10DCAOPH),
717 ~SYM_MASK(DCACtrlD, RcvHdrq10DCAOPH) , KREG_IDX(DCACtrlD) },
718 { 2, SYM_LSB(DCACtrlD, RcvHdrq11DCAOPH),
719 ~SYM_MASK(DCACtrlD, RcvHdrq11DCAOPH) , KREG_IDX(DCACtrlD) },
720 { 3, SYM_LSB(DCACtrlE, RcvHdrq12DCAOPH),
721 ~SYM_MASK(DCACtrlE, RcvHdrq12DCAOPH) , KREG_IDX(DCACtrlE) },
722 { 3, SYM_LSB(DCACtrlE, RcvHdrq13DCAOPH),
723 ~SYM_MASK(DCACtrlE, RcvHdrq13DCAOPH) , KREG_IDX(DCACtrlE) },
724 { 3, SYM_LSB(DCACtrlE, RcvHdrq14DCAOPH),
725 ~SYM_MASK(DCACtrlE, RcvHdrq14DCAOPH) , KREG_IDX(DCACtrlE) },
726 { 3, SYM_LSB(DCACtrlE, RcvHdrq15DCAOPH),
727 ~SYM_MASK(DCACtrlE, RcvHdrq15DCAOPH) , KREG_IDX(DCACtrlE) },
728 { 4, SYM_LSB(DCACtrlF, RcvHdrq16DCAOPH),
729 ~SYM_MASK(DCACtrlF, RcvHdrq16DCAOPH) , KREG_IDX(DCACtrlF) },
730 { 4, SYM_LSB(DCACtrlF, RcvHdrq17DCAOPH),
731 ~SYM_MASK(DCACtrlF, RcvHdrq17DCAOPH) , KREG_IDX(DCACtrlF) },
732};
733#endif
734
f931551b
RC		 735/* ibcctrl bits */
736#define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
737/* cycle through TS1/TS2 till OK */
738#define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
739/* wait for TS1, then go on */
740#define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
741#define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
742
743#define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
744#define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
745#define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
746
747#define BLOB_7322_IBCHG 0x101
748
749static inline void qib_write_kreg(const struct qib_devdata *dd,
750 const u32 regno, u64 value);
751static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
752static void write_7322_initregs(struct qib_devdata *);
753static void write_7322_init_portregs(struct qib_pportdata *);
754static void setup_7322_link_recovery(struct qib_pportdata *, u32);
755static void check_7322_rxe_status(struct qib_pportdata *);
756static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
8469ba39
MM		 757#ifdef CONFIG_INFINIBAND_QIB_DCA
758static void qib_setup_dca(struct qib_devdata *dd);
759static void setup_dca_notifier(struct qib_devdata *dd,
760 struct qib_msix_entry *m);
761static void reset_dca_notifier(struct qib_devdata *dd,
762 struct qib_msix_entry *m);
763#endif
f931551b
RC		 764
765/**
766 * qib_read_ureg32 - read 32-bit virtualized per-context register
767 * @dd: device
768 * @regno: register number
769 * @ctxt: context number
770 *
771 * Return the contents of a register that is virtualized to be per context.
772 * Returns -1 on errors (not distinguishable from valid contents at
773 * runtime; we may add a separate error variable at some point).
774 */
775static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
776 enum qib_ureg regno, int ctxt)
777{
778 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
779 return 0;
780 return readl(regno + (u64 __iomem *)(
781 (dd->ureg_align * ctxt) + (dd->userbase ?
782 (char __iomem *)dd->userbase :
783 (char __iomem *)dd->kregbase + dd->uregbase)));
784}
785
786/**
787 * qib_read_ureg - read virtualized per-context register
788 * @dd: device
789 * @regno: register number
790 * @ctxt: context number
791 *
792 * Return the contents of a register that is virtualized to be per context.
793 * Returns -1 on errors (not distinguishable from valid contents at
794 * runtime; we may add a separate error variable at some point).
795 */
796static inline u64 qib_read_ureg(const struct qib_devdata *dd,
797 enum qib_ureg regno, int ctxt)
798{
799
800 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
801 return 0;
802 return readq(regno + (u64 __iomem *)(
803 (dd->ureg_align * ctxt) + (dd->userbase ?
804 (char __iomem *)dd->userbase :
805 (char __iomem *)dd->kregbase + dd->uregbase)));
806}
807
808/**
809 * qib_write_ureg - write virtualized per-context register
810 * @dd: device
811 * @regno: register number
812 * @value: value
813 * @ctxt: context
814 *
815 * Write the contents of a register that is virtualized to be per context.
816 */
817static inline void qib_write_ureg(const struct qib_devdata *dd,
818 enum qib_ureg regno, u64 value, int ctxt)
819{
820 u64 __iomem *ubase;
da12c1f6 821
f931551b
RC		 822 if (dd->userbase)
823 ubase = (u64 __iomem *)
824 ((char __iomem *) dd->userbase +
825 dd->ureg_align * ctxt);
826 else
827 ubase = (u64 __iomem *)
828 (dd->uregbase +
829 (char __iomem *) dd->kregbase +
830 dd->ureg_align * ctxt);
831
832 if (dd->kregbase && (dd->flags & QIB_PRESENT))
833 writeq(value, &ubase[regno]);
834}
835
836static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
837 const u32 regno)
838{
839 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
840 return -1;
841 return readl((u32 __iomem *) &dd->kregbase[regno]);
842}
843
844static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
845 const u32 regno)
846{
847 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
848 return -1;
849 return readq(&dd->kregbase[regno]);
850}
851
852static inline void qib_write_kreg(const struct qib_devdata *dd,
853 const u32 regno, u64 value)
854{
855 if (dd->kregbase && (dd->flags & QIB_PRESENT))
856 writeq(value, &dd->kregbase[regno]);
857}
858
859/*
860 * not many sanity checks for the port-specific kernel register routines,
861 * since they are only used when it's known to be safe.
862*/
863static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
864 const u16 regno)
865{
866 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
867 return 0ULL;
868 return readq(&ppd->cpspec->kpregbase[regno]);
869}
870
871static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
872 const u16 regno, u64 value)
873{
874 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
875 (ppd->dd->flags & QIB_PRESENT))
876 writeq(value, &ppd->cpspec->kpregbase[regno]);
877}
878
879/**
880 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
881 * @dd: the qlogic_ib device
882 * @regno: the register number to write
883 * @ctxt: the context containing the register
884 * @value: the value to write
885 */
886static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
887 const u16 regno, unsigned ctxt,
888 u64 value)
889{
890 qib_write_kreg(dd, regno + ctxt, value);
891}
892
893static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
894{
895 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
896 return 0;
897 return readq(&dd->cspec->cregbase[regno]);
898
899
900}
901
902static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
903{
904 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
905 return 0;
906 return readl(&dd->cspec->cregbase[regno]);
907
908
909}
910
911static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
912 u16 regno, u64 value)
913{
914 if (ppd->cpspec && ppd->cpspec->cpregbase &&
915 (ppd->dd->flags & QIB_PRESENT))
916 writeq(value, &ppd->cpspec->cpregbase[regno]);
917}
918
919static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
920 u16 regno)
921{
922 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
923 !(ppd->dd->flags & QIB_PRESENT))
924 return 0;
925 return readq(&ppd->cpspec->cpregbase[regno]);
926}
927
928static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
929 u16 regno)
930{
931 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
932 !(ppd->dd->flags & QIB_PRESENT))
933 return 0;
934 return readl(&ppd->cpspec->cpregbase[regno]);
935}
936
937/* bits in Control register */
938#define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
939#define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
940
941/* bits in general interrupt regs */
942#define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
943#define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
944#define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
945#define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
946#define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
947#define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
948#define QIB_I_C_ERROR INT_MASK(Err)
949
950#define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
951#define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
952#define QIB_I_GPIO INT_MASK(AssertGPIO)
953#define QIB_I_P_SDMAINT(pidx) \
954 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
955 INT_MASK_P(SDmaProgress, pidx) | \
956 INT_MASK_PM(SDmaCleanupDone, pidx))
957
958/* Interrupt bits that are "per port" */
959#define QIB_I_P_BITSEXTANT(pidx) \
960 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
961 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
962 INT_MASK_P(SDmaProgress, pidx) | \
963 INT_MASK_PM(SDmaCleanupDone, pidx))
964
965/* Interrupt bits that are common to a device */
966/* currently unused: QIB_I_SPIOSENT */
967#define QIB_I_C_BITSEXTANT \
968 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
969 QIB_I_SPIOSENT | \
970 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
971
972#define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
973 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
974
975/*
976 * Error bits that are "per port".
977 */
978#define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
979#define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
980#define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
981#define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
982#define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
983#define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
984#define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
985#define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
986#define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
987#define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
988#define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
989#define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
990#define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
991#define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
992#define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
993#define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
994#define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
995#define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
996#define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
997#define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
998#define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
999#define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
1000#define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
1001#define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
1002#define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
1003#define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
1004#define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
1005#define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
1006
1007#define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
1008#define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
1009#define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
1010#define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
1011#define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
1012#define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
1013#define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
1014#define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
1015#define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
1016#define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
1017#define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
1018
1019/* Error bits that are common to a device */
1020#define QIB_E_RESET ERR_MASK(ResetNegated)
1021#define QIB_E_HARDWARE ERR_MASK(HardwareErr)
1022#define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
1023
1024
1025/*
1026 * Per chip (rather than per-port) errors. Most either do
1027 * nothing but trigger a print (because they self-recover, or
1028 * always occur in tandem with other errors that handle the
1029 * issue), or because they indicate errors with no recovery,
1030 * but we want to know that they happened.
1031 */
1032#define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
1033#define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
1034#define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
1035#define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
1036#define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
1037#define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
1038#define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
1039#define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
1040
1041/* SDMA chip errors (not per port)
1042 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
1043 * the SDMAHALT error immediately, so we just print the dup error via the
1044 * E_AUTO mechanism. This is true of most of the per-port fatal errors
1045 * as well, but since this is port-independent, by definition, it's
1046 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per
1047 * packet send errors, and so are handled in the same manner as other
1048 * per-packet errors.
1049 */
1050#define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
1051#define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
1052#define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
1053
1054/*
1055 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
1056 * it is used to print "common" packet errors.
1057 */
1058#define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
1059 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
1060 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
1061 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
1062 QIB_E_P_REBP)
1063
1064/* Error Bits that Packet-related (Receive, per-port) */
1065#define QIB_E_P_RPKTERRS (\
1066 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
1067 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
1068 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
1069 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
1070 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
1071 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
1072
1073/*
1074 * Error bits that are Send-related (per port)
1075 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
1076 * All of these potentially need to have a buffer disarmed
1077 */
1078#define QIB_E_P_SPKTERRS (\
1079 QIB_E_P_SUNEXP_PKTNUM |\
1080 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1081 QIB_E_P_SMAXPKTLEN |\
1082 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
1083 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
1084 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
1085
1086#define QIB_E_SPKTERRS ( \
1087 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
1088 ERR_MASK_N(SendUnsupportedVLErr) | \
1089 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
1090
1091#define QIB_E_P_SDMAERRS ( \
1092 QIB_E_P_SDMAHALT | \
1093 QIB_E_P_SDMADESCADDRMISALIGN | \
1094 QIB_E_P_SDMAUNEXPDATA | \
1095 QIB_E_P_SDMAMISSINGDW | \
1096 QIB_E_P_SDMADWEN | \
1097 QIB_E_P_SDMARPYTAG | \
1098 QIB_E_P_SDMA1STDESC | \
1099 QIB_E_P_SDMABASE | \
1100 QIB_E_P_SDMATAILOUTOFBOUND | \
1101 QIB_E_P_SDMAOUTOFBOUND | \
1102 QIB_E_P_SDMAGENMISMATCH)
1103
1104/*
1105 * This sets some bits more than once, but makes it more obvious which
1106 * bits are not handled under other categories, and the repeat definition
1107 * is not a problem.
1108 */
1109#define QIB_E_P_BITSEXTANT ( \
1110 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1111 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1112 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1113 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1114 )
1115
1116/*
1117 * These are errors that can occur when the link
1118 * changes state while a packet is being sent or received. This doesn't
1119 * cover things like EBP or VCRC that can be the result of a sending
1120 * having the link change state, so we receive a "known bad" packet.
1121 * All of these are "per port", so renamed:
1122 */
1123#define QIB_E_P_LINK_PKTERRS (\
1124 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1125 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1126 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1127 QIB_E_P_RUNEXPCHAR)
1128
1129/*
1130 * This sets some bits more than once, but makes it more obvious which
1131 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
1132 * and the repeat definition is not a problem.
1133 */
1134#define QIB_E_C_BITSEXTANT (\
1135 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1136 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1137 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1138
1139/* Likewise Neuter E_SPKT_ERRS_IGNORE */
1140#define E_SPKT_ERRS_IGNORE 0
1141
1142#define QIB_EXTS_MEMBIST_DISABLED \
1143 SYM_MASK(EXTStatus, MemBISTDisabled)
1144#define QIB_EXTS_MEMBIST_ENDTEST \
1145 SYM_MASK(EXTStatus, MemBISTEndTest)
1146
1147#define QIB_E_SPIOARMLAUNCH \
1148 ERR_MASK(SendArmLaunchErr)
1149
1150#define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1151#define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1152
1153/*
1154 * IBTA_1_2 is set when multiple speeds are enabled (normal),
1155 * and also if forced QDR (only QDR enabled). It's enabled for the
1156 * forced QDR case so that scrambling will be enabled by the TS3
1157 * exchange, when supported by both sides of the link.
1158 */
1159#define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1160#define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1161#define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1162#define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1163#define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1164#define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1165 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1166#define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1167
1168#define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1169#define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1170
1171#define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1172#define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1173#define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1174
1175#define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1176#define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1177#define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1178 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1179#define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1180 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1181#define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1182
1183#define IBA7322_REDIRECT_VEC_PER_REG 12
1184
1185#define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1186#define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1187#define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1188#define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1189#define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1190
1191#define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */
1192
1193#define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
e67306a3 1194 .msg = #fldname , .sz = sizeof(#fldname) }
f931551b 1195#define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
e67306a3 1196 fldname##Mask##_##port), .msg = #fldname , .sz = sizeof(#fldname) }
f931551b
RC		 1197static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1198 HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
1199 HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
1200 HWE_AUTO(PCIESerdesPClkNotDetect),
1201 HWE_AUTO(PowerOnBISTFailed),
1202 HWE_AUTO(TempsenseTholdReached),
1203 HWE_AUTO(MemoryErr),
1204 HWE_AUTO(PCIeBusParityErr),
1205 HWE_AUTO(PcieCplTimeout),
1206 HWE_AUTO(PciePoisonedTLP),
1207 HWE_AUTO_P(SDmaMemReadErr, 1),
1208 HWE_AUTO_P(SDmaMemReadErr, 0),
1209 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
b9e03e04 1210 HWE_AUTO_P(IBCBusToSPCParityErr, 1),
f931551b 1211 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
b9e03e04 1212 HWE_AUTO(statusValidNoEop),
f931551b 1213 HWE_AUTO(LATriggered),
e67306a3 1214 { .mask = 0, .sz = 0 }
f931551b
RC		 1215};
1216
1217#define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
e67306a3 1218 .msg = #fldname, .sz = sizeof(#fldname) }
f931551b 1219#define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
e67306a3 1220 .msg = #fldname, .sz = sizeof(#fldname) }
f931551b 1221static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
e67306a3
MM		 1222 E_AUTO(RcvEgrFullErr),
1223 E_AUTO(RcvHdrFullErr),
f931551b
RC		 1224 E_AUTO(ResetNegated),
1225 E_AUTO(HardwareErr),
1226 E_AUTO(InvalidAddrErr),
1227 E_AUTO(SDmaVL15Err),
1228 E_AUTO(SBufVL15MisUseErr),
1229 E_AUTO(InvalidEEPCmd),
1230 E_AUTO(RcvContextShareErr),
1231 E_AUTO(SendVLMismatchErr),
1232 E_AUTO(SendArmLaunchErr),
1233 E_AUTO(SendSpecialTriggerErr),
1234 E_AUTO(SDmaWrongPortErr),
1235 E_AUTO(SDmaBufMaskDuplicateErr),
e67306a3 1236 { .mask = 0, .sz = 0 }
f931551b
RC		 1237};
1238
1239static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = {
1240 E_P_AUTO(IBStatusChanged),
1241 E_P_AUTO(SHeadersErr),
1242 E_P_AUTO(VL15BufMisuseErr),
1243 /*
1244 * SDmaHaltErr is not really an error, make it clearer;
1245 */
e67306a3
MM		 1246 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted",
1247 .sz = 11},
f931551b
RC		 1248 E_P_AUTO(SDmaDescAddrMisalignErr),
1249 E_P_AUTO(SDmaUnexpDataErr),
1250 E_P_AUTO(SDmaMissingDwErr),
1251 E_P_AUTO(SDmaDwEnErr),
1252 E_P_AUTO(SDmaRpyTagErr),
1253 E_P_AUTO(SDma1stDescErr),
1254 E_P_AUTO(SDmaBaseErr),
1255 E_P_AUTO(SDmaTailOutOfBoundErr),
1256 E_P_AUTO(SDmaOutOfBoundErr),
1257 E_P_AUTO(SDmaGenMismatchErr),
1258 E_P_AUTO(SendBufMisuseErr),
1259 E_P_AUTO(SendUnsupportedVLErr),
1260 E_P_AUTO(SendUnexpectedPktNumErr),
1261 E_P_AUTO(SendDroppedDataPktErr),
1262 E_P_AUTO(SendDroppedSmpPktErr),
1263 E_P_AUTO(SendPktLenErr),
1264 E_P_AUTO(SendUnderRunErr),
1265 E_P_AUTO(SendMaxPktLenErr),
1266 E_P_AUTO(SendMinPktLenErr),
1267 E_P_AUTO(RcvIBLostLinkErr),
1268 E_P_AUTO(RcvHdrErr),
1269 E_P_AUTO(RcvHdrLenErr),
1270 E_P_AUTO(RcvBadTidErr),
1271 E_P_AUTO(RcvBadVersionErr),
1272 E_P_AUTO(RcvIBFlowErr),
1273 E_P_AUTO(RcvEBPErr),
1274 E_P_AUTO(RcvUnsupportedVLErr),
1275 E_P_AUTO(RcvUnexpectedCharErr),
1276 E_P_AUTO(RcvShortPktLenErr),
1277 E_P_AUTO(RcvLongPktLenErr),
1278 E_P_AUTO(RcvMaxPktLenErr),
1279 E_P_AUTO(RcvMinPktLenErr),
1280 E_P_AUTO(RcvICRCErr),
1281 E_P_AUTO(RcvVCRCErr),
1282 E_P_AUTO(RcvFormatErr),
e67306a3 1283 { .mask = 0, .sz = 0 }
f931551b
RC		 1284};
1285
1286/*
1287 * Below generates "auto-message" for interrupts not specific to any port or
1288 * context
1289 */
1290#define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
e67306a3 1291 .msg = #fldname, .sz = sizeof(#fldname) }
f931551b
RC		 1292/* Below generates "auto-message" for interrupts specific to a port */
1293#define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1294 SYM_LSB(IntMask, fldname##Mask##_0), \
1295 SYM_LSB(IntMask, fldname##Mask##_1)), \
e67306a3 1296 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
f931551b
RC		 1297/* For some reason, the SerDesTrimDone bits are reversed */
1298#define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1299 SYM_LSB(IntMask, fldname##Mask##_1), \
1300 SYM_LSB(IntMask, fldname##Mask##_0)), \
e67306a3 1301 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
f931551b
RC		 1302/*
1303 * Below generates "auto-message" for interrupts specific to a context,
1304 * with ctxt-number appended
1305 */
1306#define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1307 SYM_LSB(IntMask, fldname##0IntMask), \
1308 SYM_LSB(IntMask, fldname##17IntMask)), \
e67306a3 1309 .msg = #fldname "_C", .sz = sizeof(#fldname "_C") }
f931551b
RC		 1310
1311static const struct qib_hwerror_msgs qib_7322_intr_msgs[] = {
1312 INTR_AUTO_P(SDmaInt),
1313 INTR_AUTO_P(SDmaProgressInt),
1314 INTR_AUTO_P(SDmaIdleInt),
1315 INTR_AUTO_P(SDmaCleanupDone),
1316 INTR_AUTO_C(RcvUrg),
1317 INTR_AUTO_P(ErrInt),
1318 INTR_AUTO(ErrInt), /* non-port-specific errs */
1319 INTR_AUTO(AssertGPIOInt),
1320 INTR_AUTO_P(SendDoneInt),
1321 INTR_AUTO(SendBufAvailInt),
1322 INTR_AUTO_C(RcvAvail),
e67306a3 1323 { .mask = 0, .sz = 0 }
f931551b
RC		 1324};
1325
1326#define TXSYMPTOM_AUTO_P(fldname) \
e67306a3
MM		 1327 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \
1328 .msg = #fldname, .sz = sizeof(#fldname) }
f931551b
RC		 1329static const struct qib_hwerror_msgs hdrchk_msgs[] = {
1330 TXSYMPTOM_AUTO_P(NonKeyPacket),
1331 TXSYMPTOM_AUTO_P(GRHFail),
1332 TXSYMPTOM_AUTO_P(PkeyFail),
1333 TXSYMPTOM_AUTO_P(QPFail),
1334 TXSYMPTOM_AUTO_P(SLIDFail),
1335 TXSYMPTOM_AUTO_P(RawIPV6),
1336 TXSYMPTOM_AUTO_P(PacketTooSmall),
e67306a3 1337 { .mask = 0, .sz = 0 }
f931551b
RC		 1338};
1339
1340#define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
1341
1342/*
1343 * Called when we might have an error that is specific to a particular
1344 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1345 * because we don't need to force the update of pioavail
1346 */
1347static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
1348{
1349 struct qib_devdata *dd = ppd->dd;
1350 u32 i;
1351 int any;
1352 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
1353 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
1354 unsigned long sbuf[4];
1355
1356 /*
1357 * It's possible that sendbuffererror could have bits set; might
1358 * have already done this as a result of hardware error handling.
1359 */
1360 any = 0;
1361 for (i = 0; i < regcnt; ++i) {
1362 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
1363 if (sbuf[i]) {
1364 any = 1;
1365 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
1366 }
1367 }
1368
1369 if (any)
1370 qib_disarm_piobufs_set(dd, sbuf, piobcnt);
1371}
1372
1373/* No txe_recover yet, if ever */
1374
1375/* No decode__errors yet */
1376static void err_decode(char *msg, size_t len, u64 errs,
1377 const struct qib_hwerror_msgs *msp)
1378{
1379 u64 these, lmask;
1380 int took, multi, n = 0;
1381
e67306a3 1382 while (errs && msp && msp->mask) {
f931551b
RC		 1383 multi = (msp->mask & (msp->mask - 1));
1384 while (errs & msp->mask) {
1385 these = (errs & msp->mask);
1386 lmask = (these & (these - 1)) ^ these;
1387 if (len) {
1388 if (n++) {
1389 /* separate the strings */
1390 *msg++ = ',';
1391 len--;
1392 }
e67306a3
MM		 1393 BUG_ON(!msp->sz);
1394 /* msp->sz counts the nul */
1395 took = min_t(size_t, msp->sz - (size_t)1, len);
1396 memcpy(msg, msp->msg, took);
f931551b
RC		 1397 len -= took;
1398 msg += took;
e67306a3
MM		 1399 if (len)
1400 *msg = '\0';
f931551b
RC		 1401 }
1402 errs &= ~lmask;
1403 if (len && multi) {
1404 /* More than one bit this mask */
1405 int idx = -1;
1406
1407 while (lmask & msp->mask) {
1408 ++idx;
1409 lmask >>= 1;
1410 }
1411 took = scnprintf(msg, len, "_%d", idx);
1412 len -= took;
1413 msg += took;
1414 }
1415 }
1416 ++msp;
1417 }
1418 /* If some bits are left, show in hex. */
1419 if (len && errs)
1420 snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
1421 (unsigned long long) errs);
1422}
1423
1424/* only called if r1 set */
1425static void flush_fifo(struct qib_pportdata *ppd)
1426{
1427 struct qib_devdata *dd = ppd->dd;
1428 u32 __iomem *piobuf;
1429 u32 bufn;
1430 u32 *hdr;
1431 u64 pbc;
1432 const unsigned hdrwords = 7;
1433 static struct qib_ib_header ibhdr = {
1434 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
1435 .lrh[1] = IB_LID_PERMISSIVE,
1436 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
1437 .lrh[3] = IB_LID_PERMISSIVE,
1438 .u.oth.bth[0] = cpu_to_be32(
1439 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
1440 .u.oth.bth[1] = cpu_to_be32(0),
1441 .u.oth.bth[2] = cpu_to_be32(0),
1442 .u.oth.u.ud.deth[0] = cpu_to_be32(0),
1443 .u.oth.u.ud.deth[1] = cpu_to_be32(0),
1444 };
1445
1446 /*
1447 * Send a dummy VL15 packet to flush the launch FIFO.
1448 * This will not actually be sent since the TxeBypassIbc bit is set.
1449 */
1450 pbc = PBC_7322_VL15_SEND |
1451 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
1452 (hdrwords + SIZE_OF_CRC);
1453 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
1454 if (!piobuf)
1455 return;
1456 writeq(pbc, piobuf);
1457 hdr = (u32 *) &ibhdr;
1458 if (dd->flags & QIB_PIO_FLUSH_WC) {
1459 qib_flush_wc();
1460 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
1461 qib_flush_wc();
1462 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
1463 qib_flush_wc();
1464 } else
1465 qib_pio_copy(piobuf + 2, hdr, hdrwords);
1466 qib_sendbuf_done(dd, bufn);
1467}
1468
1469/*
1470 * This is called with interrupts disabled and sdma_lock held.
1471 */
1472static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
1473{
1474 struct qib_devdata *dd = ppd->dd;
1475 u64 set_sendctrl = 0;
1476 u64 clr_sendctrl = 0;
1477
1478 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
1479 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1480 else
1481 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1482
1483 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
1484 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1485 else
1486 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1487
1488 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
1489 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1490 else
1491 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1492
1493 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
1494 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1495 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1496 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1497 else
1498 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1499 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1500 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1501
1502 spin_lock(&dd->sendctrl_lock);
1503
1504 /* If we are draining everything, block sends first */
1505 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1506 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1507 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1508 qib_write_kreg(dd, kr_scratch, 0);
1509 }
1510
1511 ppd->p_sendctrl |= set_sendctrl;
1512 ppd->p_sendctrl &= ~clr_sendctrl;
1513
1514 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
1515 qib_write_kreg_port(ppd, krp_sendctrl,
1516 ppd->p_sendctrl |
1517 SYM_MASK(SendCtrl_0, SDmaCleanup));
1518 else
1519 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1520 qib_write_kreg(dd, kr_scratch, 0);
1521
1522 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1523 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1524 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1525 qib_write_kreg(dd, kr_scratch, 0);
1526 }
1527
1528 spin_unlock(&dd->sendctrl_lock);
1529
1530 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1531 flush_fifo(ppd);
1532}
1533
1534static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
1535{
1536 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
1537}
1538
1539static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
1540{
1541 /*
1542 * Set SendDmaLenGen and clear and set
1543 * the MSB of the generation count to enable generation checking
1544 * and load the internal generation counter.
1545 */
1546 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
1547 qib_write_kreg_port(ppd, krp_senddmalengen,
1548 ppd->sdma_descq_cnt |
1549 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
1550}
1551
1552/*
1553 * Must be called with sdma_lock held, or before init finished.
1554 */
1555static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
1556{
1557 /* Commit writes to memory and advance the tail on the chip */
1558 wmb();
1559 ppd->sdma_descq_tail = tail;
1560 qib_write_kreg_port(ppd, krp_senddmatail, tail);
1561}
1562
1563/*
1564 * This is called with interrupts disabled and sdma_lock held.
1565 */
1566static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
1567{
1568 /*
1569 * Drain all FIFOs.
1570 * The hardware doesn't require this but we do it so that verbs
1571 * and user applications don't wait for link active to send stale
1572 * data.
1573 */
1574 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);
1575
1576 qib_sdma_7322_setlengen(ppd);
1577 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
1578 ppd->sdma_head_dma[0] = 0;
1579 qib_7322_sdma_sendctrl(ppd,
1580 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
1581}
1582
1583#define DISABLES_SDMA ( \
1584 QIB_E_P_SDMAHALT | \
1585 QIB_E_P_SDMADESCADDRMISALIGN | \
1586 QIB_E_P_SDMAMISSINGDW | \
1587 QIB_E_P_SDMADWEN | \
1588 QIB_E_P_SDMARPYTAG | \
1589 QIB_E_P_SDMA1STDESC | \
1590 QIB_E_P_SDMABASE | \
1591 QIB_E_P_SDMATAILOUTOFBOUND | \
1592 QIB_E_P_SDMAOUTOFBOUND | \
1593 QIB_E_P_SDMAGENMISMATCH)
1594
1595static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
1596{
1597 unsigned long flags;
1598 struct qib_devdata *dd = ppd->dd;
1599
1600 errs &= QIB_E_P_SDMAERRS;
b268e4db
MM		 1601 err_decode(ppd->cpspec->sdmamsgbuf, sizeof(ppd->cpspec->sdmamsgbuf),
1602 errs, qib_7322p_error_msgs);
f931551b
RC		 1603
1604 if (errs & QIB_E_P_SDMAUNEXPDATA)
1605 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
1606 ppd->port);
1607
1608 spin_lock_irqsave(&ppd->sdma_lock, flags);
1609
0b3ddf38
DL		 1610 if (errs != QIB_E_P_SDMAHALT) {
1611 /* SDMA errors have QIB_E_P_SDMAHALT and another bit set */
1612 qib_dev_porterr(dd, ppd->port,
1613 "SDMA %s 0x%016llx %s\n",
1614 qib_sdma_state_names[ppd->sdma_state.current_state],
1615 errs, ppd->cpspec->sdmamsgbuf);
1616 dump_sdma_7322_state(ppd);
1617 }
1618
f931551b
RC		 1619 switch (ppd->sdma_state.current_state) {
1620 case qib_sdma_state_s00_hw_down:
1621 break;
1622
1623 case qib_sdma_state_s10_hw_start_up_wait:
1624 if (errs & QIB_E_P_SDMAHALT)
1625 __qib_sdma_process_event(ppd,
1626 qib_sdma_event_e20_hw_started);
1627 break;
1628
1629 case qib_sdma_state_s20_idle:
1630 break;
1631
1632 case qib_sdma_state_s30_sw_clean_up_wait:
1633 break;
1634
1635 case qib_sdma_state_s40_hw_clean_up_wait:
1636 if (errs & QIB_E_P_SDMAHALT)
1637 __qib_sdma_process_event(ppd,
1638 qib_sdma_event_e50_hw_cleaned);
1639 break;
1640
1641 case qib_sdma_state_s50_hw_halt_wait:
1642 if (errs & QIB_E_P_SDMAHALT)
1643 __qib_sdma_process_event(ppd,
1644 qib_sdma_event_e60_hw_halted);
1645 break;
1646
1647 case qib_sdma_state_s99_running:
1648 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
1649 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1650 break;
1651 }
1652
1653 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1654}
1655
1656/*
1657 * handle per-device errors (not per-port errors)
1658 */
1659static noinline void handle_7322_errors(struct qib_devdata *dd)
1660{
1661 char *msg;
1662 u64 iserr = 0;
1663 u64 errs;
1664 u64 mask;
1665 int log_idx;
1666
1667 qib_stats.sps_errints++;
1668 errs = qib_read_kreg64(dd, kr_errstatus);
1669 if (!errs) {
7fac3301
MM		 1670 qib_devinfo(dd->pcidev,
1671 "device error interrupt, but no error bits set!\n");
f931551b
RC		 1672 goto done;
1673 }
1674
1675 /* don't report errors that are masked */
1676 errs &= dd->cspec->errormask;
1677 msg = dd->cspec->emsgbuf;
1678
1679 /* do these first, they are most important */
1680 if (errs & QIB_E_HARDWARE) {
1681 *msg = '\0';
041af0bb 1682 qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf));
f931551b
RC		 1683 } else
1684 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1685 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1686 qib_inc_eeprom_err(dd, log_idx, 1);
1687
1688 if (errs & QIB_E_SPKTERRS) {
1689 qib_disarm_7322_senderrbufs(dd->pport);
1690 qib_stats.sps_txerrs++;
1691 } else if (errs & QIB_E_INVALIDADDR)
1692 qib_stats.sps_txerrs++;
1693 else if (errs & QIB_E_ARMLAUNCH) {
1694 qib_stats.sps_txerrs++;
1695 qib_disarm_7322_senderrbufs(dd->pport);
1696 }
1697 qib_write_kreg(dd, kr_errclear, errs);
1698
1699 /*
1700 * The ones we mask off are handled specially below
1701 * or above. Also mask SDMADISABLED by default as it
1702 * is too chatty.
1703 */
1704 mask = QIB_E_HARDWARE;
1705 *msg = '\0';
1706
041af0bb 1707 err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask,
f931551b
RC		 1708 qib_7322error_msgs);
1709
1710 /*
1711 * Getting reset is a tragedy for all ports. Mark the device
1712 * _and_ the ports as "offline" in way meaningful to each.
1713 */
1714 if (errs & QIB_E_RESET) {
1715 int pidx;
1716
7fac3301
MM		 1717 qib_dev_err(dd,
1718 "Got reset, requires re-init (unload and reload driver)\n");
f931551b
RC		 1719 dd->flags &= ~QIB_INITTED; /* needs re-init */
1720 /* mark as having had error */
1721 *dd->devstatusp |= QIB_STATUS_HWERROR;
1722 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1723 if (dd->pport[pidx].link_speed_supported)
1724 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
1725 }
1726
1727 if (*msg && iserr)
1728 qib_dev_err(dd, "%s error\n", msg);
1729
1730 /*
1731 * If there were hdrq or egrfull errors, wake up any processes
1732 * waiting in poll. We used to try to check which contexts had
1733 * the overflow, but given the cost of that and the chip reads
1734 * to support it, it's better to just wake everybody up if we
1735 * get an overflow; waiters can poll again if it's not them.
1736 */
1737 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1738 qib_handle_urcv(dd, ~0U);
1739 if (errs & ERR_MASK(RcvEgrFullErr))
1740 qib_stats.sps_buffull++;
1741 else
1742 qib_stats.sps_hdrfull++;
1743 }
1744
1745done:
1746 return;
1747}
1748
e67306a3
MM		 1749static void qib_error_tasklet(unsigned long data)
1750{
1751 struct qib_devdata *dd = (struct qib_devdata *)data;
1752
1753 handle_7322_errors(dd);
1754 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1755}
1756
f931551b
RC		 1757static void reenable_chase(unsigned long opaque)
1758{
1759 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1760
1761 ppd->cpspec->chase_timer.expires = 0;
1762 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1763 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1764}
1765
8482d5d1
MM		 1766static void disable_chase(struct qib_pportdata *ppd, unsigned long tnow,
1767 u8 ibclt)
f931551b
RC		 1768{
1769 ppd->cpspec->chase_end = 0;
1770
1771 if (!qib_chase)
1772 return;
1773
1774 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1775 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1776 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
1777 add_timer(&ppd->cpspec->chase_timer);
1778}
1779
1780static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
1781{
1782 u8 ibclt;
8482d5d1 1783 unsigned long tnow;
f931551b
RC		 1784
1785 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);
1786
1787 /*
1788 * Detect and handle the state chase issue, where we can
1789 * get stuck if we are unlucky on timing on both sides of
1790 * the link. If we are, we disable, set a timer, and
1791 * then re-enable.
1792 */
1793 switch (ibclt) {
1794 case IB_7322_LT_STATE_CFGRCVFCFG:
1795 case IB_7322_LT_STATE_CFGWAITRMT:
1796 case IB_7322_LT_STATE_TXREVLANES:
1797 case IB_7322_LT_STATE_CFGENH:
8482d5d1 1798 tnow = jiffies;
f931551b 1799 if (ppd->cpspec->chase_end &&
8482d5d1 1800 time_after(tnow, ppd->cpspec->chase_end))
f931551b
RC		 1801 disable_chase(ppd, tnow, ibclt);
1802 else if (!ppd->cpspec->chase_end)
1803 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1804 break;
1805 default:
1806 ppd->cpspec->chase_end = 0;
1807 break;
1808 }
1809
31264484
MH		 1810 if (((ibclt >= IB_7322_LT_STATE_CFGTEST &&
1811 ibclt <= IB_7322_LT_STATE_CFGWAITENH) ||
1812 ibclt == IB_7322_LT_STATE_LINKUP) &&
f931551b
RC		 1813 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1814 force_h1(ppd);
1815 ppd->cpspec->qdr_reforce = 1;
a0a234d4
MM		 1816 if (!ppd->dd->cspec->r1)
1817 serdes_7322_los_enable(ppd, 0);
f931551b
RC		 1818 } else if (ppd->cpspec->qdr_reforce &&
1819 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1820 (ibclt == IB_7322_LT_STATE_CFGENH ||
1821 ibclt == IB_7322_LT_STATE_CFGIDLE ||
1822 ibclt == IB_7322_LT_STATE_LINKUP))
1823 force_h1(ppd);
1824
1825 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
1826 ppd->link_speed_enabled == QIB_IB_QDR &&
1827 (ibclt == IB_7322_LT_STATE_CFGTEST ||
1828 ibclt == IB_7322_LT_STATE_CFGENH ||
1829 (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
1830 ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
1831 adj_tx_serdes(ppd);
1832
a0a234d4
MM		 1833 if (ibclt != IB_7322_LT_STATE_LINKUP) {
1834 u8 ltstate = qib_7322_phys_portstate(ibcst);
1835 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
1836 LinkTrainingState);
1837 if (!ppd->dd->cspec->r1 &&
1838 pibclt == IB_7322_LT_STATE_LINKUP &&
1839 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1840 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1841 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1842 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1843 /* If the link went down (but no into recovery,
1844 * turn LOS back on */
1845 serdes_7322_los_enable(ppd, 1);
1846 if (!ppd->cpspec->qdr_dfe_on &&
1847 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
1848 ppd->cpspec->qdr_dfe_on = 1;
1849 ppd->cpspec->qdr_dfe_time = 0;
1850 /* On link down, reenable QDR adaptation */
1851 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
1852 ppd->dd->cspec->r1 ?
1853 QDR_STATIC_ADAPT_DOWN_R1 :
1854 QDR_STATIC_ADAPT_DOWN);
7fac3301
MM		 1855 pr_info(
1856 "IB%u:%u re-enabled QDR adaptation ibclt %x\n",
1857 ppd->dd->unit, ppd->port, ibclt);
a0a234d4 1858 }
f931551b
RC		 1859 }
1860}
1861
f2d255a0
MM		 1862static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32);
1863
f931551b
RC		 1864/*
1865 * This is per-pport error handling.
1866 * will likely get it's own MSIx interrupt (one for each port,
1867 * although just a single handler).
1868 */
1869static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
1870{
1871 char *msg;
1872 u64 ignore_this_time = 0, iserr = 0, errs, fmask;
1873 struct qib_devdata *dd = ppd->dd;
1874
1875 /* do this as soon as possible */
1876 fmask = qib_read_kreg64(dd, kr_act_fmask);
1877 if (!fmask)
1878 check_7322_rxe_status(ppd);
1879
1880 errs = qib_read_kreg_port(ppd, krp_errstatus);
1881 if (!errs)
1882 qib_devinfo(dd->pcidev,
1883 "Port%d error interrupt, but no error bits set!\n",
1884 ppd->port);
1885 if (!fmask)
1886 errs &= ~QIB_E_P_IBSTATUSCHANGED;
1887 if (!errs)
1888 goto done;
1889
1890 msg = ppd->cpspec->epmsgbuf;
1891 *msg = '\0';
1892
1893 if (errs & ~QIB_E_P_BITSEXTANT) {
041af0bb 1894 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf),
f931551b
RC		 1895 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
1896 if (!*msg)
041af0bb 1897 snprintf(msg, sizeof(ppd->cpspec->epmsgbuf),
f931551b 1898 "no others");
7fac3301
MM		 1899 qib_dev_porterr(dd, ppd->port,
1900 "error interrupt with unknown errors 0x%016Lx set (and %s)\n",
1901 (errs & ~QIB_E_P_BITSEXTANT), msg);
f931551b
RC		 1902 *msg = '\0';
1903 }
1904
1905 if (errs & QIB_E_P_SHDR) {
1906 u64 symptom;
1907
1908 /* determine cause, then write to clear */
1909 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
1910 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
041af0bb 1911 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), symptom,
f931551b
RC		 1912 hdrchk_msgs);
1913 *msg = '\0';
1914 /* senderrbuf cleared in SPKTERRS below */
1915 }
1916
1917 if (errs & QIB_E_P_SPKTERRS) {
1918 if ((errs & QIB_E_P_LINK_PKTERRS) &&
1919 !(ppd->lflags & QIBL_LINKACTIVE)) {
1920 /*
1921 * This can happen when trying to bring the link
1922 * up, but the IB link changes state at the "wrong"
1923 * time. The IB logic then complains that the packet
1924 * isn't valid. We don't want to confuse people, so
1925 * we just don't print them, except at debug
1926 */
041af0bb 1927 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf),
f931551b
RC		 1928 (errs & QIB_E_P_LINK_PKTERRS),
1929 qib_7322p_error_msgs);
1930 *msg = '\0';
1931 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1932 }
1933 qib_disarm_7322_senderrbufs(ppd);
1934 } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
1935 !(ppd->lflags & QIBL_LINKACTIVE)) {
1936 /*
1937 * This can happen when SMA is trying to bring the link
1938 * up, but the IB link changes state at the "wrong" time.
1939 * The IB logic then complains that the packet isn't
1940 * valid. We don't want to confuse people, so we just
1941 * don't print them, except at debug
1942 */
041af0bb 1943 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), errs,
f931551b
RC		 1944 qib_7322p_error_msgs);
1945 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1946 *msg = '\0';
1947 }
1948
1949 qib_write_kreg_port(ppd, krp_errclear, errs);
1950
1951 errs &= ~ignore_this_time;
1952 if (!errs)
1953 goto done;
1954
1955 if (errs & QIB_E_P_RPKTERRS)
1956 qib_stats.sps_rcverrs++;
1957 if (errs & QIB_E_P_SPKTERRS)
1958 qib_stats.sps_txerrs++;
1959
1960 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);
1961
1962 if (errs & QIB_E_P_SDMAERRS)
1963 sdma_7322_p_errors(ppd, errs);
1964
1965 if (errs & QIB_E_P_IBSTATUSCHANGED) {
1966 u64 ibcs;
1967 u8 ltstate;
1968
1969 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
1970 ltstate = qib_7322_phys_portstate(ibcs);
1971
1972 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1973 handle_serdes_issues(ppd, ibcs);
1974 if (!(ppd->cpspec->ibcctrl_a &
1975 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1976 /*
1977 * We got our interrupt, so init code should be
1978 * happy and not try alternatives. Now squelch
1979 * other "chatter" from link-negotiation (pre Init)
1980 */
1981 ppd->cpspec->ibcctrl_a |=
1982 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1983 qib_write_kreg_port(ppd, krp_ibcctrl_a,
1984 ppd->cpspec->ibcctrl_a);
1985 }
1986
1987 /* Update our picture of width and speed from chip */
1988 ppd->link_width_active =
1989 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1990 IB_WIDTH_4X : IB_WIDTH_1X;
1991 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1992 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
1993 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1994 QIB_IB_DDR : QIB_IB_SDR;
1995
1996 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
1997 IB_PHYSPORTSTATE_DISABLED)
1998 qib_set_ib_7322_lstate(ppd, 0,
1999 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
d70585f7 2000 else
f931551b
RC		 2001 /*
2002 * Since going into a recovery state causes the link
2003 * state to go down and since recovery is transitory,
2004 * it is better if we "miss" ever seeing the link
2005 * training state go into recovery (i.e., ignore this
2006 * transition for link state special handling purposes)
2007 * without updating lastibcstat.
2008 */
2009 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
2010 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
2011 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
2012 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
2013 qib_handle_e_ibstatuschanged(ppd, ibcs);
2014 }
2015 if (*msg && iserr)
2016 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
2017
2018 if (ppd->state_wanted & ppd->lflags)
2019 wake_up_interruptible(&ppd->state_wait);
2020done:
2021 return;
2022}
2023
2024/* enable/disable chip from delivering interrupts */
2025static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
2026{
2027 if (enable) {
2028 if (dd->flags & QIB_BADINTR)
2029 return;
2030 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
2031 /* cause any pending enabled interrupts to be re-delivered */
2032 qib_write_kreg(dd, kr_intclear, 0ULL);
2033 if (dd->cspec->num_msix_entries) {
2034 /* and same for MSIx */
2035 u64 val = qib_read_kreg64(dd, kr_intgranted);
da12c1f6 2036
f931551b
RC		 2037 if (val)
2038 qib_write_kreg(dd, kr_intgranted, val);
2039 }
2040 } else
2041 qib_write_kreg(dd, kr_intmask, 0ULL);
2042}
2043
2044/*
2045 * Try to cleanup as much as possible for anything that might have gone
2046 * wrong while in freeze mode, such as pio buffers being written by user
2047 * processes (causing armlaunch), send errors due to going into freeze mode,
2048 * etc., and try to avoid causing extra interrupts while doing so.
2049 * Forcibly update the in-memory pioavail register copies after cleanup
2050 * because the chip won't do it while in freeze mode (the register values
2051 * themselves are kept correct).
2052 * Make sure that we don't lose any important interrupts by using the chip
2053 * feature that says that writing 0 to a bit in *clear that is set in
2054 * *status will cause an interrupt to be generated again (if allowed by
2055 * the *mask value).
2056 * This is in chip-specific code because of all of the register accesses,
2057 * even though the details are similar on most chips.
2058 */
2059static void qib_7322_clear_freeze(struct qib_devdata *dd)
2060{
2061 int pidx;
2062
2063 /* disable error interrupts, to avoid confusion */
2064 qib_write_kreg(dd, kr_errmask, 0ULL);
2065
2066 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2067 if (dd->pport[pidx].link_speed_supported)
2068 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2069 0ULL);
2070
2071 /* also disable interrupts; errormask is sometimes overwriten */
2072 qib_7322_set_intr_state(dd, 0);
2073
2074 /* clear the freeze, and be sure chip saw it */
2075 qib_write_kreg(dd, kr_control, dd->control);
2076 qib_read_kreg32(dd, kr_scratch);
2077
2078 /*
2079 * Force new interrupt if any hwerr, error or interrupt bits are
2080 * still set, and clear "safe" send packet errors related to freeze
2081 * and cancelling sends. Re-enable error interrupts before possible
2082 * force of re-interrupt on pending interrupts.
2083 */
2084 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
2085 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
2086 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2087 /* We need to purge per-port errs and reset mask, too */
2088 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
2089 if (!dd->pport[pidx].link_speed_supported)
2090 continue;
2091 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
2092 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
2093 }
2094 qib_7322_set_intr_state(dd, 1);
2095}
2096
2097/* no error handling to speak of */
2098/**
2099 * qib_7322_handle_hwerrors - display hardware errors.
2100 * @dd: the qlogic_ib device
2101 * @msg: the output buffer
2102 * @msgl: the size of the output buffer
2103 *
2104 * Use same msg buffer as regular errors to avoid excessive stack
2105 * use. Most hardware errors are catastrophic, but for right now,
2106 * we'll print them and continue. We reuse the same message buffer as
2107 * qib_handle_errors() to avoid excessive stack usage.
2108 */
2109static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
2110 size_t msgl)
2111{
2112 u64 hwerrs;
2113 u32 ctrl;
2114 int isfatal = 0;
2115
2116 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2117 if (!hwerrs)
2118 goto bail;
2119 if (hwerrs == ~0ULL) {
7fac3301
MM		 2120 qib_dev_err(dd,
2121 "Read of hardware error status failed (all bits set); ignoring\n");
f931551b
RC		 2122 goto bail;
2123 }
2124 qib_stats.sps_hwerrs++;
2125
2126 /* Always clear the error status register, except BIST fail */
2127 qib_write_kreg(dd, kr_hwerrclear, hwerrs &
2128 ~HWE_MASK(PowerOnBISTFailed));
2129
2130 hwerrs &= dd->cspec->hwerrmask;
2131
2132 /* no EEPROM logging, yet */
2133
2134 if (hwerrs)
7fac3301
MM		 2135 qib_devinfo(dd->pcidev,
2136 "Hardware error: hwerr=0x%llx (cleared)\n",
2137 (unsigned long long) hwerrs);
f931551b
RC		 2138
2139 ctrl = qib_read_kreg32(dd, kr_control);
2140 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
2141 /*
2142 * No recovery yet...
2143 */
2144 if ((hwerrs & ~HWE_MASK(LATriggered)) ||
2145 dd->cspec->stay_in_freeze) {
2146 /*
2147 * If any set that we aren't ignoring only make the
2148 * complaint once, in case it's stuck or recurring,
2149 * and we get here multiple times
2150 * Force link down, so switch knows, and
2151 * LEDs are turned off.
2152 */
2153 if (dd->flags & QIB_INITTED)
2154 isfatal = 1;
2155 } else
2156 qib_7322_clear_freeze(dd);
2157 }
2158
2159 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
2160 isfatal = 1;
7fac3301
MM		 2161 strlcpy(msg,
2162 "[Memory BIST test failed, InfiniPath hardware unusable]",
2163 msgl);
f931551b
RC		 2164 /* ignore from now on, so disable until driver reloaded */
2165 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2166 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2167 }
2168
2169 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);
2170
2171 /* Ignore esoteric PLL failures et al. */
2172
2173 qib_dev_err(dd, "%s hardware error\n", msg);
2174
0b3ddf38
DL		 2175 if (hwerrs &
2176 (SYM_MASK(HwErrMask, SDmaMemReadErrMask_0) |
2177 SYM_MASK(HwErrMask, SDmaMemReadErrMask_1))) {
2178 int pidx = 0;
2179 int err;
2180 unsigned long flags;
2181 struct qib_pportdata *ppd = dd->pport;
da12c1f6 2182
0b3ddf38
DL		 2183 for (; pidx < dd->num_pports; ++pidx, ppd++) {
2184 err = 0;
2185 if (pidx == 0 && (hwerrs &
2186 SYM_MASK(HwErrMask, SDmaMemReadErrMask_0)))
2187 err++;
2188 if (pidx == 1 && (hwerrs &
2189 SYM_MASK(HwErrMask, SDmaMemReadErrMask_1)))
2190 err++;
2191 if (err) {
2192 spin_lock_irqsave(&ppd->sdma_lock, flags);
2193 dump_sdma_7322_state(ppd);
2194 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
2195 }
2196 }
2197 }
2198
f931551b 2199 if (isfatal && !dd->diag_client) {
7fac3301
MM		 2200 qib_dev_err(dd,
2201 "Fatal Hardware Error, no longer usable, SN %.16s\n",
2202 dd->serial);
f931551b
RC		 2203 /*
2204 * for /sys status file and user programs to print; if no
2205 * trailing brace is copied, we'll know it was truncated.
2206 */
2207 if (dd->freezemsg)
2208 snprintf(dd->freezemsg, dd->freezelen,
2209 "{%s}", msg);
2210 qib_disable_after_error(dd);
2211 }
2212bail:;
2213}
2214
2215/**
2216 * qib_7322_init_hwerrors - enable hardware errors
2217 * @dd: the qlogic_ib device
2218 *
2219 * now that we have finished initializing everything that might reasonably
2220 * cause a hardware error, and cleared those errors bits as they occur,
2221 * we can enable hardware errors in the mask (potentially enabling
2222 * freeze mode), and enable hardware errors as errors (along with
2223 * everything else) in errormask
2224 */
2225static void qib_7322_init_hwerrors(struct qib_devdata *dd)
2226{
2227 int pidx;
2228 u64 extsval;
2229
2230 extsval = qib_read_kreg64(dd, kr_extstatus);
2231 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
2232 QIB_EXTS_MEMBIST_ENDTEST)))
2233 qib_dev_err(dd, "MemBIST did not complete!\n");
2234
2235 /* never clear BIST failure, so reported on each driver load */
2236 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
2237 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2238
2239 /* clear all */
2240 qib_write_kreg(dd, kr_errclear, ~0ULL);
2241 /* enable errors that are masked, at least this first time. */
2242 qib_write_kreg(dd, kr_errmask, ~0ULL);
2243 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2244 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2245 if (dd->pport[pidx].link_speed_supported)
2246 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2247 ~0ULL);
2248}
2249
2250/*
2251 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
2252 * on chips that are count-based, rather than trigger-based. There is no
2253 * reference counting, but that's also fine, given the intended use.
2254 * Only chip-specific because it's all register accesses
2255 */
2256static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
2257{
2258 if (enable) {
2259 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
2260 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2261 } else
2262 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2263 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2264}
2265
2266/*
2267 * Formerly took parameter <which> in pre-shifted,
2268 * pre-merged form with LinkCmd and LinkInitCmd
2269 * together, and assuming the zero was NOP.
2270 */
2271static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
2272 u16 linitcmd)
2273{
2274 u64 mod_wd;
2275 struct qib_devdata *dd = ppd->dd;
2276 unsigned long flags;
2277
2278 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
2279 /*
2280 * If we are told to disable, note that so link-recovery
2281 * code does not attempt to bring us back up.
2282 * Also reset everything that we can, so we start
2283 * completely clean when re-enabled (before we
2284 * actually issue the disable to the IBC)
2285 */
2286 qib_7322_mini_pcs_reset(ppd);
2287 spin_lock_irqsave(&ppd->lflags_lock, flags);
2288 ppd->lflags |= QIBL_IB_LINK_DISABLED;
2289 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2290 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
2291 /*
2292 * Any other linkinitcmd will lead to LINKDOWN and then
2293 * to INIT (if all is well), so clear flag to let
2294 * link-recovery code attempt to bring us back up.
2295 */
2296 spin_lock_irqsave(&ppd->lflags_lock, flags);
2297 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
2298 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2299 /*
2300 * Clear status change interrupt reduction so the
2301 * new state is seen.
2302 */
2303 ppd->cpspec->ibcctrl_a &=
2304 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2305 }
2306
2307 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
2308 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2309
2310 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
2311 mod_wd);
2312 /* write to chip to prevent back-to-back writes of ibc reg */
2313 qib_write_kreg(dd, kr_scratch, 0);
2314
2315}
2316
2317/*
2318 * The total RCV buffer memory is 64KB, used for both ports, and is
2319 * in units of 64 bytes (same as IB flow control credit unit).
2320 * The consumedVL unit in the same registers are in 32 byte units!
2321 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
2322 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
2323 * in krp_rxcreditvl15, rather than 10.
2324 */
2325#define RCV_BUF_UNITSZ 64
2326#define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2327
2328static void set_vls(struct qib_pportdata *ppd)
2329{
2330 int i, numvls, totcred, cred_vl, vl0extra;
2331 struct qib_devdata *dd = ppd->dd;
2332 u64 val;
2333
2334 numvls = qib_num_vls(ppd->vls_operational);
2335
2336 /*
2337 * Set up per-VL credits. Below is kluge based on these assumptions:
2338 * 1) port is disabled at the time early_init is called.
2339 * 2) give VL15 17 credits, for two max-plausible packets.
2340 * 3) Give VL0-N the rest, with any rounding excess used for VL0
2341 */
2342 /* 2 VL15 packets @ 288 bytes each (including IB headers) */
2343 totcred = NUM_RCV_BUF_UNITS(dd);
2344 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
2345 totcred -= cred_vl;
2346 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
2347 cred_vl = totcred / numvls;
2348 vl0extra = totcred - cred_vl * numvls;
2349 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
2350 for (i = 1; i < numvls; i++)
2351 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
2352 for (; i < 8; i++) /* no buffer space for other VLs */
2353 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
2354
2355 /* Notify IBC that credits need to be recalculated */
2356 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2357 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2358 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2359 qib_write_kreg(dd, kr_scratch, 0ULL);
2360 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2361 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2362
2363 for (i = 0; i < numvls; i++)
2364 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2365 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2366
2367 /* Change the number of operational VLs */
2368 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
2369 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2370 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2371 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2372 qib_write_kreg(dd, kr_scratch, 0ULL);
2373}
2374
2375/*
2376 * The code that deals with actual SerDes is in serdes_7322_init().
2377 * Compared to the code for iba7220, it is minimal.
2378 */
2379static int serdes_7322_init(struct qib_pportdata *ppd);
2380
2381/**
2382 * qib_7322_bringup_serdes - bring up the serdes
2383 * @ppd: physical port on the qlogic_ib device
2384 */
2385static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
2386{
2387 struct qib_devdata *dd = ppd->dd;
2388 u64 val, guid, ibc;
2389 unsigned long flags;
2390 int ret = 0;
2391
2392 /*
2393 * SerDes model not in Pd, but still need to
2394 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
2395 * eventually.
2396 */
2397 /* Put IBC in reset, sends disabled (should be in reset already) */
2398 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2399 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2400 qib_write_kreg(dd, kr_scratch, 0ULL);
2401
2f75e12c
MM		 2402 /* ensure previous Tx parameters are not still forced */
2403 qib_write_kreg_port(ppd, krp_tx_deemph_override,
2404 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
2405 reset_tx_deemphasis_override));
2406
f931551b
RC		 2407 if (qib_compat_ddr_negotiate) {
2408 ppd->cpspec->ibdeltainprog = 1;
2409 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
2410 crp_ibsymbolerr);
2411 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
2412 crp_iblinkerrrecov);
2413 }
2414
2415 /* flowcontrolwatermark is in units of KBytes */
2416 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2417 /*
2418 * Flow control is sent this often, even if no changes in
2419 * buffer space occur. Units are 128ns for this chip.
2420 * Set to 3usec.
2421 */
2422 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2423 /* max error tolerance */
2424 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2425 /* IB credit flow control. */
2426 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2427 /*
2428 * set initial max size pkt IBC will send, including ICRC; it's the
2429 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
2430 */
2431 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
2432 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2433 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */
2434
f931551b
RC		 2435 /*
2436 * Reset the PCS interface to the serdes (and also ibc, which is still
2437 * in reset from above). Writes new value of ibcctrl_a as last step.
2438 */
2439 qib_7322_mini_pcs_reset(ppd);
f931551b
RC		 2440
2441 if (!ppd->cpspec->ibcctrl_b) {
2442 unsigned lse = ppd->link_speed_enabled;
2443
2444 /*
2445 * Not on re-init after reset, establish shadow
2446 * and force initial config.
2447 */
2448 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
2449 krp_ibcctrl_b);
2450 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
2451 IBA7322_IBC_SPEED_DDR |
2452 IBA7322_IBC_SPEED_SDR |
2453 IBA7322_IBC_WIDTH_AUTONEG |
2454 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2455 if (lse & (lse - 1)) /* Muliple speeds enabled */
2456 ppd->cpspec->ibcctrl_b |=
2457 (lse << IBA7322_IBC_SPEED_LSB) |
2458 IBA7322_IBC_IBTA_1_2_MASK |
2459 IBA7322_IBC_MAX_SPEED_MASK;
2460 else
2461 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
2462 IBA7322_IBC_SPEED_QDR |
2463 IBA7322_IBC_IBTA_1_2_MASK :
2464 (lse == QIB_IB_DDR) ?
2465 IBA7322_IBC_SPEED_DDR :
2466 IBA7322_IBC_SPEED_SDR;
2467 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
2468 (IB_WIDTH_1X | IB_WIDTH_4X))
2469 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
2470 else
2471 ppd->cpspec->ibcctrl_b |=
2472 ppd->link_width_enabled == IB_WIDTH_4X ?
2473 IBA7322_IBC_WIDTH_4X_ONLY :
2474 IBA7322_IBC_WIDTH_1X_ONLY;
2475
2476 /* always enable these on driver reload, not sticky */
2477 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
2478 IBA7322_IBC_HRTBT_MASK);
2479 }
2480 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
2481
2482 /* setup so we have more time at CFGTEST to change H1 */
2483 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2484 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2485 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2486 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2487
2488 serdes_7322_init(ppd);
2489
2490 guid = be64_to_cpu(ppd->guid);
2491 if (!guid) {
2492 if (dd->base_guid)
2493 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
2494 ppd->guid = cpu_to_be64(guid);
2495 }
2496
2497 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
2498 /* write to chip to prevent back-to-back writes of ibc reg */
2499 qib_write_kreg(dd, kr_scratch, 0);
2500
2501 /* Enable port */
2502 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2503 set_vls(ppd);
2504
8ee887d7
MM		 2505 /* initially come up DISABLED, without sending anything. */
2506 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2507 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2508 qib_write_kreg_port(ppd, krp_ibcctrl_a, val);
2509 qib_write_kreg(dd, kr_scratch, 0ULL);
2510 /* clear the linkinit cmds */
2511 ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd);
2512
f931551b
RC		 2513 /* be paranoid against later code motion, etc. */
2514 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2515 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2516 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
2517 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2518
2519 /* Also enable IBSTATUSCHG interrupt. */
2520 val = qib_read_kreg_port(ppd, krp_errmask);
2521 qib_write_kreg_port(ppd, krp_errmask,
2522 val | ERR_MASK_N(IBStatusChanged));
2523
2524 /* Always zero until we start messing with SerDes for real */
2525 return ret;
2526}
2527
2528/**
2529 * qib_7322_quiet_serdes - set serdes to txidle
2530 * @dd: the qlogic_ib device
2531 * Called when driver is being unloaded
2532 */
2533static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2534{
2535 u64 val;
2536 unsigned long flags;
2537
2538 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2539
2540 spin_lock_irqsave(&ppd->lflags_lock, flags);
2541 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
2542 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2543 wake_up(&ppd->cpspec->autoneg_wait);
f0626710 2544 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
f931551b 2545 if (ppd->dd->cspec->r1)
f0626710 2546 cancel_delayed_work_sync(&ppd->cpspec->ipg_work);
f931551b
RC		 2547
2548 ppd->cpspec->chase_end = 0;
2549 if (ppd->cpspec->chase_timer.data) /* if initted */
2550 del_timer_sync(&ppd->cpspec->chase_timer);
2551
2552 /*
2553 * Despite the name, actually disables IBC as well. Do it when
2554 * we are as sure as possible that no more packets can be
2555 * received, following the down and the PCS reset.
2556 * The actual disabling happens in qib_7322_mini_pci_reset(),
2557 * along with the PCS being reset.
2558 */
2559 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2560 qib_7322_mini_pcs_reset(ppd);
2561
2562 /*
2563 * Update the adjusted counters so the adjustment persists
2564 * across driver reload.
2565 */
2566 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
2567 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
2568 struct qib_devdata *dd = ppd->dd;
2569 u64 diagc;
2570
2571 /* enable counter writes */
2572 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
2573 qib_write_kreg(dd, kr_hwdiagctrl,
2574 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2575
2576 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
2577 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2578 if (ppd->cpspec->ibdeltainprog)
2579 val -= val - ppd->cpspec->ibsymsnap;
2580 val -= ppd->cpspec->ibsymdelta;
2581 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2582 }
2583 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
2584 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2585 if (ppd->cpspec->ibdeltainprog)
2586 val -= val - ppd->cpspec->iblnkerrsnap;
2587 val -= ppd->cpspec->iblnkerrdelta;
2588 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2589 }
2590 if (ppd->cpspec->iblnkdowndelta) {
2591 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2592 val += ppd->cpspec->iblnkdowndelta;
2593 write_7322_creg_port(ppd, crp_iblinkdown, val);
2594 }
2595 /*
2596 * No need to save ibmalfdelta since IB perfcounters
2597 * are cleared on driver reload.
2598 */
2599
2600 /* and disable counter writes */
2601 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
2602 }
2603}
2604
2605/**
2606 * qib_setup_7322_setextled - set the state of the two external LEDs
2607 * @ppd: physical port on the qlogic_ib device
2608 * @on: whether the link is up or not
2609 *
2610 * The exact combo of LEDs if on is true is determined by looking
2611 * at the ibcstatus.
2612 *
2613 * These LEDs indicate the physical and logical state of IB link.
2614 * For this chip (at least with recommended board pinouts), LED1
2615 * is Yellow (logical state) and LED2 is Green (physical state),
2616 *
2617 * Note: We try to match the Mellanox HCA LED behavior as best
2618 * we can. Green indicates physical link state is OK (something is
2619 * plugged in, and we can train).
2620 * Amber indicates the link is logically up (ACTIVE).
2621 * Mellanox further blinks the amber LED to indicate data packet
2622 * activity, but we have no hardware support for that, so it would
2623 * require waking up every 10-20 msecs and checking the counters
2624 * on the chip, and then turning the LED off if appropriate. That's
2625 * visible overhead, so not something we will do.
2626 */
2627static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
2628{
2629 struct qib_devdata *dd = ppd->dd;
2630 u64 extctl, ledblink = 0, val;
2631 unsigned long flags;
2632 int yel, grn;
2633
2634 /*
2635 * The diags use the LED to indicate diag info, so we leave
2636 * the external LED alone when the diags are running.
2637 */
2638 if (dd->diag_client)
2639 return;
2640
2641 /* Allow override of LED display for, e.g. Locating system in rack */
2642 if (ppd->led_override) {
2643 grn = (ppd->led_override & QIB_LED_PHYS);
2644 yel = (ppd->led_override & QIB_LED_LOG);
2645 } else if (on) {
2646 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2647 grn = qib_7322_phys_portstate(val) ==
2648 IB_PHYSPORTSTATE_LINKUP;
2649 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
2650 } else {
2651 grn = 0;
2652 yel = 0;
2653 }
2654
2655 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2656 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2657 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
2658 if (grn) {
2659 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
2660 /*
2661 * Counts are in chip clock (4ns) periods.
2662 * This is 1/16 sec (66.6ms) on,
2663 * 3/16 sec (187.5 ms) off, with packets rcvd.
2664 */
2665 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
2666 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
2667 }
2668 if (yel)
2669 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
2670 dd->cspec->extctrl = extctl;
2671 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2672 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2673
2674 if (ledblink) /* blink the LED on packet receive */
2675 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
2676}
2677
8469ba39
MM		 2678#ifdef CONFIG_INFINIBAND_QIB_DCA
2679
2680static int qib_7322_notify_dca(struct qib_devdata *dd, unsigned long event)
2681{
2682 switch (event) {
2683 case DCA_PROVIDER_ADD:
2684 if (dd->flags & QIB_DCA_ENABLED)
2685 break;
2686 if (!dca_add_requester(&dd->pcidev->dev)) {
2687 qib_devinfo(dd->pcidev, "DCA enabled\n");
2688 dd->flags |= QIB_DCA_ENABLED;
2689 qib_setup_dca(dd);
2690 }
2691 break;
2692 case DCA_PROVIDER_REMOVE:
2693 if (dd->flags & QIB_DCA_ENABLED) {
2694 dca_remove_requester(&dd->pcidev->dev);
2695 dd->flags &= ~QIB_DCA_ENABLED;
2696 dd->cspec->dca_ctrl = 0;
2697 qib_write_kreg(dd, KREG_IDX(DCACtrlA),
2698 dd->cspec->dca_ctrl);
2699 }
2700 break;
2701 }
2702 return 0;
2703}
2704
2705static void qib_update_rhdrq_dca(struct qib_ctxtdata *rcd, int cpu)
2706{
2707 struct qib_devdata *dd = rcd->dd;
2708 struct qib_chip_specific *cspec = dd->cspec;
2709
2710 if (!(dd->flags & QIB_DCA_ENABLED))
2711 return;
2712 if (cspec->rhdr_cpu[rcd->ctxt] != cpu) {
2713 const struct dca_reg_map *rmp;
2714
2715 cspec->rhdr_cpu[rcd->ctxt] = cpu;
2716 rmp = &dca_rcvhdr_reg_map[rcd->ctxt];
2717 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask;
2718 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |=
2719 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << rmp->lsb;
2720 qib_devinfo(dd->pcidev,
2721 "Ctxt %d cpu %d dca %llx\n", rcd->ctxt, cpu,
2722 (long long) cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
2723 qib_write_kreg(dd, rmp->regno,
2724 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
2725 cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable);
2726 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
2727 }
2728}
2729
2730static void qib_update_sdma_dca(struct qib_pportdata *ppd, int cpu)
2731{
2732 struct qib_devdata *dd = ppd->dd;
2733 struct qib_chip_specific *cspec = dd->cspec;
2734 unsigned pidx = ppd->port - 1;
2735
2736 if (!(dd->flags & QIB_DCA_ENABLED))
2737 return;
2738 if (cspec->sdma_cpu[pidx] != cpu) {
2739 cspec->sdma_cpu[pidx] = cpu;
2740 cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ?
2741 SYM_MASK(DCACtrlF, SendDma1DCAOPH) :
2742 SYM_MASK(DCACtrlF, SendDma0DCAOPH));
2743 cspec->dca_rcvhdr_ctrl[4] |=
2744 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) <<
2745 (ppd->hw_pidx ?
2746 SYM_LSB(DCACtrlF, SendDma1DCAOPH) :
2747 SYM_LSB(DCACtrlF, SendDma0DCAOPH));
2748 qib_devinfo(dd->pcidev,
2749 "sdma %d cpu %d dca %llx\n", ppd->hw_pidx, cpu,
2750 (long long) cspec->dca_rcvhdr_ctrl[4]);
2751 qib_write_kreg(dd, KREG_IDX(DCACtrlF),
2752 cspec->dca_rcvhdr_ctrl[4]);
2753 cspec->dca_ctrl |= ppd->hw_pidx ?
2754 SYM_MASK(DCACtrlA, SendDMAHead1DCAEnable) :
2755 SYM_MASK(DCACtrlA, SendDMAHead0DCAEnable);
2756 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
2757 }
2758}
2759
2760static void qib_setup_dca(struct qib_devdata *dd)
2761{
2762 struct qib_chip_specific *cspec = dd->cspec;
2763 int i;
2764
2765 for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++)
2766 cspec->rhdr_cpu[i] = -1;
2767 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
2768 cspec->sdma_cpu[i] = -1;
2769 cspec->dca_rcvhdr_ctrl[0] =
2770 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq0DCAXfrCnt)) |
2771 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq1DCAXfrCnt)) |
2772 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq2DCAXfrCnt)) |
2773 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq3DCAXfrCnt));
2774 cspec->dca_rcvhdr_ctrl[1] =
2775 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq4DCAXfrCnt)) |
2776 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq5DCAXfrCnt)) |
2777 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq6DCAXfrCnt)) |
2778 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq7DCAXfrCnt));
2779 cspec->dca_rcvhdr_ctrl[2] =
2780 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq8DCAXfrCnt)) |
2781 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq9DCAXfrCnt)) |
2782 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq10DCAXfrCnt)) |
2783 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq11DCAXfrCnt));
2784 cspec->dca_rcvhdr_ctrl[3] =
2785 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq12DCAXfrCnt)) |
2786 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq13DCAXfrCnt)) |
2787 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq14DCAXfrCnt)) |
2788 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq15DCAXfrCnt));
2789 cspec->dca_rcvhdr_ctrl[4] =
2790 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq16DCAXfrCnt)) |
2791 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq17DCAXfrCnt));
2792 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
2793 qib_write_kreg(dd, KREG_IDX(DCACtrlB) + i,
2794 cspec->dca_rcvhdr_ctrl[i]);
2795 for (i = 0; i < cspec->num_msix_entries; i++)
2796 setup_dca_notifier(dd, &cspec->msix_entries[i]);
2797}
2798
2799static void qib_irq_notifier_notify(struct irq_affinity_notify *notify,
2800 const cpumask_t *mask)
2801{
2802 struct qib_irq_notify *n =
2803 container_of(notify, struct qib_irq_notify, notify);
2804 int cpu = cpumask_first(mask);
2805
2806 if (n->rcv) {
2807 struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg;
da12c1f6 2808
8469ba39
MM		 2809 qib_update_rhdrq_dca(rcd, cpu);
2810 } else {
2811 struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg;
da12c1f6 2812
8469ba39
MM		 2813 qib_update_sdma_dca(ppd, cpu);
2814 }
2815}
2816
2817static void qib_irq_notifier_release(struct kref *ref)
2818{
2819 struct qib_irq_notify *n =
2820 container_of(ref, struct qib_irq_notify, notify.kref);
2821 struct qib_devdata *dd;
2822
2823 if (n->rcv) {
2824 struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg;
da12c1f6 2825
8469ba39
MM		 2826 dd = rcd->dd;
2827 } else {
2828 struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg;
da12c1f6 2829
8469ba39
MM		 2830 dd = ppd->dd;
2831 }
2832 qib_devinfo(dd->pcidev,
2833 "release on HCA notify 0x%p n 0x%p\n", ref, n);
2834 kfree(n);
2835}
2836#endif
2837
f931551b
RC		 2838/*
2839 * Disable MSIx interrupt if enabled, call generic MSIx code
2840 * to cleanup, and clear pending MSIx interrupts.
2841 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2842 */
2843static void qib_7322_nomsix(struct qib_devdata *dd)
2844{
2845 u64 intgranted;
2846 int n;
2847
2848 dd->cspec->main_int_mask = ~0ULL;
2849 n = dd->cspec->num_msix_entries;
2850 if (n) {
2851 int i;
2852
2853 dd->cspec->num_msix_entries = 0;
a778f3fd 2854 for (i = 0; i < n; i++) {
8469ba39
MM		 2855#ifdef CONFIG_INFINIBAND_QIB_DCA
2856 reset_dca_notifier(dd, &dd->cspec->msix_entries[i]);
2857#endif
a778f3fd
MM		 2858 irq_set_affinity_hint(
2859 dd->cspec->msix_entries[i].msix.vector, NULL);
2860 free_cpumask_var(dd->cspec->msix_entries[i].mask);
2861 free_irq(dd->cspec->msix_entries[i].msix.vector,
2862 dd->cspec->msix_entries[i].arg);
2863 }
f931551b
RC		 2864 qib_nomsix(dd);
2865 }
2866 /* make sure no MSIx interrupts are left pending */
2867 intgranted = qib_read_kreg64(dd, kr_intgranted);
2868 if (intgranted)
2869 qib_write_kreg(dd, kr_intgranted, intgranted);
2870}
2871
2872static void qib_7322_free_irq(struct qib_devdata *dd)
2873{
2874 if (dd->cspec->irq) {
2875 free_irq(dd->cspec->irq, dd);
2876 dd->cspec->irq = 0;
2877 }
2878 qib_7322_nomsix(dd);
2879}
2880
2881static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2882{
2883 int i;
2884
8469ba39
MM		 2885#ifdef CONFIG_INFINIBAND_QIB_DCA
2886 if (dd->flags & QIB_DCA_ENABLED) {
2887 dca_remove_requester(&dd->pcidev->dev);
2888 dd->flags &= ~QIB_DCA_ENABLED;
2889 dd->cspec->dca_ctrl = 0;
2890 qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl);
2891 }
2892#endif
2893
f931551b
RC		 2894 qib_7322_free_irq(dd);
2895 kfree(dd->cspec->cntrs);
2896 kfree(dd->cspec->sendchkenable);
2897 kfree(dd->cspec->sendgrhchk);
2898 kfree(dd->cspec->sendibchk);
2899 kfree(dd->cspec->msix_entries);
f931551b
RC		 2900 for (i = 0; i < dd->num_pports; i++) {
2901 unsigned long flags;
2902 u32 mask = QSFP_GPIO_MOD_PRS_N |
2903 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);
2904
2905 kfree(dd->pport[i].cpspec->portcntrs);
2906 if (dd->flags & QIB_HAS_QSFP) {
2907 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2908 dd->cspec->gpio_mask &= ~mask;
2909 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2910 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2911 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data);
2912 }
f931551b
RC		 2913 }
2914}
2915
2916/* handle SDMA interrupts */
2917static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
2918{
2919 struct qib_pportdata *ppd0 = &dd->pport[0];
2920 struct qib_pportdata *ppd1 = &dd->pport[1];
2921 u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
2922 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
2923 u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
2924 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));
2925
2926 if (intr0)
2927 qib_sdma_intr(ppd0);
2928 if (intr1)
2929 qib_sdma_intr(ppd1);
2930
2931 if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
2932 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
2933 if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
2934 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
2935}
2936
2937/*
2938 * Set or clear the Send buffer available interrupt enable bit.
2939 */
2940static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
2941{
2942 unsigned long flags;
2943
2944 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2945 if (needint)
2946 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2947 else
2948 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
2949 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2950 qib_write_kreg(dd, kr_scratch, 0ULL);
2951 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2952}
2953
2954/*
2955 * Somehow got an interrupt with reserved bits set in interrupt status.
2956 * Print a message so we know it happened, then clear them.
2957 * keep mainline interrupt handler cache-friendly
2958 */
2959static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
2960{
2961 u64 kills;
2962 char msg[128];
2963
2964 kills = istat & ~QIB_I_BITSEXTANT;
7fac3301
MM		 2965 qib_dev_err(dd,
2966 "Clearing reserved interrupt(s) 0x%016llx: %s\n",
2967 (unsigned long long) kills, msg);
f931551b
RC		 2968 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2969}
2970
2971/* keep mainline interrupt handler cache-friendly */
2972static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
2973{
2974 u32 gpiostatus;
2975 int handled = 0;
2976 int pidx;
2977
2978 /*
2979 * Boards for this chip currently don't use GPIO interrupts,
2980 * so clear by writing GPIOstatus to GPIOclear, and complain
2981 * to developer. To avoid endless repeats, clear
2982 * the bits in the mask, since there is some kind of
2983 * programming error or chip problem.
2984 */
2985 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
2986 /*
2987 * In theory, writing GPIOstatus to GPIOclear could
2988 * have a bad side-effect on some diagnostic that wanted
2989 * to poll for a status-change, but the various shadows
2990 * make that problematic at best. Diags will just suppress
2991 * all GPIO interrupts during such tests.
2992 */
2993 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
2994 /*
2995 * Check for QSFP MOD_PRS changes
2996 * only works for single port if IB1 != pidx1
2997 */
2998 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
2999 ++pidx) {
3000 struct qib_pportdata *ppd;
3001 struct qib_qsfp_data *qd;
3002 u32 mask;
da12c1f6 3003
f931551b
RC		 3004 if (!dd->pport[pidx].link_speed_supported)
3005 continue;
3006 mask = QSFP_GPIO_MOD_PRS_N;
3007 ppd = dd->pport + pidx;
3008 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
3009 if (gpiostatus & dd->cspec->gpio_mask & mask) {
3010 u64 pins;
da12c1f6 3011
f931551b
RC		 3012 qd = &ppd->cpspec->qsfp_data;
3013 gpiostatus &= ~mask;
3014 pins = qib_read_kreg64(dd, kr_extstatus);
3015 pins >>= SYM_LSB(EXTStatus, GPIOIn);
3016 if (!(pins & mask)) {
3017 ++handled;
8482d5d1 3018 qd->t_insert = jiffies;
f0626710 3019 queue_work(ib_wq, &qd->work);
f931551b
RC		 3020 }
3021 }
3022 }
3023
3024 if (gpiostatus && !handled) {
3025 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
3026 u32 gpio_irq = mask & gpiostatus;
3027
3028 /*
3029 * Clear any troublemakers, and update chip from shadow
3030 */
3031 dd->cspec->gpio_mask &= ~gpio_irq;
3032 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
3033 }
3034}
3035
3036/*
3037 * Handle errors and unusual events first, separate function
3038 * to improve cache hits for fast path interrupt handling.
3039 */
3040static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat)
3041{
3042 if (istat & ~QIB_I_BITSEXTANT)
3043 unknown_7322_ibits(dd, istat);
3044 if (istat & QIB_I_GPIO)
3045 unknown_7322_gpio_intr(dd);
e67306a3
MM		 3046 if (istat & QIB_I_C_ERROR) {
3047 qib_write_kreg(dd, kr_errmask, 0ULL);
3048 tasklet_schedule(&dd->error_tasklet);
3049 }
f931551b
RC		 3050 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0])
3051 handle_7322_p_errors(dd->rcd[0]->ppd);
3052 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1])
3053 handle_7322_p_errors(dd->rcd[1]->ppd);
3054}
3055
3056/*
3057 * Dynamically adjust the rcv int timeout for a context based on incoming
3058 * packet rate.
3059 */
3060static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts)
3061{
3062 struct qib_devdata *dd = rcd->dd;
3063 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
3064
3065 /*
3066 * Dynamically adjust idle timeout on chip
3067 * based on number of packets processed.
3068 */
3069 if (npkts < rcv_int_count && timeout > 2)
3070 timeout >>= 1;
3071 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout)
3072 timeout = min(timeout << 1, rcv_int_timeout);
3073 else
3074 return;
3075
3076 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
3077 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);
3078}
3079
3080/*
3081 * This is the main interrupt handler.
3082 * It will normally only be used for low frequency interrupts but may
3083 * have to handle all interrupts if INTx is enabled or fewer than normal
3084 * MSIx interrupts were allocated.
3085 * This routine should ignore the interrupt bits for any of the
3086 * dedicated MSIx handlers.
3087 */
3088static irqreturn_t qib_7322intr(int irq, void *data)
3089{
3090 struct qib_devdata *dd = data;
3091 irqreturn_t ret;
3092 u64 istat;
3093 u64 ctxtrbits;
3094 u64 rmask;
3095 unsigned i;
3096 u32 npkts;
3097
3098 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
3099 /*
3100 * This return value is not great, but we do not want the
3101 * interrupt core code to remove our interrupt handler
3102 * because we don't appear to be handling an interrupt
3103 * during a chip reset.
3104 */
3105 ret = IRQ_HANDLED;
3106 goto bail;
3107 }
3108
3109 istat = qib_read_kreg64(dd, kr_intstatus);
3110
3111 if (unlikely(istat == ~0ULL)) {
3112 qib_bad_intrstatus(dd);
3113 qib_dev_err(dd, "Interrupt status all f's, skipping\n");
3114 /* don't know if it was our interrupt or not */
3115 ret = IRQ_NONE;
3116 goto bail;
3117 }
3118
3119 istat &= dd->cspec->main_int_mask;
3120 if (unlikely(!istat)) {
3121 /* already handled, or shared and not us */
3122 ret = IRQ_NONE;
3123 goto bail;
3124 }
3125
1ed88dd7 3126 this_cpu_inc(*dd->int_counter);
f931551b
RC		 3127
3128 /* handle "errors" of various kinds first, device ahead of port */
3129 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO |
3130 QIB_I_C_ERROR | INT_MASK_P(Err, 0) |
3131 INT_MASK_P(Err, 1))))
3132 unlikely_7322_intr(dd, istat);
3133
3134 /*
3135 * Clear the interrupt bits we found set, relatively early, so we
3136 * "know" know the chip will have seen this by the time we process
3137 * the queue, and will re-interrupt if necessary. The processor
3138 * itself won't take the interrupt again until we return.
3139 */
3140 qib_write_kreg(dd, kr_intclear, istat);
3141
3142 /*
3143 * Handle kernel receive queues before checking for pio buffers
3144 * available since receives can overflow; piobuf waiters can afford
3145 * a few extra cycles, since they were waiting anyway.
3146 */
3147 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK);
3148 if (ctxtrbits) {
3149 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) |
3150 (1ULL << QIB_I_RCVURG_LSB);
3151 for (i = 0; i < dd->first_user_ctxt; i++) {
3152 if (ctxtrbits & rmask) {
3153 ctxtrbits &= ~rmask;
44d75d3d 3154 if (dd->rcd[i])
f931551b 3155 qib_kreceive(dd->rcd[i], NULL, &npkts);
f931551b
RC		 3156 }
3157 rmask <<= 1;
3158 }
3159 if (ctxtrbits) {
3160 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) |
3161 (ctxtrbits >> QIB_I_RCVURG_LSB);
3162 qib_handle_urcv(dd, ctxtrbits);
3163 }
3164 }
3165
3166 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
3167 sdma_7322_intr(dd, istat);
3168
3169 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
3170 qib_ib_piobufavail(dd);
3171
3172 ret = IRQ_HANDLED;
3173bail:
3174 return ret;
3175}
3176
3177/*
3178 * Dedicated receive packet available interrupt handler.
3179 */
3180static irqreturn_t qib_7322pintr(int irq, void *data)
3181{
3182 struct qib_ctxtdata *rcd = data;
3183 struct qib_devdata *dd = rcd->dd;
3184 u32 npkts;
3185
3186 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3187 /*
3188 * This return value is not great, but we do not want the
3189 * interrupt core code to remove our interrupt handler
3190 * because we don't appear to be handling an interrupt
3191 * during a chip reset.
3192 */
3193 return IRQ_HANDLED;
3194
1ed88dd7 3195 this_cpu_inc(*dd->int_counter);
f931551b 3196
f931551b
RC		 3197 /* Clear the interrupt bit we expect to be set. */
3198 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) |
3199 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
3200
3201 qib_kreceive(rcd, NULL, &npkts);
f931551b
RC		 3202
3203 return IRQ_HANDLED;
3204}
3205
3206/*
3207 * Dedicated Send buffer available interrupt handler.
3208 */
3209static irqreturn_t qib_7322bufavail(int irq, void *data)
3210{
3211 struct qib_devdata *dd = data;
3212
3213 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3214 /*
3215 * This return value is not great, but we do not want the
3216 * interrupt core code to remove our interrupt handler
3217 * because we don't appear to be handling an interrupt
3218 * during a chip reset.
3219 */
3220 return IRQ_HANDLED;
3221
1ed88dd7 3222 this_cpu_inc(*dd->int_counter);
f931551b
RC		 3223
3224 /* Clear the interrupt bit we expect to be set. */
3225 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL);
3226
3227 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */
3228 if (dd->flags & QIB_INITTED)
3229 qib_ib_piobufavail(dd);
3230 else
3231 qib_wantpiobuf_7322_intr(dd, 0);
3232
3233 return IRQ_HANDLED;
3234}
3235
3236/*
3237 * Dedicated Send DMA interrupt handler.
3238 */
3239static irqreturn_t sdma_intr(int irq, void *data)
3240{
3241 struct qib_pportdata *ppd = data;
3242 struct qib_devdata *dd = ppd->dd;
3243
3244 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3245 /*
3246 * This return value is not great, but we do not want the
3247 * interrupt core code to remove our interrupt handler
3248 * because we don't appear to be handling an interrupt
3249 * during a chip reset.
3250 */
3251 return IRQ_HANDLED;
3252
1ed88dd7 3253 this_cpu_inc(*dd->int_counter);
f931551b 3254
f931551b
RC		 3255 /* Clear the interrupt bit we expect to be set. */
3256 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3257 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0));
3258 qib_sdma_intr(ppd);
3259
3260 return IRQ_HANDLED;
3261}
3262
3263/*
3264 * Dedicated Send DMA idle interrupt handler.
3265 */
3266static irqreturn_t sdma_idle_intr(int irq, void *data)
3267{
3268 struct qib_pportdata *ppd = data;
3269 struct qib_devdata *dd = ppd->dd;
3270
3271 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3272 /*
3273 * This return value is not great, but we do not want the
3274 * interrupt core code to remove our interrupt handler
3275 * because we don't appear to be handling an interrupt
3276 * during a chip reset.
3277 */
3278 return IRQ_HANDLED;
3279
1ed88dd7 3280 this_cpu_inc(*dd->int_counter);
f931551b 3281
f931551b
RC		 3282 /* Clear the interrupt bit we expect to be set. */
3283 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3284 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0));
3285 qib_sdma_intr(ppd);
3286
3287 return IRQ_HANDLED;
3288}
3289
3290/*
3291 * Dedicated Send DMA progress interrupt handler.
3292 */
3293static irqreturn_t sdma_progress_intr(int irq, void *data)
3294{
3295 struct qib_pportdata *ppd = data;
3296 struct qib_devdata *dd = ppd->dd;
3297
3298 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3299 /*
3300 * This return value is not great, but we do not want the
3301 * interrupt core code to remove our interrupt handler
3302 * because we don't appear to be handling an interrupt
3303 * during a chip reset.
3304 */
3305 return IRQ_HANDLED;
3306
1ed88dd7 3307 this_cpu_inc(*dd->int_counter);
f931551b 3308
f931551b
RC		 3309 /* Clear the interrupt bit we expect to be set. */
3310 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3311 INT_MASK_P(SDmaProgress, 1) :
3312 INT_MASK_P(SDmaProgress, 0));
3313 qib_sdma_intr(ppd);
3314
3315 return IRQ_HANDLED;
3316}
3317
3318/*
3319 * Dedicated Send DMA cleanup interrupt handler.
3320 */
3321static irqreturn_t sdma_cleanup_intr(int irq, void *data)
3322{
3323 struct qib_pportdata *ppd = data;
3324 struct qib_devdata *dd = ppd->dd;
3325
3326 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3327 /*
3328 * This return value is not great, but we do not want the
3329 * interrupt core code to remove our interrupt handler
3330 * because we don't appear to be handling an interrupt
3331 * during a chip reset.
3332 */
3333 return IRQ_HANDLED;
3334
1ed88dd7 3335 this_cpu_inc(*dd->int_counter);
f931551b 3336
f931551b
RC		 3337 /* Clear the interrupt bit we expect to be set. */
3338 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3339 INT_MASK_PM(SDmaCleanupDone, 1) :
3340 INT_MASK_PM(SDmaCleanupDone, 0));
3341 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
3342
3343 return IRQ_HANDLED;
3344}
3345
8469ba39
MM		 3346#ifdef CONFIG_INFINIBAND_QIB_DCA
3347
3348static void reset_dca_notifier(struct qib_devdata *dd, struct qib_msix_entry *m)
3349{
3350 if (!m->dca)
3351 return;
3352 qib_devinfo(dd->pcidev,
3353 "Disabling notifier on HCA %d irq %d\n",
3354 dd->unit,
3355 m->msix.vector);
3356 irq_set_affinity_notifier(
3357 m->msix.vector,
3358 NULL);
3359 m->notifier = NULL;
3360}
3361
3362static void setup_dca_notifier(struct qib_devdata *dd, struct qib_msix_entry *m)
3363{
3364 struct qib_irq_notify *n;
3365
3366 if (!m->dca)
3367 return;
3368 n = kzalloc(sizeof(*n), GFP_KERNEL);
3369 if (n) {
3370 int ret;
3371
3372 m->notifier = n;
3373 n->notify.irq = m->msix.vector;
3374 n->notify.notify = qib_irq_notifier_notify;
3375 n->notify.release = qib_irq_notifier_release;
3376 n->arg = m->arg;
3377 n->rcv = m->rcv;
3378 qib_devinfo(dd->pcidev,
3379 "set notifier irq %d rcv %d notify %p\n",
3380 n->notify.irq, n->rcv, &n->notify);
3381 ret = irq_set_affinity_notifier(
3382 n->notify.irq,
3383 &n->notify);
3384 if (ret) {
3385 m->notifier = NULL;
3386 kfree(n);
3387 }
3388 }
3389}
3390
3391#endif
3392
f931551b
RC		 3393/*
3394 * Set up our chip-specific interrupt handler.
3395 * The interrupt type has already been setup, so
3396 * we just need to do the registration and error checking.
3397 * If we are using MSIx interrupts, we may fall back to
3398 * INTx later, if the interrupt handler doesn't get called
3399 * within 1/2 second (see verify_interrupt()).
3400 */
3401static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3402{
3403 int ret, i, msixnum;
3404 u64 redirect[6];
3405 u64 mask;
a778f3fd
MM		 3406 const struct cpumask *local_mask;
3407 int firstcpu, secondcpu = 0, currrcvcpu = 0;
f931551b
RC		 3408
3409 if (!dd->num_pports)
3410 return;
3411
3412 if (clearpend) {
3413 /*
3414 * if not switching interrupt types, be sure interrupts are
3415 * disabled, and then clear anything pending at this point,
3416 * because we are starting clean.
3417 */
3418 qib_7322_set_intr_state(dd, 0);
3419
3420 /* clear the reset error, init error/hwerror mask */
3421 qib_7322_init_hwerrors(dd);
3422
3423 /* clear any interrupt bits that might be set */
3424 qib_write_kreg(dd, kr_intclear, ~0ULL);
3425
3426 /* make sure no pending MSIx intr, and clear diag reg */
3427 qib_write_kreg(dd, kr_intgranted, ~0ULL);
3428 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL);
3429 }
3430
3431 if (!dd->cspec->num_msix_entries) {
3432 /* Try to get INTx interrupt */
3433try_intx:
3434 if (!dd->pcidev->irq) {
7fac3301
MM		 3435 qib_dev_err(dd,
3436 "irq is 0, BIOS error? Interrupts won't work\n");
f931551b
RC		 3437 goto bail;
3438 }
3439 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3440 IRQF_SHARED, QIB_DRV_NAME, dd);
3441 if (ret) {
7fac3301
MM		 3442 qib_dev_err(dd,
3443 "Couldn't setup INTx interrupt (irq=%d): %d\n",
3444 dd->pcidev->irq, ret);
f931551b
RC		 3445 goto bail;
3446 }
3447 dd->cspec->irq = dd->pcidev->irq;
3448 dd->cspec->main_int_mask = ~0ULL;
3449 goto bail;
3450 }
3451
3452 /* Try to get MSIx interrupts */
041af0bb 3453 memset(redirect, 0, sizeof(redirect));
f931551b
RC		 3454 mask = ~0ULL;
3455 msixnum = 0;
a778f3fd
MM		 3456 local_mask = cpumask_of_pcibus(dd->pcidev->bus);
3457 firstcpu = cpumask_first(local_mask);
3458 if (firstcpu >= nr_cpu_ids ||
3459 cpumask_weight(local_mask) == num_online_cpus()) {
3460 local_mask = topology_core_cpumask(0);
3461 firstcpu = cpumask_first(local_mask);
3462 }
3463 if (firstcpu < nr_cpu_ids) {
3464 secondcpu = cpumask_next(firstcpu, local_mask);
3465 if (secondcpu >= nr_cpu_ids)
3466 secondcpu = firstcpu;
3467 currrcvcpu = secondcpu;
3468 }
f931551b
RC		 3469 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3470 irq_handler_t handler;
f931551b
RC		 3471 void *arg;
3472 u64 val;
3473 int lsb, reg, sh;
8469ba39
MM		 3474#ifdef CONFIG_INFINIBAND_QIB_DCA
3475 int dca = 0;
3476#endif
f931551b 3477
a778f3fd
MM		 3478 dd->cspec->msix_entries[msixnum].
3479 name[sizeof(dd->cspec->msix_entries[msixnum].name) - 1]
3480 = '\0';
f931551b
RC		 3481 if (i < ARRAY_SIZE(irq_table)) {
3482 if (irq_table[i].port) {
3483 /* skip if for a non-configured port */
3484 if (irq_table[i].port > dd->num_pports)
3485 continue;
3486 arg = dd->pport + irq_table[i].port - 1;
3487 } else
3488 arg = dd;
8469ba39
MM		 3489#ifdef CONFIG_INFINIBAND_QIB_DCA
3490 dca = irq_table[i].dca;
3491#endif
f931551b
RC		 3492 lsb = irq_table[i].lsb;
3493 handler = irq_table[i].handler;
a778f3fd
MM		 3494 snprintf(dd->cspec->msix_entries[msixnum].name,
3495 sizeof(dd->cspec->msix_entries[msixnum].name)
3496 - 1,
3497 QIB_DRV_NAME "%d%s", dd->unit,
3498 irq_table[i].name);
f931551b
RC		 3499 } else {
3500 unsigned ctxt;
3501
3502 ctxt = i - ARRAY_SIZE(irq_table);
3503 /* per krcvq context receive interrupt */
3504 arg = dd->rcd[ctxt];
3505 if (!arg)
3506 continue;
e67306a3
MM		 3507 if (qib_krcvq01_no_msi && ctxt < 2)
3508 continue;
8469ba39
MM		 3509#ifdef CONFIG_INFINIBAND_QIB_DCA
3510 dca = 1;
3511#endif
f931551b
RC		 3512 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3513 handler = qib_7322pintr;
a778f3fd
MM		 3514 snprintf(dd->cspec->msix_entries[msixnum].name,
3515 sizeof(dd->cspec->msix_entries[msixnum].name)
3516 - 1,
3517 QIB_DRV_NAME "%d (kctx)", dd->unit);
f931551b 3518 }
a778f3fd
MM		 3519 ret = request_irq(
3520 dd->cspec->msix_entries[msixnum].msix.vector,
3521 handler, 0, dd->cspec->msix_entries[msixnum].name,
3522 arg);
f931551b
RC		 3523 if (ret) {
3524 /*
3525 * Shouldn't happen since the enable said we could
3526 * have as many as we are trying to setup here.
3527 */
7fac3301
MM		 3528 qib_dev_err(dd,
3529 "Couldn't setup MSIx interrupt (vec=%d, irq=%d): %d\n",
3530 msixnum,
a778f3fd
MM		 3531 dd->cspec->msix_entries[msixnum].msix.vector,
3532 ret);
f931551b
RC		 3533 qib_7322_nomsix(dd);
3534 goto try_intx;
3535 }
a778f3fd 3536 dd->cspec->msix_entries[msixnum].arg = arg;
8469ba39
MM		 3537#ifdef CONFIG_INFINIBAND_QIB_DCA
3538 dd->cspec->msix_entries[msixnum].dca = dca;
3539 dd->cspec->msix_entries[msixnum].rcv =
3540 handler == qib_7322pintr;
3541#endif
f931551b
RC		 3542 if (lsb >= 0) {
3543 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG;
3544 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) *
3545 SYM_LSB(IntRedirect0, vec1);
3546 mask &= ~(1ULL << lsb);
3547 redirect[reg] |= ((u64) msixnum) << sh;
3548 }
3549 val = qib_read_kreg64(dd, 2 * msixnum + 1 +
3550 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
a778f3fd
MM		 3551 if (firstcpu < nr_cpu_ids &&
3552 zalloc_cpumask_var(
3553 &dd->cspec->msix_entries[msixnum].mask,
3554 GFP_KERNEL)) {
3555 if (handler == qib_7322pintr) {
3556 cpumask_set_cpu(currrcvcpu,
3557 dd->cspec->msix_entries[msixnum].mask);
3558 currrcvcpu = cpumask_next(currrcvcpu,
3559 local_mask);
3560 if (currrcvcpu >= nr_cpu_ids)
3561 currrcvcpu = secondcpu;
3562 } else {
3563 cpumask_set_cpu(firstcpu,
3564 dd->cspec->msix_entries[msixnum].mask);
3565 }
3566 irq_set_affinity_hint(
3567 dd->cspec->msix_entries[msixnum].msix.vector,
3568 dd->cspec->msix_entries[msixnum].mask);
3569 }
f931551b
RC		 3570 msixnum++;
3571 }
3572 /* Initialize the vector mapping */
3573 for (i = 0; i < ARRAY_SIZE(redirect); i++)
3574 qib_write_kreg(dd, kr_intredirect + i, redirect[i]);
3575 dd->cspec->main_int_mask = mask;
e67306a3
MM		 3576 tasklet_init(&dd->error_tasklet, qib_error_tasklet,
3577 (unsigned long)dd);
f931551b
RC		 3578bail:;
3579}
3580
3581/**
3582 * qib_7322_boardname - fill in the board name and note features
3583 * @dd: the qlogic_ib device
3584 *
3585 * info will be based on the board revision register
3586 */
3587static unsigned qib_7322_boardname(struct qib_devdata *dd)
3588{
3589 /* Will need enumeration of board-types here */
3590 char *n;
3591 u32 boardid, namelen;
3592 unsigned features = DUAL_PORT_CAP;
3593
3594 boardid = SYM_FIELD(dd->revision, Revision, BoardID);
3595
3596 switch (boardid) {
3597 case 0:
3598 n = "InfiniPath_QLE7342_Emulation";
3599 break;
3600 case 1:
3601 n = "InfiniPath_QLE7340";
3602 dd->flags |= QIB_HAS_QSFP;
3603 features = PORT_SPD_CAP;
3604 break;
3605 case 2:
3606 n = "InfiniPath_QLE7342";
3607 dd->flags |= QIB_HAS_QSFP;
3608 break;
3609 case 3:
3610 n = "InfiniPath_QMI7342";
3611 break;
3612 case 4:
3613 n = "InfiniPath_Unsupported7342";
3614 qib_dev_err(dd, "Unsupported version of QMH7342\n");
3615 features = 0;
3616 break;
3617 case BOARD_QMH7342:
3618 n = "InfiniPath_QMH7342";
3619 features = 0x24;
3620 break;
3621 case BOARD_QME7342:
3622 n = "InfiniPath_QME7342";
3623 break;
f509f9c1
MM		 3624 case 8:
3625 n = "InfiniPath_QME7362";
3626 dd->flags |= QIB_HAS_QSFP;
3627 break;
0e6bbba5
VA		 3628 case BOARD_QMH7360:
3629 n = "Intel IB QDR 1P FLR-QSFP Adptr";
3630 dd->flags |= QIB_HAS_QSFP;
3631 break;
f931551b
RC		 3632 case 15:
3633 n = "InfiniPath_QLE7342_TEST";
3634 dd->flags |= QIB_HAS_QSFP;
3635 break;
3636 default:
3637 n = "InfiniPath_QLE73xy_UNKNOWN";
3638 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid);
3639 break;
3640 }
3641 dd->board_atten = 1; /* index into txdds_Xdr */
3642
3643 namelen = strlen(n) + 1;
3644 dd->boardname = kmalloc(namelen, GFP_KERNEL);
3645 if (!dd->boardname)
3646 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
3647 else
3648 snprintf(dd->boardname, namelen, "%s", n);
3649
3650 snprintf(dd->boardversion, sizeof(dd->boardversion),
3651 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3652 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
3653 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
3654 dd->majrev, dd->minrev,
3655 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
3656
3657 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) {
7fac3301
MM		 3658 qib_devinfo(dd->pcidev,
3659 "IB%u: Forced to single port mode by module parameter\n",
3660 dd->unit);
f931551b
RC		 3661 features &= PORT_SPD_CAP;
3662 }
3663
3664 return features;
3665}
3666
3667/*
3668 * This routine sleeps, so it can only be called from user context, not
3669 * from interrupt context.
3670 */
3671static int qib_do_7322_reset(struct qib_devdata *dd)
3672{
3673 u64 val;
3674 u64 *msix_vecsave;
3675 int i, msix_entries, ret = 1;
3676 u16 cmdval;
3677 u8 int_line, clinesz;
3678 unsigned long flags;
3679
3680 /* Use dev_err so it shows up in logs, etc. */
3681 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
3682
3683 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
3684
3685 msix_entries = dd->cspec->num_msix_entries;
3686
3687 /* no interrupts till re-initted */
3688 qib_7322_set_intr_state(dd, 0);
3689
3690 if (msix_entries) {
3691 qib_7322_nomsix(dd);
3692 /* can be up to 512 bytes, too big for stack */
3693 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3694 sizeof(u64), GFP_KERNEL);
3695 if (!msix_vecsave)
3696 qib_dev_err(dd, "No mem to save MSIx data\n");
3697 } else
3698 msix_vecsave = NULL;
3699
3700 /*
3701 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
3702 * info that is set up by the BIOS, so we have to save and restore
3703 * it ourselves. There is some risk something could change it,
3704 * after we save it, but since we have disabled the MSIx, it
3705 * shouldn't be touched...
3706 */
3707 for (i = 0; i < msix_entries; i++) {
3708 u64 vecaddr, vecdata;
da12c1f6 3709
f931551b
RC		 3710 vecaddr = qib_read_kreg64(dd, 2 * i +
3711 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3712 vecdata = qib_read_kreg64(dd, 1 + 2 * i +
3713 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3714 if (msix_vecsave) {
3715 msix_vecsave[2 * i] = vecaddr;
3716 /* save it without the masked bit set */
3717 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL;
3718 }
3719 }
3720
3721 dd->pport->cpspec->ibdeltainprog = 0;
3722 dd->pport->cpspec->ibsymdelta = 0;
3723 dd->pport->cpspec->iblnkerrdelta = 0;
3724 dd->pport->cpspec->ibmalfdelta = 0;
1ed88dd7
MM		 3725 /* so we check interrupts work again */
3726 dd->z_int_counter = qib_int_counter(dd);
f931551b
RC		 3727
3728 /*
3729 * Keep chip from being accessed until we are ready. Use
3730 * writeq() directly, to allow the write even though QIB_PRESENT
e9c54999 3731 * isn't set.
f931551b
RC		 3732 */
3733 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR);
3734 dd->flags |= QIB_DOING_RESET;
3735 val = dd->control | QLOGIC_IB_C_RESET;
3736 writeq(val, &dd->kregbase[kr_control]);
3737
3738 for (i = 1; i <= 5; i++) {
3739 /*
3740 * Allow MBIST, etc. to complete; longer on each retry.
3741 * We sometimes get machine checks from bus timeout if no
3742 * response, so for now, make it *really* long.
3743 */
3744 msleep(1000 + (1 + i) * 3000);
3745
3746 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
3747
3748 /*
3749 * Use readq directly, so we don't need to mark it as PRESENT
3750 * until we get a successful indication that all is well.
3751 */
3752 val = readq(&dd->kregbase[kr_revision]);
3753 if (val == dd->revision)
3754 break;
3755 if (i == 5) {
7fac3301
MM		 3756 qib_dev_err(dd,
3757 "Failed to initialize after reset, unusable\n");
f931551b
RC		 3758 ret = 0;
3759 goto bail;
3760 }
3761 }
3762
3763 dd->flags |= QIB_PRESENT; /* it's back */
3764
3765 if (msix_entries) {
3766 /* restore the MSIx vector address and data if saved above */
3767 for (i = 0; i < msix_entries; i++) {
a778f3fd 3768 dd->cspec->msix_entries[i].msix.entry = i;
f931551b
RC		 3769 if (!msix_vecsave || !msix_vecsave[2 * i])
3770 continue;
3771 qib_write_kreg(dd, 2 * i +
3772 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3773 msix_vecsave[2 * i]);
3774 qib_write_kreg(dd, 1 + 2 * i +
3775 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3776 msix_vecsave[1 + 2 * i]);
3777 }
3778 }
3779
3780 /* initialize the remaining registers. */
3781 for (i = 0; i < dd->num_pports; ++i)
3782 write_7322_init_portregs(&dd->pport[i]);
3783 write_7322_initregs(dd);
3784
3785 if (qib_pcie_params(dd, dd->lbus_width,
3786 &dd->cspec->num_msix_entries,
3787 dd->cspec->msix_entries))
7fac3301
MM		 3788 qib_dev_err(dd,
3789 "Reset failed to setup PCIe or interrupts; continuing anyway\n");
f931551b
RC		 3790
3791 qib_setup_7322_interrupt(dd, 1);
3792
3793 for (i = 0; i < dd->num_pports; ++i) {
3794 struct qib_pportdata *ppd = &dd->pport[i];
3795
3796 spin_lock_irqsave(&ppd->lflags_lock, flags);
3797 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
3798 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3799 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3800 }
3801
3802bail:
3803 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */
3804 kfree(msix_vecsave);
3805 return ret;
3806}
3807
3808/**
3809 * qib_7322_put_tid - write a TID to the chip
3810 * @dd: the qlogic_ib device
3811 * @tidptr: pointer to the expected TID (in chip) to update
3812 * @tidtype: 0 for eager, 1 for expected
3813 * @pa: physical address of in memory buffer; tidinvalid if freeing
3814 */
3815static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
3816 u32 type, unsigned long pa)
3817{
3818 if (!(dd->flags & QIB_PRESENT))
3819 return;
3820 if (pa != dd->tidinvalid) {
3821 u64 chippa = pa >> IBA7322_TID_PA_SHIFT;
3822
3823 /* paranoia checks */
3824 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) {
3825 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
3826 pa);
3827 return;
3828 }
3829 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) {
7fac3301
MM		 3830 qib_dev_err(dd,
3831 "Physical page address 0x%lx larger than supported\n",
3832 pa);
f931551b
RC		 3833 return;
3834 }
3835
3836 if (type == RCVHQ_RCV_TYPE_EAGER)
3837 chippa |= dd->tidtemplate;
3838 else /* for now, always full 4KB page */
3839 chippa |= IBA7322_TID_SZ_4K;
3840 pa = chippa;
3841 }
3842 writeq(pa, tidptr);
3843 mmiowb();
3844}
3845
3846/**
3847 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3848 * @dd: the qlogic_ib device
3849 * @ctxt: the ctxt
3850 *
3851 * clear all TID entries for a ctxt, expected and eager.
3852 * Used from qib_close().
3853 */
3854static void qib_7322_clear_tids(struct qib_devdata *dd,
3855 struct qib_ctxtdata *rcd)
3856{
3857 u64 __iomem *tidbase;
3858 unsigned long tidinv;
3859 u32 ctxt;
3860 int i;
3861
3862 if (!dd->kregbase || !rcd)
3863 return;
3864
3865 ctxt = rcd->ctxt;
3866
3867 tidinv = dd->tidinvalid;
3868 tidbase = (u64 __iomem *)
3869 ((char __iomem *) dd->kregbase +
3870 dd->rcvtidbase +
3871 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
3872
3873 for (i = 0; i < dd->rcvtidcnt; i++)
3874 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
3875 tidinv);
3876
3877 tidbase = (u64 __iomem *)
3878 ((char __iomem *) dd->kregbase +
3879 dd->rcvegrbase +
3880 rcd->rcvegr_tid_base * sizeof(*tidbase));
3881
3882 for (i = 0; i < rcd->rcvegrcnt; i++)
3883 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
3884 tidinv);
3885}
3886
3887/**
3888 * qib_7322_tidtemplate - setup constants for TID updates
3889 * @dd: the qlogic_ib device
3890 *
3891 * We setup stuff that we use a lot, to avoid calculating each time
3892 */
3893static void qib_7322_tidtemplate(struct qib_devdata *dd)
3894{
3895 /*
3896 * For now, we always allocate 4KB buffers (at init) so we can
3897 * receive max size packets. We may want a module parameter to
3898 * specify 2KB or 4KB and/or make it per port instead of per device
3899 * for those who want to reduce memory footprint. Note that the
3900 * rcvhdrentsize size must be large enough to hold the largest
3901 * IB header (currently 96 bytes) that we expect to handle (plus of
3902 * course the 2 dwords of RHF).
3903 */
3904 if (dd->rcvegrbufsize == 2048)
3905 dd->tidtemplate = IBA7322_TID_SZ_2K;
3906 else if (dd->rcvegrbufsize == 4096)
3907 dd->tidtemplate = IBA7322_TID_SZ_4K;
3908 dd->tidinvalid = 0;
3909}
3910
3911/**
3912 * qib_init_7322_get_base_info - set chip-specific flags for user code
3913 * @rcd: the qlogic_ib ctxt
3914 * @kbase: qib_base_info pointer
3915 *
3916 * We set the PCIE flag because the lower bandwidth on PCIe vs
3917 * HyperTransport can affect some user packet algorithims.
3918 */
3919
3920static int qib_7322_get_base_info(struct qib_ctxtdata *rcd,
3921 struct qib_base_info *kinfo)
3922{
3923 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP |
3924 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL |
3925 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA;
3926 if (rcd->dd->cspec->r1)
3927 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK;
3928 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
3929 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
3930
3931 return 0;
3932}
3933
3934static struct qib_message_header *
3935qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
3936{
3937 u32 offset = qib_hdrget_offset(rhf_addr);
3938
3939 return (struct qib_message_header *)
3940 (rhf_addr - dd->rhf_offset + offset);
3941}
3942
3943/*
3944 * Configure number of contexts.
3945 */
3946static void qib_7322_config_ctxts(struct qib_devdata *dd)
3947{
3948 unsigned long flags;
3949 u32 nchipctxts;
3950
3951 nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
3952 dd->cspec->numctxts = nchipctxts;
3953 if (qib_n_krcv_queues > 1 && dd->num_pports) {
f931551b
RC		 3954 dd->first_user_ctxt = NUM_IB_PORTS +
3955 (qib_n_krcv_queues - 1) * dd->num_pports;
3956 if (dd->first_user_ctxt > nchipctxts)
3957 dd->first_user_ctxt = nchipctxts;
3958 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports;
3959 } else {
3960 dd->first_user_ctxt = NUM_IB_PORTS;
3961 dd->n_krcv_queues = 1;
3962 }
3963
3964 if (!qib_cfgctxts) {
3965 int nctxts = dd->first_user_ctxt + num_online_cpus();
3966
3967 if (nctxts <= 6)
3968 dd->ctxtcnt = 6;
3969 else if (nctxts <= 10)
3970 dd->ctxtcnt = 10;
3971 else if (nctxts <= nchipctxts)
3972 dd->ctxtcnt = nchipctxts;
3973 } else if (qib_cfgctxts < dd->num_pports)
3974 dd->ctxtcnt = dd->num_pports;
3975 else if (qib_cfgctxts <= nchipctxts)
3976 dd->ctxtcnt = qib_cfgctxts;
3977 if (!dd->ctxtcnt) /* none of the above, set to max */
3978 dd->ctxtcnt = nchipctxts;
3979
3980 /*
3981 * Chip can be configured for 6, 10, or 18 ctxts, and choice
3982 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
3983 * Lock to be paranoid about later motion, etc.
3984 */
3985 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3986 if (dd->ctxtcnt > 10)
3987 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3988 else if (dd->ctxtcnt > 6)
3989 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3990 /* else configure for default 6 receive ctxts */
3991
3992 /* The XRC opcode is 5. */
3993 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
3994
3995 /*
3996 * RcvCtrl *must* be written here so that the
3997 * chip understands how to change rcvegrcnt below.
3998 */
3999 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4000 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4001
4002 /* kr_rcvegrcnt changes based on the number of contexts enabled */
4003 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
0a43e117
MM		 4004 if (qib_rcvhdrcnt)
4005 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
4006 else
8d4548f2 4007 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt,
0a43e117 4008 dd->num_pports > 1 ? 1024U : 2048U);
f931551b
RC		 4009}
4010
4011static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
4012{
4013
4014 int lsb, ret = 0;
4015 u64 maskr; /* right-justified mask */
4016
4017 switch (which) {
4018
4019 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
4020 ret = ppd->link_width_enabled;
4021 goto done;
4022
4023 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
4024 ret = ppd->link_width_active;
4025 goto done;
4026
4027 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
4028 ret = ppd->link_speed_enabled;
4029 goto done;
4030
4031 case QIB_IB_CFG_SPD: /* Get current Link spd */
4032 ret = ppd->link_speed_active;
4033 goto done;
4034
4035 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
4036 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4037 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4038 break;
4039
4040 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
4041 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4042 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4043 break;
4044
4045 case QIB_IB_CFG_LINKLATENCY:
4046 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
4047 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
4048 goto done;
4049
4050 case QIB_IB_CFG_OP_VLS:
4051 ret = ppd->vls_operational;
4052 goto done;
4053
4054 case QIB_IB_CFG_VL_HIGH_CAP:
4055 ret = 16;
4056 goto done;
4057
4058 case QIB_IB_CFG_VL_LOW_CAP:
4059 ret = 16;
4060 goto done;
4061
4062 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
4063 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4064 OverrunThreshold);
4065 goto done;
4066
4067 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
4068 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4069 PhyerrThreshold);
4070 goto done;
4071
4072 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
4073 /* will only take effect when the link state changes */
4074 ret = (ppd->cpspec->ibcctrl_a &
4075 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
4076 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
4077 goto done;
4078
4079 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
4080 lsb = IBA7322_IBC_HRTBT_LSB;
4081 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
4082 break;
4083
4084 case QIB_IB_CFG_PMA_TICKS:
4085 /*
4086 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
4087 * Since the clock is always 250MHz, the value is 3, 1 or 0.
4088 */
4089 if (ppd->link_speed_active == QIB_IB_QDR)
4090 ret = 3;
4091 else if (ppd->link_speed_active == QIB_IB_DDR)
4092 ret = 1;
4093 else
4094 ret = 0;
4095 goto done;
4096
4097 default:
4098 ret = -EINVAL;
4099 goto done;
4100 }
4101 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr);
4102done:
4103 return ret;
4104}
4105
4106/*
4107 * Below again cribbed liberally from older version. Do not lean
4108 * heavily on it.
4109 */
4110#define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
4111#define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
4112 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
4113
4114static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
4115{
4116 struct qib_devdata *dd = ppd->dd;
4117 u64 maskr; /* right-justified mask */
4118 int lsb, ret = 0;
4119 u16 lcmd, licmd;
4120 unsigned long flags;
4121
4122 switch (which) {
4123 case QIB_IB_CFG_LIDLMC:
4124 /*
4125 * Set LID and LMC. Combined to avoid possible hazard
4126 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
4127 */
4128 lsb = IBA7322_IBC_DLIDLMC_SHIFT;
4129 maskr = IBA7322_IBC_DLIDLMC_MASK;
4130 /*
4131 * For header-checking, the SLID in the packet will
4132 * be masked with SendIBSLMCMask, and compared
4133 * with SendIBSLIDAssignMask. Make sure we do not
4134 * set any bits not covered by the mask, or we get
4135 * false-positives.
4136 */
4137 qib_write_kreg_port(ppd, krp_sendslid,
4138 val & (val >> 16) & SendIBSLIDAssignMask);
4139 qib_write_kreg_port(ppd, krp_sendslidmask,
4140 (val >> 16) & SendIBSLMCMask);
4141 break;
4142
4143 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
4144 ppd->link_width_enabled = val;
4145 /* convert IB value to chip register value */
4146 if (val == IB_WIDTH_1X)
4147 val = 0;
4148 else if (val == IB_WIDTH_4X)
4149 val = 1;
4150 else
4151 val = 3;
4152 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS);
4153 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
4154 break;
4155
4156 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
4157 /*
4158 * As with width, only write the actual register if the
4159 * link is currently down, otherwise takes effect on next
25985edc 4160 * link change. Since setting is being explicitly requested
f931551b
RC		 4161 * (via MAD or sysfs), clear autoneg failure status if speed
4162 * autoneg is enabled.
4163 */
4164 ppd->link_speed_enabled = val;
4165 val <<= IBA7322_IBC_SPEED_LSB;
4166 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK |
4167 IBA7322_IBC_MAX_SPEED_MASK;
4168 if (val & (val - 1)) {
4169 /* Muliple speeds enabled */
4170 val |= IBA7322_IBC_IBTA_1_2_MASK |
4171 IBA7322_IBC_MAX_SPEED_MASK;
4172 spin_lock_irqsave(&ppd->lflags_lock, flags);
4173 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
4174 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
4175 } else if (val & IBA7322_IBC_SPEED_QDR)
4176 val |= IBA7322_IBC_IBTA_1_2_MASK;
4177 /* IBTA 1.2 mode + min/max + speed bits are contiguous */
4178 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
4179 break;
4180
4181 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
4182 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4183 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4184 break;
4185
4186 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
4187 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4188 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4189 break;
4190
4191 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
4192 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4193 OverrunThreshold);
4194 if (maskr != val) {
4195 ppd->cpspec->ibcctrl_a &=
4196 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
4197 ppd->cpspec->ibcctrl_a |= (u64) val <<
4198 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
4199 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4200 ppd->cpspec->ibcctrl_a);
4201 qib_write_kreg(dd, kr_scratch, 0ULL);
4202 }
4203 goto bail;
4204
4205 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
4206 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4207 PhyerrThreshold);
4208 if (maskr != val) {
4209 ppd->cpspec->ibcctrl_a &=
4210 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
4211 ppd->cpspec->ibcctrl_a |= (u64) val <<
4212 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
4213 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4214 ppd->cpspec->ibcctrl_a);
4215 qib_write_kreg(dd, kr_scratch, 0ULL);
4216 }
4217 goto bail;
4218
4219 case QIB_IB_CFG_PKEYS: /* update pkeys */
4220 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
4221 ((u64) ppd->pkeys[2] << 32) |
4222 ((u64) ppd->pkeys[3] << 48);
4223 qib_write_kreg_port(ppd, krp_partitionkey, maskr);
4224 goto bail;
4225
4226 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
4227 /* will only take effect when the link state changes */
4228 if (val == IB_LINKINITCMD_POLL)
4229 ppd->cpspec->ibcctrl_a &=
4230 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
4231 else /* SLEEP */
4232 ppd->cpspec->ibcctrl_a |=
4233 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
4234 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4235 qib_write_kreg(dd, kr_scratch, 0ULL);
4236 goto bail;
4237
4238 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
4239 /*
4240 * Update our housekeeping variables, and set IBC max
4241 * size, same as init code; max IBC is max we allow in
4242 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
4243 * Set even if it's unchanged, print debug message only
4244 * on changes.
4245 */
4246 val = (ppd->ibmaxlen >> 2) + 1;
4247 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
4248 ppd->cpspec->ibcctrl_a |= (u64)val <<
4249 SYM_LSB(IBCCtrlA_0, MaxPktLen);
4250 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4251 ppd->cpspec->ibcctrl_a);
4252 qib_write_kreg(dd, kr_scratch, 0ULL);
4253 goto bail;
4254
4255 case QIB_IB_CFG_LSTATE: /* set the IB link state */
4256 switch (val & 0xffff0000) {
4257 case IB_LINKCMD_DOWN:
4258 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
4259 ppd->cpspec->ibmalfusesnap = 1;
4260 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
4261 crp_errlink);
4262 if (!ppd->cpspec->ibdeltainprog &&
4263 qib_compat_ddr_negotiate) {
4264 ppd->cpspec->ibdeltainprog = 1;
4265 ppd->cpspec->ibsymsnap =
4266 read_7322_creg32_port(ppd,
4267 crp_ibsymbolerr);
4268 ppd->cpspec->iblnkerrsnap =
4269 read_7322_creg32_port(ppd,
4270 crp_iblinkerrrecov);
4271 }
4272 break;
4273
4274 case IB_LINKCMD_ARMED:
4275 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
4276 if (ppd->cpspec->ibmalfusesnap) {
4277 ppd->cpspec->ibmalfusesnap = 0;
4278 ppd->cpspec->ibmalfdelta +=
4279 read_7322_creg32_port(ppd,
4280 crp_errlink) -
4281 ppd->cpspec->ibmalfsnap;
4282 }
4283 break;
4284
4285 case IB_LINKCMD_ACTIVE:
4286 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
4287 break;
4288
4289 default:
4290 ret = -EINVAL;
4291 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
4292 goto bail;
4293 }
4294 switch (val & 0xffff) {
4295 case IB_LINKINITCMD_NOP:
4296 licmd = 0;
4297 break;
4298
4299 case IB_LINKINITCMD_POLL:
4300 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
4301 break;
4302
4303 case IB_LINKINITCMD_SLEEP:
4304 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
4305 break;
4306
4307 case IB_LINKINITCMD_DISABLE:
4308 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
4309 ppd->cpspec->chase_end = 0;
4310 /*
4311 * stop state chase counter and timer, if running.
4312 * wait forpending timer, but don't clear .data (ppd)!
4313 */
4314 if (ppd->cpspec->chase_timer.expires) {
4315 del_timer_sync(&ppd->cpspec->chase_timer);
4316 ppd->cpspec->chase_timer.expires = 0;
4317 }
4318 break;
4319
4320 default:
4321 ret = -EINVAL;
4322 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
4323 val & 0xffff);
4324 goto bail;
4325 }
4326 qib_set_ib_7322_lstate(ppd, lcmd, licmd);
4327 goto bail;
4328
4329 case QIB_IB_CFG_OP_VLS:
4330 if (ppd->vls_operational != val) {
4331 ppd->vls_operational = val;
4332 set_vls(ppd);
4333 }
4334 goto bail;
4335
4336 case QIB_IB_CFG_VL_HIGH_LIMIT:
4337 qib_write_kreg_port(ppd, krp_highprio_limit, val);
4338 goto bail;
4339
4340 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
4341 if (val > 3) {
4342 ret = -EINVAL;
4343 goto bail;
4344 }
4345 lsb = IBA7322_IBC_HRTBT_LSB;
4346 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
4347 break;
4348
4349 case QIB_IB_CFG_PORT:
4350 /* val is the port number of the switch we are connected to. */
4351 if (ppd->dd->cspec->r1) {
4352 cancel_delayed_work(&ppd->cpspec->ipg_work);
4353 ppd->cpspec->ipg_tries = 0;
4354 }
4355 goto bail;
4356
4357 default:
4358 ret = -EINVAL;
4359 goto bail;
4360 }
4361 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb);
4362 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
4363 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
4364 qib_write_kreg(dd, kr_scratch, 0);
4365bail:
4366 return ret;
4367}
4368
4369static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what)
4370{
4371 int ret = 0;
4372 u64 val, ctrlb;
4373
4374 /* only IBC loopback, may add serdes and xgxs loopbacks later */
4375 if (!strncmp(what, "ibc", 3)) {
4376 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
4377 Loopback);
4378 val = 0; /* disable heart beat, so link will come up */
4379 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
4380 ppd->dd->unit, ppd->port);
4381 } else if (!strncmp(what, "off", 3)) {
4382 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
4383 Loopback);
4384 /* enable heart beat again */
4385 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
7fac3301
MM		 4386 qib_devinfo(ppd->dd->pcidev,
4387 "Disabling IB%u:%u IBC loopback (normal)\n",
4388 ppd->dd->unit, ppd->port);
f931551b
RC		 4389 } else
4390 ret = -EINVAL;
4391 if (!ret) {
4392 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4393 ppd->cpspec->ibcctrl_a);
4394 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK
4395 << IBA7322_IBC_HRTBT_LSB);
4396 ppd->cpspec->ibcctrl_b = ctrlb | val;
4397 qib_write_kreg_port(ppd, krp_ibcctrl_b,
4398 ppd->cpspec->ibcctrl_b);
4399 qib_write_kreg(ppd->dd, kr_scratch, 0);
4400 }
4401 return ret;
4402}
4403
4404static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4405 struct ib_vl_weight_elem *vl)
4406{
4407 unsigned i;
4408
4409 for (i = 0; i < 16; i++, regno++, vl++) {
4410 u32 val = qib_read_kreg_port(ppd, regno);
4411
4412 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
4413 SYM_RMASK(LowPriority0_0, VirtualLane);
4414 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
4415 SYM_RMASK(LowPriority0_0, Weight);
4416 }
4417}
4418
4419static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4420 struct ib_vl_weight_elem *vl)
4421{
4422 unsigned i;
4423
4424 for (i = 0; i < 16; i++, regno++, vl++) {
4425 u64 val;
4426
4427 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
4428 SYM_LSB(LowPriority0_0, VirtualLane)) |
4429 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) <<
4430 SYM_LSB(LowPriority0_0, Weight));
4431 qib_write_kreg_port(ppd, regno, val);
4432 }
4433 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
4434 struct qib_devdata *dd = ppd->dd;
4435 unsigned long flags;
4436
4437 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4438 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
4439 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4440 qib_write_kreg(dd, kr_scratch, 0);
4441 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4442 }
4443}
4444
4445static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t)
4446{
4447 switch (which) {
4448 case QIB_IB_TBL_VL_HIGH_ARB:
4449 get_vl_weights(ppd, krp_highprio_0, t);
4450 break;
4451
4452 case QIB_IB_TBL_VL_LOW_ARB:
4453 get_vl_weights(ppd, krp_lowprio_0, t);
4454 break;
4455
4456 default:
4457 return -EINVAL;
4458 }
4459 return 0;
4460}
4461
4462static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
4463{
4464 switch (which) {
4465 case QIB_IB_TBL_VL_HIGH_ARB:
4466 set_vl_weights(ppd, krp_highprio_0, t);
4467 break;
4468
4469 case QIB_IB_TBL_VL_LOW_ARB:
4470 set_vl_weights(ppd, krp_lowprio_0, t);
4471 break;
4472
4473 default:
4474 return -EINVAL;
4475 }
4476 return 0;
4477}
4478
4479static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
19ede2e4 4480 u32 updegr, u32 egrhd, u32 npkts)
f931551b 4481{
19ede2e4
MM		 4482 /*
4483 * Need to write timeout register before updating rcvhdrhead to ensure
4484 * that the timer is enabled on reception of a packet.
4485 */
4486 if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT)
4487 adjust_rcv_timeout(rcd, npkts);
f931551b
RC		 4488 if (updegr)
4489 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
eddfb675
RV		 4490 mmiowb();
4491 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4492 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4493 mmiowb();
f931551b
RC		 4494}
4495
4496static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd)
4497{
4498 u32 head, tail;
4499
4500 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
4501 if (rcd->rcvhdrtail_kvaddr)
4502 tail = qib_get_rcvhdrtail(rcd);
4503 else
4504 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
4505 return head == tail;
4506}
4507
4508#define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4509 QIB_RCVCTRL_CTXT_DIS | \
4510 QIB_RCVCTRL_TIDFLOW_ENB | \
4511 QIB_RCVCTRL_TIDFLOW_DIS | \
4512 QIB_RCVCTRL_TAILUPD_ENB | \
4513 QIB_RCVCTRL_TAILUPD_DIS | \
4514 QIB_RCVCTRL_INTRAVAIL_ENB | \
4515 QIB_RCVCTRL_INTRAVAIL_DIS | \
4516 QIB_RCVCTRL_BP_ENB | \
4517 QIB_RCVCTRL_BP_DIS)
4518
4519#define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4520 QIB_RCVCTRL_CTXT_DIS | \
4521 QIB_RCVCTRL_PKEY_DIS | \
4522 QIB_RCVCTRL_PKEY_ENB)
4523
4524/*
4525 * Modify the RCVCTRL register in chip-specific way. This
4526 * is a function because bit positions and (future) register
4527 * location is chip-specifc, but the needed operations are
4528 * generic. <op> is a bit-mask because we often want to
4529 * do multiple modifications.
4530 */
4531static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op,
4532 int ctxt)
4533{
4534 struct qib_devdata *dd = ppd->dd;
4535 struct qib_ctxtdata *rcd;
4536 u64 mask, val;
4537 unsigned long flags;
4538
4539 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4540
4541 if (op & QIB_RCVCTRL_TIDFLOW_ENB)
4542 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4543 if (op & QIB_RCVCTRL_TIDFLOW_DIS)
4544 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4545 if (op & QIB_RCVCTRL_TAILUPD_ENB)
4546 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4547 if (op & QIB_RCVCTRL_TAILUPD_DIS)
4548 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4549 if (op & QIB_RCVCTRL_PKEY_ENB)
4550 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4551 if (op & QIB_RCVCTRL_PKEY_DIS)
4552 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4553 if (ctxt < 0) {
4554 mask = (1ULL << dd->ctxtcnt) - 1;
4555 rcd = NULL;
4556 } else {
4557 mask = (1ULL << ctxt);
4558 rcd = dd->rcd[ctxt];
4559 }
4560 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) {
4561 ppd->p_rcvctrl |=
4562 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4563 if (!(dd->flags & QIB_NODMA_RTAIL)) {
4564 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */
4565 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4566 }
4567 /* Write these registers before the context is enabled. */
4568 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,
4569 rcd->rcvhdrqtailaddr_phys);
4570 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,
4571 rcd->rcvhdrq_phys);
4572 rcd->seq_cnt = 1;
f931551b
RC		 4573 }
4574 if (op & QIB_RCVCTRL_CTXT_DIS)
4575 ppd->p_rcvctrl &=
4576 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4577 if (op & QIB_RCVCTRL_BP_ENB)
4578 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4579 if (op & QIB_RCVCTRL_BP_DIS)
4580 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4581 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
4582 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4583 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
4584 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4585 /*
4586 * Decide which registers to write depending on the ops enabled.
4587 * Special case is "flush" (no bits set at all)
4588 * which needs to write both.
4589 */
4590 if (op == 0 || (op & RCVCTRL_COMMON_MODS))
4591 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4592 if (op == 0 || (op & RCVCTRL_PORT_MODS))
4593 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
4594 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {
4595 /*
4596 * Init the context registers also; if we were
4597 * disabled, tail and head should both be zero
4598 * already from the enable, but since we don't
25985edc 4599 * know, we have to do it explicitly.
f931551b
RC		 4600 */
4601 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4602 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4603
4604 /* be sure enabling write seen; hd/tl should be 0 */
4605 (void) qib_read_kreg32(dd, kr_scratch);
4606 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4607 dd->rcd[ctxt]->head = val;
4608 /* If kctxt, interrupt on next receive. */
4609 if (ctxt < dd->first_user_ctxt)
4610 val |= dd->rhdrhead_intr_off;
4611 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4612 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) &&
4613 dd->rcd[ctxt] && dd->rhdrhead_intr_off) {
4614 /* arm rcv interrupt */
4615 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4616 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4617 }
4618 if (op & QIB_RCVCTRL_CTXT_DIS) {
4619 unsigned f;
4620
4621 /* Now that the context is disabled, clear these registers. */
4622 if (ctxt >= 0) {
4623 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);
4624 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);
4625 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4626 qib_write_ureg(dd, ur_rcvflowtable + f,
4627 TIDFLOW_ERRBITS, ctxt);
4628 } else {
4629 unsigned i;
4630
4631 for (i = 0; i < dd->cfgctxts; i++) {
4632 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr,
4633 i, 0);
4634 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0);
4635 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4636 qib_write_ureg(dd, ur_rcvflowtable + f,
4637 TIDFLOW_ERRBITS, i);
4638 }
4639 }
4640 }
4641 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4642}
4643
4644/*
4645 * Modify the SENDCTRL register in chip-specific way. This
4646 * is a function where there are multiple such registers with
4647 * slightly different layouts.
4648 * The chip doesn't allow back-to-back sendctrl writes, so write
4649 * the scratch register after writing sendctrl.
4650 *
4651 * Which register is written depends on the operation.
4652 * Most operate on the common register, while
4653 * SEND_ENB and SEND_DIS operate on the per-port ones.
4654 * SEND_ENB is included in common because it can change SPCL_TRIG
4655 */
4656#define SENDCTRL_COMMON_MODS (\
4657 QIB_SENDCTRL_CLEAR | \
4658 QIB_SENDCTRL_AVAIL_DIS | \
4659 QIB_SENDCTRL_AVAIL_ENB | \
4660 QIB_SENDCTRL_AVAIL_BLIP | \
4661 QIB_SENDCTRL_DISARM | \
4662 QIB_SENDCTRL_DISARM_ALL | \
4663 QIB_SENDCTRL_SEND_ENB)
4664
4665#define SENDCTRL_PORT_MODS (\
4666 QIB_SENDCTRL_CLEAR | \
4667 QIB_SENDCTRL_SEND_ENB | \
4668 QIB_SENDCTRL_SEND_DIS | \
4669 QIB_SENDCTRL_FLUSH)
4670
4671static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op)
4672{
4673 struct qib_devdata *dd = ppd->dd;
4674 u64 tmp_dd_sendctrl;
4675 unsigned long flags;
4676
4677 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4678
4679 /* First the dd ones that are "sticky", saved in shadow */
4680 if (op & QIB_SENDCTRL_CLEAR)
4681 dd->sendctrl = 0;
4682 if (op & QIB_SENDCTRL_AVAIL_DIS)
4683 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4684 else if (op & QIB_SENDCTRL_AVAIL_ENB) {
4685 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4686 if (dd->flags & QIB_USE_SPCL_TRIG)
4687 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4688 }
4689
4690 /* Then the ppd ones that are "sticky", saved in shadow */
4691 if (op & QIB_SENDCTRL_SEND_DIS)
4692 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4693 else if (op & QIB_SENDCTRL_SEND_ENB)
4694 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4695
4696 if (op & QIB_SENDCTRL_DISARM_ALL) {
4697 u32 i, last;
4698
4699 tmp_dd_sendctrl = dd->sendctrl;
4700 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
4701 /*
4702 * Disarm any buffers that are not yet launched,
4703 * disabling updates until done.
4704 */
4705 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4706 for (i = 0; i < last; i++) {
4707 qib_write_kreg(dd, kr_sendctrl,
4708 tmp_dd_sendctrl |
4709 SYM_MASK(SendCtrl, Disarm) | i);
4710 qib_write_kreg(dd, kr_scratch, 0);
4711 }
4712 }
4713
4714 if (op & QIB_SENDCTRL_FLUSH) {
4715 u64 tmp_ppd_sendctrl = ppd->p_sendctrl;
4716
4717 /*
4718 * Now drain all the fifos. The Abort bit should never be
4719 * needed, so for now, at least, we don't use it.
4720 */
4721 tmp_ppd_sendctrl |=
4722 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4723 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4724 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4725 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl);
4726 qib_write_kreg(dd, kr_scratch, 0);
4727 }
4728
4729 tmp_dd_sendctrl = dd->sendctrl;
4730
4731 if (op & QIB_SENDCTRL_DISARM)
4732 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4733 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) <<
4734 SYM_LSB(SendCtrl, DisarmSendBuf));
4735 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
4736 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4737 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4738
4739 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) {
4740 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
4741 qib_write_kreg(dd, kr_scratch, 0);
4742 }
4743
4744 if (op == 0 || (op & SENDCTRL_PORT_MODS)) {
4745 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4746 qib_write_kreg(dd, kr_scratch, 0);
4747 }
4748
4749 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
4750 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
4751 qib_write_kreg(dd, kr_scratch, 0);
4752 }
4753
4754 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4755
4756 if (op & QIB_SENDCTRL_FLUSH) {
4757 u32 v;
4758 /*
4759 * ensure writes have hit chip, then do a few
4760 * more reads, to allow DMA of pioavail registers
4761 * to occur, so in-memory copy is in sync with
4762 * the chip. Not always safe to sleep.
4763 */
4764 v = qib_read_kreg32(dd, kr_scratch);
4765 qib_write_kreg(dd, kr_scratch, v);
4766 v = qib_read_kreg32(dd, kr_scratch);
4767 qib_write_kreg(dd, kr_scratch, v);
4768 qib_read_kreg32(dd, kr_scratch);
4769 }
4770}
4771
4772#define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */
4773#define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */
4774#define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
4775
4776/**
4777 * qib_portcntr_7322 - read a per-port chip counter
4778 * @ppd: the qlogic_ib pport
4779 * @creg: the counter to read (not a chip offset)
4780 */
4781static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg)
4782{
4783 struct qib_devdata *dd = ppd->dd;
4784 u64 ret = 0ULL;
4785 u16 creg;
4786 /* 0xffff for unimplemented or synthesized counters */
4787 static const u32 xlator[] = {
4788 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG,
4789 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG,
4790 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount,
4791 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount,
4792 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount,
4793 [QIBPORTCNTR_SENDSTALL] = crp_sendstall,
4794 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG,
4795 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount,
4796 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount,
4797 [QIBPORTCNTR_RCVEBP] = crp_rcvebp,
4798 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl,
4799 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG,
4800 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */
4801 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr,
4802 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr,
4803 [QIBPORTCNTR_ERRICRC] = crp_erricrc,
4804 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc,
4805 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc,
4806 [QIBPORTCNTR_BADFORMAT] = crp_badformat,
4807 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen,
4808 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr,
4809 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen,
4810 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl,
4811 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl,
4812 [QIBPORTCNTR_ERRLINK] = crp_errlink,
4813 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown,
4814 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov,
4815 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr,
4816 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt,
4817 [QIBPORTCNTR_ERRPKEY] = crp_errpkey,
4818 /*
4819 * the next 3 aren't really counters, but were implemented
4820 * as counters in older chips, so still get accessed as
4821 * though they were counters from this code.
4822 */
4823 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval,
4824 [QIBPORTCNTR_PSSTART] = krp_psstart,
4825 [QIBPORTCNTR_PSSTAT] = krp_psstat,
4826 /* pseudo-counter, summed for all ports */
4827 [QIBPORTCNTR_KHDROVFL] = 0xffff,
4828 };
4829
4830 if (reg >= ARRAY_SIZE(xlator)) {
4831 qib_devinfo(ppd->dd->pcidev,
4832 "Unimplemented portcounter %u\n", reg);
4833 goto done;
4834 }
4835 creg = xlator[reg] & _PORT_CNTR_IDXMASK;
4836
4837 /* handle non-counters and special cases first */
4838 if (reg == QIBPORTCNTR_KHDROVFL) {
4839 int i;
4840
4841 /* sum over all kernel contexts (skip if mini_init) */
4842 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) {
4843 struct qib_ctxtdata *rcd = dd->rcd[i];
4844
4845 if (!rcd || rcd->ppd != ppd)
4846 continue;
4847 ret += read_7322_creg32(dd, cr_base_egrovfl + i);
4848 }
4849 goto done;
4850 } else if (reg == QIBPORTCNTR_RXDROPPKT) {
4851 /*
4852 * Used as part of the synthesis of port_rcv_errors
4853 * in the verbs code for IBTA counters. Not needed for 7322,
4854 * because all the errors are already counted by other cntrs.
4855 */
4856 goto done;
4857 } else if (reg == QIBPORTCNTR_PSINTERVAL ||
4858 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) {
4859 /* were counters in older chips, now per-port kernel regs */
4860 ret = qib_read_kreg_port(ppd, creg);
4861 goto done;
4862 }
4863
4864 /*
4865 * Only fast increment counters are 64 bits; use 32 bit reads to
4866 * avoid two independent reads when on Opteron.
4867 */
4868 if (xlator[reg] & _PORT_64BIT_FLAG)
4869 ret = read_7322_creg_port(ppd, creg);
4870 else
4871 ret = read_7322_creg32_port(ppd, creg);
4872 if (creg == crp_ibsymbolerr) {
4873 if (ppd->cpspec->ibdeltainprog)
4874 ret -= ret - ppd->cpspec->ibsymsnap;
4875 ret -= ppd->cpspec->ibsymdelta;
4876 } else if (creg == crp_iblinkerrrecov) {
4877 if (ppd->cpspec->ibdeltainprog)
4878 ret -= ret - ppd->cpspec->iblnkerrsnap;
4879 ret -= ppd->cpspec->iblnkerrdelta;
4880 } else if (creg == crp_errlink)
4881 ret -= ppd->cpspec->ibmalfdelta;
4882 else if (creg == crp_iblinkdown)
4883 ret += ppd->cpspec->iblnkdowndelta;
4884done:
4885 return ret;
4886}
4887
4888/*
4889 * Device counter names (not port-specific), one line per stat,
4890 * single string. Used by utilities like ipathstats to print the stats
4891 * in a way which works for different versions of drivers, without changing
4892 * the utility. Names need to be 12 chars or less (w/o newline), for proper
4893 * display by utility.
4894 * Non-error counters are first.
4895 * Start of "error" conters is indicated by a leading "E " on the first
4896 * "error" counter, and doesn't count in label length.
4897 * The EgrOvfl list needs to be last so we truncate them at the configured
4898 * context count for the device.
4899 * cntr7322indices contains the corresponding register indices.
4900 */
4901static const char cntr7322names[] =
4902 "Interrupts\n"
4903 "HostBusStall\n"
4904 "E RxTIDFull\n"
4905 "RxTIDInvalid\n"
4906 "RxTIDFloDrop\n" /* 7322 only */
4907 "Ctxt0EgrOvfl\n"
4908 "Ctxt1EgrOvfl\n"
4909 "Ctxt2EgrOvfl\n"
4910 "Ctxt3EgrOvfl\n"
4911 "Ctxt4EgrOvfl\n"
4912 "Ctxt5EgrOvfl\n"
4913 "Ctxt6EgrOvfl\n"
4914 "Ctxt7EgrOvfl\n"
4915 "Ctxt8EgrOvfl\n"
4916 "Ctxt9EgrOvfl\n"
4917 "Ctx10EgrOvfl\n"
4918 "Ctx11EgrOvfl\n"
4919 "Ctx12EgrOvfl\n"
4920 "Ctx13EgrOvfl\n"
4921 "Ctx14EgrOvfl\n"
4922 "Ctx15EgrOvfl\n"
4923 "Ctx16EgrOvfl\n"
4924 "Ctx17EgrOvfl\n"
4925 ;
4926
4927static const u32 cntr7322indices[] = {
4928 cr_lbint | _PORT_64BIT_FLAG,
4929 cr_lbstall | _PORT_64BIT_FLAG,
4930 cr_tidfull,
4931 cr_tidinvalid,
4932 cr_rxtidflowdrop,
4933 cr_base_egrovfl + 0,
4934 cr_base_egrovfl + 1,
4935 cr_base_egrovfl + 2,
4936 cr_base_egrovfl + 3,
4937 cr_base_egrovfl + 4,
4938 cr_base_egrovfl + 5,
4939 cr_base_egrovfl + 6,
4940 cr_base_egrovfl + 7,
4941 cr_base_egrovfl + 8,
4942 cr_base_egrovfl + 9,
4943 cr_base_egrovfl + 10,
4944 cr_base_egrovfl + 11,
4945 cr_base_egrovfl + 12,
4946 cr_base_egrovfl + 13,
4947 cr_base_egrovfl + 14,
4948 cr_base_egrovfl + 15,
4949 cr_base_egrovfl + 16,
4950 cr_base_egrovfl + 17,
4951};
4952
4953/*
4954 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4955 * portcntr7322indices is somewhat complicated by some registers needing
4956 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
4957 */
4958static const char portcntr7322names[] =
4959 "TxPkt\n"
4960 "TxFlowPkt\n"
4961 "TxWords\n"
4962 "RxPkt\n"
4963 "RxFlowPkt\n"
4964 "RxWords\n"
4965 "TxFlowStall\n"
4966 "TxDmaDesc\n" /* 7220 and 7322-only */
4967 "E RxDlidFltr\n" /* 7220 and 7322-only */
4968 "IBStatusChng\n"
4969 "IBLinkDown\n"
4970 "IBLnkRecov\n"
4971 "IBRxLinkErr\n"
4972 "IBSymbolErr\n"
4973 "RxLLIErr\n"
4974 "RxBadFormat\n"
4975 "RxBadLen\n"
4976 "RxBufOvrfl\n"
4977 "RxEBP\n"
4978 "RxFlowCtlErr\n"
4979 "RxICRCerr\n"
4980 "RxLPCRCerr\n"
4981 "RxVCRCerr\n"
4982 "RxInvalLen\n"
4983 "RxInvalPKey\n"
4984 "RxPktDropped\n"
4985 "TxBadLength\n"
4986 "TxDropped\n"
4987 "TxInvalLen\n"
4988 "TxUnderrun\n"
4989 "TxUnsupVL\n"
4990 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4991 "RxVL15Drop\n"
4992 "RxVlErr\n"
4993 "XcessBufOvfl\n"
4994 "RxQPBadCtxt\n" /* 7322-only from here down */
4995 "TXBadHeader\n"
4996 ;
4997
4998static const u32 portcntr7322indices[] = {
4999 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
5000 crp_pktsendflow,
5001 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
5002 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
5003 crp_pktrcvflowctrl,
5004 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
5005 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
5006 crp_txsdmadesc | _PORT_64BIT_FLAG,
5007 crp_rxdlidfltr,
5008 crp_ibstatuschange,
5009 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
5010 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
5011 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
5012 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
5013 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
5014 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
5015 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
5016 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
5017 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
5018 crp_rcvflowctrlviol,
5019 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
5020 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
5021 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
5022 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
5023 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
5024 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
5025 crp_txminmaxlenerr,
5026 crp_txdroppedpkt,
5027 crp_txlenerr,
5028 crp_txunderrun,
5029 crp_txunsupvl,
5030 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
5031 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
5032 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
5033 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
5034 crp_rxqpinvalidctxt,
5035 crp_txhdrerr,
5036};
5037
5038/* do all the setup to make the counter reads efficient later */
5039static void init_7322_cntrnames(struct qib_devdata *dd)
5040{
5041 int i, j = 0;
5042 char *s;
5043
5044 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts;
5045 i++) {
5046 /* we always have at least one counter before the egrovfl */
5047 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
5048 j = 1;
5049 s = strchr(s + 1, '\n');
5050 if (s && j)
5051 j++;
5052 }
5053 dd->cspec->ncntrs = i;
5054 if (!s)
5055 /* full list; size is without terminating null */
5056 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
5057 else
5058 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
5059 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
5060 * sizeof(u64), GFP_KERNEL);
5061 if (!dd->cspec->cntrs)
5062 qib_dev_err(dd, "Failed allocation for counters\n");
5063
5064 for (i = 0, s = (char *)portcntr7322names; s; i++)
5065 s = strchr(s + 1, '\n');
5066 dd->cspec->nportcntrs = i - 1;
5067 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
5068 for (i = 0; i < dd->num_pports; ++i) {
5069 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
5070 * sizeof(u64), GFP_KERNEL);
5071 if (!dd->pport[i].cpspec->portcntrs)
7fac3301
MM		 5072 qib_dev_err(dd,
5073 "Failed allocation for portcounters\n");
f931551b
RC		 5074 }
5075}
5076
5077static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
5078 u64 **cntrp)
5079{
5080 u32 ret;
5081
5082 if (namep) {
5083 ret = dd->cspec->cntrnamelen;
5084 if (pos >= ret)
5085 ret = 0; /* final read after getting everything */
5086 else
5087 *namep = (char *) cntr7322names;
5088 } else {
5089 u64 *cntr = dd->cspec->cntrs;
5090 int i;
5091
5092 ret = dd->cspec->ncntrs * sizeof(u64);
5093 if (!cntr || pos >= ret) {
5094 /* everything read, or couldn't get memory */
5095 ret = 0;
5096 goto done;
5097 }
5098 *cntrp = cntr;
5099 for (i = 0; i < dd->cspec->ncntrs; i++)
5100 if (cntr7322indices[i] & _PORT_64BIT_FLAG)
5101 *cntr++ = read_7322_creg(dd,
5102 cntr7322indices[i] &
5103 _PORT_CNTR_IDXMASK);
5104 else
5105 *cntr++ = read_7322_creg32(dd,
5106 cntr7322indices[i]);
5107 }
5108done:
5109 return ret;
5110}
5111
5112static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
5113 char **namep, u64 **cntrp)
5114{
5115 u32 ret;
5116
5117 if (namep) {
5118 ret = dd->cspec->portcntrnamelen;
5119 if (pos >= ret)
5120 ret = 0; /* final read after getting everything */
5121 else
5122 *namep = (char *)portcntr7322names;
5123 } else {
5124 struct qib_pportdata *ppd = &dd->pport[port];
5125 u64 *cntr = ppd->cpspec->portcntrs;
5126 int i;
5127
5128 ret = dd->cspec->nportcntrs * sizeof(u64);
5129 if (!cntr || pos >= ret) {
5130 /* everything read, or couldn't get memory */
5131 ret = 0;
5132 goto done;
5133 }
5134 *cntrp = cntr;
5135 for (i = 0; i < dd->cspec->nportcntrs; i++) {
5136 if (portcntr7322indices[i] & _PORT_VIRT_FLAG)
5137 *cntr++ = qib_portcntr_7322(ppd,
5138 portcntr7322indices[i] &
5139 _PORT_CNTR_IDXMASK);
5140 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG)
5141 *cntr++ = read_7322_creg_port(ppd,
5142 portcntr7322indices[i] &
5143 _PORT_CNTR_IDXMASK);
5144 else
5145 *cntr++ = read_7322_creg32_port(ppd,
5146 portcntr7322indices[i]);
5147 }
5148 }
5149done:
5150 return ret;
5151}
5152
5153/**
5154 * qib_get_7322_faststats - get word counters from chip before they overflow
5155 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
5156 *
5157 * VESTIGIAL IBA7322 has no "small fast counters", so the only
5158 * real purpose of this function is to maintain the notion of
5159 * "active time", which in turn is only logged into the eeprom,
5160 * which we don;t have, yet, for 7322-based boards.
5161 *
5162 * called from add_timer
5163 */
5164static void qib_get_7322_faststats(unsigned long opaque)
5165{
5166 struct qib_devdata *dd = (struct qib_devdata *) opaque;
5167 struct qib_pportdata *ppd;
5168 unsigned long flags;
5169 u64 traffic_wds;
5170 int pidx;
5171
5172 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5173 ppd = dd->pport + pidx;
5174
5175 /*
5176 * If port isn't enabled or not operational ports, or
5177 * diags is running (can cause memory diags to fail)
5178 * skip this port this time.
5179 */
5180 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED)
5181 || dd->diag_client)
5182 continue;
5183
5184 /*
5185 * Maintain an activity timer, based on traffic
5186 * exceeding a threshold, so we need to check the word-counts
5187 * even if they are 64-bit.
5188 */
5189 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) +
5190 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND);
5191 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags);
5192 traffic_wds -= ppd->dd->traffic_wds;
5193 ppd->dd->traffic_wds += traffic_wds;
f931551b
RC		 5194 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags);
5195 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active &
5196 QIB_IB_QDR) &&
5197 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
5198 QIBL_LINKACTIVE)) &&
5199 ppd->cpspec->qdr_dfe_time &&
8482d5d1 5200 time_is_before_jiffies(ppd->cpspec->qdr_dfe_time)) {
f931551b
RC		 5201 ppd->cpspec->qdr_dfe_on = 0;
5202
5203 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
5204 ppd->dd->cspec->r1 ?
5205 QDR_STATIC_ADAPT_INIT_R1 :
5206 QDR_STATIC_ADAPT_INIT);
5207 force_h1(ppd);
5208 }
5209 }
5210 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
5211}
5212
5213/*
5214 * If we were using MSIx, try to fallback to INTx.
5215 */
5216static int qib_7322_intr_fallback(struct qib_devdata *dd)
5217{
5218 if (!dd->cspec->num_msix_entries)
5219 return 0; /* already using INTx */
5220
7fac3301
MM		 5221 qib_devinfo(dd->pcidev,
5222 "MSIx interrupt not detected, trying INTx interrupts\n");
f931551b
RC		 5223 qib_7322_nomsix(dd);
5224 qib_enable_intx(dd->pcidev);
5225 qib_setup_7322_interrupt(dd, 0);
5226 return 1;
5227}
5228
5229/*
5230 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
5231 * than resetting the IBC or external link state, and useful in some
5232 * cases to cause some retraining. To do this right, we reset IBC
5233 * as well, then return to previous state (which may be still in reset)
5234 * NOTE: some callers of this "know" this writes the current value
5235 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
5236 * check all callers.
5237 */
5238static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
5239{
5240 u64 val;
5241 struct qib_devdata *dd = ppd->dd;
5242 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
5243 SYM_MASK(IBPCSConfig_0, xcv_treset) |
5244 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
5245
5246 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
b9e03e04
RC		 5247 qib_write_kreg(dd, kr_hwerrmask,
5248 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
f931551b
RC		 5249 qib_write_kreg_port(ppd, krp_ibcctrl_a,
5250 ppd->cpspec->ibcctrl_a &
5251 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
5252
5253 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
5254 qib_read_kreg32(dd, kr_scratch);
5255 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
5256 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
5257 qib_write_kreg(dd, kr_scratch, 0ULL);
b9e03e04
RC		 5258 qib_write_kreg(dd, kr_hwerrclear,
5259 SYM_MASK(HwErrClear, statusValidNoEopClear));
5260 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
f931551b
RC		 5261}
5262
5263/*
5264 * This code for non-IBTA-compliant IB speed negotiation is only known to
5265 * work for the SDR to DDR transition, and only between an HCA and a switch
5266 * with recent firmware. It is based on observed heuristics, rather than
5267 * actual knowledge of the non-compliant speed negotiation.
5268 * It has a number of hard-coded fields, since the hope is to rewrite this
5269 * when a spec is available on how the negoation is intended to work.
5270 */
5271static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
5272 u32 dcnt, u32 *data)
5273{
5274 int i;
5275 u64 pbc;
5276 u32 __iomem *piobuf;
5277 u32 pnum, control, len;
5278 struct qib_devdata *dd = ppd->dd;
5279
5280 i = 0;
5281 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
5282 control = qib_7322_setpbc_control(ppd, len, 0, 15);
5283 pbc = ((u64) control << 32) | len;
5284 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) {
5285 if (i++ > 15)
5286 return;
5287 udelay(2);
5288 }
5289 /* disable header check on this packet, since it can't be valid */
5290 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL);
5291 writeq(pbc, piobuf);
5292 qib_flush_wc();
5293 qib_pio_copy(piobuf + 2, hdr, 7);
5294 qib_pio_copy(piobuf + 9, data, dcnt);
5295 if (dd->flags & QIB_USE_SPCL_TRIG) {
5296 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
5297
5298 qib_flush_wc();
5299 __raw_writel(0xaebecede, piobuf + spcl_off);
5300 }
5301 qib_flush_wc();
5302 qib_sendbuf_done(dd, pnum);
5303 /* and re-enable hdr check */
5304 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
5305}
5306
5307/*
5308 * _start packet gets sent twice at start, _done gets sent twice at end
5309 */
5310static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which)
5311{
5312 struct qib_devdata *dd = ppd->dd;
5313 static u32 swapped;
5314 u32 dw, i, hcnt, dcnt, *data;
5315 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
5316 static u32 madpayload_start[0x40] = {
5317 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
5318 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
5319 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
5320 };
5321 static u32 madpayload_done[0x40] = {
5322 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
5323 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
5324 0x40000001, 0x1388, 0x15e, /* rest 0's */
5325 };
5326
5327 dcnt = ARRAY_SIZE(madpayload_start);
5328 hcnt = ARRAY_SIZE(hdr);
5329 if (!swapped) {
5330 /* for maintainability, do it at runtime */
5331 for (i = 0; i < hcnt; i++) {
5332 dw = (__force u32) cpu_to_be32(hdr[i]);
5333 hdr[i] = dw;
5334 }
5335 for (i = 0; i < dcnt; i++) {
5336 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
5337 madpayload_start[i] = dw;
5338 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
5339 madpayload_done[i] = dw;
5340 }
5341 swapped = 1;
5342 }
5343
5344 data = which ? madpayload_done : madpayload_start;
5345
5346 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
5347 qib_read_kreg64(dd, kr_scratch);
5348 udelay(2);
5349 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
5350 qib_read_kreg64(dd, kr_scratch);
5351 udelay(2);
5352}
5353
5354/*
5355 * Do the absolute minimum to cause an IB speed change, and make it
5356 * ready, but don't actually trigger the change. The caller will
5357 * do that when ready (if link is in Polling training state, it will
5358 * happen immediately, otherwise when link next goes down)
5359 *
5360 * This routine should only be used as part of the DDR autonegotation
5361 * code for devices that are not compliant with IB 1.2 (or code that
5362 * fixes things up for same).
5363 *
5364 * When link has gone down, and autoneg enabled, or autoneg has
5365 * failed and we give up until next time we set both speeds, and
5366 * then we want IBTA enabled as well as "use max enabled speed.
5367 */
5368static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
5369{
5370 u64 newctrlb;
da12c1f6 5371
f931551b
RC		 5372 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK |
5373 IBA7322_IBC_IBTA_1_2_MASK |
5374 IBA7322_IBC_MAX_SPEED_MASK);
5375
5376 if (speed & (speed - 1)) /* multiple speeds */
5377 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) |
5378 IBA7322_IBC_IBTA_1_2_MASK |
5379 IBA7322_IBC_MAX_SPEED_MASK;
5380 else
5381 newctrlb |= speed == QIB_IB_QDR ?
5382 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK :
5383 ((speed == QIB_IB_DDR ?
5384 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR));
5385
5386 if (newctrlb == ppd->cpspec->ibcctrl_b)
5387 return;
5388
5389 ppd->cpspec->ibcctrl_b = newctrlb;
5390 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
5391 qib_write_kreg(ppd->dd, kr_scratch, 0);
5392}
5393
5394/*
5395 * This routine is only used when we are not talking to another
5396 * IB 1.2-compliant device that we think can do DDR.
5397 * (This includes all existing switch chips as of Oct 2007.)
5398 * 1.2-compliant devices go directly to DDR prior to reaching INIT
5399 */
5400static void try_7322_autoneg(struct qib_pportdata *ppd)
5401{
5402 unsigned long flags;
5403
5404 spin_lock_irqsave(&ppd->lflags_lock, flags);
5405 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
5406 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5407 qib_autoneg_7322_send(ppd, 0);
5408 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5409 qib_7322_mini_pcs_reset(ppd);
5410 /* 2 msec is minimum length of a poll cycle */
f0626710
TH		 5411 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work,
5412 msecs_to_jiffies(2));
f931551b
RC		 5413}
5414
5415/*
5416 * Handle the empirically determined mechanism for auto-negotiation
5417 * of DDR speed with switches.
5418 */
5419static void autoneg_7322_work(struct work_struct *work)
5420{
5421 struct qib_pportdata *ppd;
5422 struct qib_devdata *dd;
5423 u64 startms;
5424 u32 i;
5425 unsigned long flags;
5426
5427 ppd = container_of(work, struct qib_chippport_specific,
5428 autoneg_work.work)->ppd;
5429 dd = ppd->dd;
5430
5431 startms = jiffies_to_msecs(jiffies);
5432
5433 /*
5434 * Busy wait for this first part, it should be at most a
5435 * few hundred usec, since we scheduled ourselves for 2msec.
5436 */
5437 for (i = 0; i < 25; i++) {
5438 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState)
5439 == IB_7322_LT_STATE_POLLQUIET) {
5440 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
5441 break;
5442 }
5443 udelay(100);
5444 }
5445
5446 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
5447 goto done; /* we got there early or told to stop */
5448
5449 /* we expect this to timeout */
5450 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5451 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5452 msecs_to_jiffies(90)))
5453 goto done;
5454 qib_7322_mini_pcs_reset(ppd);
5455
5456 /* we expect this to timeout */
5457 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5458 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5459 msecs_to_jiffies(1700)))
5460 goto done;
5461 qib_7322_mini_pcs_reset(ppd);
5462
5463 set_7322_ibspeed_fast(ppd, QIB_IB_SDR);
5464
5465 /*
5466 * Wait up to 250 msec for link to train and get to INIT at DDR;
5467 * this should terminate early.
5468 */
5469 wait_event_timeout(ppd->cpspec->autoneg_wait,
5470 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5471 msecs_to_jiffies(250));
5472done:
5473 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
5474 spin_lock_irqsave(&ppd->lflags_lock, flags);
5475 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
5476 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) {
5477 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
5478 ppd->cpspec->autoneg_tries = 0;
5479 }
5480 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5481 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5482 }
5483}
5484
5485/*
5486 * This routine is used to request IPG set in the QLogic switch.
5487 * Only called if r1.
5488 */
5489static void try_7322_ipg(struct qib_pportdata *ppd)
5490{
5491 struct qib_ibport *ibp = &ppd->ibport_data;
5492 struct ib_mad_send_buf *send_buf;
5493 struct ib_mad_agent *agent;
5494 struct ib_smp *smp;
5495 unsigned delay;
5496 int ret;
5497
f24a6d48 5498 agent = ibp->rvp.send_agent;
f931551b
RC		 5499 if (!agent)
5500 goto retry;
5501
5502 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR,
da2dfaa3
IW		 5503 IB_MGMT_MAD_DATA, GFP_ATOMIC,
5504 IB_MGMT_BASE_VERSION);
f931551b
RC		 5505 if (IS_ERR(send_buf))
5506 goto retry;
5507
4eadd8ff 5508 if (!ibp->smi_ah) {
f931551b
RC		 5509 struct ib_ah *ah;
5510
1fb9fed6 5511 ah = qib_create_qp0_ah(ibp, be16_to_cpu(IB_LID_PERMISSIVE));
f931551b 5512 if (IS_ERR(ah))
1fb9fed6 5513 ret = PTR_ERR(ah);
f931551b
RC		 5514 else {
5515 send_buf->ah = ah;
4eadd8ff 5516 ibp->smi_ah = ibah_to_rvtah(ah);
f931551b
RC		 5517 ret = 0;
5518 }
5519 } else {
4eadd8ff 5520 send_buf->ah = &ibp->smi_ah->ibah;
f931551b
RC		 5521 ret = 0;
5522 }
5523
5524 smp = send_buf->mad;
5525 smp->base_version = IB_MGMT_BASE_VERSION;
5526 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE;
5527 smp->class_version = 1;
5528 smp->method = IB_MGMT_METHOD_SEND;
5529 smp->hop_cnt = 1;
5530 smp->attr_id = QIB_VENDOR_IPG;
5531 smp->attr_mod = 0;
5532
5533 if (!ret)
5534 ret = ib_post_send_mad(send_buf, NULL);
5535 if (ret)
5536 ib_free_send_mad(send_buf);
5537retry:
5538 delay = 2 << ppd->cpspec->ipg_tries;
f0626710
TH		 5539 queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work,
5540 msecs_to_jiffies(delay));
f931551b
RC		 5541}
5542
5543/*
5544 * Timeout handler for setting IPG.
5545 * Only called if r1.
5546 */
5547static void ipg_7322_work(struct work_struct *work)
5548{
5549 struct qib_pportdata *ppd;
5550
5551 ppd = container_of(work, struct qib_chippport_specific,
5552 ipg_work.work)->ppd;
5553 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE))
5554 && ++ppd->cpspec->ipg_tries <= 10)
5555 try_7322_ipg(ppd);
5556}
5557
5558static u32 qib_7322_iblink_state(u64 ibcs)
5559{
5560 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState);
5561
5562 switch (state) {
5563 case IB_7322_L_STATE_INIT:
5564 state = IB_PORT_INIT;
5565 break;
5566 case IB_7322_L_STATE_ARM:
5567 state = IB_PORT_ARMED;
5568 break;
5569 case IB_7322_L_STATE_ACTIVE:
5570 /* fall through */
5571 case IB_7322_L_STATE_ACT_DEFER:
5572 state = IB_PORT_ACTIVE;
5573 break;
5574 default: /* fall through */
5575 case IB_7322_L_STATE_DOWN:
5576 state = IB_PORT_DOWN;
5577 break;
5578 }
5579 return state;
5580}
5581
5582/* returns the IBTA port state, rather than the IBC link training state */
5583static u8 qib_7322_phys_portstate(u64 ibcs)
5584{
5585 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState);
5586 return qib_7322_physportstate[state];
5587}
5588
5589static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
5590{
5591 int ret = 0, symadj = 0;
5592 unsigned long flags;
5593 int mult;
5594
5595 spin_lock_irqsave(&ppd->lflags_lock, flags);
5596 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
5597 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5598
5599 /* Update our picture of width and speed from chip */
5600 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5601 ppd->link_speed_active = QIB_IB_QDR;
5602 mult = 4;
5603 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5604 ppd->link_speed_active = QIB_IB_DDR;
5605 mult = 2;
5606 } else {
5607 ppd->link_speed_active = QIB_IB_SDR;
5608 mult = 1;
5609 }
5610 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5611 ppd->link_width_active = IB_WIDTH_4X;
5612 mult *= 4;
5613 } else
5614 ppd->link_width_active = IB_WIDTH_1X;
5615 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)];
5616
5617 if (!ibup) {
5618 u64 clr;
5619
5620 /* Link went down. */
5621 /* do IPG MAD again after linkdown, even if last time failed */
5622 ppd->cpspec->ipg_tries = 0;
5623 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5624 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5625 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5626 if (clr)
5627 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5628 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5629 QIBL_IB_AUTONEG_INPROG)))
5630 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5631 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
dde05cbd
MH		 5632 struct qib_qsfp_data *qd =
5633 &ppd->cpspec->qsfp_data;
a77fcf89
RC		 5634 /* unlock the Tx settings, speed may change */
5635 qib_write_kreg_port(ppd, krp_tx_deemph_override,
5636 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5637 reset_tx_deemphasis_override));
f931551b 5638 qib_cancel_sends(ppd);
a77fcf89
RC		 5639 /* on link down, ensure sane pcs state */
5640 qib_7322_mini_pcs_reset(ppd);
dde05cbd
MH		 5641 /* schedule the qsfp refresh which should turn the link
5642 off */
5643 if (ppd->dd->flags & QIB_HAS_QSFP) {
8482d5d1 5644 qd->t_insert = jiffies;
042f36e1 5645 queue_work(ib_wq, &qd->work);
dde05cbd 5646 }
f931551b
RC		 5647 spin_lock_irqsave(&ppd->sdma_lock, flags);
5648 if (__qib_sdma_running(ppd))
5649 __qib_sdma_process_event(ppd,
5650 qib_sdma_event_e70_go_idle);
5651 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
5652 }
5653 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5654 if (clr == ppd->cpspec->iblnkdownsnap)
5655 ppd->cpspec->iblnkdowndelta++;
5656 } else {
5657 if (qib_compat_ddr_negotiate &&
5658 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5659 QIBL_IB_AUTONEG_INPROG)) &&
5660 ppd->link_speed_active == QIB_IB_SDR &&
5661 (ppd->link_speed_enabled & QIB_IB_DDR)
5662 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) {
5663 /* we are SDR, and auto-negotiation enabled */
5664 ++ppd->cpspec->autoneg_tries;
5665 if (!ppd->cpspec->ibdeltainprog) {
5666 ppd->cpspec->ibdeltainprog = 1;
5667 ppd->cpspec->ibsymdelta +=
5668 read_7322_creg32_port(ppd,
5669 crp_ibsymbolerr) -
5670 ppd->cpspec->ibsymsnap;
5671 ppd->cpspec->iblnkerrdelta +=
5672 read_7322_creg32_port(ppd,
5673 crp_iblinkerrrecov) -
5674 ppd->cpspec->iblnkerrsnap;
5675 }
5676 try_7322_autoneg(ppd);
5677 ret = 1; /* no other IB status change processing */
5678 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5679 ppd->link_speed_active == QIB_IB_SDR) {
5680 qib_autoneg_7322_send(ppd, 1);
5681 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5682 qib_7322_mini_pcs_reset(ppd);
5683 udelay(2);
5684 ret = 1; /* no other IB status change processing */
5685 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5686 (ppd->link_speed_active & QIB_IB_DDR)) {
5687 spin_lock_irqsave(&ppd->lflags_lock, flags);
5688 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
5689 QIBL_IB_AUTONEG_FAILED);
5690 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5691 ppd->cpspec->autoneg_tries = 0;
5692 /* re-enable SDR, for next link down */
5693 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5694 wake_up(&ppd->cpspec->autoneg_wait);
5695 symadj = 1;
5696 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
5697 /*
5698 * Clear autoneg failure flag, and do setup
5699 * so we'll try next time link goes down and
5700 * back to INIT (possibly connected to a
5701 * different device).
5702 */
5703 spin_lock_irqsave(&ppd->lflags_lock, flags);
5704 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
5705 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5706 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK;
5707 symadj = 1;
5708 }
5709 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5710 symadj = 1;
5711 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5712 try_7322_ipg(ppd);
5713 if (!ppd->cpspec->recovery_init)
5714 setup_7322_link_recovery(ppd, 0);
5715 ppd->cpspec->qdr_dfe_time = jiffies +
5716 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY);
5717 }
5718 ppd->cpspec->ibmalfusesnap = 0;
5719 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
5720 crp_errlink);
5721 }
5722 if (symadj) {
5723 ppd->cpspec->iblnkdownsnap =
5724 read_7322_creg32_port(ppd, crp_iblinkdown);
5725 if (ppd->cpspec->ibdeltainprog) {
5726 ppd->cpspec->ibdeltainprog = 0;
5727 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd,
5728 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap;
5729 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd,
5730 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
5731 }
5732 } else if (!ibup && qib_compat_ddr_negotiate &&
5733 !ppd->cpspec->ibdeltainprog &&
5734 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5735 ppd->cpspec->ibdeltainprog = 1;
5736 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
5737 crp_ibsymbolerr);
5738 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
5739 crp_iblinkerrrecov);
5740 }
5741
5742 if (!ret)
5743 qib_setup_7322_setextled(ppd, ibup);
5744 return ret;
5745}
5746
5747/*
5748 * Does read/modify/write to appropriate registers to
5749 * set output and direction bits selected by mask.
5750 * these are in their canonical postions (e.g. lsb of
5751 * dir will end up in D48 of extctrl on existing chips).
5752 * returns contents of GP Inputs.
5753 */
5754static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5755{
5756 u64 read_val, new_out;
5757 unsigned long flags;
5758
5759 if (mask) {
5760 /* some bits being written, lock access to GPIO */
5761 dir &= mask;
5762 out &= mask;
5763 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5764 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5765 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5766 new_out = (dd->cspec->gpio_out & ~mask) | out;
5767
5768 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5769 qib_write_kreg(dd, kr_gpio_out, new_out);
5770 dd->cspec->gpio_out = new_out;
5771 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5772 }
5773 /*
5774 * It is unlikely that a read at this time would get valid
5775 * data on a pin whose direction line was set in the same
5776 * call to this function. We include the read here because
5777 * that allows us to potentially combine a change on one pin with
5778 * a read on another, and because the old code did something like
5779 * this.
5780 */
5781 read_val = qib_read_kreg64(dd, kr_extstatus);
5782 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
5783}
5784
5785/* Enable writes to config EEPROM, if possible. Returns previous state */
5786static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen)
5787{
5788 int prev_wen;
5789 u32 mask;
5790
5791 mask = 1 << QIB_EEPROM_WEN_NUM;
5792 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM;
5793 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5794
5795 return prev_wen & 1;
5796}
5797
5798/*
5799 * Read fundamental info we need to use the chip. These are
5800 * the registers that describe chip capabilities, and are
5801 * saved in shadow registers.
5802 */
5803static void get_7322_chip_params(struct qib_devdata *dd)
5804{
5805 u64 val;
5806 u32 piobufs;
5807 int mtu;
5808
5809 dd->palign = qib_read_kreg32(dd, kr_pagealign);
5810
5811 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
5812
5813 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
5814 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
5815 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
5816 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
5817 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
5818
5819 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5820 dd->piobcnt2k = val & ~0U;
5821 dd->piobcnt4k = val >> 32;
5822 val = qib_read_kreg64(dd, kr_sendpiosize);
5823 dd->piosize2k = val & ~0U;
5824 dd->piosize4k = val >> 32;
5825
5826 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5827 if (mtu == -1)
5828 mtu = QIB_DEFAULT_MTU;
5829 dd->pport[0].ibmtu = (u32)mtu;
5830 dd->pport[1].ibmtu = (u32)mtu;
5831
5832 /* these may be adjusted in init_chip_wc_pat() */
5833 dd->pio2kbase = (u32 __iomem *)
5834 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
5835 dd->pio4kbase = (u32 __iomem *)
5836 ((char __iomem *) dd->kregbase +
5837 (dd->piobufbase >> 32));
5838 /*
5839 * 4K buffers take 2 pages; we use roundup just to be
5840 * paranoid; we calculate it once here, rather than on
5841 * ever buf allocate
5842 */
5843 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
5844
5845 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS;
5846
5847 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
5848 (sizeof(u64) * BITS_PER_BYTE / 2);
5849}
5850
5851/*
5852 * The chip base addresses in cspec and cpspec have to be set
5853 * after possible init_chip_wc_pat(), rather than in
5854 * get_7322_chip_params(), so split out as separate function
5855 */
5856static void qib_7322_set_baseaddrs(struct qib_devdata *dd)
5857{
5858 u32 cregbase;
da12c1f6 5859
f931551b
RC		 5860 cregbase = qib_read_kreg32(dd, kr_counterregbase);
5861
5862 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5863 (char __iomem *)dd->kregbase);
5864
5865 dd->egrtidbase = (u64 __iomem *)
5866 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
5867
5868 /* port registers are defined as relative to base of chip */
5869 dd->pport[0].cpspec->kpregbase =
5870 (u64 __iomem *)((char __iomem *)dd->kregbase);
5871 dd->pport[1].cpspec->kpregbase =
5872 (u64 __iomem *)(dd->palign +
5873 (char __iomem *)dd->kregbase);
5874 dd->pport[0].cpspec->cpregbase =
5875 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0],
5876 kr_counterregbase) + (char __iomem *)dd->kregbase);
5877 dd->pport[1].cpspec->cpregbase =
5878 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1],
5879 kr_counterregbase) + (char __iomem *)dd->kregbase);
5880}
5881
5882/*
5883 * This is a fairly special-purpose observer, so we only support
5884 * the port-specific parts of SendCtrl
5885 */
5886
5887#define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5888 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5889 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5890 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5891 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5892 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5893 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5894
5895static int sendctrl_hook(struct qib_devdata *dd,
5896 const struct diag_observer *op, u32 offs,
5897 u64 *data, u64 mask, int only_32)
5898{
5899 unsigned long flags;
5900 unsigned idx;
5901 unsigned pidx;
5902 struct qib_pportdata *ppd = NULL;
5903 u64 local_data, all_bits;
5904
5905 /*
5906 * The fixed correspondence between Physical ports and pports is
5907 * severed. We need to hunt for the ppd that corresponds
5908 * to the offset we got. And we have to do that without admitting
5909 * we know the stride, apparently.
5910 */
5911 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5912 u64 __iomem *psptr;
5913 u32 psoffs;
5914
5915 ppd = dd->pport + pidx;
5916 if (!ppd->cpspec->kpregbase)
5917 continue;
5918
5919 psptr = ppd->cpspec->kpregbase + krp_sendctrl;
5920 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr);
5921 if (psoffs == offs)
5922 break;
5923 }
5924
5925 /* If pport is not being managed by driver, just avoid shadows. */
5926 if (pidx >= dd->num_pports)
5927 ppd = NULL;
5928
5929 /* In any case, "idx" is flat index in kreg space */
5930 idx = offs / sizeof(u64);
5931
5932 all_bits = ~0ULL;
5933 if (only_32)
5934 all_bits >>= 32;
5935
5936 spin_lock_irqsave(&dd->sendctrl_lock, flags);
5937 if (!ppd || (mask & all_bits) != all_bits) {
5938 /*
5939 * At least some mask bits are zero, so we need
5940 * to read. The judgement call is whether from
5941 * reg or shadow. First-cut: read reg, and complain
5942 * if any bits which should be shadowed are different
5943 * from their shadowed value.
5944 */
5945 if (only_32)
5946 local_data = (u64)qib_read_kreg32(dd, idx);
5947 else
5948 local_data = qib_read_kreg64(dd, idx);
5949 *data = (local_data & ~mask) | (*data & mask);
5950 }
5951 if (mask) {
5952 /*
5953 * At least some mask bits are one, so we need
5954 * to write, but only shadow some bits.
5955 */
5956 u64 sval, tval; /* Shadowed, transient */
5957
5958 /*
5959 * New shadow val is bits we don't want to touch,
5960 * ORed with bits we do, that are intended for shadow.
5961 */
5962 if (ppd) {
5963 sval = ppd->p_sendctrl & ~mask;
5964 sval |= *data & SENDCTRL_SHADOWED & mask;
5965 ppd->p_sendctrl = sval;
5966 } else
5967 sval = *data & SENDCTRL_SHADOWED & mask;
5968 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
5969 qib_write_kreg(dd, idx, tval);
5970 qib_write_kreg(dd, kr_scratch, 0Ull);
5971 }
5972 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
5973 return only_32 ? 4 : 8;
5974}
5975
5976static const struct diag_observer sendctrl_0_observer = {
5977 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64),
5978 KREG_IDX(SendCtrl_0) * sizeof(u64)
5979};
5980
5981static const struct diag_observer sendctrl_1_observer = {
5982 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64),
5983 KREG_IDX(SendCtrl_1) * sizeof(u64)
5984};
5985
5986static ushort sdma_fetch_prio = 8;
5987module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
5988MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority");
5989
5990/* Besides logging QSFP events, we set appropriate TxDDS values */
5991static void init_txdds_table(struct qib_pportdata *ppd, int override);
5992
5993static void qsfp_7322_event(struct work_struct *work)
5994{
5995 struct qib_qsfp_data *qd;
5996 struct qib_pportdata *ppd;
8482d5d1 5997 unsigned long pwrup;
16d99812 5998 unsigned long flags;
f931551b
RC		 5999 int ret;
6000 u32 le2;
6001
6002 qd = container_of(work, struct qib_qsfp_data, work);
6003 ppd = qd->ppd;
dde05cbd
MH		 6004 pwrup = qd->t_insert +
6005 msecs_to_jiffies(QSFP_PWR_LAG_MSEC - QSFP_MODPRS_LAG_MSEC);
f931551b 6006
dde05cbd
MH		 6007 /* Delay for 20 msecs to allow ModPrs resistor to setup */
6008 mdelay(QSFP_MODPRS_LAG_MSEC);
6009
16d99812
MH		 6010 if (!qib_qsfp_mod_present(ppd)) {
6011 ppd->cpspec->qsfp_data.modpresent = 0;
dde05cbd
MH		 6012 /* Set the physical link to disabled */
6013 qib_set_ib_7322_lstate(ppd, 0,
6014 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
16d99812
MH		 6015 spin_lock_irqsave(&ppd->lflags_lock, flags);
6016 ppd->lflags &= ~QIBL_LINKV;
6017 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
6018 } else {
dde05cbd
MH		 6019 /*
6020 * Some QSFP's not only do not respond until the full power-up
6021 * time, but may behave badly if we try. So hold off responding
6022 * to insertion.
6023 */
6024 while (1) {
8482d5d1 6025 if (time_is_before_jiffies(pwrup))
dde05cbd
MH		 6026 break;
6027 msleep(20);
6028 }
6029
6030 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
6031
6032 /*
6033 * Need to change LE2 back to defaults if we couldn't
6034 * read the cable type (to handle cable swaps), so do this
6035 * even on failure to read cable information. We don't
6036 * get here for QME, so IS_QME check not needed here.
6037 */
6038 if (!ret && !ppd->dd->cspec->r1) {
6039 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech))
6040 le2 = LE2_QME;
6041 else if (qd->cache.atten[1] >= qib_long_atten &&
6042 QSFP_IS_CU(qd->cache.tech))
6043 le2 = LE2_5m;
6044 else
6045 le2 = LE2_DEFAULT;
6046 } else
4634b794 6047 le2 = LE2_DEFAULT;
dde05cbd
MH		 6048 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7));
6049 /*
6050 * We always change parameteters, since we can choose
6051 * values for cables without eeproms, and the cable may have
6052 * changed from a cable with full or partial eeprom content
6053 * to one with partial or no content.
6054 */
6055 init_txdds_table(ppd, 0);
6056 /* The physical link is being re-enabled only when the
16d99812
MH		 6057 * previous state was DISABLED and the VALID bit is not
6058 * set. This should only happen when the cable has been
6059 * physically pulled. */
6060 if (!ppd->cpspec->qsfp_data.modpresent &&
6061 (ppd->lflags & (QIBL_LINKV | QIBL_IB_LINK_DISABLED))) {
6062 ppd->cpspec->qsfp_data.modpresent = 1;
dde05cbd
MH		 6063 qib_set_ib_7322_lstate(ppd, 0,
6064 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
16d99812
MH		 6065 spin_lock_irqsave(&ppd->lflags_lock, flags);
6066 ppd->lflags |= QIBL_LINKV;
6067 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
6068 }
dde05cbd 6069 }
f931551b
RC		 6070}
6071
6072/*
6073 * There is little we can do but complain to the user if QSFP
6074 * initialization fails.
6075 */
6076static void qib_init_7322_qsfp(struct qib_pportdata *ppd)
6077{
6078 unsigned long flags;
6079 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data;
6080 struct qib_devdata *dd = ppd->dd;
6081 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N;
6082
6083 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
6084 qd->ppd = ppd;
6085 qib_qsfp_init(qd, qsfp_7322_event);
6086 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
6087 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
6088 dd->cspec->gpio_mask |= mod_prs_bit;
6089 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
6090 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
6091 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
6092}
6093
6094/*
a77fcf89 6095 * called at device initialization time, and also if the txselect
f931551b
RC		 6096 * module parameter is changed. This is used for cables that don't
6097 * have valid QSFP EEPROMs (not present, or attenuation is zero).
6098 * We initialize to the default, then if there is a specific
a77fcf89
RC		 6099 * unit,port match, we use that (and set it immediately, for the
6100 * current speed, if the link is at INIT or better).
f931551b 6101 * String format is "default# unit#,port#=# ... u,p=#", separators must
a77fcf89
RC		 6102 * be a SPACE character. A newline terminates. The u,p=# tuples may
6103 * optionally have "u,p=#,#", where the final # is the H1 value
f931551b
RC		 6104 * The last specific match is used (actually, all are used, but last
6105 * one is the one that winds up set); if none at all, fall back on default.
6106 */
6107static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
6108{
6109 char *nxt, *str;
a77fcf89 6110 u32 pidx, unit, port, deflt, h1;
f931551b 6111 unsigned long val;
a77fcf89 6112 int any = 0, seth1;
e706203c 6113 int txdds_size;
f931551b 6114
a77fcf89 6115 str = txselect_list;
f931551b 6116
a77fcf89 6117 /* default number is validated in setup_txselect() */
f931551b
RC		 6118 deflt = simple_strtoul(str, &nxt, 0);
6119 for (pidx = 0; pidx < dd->num_pports; ++pidx)
6120 dd->pport[pidx].cpspec->no_eep = deflt;
6121
e706203c
MM		 6122 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ;
6123 if (IS_QME(dd) || IS_QMH(dd))
6124 txdds_size += TXDDS_MFG_SZ;
6125
f931551b
RC		 6126 while (*nxt && nxt[1]) {
6127 str = ++nxt;
6128 unit = simple_strtoul(str, &nxt, 0);
6129 if (nxt == str || !*nxt || *nxt != ',') {
6130 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
6131 ;
6132 continue;
6133 }
6134 str = ++nxt;
6135 port = simple_strtoul(str, &nxt, 0);
6136 if (nxt == str || *nxt != '=') {
6137 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
6138 ;
6139 continue;
6140 }
6141 str = ++nxt;
6142 val = simple_strtoul(str, &nxt, 0);
6143 if (nxt == str) {
6144 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
6145 ;
6146 continue;
6147 }
e706203c 6148 if (val >= txdds_size)
f931551b 6149 continue;
a77fcf89
RC		 6150 seth1 = 0;
6151 h1 = 0; /* gcc thinks it might be used uninitted */
6152 if (*nxt == ',' && nxt[1]) {
6153 str = ++nxt;
6154 h1 = (u32)simple_strtoul(str, &nxt, 0);
6155 if (nxt == str)
6156 while (*nxt && *nxt++ != ' ') /* skip */
6157 ;
6158 else
6159 seth1 = 1;
6160 }
f931551b
RC		 6161 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports;
6162 ++pidx) {
a77fcf89
RC		 6163 struct qib_pportdata *ppd = &dd->pport[pidx];
6164
6165 if (ppd->port != port || !ppd->link_speed_supported)
f931551b 6166 continue;
a77fcf89 6167 ppd->cpspec->no_eep = val;
7c7a416e
RC		 6168 if (seth1)
6169 ppd->cpspec->h1_val = h1;
f931551b 6170 /* now change the IBC and serdes, overriding generic */
a77fcf89 6171 init_txdds_table(ppd, 1);
d70585f7 6172 /* Re-enable the physical state machine on mezz boards
dde05cbd
MH		 6173 * now that the correct settings have been set.
6174 * QSFP boards are handles by the QSFP event handler */
d70585f7
MH		 6175 if (IS_QMH(dd) || IS_QME(dd))
6176 qib_set_ib_7322_lstate(ppd, 0,
6177 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
f931551b
RC		 6178 any++;
6179 }
6180 if (*nxt == '\n')
6181 break; /* done */
6182 }
6183 if (change && !any) {
6184 /* no specific setting, use the default.
6185 * Change the IBC and serdes, but since it's
6186 * general, don't override specific settings.
6187 */
a77fcf89
RC		 6188 for (pidx = 0; pidx < dd->num_pports; ++pidx)
6189 if (dd->pport[pidx].link_speed_supported)
6190 init_txdds_table(&dd->pport[pidx], 0);
f931551b
RC		 6191 }
6192}
6193
a77fcf89
RC		 6194/* handle the txselect parameter changing */
6195static int setup_txselect(const char *str, struct kernel_param *kp)
f931551b
RC		 6196{
6197 struct qib_devdata *dd;
6198 unsigned long val;
2fadd831 6199 char *n;
da12c1f6 6200
f931551b 6201 if (strlen(str) >= MAX_ATTEN_LEN) {
7fac3301 6202 pr_info("txselect_values string too long\n");
f931551b
RC		 6203 return -ENOSPC;
6204 }
2fadd831
MM		 6205 val = simple_strtoul(str, &n, 0);
6206 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
e706203c 6207 TXDDS_MFG_SZ)) {
7fac3301 6208 pr_info("txselect_values must start with a number < %d\n",
e706203c 6209 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ);
2fadd831 6210 return -EINVAL;
f931551b 6211 }
7fac3301 6212 strcpy(txselect_list, str);
2fadd831 6213
f931551b 6214 list_for_each_entry(dd, &qib_dev_list, list)
a77fcf89
RC		 6215 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)
6216 set_no_qsfp_atten(dd, 1);
f931551b
RC		 6217 return 0;
6218}
6219
6220/*
6221 * Write the final few registers that depend on some of the
6222 * init setup. Done late in init, just before bringing up
6223 * the serdes.
6224 */
6225static int qib_late_7322_initreg(struct qib_devdata *dd)
6226{
6227 int ret = 0, n;
6228 u64 val;
6229
6230 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
6231 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
6232 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
6233 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
6234 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
6235 if (val != dd->pioavailregs_phys) {
7fac3301
MM		 6236 qib_dev_err(dd,
6237 "Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n",
6238 (unsigned long) dd->pioavailregs_phys,
6239 (unsigned long long) val);
f931551b
RC		 6240 ret = -EINVAL;
6241 }
6242
6243 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
6244 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL);
6245 /* driver sends get pkey, lid, etc. checking also, to catch bugs */
6246 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL);
6247
6248 qib_register_observer(dd, &sendctrl_0_observer);
6249 qib_register_observer(dd, &sendctrl_1_observer);
6250
6251 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN;
6252 qib_write_kreg(dd, kr_control, dd->control);
6253 /*
6254 * Set SendDmaFetchPriority and init Tx params, including
6255 * QSFP handler on boards that have QSFP.
6256 * First set our default attenuation entry for cables that
6257 * don't have valid attenuation.
6258 */
6259 set_no_qsfp_atten(dd, 0);
6260 for (n = 0; n < dd->num_pports; ++n) {
6261 struct qib_pportdata *ppd = dd->pport + n;
6262
6263 qib_write_kreg_port(ppd, krp_senddmaprioritythld,
6264 sdma_fetch_prio & 0xf);
6265 /* Initialize qsfp if present on board. */
6266 if (dd->flags & QIB_HAS_QSFP)
6267 qib_init_7322_qsfp(ppd);
6268 }
6269 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN;
6270 qib_write_kreg(dd, kr_control, dd->control);
6271
6272 return ret;
6273}
6274
6275/* per IB port errors. */
6276#define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
6277 MASK_ACROSS(8, 15))
6278#define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
6279#define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
6280 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
6281 MASK_ACROSS(0, 11))
6282
6283/*
6284 * Write the initialization per-port registers that need to be done at
6285 * driver load and after reset completes (i.e., that aren't done as part
6286 * of other init procedures called from qib_init.c).
6287 * Some of these should be redundant on reset, but play safe.
6288 */
6289static void write_7322_init_portregs(struct qib_pportdata *ppd)
6290{
6291 u64 val;
6292 int i;
6293
6294 if (!ppd->link_speed_supported) {
6295 /* no buffer credits for this port */
6296 for (i = 1; i < 8; i++)
6297 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
6298 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0);
6299 qib_write_kreg(ppd->dd, kr_scratch, 0);
6300 return;
6301 }
6302
6303 /*
6304 * Set the number of supported virtual lanes in IBC,
6305 * for flow control packet handling on unsupported VLs
6306 */
6307 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
6308 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
6309 val |= (u64)(ppd->vls_supported - 1) <<
6310 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
6311 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
6312
6313 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP);
6314
6315 /* enable tx header checking */
6316 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY |
6317 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID |
6318 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ);
6319
6320 qib_write_kreg_port(ppd, krp_ncmodectrl,
6321 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
6322
6323 /*
6324 * Unconditionally clear the bufmask bits. If SDMA is
6325 * enabled, we'll set them appropriately later.
6326 */
6327 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0);
6328 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0);
6329 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0);
6330 if (ppd->dd->cspec->r1)
6331 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
6332}
6333
6334/*
6335 * Write the initialization per-device registers that need to be done at
6336 * driver load and after reset completes (i.e., that aren't done as part
6337 * of other init procedures called from qib_init.c). Also write per-port
6338 * registers that are affected by overall device config, such as QP mapping
6339 * Some of these should be redundant on reset, but play safe.
6340 */
6341static void write_7322_initregs(struct qib_devdata *dd)
6342{
6343 struct qib_pportdata *ppd;
6344 int i, pidx;
6345 u64 val;
6346
6347 /* Set Multicast QPs received by port 2 to map to context one. */
6348 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1);
6349
6350 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
6351 unsigned n, regno;
6352 unsigned long flags;
6353
2528ea60
MM		 6354 if (dd->n_krcv_queues < 2 ||
6355 !dd->pport[pidx].link_speed_supported)
f931551b
RC		 6356 continue;
6357
6358 ppd = &dd->pport[pidx];
6359
6360 /* be paranoid against later code motion, etc. */
6361 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
6362 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
6363 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
6364
6365 /* Initialize QP to context mapping */
6366 regno = krp_rcvqpmaptable;
6367 val = 0;
6368 if (dd->num_pports > 1)
6369 n = dd->first_user_ctxt / dd->num_pports;
6370 else
6371 n = dd->first_user_ctxt - 1;
6372 for (i = 0; i < 32; ) {
6373 unsigned ctxt;
6374
6375 if (dd->num_pports > 1)
6376 ctxt = (i % n) * dd->num_pports + pidx;
6377 else if (i % n)
6378 ctxt = (i % n) + 1;
6379 else
6380 ctxt = ppd->hw_pidx;
6381 val |= ctxt << (5 * (i % 6));
6382 i++;
6383 if (i % 6 == 0) {
6384 qib_write_kreg_port(ppd, regno, val);
6385 val = 0;
6386 regno++;
6387 }
6388 }
6389 qib_write_kreg_port(ppd, regno, val);
6390 }
6391
6392 /*
6393 * Setup up interrupt mitigation for kernel contexts, but
6394 * not user contexts (user contexts use interrupts when
6395 * stalled waiting for any packet, so want those interrupts
6396 * right away).
6397 */
6398 for (i = 0; i < dd->first_user_ctxt; i++) {
6399 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
6400 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout);
6401 }
6402
6403 /*
6404 * Initialize as (disabled) rcvflow tables. Application code
6405 * will setup each flow as it uses the flow.
6406 * Doesn't clear any of the error bits that might be set.
6407 */
6408 val = TIDFLOW_ERRBITS; /* these are W1C */
0502f94c 6409 for (i = 0; i < dd->cfgctxts; i++) {
f931551b 6410 int flow;
da12c1f6 6411
f931551b
RC		 6412 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++)
6413 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
6414 }
6415
6416 /*
6417 * dual cards init to dual port recovery, single port cards to
6418 * the one port. Dual port cards may later adjust to 1 port,
6419 * and then back to dual port if both ports are connected
6420 * */
6421 if (dd->num_pports)
6422 setup_7322_link_recovery(dd->pport, dd->num_pports > 1);
6423}
6424
6425static int qib_init_7322_variables(struct qib_devdata *dd)
6426{
6427 struct qib_pportdata *ppd;
6428 unsigned features, pidx, sbufcnt;
6429 int ret, mtu;
6430 u32 sbufs, updthresh;
d4988623 6431 resource_size_t vl15off;
f931551b
RC		 6432
6433 /* pport structs are contiguous, allocated after devdata */
6434 ppd = (struct qib_pportdata *)(dd + 1);
6435 dd->pport = ppd;
6436 ppd[0].dd = dd;
6437 ppd[1].dd = dd;
6438
6439 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
6440
6441 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
6442 ppd[1].cpspec = &ppd[0].cpspec[1];
6443 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */
6444 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */
6445
6446 spin_lock_init(&dd->cspec->rcvmod_lock);
6447 spin_lock_init(&dd->cspec->gpio_lock);
6448
6449 /* we haven't yet set QIB_PRESENT, so use read directly */
6450 dd->revision = readq(&dd->kregbase[kr_revision]);
6451
6452 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
7fac3301
MM		 6453 qib_dev_err(dd,
6454 "Revision register read failure, giving up initialization\n");
f931551b
RC		 6455 ret = -ENODEV;
6456 goto bail;
6457 }
6458 dd->flags |= QIB_PRESENT; /* now register routines work */
6459
6460 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor);
6461 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor);
6462 dd->cspec->r1 = dd->minrev == 1;
6463
6464 get_7322_chip_params(dd);
6465 features = qib_7322_boardname(dd);
6466
6467 /* now that piobcnt2k and 4k set, we can allocate these */
6468 sbufcnt = dd->piobcnt2k + dd->piobcnt4k +
6469 NUM_VL15_BUFS + BITS_PER_LONG - 1;
6470 sbufcnt /= BITS_PER_LONG;
6471 dd->cspec->sendchkenable = kmalloc(sbufcnt *
6472 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
6473 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
6474 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
6475 dd->cspec->sendibchk = kmalloc(sbufcnt *
6476 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
6477 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
6478 !dd->cspec->sendibchk) {
6479 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n");
6480 ret = -ENOMEM;
6481 goto bail;
6482 }
6483
6484 ppd = dd->pport;
6485
6486 /*
6487 * GPIO bits for TWSI data and clock,
6488 * used for serial EEPROM.
6489 */
6490 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
6491 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
6492 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
6493
6494 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
6495 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP |
6496 QIB_HAS_THRESH_UPDATE |
6497 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0);
6498 dd->flags |= qib_special_trigger ?
6499 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
6500
6501 /*
6502 * Setup initial values. These may change when PAT is enabled, but
6503 * we need these to do initial chip register accesses.
6504 */
6505 qib_7322_set_baseaddrs(dd);
6506
6507 mtu = ib_mtu_enum_to_int(qib_ibmtu);
6508 if (mtu == -1)
6509 mtu = QIB_DEFAULT_MTU;
6510
6511 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6512 /* all hwerrors become interrupts, unless special purposed */
6513 dd->cspec->hwerrmask = ~0ULL;
6514 /* link_recovery setup causes these errors, so ignore them,
6515 * other than clearing them when they occur */
6516 dd->cspec->hwerrmask &=
6517 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
6518 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
6519 HWE_MASK(LATriggered));
6520
6521 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) {
6522 struct qib_chippport_specific *cp = ppd->cpspec;
da12c1f6 6523
f931551b
RC		 6524 ppd->link_speed_supported = features & PORT_SPD_CAP;
6525 features >>= PORT_SPD_CAP_SHIFT;
6526 if (!ppd->link_speed_supported) {
6527 /* single port mode (7340, or configured) */
6528 dd->skip_kctxt_mask |= 1 << pidx;
6529 if (pidx == 0) {
6530 /* Make sure port is disabled. */
6531 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6532 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6533 ppd[0] = ppd[1];
6534 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6535 IBSerdesPClkNotDetectMask_0)
6536 | SYM_MASK(HwErrMask,
6537 SDmaMemReadErrMask_0));
6538 dd->cspec->int_enable_mask &= ~(
6539 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
6540 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
6541 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
6542 SYM_MASK(IntMask, SDmaIntMask_0) |
6543 SYM_MASK(IntMask, ErrIntMask_0) |
6544 SYM_MASK(IntMask, SendDoneIntMask_0));
6545 } else {
6546 /* Make sure port is disabled. */
6547 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6548 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6549 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6550 IBSerdesPClkNotDetectMask_1)
6551 | SYM_MASK(HwErrMask,
6552 SDmaMemReadErrMask_1));
6553 dd->cspec->int_enable_mask &= ~(
6554 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6555 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6556 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6557 SYM_MASK(IntMask, SDmaIntMask_1) |
6558 SYM_MASK(IntMask, ErrIntMask_1) |
6559 SYM_MASK(IntMask, SendDoneIntMask_1));
6560 }
6561 continue;
6562 }
6563
6564 dd->num_pports++;
7d7632ad
MM		 6565 ret = qib_init_pportdata(ppd, dd, pidx, dd->num_pports);
6566 if (ret) {
6567 dd->num_pports--;
6568 goto bail;
6569 }
f931551b
RC		 6570
6571 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
6572 ppd->link_width_enabled = IB_WIDTH_4X;
6573 ppd->link_speed_enabled = ppd->link_speed_supported;
6574 /*
6575 * Set the initial values to reasonable default, will be set
6576 * for real when link is up.
6577 */
6578 ppd->link_width_active = IB_WIDTH_4X;
6579 ppd->link_speed_active = QIB_IB_SDR;
6580 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS];
6581 switch (qib_num_cfg_vls) {
6582 case 1:
6583 ppd->vls_supported = IB_VL_VL0;
6584 break;
6585 case 2:
6586 ppd->vls_supported = IB_VL_VL0_1;
6587 break;
6588 default:
6589 qib_devinfo(dd->pcidev,
6590 "Invalid num_vls %u, using 4 VLs\n",
6591 qib_num_cfg_vls);
6592 qib_num_cfg_vls = 4;
6593 /* fall through */
6594 case 4:
6595 ppd->vls_supported = IB_VL_VL0_3;
6596 break;
6597 case 8:
6598 if (mtu <= 2048)
6599 ppd->vls_supported = IB_VL_VL0_7;
6600 else {
6601 qib_devinfo(dd->pcidev,
a46a2802 6602 "Invalid num_vls %u for MTU %d , using 4 VLs\n",
f931551b
RC		 6603 qib_num_cfg_vls, mtu);
6604 ppd->vls_supported = IB_VL_VL0_3;
6605 qib_num_cfg_vls = 4;
6606 }
6607 break;
6608 }
6609 ppd->vls_operational = ppd->vls_supported;
6610
6611 init_waitqueue_head(&cp->autoneg_wait);
6612 INIT_DELAYED_WORK(&cp->autoneg_work,
6613 autoneg_7322_work);
6614 if (ppd->dd->cspec->r1)
6615 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work);
6616
6617 /*
6618 * For Mez and similar cards, no qsfp info, so do
6619 * the "cable info" setup here. Can be overridden
6620 * in adapter-specific routines.
6621 */
7c7a416e
RC		 6622 if (!(dd->flags & QIB_HAS_QSFP)) {
6623 if (!IS_QMH(dd) && !IS_QME(dd))
7fac3301
MM		 6624 qib_devinfo(dd->pcidev,
6625 "IB%u:%u: Unknown mezzanine card type\n",
6626 dd->unit, ppd->port);
a77fcf89 6627 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
f931551b 6628 /*
a77fcf89
RC		 6629 * Choose center value as default tx serdes setting
6630 * until changed through module parameter.
f931551b 6631 */
a77fcf89
RC		 6632 ppd->cpspec->no_eep = IS_QMH(dd) ?
6633 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4;
f931551b
RC		 6634 } else
6635 cp->h1_val = H1_FORCE_VAL;
6636
6637 /* Avoid writes to chip for mini_init */
6638 if (!qib_mini_init)
6639 write_7322_init_portregs(ppd);
6640
6641 init_timer(&cp->chase_timer);
6642 cp->chase_timer.function = reenable_chase;
6643 cp->chase_timer.data = (unsigned long)ppd;
6644
6645 ppd++;
6646 }
6647
0a43e117
MM		 6648 dd->rcvhdrentsize = qib_rcvhdrentsize ?
6649 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE;
6650 dd->rcvhdrsize = qib_rcvhdrsize ?
6651 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE;
a77fcf89 6652 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
f931551b
RC		 6653
6654 /* we always allocate at least 2048 bytes for eager buffers */
6655 dd->rcvegrbufsize = max(mtu, 2048);
9e1c0e43
MM		 6656 BUG_ON(!is_power_of_2(dd->rcvegrbufsize));
6657 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
f931551b
RC		 6658
6659 qib_7322_tidtemplate(dd);
6660
6661 /*
6662 * We can request a receive interrupt for 1 or
6663 * more packets from current offset.
6664 */
6665 dd->rhdrhead_intr_off =
6666 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6667
6668 /* setup the stats timer; the add_timer is done at end of init */
6669 init_timer(&dd->stats_timer);
6670 dd->stats_timer.function = qib_get_7322_faststats;
6671 dd->stats_timer.data = (unsigned long) dd;
6672
6673 dd->ureg_align = 0x10000; /* 64KB alignment */
6674
6675 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
6676
6677 qib_7322_config_ctxts(dd);
6678 qib_set_ctxtcnt(dd);
6679
d4988623
LR		 6680 /*
6681 * We do not set WC on the VL15 buffers to avoid
6682 * a rare problem with unaligned writes from
6683 * interrupt-flushed store buffers, so we need
6684 * to map those separately here. We can't solve
6685 * this for the rarely used mtrr case.
6686 */
6687 ret = init_chip_wc_pat(dd, 0);
6688 if (ret)
6689 goto bail;
fce24a9d 6690
d4988623
LR		 6691 /* vl15 buffers start just after the 4k buffers */
6692 vl15off = dd->physaddr + (dd->piobufbase >> 32) +
6693 dd->piobcnt4k * dd->align4k;
6694 dd->piovl15base = ioremap_nocache(vl15off,
6695 NUM_VL15_BUFS * dd->align4k);
6696 if (!dd->piovl15base) {
6697 ret = -ENOMEM;
6698 goto bail;
f931551b 6699 }
d4988623 6700
f931551b
RC		 6701 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
6702
6703 ret = 0;
6704 if (qib_mini_init)
6705 goto bail;
6706 if (!dd->num_pports) {
6707 qib_dev_err(dd, "No ports enabled, giving up initialization\n");
6708 goto bail; /* no error, so can still figure out why err */
6709 }
6710
6711 write_7322_initregs(dd);
6712 ret = qib_create_ctxts(dd);
6713 init_7322_cntrnames(dd);
6714
6715 updthresh = 8U; /* update threshold */
6716
6717 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
6718 * reserve the update threshold amount for other kernel use, such
6719 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
6720 * unless we aren't enabling SDMA, in which case we want to use
6721 * all the 4k bufs for the kernel.
6722 * if this was less than the update threshold, we could wait
6723 * a long time for an update. Coded this way because we
6724 * sometimes change the update threshold for various reasons,
6725 * and we want this to remain robust.
6726 */
6727 if (dd->flags & QIB_HAS_SEND_DMA) {
6728 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6729 sbufs = updthresh > 3 ? updthresh : 3;
6730 } else {
6731 dd->cspec->sdmabufcnt = 0;
6732 sbufs = dd->piobcnt4k;
6733 }
6734 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6735 dd->cspec->sdmabufcnt;
6736 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6737 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
bb77a077 6738 dd->last_pio = dd->cspec->lastbuf_for_pio;
f931551b
RC		 6739 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ?
6740 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0;
6741
6742 /*
6743 * If we have 16 user contexts, we will have 7 sbufs
6744 * per context, so reduce the update threshold to match. We
6745 * want to update before we actually run out, at low pbufs/ctxt
6746 * so give ourselves some margin.
6747 */
6748 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh)
6749 updthresh = dd->pbufsctxt - 2;
6750 dd->cspec->updthresh_dflt = updthresh;
6751 dd->cspec->updthresh = updthresh;
6752
6753 /* before full enable, no interrupts, no locking needed */
6754 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
6755 << SYM_LSB(SendCtrl, AvailUpdThld)) |
6756 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6757
6758 dd->psxmitwait_supported = 1;
6759 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE;
6760bail:
6761 if (!dd->ctxtcnt)
6762 dd->ctxtcnt = 1; /* for other initialization code */
6763
6764 return ret;
6765}
6766
6767static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
6768 u32 *pbufnum)
6769{
6770 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
6771 struct qib_devdata *dd = ppd->dd;
6772
6773 /* last is same for 2k and 4k, because we use 4k if all 2k busy */
6774 if (pbc & PBC_7322_VL15_SEND) {
6775 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx;
6776 last = first;
6777 } else {
6778 if ((plen + 1) > dd->piosize2kmax_dwords)
6779 first = dd->piobcnt2k;
6780 else
6781 first = 0;
6782 last = dd->cspec->lastbuf_for_pio;
6783 }
6784 return qib_getsendbuf_range(dd, pbufnum, first, last);
6785}
6786
6787static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv,
6788 u32 start)
6789{
6790 qib_write_kreg_port(ppd, krp_psinterval, intv);
6791 qib_write_kreg_port(ppd, krp_psstart, start);
6792}
6793
6794/*
6795 * Must be called with sdma_lock held, or before init finished.
6796 */
6797static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
6798{
6799 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt);
6800}
6801
0b3ddf38
DL		 6802/*
6803 * sdma_lock should be acquired before calling this routine
6804 */
6805static void dump_sdma_7322_state(struct qib_pportdata *ppd)
6806{
6807 u64 reg, reg1, reg2;
6808
6809 reg = qib_read_kreg_port(ppd, krp_senddmastatus);
6810 qib_dev_porterr(ppd->dd, ppd->port,
6811 "SDMA senddmastatus: 0x%016llx\n", reg);
6812
6813 reg = qib_read_kreg_port(ppd, krp_sendctrl);
6814 qib_dev_porterr(ppd->dd, ppd->port,
6815 "SDMA sendctrl: 0x%016llx\n", reg);
6816
6817 reg = qib_read_kreg_port(ppd, krp_senddmabase);
6818 qib_dev_porterr(ppd->dd, ppd->port,
6819 "SDMA senddmabase: 0x%016llx\n", reg);
6820
6821 reg = qib_read_kreg_port(ppd, krp_senddmabufmask0);
6822 reg1 = qib_read_kreg_port(ppd, krp_senddmabufmask1);
6823 reg2 = qib_read_kreg_port(ppd, krp_senddmabufmask2);
6824 qib_dev_porterr(ppd->dd, ppd->port,
6825 "SDMA senddmabufmask 0:%llx 1:%llx 2:%llx\n",
6826 reg, reg1, reg2);
6827
6828 /* get bufuse bits, clear them, and print them again if non-zero */
6829 reg = qib_read_kreg_port(ppd, krp_senddmabuf_use0);
6830 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg);
6831 reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1);
6832 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg1);
6833 reg2 = qib_read_kreg_port(ppd, krp_senddmabuf_use2);
6834 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg2);
6835 /* 0 and 1 should always be zero, so print as short form */
6836 qib_dev_porterr(ppd->dd, ppd->port,
6837 "SDMA current senddmabuf_use 0:%llx 1:%llx 2:%llx\n",
6838 reg, reg1, reg2);
6839 reg = qib_read_kreg_port(ppd, krp_senddmabuf_use0);
6840 reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1);
6841 reg2 = qib_read_kreg_port(ppd, krp_senddmabuf_use2);
6842 /* 0 and 1 should always be zero, so print as short form */
6843 qib_dev_porterr(ppd->dd, ppd->port,
6844 "SDMA cleared senddmabuf_use 0:%llx 1:%llx 2:%llx\n",
6845 reg, reg1, reg2);
6846
6847 reg = qib_read_kreg_port(ppd, krp_senddmatail);
6848 qib_dev_porterr(ppd->dd, ppd->port,
6849 "SDMA senddmatail: 0x%016llx\n", reg);
6850
6851 reg = qib_read_kreg_port(ppd, krp_senddmahead);
6852 qib_dev_porterr(ppd->dd, ppd->port,
6853 "SDMA senddmahead: 0x%016llx\n", reg);
6854
6855 reg = qib_read_kreg_port(ppd, krp_senddmaheadaddr);
6856 qib_dev_porterr(ppd->dd, ppd->port,
6857 "SDMA senddmaheadaddr: 0x%016llx\n", reg);
6858
6859 reg = qib_read_kreg_port(ppd, krp_senddmalengen);
6860 qib_dev_porterr(ppd->dd, ppd->port,
6861 "SDMA senddmalengen: 0x%016llx\n", reg);
6862
6863 reg = qib_read_kreg_port(ppd, krp_senddmadesccnt);
6864 qib_dev_porterr(ppd->dd, ppd->port,
6865 "SDMA senddmadesccnt: 0x%016llx\n", reg);
6866
6867 reg = qib_read_kreg_port(ppd, krp_senddmaidlecnt);
6868 qib_dev_porterr(ppd->dd, ppd->port,
6869 "SDMA senddmaidlecnt: 0x%016llx\n", reg);
6870
6871 reg = qib_read_kreg_port(ppd, krp_senddmaprioritythld);
6872 qib_dev_porterr(ppd->dd, ppd->port,
6873 "SDMA senddmapriorityhld: 0x%016llx\n", reg);
6874
6875 reg = qib_read_kreg_port(ppd, krp_senddmareloadcnt);
6876 qib_dev_porterr(ppd->dd, ppd->port,
6877 "SDMA senddmareloadcnt: 0x%016llx\n", reg);
6878
6879 dump_sdma_state(ppd);
6880}
6881
f931551b
RC		 6882static struct sdma_set_state_action sdma_7322_action_table[] = {
6883 [qib_sdma_state_s00_hw_down] = {
6884 .go_s99_running_tofalse = 1,
6885 .op_enable = 0,
6886 .op_intenable = 0,
6887 .op_halt = 0,
6888 .op_drain = 0,
6889 },
6890 [qib_sdma_state_s10_hw_start_up_wait] = {
6891 .op_enable = 0,
6892 .op_intenable = 1,
6893 .op_halt = 1,
6894 .op_drain = 0,
6895 },
6896 [qib_sdma_state_s20_idle] = {
6897 .op_enable = 1,
6898 .op_intenable = 1,
6899 .op_halt = 1,
6900 .op_drain = 0,
6901 },
6902 [qib_sdma_state_s30_sw_clean_up_wait] = {
6903 .op_enable = 0,
6904 .op_intenable = 1,
6905 .op_halt = 1,
6906 .op_drain = 0,
6907 },
6908 [qib_sdma_state_s40_hw_clean_up_wait] = {
6909 .op_enable = 1,
6910 .op_intenable = 1,
6911 .op_halt = 1,
6912 .op_drain = 0,
6913 },
6914 [qib_sdma_state_s50_hw_halt_wait] = {
6915 .op_enable = 1,
6916 .op_intenable = 1,
6917 .op_halt = 1,
6918 .op_drain = 1,
6919 },
6920 [qib_sdma_state_s99_running] = {
6921 .op_enable = 1,
6922 .op_intenable = 1,
6923 .op_halt = 0,
6924 .op_drain = 0,
6925 .go_s99_running_totrue = 1,
6926 },
6927};
6928
6929static void qib_7322_sdma_init_early(struct qib_pportdata *ppd)
6930{
6931 ppd->sdma_state.set_state_action = sdma_7322_action_table;
6932}
6933
6934static int init_sdma_7322_regs(struct qib_pportdata *ppd)
6935{
6936 struct qib_devdata *dd = ppd->dd;
6937 unsigned lastbuf, erstbuf;
6938 u64 senddmabufmask[3] = { 0 };
6939 int n, ret = 0;
6940
6941 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys);
6942 qib_sdma_7322_setlengen(ppd);
6943 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
6944 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt);
6945 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0);
6946 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys);
6947
6948 if (dd->num_pports)
6949 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6950 else
6951 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6952 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) -
6953 ((dd->num_pports == 1 || ppd->port == 2) ? n :
6954 dd->cspec->sdmabufcnt);
6955 lastbuf = erstbuf + n;
6956
6957 ppd->sdma_state.first_sendbuf = erstbuf;
6958 ppd->sdma_state.last_sendbuf = lastbuf;
6959 for (; erstbuf < lastbuf; ++erstbuf) {
6960 unsigned word = erstbuf / BITS_PER_LONG;
6961 unsigned bit = erstbuf & (BITS_PER_LONG - 1);
6962
6963 BUG_ON(word >= 3);
6964 senddmabufmask[word] |= 1ULL << bit;
6965 }
6966 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]);
6967 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]);
6968 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]);
6969 return ret;
6970}
6971
6972/* sdma_lock must be held */
6973static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd)
6974{
6975 struct qib_devdata *dd = ppd->dd;
6976 int sane;
6977 int use_dmahead;
6978 u16 swhead;
6979 u16 swtail;
6980 u16 cnt;
6981 u16 hwhead;
6982
6983 use_dmahead = __qib_sdma_running(ppd) &&
6984 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
6985retry:
6986 hwhead = use_dmahead ?
6987 (u16) le64_to_cpu(*ppd->sdma_head_dma) :
6988 (u16) qib_read_kreg_port(ppd, krp_senddmahead);
6989
6990 swhead = ppd->sdma_descq_head;
6991 swtail = ppd->sdma_descq_tail;
6992 cnt = ppd->sdma_descq_cnt;
6993
6994 if (swhead < swtail)
6995 /* not wrapped */
6996 sane = (hwhead >= swhead) & (hwhead <= swtail);
6997 else if (swhead > swtail)
6998 /* wrapped around */
6999 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
7000 (hwhead <= swtail);
7001 else
7002 /* empty */
7003 sane = (hwhead == swhead);
7004
7005 if (unlikely(!sane)) {
7006 if (use_dmahead) {
7007 /* try one more time, directly from the register */
7008 use_dmahead = 0;
7009 goto retry;
7010 }
7011 /* proceed as if no progress */
7012 hwhead = swhead;
7013 }
7014
7015 return hwhead;
7016}
7017
7018static int qib_sdma_7322_busy(struct qib_pportdata *ppd)
7019{
7020 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus);
7021
7022 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
7023 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
7024 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
7025 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
7026}
7027
7028/*
7029 * Compute the amount of delay before sending the next packet if the
7030 * port's send rate differs from the static rate set for the QP.
7031 * The delay affects the next packet and the amount of the delay is
7032 * based on the length of the this packet.
7033 */
7034static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen,
7035 u8 srate, u8 vl)
7036{
7037 u8 snd_mult = ppd->delay_mult;
7038 u8 rcv_mult = ib_rate_to_delay[srate];
7039 u32 ret;
7040
7041 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0;
7042
7043 /* Indicate VL15, else set the VL in the control word */
7044 if (vl == 15)
7045 ret |= PBC_7322_VL15_SEND_CTRL;
7046 else
7047 ret |= vl << PBC_VL_NUM_LSB;
7048 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB;
7049
7050 return ret;
7051}
7052
7053/*
7054 * Enable the per-port VL15 send buffers for use.
7055 * They follow the rest of the buffers, without a config parameter.
7056 * This was in initregs, but that is done before the shadow
7057 * is set up, and this has to be done after the shadow is
7058 * set up.
7059 */
7060static void qib_7322_initvl15_bufs(struct qib_devdata *dd)
7061{
7062 unsigned vl15bufs;
7063
7064 vl15bufs = dd->piobcnt2k + dd->piobcnt4k;
7065 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS,
7066 TXCHK_CHG_TYPE_KERN, NULL);
7067}
7068
7069static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd)
7070{
7071 if (rcd->ctxt < NUM_IB_PORTS) {
7072 if (rcd->dd->num_pports > 1) {
7073 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2;
7074 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;
7075 } else {
7076 rcd->rcvegrcnt = KCTXT0_EGRCNT;
7077 rcd->rcvegr_tid_base = 0;
7078 }
7079 } else {
7080 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
7081 rcd->rcvegr_tid_base = KCTXT0_EGRCNT +
7082 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;
7083 }
7084}
7085
7086#define QTXSLEEPS 5000
7087static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
7088 u32 len, u32 which, struct qib_ctxtdata *rcd)
7089{
7090 int i;
7091 const int last = start + len - 1;
7092 const int lastr = last / BITS_PER_LONG;
7093 u32 sleeps = 0;
7094 int wait = rcd != NULL;
7095 unsigned long flags;
7096
7097 while (wait) {
7098 unsigned long shadow;
7099 int cstart, previ = -1;
7100
7101 /*
7102 * when flipping from kernel to user, we can't change
7103 * the checking type if the buffer is allocated to the
7104 * driver. It's OK the other direction, because it's
7105 * from close, and we have just disarm'ed all the
7106 * buffers. All the kernel to kernel changes are also
7107 * OK.
7108 */
7109 for (cstart = start; cstart <= last; cstart++) {
7110 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
7111 / BITS_PER_LONG;
7112 if (i != previ) {
7113 shadow = (unsigned long)
7114 le64_to_cpu(dd->pioavailregs_dma[i]);
7115 previ = i;
7116 }
7117 if (test_bit(((2 * cstart) +
7118 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
7119 % BITS_PER_LONG, &shadow))
7120 break;
7121 }
7122
7123 if (cstart > last)
7124 break;
7125
7126 if (sleeps == QTXSLEEPS)
7127 break;
7128 /* make sure we see an updated copy next time around */
7129 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
7130 sleeps++;
a0a234d4 7131 msleep(20);
f931551b
RC		 7132 }
7133
7134 switch (which) {
7135 case TXCHK_CHG_TYPE_DIS1:
7136 /*
7137 * disable checking on a range; used by diags; just
7138 * one buffer, but still written generically
7139 */
7140 for (i = start; i <= last; i++)
7141 clear_bit(i, dd->cspec->sendchkenable);
7142 break;
7143
7144 case TXCHK_CHG_TYPE_ENAB1:
7145 /*
7146 * (re)enable checking on a range; used by diags; just
7147 * one buffer, but still written generically; read
7148 * scratch to be sure buffer actually triggered, not
7149 * just flushed from processor.
7150 */
7151 qib_read_kreg32(dd, kr_scratch);
7152 for (i = start; i <= last; i++)
7153 set_bit(i, dd->cspec->sendchkenable);
7154 break;
7155
7156 case TXCHK_CHG_TYPE_KERN:
7157 /* usable by kernel */
7158 for (i = start; i <= last; i++) {
7159 set_bit(i, dd->cspec->sendibchk);
7160 clear_bit(i, dd->cspec->sendgrhchk);
7161 }
7162 spin_lock_irqsave(&dd->uctxt_lock, flags);
7163 /* see if we need to raise avail update threshold */
7164 for (i = dd->first_user_ctxt;
7165 dd->cspec->updthresh != dd->cspec->updthresh_dflt
7166 && i < dd->cfgctxts; i++)
7167 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
7168 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
7169 < dd->cspec->updthresh_dflt)
7170 break;
7171 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
7172 if (i == dd->cfgctxts) {
7173 spin_lock_irqsave(&dd->sendctrl_lock, flags);
7174 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
7175 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
7176 dd->sendctrl |= (dd->cspec->updthresh &
7177 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
7178 SYM_LSB(SendCtrl, AvailUpdThld);
7179 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
7180 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
7181 }
7182 break;
7183
7184 case TXCHK_CHG_TYPE_USER:
7185 /* for user process */
7186 for (i = start; i <= last; i++) {
7187 clear_bit(i, dd->cspec->sendibchk);
7188 set_bit(i, dd->cspec->sendgrhchk);
7189 }
7190 spin_lock_irqsave(&dd->sendctrl_lock, flags);
7191 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
7192 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
7193 dd->cspec->updthresh = (rcd->piocnt /
7194 rcd->subctxt_cnt) - 1;
7195 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
7196 dd->sendctrl |= (dd->cspec->updthresh &
7197 SYM_RMASK(SendCtrl, AvailUpdThld))
7198 << SYM_LSB(SendCtrl, AvailUpdThld);
7199 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
7200 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
7201 } else
7202 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
7203 break;
7204
7205 default:
7206 break;
7207 }
7208
7209 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i)
7210 qib_write_kreg(dd, kr_sendcheckmask + i,
7211 dd->cspec->sendchkenable[i]);
7212
7213 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) {
7214 qib_write_kreg(dd, kr_sendgrhcheckmask + i,
7215 dd->cspec->sendgrhchk[i]);
7216 qib_write_kreg(dd, kr_sendibpktmask + i,
7217 dd->cspec->sendibchk[i]);
7218 }
7219
7220 /*
7221 * Be sure whatever we did was seen by the chip and acted upon,
7222 * before we return. Mostly important for which >= 2.
7223 */
7224 qib_read_kreg32(dd, kr_scratch);
7225}
7226
7227
7228/* useful for trigger analyzers, etc. */
7229static void writescratch(struct qib_devdata *dd, u32 val)
7230{
7231 qib_write_kreg(dd, kr_scratch, val);
7232}
7233
7234/* Dummy for now, use chip regs soon */
7235static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum)
7236{
7237 return -ENXIO;
7238}
7239
7240/**
7241 * qib_init_iba7322_funcs - set up the chip-specific function pointers
7242 * @dev: the pci_dev for qlogic_ib device
7243 * @ent: pci_device_id struct for this dev
7244 *
7245 * Also allocates, inits, and returns the devdata struct for this
7246 * device instance
7247 *
7248 * This is global, and is called directly at init to set up the
7249 * chip-specific function pointers for later use.
7250 */
7251struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
7252 const struct pci_device_id *ent)
7253{
7254 struct qib_devdata *dd;
7255 int ret, i;
7256 u32 tabsize, actual_cnt = 0;
7257
7258 dd = qib_alloc_devdata(pdev,
7259 NUM_IB_PORTS * sizeof(struct qib_pportdata) +
7260 sizeof(struct qib_chip_specific) +
7261 NUM_IB_PORTS * sizeof(struct qib_chippport_specific));
7262 if (IS_ERR(dd))
7263 goto bail;
7264
7265 dd->f_bringup_serdes = qib_7322_bringup_serdes;
7266 dd->f_cleanup = qib_setup_7322_cleanup;
7267 dd->f_clear_tids = qib_7322_clear_tids;
7268 dd->f_free_irq = qib_7322_free_irq;
7269 dd->f_get_base_info = qib_7322_get_base_info;
7270 dd->f_get_msgheader = qib_7322_get_msgheader;
7271 dd->f_getsendbuf = qib_7322_getsendbuf;
7272 dd->f_gpio_mod = gpio_7322_mod;
7273 dd->f_eeprom_wen = qib_7322_eeprom_wen;
7274 dd->f_hdrqempty = qib_7322_hdrqempty;
7275 dd->f_ib_updown = qib_7322_ib_updown;
7276 dd->f_init_ctxt = qib_7322_init_ctxt;
7277 dd->f_initvl15_bufs = qib_7322_initvl15_bufs;
7278 dd->f_intr_fallback = qib_7322_intr_fallback;
7279 dd->f_late_initreg = qib_late_7322_initreg;
7280 dd->f_setpbc_control = qib_7322_setpbc_control;
7281 dd->f_portcntr = qib_portcntr_7322;
7282 dd->f_put_tid = qib_7322_put_tid;
7283 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes;
7284 dd->f_rcvctrl = rcvctrl_7322_mod;
7285 dd->f_read_cntrs = qib_read_7322cntrs;
7286 dd->f_read_portcntrs = qib_read_7322portcntrs;
7287 dd->f_reset = qib_do_7322_reset;
7288 dd->f_init_sdma_regs = init_sdma_7322_regs;
7289 dd->f_sdma_busy = qib_sdma_7322_busy;
7290 dd->f_sdma_gethead = qib_sdma_7322_gethead;
7291 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl;
7292 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt;
7293 dd->f_sdma_update_tail = qib_sdma_update_7322_tail;
7294 dd->f_sendctrl = sendctrl_7322_mod;
7295 dd->f_set_armlaunch = qib_set_7322_armlaunch;
7296 dd->f_set_cntr_sample = qib_set_cntr_7322_sample;
7297 dd->f_iblink_state = qib_7322_iblink_state;
7298 dd->f_ibphys_portstate = qib_7322_phys_portstate;
7299 dd->f_get_ib_cfg = qib_7322_get_ib_cfg;
7300 dd->f_set_ib_cfg = qib_7322_set_ib_cfg;
7301 dd->f_set_ib_loopback = qib_7322_set_loopback;
7302 dd->f_get_ib_table = qib_7322_get_ib_table;
7303 dd->f_set_ib_table = qib_7322_set_ib_table;
7304 dd->f_set_intr_state = qib_7322_set_intr_state;
7305 dd->f_setextled = qib_setup_7322_setextled;
7306 dd->f_txchk_change = qib_7322_txchk_change;
7307 dd->f_update_usrhead = qib_update_7322_usrhead;
7308 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr;
7309 dd->f_xgxs_reset = qib_7322_mini_pcs_reset;
7310 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up;
7311 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up;
7312 dd->f_sdma_init_early = qib_7322_sdma_init_early;
7313 dd->f_writescratch = writescratch;
7314 dd->f_tempsense_rd = qib_7322_tempsense_rd;
8469ba39
MM		 7315#ifdef CONFIG_INFINIBAND_QIB_DCA
7316 dd->f_notify_dca = qib_7322_notify_dca;
7317#endif
f931551b
RC		 7318 /*
7319 * Do remaining PCIe setup and save PCIe values in dd.
7320 * Any error printing is already done by the init code.
7321 * On return, we have the chip mapped, but chip registers
7322 * are not set up until start of qib_init_7322_variables.
7323 */
7324 ret = qib_pcie_ddinit(dd, pdev, ent);
7325 if (ret < 0)
7326 goto bail_free;
7327
7328 /* initialize chip-specific variables */
7329 ret = qib_init_7322_variables(dd);
7330 if (ret)
7331 goto bail_cleanup;
7332
7333 if (qib_mini_init || !dd->num_pports)
7334 goto bail;
7335
7336 /*
7337 * Determine number of vectors we want; depends on port count
7338 * and number of configured kernel receive queues actually used.
7339 * Should also depend on whether sdma is enabled or not, but
7340 * that's such a rare testing case it's not worth worrying about.
7341 */
7342 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table);
7343 for (i = 0; i < tabsize; i++)
7344 if ((i < ARRAY_SIZE(irq_table) &&
7345 irq_table[i].port <= dd->num_pports) ||
7346 (i >= ARRAY_SIZE(irq_table) &&
7347 dd->rcd[i - ARRAY_SIZE(irq_table)]))
7348 actual_cnt++;
e67306a3
MM		 7349 /* reduce by ctxt's < 2 */
7350 if (qib_krcvq01_no_msi)
7351 actual_cnt -= dd->num_pports;
7352
f931551b 7353 tabsize = actual_cnt;
8469ba39 7354 dd->cspec->msix_entries = kzalloc(tabsize *
a778f3fd
MM		 7355 sizeof(struct qib_msix_entry), GFP_KERNEL);
7356 if (!dd->cspec->msix_entries) {
f931551b
RC		 7357 qib_dev_err(dd, "No memory for MSIx table\n");
7358 tabsize = 0;
7359 }
7360 for (i = 0; i < tabsize; i++)
a778f3fd 7361 dd->cspec->msix_entries[i].msix.entry = i;
f931551b
RC		 7362
7363 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries))
7fac3301
MM		 7364 qib_dev_err(dd,
7365 "Failed to setup PCIe or interrupts; continuing anyway\n");
f931551b
RC		 7366 /* may be less than we wanted, if not enough available */
7367 dd->cspec->num_msix_entries = tabsize;
7368
7369 /* setup interrupt handler */
7370 qib_setup_7322_interrupt(dd, 1);
7371
7372 /* clear diagctrl register, in case diags were running and crashed */
7373 qib_write_kreg(dd, kr_hwdiagctrl, 0);
8469ba39
MM		 7374#ifdef CONFIG_INFINIBAND_QIB_DCA
7375 if (!dca_add_requester(&pdev->dev)) {
7376 qib_devinfo(dd->pcidev, "DCA enabled\n");
7377 dd->flags |= QIB_DCA_ENABLED;
7378 qib_setup_dca(dd);
7379 }
7380#endif
f931551b
RC		 7381 goto bail;
7382
7383bail_cleanup:
7384 qib_pcie_ddcleanup(dd);
7385bail_free:
7386 qib_free_devdata(dd);
7387 dd = ERR_PTR(ret);
7388bail:
7389 return dd;
7390}
7391
7392/*
7393 * Set the table entry at the specified index from the table specifed.
7394 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first
7395 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR.
7396 * 'idx' below addresses the correct entry, while its 4 LSBs select the
7397 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table.
7398 */
7399#define DDS_ENT_AMP_LSB 14
7400#define DDS_ENT_MAIN_LSB 9
7401#define DDS_ENT_POST_LSB 5
7402#define DDS_ENT_PRE_XTRA_LSB 3
7403#define DDS_ENT_PRE_LSB 0
7404
7405/*
7406 * Set one entry in the TxDDS table for spec'd port
7407 * ridx picks one of the entries, while tp points
7408 * to the appropriate table entry.
7409 */
7410static void set_txdds(struct qib_pportdata *ppd, int ridx,
7411 const struct txdds_ent *tp)
7412{
7413 struct qib_devdata *dd = ppd->dd;
7414 u32 pack_ent;
7415 int regidx;
7416
7417 /* Get correct offset in chip-space, and in source table */
7418 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx;
7419 /*
7420 * We do not use qib_write_kreg_port() because it was intended
7421 * only for registers in the lower "port specific" pages.
7422 * So do index calculation by hand.
7423 */
7424 if (ppd->hw_pidx)
7425 regidx += (dd->palign / sizeof(u64));
7426
7427 pack_ent = tp->amp << DDS_ENT_AMP_LSB;
7428 pack_ent |= tp->main << DDS_ENT_MAIN_LSB;
7429 pack_ent |= tp->pre << DDS_ENT_PRE_LSB;
7430 pack_ent |= tp->post << DDS_ENT_POST_LSB;
7431 qib_write_kreg(dd, regidx, pack_ent);
7432 /* Prevent back-to-back writes by hitting scratch */
7433 qib_write_kreg(ppd->dd, kr_scratch, 0);
7434}
7435
7436static const struct vendor_txdds_ent vendor_txdds[] = {
7437 { /* Amphenol 1m 30awg NoEq */
7438 { 0x41, 0x50, 0x48 }, "584470002 ",
7439 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
7440 },
7441 { /* Amphenol 3m 28awg NoEq */
7442 { 0x41, 0x50, 0x48 }, "584470004 ",
7443 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
7444 },
7445 { /* Finisar 3m OM2 Optical */
7446 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
7447 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
7448 },
7449 { /* Finisar 30m OM2 Optical */
7450 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
7451 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
7452 },
7453 { /* Finisar Default OM2 Optical */
7454 { 0x00, 0x90, 0x65 }, NULL,
7455 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
7456 },
7457 { /* Gore 1m 30awg NoEq */
7458 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
7459 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
7460 },
7461 { /* Gore 2m 30awg NoEq */
7462 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
7463 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
7464 },
7465 { /* Gore 1m 28awg NoEq */
7466 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
7467 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
7468 },
7469 { /* Gore 3m 28awg NoEq */
7470 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
7471 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
7472 },
7473 { /* Gore 5m 24awg Eq */
7474 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
7475 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
7476 },
7477 { /* Gore 7m 24awg Eq */
7478 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
7479 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
7480 },
7481 { /* Gore 5m 26awg Eq */
7482 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
7483 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
7484 },
7485 { /* Gore 7m 26awg Eq */
7486 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
7487 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
7488 },
7489 { /* Intersil 12m 24awg Active */
7490 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
7491 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
7492 },
7493 { /* Intersil 10m 28awg Active */
7494 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
7495 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
7496 },
7497 { /* Intersil 7m 30awg Active */
7498 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
7499 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
7500 },
7501 { /* Intersil 5m 32awg Active */
7502 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
7503 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
7504 },
7505 { /* Intersil Default Active */
7506 { 0x00, 0x30, 0xB4 }, NULL,
7507 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
7508 },
7509 { /* Luxtera 20m Active Optical */
7510 { 0x00, 0x25, 0x63 }, NULL,
7511 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
7512 },
7513 { /* Molex 1M Cu loopback */
7514 { 0x00, 0x09, 0x3A }, "74763-0025 ",
7515 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
7516 },
7517 { /* Molex 2m 28awg NoEq */
7518 { 0x00, 0x09, 0x3A }, "74757-2201 ",
7519 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
7520 },
7521};
7522
7523static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = {
7524 /* amp, pre, main, post */
7525 { 2, 2, 15, 6 }, /* Loopback */
7526 { 0, 0, 0, 1 }, /* 2 dB */
7527 { 0, 0, 0, 2 }, /* 3 dB */
7528 { 0, 0, 0, 3 }, /* 4 dB */
7529 { 0, 0, 0, 4 }, /* 5 dB */
7530 { 0, 0, 0, 5 }, /* 6 dB */
7531 { 0, 0, 0, 6 }, /* 7 dB */
7532 { 0, 0, 0, 7 }, /* 8 dB */
7533 { 0, 0, 0, 8 }, /* 9 dB */
7534 { 0, 0, 0, 9 }, /* 10 dB */
7535 { 0, 0, 0, 10 }, /* 11 dB */
7536 { 0, 0, 0, 11 }, /* 12 dB */
7537 { 0, 0, 0, 12 }, /* 13 dB */
7538 { 0, 0, 0, 13 }, /* 14 dB */
7539 { 0, 0, 0, 14 }, /* 15 dB */
7540 { 0, 0, 0, 15 }, /* 16 dB */
7541};
7542
7543static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = {
7544 /* amp, pre, main, post */
7545 { 2, 2, 15, 6 }, /* Loopback */
7546 { 0, 0, 0, 8 }, /* 2 dB */
7547 { 0, 0, 0, 8 }, /* 3 dB */
7548 { 0, 0, 0, 9 }, /* 4 dB */
7549 { 0, 0, 0, 9 }, /* 5 dB */
7550 { 0, 0, 0, 10 }, /* 6 dB */
7551 { 0, 0, 0, 10 }, /* 7 dB */
7552 { 0, 0, 0, 11 }, /* 8 dB */
7553 { 0, 0, 0, 11 }, /* 9 dB */
7554 { 0, 0, 0, 12 }, /* 10 dB */
7555 { 0, 0, 0, 12 }, /* 11 dB */
7556 { 0, 0, 0, 13 }, /* 12 dB */
7557 { 0, 0, 0, 13 }, /* 13 dB */
7558 { 0, 0, 0, 14 }, /* 14 dB */
7559 { 0, 0, 0, 14 }, /* 15 dB */
7560 { 0, 0, 0, 15 }, /* 16 dB */
7561};
7562
7563static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = {
7564 /* amp, pre, main, post */
7565 { 2, 2, 15, 6 }, /* Loopback */
a77fcf89
RC		 7566 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */
7567 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */
f931551b
RC		 7568 { 0, 1, 0, 11 }, /* 4 dB */
7569 { 0, 1, 0, 13 }, /* 5 dB */
7570 { 0, 1, 0, 15 }, /* 6 dB */
7571 { 0, 1, 3, 15 }, /* 7 dB */
7572 { 0, 1, 7, 15 }, /* 8 dB */
7573 { 0, 1, 7, 15 }, /* 9 dB */
7574 { 0, 1, 8, 15 }, /* 10 dB */
7575 { 0, 1, 9, 15 }, /* 11 dB */
7576 { 0, 1, 10, 15 }, /* 12 dB */
7577 { 0, 2, 6, 15 }, /* 13 dB */
7578 { 0, 2, 7, 15 }, /* 14 dB */
7579 { 0, 2, 8, 15 }, /* 15 dB */
7580 { 0, 2, 9, 15 }, /* 16 dB */
7581};
7582
a77fcf89
RC		 7583/*
7584 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ.
7585 * These are mostly used for mez cards going through connectors
7586 * and backplane traces, but can be used to add other "unusual"
7587 * table values as well.
7588 */
7589static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
7590 /* amp, pre, main, post */
7591 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7592 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7593 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7594 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7c7a416e
RC		 7595 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */
7596 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */
22baa407
MH		 7597 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */
7598 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */
7599 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */
7600 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */
7601 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */
7602 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */
7603 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */
7604 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */
7605 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */
7606 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */
7607 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */
7608 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */
a77fcf89
RC		 7609};
7610
7611static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
7612 /* amp, pre, main, post */
7613 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7614 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7615 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7616 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7c7a416e
RC		 7617 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */
7618 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */
22baa407
MH		 7619 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */
7620 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */
7621 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */
7622 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */
7623 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */
7624 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */
7625 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */
7626 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */
7627 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */
7628 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */
7629 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */
7630 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */
a77fcf89
RC		 7631};
7632
7633static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
7634 /* amp, pre, main, post */
7635 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */
7636 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */
7637 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */
7638 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */
7c7a416e
RC		 7639 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */
7640 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */
22baa407
MH		 7641 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */
7642 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */
7643 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */
7644 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */
7645 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */
7646 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */
7647 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */
7648 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */
7649 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */
7650 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */
7651 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */
7652 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */
a77fcf89
RC		 7653};
7654
e706203c
MM		 7655static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = {
7656 /* amp, pre, main, post */
7657 { 0, 0, 0, 0 }, /* QME7342 mfg settings */
7658 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */
7659};
7660
f931551b
RC		 7661static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
7662 unsigned atten)
7663{
7664 /*
7665 * The attenuation table starts at 2dB for entry 1,
7666 * with entry 0 being the loopback entry.
7667 */
7668 if (atten <= 2)
7669 atten = 1;
7670 else if (atten > TXDDS_TABLE_SZ)
7671 atten = TXDDS_TABLE_SZ - 1;
7672 else
7673 atten--;
7674 return txdds + atten;
7675}
7676
7677/*
a77fcf89 7678 * if override is set, the module parameter txselect has a value
f931551b
RC		 7679 * for this specific port, so use it, rather than our normal mechanism.
7680 */
7681static void find_best_ent(struct qib_pportdata *ppd,
7682 const struct txdds_ent **sdr_dds,
7683 const struct txdds_ent **ddr_dds,
7684 const struct txdds_ent **qdr_dds, int override)
7685{
7686 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
7687 int idx;
7688
7689 /* Search table of known cables */
7690 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) {
7691 const struct vendor_txdds_ent *v = vendor_txdds + idx;
7692
7693 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) &&
7694 (!v->partnum ||
7695 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) {
7696 *sdr_dds = &v->sdr;
7697 *ddr_dds = &v->ddr;
7698 *qdr_dds = &v->qdr;
7699 return;
7700 }
7701 }
7702
dde05cbd
MH		 7703 /* Active cables don't have attenuation so we only set SERDES
7704 * settings to account for the attenuation of the board traces. */
f931551b
RC		 7705 if (!override && QSFP_IS_ACTIVE(qd->tech)) {
7706 *sdr_dds = txdds_sdr + ppd->dd->board_atten;
7707 *ddr_dds = txdds_ddr + ppd->dd->board_atten;
7708 *qdr_dds = txdds_qdr + ppd->dd->board_atten;
7709 return;
7710 }
7711
7712 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] ||
7713 qd->atten[1])) {
7714 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]);
7715 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]);
7716 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]);
7717 return;
a77fcf89 7718 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) {
f931551b
RC		 7719 /*
7720 * If we have no (or incomplete) data from the cable
a77fcf89
RC		 7721 * EEPROM, or no QSFP, or override is set, use the
7722 * module parameter value to index into the attentuation
7723 * table.
f931551b 7724 */
a77fcf89
RC		 7725 idx = ppd->cpspec->no_eep;
7726 *sdr_dds = &txdds_sdr[idx];
7727 *ddr_dds = &txdds_ddr[idx];
7728 *qdr_dds = &txdds_qdr[idx];
7729 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
7730 /* similar to above, but index into the "extra" table. */
7731 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ;
7732 *sdr_dds = &txdds_extra_sdr[idx];
7733 *ddr_dds = &txdds_extra_ddr[idx];
7734 *qdr_dds = &txdds_extra_qdr[idx];
e706203c
MM		 7735 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) &&
7736 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
7737 TXDDS_MFG_SZ)) {
7738 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
7fac3301 7739 pr_info("IB%u:%u use idx %u into txdds_mfg\n",
e706203c
MM		 7740 ppd->dd->unit, ppd->port, idx);
7741 *sdr_dds = &txdds_extra_mfg[idx];
7742 *ddr_dds = &txdds_extra_mfg[idx];
7743 *qdr_dds = &txdds_extra_mfg[idx];
a77fcf89
RC		 7744 } else {
7745 /* this shouldn't happen, it's range checked */
7746 *sdr_dds = txdds_sdr + qib_long_atten;
7747 *ddr_dds = txdds_ddr + qib_long_atten;
7748 *qdr_dds = txdds_qdr + qib_long_atten;
f931551b
RC		 7749 }
7750}
7751
7752static void init_txdds_table(struct qib_pportdata *ppd, int override)
7753{
7754 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7755 struct txdds_ent *dds;
7756 int idx;
7757 int single_ent = 0;
7758
a77fcf89
RC		 7759 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override);
7760
7761 /* for mez cards or override, use the selected value for all entries */
7762 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override)
f931551b 7763 single_ent = 1;
f931551b
RC		 7764
7765 /* Fill in the first entry with the best entry found. */
7766 set_txdds(ppd, 0, sdr_dds);
7767 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds);
7768 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds);
a77fcf89
RC		 7769 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
7770 QIBL_LINKACTIVE)) {
7771 dds = (struct txdds_ent *)(ppd->link_speed_active ==
7772 QIB_IB_QDR ? qdr_dds :
7773 (ppd->link_speed_active ==
7774 QIB_IB_DDR ? ddr_dds : sdr_dds));
7775 write_tx_serdes_param(ppd, dds);
7776 }
f931551b
RC		 7777
7778 /* Fill in the remaining entries with the default table values. */
7779 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) {
7780 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx);
7781 set_txdds(ppd, idx + TXDDS_TABLE_SZ,
7782 single_ent ? ddr_dds : txdds_ddr + idx);
7783 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ,
7784 single_ent ? qdr_dds : txdds_qdr + idx);
7785 }
7786}
7787
7788#define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7789#define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7790#define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7791#define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7792#define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7793#define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7794#define AHB_TRANS_TRIES 10
7795
7796/*
7797 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4,
7798 * 5=subsystem which is why most calls have "chan + chan >> 1"
7799 * for the channel argument.
7800 */
7801static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr,
7802 u32 data, u32 mask)
7803{
7804 u32 rd_data, wr_data, sz_mask;
7805 u64 trans, acc, prev_acc;
7806 u32 ret = 0xBAD0BAD;
7807 int tries;
7808
7809 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC);
7810 /* From this point on, make sure we return access */
7811 acc = (quad << 1) | 1;
7812 qib_write_kreg(dd, KR_AHB_ACC, acc);
7813
7814 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7815 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7816 if (trans & AHB_TRANS_RDY)
7817 break;
7818 }
7819 if (tries >= AHB_TRANS_TRIES) {
7820 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES);
7821 goto bail;
7822 }
7823
7824 /* If mask is not all 1s, we need to read, but different SerDes
7825 * entities have different sizes
7826 */
7827 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1;
7828 wr_data = data & mask & sz_mask;
7829 if ((~mask & sz_mask) != 0) {
7830 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7831 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7832
7833 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7834 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7835 if (trans & AHB_TRANS_RDY)
7836 break;
7837 }
7838 if (tries >= AHB_TRANS_TRIES) {
7839 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n",
7840 AHB_TRANS_TRIES);
7841 goto bail;
7842 }
7843 /* Re-read in case host split reads and read data first */
7844 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7845 rd_data = (uint32_t)(trans >> AHB_DATA_LSB);
7846 wr_data |= (rd_data & ~mask & sz_mask);
7847 }
7848
7849 /* If mask is not zero, we need to write. */
7850 if (mask & sz_mask) {
7851 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7852 trans |= ((uint64_t)wr_data << AHB_DATA_LSB);
7853 trans |= AHB_WR;
7854 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7855
7856 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7857 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7858 if (trans & AHB_TRANS_RDY)
7859 break;
7860 }
7861 if (tries >= AHB_TRANS_TRIES) {
7862 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n",
7863 AHB_TRANS_TRIES);
7864 goto bail;
7865 }
7866 }
7867 ret = wr_data;
7868bail:
7869 qib_write_kreg(dd, KR_AHB_ACC, prev_acc);
7870 return ret;
7871}
7872
7873static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7874 unsigned mask)
7875{
7876 struct qib_devdata *dd = ppd->dd;
7877 int chan;
7878 u32 rbc;
7879
7880 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7881 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7882 data, mask);
7883 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7884 addr, 0, 0);
7885 }
7886}
7887
a0a234d4
MM		 7888static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable)
7889{
7890 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl);
31264484
MH		 7891 u8 state = SYM_FIELD(data, IBSerdesCtrl_0, RXLOSEN);
7892
7893 if (enable && !state) {
7fac3301 7894 pr_info("IB%u:%u Turning LOS on\n",
31264484 7895 ppd->dd->unit, ppd->port);
a0a234d4 7896 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
31264484 7897 } else if (!enable && state) {
7fac3301 7898 pr_info("IB%u:%u Turning LOS off\n",
31264484 7899 ppd->dd->unit, ppd->port);
a0a234d4 7900 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
31264484 7901 }
a0a234d4
MM		 7902 qib_write_kreg_port(ppd, krp_serdesctrl, data);
7903}
7904
f931551b
RC		 7905static int serdes_7322_init(struct qib_pportdata *ppd)
7906{
a0a234d4 7907 int ret = 0;
da12c1f6 7908
a0a234d4
MM		 7909 if (ppd->dd->cspec->r1)
7910 ret = serdes_7322_init_old(ppd);
7911 else
7912 ret = serdes_7322_init_new(ppd);
7913 return ret;
7914}
7915
7916static int serdes_7322_init_old(struct qib_pportdata *ppd)
7917{
f931551b
RC		 7918 u32 le_val;
7919
7920 /*
7921 * Initialize the Tx DDS tables. Also done every QSFP event,
7922 * for adapters with QSFP
7923 */
7924 init_txdds_table(ppd, 0);
7925
a77fcf89
RC		 7926 /* ensure no tx overrides from earlier driver loads */
7927 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7928 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7929 reset_tx_deemphasis_override));
7930
f931551b
RC		 7931 /* Patch some SerDes defaults to "Better for IB" */
7932 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */
7933 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7934
7935 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7936 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7937 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */
7938 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6));
7939
7940 /* May be overridden in qsfp_7322_event */
7941 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7942 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7943
7944 /* enable LE1 adaptation for all but QME, which is disabled */
7945 le_val = IS_QME(ppd->dd) ? 0 : 1;
7946 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5));
7947
7948 /* Clear cmode-override, may be set from older driver */
7949 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7950
7951 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */
7952 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8));
7953
7954 /* setup LoS params; these are subsystem, so chan == 5 */
7955 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7956 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7957 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7958 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7959 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7960
7961 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7962 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7963 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7964 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7965 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7966
7967 /* LoS filter select enabled */
7968 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7969
7970 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7971 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7972 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7973 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7974
a0a234d4 7975 serdes_7322_los_enable(ppd, 1);
f931551b
RC		 7976
7977 /* rxbistena; set 0 to avoid effects of it switch later */
7978 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
7979
7980 /* Configure 4 DFE taps, and only they adapt */
7981 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0));
7982
7983 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7984 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7985 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7986
7987 /*
7988 * Set receive adaptation mode. SDR and DDR adaptation are
7989 * always on, and QDR is initially enabled; later disabled.
7990 */
7991 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7992 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7993 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7994 ppd->dd->cspec->r1 ?
7995 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7996 ppd->cpspec->qdr_dfe_on = 1;
7997
a77fcf89 7998 /* FLoop LOS gate: PPM filter enabled */
f931551b
RC		 7999 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
8000
8001 /* rx offset center enabled */
8002 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4);
8003
8004 if (!ppd->dd->cspec->r1) {
8005 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12);
8006 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8);
8007 }
8008
8009 /* Set the frequency loop bandwidth to 15 */
8010 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5));
8011
8012 return 0;
8013}
8014
a0a234d4
MM		 8015static int serdes_7322_init_new(struct qib_pportdata *ppd)
8016{
8482d5d1 8017 unsigned long tend;
a0a234d4
MM		 8018 u32 le_val, rxcaldone;
8019 int chan, chan_done = (1 << SERDES_CHANS) - 1;
8020
a0a234d4
MM		 8021 /* Clear cmode-override, may be set from older driver */
8022 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
8023
8024 /* ensure no tx overrides from earlier driver loads */
8025 qib_write_kreg_port(ppd, krp_tx_deemph_override,
8026 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8027 reset_tx_deemphasis_override));
8028
8029 /* START OF LSI SUGGESTED SERDES BRINGUP */
8030 /* Reset - Calibration Setup */
8031 /* Stop DFE adaptaion */
8032 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1));
8033 /* Disable LE1 */
8034 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5));
8035 /* Disable autoadapt for LE1 */
8036 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15));
8037 /* Disable LE2 */
8038 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6));
8039 /* Disable VGA */
8040 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
8041 /* Disable AFE Offset Cancel */
8042 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12));
8043 /* Disable Timing Loop */
8044 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3));
8045 /* Disable Frequency Loop */
8046 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4));
8047 /* Disable Baseline Wander Correction */
8048 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13));
8049 /* Disable RX Calibration */
8050 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
8051 /* Disable RX Offset Calibration */
8052 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4));
8053 /* Select BB CDR */
8054 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15));
8055 /* CDR Step Size */
8056 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8));
8057 /* Enable phase Calibration */
8058 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5));
8059 /* DFE Bandwidth [2:14-12] */
8060 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12));
8061 /* DFE Config (4 taps only) */
8062 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0));
8063 /* Gain Loop Bandwidth */
8064 if (!ppd->dd->cspec->r1) {
8065 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12));
8066 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8));
8067 } else {
8068 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11));
8069 }
8070 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */
8071 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */
8072 /* Data Rate Select [5:7-6] (leave as default) */
25985edc 8073 /* RX Parallel Word Width [3:10-8] (leave as default) */
a0a234d4
MM		 8074
8075 /* RX REST */
8076 /* Single- or Multi-channel reset */
8077 /* RX Analog reset */
8078 /* RX Digital reset */
8079 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13));
8080 msleep(20);
8081 /* RX Analog reset */
8082 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14));
8083 msleep(20);
8084 /* RX Digital reset */
8085 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13));
8086 msleep(20);
8087
8088 /* setup LoS params; these are subsystem, so chan == 5 */
8089 /* LoS filter threshold_count on, ch 0-3, set to 8 */
8090 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
8091 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
8092 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
8093 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
8094
8095 /* LoS filter threshold_count off, ch 0-3, set to 4 */
8096 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
8097 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
8098 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
8099 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
8100
8101 /* LoS filter select enabled */
8102 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
8103
8104 /* LoS target data: SDR=4, DDR=2, QDR=1 */
8105 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
8106 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
8107 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
8108
8109 /* Turn on LOS on initial SERDES init */
8110 serdes_7322_los_enable(ppd, 1);
8111 /* FLoop LOS gate: PPM filter enabled */
8112 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
8113
8114 /* RX LATCH CALIBRATION */
8115 /* Enable Eyefinder Phase Calibration latch */
8116 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0));
8117 /* Enable RX Offset Calibration latch */
8118 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4));
8119 msleep(20);
8120 /* Start Calibration */
8121 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10));
8482d5d1
MM		 8122 tend = jiffies + msecs_to_jiffies(500);
8123 while (chan_done && !time_is_before_jiffies(tend)) {
a0a234d4
MM		 8124 msleep(20);
8125 for (chan = 0; chan < SERDES_CHANS; ++chan) {
8126 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
8127 (chan + (chan >> 1)),
8128 25, 0, 0);
8129 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 &&
8130 (~chan_done & (1 << chan)) == 0)
8131 chan_done &= ~(1 << chan);
8132 }
8133 }
8134 if (chan_done) {
7fac3301 8135 pr_info("Serdes %d calibration not done after .5 sec: 0x%x\n",
a0a234d4
MM		 8136 IBSD(ppd->hw_pidx), chan_done);
8137 } else {
8138 for (chan = 0; chan < SERDES_CHANS; ++chan) {
8139 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
8140 (chan + (chan >> 1)),
8141 25, 0, 0);
8142 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0)
7fac3301
MM		 8143 pr_info("Serdes %d chan %d calibration failed\n",
8144 IBSD(ppd->hw_pidx), chan);
a0a234d4
MM		 8145 }
8146 }
8147
8148 /* Turn off Calibration */
8149 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
8150 msleep(20);
8151
8152 /* BRING RX UP */
8153 /* Set LE2 value (May be overridden in qsfp_7322_event) */
8154 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
8155 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
8156 /* Set LE2 Loop bandwidth */
8157 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5));
8158 /* Enable LE2 */
8159 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6));
8160 msleep(20);
8161 /* Enable H0 only */
8162 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1));
8163 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
8164 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
8165 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
8166 /* Enable VGA */
8167 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
8168 msleep(20);
8169 /* Set Frequency Loop Bandwidth */
f665acb3 8170 ibsd_wr_allchans(ppd, 2, (15 << 5), BMASK(8, 5));
a0a234d4
MM		 8171 /* Enable Frequency Loop */
8172 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4));
8173 /* Set Timing Loop Bandwidth */
8174 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
8175 /* Enable Timing Loop */
8176 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3));
8177 msleep(50);
8178 /* Enable DFE
8179 * Set receive adaptation mode. SDR and DDR adaptation are
8180 * always on, and QDR is initially enabled; later disabled.
8181 */
8182 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
8183 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
8184 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
8185 ppd->dd->cspec->r1 ?
8186 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
8187 ppd->cpspec->qdr_dfe_on = 1;
8188 /* Disable LE1 */
8189 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5));
8190 /* Disable auto adapt for LE1 */
8191 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15));
8192 msleep(20);
8193 /* Enable AFE Offset Cancel */
8194 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12));
8195 /* Enable Baseline Wander Correction */
8196 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13));
8197 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
8198 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
8199 /* VGA output common mode */
8200 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2));
8201
dde05cbd
MH		 8202 /*
8203 * Initialize the Tx DDS tables. Also done every QSFP event,
8204 * for adapters with QSFP
8205 */
8206 init_txdds_table(ppd, 0);
8207
a0a234d4
MM		 8208 return 0;
8209}
8210
f931551b
RC		 8211/* start adjust QMH serdes parameters */
8212
8213static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
8214{
8215 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8216 9, code << 9, 0x3f << 9);
8217}
8218
8219static void set_man_mode_h1(struct qib_pportdata *ppd, int chan,
8220 int enable, u32 tapenable)
8221{
8222 if (enable)
8223 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8224 1, 3 << 10, 0x1f << 10);
8225 else
8226 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8227 1, 0, 0x1f << 10);
8228}
8229
8230/* Set clock to 1, 0, 1, 0 */
8231static void clock_man(struct qib_pportdata *ppd, int chan)
8232{
8233 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8234 4, 0x4000, 0x4000);
8235 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8236 4, 0, 0x4000);
8237 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8238 4, 0x4000, 0x4000);
8239 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8240 4, 0, 0x4000);
8241}
8242
8243/*
8244 * write the current Tx serdes pre,post,main,amp settings into the serdes.
8245 * The caller must pass the settings appropriate for the current speed,
8246 * or not care if they are correct for the current speed.
8247 */
8248static void write_tx_serdes_param(struct qib_pportdata *ppd,
8249 struct txdds_ent *txdds)
8250{
8251 u64 deemph;
8252
8253 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override);
8254 /* field names for amp, main, post, pre, respectively */
8255 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
8256 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
8257 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
8258 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
a77fcf89
RC		 8259
8260 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8261 tx_override_deemphasis_select);
8262 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8263 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8264 txampcntl_d2a);
8265 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8266 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8267 txc0_ena);
8268 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8269 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8270 txcp1_ena);
8271 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8272 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
f931551b
RC		 8273 txcn1_ena);
8274 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph);
8275}
8276
8277/*
a77fcf89
RC		 8278 * Set the parameters for mez cards on link bounce, so they are
8279 * always exactly what was requested. Similar logic to init_txdds
8280 * but does just the serdes.
f931551b
RC		 8281 */
8282static void adj_tx_serdes(struct qib_pportdata *ppd)
8283{
a77fcf89
RC		 8284 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
8285 struct txdds_ent *dds;
f931551b 8286
a77fcf89
RC		 8287 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1);
8288 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ?
8289 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ?
8290 ddr_dds : sdr_dds));
8291 write_tx_serdes_param(ppd, dds);
f931551b
RC		 8292}
8293
8294/* set QDR forced value for H1, if needed */
8295static void force_h1(struct qib_pportdata *ppd)
8296{
8297 int chan;
8298
8299 ppd->cpspec->qdr_reforce = 0;
8300 if (!ppd->dd->cspec->r1)
8301 return;
8302
8303 for (chan = 0; chan < SERDES_CHANS; chan++) {
8304 set_man_mode_h1(ppd, chan, 1, 0);
8305 set_man_code(ppd, chan, ppd->cpspec->h1_val);
8306 clock_man(ppd, chan);
8307 set_man_mode_h1(ppd, chan, 0, 0);
8308 }
8309}
8310
f931551b
RC		 8311#define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
8312#define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
8313
8314#define R_OPCODE_LSB 3
8315#define R_OP_NOP 0
8316#define R_OP_SHIFT 2
8317#define R_OP_UPDATE 3
8318#define R_TDI_LSB 2
8319#define R_TDO_LSB 1
8320#define R_RDY 1
8321
8322static int qib_r_grab(struct qib_devdata *dd)
8323{
da12c1f6
MM		 8324 u64 val = SJA_EN;
8325
f931551b
RC		 8326 qib_write_kreg(dd, kr_r_access, val);
8327 qib_read_kreg32(dd, kr_scratch);
8328 return 0;
8329}
8330
8331/* qib_r_wait_for_rdy() not only waits for the ready bit, it
8332 * returns the current state of R_TDO
8333 */
8334static int qib_r_wait_for_rdy(struct qib_devdata *dd)
8335{
8336 u64 val;
8337 int timeout;
da12c1f6 8338
f931551b
RC		 8339 for (timeout = 0; timeout < 100 ; ++timeout) {
8340 val = qib_read_kreg32(dd, kr_r_access);
8341 if (val & R_RDY)
8342 return (val >> R_TDO_LSB) & 1;
8343 }
8344 return -1;
8345}
8346
8347static int qib_r_shift(struct qib_devdata *dd, int bisten,
8348 int len, u8 *inp, u8 *outp)
8349{
8350 u64 valbase, val;
8351 int ret, pos;
8352
8353 valbase = SJA_EN | (bisten << BISTEN_LSB) |
8354 (R_OP_SHIFT << R_OPCODE_LSB);
8355 ret = qib_r_wait_for_rdy(dd);
8356 if (ret < 0)
8357 goto bail;
8358 for (pos = 0; pos < len; ++pos) {
8359 val = valbase;
8360 if (outp) {
8361 outp[pos >> 3] &= ~(1 << (pos & 7));
8362 outp[pos >> 3] |= (ret << (pos & 7));
8363 }
8364 if (inp) {
8365 int tdi = inp[pos >> 3] >> (pos & 7);
da12c1f6 8366
f931551b
RC		 8367 val |= ((tdi & 1) << R_TDI_LSB);
8368 }
8369 qib_write_kreg(dd, kr_r_access, val);
8370 qib_read_kreg32(dd, kr_scratch);
8371 ret = qib_r_wait_for_rdy(dd);
8372 if (ret < 0)
8373 break;
8374 }
8375 /* Restore to NOP between operations. */
8376 val = SJA_EN | (bisten << BISTEN_LSB);
8377 qib_write_kreg(dd, kr_r_access, val);
8378 qib_read_kreg32(dd, kr_scratch);
8379 ret = qib_r_wait_for_rdy(dd);
8380
8381 if (ret >= 0)
8382 ret = pos;
8383bail:
8384 return ret;
8385}
8386
8387static int qib_r_update(struct qib_devdata *dd, int bisten)
8388{
8389 u64 val;
8390 int ret;
8391
8392 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
8393 ret = qib_r_wait_for_rdy(dd);
8394 if (ret >= 0) {
8395 qib_write_kreg(dd, kr_r_access, val);
8396 qib_read_kreg32(dd, kr_scratch);
8397 }
8398 return ret;
8399}
8400
8401#define BISTEN_PORT_SEL 15
8402#define LEN_PORT_SEL 625
8403#define BISTEN_AT 17
8404#define LEN_AT 156
8405#define BISTEN_ETM 16
8406#define LEN_ETM 632
8407
8408#define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
8409
8410/* these are common for all IB port use cases. */
8411static u8 reset_at[BIT2BYTE(LEN_AT)] = {
8412 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8413 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
8414};
8415static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = {
8416 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8417 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8418 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
8419 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
8420 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
8421 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
8422 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8423 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
8424};
8425static u8 at[BIT2BYTE(LEN_AT)] = {
8426 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
8427 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
8428};
8429
8430/* used for IB1 or IB2, only one in use */
8431static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = {
8432 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8433 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8434 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8435 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
8436 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8437 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
8438 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
8439 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
8440};
8441
8442/* used when both IB1 and IB2 are in use */
8443static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = {
8444 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8445 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
8446 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8447 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
8448 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
8449 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
8450 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
8451 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
8452};
8453
8454/* used when only IB1 is in use */
8455static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = {
8456 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
8457 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
8458 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8459 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8460 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
8461 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8462 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8463 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
8464};
8465
8466/* used when only IB2 is in use */
8467static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = {
8468 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
8469 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
8470 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
8471 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
8472 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
8473 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
8474 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
8475 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
8476};
8477
8478/* used when both IB1 and IB2 are in use */
8479static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = {
8480 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
8481 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
8482 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8483 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8484 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
8485 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
8486 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8487 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
8488};
8489
8490/*
8491 * Do setup to properly handle IB link recovery; if port is zero, we
8492 * are initializing to cover both ports; otherwise we are initializing
8493 * to cover a single port card, or the port has reached INIT and we may
8494 * need to switch coverage types.
8495 */
8496static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both)
8497{
8498 u8 *portsel, *etm;
8499 struct qib_devdata *dd = ppd->dd;
8500
8501 if (!ppd->dd->cspec->r1)
8502 return;
8503 if (!both) {
8504 dd->cspec->recovery_ports_initted++;
8505 ppd->cpspec->recovery_init = 1;
8506 }
8507 if (!both && dd->cspec->recovery_ports_initted == 1) {
8508 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2;
8509 etm = atetm_1port;
8510 } else {
8511 portsel = portsel_2port;
8512 etm = atetm_2port;
8513 }
8514
8515 if (qib_r_grab(dd) < 0 ||
8516 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 ||
8517 qib_r_update(dd, BISTEN_ETM) < 0 ||
8518 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 ||
8519 qib_r_update(dd, BISTEN_AT) < 0 ||
8520 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL,
8521 portsel, NULL) < 0 ||
8522 qib_r_update(dd, BISTEN_PORT_SEL) < 0 ||
8523 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 ||
8524 qib_r_update(dd, BISTEN_AT) < 0 ||
8525 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 ||
8526 qib_r_update(dd, BISTEN_ETM) < 0)
8527 qib_dev_err(dd, "Failed IB link recovery setup\n");
8528}
8529
8530static void check_7322_rxe_status(struct qib_pportdata *ppd)
8531{
8532 struct qib_devdata *dd = ppd->dd;
8533 u64 fmask;
8534
8535 if (dd->cspec->recovery_ports_initted != 1)
8536 return; /* rest doesn't apply to dualport */
8537 qib_write_kreg(dd, kr_control, dd->control |
8538 SYM_MASK(Control, FreezeMode));
8539 (void)qib_read_kreg64(dd, kr_scratch);
8540 udelay(3); /* ibcreset asserted 400ns, be sure that's over */
8541 fmask = qib_read_kreg64(dd, kr_act_fmask);
8542 if (!fmask) {
8543 /*
8544 * require a powercycle before we'll work again, and make
8545 * sure we get no more interrupts, and don't turn off
8546 * freeze.
8547 */
8548 ppd->dd->cspec->stay_in_freeze = 1;
8549 qib_7322_set_intr_state(ppd->dd, 0);
8550 qib_write_kreg(dd, kr_fmask, 0ULL);
8551 qib_dev_err(dd, "HCA unusable until powercycled\n");
8552 return; /* eventually reset */
8553 }
8554
8555 qib_write_kreg(ppd->dd, kr_hwerrclear,
8556 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
8557
8558 /* don't do the full clear_freeze(), not needed for this */
8559 qib_write_kreg(dd, kr_control, dd->control);
8560 qib_read_kreg32(dd, kr_scratch);
8561 /* take IBC out of reset */
8562 if (ppd->link_speed_supported) {
8563 ppd->cpspec->ibcctrl_a &=
8564 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
8565 qib_write_kreg_port(ppd, krp_ibcctrl_a,
8566 ppd->cpspec->ibcctrl_a);
8567 qib_read_kreg32(dd, kr_scratch);
8568 if (ppd->lflags & QIBL_IB_LINK_DISABLED)
8569 qib_set_ib_7322_lstate(ppd, 0,
8570 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
8571 }
8572}
Linux 6.x block layer and io_uring tree(s)