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RDMA/nes: Get rid of ring_doorbell parameter of nes_post_cqp_request()
[linux-block.git] / drivers / infiniband / hw / nes / nes.h
CommitLineData
3c2d774c
GS		 1/*
2 * Copyright (c) 2006 - 2008 NetEffect, Inc. All rights reserved.
3 * Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#ifndef __NES_H
35#define __NES_H
36
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/spinlock.h>
40#include <linux/kernel.h>
41#include <linux/delay.h>
42#include <linux/pci.h>
43#include <linux/dma-mapping.h>
44#include <linux/workqueue.h>
45#include <linux/slab.h>
3c2d774c
GS		 46#include <linux/version.h>
47#include <asm/io.h>
48#include <linux/crc32c.h>
49
50#include <rdma/ib_smi.h>
51#include <rdma/ib_verbs.h>
52#include <rdma/ib_pack.h>
53#include <rdma/rdma_cm.h>
54#include <rdma/iw_cm.h>
55
56#define NES_SEND_FIRST_WRITE
57
58#define QUEUE_DISCONNECTS
59
60#define DRV_BUILD "1"
61
62#define DRV_NAME "iw_nes"
63#define DRV_VERSION "1.0 KO Build " DRV_BUILD
64#define PFX DRV_NAME ": "
65
66/*
67 * NetEffect PCI vendor id and NE010 PCI device id.
68 */
69#ifndef PCI_VENDOR_ID_NETEFFECT /* not in pci.ids yet */
70#define PCI_VENDOR_ID_NETEFFECT 0x1678
71#define PCI_DEVICE_ID_NETEFFECT_NE020 0x0100
72#endif
73
74#define NE020_REV 4
75#define NE020_REV1 5
76
77#define BAR_0 0
78#define BAR_1 2
79
80#define RX_BUF_SIZE (1536 + 8)
81#define NES_REG0_SIZE (4 * 1024)
82#define NES_TX_TIMEOUT (6*HZ)
83#define NES_FIRST_QPN 64
84#define NES_SW_CONTEXT_ALIGN 1024
85
86#define NES_NIC_MAX_NICS 16
87#define NES_MAX_ARP_TABLE_SIZE 4096
88
89#define NES_NIC_CEQ_SIZE 8
90/* NICs will be on a separate CQ */
91#define NES_CCEQ_SIZE ((nesadapter->max_cq / nesadapter->port_count) - 32)
92
93#define NES_MAX_PORT_COUNT 4
94
95#define MAX_DPC_ITERATIONS 128
96
3c2d774c
GS		 97#define NES_DRV_OPT_ENABLE_MPA_VER_0 0x00000001
98#define NES_DRV_OPT_DISABLE_MPA_CRC 0x00000002
99#define NES_DRV_OPT_DISABLE_FIRST_WRITE 0x00000004
100#define NES_DRV_OPT_DISABLE_INTF 0x00000008
101#define NES_DRV_OPT_ENABLE_MSI 0x00000010
102#define NES_DRV_OPT_DUAL_LOGICAL_PORT 0x00000020
103#define NES_DRV_OPT_SUPRESS_OPTION_BC 0x00000040
104#define NES_DRV_OPT_NO_INLINE_DATA 0x00000080
105#define NES_DRV_OPT_DISABLE_INT_MOD 0x00000100
106#define NES_DRV_OPT_DISABLE_VIRT_WQ 0x00000200
107
108#define NES_AEQ_EVENT_TIMEOUT 2500
109#define NES_DISCONNECT_EVENT_TIMEOUT 2000
110
111/* debug levels */
112/* must match userspace */
113#define NES_DBG_HW 0x00000001
114#define NES_DBG_INIT 0x00000002
115#define NES_DBG_ISR 0x00000004
116#define NES_DBG_PHY 0x00000008
117#define NES_DBG_NETDEV 0x00000010
118#define NES_DBG_CM 0x00000020
119#define NES_DBG_CM1 0x00000040
120#define NES_DBG_NIC_RX 0x00000080
121#define NES_DBG_NIC_TX 0x00000100
122#define NES_DBG_CQP 0x00000200
123#define NES_DBG_MMAP 0x00000400
124#define NES_DBG_MR 0x00000800
125#define NES_DBG_PD 0x00001000
126#define NES_DBG_CQ 0x00002000
127#define NES_DBG_QP 0x00004000
128#define NES_DBG_MOD_QP 0x00008000
129#define NES_DBG_AEQ 0x00010000
130#define NES_DBG_IW_RX 0x00020000
131#define NES_DBG_IW_TX 0x00040000
132#define NES_DBG_SHUTDOWN 0x00080000
133#define NES_DBG_RSVD1 0x10000000
134#define NES_DBG_RSVD2 0x20000000
135#define NES_DBG_RSVD3 0x40000000
136#define NES_DBG_RSVD4 0x80000000
137#define NES_DBG_ALL 0xffffffff
138
139#ifdef CONFIG_INFINIBAND_NES_DEBUG
140#define nes_debug(level, fmt, args...) \
141 if (level & nes_debug_level) \
33718363 142 printk(KERN_ERR PFX "%s[%u]: " fmt, __func__, __LINE__, ##args)
3c2d774c
GS		 143
144#define assert(expr) \
145if (!(expr)) { \
146 printk(KERN_ERR PFX "Assertion failed! %s, %s, %s, line %d\n", \
33718363 147 #expr, __FILE__, __func__, __LINE__); \
3c2d774c
GS		 148}
149
150#define NES_EVENT_TIMEOUT 1200000
151#else
152#define nes_debug(level, fmt, args...)
153#define assert(expr) do {} while (0)
154
155#define NES_EVENT_TIMEOUT 100000
156#endif
157
158#include "nes_hw.h"
159#include "nes_verbs.h"
160#include "nes_context.h"
161#include "nes_user.h"
162#include "nes_cm.h"
163
164extern int max_mtu;
3c2d774c
GS		 165#define max_frame_len (max_mtu+ETH_HLEN)
166extern int interrupt_mod_interval;
167extern int nes_if_count;
168extern int mpa_version;
169extern int disable_mpa_crc;
170extern unsigned int send_first;
171extern unsigned int nes_drv_opt;
172extern unsigned int nes_debug_level;
173
174extern struct list_head nes_adapter_list;
3c2d774c
GS		 175
176extern atomic_t cm_connects;
177extern atomic_t cm_accepts;
178extern atomic_t cm_disconnects;
179extern atomic_t cm_closes;
180extern atomic_t cm_connecteds;
181extern atomic_t cm_connect_reqs;
182extern atomic_t cm_rejects;
183extern atomic_t mod_qp_timouts;
184extern atomic_t qps_created;
185extern atomic_t qps_destroyed;
186extern atomic_t sw_qps_destroyed;
187extern u32 mh_detected;
188extern u32 mh_pauses_sent;
189extern u32 cm_packets_sent;
190extern u32 cm_packets_bounced;
191extern u32 cm_packets_created;
192extern u32 cm_packets_received;
193extern u32 cm_packets_dropped;
194extern u32 cm_packets_retrans;
195extern u32 cm_listens_created;
196extern u32 cm_listens_destroyed;
197extern u32 cm_backlog_drops;
198extern atomic_t cm_loopbacks;
199extern atomic_t cm_nodes_created;
200extern atomic_t cm_nodes_destroyed;
201extern atomic_t cm_accel_dropped_pkts;
202extern atomic_t cm_resets_recvd;
203
3c2d774c
GS		 204extern u32 int_mod_timer_init;
205extern u32 int_mod_cq_depth_256;
206extern u32 int_mod_cq_depth_128;
207extern u32 int_mod_cq_depth_32;
208extern u32 int_mod_cq_depth_24;
209extern u32 int_mod_cq_depth_16;
210extern u32 int_mod_cq_depth_4;
211extern u32 int_mod_cq_depth_1;
212
3c2d774c
GS		 213struct nes_device {
214 struct nes_adapter *nesadapter;
215 void __iomem *regs;
216 void __iomem *index_reg;
217 struct pci_dev *pcidev;
218 struct net_device *netdev[NES_NIC_MAX_NICS];
219 u64 link_status_interrupts;
220 struct tasklet_struct dpc_tasklet;
221 spinlock_t indexed_regs_lock;
222 unsigned long csr_start;
223 unsigned long doorbell_region;
224 unsigned long doorbell_start;
225 unsigned long mac_tx_errors;
226 unsigned long mac_pause_frames_sent;
227 unsigned long mac_pause_frames_received;
228 unsigned long mac_rx_errors;
229 unsigned long mac_rx_crc_errors;
230 unsigned long mac_rx_symbol_err_frames;
231 unsigned long mac_rx_jabber_frames;
232 unsigned long mac_rx_oversized_frames;
233 unsigned long mac_rx_short_frames;
234 unsigned long port_rx_discards;
235 unsigned long port_tx_discards;
236 unsigned int mac_index;
237 unsigned int nes_stack_start;
238
239 /* Control Structures */
240 void *cqp_vbase;
241 dma_addr_t cqp_pbase;
242 u32 cqp_mem_size;
243 u8 ceq_index;
244 u8 nic_ceq_index;
245 struct nes_hw_cqp cqp;
246 struct nes_hw_cq ccq;
247 struct list_head cqp_avail_reqs;
248 struct list_head cqp_pending_reqs;
249 struct nes_cqp_request *nes_cqp_requests;
250
251 u32 int_req;
252 u32 int_stat;
253 u32 timer_int_req;
254 u32 timer_only_int_count;
255 u32 intf_int_req;
256 u32 last_mac_tx_pauses;
257 u32 last_used_chunks_tx;
258 struct list_head list;
259
260 u16 base_doorbell_index;
261 u16 currcq_count;
262 u16 deepcq_count;
263 u8 msi_enabled;
264 u8 netdev_count;
265 u8 napi_isr_ran;
266 u8 disable_rx_flow_control;
267 u8 disable_tx_flow_control;
268};
269
270
30da7cff
FL		 271static inline __le32 get_crc_value(struct nes_v4_quad *nes_quad)
272{
273 u32 crc_value;
274 crc_value = crc32c(~0, (void *)nes_quad, sizeof (struct nes_v4_quad));
275
276 /*
277 * With commit ef19454b ("[LIB] crc32c: Keep intermediate crc
278 * state in cpu order"), behavior of crc32c changes on
279 * big-endian platforms. Our algorithm expects the previous
280 * behavior; otherwise we have RDMA connection establishment
281 * issue on big-endian.
282 */
283 return cpu_to_le32(crc_value);
284}
285
3c2d774c
GS		 286static inline void
287set_wqe_64bit_value(__le32 *wqe_words, u32 index, u64 value)
288{
289 wqe_words[index] = cpu_to_le32((u32) ((unsigned long)value));
290 wqe_words[index + 1] = cpu_to_le32((u32)(upper_32_bits((unsigned long)value)));
291}
292
293static inline void
294set_wqe_32bit_value(__le32 *wqe_words, u32 index, u32 value)
295{
296 wqe_words[index] = cpu_to_le32(value);
297}
298
299static inline void
300nes_fill_init_cqp_wqe(struct nes_hw_cqp_wqe *cqp_wqe, struct nes_device *nesdev)
301{
302 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_COMP_CTX_LOW_IDX,
303 (u64)((unsigned long) &nesdev->cqp));
304 cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
305 cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
306 cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX] = 0;
307 cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_LEN_IDX] = 0;
308 cqp_wqe->wqe_words[NES_CQP_STAG_WQE_LEN_LOW_IDX] = 0;
309 cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_LOW_IDX] = 0;
310 cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_HIGH_IDX] = 0;
311}
312
313static inline void
314nes_fill_init_qp_wqe(struct nes_hw_qp_wqe *wqe, struct nes_qp *nesqp, u32 head)
315{
316 u32 value;
317 value = ((u32)((unsigned long) nesqp)) | head;
318 set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX,
319 (u32)(upper_32_bits((unsigned long)(nesqp))));
320 set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX, value);
321}
322
323/* Read from memory-mapped device */
324static inline u32 nes_read_indexed(struct nes_device *nesdev, u32 reg_index)
325{
326 unsigned long flags;
327 void __iomem *addr = nesdev->index_reg;
328 u32 value;
329
330 spin_lock_irqsave(&nesdev->indexed_regs_lock, flags);
331
332 writel(reg_index, addr);
333 value = readl((void __iomem *)addr + 4);
334
335 spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags);
336 return value;
337}
338
339static inline u32 nes_read32(const void __iomem *addr)
340{
341 return readl(addr);
342}
343
344static inline u16 nes_read16(const void __iomem *addr)
345{
346 return readw(addr);
347}
348
349static inline u8 nes_read8(const void __iomem *addr)
350{
351 return readb(addr);
352}
353
354/* Write to memory-mapped device */
355static inline void nes_write_indexed(struct nes_device *nesdev, u32 reg_index, u32 val)
356{
357 unsigned long flags;
358 void __iomem *addr = nesdev->index_reg;
359
360 spin_lock_irqsave(&nesdev->indexed_regs_lock, flags);
361
362 writel(reg_index, addr);
363 writel(val, (void __iomem *)addr + 4);
364
365 spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags);
366}
367
368static inline void nes_write32(void __iomem *addr, u32 val)
369{
370 writel(val, addr);
371}
372
373static inline void nes_write16(void __iomem *addr, u16 val)
374{
375 writew(val, addr);
376}
377
378static inline void nes_write8(void __iomem *addr, u8 val)
379{
380 writeb(val, addr);
381}
382
383
384
385static inline int nes_alloc_resource(struct nes_adapter *nesadapter,
386 unsigned long *resource_array, u32 max_resources,
387 u32 *req_resource_num, u32 *next)
388{
389 unsigned long flags;
390 u32 resource_num;
391
392 spin_lock_irqsave(&nesadapter->resource_lock, flags);
393
394 resource_num = find_next_zero_bit(resource_array, max_resources, *next);
395 if (resource_num >= max_resources) {
396 resource_num = find_first_zero_bit(resource_array, max_resources);
397 if (resource_num >= max_resources) {
33718363 398 printk(KERN_ERR PFX "%s: No available resourcess.\n", __func__);
3c2d774c
GS		 399 spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
400 return -EMFILE;
401 }
402 }
403 set_bit(resource_num, resource_array);
404 *next = resource_num+1;
405 if (*next == max_resources) {
406 *next = 0;
407 }
408 spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
409 *req_resource_num = resource_num;
410
411 return 0;
412}
413
414static inline int nes_is_resource_allocated(struct nes_adapter *nesadapter,
415 unsigned long *resource_array, u32 resource_num)
416{
417 unsigned long flags;
418 int bit_is_set;
419
420 spin_lock_irqsave(&nesadapter->resource_lock, flags);
421
422 bit_is_set = test_bit(resource_num, resource_array);
423 nes_debug(NES_DBG_HW, "resource_num %u is%s allocated.\n",
424 resource_num, (bit_is_set ? "": " not"));
425 spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
426
427 return bit_is_set;
428}
429
430static inline void nes_free_resource(struct nes_adapter *nesadapter,
431 unsigned long *resource_array, u32 resource_num)
432{
433 unsigned long flags;
434
435 spin_lock_irqsave(&nesadapter->resource_lock, flags);
436 clear_bit(resource_num, resource_array);
437 spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
438}
439
440static inline struct nes_vnic *to_nesvnic(struct ib_device *ibdev)
441{
442 return container_of(ibdev, struct nes_ib_device, ibdev)->nesvnic;
443}
444
445static inline struct nes_pd *to_nespd(struct ib_pd *ibpd)
446{
447 return container_of(ibpd, struct nes_pd, ibpd);
448}
449
450static inline struct nes_ucontext *to_nesucontext(struct ib_ucontext *ibucontext)
451{
452 return container_of(ibucontext, struct nes_ucontext, ibucontext);
453}
454
455static inline struct nes_mr *to_nesmr(struct ib_mr *ibmr)
456{
457 return container_of(ibmr, struct nes_mr, ibmr);
458}
459
460static inline struct nes_mr *to_nesmr_from_ibfmr(struct ib_fmr *ibfmr)
461{
462 return container_of(ibfmr, struct nes_mr, ibfmr);
463}
464
465static inline struct nes_mr *to_nesmw(struct ib_mw *ibmw)
466{
467 return container_of(ibmw, struct nes_mr, ibmw);
468}
469
470static inline struct nes_fmr *to_nesfmr(struct nes_mr *nesmr)
471{
472 return container_of(nesmr, struct nes_fmr, nesmr);
473}
474
475static inline struct nes_cq *to_nescq(struct ib_cq *ibcq)
476{
477 return container_of(ibcq, struct nes_cq, ibcq);
478}
479
480static inline struct nes_qp *to_nesqp(struct ib_qp *ibqp)
481{
482 return container_of(ibqp, struct nes_qp, ibqp);
483}
484
485
486
487/* nes.c */
488void nes_add_ref(struct ib_qp *);
489void nes_rem_ref(struct ib_qp *);
490struct ib_qp *nes_get_qp(struct ib_device *, int);
491
492
493/* nes_hw.c */
494struct nes_adapter *nes_init_adapter(struct nes_device *, u8);
495void nes_nic_init_timer_defaults(struct nes_device *, u8);
3c2d774c
GS		 496void nes_destroy_adapter(struct nes_adapter *);
497int nes_init_cqp(struct nes_device *);
498int nes_init_phy(struct nes_device *);
499int nes_init_nic_qp(struct nes_device *, struct net_device *);
500void nes_destroy_nic_qp(struct nes_vnic *);
501int nes_napi_isr(struct nes_device *);
502void nes_dpc(unsigned long);
3c2d774c 503void nes_nic_ce_handler(struct nes_device *, struct nes_hw_nic_cq *);
3c2d774c
GS		 504void nes_iwarp_ce_handler(struct nes_device *, struct nes_hw_cq *);
505int nes_destroy_cqp(struct nes_device *);
506int nes_nic_cm_xmit(struct sk_buff *, struct net_device *);
507
508/* nes_nic.c */
3c2d774c
GS		 509struct net_device *nes_netdev_init(struct nes_device *, void __iomem *);
510void nes_netdev_destroy(struct net_device *);
511int nes_nic_cm_xmit(struct sk_buff *, struct net_device *);
512
513/* nes_cm.c */
514void *nes_cm_create(struct net_device *);
515int nes_cm_recv(struct sk_buff *, struct net_device *);
516void nes_update_arp(unsigned char *, u32, u32, u16, u16);
517void nes_manage_arp_cache(struct net_device *, unsigned char *, u32, u32);
518void nes_sock_release(struct nes_qp *, unsigned long *);
3c2d774c
GS		 519void flush_wqes(struct nes_device *nesdev, struct nes_qp *, u32, u32);
520int nes_manage_apbvt(struct nes_vnic *, u32, u32, u32);
521int nes_cm_disconn(struct nes_qp *);
522void nes_cm_disconn_worker(void *);
523
524/* nes_verbs.c */
525int nes_hw_modify_qp(struct nes_device *, struct nes_qp *, u32, u32);
526int nes_modify_qp(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *);
527struct nes_ib_device *nes_init_ofa_device(struct net_device *);
528void nes_destroy_ofa_device(struct nes_ib_device *);
529int nes_register_ofa_device(struct nes_ib_device *);
3c2d774c
GS		 530
531/* nes_util.c */
532int nes_read_eeprom_values(struct nes_device *, struct nes_adapter *);
533void nes_write_1G_phy_reg(struct nes_device *, u8, u8, u16);
534void nes_read_1G_phy_reg(struct nes_device *, u8, u8, u16 *);
0e1de5d6
ES		 535void nes_write_10G_phy_reg(struct nes_device *, u16, u8, u16, u16);
536void nes_read_10G_phy_reg(struct nes_device *, u8, u8, u16);
3c2d774c 537struct nes_cqp_request *nes_get_cqp_request(struct nes_device *);
1ff66e8c
RD		 538void nes_free_cqp_request(struct nes_device *nesdev,
539 struct nes_cqp_request *cqp_request);
540void nes_put_cqp_request(struct nes_device *nesdev,
541 struct nes_cqp_request *cqp_request);
8294f297 542void nes_post_cqp_request(struct nes_device *, struct nes_cqp_request *);
3c2d774c
GS		 543int nes_arp_table(struct nes_device *, u32, u8 *, u32);
544void nes_mh_fix(unsigned long);
545void nes_clc(unsigned long);
546void nes_dump_mem(unsigned int, void *, int);
547u32 nes_crc32(u32, u32, u32, u32, u8 *, u32, u32, u32);
548
549#endif /* __NES_H */
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