[linux-block.git] / drivers / infiniband / hw / mthca / mthca_dev.h

/*
 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
 * Copyright (c) 2005 Cisco Systems.  All rights reserved.
 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
 */

#ifndef MTHCA_DEV_H
#define MTHCA_DEV_H

#include <linux/spinlock.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <asm/semaphore.h>

#include "mthca_provider.h"
#include "mthca_doorbell.h"

#define DRV_NAME	"ib_mthca"
#define PFX		DRV_NAME ": "
#define DRV_VERSION	"0.06"
#define DRV_RELDATE	"June 23, 2005"

enum {
	MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
	MTHCA_FLAG_SRQ        = 1 << 2,
	MTHCA_FLAG_MSI        = 1 << 3,
	MTHCA_FLAG_MSI_X      = 1 << 4,
	MTHCA_FLAG_NO_LAM     = 1 << 5,
	MTHCA_FLAG_FMR        = 1 << 6,
	MTHCA_FLAG_MEMFREE    = 1 << 7,
	MTHCA_FLAG_PCIE       = 1 << 8
};

enum {
	MTHCA_MAX_PORTS = 2
};

enum {
	MTHCA_BOARD_ID_LEN = 64
};

enum {
	MTHCA_EQ_CONTEXT_SIZE =  0x40,
	MTHCA_CQ_CONTEXT_SIZE =  0x40,
	MTHCA_QP_CONTEXT_SIZE = 0x200,
	MTHCA_RDB_ENTRY_SIZE  =  0x20,
	MTHCA_AV_SIZE         =  0x20,
	MTHCA_MGM_ENTRY_SIZE  =  0x40,

	/* Arbel FW gives us these, but we need them for Tavor */
	MTHCA_MPT_ENTRY_SIZE  =  0x40,
	MTHCA_MTT_SEG_SIZE    =  0x40,
};

enum {
	MTHCA_EQ_CMD,
	MTHCA_EQ_ASYNC,
	MTHCA_EQ_COMP,
	MTHCA_NUM_EQ
};

enum {
	MTHCA_OPCODE_NOP            = 0x00,
	MTHCA_OPCODE_RDMA_WRITE     = 0x08,
	MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
	MTHCA_OPCODE_SEND           = 0x0a,
	MTHCA_OPCODE_SEND_IMM       = 0x0b,
	MTHCA_OPCODE_RDMA_READ      = 0x10,
	MTHCA_OPCODE_ATOMIC_CS      = 0x11,
	MTHCA_OPCODE_ATOMIC_FA      = 0x12,
	MTHCA_OPCODE_BIND_MW        = 0x18,
	MTHCA_OPCODE_INVALID        = 0xff
};

struct mthca_cmd {
	struct pci_pool          *pool;
	int                       use_events;
	struct semaphore          hcr_sem;
	struct semaphore 	  poll_sem;
	struct semaphore 	  event_sem;
	int              	  max_cmds;
	spinlock_t                context_lock;
	int                       free_head;
	struct mthca_cmd_context *context;
	u16                       token_mask;
};

struct mthca_limits {
	int      num_ports;
	int      vl_cap;
	int      mtu_cap;
	int      gid_table_len;
	int      pkey_table_len;
	int      local_ca_ack_delay;
	int      num_uars;
	int      max_sg;
	int      num_qps;
	int      reserved_qps;
	int      num_srqs;
	int      reserved_srqs;
	int      num_eecs;
	int      reserved_eecs;
	int      num_cqs;
	int      reserved_cqs;
	int      num_eqs;
	int      reserved_eqs;
	int      num_mpts;
	int      num_mtt_segs;
	int      fmr_reserved_mtts;
	int      reserved_mtts;
	int      reserved_mrws;
	int      reserved_uars;
	int      num_mgms;
	int      num_amgms;
	int      reserved_mcgs;
	int      num_pds;
	int      reserved_pds;
	u8       port_width_cap;
};

struct mthca_alloc {
	u32            last;
	u32            top;
	u32            max;
	u32            mask;
	spinlock_t     lock;
	unsigned long *table;
};

struct mthca_array {
	struct {
		void    **page;
		int       used;
	} *page_list;
};

struct mthca_uar_table {
	struct mthca_alloc alloc;
	u64                uarc_base;
	int                uarc_size;
};

struct mthca_pd_table {
	struct mthca_alloc alloc;
};

struct mthca_buddy {
	unsigned long **bits;
	int             max_order;
	spinlock_t      lock;
};

struct mthca_mr_table {
	struct mthca_alloc      mpt_alloc;
	struct mthca_buddy      mtt_buddy;
	struct mthca_buddy     *fmr_mtt_buddy;
	u64                     mtt_base;
	u64                     mpt_base;
	struct mthca_icm_table *mtt_table;
	struct mthca_icm_table *mpt_table;
	struct {
		void __iomem   *mpt_base;
		void __iomem   *mtt_base;
		struct mthca_buddy mtt_buddy;
	} tavor_fmr;
};

struct mthca_eq_table {
	struct mthca_alloc alloc;
	void __iomem      *clr_int;
	u32                clr_mask;
	u32                arm_mask;
	struct mthca_eq    eq[MTHCA_NUM_EQ];
	u64                icm_virt;
	struct page       *icm_page;
	dma_addr_t         icm_dma;
	int                have_irq;
	u8                 inta_pin;
};

struct mthca_cq_table {
	struct mthca_alloc 	alloc;
	spinlock_t         	lock;
	struct mthca_array      cq;
	struct mthca_icm_table *table;
};

struct mthca_qp_table {
	struct mthca_alloc     	alloc;
	u32                    	rdb_base;
	int                    	rdb_shift;
	int                    	sqp_start;
	spinlock_t             	lock;
	struct mthca_array     	qp;
	struct mthca_icm_table *qp_table;
	struct mthca_icm_table *eqp_table;
	struct mthca_icm_table *rdb_table;
};

struct mthca_av_table {
	struct pci_pool   *pool;
	int                num_ddr_avs;
	u64                ddr_av_base;
	void __iomem      *av_map;
	struct mthca_alloc alloc;
};

struct mthca_mcg_table {
	struct semaphore   	sem;
	struct mthca_alloc 	alloc;
	struct mthca_icm_table *table;
};

struct mthca_dev {
	struct ib_device  ib_dev;
	struct pci_dev   *pdev;

	int          	 hca_type;
	unsigned long	 mthca_flags;
	unsigned long    device_cap_flags;

	u32              rev_id;
	char             board_id[MTHCA_BOARD_ID_LEN];

	/* firmware info */
	u64              fw_ver;
	union {
		struct {
			u64 fw_start;
			u64 fw_end;
		}        tavor;
		struct {
			u64 clr_int_base;
			u64 eq_arm_base;
			u64 eq_set_ci_base;
			struct mthca_icm *fw_icm;
			struct mthca_icm *aux_icm;
			u16 fw_pages;
		}        arbel;
	}                fw;

	u64              ddr_start;
	u64              ddr_end;

	MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
	struct semaphore cap_mask_mutex;

	void __iomem    *hcr;
	void __iomem    *kar;
	void __iomem    *clr_base;
	union {
		struct {
			void __iomem *ecr_base;
		} tavor;
		struct {
			void __iomem *eq_arm;
			void __iomem *eq_set_ci_base;
		} arbel;
	} eq_regs;

	struct mthca_cmd    cmd;
	struct mthca_limits limits;

	struct mthca_uar_table uar_table;
	struct mthca_pd_table  pd_table;
	struct mthca_mr_table  mr_table;
	struct mthca_eq_table  eq_table;
	struct mthca_cq_table  cq_table;
	struct mthca_qp_table  qp_table;
	struct mthca_av_table  av_table;
	struct mthca_mcg_table mcg_table;

	struct mthca_uar       driver_uar;
	struct mthca_db_table *db_tab;
	struct mthca_pd        driver_pd;
	struct mthca_mr        driver_mr;

	struct ib_mad_agent  *send_agent[MTHCA_MAX_PORTS][2];
	struct ib_ah         *sm_ah[MTHCA_MAX_PORTS];
	spinlock_t            sm_lock;
};

#define mthca_dbg(mdev, format, arg...) \
	dev_dbg(&mdev->pdev->dev, format, ## arg)
#define mthca_err(mdev, format, arg...) \
	dev_err(&mdev->pdev->dev, format, ## arg)
#define mthca_info(mdev, format, arg...) \
	dev_info(&mdev->pdev->dev, format, ## arg)
#define mthca_warn(mdev, format, arg...) \
	dev_warn(&mdev->pdev->dev, format, ## arg)

extern void __buggy_use_of_MTHCA_GET(void);
extern void __buggy_use_of_MTHCA_PUT(void);

#define MTHCA_GET(dest, source, offset)                               \
	do {                                                          \
		void *__p = (char *) (source) + (offset);             \
		switch (sizeof (dest)) {                              \
			case 1: (dest) = *(u8 *) __p;       break;    \
			case 2: (dest) = be16_to_cpup(__p); break;    \
			case 4: (dest) = be32_to_cpup(__p); break;    \
			case 8: (dest) = be64_to_cpup(__p); break;    \
			default: __buggy_use_of_MTHCA_GET();          \
		}                                                     \
	} while (0)

#define MTHCA_PUT(dest, source, offset)                               \
	do {                                                          \
		void *__d = ((char *) (dest) + (offset));	      \
		switch (sizeof(source)) {                             \
		case 1: *(u8 *) __d = (source);                break; \
		case 2:	*(__be16 *) __d = cpu_to_be16(source); break; \
		case 4:	*(__be32 *) __d = cpu_to_be32(source); break; \
		case 8:	*(__be64 *) __d = cpu_to_be64(source); break; \
		default: __buggy_use_of_MTHCA_PUT();		      \
		}                                                     \
	} while (0)

int mthca_reset(struct mthca_dev *mdev);

u32 mthca_alloc(struct mthca_alloc *alloc);
void mthca_free(struct mthca_alloc *alloc, u32 obj);
int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
		     u32 reserved);
void mthca_alloc_cleanup(struct mthca_alloc *alloc);
void *mthca_array_get(struct mthca_array *array, int index);
int mthca_array_set(struct mthca_array *array, int index, void *value);
void mthca_array_clear(struct mthca_array *array, int index);
int mthca_array_init(struct mthca_array *array, int nent);
void mthca_array_cleanup(struct mthca_array *array, int nent);

int mthca_init_uar_table(struct mthca_dev *dev);
int mthca_init_pd_table(struct mthca_dev *dev);
int mthca_init_mr_table(struct mthca_dev *dev);
int mthca_init_eq_table(struct mthca_dev *dev);
int mthca_init_cq_table(struct mthca_dev *dev);
int mthca_init_qp_table(struct mthca_dev *dev);
int mthca_init_av_table(struct mthca_dev *dev);
int mthca_init_mcg_table(struct mthca_dev *dev);

void mthca_cleanup_uar_table(struct mthca_dev *dev);
void mthca_cleanup_pd_table(struct mthca_dev *dev);
void mthca_cleanup_mr_table(struct mthca_dev *dev);
void mthca_cleanup_eq_table(struct mthca_dev *dev);
void mthca_cleanup_cq_table(struct mthca_dev *dev);
void mthca_cleanup_qp_table(struct mthca_dev *dev);
void mthca_cleanup_av_table(struct mthca_dev *dev);
void mthca_cleanup_mcg_table(struct mthca_dev *dev);

int mthca_register_device(struct mthca_dev *dev);
void mthca_unregister_device(struct mthca_dev *dev);

int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);

int mthca_pd_alloc(struct mthca_dev *dev, int privileged, struct mthca_pd *pd);
void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);

struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size);
void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt);
int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
		    int start_index, u64 *buffer_list, int list_len);
int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
		   u64 iova, u64 total_size, u32 access, struct mthca_mr *mr);
int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
			   u32 access, struct mthca_mr *mr);
int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
			u64 *buffer_list, int buffer_size_shift,
			int list_len, u64 iova, u64 total_size,
			u32 access, struct mthca_mr *mr);
void mthca_free_mr(struct mthca_dev *dev,  struct mthca_mr *mr);

int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
		    u32 access, struct mthca_fmr *fmr);
int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
			     int list_len, u64 iova);
void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
			     int list_len, u64 iova);
void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
int mthca_free_fmr(struct mthca_dev *dev,  struct mthca_fmr *fmr);

int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
void mthca_unmap_eq_icm(struct mthca_dev *dev);

int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
		  struct ib_wc *entry);
int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
int mthca_init_cq(struct mthca_dev *dev, int nent,
		  struct mthca_ucontext *ctx, u32 pdn,
		  struct mthca_cq *cq);
void mthca_free_cq(struct mthca_dev *dev,
		   struct mthca_cq *cq);
void mthca_cq_event(struct mthca_dev *dev, u32 cqn);
void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn);

void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
		    enum ib_event_type event_type);
int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask);
int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
			  struct ib_send_wr **bad_wr);
int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
			     struct ib_recv_wr **bad_wr);
int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
			  struct ib_send_wr **bad_wr);
int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
			     struct ib_recv_wr **bad_wr);
int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
		       int index, int *dbd, __be32 *new_wqe);
int mthca_alloc_qp(struct mthca_dev *dev,
		   struct mthca_pd *pd,
		   struct mthca_cq *send_cq,
		   struct mthca_cq *recv_cq,
		   enum ib_qp_type type,
		   enum ib_sig_type send_policy,
		   struct ib_qp_cap *cap,
		   struct mthca_qp *qp);
int mthca_alloc_sqp(struct mthca_dev *dev,
		    struct mthca_pd *pd,
		    struct mthca_cq *send_cq,
		    struct mthca_cq *recv_cq,
		    enum ib_sig_type send_policy,
		    struct ib_qp_cap *cap,
		    int qpn,
		    int port,
		    struct mthca_sqp *sqp);
void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
int mthca_create_ah(struct mthca_dev *dev,
		    struct mthca_pd *pd,
		    struct ib_ah_attr *ah_attr,
		    struct mthca_ah *ah);
int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
		  struct ib_ud_header *header);

int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);

int mthca_process_mad(struct ib_device *ibdev,
		      int mad_flags,
		      u8 port_num,
		      struct ib_wc *in_wc,
		      struct ib_grh *in_grh,
		      struct ib_mad *in_mad,
		      struct ib_mad *out_mad);
int mthca_create_agents(struct mthca_dev *dev);
void mthca_free_agents(struct mthca_dev *dev);

static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
{
	return container_of(ibdev, struct mthca_dev, ib_dev);
}

static inline int mthca_is_memfree(struct mthca_dev *dev)
{
	return dev->mthca_flags & MTHCA_FLAG_MEMFREE;
}

#endif /* MTHCA_DEV_H */
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
cd4e8fb4	3	* Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
99264c1e	4	* Copyright (c) 2005 Cisco Systems. All rights reserved.
2a1d9b7f RD	5	* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
2a1d9b7f RD	6	* Copyright (c) 2004 Voltaire, Inc. All rights reserved.
1da177e4 LT	7	*
	8	* This software is available to you under a choice of one of two
	9	* licenses. You may choose to be licensed under the terms of the GNU
	10	* General Public License (GPL) Version 2, available from the file
	11	* COPYING in the main directory of this source tree, or the
	12	* OpenIB.org BSD license below:
	13	*
	14	* Redistribution and use in source and binary forms, with or
	15	* without modification, are permitted provided that the following
	16	* conditions are met:
	17	*
	18	* - Redistributions of source code must retain the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer.
	21	*
	22	* - Redistributions in binary form must reproduce the above
	23	* copyright notice, this list of conditions and the following
	24	* disclaimer in the documentation and/or other materials
	25	* provided with the distribution.
	26	*
	27	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	28	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	29	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	30	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	31	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	32	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	33	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	34	* SOFTWARE.
	35	*
	36	* $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
	37	*/
	38
	39	#ifndef MTHCA_DEV_H
	40	#define MTHCA_DEV_H
	41
	42	#include <linux/spinlock.h>
	43	#include <linux/kernel.h>
	44	#include <linux/pci.h>
	45	#include <linux/dma-mapping.h>
	46	#include <asm/semaphore.h>
	47
	48	#include "mthca_provider.h"
	49	#include "mthca_doorbell.h"
	50
	51	#define DRV_NAME "ib_mthca"
	52	#define PFX DRV_NAME ": "
cae54bdf RD	53	#define DRV_VERSION "0.06"
cae54bdf RD	54	#define DRV_RELDATE "June 23, 2005"
1da177e4	55
1da177e4 LT	56	enum {
	57	MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
	58	MTHCA_FLAG_SRQ = 1 << 2,
	59	MTHCA_FLAG_MSI = 1 << 3,
	60	MTHCA_FLAG_MSI_X = 1 << 4,
e0f5fdca	61	MTHCA_FLAG_NO_LAM = 1 << 5,
68a3c212 RD	62	MTHCA_FLAG_FMR = 1 << 6,
	63	MTHCA_FLAG_MEMFREE = 1 << 7,
	64	MTHCA_FLAG_PCIE = 1 << 8
1da177e4 LT	65	};
	66
	67	enum {
	68	MTHCA_MAX_PORTS = 2
	69	};
	70
2e8b981c MT	71	enum {
	72	MTHCA_BOARD_ID_LEN = 64
	73	};
	74
1da177e4 LT	75	enum {
	76	MTHCA_EQ_CONTEXT_SIZE = 0x40,
	77	MTHCA_CQ_CONTEXT_SIZE = 0x40,
	78	MTHCA_QP_CONTEXT_SIZE = 0x200,
	79	MTHCA_RDB_ENTRY_SIZE = 0x20,
	80	MTHCA_AV_SIZE = 0x20,
	81	MTHCA_MGM_ENTRY_SIZE = 0x40,
	82
	83	/* Arbel FW gives us these, but we need them for Tavor */
	84	MTHCA_MPT_ENTRY_SIZE = 0x40,
	85	MTHCA_MTT_SEG_SIZE = 0x40,
	86	};
	87
	88	enum {
	89	MTHCA_EQ_CMD,
	90	MTHCA_EQ_ASYNC,
	91	MTHCA_EQ_COMP,
	92	MTHCA_NUM_EQ
	93	};
	94
2a4443a6 MT	95	enum {
	96	MTHCA_OPCODE_NOP = 0x00,
	97	MTHCA_OPCODE_RDMA_WRITE = 0x08,
	98	MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
	99	MTHCA_OPCODE_SEND = 0x0a,
	100	MTHCA_OPCODE_SEND_IMM = 0x0b,
	101	MTHCA_OPCODE_RDMA_READ = 0x10,
	102	MTHCA_OPCODE_ATOMIC_CS = 0x11,
	103	MTHCA_OPCODE_ATOMIC_FA = 0x12,
	104	MTHCA_OPCODE_BIND_MW = 0x18,
	105	MTHCA_OPCODE_INVALID = 0xff
	106	};
	107
1da177e4	108	struct mthca_cmd {
ed878458	109	struct pci_pool *pool;
1da177e4 LT	110	int use_events;
	111	struct semaphore hcr_sem;
	112	struct semaphore poll_sem;
	113	struct semaphore event_sem;
	114	int max_cmds;
	115	spinlock_t context_lock;
	116	int free_head;
	117	struct mthca_cmd_context *context;
	118	u16 token_mask;
	119	};
	120
	121	struct mthca_limits {
	122	int num_ports;
	123	int vl_cap;
	124	int mtu_cap;
	125	int gid_table_len;
	126	int pkey_table_len;
	127	int local_ca_ack_delay;
	128	int num_uars;
	129	int max_sg;
	130	int num_qps;
	131	int reserved_qps;
	132	int num_srqs;
	133	int reserved_srqs;
	134	int num_eecs;
	135	int reserved_eecs;
	136	int num_cqs;
	137	int reserved_cqs;
	138	int num_eqs;
	139	int reserved_eqs;
	140	int num_mpts;
	141	int num_mtt_segs;
e0f5fdca	142	int fmr_reserved_mtts;
1da177e4 LT	143	int reserved_mtts;
	144	int reserved_mrws;
	145	int reserved_uars;
	146	int num_mgms;
	147	int num_amgms;
	148	int reserved_mcgs;
	149	int num_pds;
	150	int reserved_pds;
da6561c2	151	u8 port_width_cap;
1da177e4 LT	152	};
	153
	154	struct mthca_alloc {
	155	u32 last;
	156	u32 top;
	157	u32 max;
	158	u32 mask;
	159	spinlock_t lock;
	160	unsigned long *table;
	161	};
	162
	163	struct mthca_array {
	164	struct {
	165	void **page;
	166	int used;
	167	} *page_list;
	168	};
	169
	170	struct mthca_uar_table {
	171	struct mthca_alloc alloc;
	172	u64 uarc_base;
	173	int uarc_size;
	174	};
	175
	176	struct mthca_pd_table {
	177	struct mthca_alloc alloc;
	178	};
	179
9095e208 MT	180	struct mthca_buddy {
	181	unsigned long **bits;
	182	int max_order;
	183	spinlock_t lock;
	184	};
	185
1da177e4 LT	186	struct mthca_mr_table {
1da177e4 LT	187	struct mthca_alloc mpt_alloc;
e0f5fdca MT	188	struct mthca_buddy mtt_buddy;
e0f5fdca MT	189	struct mthca_buddy *fmr_mtt_buddy;
1da177e4	190	u64 mtt_base;
e0f5fdca	191	u64 mpt_base;
1da177e4 LT	192	struct mthca_icm_table *mtt_table;
1da177e4 LT	193	struct mthca_icm_table *mpt_table;
e0f5fdca MT	194	struct {
	195	void __iomem *mpt_base;
	196	void __iomem *mtt_base;
	197	struct mthca_buddy mtt_buddy;
	198	} tavor_fmr;
1da177e4 LT	199	};
	200
	201	struct mthca_eq_table {
	202	struct mthca_alloc alloc;
	203	void __iomem *clr_int;
	204	u32 clr_mask;
	205	u32 arm_mask;
	206	struct mthca_eq eq[MTHCA_NUM_EQ];
	207	u64 icm_virt;
	208	struct page *icm_page;
	209	dma_addr_t icm_dma;
	210	int have_irq;
	211	u8 inta_pin;
	212	};
	213
	214	struct mthca_cq_table {
	215	struct mthca_alloc alloc;
	216	spinlock_t lock;
	217	struct mthca_array cq;
	218	struct mthca_icm_table *table;
	219	};
	220
	221	struct mthca_qp_table {
	222	struct mthca_alloc alloc;
	223	u32 rdb_base;
	224	int rdb_shift;
	225	int sqp_start;
	226	spinlock_t lock;
	227	struct mthca_array qp;
	228	struct mthca_icm_table *qp_table;
	229	struct mthca_icm_table *eqp_table;
08aeb14e	230	struct mthca_icm_table *rdb_table;
1da177e4 LT	231	};
	232
	233	struct mthca_av_table {
	234	struct pci_pool *pool;
	235	int num_ddr_avs;
	236	u64 ddr_av_base;
	237	void __iomem *av_map;
	238	struct mthca_alloc alloc;
	239	};
	240
	241	struct mthca_mcg_table {
	242	struct semaphore sem;
	243	struct mthca_alloc alloc;
	244	struct mthca_icm_table *table;
	245	};
	246
	247	struct mthca_dev {
	248	struct ib_device ib_dev;
	249	struct pci_dev *pdev;
	250
	251	int hca_type;
	252	unsigned long mthca_flags;
	253	unsigned long device_cap_flags;
	254
	255	u32 rev_id;
2e8b981c	256	char board_id[MTHCA_BOARD_ID_LEN];
1da177e4 LT	257
	258	/* firmware info */
	259	u64 fw_ver;
	260	union {
	261	struct {
	262	u64 fw_start;
	263	u64 fw_end;
	264	} tavor;
	265	struct {
	266	u64 clr_int_base;
	267	u64 eq_arm_base;
	268	u64 eq_set_ci_base;
	269	struct mthca_icm *fw_icm;
	270	struct mthca_icm *aux_icm;
	271	u16 fw_pages;
	272	} arbel;
	273	} fw;
	274
	275	u64 ddr_start;
	276	u64 ddr_end;
	277
	278	MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
	279	struct semaphore cap_mask_mutex;
	280
	281	void __iomem *hcr;
	282	void __iomem *kar;
	283	void __iomem *clr_base;
	284	union {
	285	struct {
	286	void __iomem *ecr_base;
	287	} tavor;
	288	struct {
	289	void __iomem *eq_arm;
	290	void __iomem *eq_set_ci_base;
	291	} arbel;
	292	} eq_regs;
	293
	294	struct mthca_cmd cmd;
	295	struct mthca_limits limits;
	296
	297	struct mthca_uar_table uar_table;
	298	struct mthca_pd_table pd_table;
	299	struct mthca_mr_table mr_table;
	300	struct mthca_eq_table eq_table;
	301	struct mthca_cq_table cq_table;
	302	struct mthca_qp_table qp_table;
	303	struct mthca_av_table av_table;
	304	struct mthca_mcg_table mcg_table;
	305
	306	struct mthca_uar driver_uar;
	307	struct mthca_db_table *db_tab;
	308	struct mthca_pd driver_pd;
	309	struct mthca_mr driver_mr;
	310
	311	struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
	312	struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
	313	spinlock_t sm_lock;
	314	};
	315
	316	#define mthca_dbg(mdev, format, arg...) \
	317	dev_dbg(&mdev->pdev->dev, format, ## arg)
	318	#define mthca_err(mdev, format, arg...) \
	319	dev_err(&mdev->pdev->dev, format, ## arg)
	320	#define mthca_info(mdev, format, arg...) \
321	dev_info(&mdev->pdev->dev, format, ## arg)
322	#define mthca_warn(mdev, format, arg...) \
323	dev_warn(&mdev->pdev->dev, format, ## arg)
324
325	extern void __buggy_use_of_MTHCA_GET(void);
326	extern void __buggy_use_of_MTHCA_PUT(void);
327
328	#define MTHCA_GET(dest, source, offset) \
329	do { \
330	void __p = (char ) (source) + (offset); \
331	switch (sizeof (dest)) { \
332	case 1: (dest) = (u8 ) __p; break; \
333	case 2: (dest) = be16_to_cpup(__p); break; \
334	case 4: (dest) = be32_to_cpup(__p); break; \
335	case 8: (dest) = be64_to_cpup(__p); break; \
336	default: __buggy_use_of_MTHCA_GET(); \
337	} \
338	} while (0)
339
340	#define MTHCA_PUT(dest, source, offset) \
341	do { \
97f52eb4	342	void __d = ((char ) (dest) + (offset)); \
1da177e4	343	switch (sizeof(source)) { \
97f52eb4 SH	344	case 1: (u8 ) __d = (source); break; \
	345	case 2: (__be16 ) __d = cpu_to_be16(source); break; \
	346	case 4: (__be32 ) __d = cpu_to_be32(source); break; \
	347	case 8: (__be64 ) __d = cpu_to_be64(source); break; \
	348	default: __buggy_use_of_MTHCA_PUT(); \
1da177e4 LT	349	} \
	350	} while (0)
	351
	352	int mthca_reset(struct mthca_dev *mdev);
	353
	354	u32 mthca_alloc(struct mthca_alloc *alloc);
	355	void mthca_free(struct mthca_alloc *alloc, u32 obj);
	356	int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
	357	u32 reserved);
	358	void mthca_alloc_cleanup(struct mthca_alloc *alloc);
	359	void mthca_array_get(struct mthca_array array, int index);
	360	int mthca_array_set(struct mthca_array array, int index, void value);
	361	void mthca_array_clear(struct mthca_array *array, int index);
	362	int mthca_array_init(struct mthca_array *array, int nent);
	363	void mthca_array_cleanup(struct mthca_array *array, int nent);
	364
	365	int mthca_init_uar_table(struct mthca_dev *dev);
	366	int mthca_init_pd_table(struct mthca_dev *dev);
	367	int mthca_init_mr_table(struct mthca_dev *dev);
	368	int mthca_init_eq_table(struct mthca_dev *dev);
	369	int mthca_init_cq_table(struct mthca_dev *dev);
	370	int mthca_init_qp_table(struct mthca_dev *dev);
	371	int mthca_init_av_table(struct mthca_dev *dev);
	372	int mthca_init_mcg_table(struct mthca_dev *dev);
	373
	374	void mthca_cleanup_uar_table(struct mthca_dev *dev);
	375	void mthca_cleanup_pd_table(struct mthca_dev *dev);
	376	void mthca_cleanup_mr_table(struct mthca_dev *dev);
	377	void mthca_cleanup_eq_table(struct mthca_dev *dev);
	378	void mthca_cleanup_cq_table(struct mthca_dev *dev);
	379	void mthca_cleanup_qp_table(struct mthca_dev *dev);
	380	void mthca_cleanup_av_table(struct mthca_dev *dev);
	381	void mthca_cleanup_mcg_table(struct mthca_dev *dev);
	382
	383	int mthca_register_device(struct mthca_dev *dev);
	384	void mthca_unregister_device(struct mthca_dev *dev);
	385
	386	int mthca_uar_alloc(struct mthca_dev dev, struct mthca_uar uar);
	387	void mthca_uar_free(struct mthca_dev dev, struct mthca_uar uar);
	388
99264c1e	389	int mthca_pd_alloc(struct mthca_dev dev, int privileged, struct mthca_pd pd);
1da177e4 LT	390	void mthca_pd_free(struct mthca_dev dev, struct mthca_pd pd);
1da177e4 LT	391
d56d6f95 RD	392	struct mthca_mtt mthca_alloc_mtt(struct mthca_dev dev, int size);
	393	void mthca_free_mtt(struct mthca_dev dev, struct mthca_mtt mtt);
	394	int mthca_write_mtt(struct mthca_dev dev, struct mthca_mtt mtt,
	395	int start_index, u64 *buffer_list, int list_len);
	396	int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
	397	u64 iova, u64 total_size, u32 access, struct mthca_mr *mr);
1da177e4 LT	398	int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
	399	u32 access, struct mthca_mr *mr);
	400	int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
	401	u64 *buffer_list, int buffer_size_shift,
	402	int list_len, u64 iova, u64 total_size,
	403	u32 access, struct mthca_mr *mr);
e0f5fdca MT	404	void mthca_free_mr(struct mthca_dev dev, struct mthca_mr mr);
	405
	406	int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
	407	u32 access, struct mthca_fmr *fmr);
	408	int mthca_tavor_map_phys_fmr(struct ib_fmr ibfmr, u64 page_list,
	409	int list_len, u64 iova);
	410	void mthca_tavor_fmr_unmap(struct mthca_dev dev, struct mthca_fmr fmr);
	411	int mthca_arbel_map_phys_fmr(struct ib_fmr ibfmr, u64 page_list,
	412	int list_len, u64 iova);
	413	void mthca_arbel_fmr_unmap(struct mthca_dev dev, struct mthca_fmr fmr);
	414	int mthca_free_fmr(struct mthca_dev dev, struct mthca_fmr fmr);
1da177e4 LT	415
	416	int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
	417	void mthca_unmap_eq_icm(struct mthca_dev *dev);
	418
	419	int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
	420	struct ib_wc *entry);
	421	int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
	422	int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
	423	int mthca_init_cq(struct mthca_dev *dev, int nent,
74c2174e	424	struct mthca_ucontext *ctx, u32 pdn,
1da177e4 LT	425	struct mthca_cq *cq);
	426	void mthca_free_cq(struct mthca_dev *dev,
	427	struct mthca_cq *cq);
	428	void mthca_cq_event(struct mthca_dev *dev, u32 cqn);
	429	void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn);
	430
	431	void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
	432	enum ib_event_type event_type);
	433	int mthca_modify_qp(struct ib_qp ibqp, struct ib_qp_attr attr, int attr_mask);
	434	int mthca_tavor_post_send(struct ib_qp ibqp, struct ib_send_wr wr,
	435	struct ib_send_wr **bad_wr);
	436	int mthca_tavor_post_receive(struct ib_qp ibqp, struct ib_recv_wr wr,
	437	struct ib_recv_wr **bad_wr);
	438	int mthca_arbel_post_send(struct ib_qp ibqp, struct ib_send_wr wr,
	439	struct ib_send_wr **bad_wr);
	440	int mthca_arbel_post_receive(struct ib_qp ibqp, struct ib_recv_wr wr,
	441	struct ib_recv_wr **bad_wr);
	442	int mthca_free_err_wqe(struct mthca_dev dev, struct mthca_qp qp, int is_send,
97f52eb4	443	int index, int dbd, __be32 new_wqe);
1da177e4 LT	444	int mthca_alloc_qp(struct mthca_dev *dev,
	445	struct mthca_pd *pd,
	446	struct mthca_cq *send_cq,
	447	struct mthca_cq *recv_cq,
	448	enum ib_qp_type type,
	449	enum ib_sig_type send_policy,
80c8ec2c	450	struct ib_qp_cap *cap,
1da177e4 LT	451	struct mthca_qp *qp);
	452	int mthca_alloc_sqp(struct mthca_dev *dev,
	453	struct mthca_pd *pd,
	454	struct mthca_cq *send_cq,
	455	struct mthca_cq *recv_cq,
	456	enum ib_sig_type send_policy,
80c8ec2c	457	struct ib_qp_cap *cap,
1da177e4 LT	458	int qpn,
	459	int port,
	460	struct mthca_sqp *sqp);
	461	void mthca_free_qp(struct mthca_dev dev, struct mthca_qp qp);
	462	int mthca_create_ah(struct mthca_dev *dev,
	463	struct mthca_pd *pd,
	464	struct ib_ah_attr *ah_attr,
	465	struct mthca_ah *ah);
	466	int mthca_destroy_ah(struct mthca_dev dev, struct mthca_ah ah);
	467	int mthca_read_ah(struct mthca_dev dev, struct mthca_ah ah,
	468	struct ib_ud_header *header);
	469
	470	int mthca_multicast_attach(struct ib_qp ibqp, union ib_gid gid, u16 lid);
	471	int mthca_multicast_detach(struct ib_qp ibqp, union ib_gid gid, u16 lid);
	472
	473	int mthca_process_mad(struct ib_device *ibdev,
	474	int mad_flags,
	475	u8 port_num,
	476	struct ib_wc *in_wc,
	477	struct ib_grh *in_grh,
	478	struct ib_mad *in_mad,
	479	struct ib_mad *out_mad);
	480	int mthca_create_agents(struct mthca_dev *dev);
	481	void mthca_free_agents(struct mthca_dev *dev);
	482
	483	static inline struct mthca_dev to_mdev(struct ib_device ibdev)
	484	{
	485	return container_of(ibdev, struct mthca_dev, ib_dev);
	486	}
	487
d10ddbf6 RD	488	static inline int mthca_is_memfree(struct mthca_dev *dev)
d10ddbf6 RD	489	{
68a3c212	490	return dev->mthca_flags & MTHCA_FLAG_MEMFREE;
d10ddbf6 RD	491	}
d10ddbf6 RD	492
1da177e4	493	#endif /* MTHCA_DEV_H */