[linux-block.git] / drivers / infiniband / hw / mthca / mthca_dev.h

/*
 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
 */

#ifndef MTHCA_DEV_H
#define MTHCA_DEV_H

#include <linux/spinlock.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <asm/semaphore.h>

#include "mthca_provider.h"
#include "mthca_doorbell.h"

#define DRV_NAME	"ib_mthca"
#define PFX		DRV_NAME ": "
#define DRV_VERSION	"0.06-pre"
#define DRV_RELDATE	"November 8, 2004"

/* Types of supported HCA */
enum {
	TAVOR,			/* MT23108                        */
	ARBEL_COMPAT,		/* MT25208 in Tavor compat mode   */
	ARBEL_NATIVE		/* MT25208 with extended features */
};

enum {
	MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
	MTHCA_FLAG_SRQ        = 1 << 2,
	MTHCA_FLAG_MSI        = 1 << 3,
	MTHCA_FLAG_MSI_X      = 1 << 4,
	MTHCA_FLAG_NO_LAM     = 1 << 5,
	MTHCA_FLAG_FMR        = 1 << 6
};

enum {
	MTHCA_MAX_PORTS = 2
};

enum {
	MTHCA_EQ_CONTEXT_SIZE =  0x40,
	MTHCA_CQ_CONTEXT_SIZE =  0x40,
	MTHCA_QP_CONTEXT_SIZE = 0x200,
	MTHCA_RDB_ENTRY_SIZE  =  0x20,
	MTHCA_AV_SIZE         =  0x20,
	MTHCA_MGM_ENTRY_SIZE  =  0x40,

	/* Arbel FW gives us these, but we need them for Tavor */
	MTHCA_MPT_ENTRY_SIZE  =  0x40,
	MTHCA_MTT_SEG_SIZE    =  0x40,
};

enum {
	MTHCA_EQ_CMD,
	MTHCA_EQ_ASYNC,
	MTHCA_EQ_COMP,
	MTHCA_NUM_EQ
};

enum {
	MTHCA_OPCODE_NOP            = 0x00,
	MTHCA_OPCODE_RDMA_WRITE     = 0x08,
	MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
	MTHCA_OPCODE_SEND           = 0x0a,
	MTHCA_OPCODE_SEND_IMM       = 0x0b,
	MTHCA_OPCODE_RDMA_READ      = 0x10,
	MTHCA_OPCODE_ATOMIC_CS      = 0x11,
	MTHCA_OPCODE_ATOMIC_FA      = 0x12,
	MTHCA_OPCODE_BIND_MW        = 0x18,
	MTHCA_OPCODE_INVALID        = 0xff
};

struct mthca_cmd {
	int                       use_events;
	struct semaphore          hcr_sem;
	struct semaphore 	  poll_sem;
	struct semaphore 	  event_sem;
	int              	  max_cmds;
	spinlock_t                context_lock;
	int                       free_head;
	struct mthca_cmd_context *context;
	u16                       token_mask;
};

struct mthca_limits {
	int      num_ports;
	int      vl_cap;
	int      mtu_cap;
	int      gid_table_len;
	int      pkey_table_len;
	int      local_ca_ack_delay;
	int      num_uars;
	int      max_sg;
	int      num_qps;
	int      reserved_qps;
	int      num_srqs;
	int      reserved_srqs;
	int      num_eecs;
	int      reserved_eecs;
	int      num_cqs;
	int      reserved_cqs;
	int      num_eqs;
	int      reserved_eqs;
	int      num_mpts;
	int      num_mtt_segs;
	int      fmr_reserved_mtts;
	int      reserved_mtts;
	int      reserved_mrws;
	int      reserved_uars;
	int      num_mgms;
	int      num_amgms;
	int      reserved_mcgs;
	int      num_pds;
	int      reserved_pds;
};

struct mthca_alloc {
	u32            last;
	u32            top;
	u32            max;
	u32            mask;
	spinlock_t     lock;
	unsigned long *table;
};

struct mthca_array {
	struct {
		void    **page;
		int       used;
	} *page_list;
};

struct mthca_uar_table {
	struct mthca_alloc alloc;
	u64                uarc_base;
	int                uarc_size;
};

struct mthca_pd_table {
	struct mthca_alloc alloc;
};

struct mthca_buddy {
	unsigned long **bits;
	int             max_order;
	spinlock_t      lock;
};

struct mthca_mr_table {
	struct mthca_alloc      mpt_alloc;
	struct mthca_buddy      mtt_buddy;
	struct mthca_buddy     *fmr_mtt_buddy;
	u64                     mtt_base;
	u64                     mpt_base;
	struct mthca_icm_table *mtt_table;
	struct mthca_icm_table *mpt_table;
	struct {
		void __iomem   *mpt_base;
		void __iomem   *mtt_base;
		struct mthca_buddy mtt_buddy;
	} tavor_fmr;
};

struct mthca_eq_table {
	struct mthca_alloc alloc;
	void __iomem      *clr_int;
	u32                clr_mask;
	u32                arm_mask;
	struct mthca_eq    eq[MTHCA_NUM_EQ];
	u64                icm_virt;
	struct page       *icm_page;
	dma_addr_t         icm_dma;
	int                have_irq;
	u8                 inta_pin;
};

struct mthca_cq_table {
	struct mthca_alloc 	alloc;
	spinlock_t         	lock;
	struct mthca_array      cq;
	struct mthca_icm_table *table;
};

struct mthca_qp_table {
	struct mthca_alloc     	alloc;
	u32                    	rdb_base;
	int                    	rdb_shift;
	int                    	sqp_start;
	spinlock_t             	lock;
	struct mthca_array     	qp;
	struct mthca_icm_table *qp_table;
	struct mthca_icm_table *eqp_table;
};

struct mthca_av_table {
	struct pci_pool   *pool;
	int                num_ddr_avs;
	u64                ddr_av_base;
	void __iomem      *av_map;
	struct mthca_alloc alloc;
};

struct mthca_mcg_table {
	struct semaphore   	sem;
	struct mthca_alloc 	alloc;
	struct mthca_icm_table *table;
};

struct mthca_dev {
	struct ib_device  ib_dev;
	struct pci_dev   *pdev;

	int          	 hca_type;
	unsigned long	 mthca_flags;
	unsigned long    device_cap_flags;

	u32              rev_id;

	/* firmware info */
	u64              fw_ver;
	union {
		struct {
			u64 fw_start;
			u64 fw_end;
		}        tavor;
		struct {
			u64 clr_int_base;
			u64 eq_arm_base;
			u64 eq_set_ci_base;
			struct mthca_icm *fw_icm;
			struct mthca_icm *aux_icm;
			u16 fw_pages;
		}        arbel;
	}                fw;

	u64              ddr_start;
	u64              ddr_end;

	MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
	struct semaphore cap_mask_mutex;

	void __iomem    *hcr;
	void __iomem    *kar;
	void __iomem    *clr_base;
	union {
		struct {
			void __iomem *ecr_base;
		} tavor;
		struct {
			void __iomem *eq_arm;
			void __iomem *eq_set_ci_base;
		} arbel;
	} eq_regs;

	struct mthca_cmd    cmd;
	struct mthca_limits limits;

	struct mthca_uar_table uar_table;
	struct mthca_pd_table  pd_table;
	struct mthca_mr_table  mr_table;
	struct mthca_eq_table  eq_table;
	struct mthca_cq_table  cq_table;
	struct mthca_qp_table  qp_table;
	struct mthca_av_table  av_table;
	struct mthca_mcg_table mcg_table;

	struct mthca_uar       driver_uar;
	struct mthca_db_table *db_tab;
	struct mthca_pd        driver_pd;
	struct mthca_mr        driver_mr;

	struct ib_mad_agent  *send_agent[MTHCA_MAX_PORTS][2];
	struct ib_ah         *sm_ah[MTHCA_MAX_PORTS];
	spinlock_t            sm_lock;
};

#define mthca_dbg(mdev, format, arg...) \
	dev_dbg(&mdev->pdev->dev, format, ## arg)
#define mthca_err(mdev, format, arg...) \
	dev_err(&mdev->pdev->dev, format, ## arg)
#define mthca_info(mdev, format, arg...) \
	dev_info(&mdev->pdev->dev, format, ## arg)
#define mthca_warn(mdev, format, arg...) \
	dev_warn(&mdev->pdev->dev, format, ## arg)

extern void __buggy_use_of_MTHCA_GET(void);
extern void __buggy_use_of_MTHCA_PUT(void);

#define MTHCA_GET(dest, source, offset)                               \
	do {                                                          \
		void *__p = (char *) (source) + (offset);             \
		switch (sizeof (dest)) {                              \
			case 1: (dest) = *(u8 *) __p;       break;    \
			case 2: (dest) = be16_to_cpup(__p); break;    \
			case 4: (dest) = be32_to_cpup(__p); break;    \
			case 8: (dest) = be64_to_cpup(__p); break;    \
			default: __buggy_use_of_MTHCA_GET();          \
		}                                                     \
	} while (0)

#define MTHCA_PUT(dest, source, offset)                               \
	do {                                                          \
		__typeof__(source) *__p =                             \
			(__typeof__(source) *) ((char *) (dest) + (offset)); \
		switch (sizeof(source)) {                             \
			case 1: *__p = (source);            break;    \
			case 2: *__p = cpu_to_be16(source); break;    \
			case 4: *__p = cpu_to_be32(source); break;    \
			case 8: *__p = cpu_to_be64(source); break;    \
			default: __buggy_use_of_MTHCA_PUT();          \
		}                                                     \
	} while (0)

int mthca_reset(struct mthca_dev *mdev);

u32 mthca_alloc(struct mthca_alloc *alloc);
void mthca_free(struct mthca_alloc *alloc, u32 obj);
int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
		     u32 reserved);
void mthca_alloc_cleanup(struct mthca_alloc *alloc);
void *mthca_array_get(struct mthca_array *array, int index);
int mthca_array_set(struct mthca_array *array, int index, void *value);
void mthca_array_clear(struct mthca_array *array, int index);
int mthca_array_init(struct mthca_array *array, int nent);
void mthca_array_cleanup(struct mthca_array *array, int nent);

int mthca_init_uar_table(struct mthca_dev *dev);
int mthca_init_pd_table(struct mthca_dev *dev);
int mthca_init_mr_table(struct mthca_dev *dev);
int mthca_init_eq_table(struct mthca_dev *dev);
int mthca_init_cq_table(struct mthca_dev *dev);
int mthca_init_qp_table(struct mthca_dev *dev);
int mthca_init_av_table(struct mthca_dev *dev);
int mthca_init_mcg_table(struct mthca_dev *dev);

void mthca_cleanup_uar_table(struct mthca_dev *dev);
void mthca_cleanup_pd_table(struct mthca_dev *dev);
void mthca_cleanup_mr_table(struct mthca_dev *dev);
void mthca_cleanup_eq_table(struct mthca_dev *dev);
void mthca_cleanup_cq_table(struct mthca_dev *dev);
void mthca_cleanup_qp_table(struct mthca_dev *dev);
void mthca_cleanup_av_table(struct mthca_dev *dev);
void mthca_cleanup_mcg_table(struct mthca_dev *dev);

int mthca_register_device(struct mthca_dev *dev);
void mthca_unregister_device(struct mthca_dev *dev);

int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);

int mthca_pd_alloc(struct mthca_dev *dev, struct mthca_pd *pd);
void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);

int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
			   u32 access, struct mthca_mr *mr);
int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
			u64 *buffer_list, int buffer_size_shift,
			int list_len, u64 iova, u64 total_size,
			u32 access, struct mthca_mr *mr);
void mthca_free_mr(struct mthca_dev *dev,  struct mthca_mr *mr);

int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
		    u32 access, struct mthca_fmr *fmr);
int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
			     int list_len, u64 iova);
void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
			     int list_len, u64 iova);
void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
int mthca_free_fmr(struct mthca_dev *dev,  struct mthca_fmr *fmr);

int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
void mthca_unmap_eq_icm(struct mthca_dev *dev);

int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
		  struct ib_wc *entry);
int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
int mthca_init_cq(struct mthca_dev *dev, int nent,
		  struct mthca_cq *cq);
void mthca_free_cq(struct mthca_dev *dev,
		   struct mthca_cq *cq);
void mthca_cq_event(struct mthca_dev *dev, u32 cqn);
void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn);

void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
		    enum ib_event_type event_type);
int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask);
int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
			  struct ib_send_wr **bad_wr);
int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
			     struct ib_recv_wr **bad_wr);
int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
			  struct ib_send_wr **bad_wr);
int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
			     struct ib_recv_wr **bad_wr);
int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
		       int index, int *dbd, u32 *new_wqe);
int mthca_alloc_qp(struct mthca_dev *dev,
		   struct mthca_pd *pd,
		   struct mthca_cq *send_cq,
		   struct mthca_cq *recv_cq,
		   enum ib_qp_type type,
		   enum ib_sig_type send_policy,
		   struct mthca_qp *qp);
int mthca_alloc_sqp(struct mthca_dev *dev,
		    struct mthca_pd *pd,
		    struct mthca_cq *send_cq,
		    struct mthca_cq *recv_cq,
		    enum ib_sig_type send_policy,
		    int qpn,
		    int port,
		    struct mthca_sqp *sqp);
void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
int mthca_create_ah(struct mthca_dev *dev,
		    struct mthca_pd *pd,
		    struct ib_ah_attr *ah_attr,
		    struct mthca_ah *ah);
int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
		  struct ib_ud_header *header);

int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);

int mthca_process_mad(struct ib_device *ibdev,
		      int mad_flags,
		      u8 port_num,
		      struct ib_wc *in_wc,
		      struct ib_grh *in_grh,
		      struct ib_mad *in_mad,
		      struct ib_mad *out_mad);
int mthca_create_agents(struct mthca_dev *dev);
void mthca_free_agents(struct mthca_dev *dev);

static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
{
	return container_of(ibdev, struct mthca_dev, ib_dev);
}

static inline int mthca_is_memfree(struct mthca_dev *dev)
{
	return dev->hca_type == ARBEL_NATIVE;
}

#endif /* MTHCA_DEV_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*
	32	* $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
	33	*/
	34
	35	#ifndef MTHCA_DEV_H
	36	#define MTHCA_DEV_H
	37
	38	#include <linux/spinlock.h>
	39	#include <linux/kernel.h>
	40	#include <linux/pci.h>
	41	#include <linux/dma-mapping.h>
	42	#include <asm/semaphore.h>
	43
	44	#include "mthca_provider.h"
	45	#include "mthca_doorbell.h"
	46
	47	#define DRV_NAME "ib_mthca"
	48	#define PFX DRV_NAME ": "
	49	#define DRV_VERSION "0.06-pre"
	50	#define DRV_RELDATE "November 8, 2004"
	51
	52	/* Types of supported HCA */
	53	enum {
	54	TAVOR, /* MT23108 */
	55	ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
	56	ARBEL_NATIVE /* MT25208 with extended features */
	57	};
	58
	59	enum {
	60	MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
	61	MTHCA_FLAG_SRQ = 1 << 2,
	62	MTHCA_FLAG_MSI = 1 << 3,
	63	MTHCA_FLAG_MSI_X = 1 << 4,
e0f5fdca MT	64	MTHCA_FLAG_NO_LAM = 1 << 5,
e0f5fdca MT	65	MTHCA_FLAG_FMR = 1 << 6
1da177e4 LT	66	};
	67
	68	enum {
	69	MTHCA_MAX_PORTS = 2
	70	};
	71
	72	enum {
	73	MTHCA_EQ_CONTEXT_SIZE = 0x40,
	74	MTHCA_CQ_CONTEXT_SIZE = 0x40,
	75	MTHCA_QP_CONTEXT_SIZE = 0x200,
	76	MTHCA_RDB_ENTRY_SIZE = 0x20,
	77	MTHCA_AV_SIZE = 0x20,
	78	MTHCA_MGM_ENTRY_SIZE = 0x40,
	79
	80	/* Arbel FW gives us these, but we need them for Tavor */
	81	MTHCA_MPT_ENTRY_SIZE = 0x40,
	82	MTHCA_MTT_SEG_SIZE = 0x40,
	83	};
	84
	85	enum {
	86	MTHCA_EQ_CMD,
	87	MTHCA_EQ_ASYNC,
	88	MTHCA_EQ_COMP,
	89	MTHCA_NUM_EQ
	90	};
	91
2a4443a6 MT	92	enum {
	93	MTHCA_OPCODE_NOP = 0x00,
	94	MTHCA_OPCODE_RDMA_WRITE = 0x08,
	95	MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
	96	MTHCA_OPCODE_SEND = 0x0a,
	97	MTHCA_OPCODE_SEND_IMM = 0x0b,
	98	MTHCA_OPCODE_RDMA_READ = 0x10,
	99	MTHCA_OPCODE_ATOMIC_CS = 0x11,
	100	MTHCA_OPCODE_ATOMIC_FA = 0x12,
	101	MTHCA_OPCODE_BIND_MW = 0x18,
	102	MTHCA_OPCODE_INVALID = 0xff
	103	};
	104
1da177e4 LT	105	struct mthca_cmd {
	106	int use_events;
	107	struct semaphore hcr_sem;
	108	struct semaphore poll_sem;
	109	struct semaphore event_sem;
	110	int max_cmds;
	111	spinlock_t context_lock;
	112	int free_head;
	113	struct mthca_cmd_context *context;
	114	u16 token_mask;
	115	};
	116
	117	struct mthca_limits {
	118	int num_ports;
	119	int vl_cap;
	120	int mtu_cap;
	121	int gid_table_len;
	122	int pkey_table_len;
	123	int local_ca_ack_delay;
	124	int num_uars;
	125	int max_sg;
	126	int num_qps;
	127	int reserved_qps;
	128	int num_srqs;
	129	int reserved_srqs;
	130	int num_eecs;
	131	int reserved_eecs;
	132	int num_cqs;
	133	int reserved_cqs;
	134	int num_eqs;
	135	int reserved_eqs;
	136	int num_mpts;
	137	int num_mtt_segs;
e0f5fdca	138	int fmr_reserved_mtts;
1da177e4 LT	139	int reserved_mtts;
	140	int reserved_mrws;
	141	int reserved_uars;
	142	int num_mgms;
	143	int num_amgms;
	144	int reserved_mcgs;
	145	int num_pds;
	146	int reserved_pds;
	147	};
	148
	149	struct mthca_alloc {
	150	u32 last;
	151	u32 top;
	152	u32 max;
	153	u32 mask;
	154	spinlock_t lock;
	155	unsigned long *table;
	156	};
	157
	158	struct mthca_array {
	159	struct {
	160	void **page;
	161	int used;
	162	} *page_list;
	163	};
	164
	165	struct mthca_uar_table {
	166	struct mthca_alloc alloc;
	167	u64 uarc_base;
	168	int uarc_size;
	169	};
	170
	171	struct mthca_pd_table {
	172	struct mthca_alloc alloc;
	173	};
	174
9095e208 MT	175	struct mthca_buddy {
	176	unsigned long **bits;
	177	int max_order;
	178	spinlock_t lock;
	179	};
	180
1da177e4 LT	181	struct mthca_mr_table {
1da177e4 LT	182	struct mthca_alloc mpt_alloc;
e0f5fdca MT	183	struct mthca_buddy mtt_buddy;
e0f5fdca MT	184	struct mthca_buddy *fmr_mtt_buddy;
1da177e4	185	u64 mtt_base;
e0f5fdca	186	u64 mpt_base;
1da177e4 LT	187	struct mthca_icm_table *mtt_table;
1da177e4 LT	188	struct mthca_icm_table *mpt_table;
e0f5fdca MT	189	struct {
	190	void __iomem *mpt_base;
	191	void __iomem *mtt_base;
	192	struct mthca_buddy mtt_buddy;
	193	} tavor_fmr;
1da177e4 LT	194	};
	195
	196	struct mthca_eq_table {
	197	struct mthca_alloc alloc;
	198	void __iomem *clr_int;
	199	u32 clr_mask;
	200	u32 arm_mask;
	201	struct mthca_eq eq[MTHCA_NUM_EQ];
	202	u64 icm_virt;
	203	struct page *icm_page;
	204	dma_addr_t icm_dma;
	205	int have_irq;
	206	u8 inta_pin;
	207	};
	208
	209	struct mthca_cq_table {
	210	struct mthca_alloc alloc;
	211	spinlock_t lock;
	212	struct mthca_array cq;
	213	struct mthca_icm_table *table;
	214	};
	215
	216	struct mthca_qp_table {
	217	struct mthca_alloc alloc;
	218	u32 rdb_base;
	219	int rdb_shift;
	220	int sqp_start;
	221	spinlock_t lock;
	222	struct mthca_array qp;
	223	struct mthca_icm_table *qp_table;
	224	struct mthca_icm_table *eqp_table;
	225	};
	226
	227	struct mthca_av_table {
	228	struct pci_pool *pool;
	229	int num_ddr_avs;
	230	u64 ddr_av_base;
	231	void __iomem *av_map;
	232	struct mthca_alloc alloc;
	233	};
	234
	235	struct mthca_mcg_table {
	236	struct semaphore sem;
	237	struct mthca_alloc alloc;
	238	struct mthca_icm_table *table;
	239	};
	240
	241	struct mthca_dev {
	242	struct ib_device ib_dev;
	243	struct pci_dev *pdev;
	244
	245	int hca_type;
	246	unsigned long mthca_flags;
	247	unsigned long device_cap_flags;
	248
	249	u32 rev_id;
	250
	251	/* firmware info */
	252	u64 fw_ver;
	253	union {
	254	struct {
	255	u64 fw_start;
	256	u64 fw_end;
	257	} tavor;
258	struct {
259	u64 clr_int_base;
260	u64 eq_arm_base;
261	u64 eq_set_ci_base;
262	struct mthca_icm *fw_icm;
263	struct mthca_icm *aux_icm;
264	u16 fw_pages;
265	} arbel;
266	} fw;
267
268	u64 ddr_start;
269	u64 ddr_end;
270
271	MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
272	struct semaphore cap_mask_mutex;
273
274	void __iomem *hcr;
275	void __iomem *kar;
276	void __iomem *clr_base;
277	union {
278	struct {
279	void __iomem *ecr_base;
280	} tavor;
281	struct {
282	void __iomem *eq_arm;
283	void __iomem *eq_set_ci_base;
284	} arbel;
285	} eq_regs;
286
287	struct mthca_cmd cmd;
288	struct mthca_limits limits;
289
290	struct mthca_uar_table uar_table;
291	struct mthca_pd_table pd_table;
292	struct mthca_mr_table mr_table;
293	struct mthca_eq_table eq_table;
294	struct mthca_cq_table cq_table;
295	struct mthca_qp_table qp_table;
296	struct mthca_av_table av_table;
297	struct mthca_mcg_table mcg_table;
298
299	struct mthca_uar driver_uar;
300	struct mthca_db_table *db_tab;
301	struct mthca_pd driver_pd;
302	struct mthca_mr driver_mr;
303
304	struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
305	struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
306	spinlock_t sm_lock;
307	};
308
309	#define mthca_dbg(mdev, format, arg...) \
310	dev_dbg(&mdev->pdev->dev, format, ## arg)
311	#define mthca_err(mdev, format, arg...) \
312	dev_err(&mdev->pdev->dev, format, ## arg)
313	#define mthca_info(mdev, format, arg...) \
314	dev_info(&mdev->pdev->dev, format, ## arg)
315	#define mthca_warn(mdev, format, arg...) \
316	dev_warn(&mdev->pdev->dev, format, ## arg)
317
318	extern void __buggy_use_of_MTHCA_GET(void);
319	extern void __buggy_use_of_MTHCA_PUT(void);
320
321	#define MTHCA_GET(dest, source, offset) \
322	do { \
323	void __p = (char ) (source) + (offset); \
324	switch (sizeof (dest)) { \
325	case 1: (dest) = (u8 ) __p; break; \
326	case 2: (dest) = be16_to_cpup(__p); break; \
327	case 4: (dest) = be32_to_cpup(__p); break; \
328	case 8: (dest) = be64_to_cpup(__p); break; \
329	default: __buggy_use_of_MTHCA_GET(); \
330	} \
331	} while (0)
332
333	#define MTHCA_PUT(dest, source, offset) \
334	do { \
335	__typeof__(source) *__p = \
336	(__typeof__(source) ) ((char ) (dest) + (offset)); \
337	switch (sizeof(source)) { \
338	case 1: *__p = (source); break; \
339	case 2: *__p = cpu_to_be16(source); break; \
340	case 4: *__p = cpu_to_be32(source); break; \
341	case 8: *__p = cpu_to_be64(source); break; \
342	default: __buggy_use_of_MTHCA_PUT(); \
343	} \
344	} while (0)
345
346	int mthca_reset(struct mthca_dev *mdev);
347
348	u32 mthca_alloc(struct mthca_alloc *alloc);
349	void mthca_free(struct mthca_alloc *alloc, u32 obj);
350	int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
351	u32 reserved);
352	void mthca_alloc_cleanup(struct mthca_alloc *alloc);
353	void mthca_array_get(struct mthca_array array, int index);
354	int mthca_array_set(struct mthca_array array, int index, void value);
355	void mthca_array_clear(struct mthca_array *array, int index);
356	int mthca_array_init(struct mthca_array *array, int nent);
357	void mthca_array_cleanup(struct mthca_array *array, int nent);
358
359	int mthca_init_uar_table(struct mthca_dev *dev);
360	int mthca_init_pd_table(struct mthca_dev *dev);
361	int mthca_init_mr_table(struct mthca_dev *dev);
362	int mthca_init_eq_table(struct mthca_dev *dev);
363	int mthca_init_cq_table(struct mthca_dev *dev);
364	int mthca_init_qp_table(struct mthca_dev *dev);
365	int mthca_init_av_table(struct mthca_dev *dev);
366	int mthca_init_mcg_table(struct mthca_dev *dev);
367
368	void mthca_cleanup_uar_table(struct mthca_dev *dev);
369	void mthca_cleanup_pd_table(struct mthca_dev *dev);
370	void mthca_cleanup_mr_table(struct mthca_dev *dev);
371	void mthca_cleanup_eq_table(struct mthca_dev *dev);
372	void mthca_cleanup_cq_table(struct mthca_dev *dev);
373	void mthca_cleanup_qp_table(struct mthca_dev *dev);
374	void mthca_cleanup_av_table(struct mthca_dev *dev);
375	void mthca_cleanup_mcg_table(struct mthca_dev *dev);
376
377	int mthca_register_device(struct mthca_dev *dev);
378	void mthca_unregister_device(struct mthca_dev *dev);
379
380	int mthca_uar_alloc(struct mthca_dev dev, struct mthca_uar uar);
381	void mthca_uar_free(struct mthca_dev dev, struct mthca_uar uar);
382
383	int mthca_pd_alloc(struct mthca_dev dev, struct mthca_pd pd);
384	void mthca_pd_free(struct mthca_dev dev, struct mthca_pd pd);
385
386	int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
387	u32 access, struct mthca_mr *mr);
388	int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
389	u64 *buffer_list, int buffer_size_shift,
390	int list_len, u64 iova, u64 total_size,
391	u32 access, struct mthca_mr *mr);
e0f5fdca MT	392	void mthca_free_mr(struct mthca_dev dev, struct mthca_mr mr);
	393
	394	int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
	395	u32 access, struct mthca_fmr *fmr);
	396	int mthca_tavor_map_phys_fmr(struct ib_fmr ibfmr, u64 page_list,
	397	int list_len, u64 iova);
	398	void mthca_tavor_fmr_unmap(struct mthca_dev dev, struct mthca_fmr fmr);
	399	int mthca_arbel_map_phys_fmr(struct ib_fmr ibfmr, u64 page_list,
	400	int list_len, u64 iova);
	401	void mthca_arbel_fmr_unmap(struct mthca_dev dev, struct mthca_fmr fmr);
	402	int mthca_free_fmr(struct mthca_dev dev, struct mthca_fmr fmr);
1da177e4 LT	403
	404	int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
	405	void mthca_unmap_eq_icm(struct mthca_dev *dev);
	406
	407	int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
	408	struct ib_wc *entry);
	409	int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
	410	int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
	411	int mthca_init_cq(struct mthca_dev *dev, int nent,
	412	struct mthca_cq *cq);
	413	void mthca_free_cq(struct mthca_dev *dev,
	414	struct mthca_cq *cq);
	415	void mthca_cq_event(struct mthca_dev *dev, u32 cqn);
	416	void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn);
	417
	418	void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
	419	enum ib_event_type event_type);
	420	int mthca_modify_qp(struct ib_qp ibqp, struct ib_qp_attr attr, int attr_mask);
	421	int mthca_tavor_post_send(struct ib_qp ibqp, struct ib_send_wr wr,
	422	struct ib_send_wr **bad_wr);
	423	int mthca_tavor_post_receive(struct ib_qp ibqp, struct ib_recv_wr wr,
	424	struct ib_recv_wr **bad_wr);
	425	int mthca_arbel_post_send(struct ib_qp ibqp, struct ib_send_wr wr,
	426	struct ib_send_wr **bad_wr);
	427	int mthca_arbel_post_receive(struct ib_qp ibqp, struct ib_recv_wr wr,
	428	struct ib_recv_wr **bad_wr);
	429	int mthca_free_err_wqe(struct mthca_dev dev, struct mthca_qp qp, int is_send,
	430	int index, int dbd, u32 new_wqe);
	431	int mthca_alloc_qp(struct mthca_dev *dev,
	432	struct mthca_pd *pd,
	433	struct mthca_cq *send_cq,
	434	struct mthca_cq *recv_cq,
	435	enum ib_qp_type type,
	436	enum ib_sig_type send_policy,
	437	struct mthca_qp *qp);
	438	int mthca_alloc_sqp(struct mthca_dev *dev,
	439	struct mthca_pd *pd,
	440	struct mthca_cq *send_cq,
	441	struct mthca_cq *recv_cq,
	442	enum ib_sig_type send_policy,
	443	int qpn,
	444	int port,
	445	struct mthca_sqp *sqp);
	446	void mthca_free_qp(struct mthca_dev dev, struct mthca_qp qp);
	447	int mthca_create_ah(struct mthca_dev *dev,
	448	struct mthca_pd *pd,
	449	struct ib_ah_attr *ah_attr,
	450	struct mthca_ah *ah);
	451	int mthca_destroy_ah(struct mthca_dev dev, struct mthca_ah ah);
	452	int mthca_read_ah(struct mthca_dev dev, struct mthca_ah ah,
	453	struct ib_ud_header *header);
	454
	455	int mthca_multicast_attach(struct ib_qp ibqp, union ib_gid gid, u16 lid);
	456	int mthca_multicast_detach(struct ib_qp ibqp, union ib_gid gid, u16 lid);
	457
	458	int mthca_process_mad(struct ib_device *ibdev,
	459	int mad_flags,
	460	u8 port_num,
	461	struct ib_wc *in_wc,
	462	struct ib_grh *in_grh,
	463	struct ib_mad *in_mad,
	464	struct ib_mad *out_mad);
	465	int mthca_create_agents(struct mthca_dev *dev);
	466	void mthca_free_agents(struct mthca_dev *dev);
467
468	static inline struct mthca_dev to_mdev(struct ib_device ibdev)
469	{
470	return container_of(ibdev, struct mthca_dev, ib_dev);
471	}
472
d10ddbf6 RD	473	static inline int mthca_is_memfree(struct mthca_dev *dev)
	474	{
	475	return dev->hca_type == ARBEL_NATIVE;
	476	}
	477
1da177e4	478	#endif /* MTHCA_DEV_H */