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IPoIB: Consolidate private neighbour data handling
[linux-block.git] / drivers / infiniband / hw / mthca / mthca_dev.h
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
cd4e8fb4 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4885bf64 4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
2a1d9b7f
RD		 5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
1da177e4
LT		 7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 *
36 * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
37 */
38
39#ifndef MTHCA_DEV_H
40#define MTHCA_DEV_H
41
42#include <linux/spinlock.h>
43#include <linux/kernel.h>
44#include <linux/pci.h>
45#include <linux/dma-mapping.h>
de25968c 46#include <linux/timer.h>
fd9cfdd1
RD		 47#include <linux/mutex.h>
48
1da177e4
LT		 49#include <asm/semaphore.h>
50
51#include "mthca_provider.h"
52#include "mthca_doorbell.h"
53
54#define DRV_NAME "ib_mthca"
55#define PFX DRV_NAME ": "
00df1b2c
RD		 56#define DRV_VERSION "0.08"
57#define DRV_RELDATE "February 14, 2006"
1da177e4 58
1da177e4
LT		 59enum {
60 MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
61 MTHCA_FLAG_SRQ = 1 << 2,
62 MTHCA_FLAG_MSI = 1 << 3,
63 MTHCA_FLAG_MSI_X = 1 << 4,
e0f5fdca 64 MTHCA_FLAG_NO_LAM = 1 << 5,
68a3c212
RD		 65 MTHCA_FLAG_FMR = 1 << 6,
66 MTHCA_FLAG_MEMFREE = 1 << 7,
651eaac9
EC		 67 MTHCA_FLAG_PCIE = 1 << 8,
68 MTHCA_FLAG_SINAI_OPT = 1 << 9
1da177e4
LT		 69};
70
71enum {
72 MTHCA_MAX_PORTS = 2
73};
74
2e8b981c
MT		 75enum {
76 MTHCA_BOARD_ID_LEN = 64
77};
78
1da177e4
LT		 79enum {
80 MTHCA_EQ_CONTEXT_SIZE = 0x40,
81 MTHCA_CQ_CONTEXT_SIZE = 0x40,
82 MTHCA_QP_CONTEXT_SIZE = 0x200,
83 MTHCA_RDB_ENTRY_SIZE = 0x20,
84 MTHCA_AV_SIZE = 0x20,
85 MTHCA_MGM_ENTRY_SIZE = 0x40,
86
87 /* Arbel FW gives us these, but we need them for Tavor */
88 MTHCA_MPT_ENTRY_SIZE = 0x40,
89 MTHCA_MTT_SEG_SIZE = 0x40,
efaae8f7
JM		 90
91 MTHCA_QP_PER_MGM = 4 * (MTHCA_MGM_ENTRY_SIZE / 16 - 2)
1da177e4
LT		 92};
93
94enum {
95 MTHCA_EQ_CMD,
96 MTHCA_EQ_ASYNC,
97 MTHCA_EQ_COMP,
98 MTHCA_NUM_EQ
99};
100
2a4443a6
MT		 101enum {
102 MTHCA_OPCODE_NOP = 0x00,
103 MTHCA_OPCODE_RDMA_WRITE = 0x08,
104 MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
105 MTHCA_OPCODE_SEND = 0x0a,
106 MTHCA_OPCODE_SEND_IMM = 0x0b,
107 MTHCA_OPCODE_RDMA_READ = 0x10,
108 MTHCA_OPCODE_ATOMIC_CS = 0x11,
109 MTHCA_OPCODE_ATOMIC_FA = 0x12,
110 MTHCA_OPCODE_BIND_MW = 0x18,
111 MTHCA_OPCODE_INVALID = 0xff
112};
113
14abdffc
EC		 114enum {
115 MTHCA_CMD_USE_EVENTS = 1 << 0,
116 MTHCA_CMD_POST_DOORBELLS = 1 << 1
117};
118
119enum {
120 MTHCA_CMD_NUM_DBELL_DWORDS = 8
121};
122
1da177e4 123struct mthca_cmd {
ed878458 124 struct pci_pool *pool;
fd9cfdd1 125 struct mutex hcr_mutex;
1da177e4
LT		 126 struct semaphore poll_sem;
127 struct semaphore event_sem;
128 int max_cmds;
129 spinlock_t context_lock;
130 int free_head;
131 struct mthca_cmd_context *context;
132 u16 token_mask;
14abdffc
EC		 133 u32 flags;
134 void __iomem *dbell_map;
135 u16 dbell_offsets[MTHCA_CMD_NUM_DBELL_DWORDS];
1da177e4
LT		 136};
137
138struct mthca_limits {
139 int num_ports;
140 int vl_cap;
141 int mtu_cap;
142 int gid_table_len;
143 int pkey_table_len;
144 int local_ca_ack_delay;
145 int num_uars;
146 int max_sg;
147 int num_qps;
efaae8f7 148 int max_wqes;
77369ed3 149 int max_desc_sz;
efaae8f7 150 int max_qp_init_rdma;
1da177e4
LT		 151 int reserved_qps;
152 int num_srqs;
efaae8f7 153 int max_srq_wqes;
1da177e4
LT		 154 int reserved_srqs;
155 int num_eecs;
156 int reserved_eecs;
157 int num_cqs;
efaae8f7 158 int max_cqes;
1da177e4
LT		 159 int reserved_cqs;
160 int num_eqs;
161 int reserved_eqs;
162 int num_mpts;
163 int num_mtt_segs;
e0f5fdca 164 int fmr_reserved_mtts;
1da177e4
LT		 165 int reserved_mtts;
166 int reserved_mrws;
167 int reserved_uars;
168 int num_mgms;
169 int num_amgms;
170 int reserved_mcgs;
171 int num_pds;
172 int reserved_pds;
0f69ce1e 173 u32 page_size_cap;
33033b79 174 u32 flags;
da6561c2 175 u8 port_width_cap;
1da177e4
LT		 176};
177
178struct mthca_alloc {
179 u32 last;
180 u32 top;
181 u32 max;
182 u32 mask;
183 spinlock_t lock;
184 unsigned long *table;
185};
186
187struct mthca_array {
188 struct {
189 void **page;
190 int used;
191 } *page_list;
192};
193
194struct mthca_uar_table {
195 struct mthca_alloc alloc;
196 u64 uarc_base;
197 int uarc_size;
198};
199
200struct mthca_pd_table {
201 struct mthca_alloc alloc;
202};
203
9095e208
MT		 204struct mthca_buddy {
205 unsigned long **bits;
206 int max_order;
207 spinlock_t lock;
208};
209
1da177e4
LT		 210struct mthca_mr_table {
211 struct mthca_alloc mpt_alloc;
e0f5fdca
MT		 212 struct mthca_buddy mtt_buddy;
213 struct mthca_buddy *fmr_mtt_buddy;
1da177e4 214 u64 mtt_base;
e0f5fdca 215 u64 mpt_base;
1da177e4
LT		 216 struct mthca_icm_table *mtt_table;
217 struct mthca_icm_table *mpt_table;
e0f5fdca
MT		 218 struct {
219 void __iomem *mpt_base;
220 void __iomem *mtt_base;
221 struct mthca_buddy mtt_buddy;
222 } tavor_fmr;
1da177e4
LT		 223};
224
225struct mthca_eq_table {
226 struct mthca_alloc alloc;
227 void __iomem *clr_int;
228 u32 clr_mask;
229 u32 arm_mask;
230 struct mthca_eq eq[MTHCA_NUM_EQ];
231 u64 icm_virt;
232 struct page *icm_page;
233 dma_addr_t icm_dma;
234 int have_irq;
235 u8 inta_pin;
236};
237
238struct mthca_cq_table {
239 struct mthca_alloc alloc;
240 spinlock_t lock;
241 struct mthca_array cq;
242 struct mthca_icm_table *table;
243};
244
ec34a922
RD		 245struct mthca_srq_table {
246 struct mthca_alloc alloc;
247 spinlock_t lock;
248 struct mthca_array srq;
249 struct mthca_icm_table *table;
250};
251
1da177e4
LT		 252struct mthca_qp_table {
253 struct mthca_alloc alloc;
254 u32 rdb_base;
255 int rdb_shift;
256 int sqp_start;
257 spinlock_t lock;
258 struct mthca_array qp;
259 struct mthca_icm_table *qp_table;
260 struct mthca_icm_table *eqp_table;
08aeb14e 261 struct mthca_icm_table *rdb_table;
1da177e4
LT		 262};
263
264struct mthca_av_table {
265 struct pci_pool *pool;
266 int num_ddr_avs;
267 u64 ddr_av_base;
268 void __iomem *av_map;
269 struct mthca_alloc alloc;
270};
271
272struct mthca_mcg_table {
fd9cfdd1 273 struct mutex mutex;
1da177e4
LT		 274 struct mthca_alloc alloc;
275 struct mthca_icm_table *table;
276};
277
3d155f8c
RD		 278struct mthca_catas_err {
279 u64 addr;
280 u32 __iomem *map;
281 unsigned long stop;
282 u32 size;
283 struct timer_list timer;
284};
285
1da177e4
LT		 286struct mthca_dev {
287 struct ib_device ib_dev;
288 struct pci_dev *pdev;
289
290 int hca_type;
291 unsigned long mthca_flags;
292 unsigned long device_cap_flags;
293
294 u32 rev_id;
2e8b981c 295 char board_id[MTHCA_BOARD_ID_LEN];
1da177e4
LT		 296
297 /* firmware info */
298 u64 fw_ver;
299 union {
300 struct {
301 u64 fw_start;
302 u64 fw_end;
303 } tavor;
304 struct {
305 u64 clr_int_base;
306 u64 eq_arm_base;
307 u64 eq_set_ci_base;
308 struct mthca_icm *fw_icm;
309 struct mthca_icm *aux_icm;
310 u16 fw_pages;
311 } arbel;
312 } fw;
313
314 u64 ddr_start;
315 u64 ddr_end;
316
317 MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
fd9cfdd1 318 struct mutex cap_mask_mutex;
1da177e4
LT		 319
320 void __iomem *hcr;
321 void __iomem *kar;
322 void __iomem *clr_base;
323 union {
324 struct {
325 void __iomem *ecr_base;
326 } tavor;
327 struct {
328 void __iomem *eq_arm;
329 void __iomem *eq_set_ci_base;
330 } arbel;
331 } eq_regs;
332
333 struct mthca_cmd cmd;
334 struct mthca_limits limits;
335
336 struct mthca_uar_table uar_table;
337 struct mthca_pd_table pd_table;
338 struct mthca_mr_table mr_table;
339 struct mthca_eq_table eq_table;
340 struct mthca_cq_table cq_table;
ec34a922 341 struct mthca_srq_table srq_table;
1da177e4
LT		 342 struct mthca_qp_table qp_table;
343 struct mthca_av_table av_table;
344 struct mthca_mcg_table mcg_table;
345
3d155f8c
RD		 346 struct mthca_catas_err catas_err;
347
1da177e4
LT		 348 struct mthca_uar driver_uar;
349 struct mthca_db_table *db_tab;
350 struct mthca_pd driver_pd;
351 struct mthca_mr driver_mr;
352
353 struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
354 struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
355 spinlock_t sm_lock;
356};
357
227c939b
RD		 358#ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
359extern int mthca_debug_level;
360
361#define mthca_dbg(mdev, format, arg...) \
362 do { \
363 if (mthca_debug_level) \
364 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
365 } while (0)
366
367#else /* CONFIG_INFINIBAND_MTHCA_DEBUG */
368
369#define mthca_dbg(mdev, format, arg...) do { (void) mdev; } while (0)
370
371#endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
372
1da177e4
LT		 373#define mthca_err(mdev, format, arg...) \
374 dev_err(&mdev->pdev->dev, format, ## arg)
375#define mthca_info(mdev, format, arg...) \
376 dev_info(&mdev->pdev->dev, format, ## arg)
377#define mthca_warn(mdev, format, arg...) \
378 dev_warn(&mdev->pdev->dev, format, ## arg)
379
380extern void __buggy_use_of_MTHCA_GET(void);
381extern void __buggy_use_of_MTHCA_PUT(void);
382
383#define MTHCA_GET(dest, source, offset) \
384 do { \
385 void *__p = (char *) (source) + (offset); \
386 switch (sizeof (dest)) { \
387 case 1: (dest) = *(u8 *) __p; break; \
388 case 2: (dest) = be16_to_cpup(__p); break; \
389 case 4: (dest) = be32_to_cpup(__p); break; \
390 case 8: (dest) = be64_to_cpup(__p); break; \
391 default: __buggy_use_of_MTHCA_GET(); \
392 } \
393 } while (0)
394
395#define MTHCA_PUT(dest, source, offset) \
396 do { \
97f52eb4 397 void *__d = ((char *) (dest) + (offset)); \
1da177e4 398 switch (sizeof(source)) { \
97f52eb4
SH		 399 case 1: *(u8 *) __d = (source); break; \
400 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
401 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
402 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
403 default: __buggy_use_of_MTHCA_PUT(); \
1da177e4
LT		 404 } \
405 } while (0)
406
407int mthca_reset(struct mthca_dev *mdev);
408
409u32 mthca_alloc(struct mthca_alloc *alloc);
410void mthca_free(struct mthca_alloc *alloc, u32 obj);
411int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
412 u32 reserved);
413void mthca_alloc_cleanup(struct mthca_alloc *alloc);
414void *mthca_array_get(struct mthca_array *array, int index);
415int mthca_array_set(struct mthca_array *array, int index, void *value);
416void mthca_array_clear(struct mthca_array *array, int index);
417int mthca_array_init(struct mthca_array *array, int nent);
418void mthca_array_cleanup(struct mthca_array *array, int nent);
87b81670
RD		 419int mthca_buf_alloc(struct mthca_dev *dev, int size, int max_direct,
420 union mthca_buf *buf, int *is_direct, struct mthca_pd *pd,
421 int hca_write, struct mthca_mr *mr);
422void mthca_buf_free(struct mthca_dev *dev, int size, union mthca_buf *buf,
423 int is_direct, struct mthca_mr *mr);
1da177e4
LT		 424
425int mthca_init_uar_table(struct mthca_dev *dev);
426int mthca_init_pd_table(struct mthca_dev *dev);
427int mthca_init_mr_table(struct mthca_dev *dev);
428int mthca_init_eq_table(struct mthca_dev *dev);
429int mthca_init_cq_table(struct mthca_dev *dev);
ec34a922 430int mthca_init_srq_table(struct mthca_dev *dev);
1da177e4
LT		 431int mthca_init_qp_table(struct mthca_dev *dev);
432int mthca_init_av_table(struct mthca_dev *dev);
433int mthca_init_mcg_table(struct mthca_dev *dev);
434
435void mthca_cleanup_uar_table(struct mthca_dev *dev);
436void mthca_cleanup_pd_table(struct mthca_dev *dev);
437void mthca_cleanup_mr_table(struct mthca_dev *dev);
438void mthca_cleanup_eq_table(struct mthca_dev *dev);
439void mthca_cleanup_cq_table(struct mthca_dev *dev);
ec34a922 440void mthca_cleanup_srq_table(struct mthca_dev *dev);
1da177e4
LT		 441void mthca_cleanup_qp_table(struct mthca_dev *dev);
442void mthca_cleanup_av_table(struct mthca_dev *dev);
443void mthca_cleanup_mcg_table(struct mthca_dev *dev);
444
445int mthca_register_device(struct mthca_dev *dev);
446void mthca_unregister_device(struct mthca_dev *dev);
447
3d155f8c
RD		 448void mthca_start_catas_poll(struct mthca_dev *dev);
449void mthca_stop_catas_poll(struct mthca_dev *dev);
450
1da177e4
LT		 451int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
452void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);
453
99264c1e 454int mthca_pd_alloc(struct mthca_dev *dev, int privileged, struct mthca_pd *pd);
1da177e4
LT		 455void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);
456
d56d6f95
RD		 457struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size);
458void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt);
459int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
460 int start_index, u64 *buffer_list, int list_len);
461int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
462 u64 iova, u64 total_size, u32 access, struct mthca_mr *mr);
1da177e4
LT		 463int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
464 u32 access, struct mthca_mr *mr);
465int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
466 u64 *buffer_list, int buffer_size_shift,
467 int list_len, u64 iova, u64 total_size,
468 u32 access, struct mthca_mr *mr);
e0f5fdca
MT		 469void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr);
470
471int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
472 u32 access, struct mthca_fmr *fmr);
473int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
474 int list_len, u64 iova);
475void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
476int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
477 int list_len, u64 iova);
478void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
479int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr);
1da177e4
LT		 480
481int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
482void mthca_unmap_eq_icm(struct mthca_dev *dev);
483
484int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
485 struct ib_wc *entry);
486int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
487int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
488int mthca_init_cq(struct mthca_dev *dev, int nent,
74c2174e 489 struct mthca_ucontext *ctx, u32 pdn,
1da177e4
LT		 490 struct mthca_cq *cq);
491void mthca_free_cq(struct mthca_dev *dev,
492 struct mthca_cq *cq);
affcd505
MT		 493void mthca_cq_completion(struct mthca_dev *dev, u32 cqn);
494void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
495 enum ib_event_type event_type);
ec34a922
RD		 496void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn,
497 struct mthca_srq *srq);
4885bf64
RD		 498void mthca_cq_resize_copy_cqes(struct mthca_cq *cq);
499int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent);
500void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe);
ec34a922
RD		 501
502int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,
503 struct ib_srq_attr *attr, struct mthca_srq *srq);
504void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq);
90f104da
RD		 505int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
506 enum ib_srq_attr_mask attr_mask);
8ebe5077 507int mthca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr);
ec34a922
RD		 508void mthca_srq_event(struct mthca_dev *dev, u32 srqn,
509 enum ib_event_type event_type);
510void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr);
511int mthca_tavor_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
512 struct ib_recv_wr **bad_wr);
513int mthca_arbel_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
514 struct ib_recv_wr **bad_wr);
1da177e4
LT		 515
516void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
517 enum ib_event_type event_type);
8ebe5077
EC		 518int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
519 struct ib_qp_init_attr *qp_init_attr);
1da177e4
LT		 520int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask);
521int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
522 struct ib_send_wr **bad_wr);
523int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
524 struct ib_recv_wr **bad_wr);
525int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
526 struct ib_send_wr **bad_wr);
527int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
528 struct ib_recv_wr **bad_wr);
d9b98b0f
RD		 529void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
530 int index, int *dbd, __be32 *new_wqe);
1da177e4
LT		 531int mthca_alloc_qp(struct mthca_dev *dev,
532 struct mthca_pd *pd,
533 struct mthca_cq *send_cq,
534 struct mthca_cq *recv_cq,
535 enum ib_qp_type type,
536 enum ib_sig_type send_policy,
80c8ec2c 537 struct ib_qp_cap *cap,
1da177e4
LT		 538 struct mthca_qp *qp);
539int mthca_alloc_sqp(struct mthca_dev *dev,
540 struct mthca_pd *pd,
541 struct mthca_cq *send_cq,
542 struct mthca_cq *recv_cq,
543 enum ib_sig_type send_policy,
80c8ec2c 544 struct ib_qp_cap *cap,
1da177e4
LT		 545 int qpn,
546 int port,
547 struct mthca_sqp *sqp);
548void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
549int mthca_create_ah(struct mthca_dev *dev,
550 struct mthca_pd *pd,
551 struct ib_ah_attr *ah_attr,
552 struct mthca_ah *ah);
553int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
554int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
555 struct ib_ud_header *header);
1d89b1ae 556int mthca_ah_query(struct ib_ah *ibah, struct ib_ah_attr *attr);
9eacee2a 557int mthca_ah_grh_present(struct mthca_ah *ah);
1da177e4
LT		 558
559int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
560int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
561
562int mthca_process_mad(struct ib_device *ibdev,
563 int mad_flags,
564 u8 port_num,
565 struct ib_wc *in_wc,
566 struct ib_grh *in_grh,
567 struct ib_mad *in_mad,
568 struct ib_mad *out_mad);
569int mthca_create_agents(struct mthca_dev *dev);
570void mthca_free_agents(struct mthca_dev *dev);
571
572static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
573{
574 return container_of(ibdev, struct mthca_dev, ib_dev);
575}
576
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RD		 577static inline int mthca_is_memfree(struct mthca_dev *dev)
578{
68a3c212 579 return dev->mthca_flags & MTHCA_FLAG_MEMFREE;
d10ddbf6
RD		 580}
581
1da177e4 582#endif /* MTHCA_DEV_H */
Linux 6.x block layer and io_uring tree(s)