[linux-block.git] / drivers / infiniband / hw / mthca / mthca_dev.h

/*
 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
 */

#ifndef MTHCA_DEV_H
#define MTHCA_DEV_H

#include <linux/spinlock.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <asm/semaphore.h>

#include "mthca_provider.h"
#include "mthca_doorbell.h"

#define DRV_NAME	"ib_mthca"
#define PFX		DRV_NAME ": "
#define DRV_VERSION	"0.06-pre"
#define DRV_RELDATE	"November 8, 2004"

/* Types of supported HCA */
enum {
	TAVOR,			/* MT23108                        */
	ARBEL_COMPAT,		/* MT25208 in Tavor compat mode   */
	ARBEL_NATIVE		/* MT25208 with extended features */
};

enum {
	MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
	MTHCA_FLAG_SRQ        = 1 << 2,
	MTHCA_FLAG_MSI        = 1 << 3,
	MTHCA_FLAG_MSI_X      = 1 << 4,
	MTHCA_FLAG_NO_LAM     = 1 << 5
};

enum {
	MTHCA_MAX_PORTS = 2
};

enum {
	MTHCA_EQ_CONTEXT_SIZE =  0x40,
	MTHCA_CQ_CONTEXT_SIZE =  0x40,
	MTHCA_QP_CONTEXT_SIZE = 0x200,
	MTHCA_RDB_ENTRY_SIZE  =  0x20,
	MTHCA_AV_SIZE         =  0x20,
	MTHCA_MGM_ENTRY_SIZE  =  0x40,

	/* Arbel FW gives us these, but we need them for Tavor */
	MTHCA_MPT_ENTRY_SIZE  =  0x40,
	MTHCA_MTT_SEG_SIZE    =  0x40,
};

enum {
	MTHCA_EQ_CMD,
	MTHCA_EQ_ASYNC,
	MTHCA_EQ_COMP,
	MTHCA_NUM_EQ
};

enum {
	MTHCA_OPCODE_NOP            = 0x00,
	MTHCA_OPCODE_RDMA_WRITE     = 0x08,
	MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
	MTHCA_OPCODE_SEND           = 0x0a,
	MTHCA_OPCODE_SEND_IMM       = 0x0b,
	MTHCA_OPCODE_RDMA_READ      = 0x10,
	MTHCA_OPCODE_ATOMIC_CS      = 0x11,
	MTHCA_OPCODE_ATOMIC_FA      = 0x12,
	MTHCA_OPCODE_BIND_MW        = 0x18,
	MTHCA_OPCODE_INVALID        = 0xff
};

struct mthca_cmd {
	int                       use_events;
	struct semaphore          hcr_sem;
	struct semaphore 	  poll_sem;
	struct semaphore 	  event_sem;
	int              	  max_cmds;
	spinlock_t                context_lock;
	int                       free_head;
	struct mthca_cmd_context *context;
	u16                       token_mask;
};

struct mthca_limits {
	int      num_ports;
	int      vl_cap;
	int      mtu_cap;
	int      gid_table_len;
	int      pkey_table_len;
	int      local_ca_ack_delay;
	int      num_uars;
	int      max_sg;
	int      num_qps;
	int      reserved_qps;
	int      num_srqs;
	int      reserved_srqs;
	int      num_eecs;
	int      reserved_eecs;
	int      num_cqs;
	int      reserved_cqs;
	int      num_eqs;
	int      reserved_eqs;
	int      num_mpts;
	int      num_mtt_segs;
	int      reserved_mtts;
	int      reserved_mrws;
	int      reserved_uars;
	int      num_mgms;
	int      num_amgms;
	int      reserved_mcgs;
	int      num_pds;
	int      reserved_pds;
};

struct mthca_alloc {
	u32            last;
	u32            top;
	u32            max;
	u32            mask;
	spinlock_t     lock;
	unsigned long *table;
};

struct mthca_array {
	struct {
		void    **page;
		int       used;
	} *page_list;
};

struct mthca_uar_table {
	struct mthca_alloc alloc;
	u64                uarc_base;
	int                uarc_size;
};

struct mthca_pd_table {
	struct mthca_alloc alloc;
};

struct mthca_buddy {
	unsigned long **bits;
	int             max_order;
	spinlock_t      lock;
};

struct mthca_mr_table {
	struct mthca_alloc      mpt_alloc;
	struct mthca_buddy	mtt_buddy;
	u64                     mtt_base;
	struct mthca_icm_table *mtt_table;
	struct mthca_icm_table *mpt_table;
};

struct mthca_eq_table {
	struct mthca_alloc alloc;
	void __iomem      *clr_int;
	u32                clr_mask;
	u32                arm_mask;
	struct mthca_eq    eq[MTHCA_NUM_EQ];
	u64                icm_virt;
	struct page       *icm_page;
	dma_addr_t         icm_dma;
	int                have_irq;
	u8                 inta_pin;
};

struct mthca_cq_table {
	struct mthca_alloc 	alloc;
	spinlock_t         	lock;
	struct mthca_array      cq;
	struct mthca_icm_table *table;
};

struct mthca_qp_table {
	struct mthca_alloc     	alloc;
	u32                    	rdb_base;
	int                    	rdb_shift;
	int                    	sqp_start;
	spinlock_t             	lock;
	struct mthca_array     	qp;
	struct mthca_icm_table *qp_table;
	struct mthca_icm_table *eqp_table;
};

struct mthca_av_table {
	struct pci_pool   *pool;
	int                num_ddr_avs;
	u64                ddr_av_base;
	void __iomem      *av_map;
	struct mthca_alloc alloc;
};

struct mthca_mcg_table {
	struct semaphore   	sem;
	struct mthca_alloc 	alloc;
	struct mthca_icm_table *table;
};

struct mthca_dev {
	struct ib_device  ib_dev;
	struct pci_dev   *pdev;

	int          	 hca_type;
	unsigned long	 mthca_flags;
	unsigned long    device_cap_flags;

	u32              rev_id;

	/* firmware info */
	u64              fw_ver;
	union {
		struct {
			u64 fw_start;
			u64 fw_end;
		}        tavor;
		struct {
			u64 clr_int_base;
			u64 eq_arm_base;
			u64 eq_set_ci_base;
			struct mthca_icm *fw_icm;
			struct mthca_icm *aux_icm;
			u16 fw_pages;
		}        arbel;
	}                fw;

	u64              ddr_start;
	u64              ddr_end;

	MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
	struct semaphore cap_mask_mutex;

	void __iomem    *hcr;
	void __iomem    *kar;
	void __iomem    *clr_base;
	union {
		struct {
			void __iomem *ecr_base;
		} tavor;
		struct {
			void __iomem *eq_arm;
			void __iomem *eq_set_ci_base;
		} arbel;
	} eq_regs;

	struct mthca_cmd    cmd;
	struct mthca_limits limits;

	struct mthca_uar_table uar_table;
	struct mthca_pd_table  pd_table;
	struct mthca_mr_table  mr_table;
	struct mthca_eq_table  eq_table;
	struct mthca_cq_table  cq_table;
	struct mthca_qp_table  qp_table;
	struct mthca_av_table  av_table;
	struct mthca_mcg_table mcg_table;

	struct mthca_uar       driver_uar;
	struct mthca_db_table *db_tab;
	struct mthca_pd        driver_pd;
	struct mthca_mr        driver_mr;

	struct ib_mad_agent  *send_agent[MTHCA_MAX_PORTS][2];
	struct ib_ah         *sm_ah[MTHCA_MAX_PORTS];
	spinlock_t            sm_lock;
};

#define mthca_dbg(mdev, format, arg...) \
	dev_dbg(&mdev->pdev->dev, format, ## arg)
#define mthca_err(mdev, format, arg...) \
	dev_err(&mdev->pdev->dev, format, ## arg)
#define mthca_info(mdev, format, arg...) \
	dev_info(&mdev->pdev->dev, format, ## arg)
#define mthca_warn(mdev, format, arg...) \
	dev_warn(&mdev->pdev->dev, format, ## arg)

extern void __buggy_use_of_MTHCA_GET(void);
extern void __buggy_use_of_MTHCA_PUT(void);

#define MTHCA_GET(dest, source, offset)                               \
	do {                                                          \
		void *__p = (char *) (source) + (offset);             \
		switch (sizeof (dest)) {                              \
			case 1: (dest) = *(u8 *) __p;       break;    \
			case 2: (dest) = be16_to_cpup(__p); break;    \
			case 4: (dest) = be32_to_cpup(__p); break;    \
			case 8: (dest) = be64_to_cpup(__p); break;    \
			default: __buggy_use_of_MTHCA_GET();          \
		}                                                     \
	} while (0)

#define MTHCA_PUT(dest, source, offset)                               \
	do {                                                          \
		__typeof__(source) *__p =                             \
			(__typeof__(source) *) ((char *) (dest) + (offset)); \
		switch (sizeof(source)) {                             \
			case 1: *__p = (source);            break;    \
			case 2: *__p = cpu_to_be16(source); break;    \
			case 4: *__p = cpu_to_be32(source); break;    \
			case 8: *__p = cpu_to_be64(source); break;    \
			default: __buggy_use_of_MTHCA_PUT();          \
		}                                                     \
	} while (0)

int mthca_reset(struct mthca_dev *mdev);

u32 mthca_alloc(struct mthca_alloc *alloc);
void mthca_free(struct mthca_alloc *alloc, u32 obj);
int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
		     u32 reserved);
void mthca_alloc_cleanup(struct mthca_alloc *alloc);
void *mthca_array_get(struct mthca_array *array, int index);
int mthca_array_set(struct mthca_array *array, int index, void *value);
void mthca_array_clear(struct mthca_array *array, int index);
int mthca_array_init(struct mthca_array *array, int nent);
void mthca_array_cleanup(struct mthca_array *array, int nent);

int mthca_init_uar_table(struct mthca_dev *dev);
int mthca_init_pd_table(struct mthca_dev *dev);
int mthca_init_mr_table(struct mthca_dev *dev);
int mthca_init_eq_table(struct mthca_dev *dev);
int mthca_init_cq_table(struct mthca_dev *dev);
int mthca_init_qp_table(struct mthca_dev *dev);
int mthca_init_av_table(struct mthca_dev *dev);
int mthca_init_mcg_table(struct mthca_dev *dev);

void mthca_cleanup_uar_table(struct mthca_dev *dev);
void mthca_cleanup_pd_table(struct mthca_dev *dev);
void mthca_cleanup_mr_table(struct mthca_dev *dev);
void mthca_cleanup_eq_table(struct mthca_dev *dev);
void mthca_cleanup_cq_table(struct mthca_dev *dev);
void mthca_cleanup_qp_table(struct mthca_dev *dev);
void mthca_cleanup_av_table(struct mthca_dev *dev);
void mthca_cleanup_mcg_table(struct mthca_dev *dev);

int mthca_register_device(struct mthca_dev *dev);
void mthca_unregister_device(struct mthca_dev *dev);

int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);

int mthca_pd_alloc(struct mthca_dev *dev, struct mthca_pd *pd);
void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);

int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
			   u32 access, struct mthca_mr *mr);
int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
			u64 *buffer_list, int buffer_size_shift,
			int list_len, u64 iova, u64 total_size,
			u32 access, struct mthca_mr *mr);
void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr);

int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
void mthca_unmap_eq_icm(struct mthca_dev *dev);

int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
		  struct ib_wc *entry);
int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
int mthca_init_cq(struct mthca_dev *dev, int nent,
		  struct mthca_cq *cq);
void mthca_free_cq(struct mthca_dev *dev,
		   struct mthca_cq *cq);
void mthca_cq_event(struct mthca_dev *dev, u32 cqn);
void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn);

void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
		    enum ib_event_type event_type);
int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask);
int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
			  struct ib_send_wr **bad_wr);
int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
			     struct ib_recv_wr **bad_wr);
int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
			  struct ib_send_wr **bad_wr);
int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
			     struct ib_recv_wr **bad_wr);
int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
		       int index, int *dbd, u32 *new_wqe);
int mthca_alloc_qp(struct mthca_dev *dev,
		   struct mthca_pd *pd,
		   struct mthca_cq *send_cq,
		   struct mthca_cq *recv_cq,
		   enum ib_qp_type type,
		   enum ib_sig_type send_policy,
		   struct mthca_qp *qp);
int mthca_alloc_sqp(struct mthca_dev *dev,
		    struct mthca_pd *pd,
		    struct mthca_cq *send_cq,
		    struct mthca_cq *recv_cq,
		    enum ib_sig_type send_policy,
		    int qpn,
		    int port,
		    struct mthca_sqp *sqp);
void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
int mthca_create_ah(struct mthca_dev *dev,
		    struct mthca_pd *pd,
		    struct ib_ah_attr *ah_attr,
		    struct mthca_ah *ah);
int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
		  struct ib_ud_header *header);

int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);

int mthca_process_mad(struct ib_device *ibdev,
		      int mad_flags,
		      u8 port_num,
		      struct ib_wc *in_wc,
		      struct ib_grh *in_grh,
		      struct ib_mad *in_mad,
		      struct ib_mad *out_mad);
int mthca_create_agents(struct mthca_dev *dev);
void mthca_free_agents(struct mthca_dev *dev);

static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
{
	return container_of(ibdev, struct mthca_dev, ib_dev);
}

#endif /* MTHCA_DEV_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*
	32	* $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
	33	*/
	34
	35	#ifndef MTHCA_DEV_H
	36	#define MTHCA_DEV_H
	37
	38	#include <linux/spinlock.h>
	39	#include <linux/kernel.h>
	40	#include <linux/pci.h>
	41	#include <linux/dma-mapping.h>
	42	#include <asm/semaphore.h>
	43
	44	#include "mthca_provider.h"
	45	#include "mthca_doorbell.h"
	46
	47	#define DRV_NAME "ib_mthca"
	48	#define PFX DRV_NAME ": "
	49	#define DRV_VERSION "0.06-pre"
	50	#define DRV_RELDATE "November 8, 2004"
	51
	52	/* Types of supported HCA */
	53	enum {
	54	TAVOR, /* MT23108 */
	55	ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
	56	ARBEL_NATIVE /* MT25208 with extended features */
	57	};
	58
	59	enum {
	60	MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
	61	MTHCA_FLAG_SRQ = 1 << 2,
	62	MTHCA_FLAG_MSI = 1 << 3,
	63	MTHCA_FLAG_MSI_X = 1 << 4,
	64	MTHCA_FLAG_NO_LAM = 1 << 5
65	};
66
67	enum {
68	MTHCA_MAX_PORTS = 2
69	};
70
71	enum {
72	MTHCA_EQ_CONTEXT_SIZE = 0x40,
73	MTHCA_CQ_CONTEXT_SIZE = 0x40,
74	MTHCA_QP_CONTEXT_SIZE = 0x200,
75	MTHCA_RDB_ENTRY_SIZE = 0x20,
76	MTHCA_AV_SIZE = 0x20,
77	MTHCA_MGM_ENTRY_SIZE = 0x40,
78
79	/* Arbel FW gives us these, but we need them for Tavor */
80	MTHCA_MPT_ENTRY_SIZE = 0x40,
81	MTHCA_MTT_SEG_SIZE = 0x40,
82	};
83
84	enum {
85	MTHCA_EQ_CMD,
86	MTHCA_EQ_ASYNC,
87	MTHCA_EQ_COMP,
88	MTHCA_NUM_EQ
89	};
90
2a4443a6 MT	91	enum {
	92	MTHCA_OPCODE_NOP = 0x00,
	93	MTHCA_OPCODE_RDMA_WRITE = 0x08,
	94	MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
	95	MTHCA_OPCODE_SEND = 0x0a,
	96	MTHCA_OPCODE_SEND_IMM = 0x0b,
	97	MTHCA_OPCODE_RDMA_READ = 0x10,
	98	MTHCA_OPCODE_ATOMIC_CS = 0x11,
	99	MTHCA_OPCODE_ATOMIC_FA = 0x12,
	100	MTHCA_OPCODE_BIND_MW = 0x18,
	101	MTHCA_OPCODE_INVALID = 0xff
	102	};
	103
1da177e4 LT	104	struct mthca_cmd {
	105	int use_events;
	106	struct semaphore hcr_sem;
	107	struct semaphore poll_sem;
	108	struct semaphore event_sem;
	109	int max_cmds;
	110	spinlock_t context_lock;
	111	int free_head;
	112	struct mthca_cmd_context *context;
	113	u16 token_mask;
	114	};
	115
	116	struct mthca_limits {
	117	int num_ports;
	118	int vl_cap;
	119	int mtu_cap;
	120	int gid_table_len;
	121	int pkey_table_len;
	122	int local_ca_ack_delay;
	123	int num_uars;
	124	int max_sg;
	125	int num_qps;
	126	int reserved_qps;
	127	int num_srqs;
	128	int reserved_srqs;
	129	int num_eecs;
	130	int reserved_eecs;
	131	int num_cqs;
	132	int reserved_cqs;
	133	int num_eqs;
	134	int reserved_eqs;
	135	int num_mpts;
	136	int num_mtt_segs;
1da177e4 LT	137	int reserved_mtts;
	138	int reserved_mrws;
	139	int reserved_uars;
	140	int num_mgms;
	141	int num_amgms;
	142	int reserved_mcgs;
	143	int num_pds;
	144	int reserved_pds;
	145	};
	146
	147	struct mthca_alloc {
	148	u32 last;
	149	u32 top;
	150	u32 max;
	151	u32 mask;
	152	spinlock_t lock;
	153	unsigned long *table;
	154	};
	155
	156	struct mthca_array {
	157	struct {
	158	void **page;
	159	int used;
	160	} *page_list;
	161	};
	162
	163	struct mthca_uar_table {
	164	struct mthca_alloc alloc;
	165	u64 uarc_base;
	166	int uarc_size;
	167	};
	168
	169	struct mthca_pd_table {
	170	struct mthca_alloc alloc;
	171	};
	172
9095e208 MT	173	struct mthca_buddy {
	174	unsigned long **bits;
	175	int max_order;
	176	spinlock_t lock;
	177	};
	178
1da177e4 LT	179	struct mthca_mr_table {
1da177e4 LT	180	struct mthca_alloc mpt_alloc;
9095e208	181	struct mthca_buddy mtt_buddy;
1da177e4 LT	182	u64 mtt_base;
	183	struct mthca_icm_table *mtt_table;
	184	struct mthca_icm_table *mpt_table;
	185	};
	186
	187	struct mthca_eq_table {
	188	struct mthca_alloc alloc;
	189	void __iomem *clr_int;
	190	u32 clr_mask;
	191	u32 arm_mask;
	192	struct mthca_eq eq[MTHCA_NUM_EQ];
	193	u64 icm_virt;
	194	struct page *icm_page;
	195	dma_addr_t icm_dma;
	196	int have_irq;
	197	u8 inta_pin;
	198	};
	199
	200	struct mthca_cq_table {
	201	struct mthca_alloc alloc;
	202	spinlock_t lock;
	203	struct mthca_array cq;
	204	struct mthca_icm_table *table;
	205	};
	206
	207	struct mthca_qp_table {
	208	struct mthca_alloc alloc;
	209	u32 rdb_base;
	210	int rdb_shift;
	211	int sqp_start;
	212	spinlock_t lock;
	213	struct mthca_array qp;
	214	struct mthca_icm_table *qp_table;
	215	struct mthca_icm_table *eqp_table;
	216	};
	217
	218	struct mthca_av_table {
	219	struct pci_pool *pool;
	220	int num_ddr_avs;
	221	u64 ddr_av_base;
	222	void __iomem *av_map;
	223	struct mthca_alloc alloc;
	224	};
	225
	226	struct mthca_mcg_table {
	227	struct semaphore sem;
	228	struct mthca_alloc alloc;
	229	struct mthca_icm_table *table;
	230	};
	231
	232	struct mthca_dev {
	233	struct ib_device ib_dev;
	234	struct pci_dev *pdev;
	235
	236	int hca_type;
	237	unsigned long mthca_flags;
	238	unsigned long device_cap_flags;
	239
	240	u32 rev_id;
	241
	242	/* firmware info */
	243	u64 fw_ver;
	244	union {
	245	struct {
246	u64 fw_start;
247	u64 fw_end;
248	} tavor;
249	struct {
250	u64 clr_int_base;
251	u64 eq_arm_base;
252	u64 eq_set_ci_base;
253	struct mthca_icm *fw_icm;
254	struct mthca_icm *aux_icm;
255	u16 fw_pages;
256	} arbel;
257	} fw;
258
259	u64 ddr_start;
260	u64 ddr_end;
261
262	MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
263	struct semaphore cap_mask_mutex;
264
265	void __iomem *hcr;
266	void __iomem *kar;
267	void __iomem *clr_base;
268	union {
269	struct {
270	void __iomem *ecr_base;
271	} tavor;
272	struct {
273	void __iomem *eq_arm;
274	void __iomem *eq_set_ci_base;
275	} arbel;
276	} eq_regs;
277
278	struct mthca_cmd cmd;
279	struct mthca_limits limits;
280
281	struct mthca_uar_table uar_table;
282	struct mthca_pd_table pd_table;
283	struct mthca_mr_table mr_table;
284	struct mthca_eq_table eq_table;
285	struct mthca_cq_table cq_table;
286	struct mthca_qp_table qp_table;
287	struct mthca_av_table av_table;
288	struct mthca_mcg_table mcg_table;
289
290	struct mthca_uar driver_uar;
291	struct mthca_db_table *db_tab;
292	struct mthca_pd driver_pd;
293	struct mthca_mr driver_mr;
294
295	struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
296	struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
297	spinlock_t sm_lock;
298	};
299
300	#define mthca_dbg(mdev, format, arg...) \
301	dev_dbg(&mdev->pdev->dev, format, ## arg)
302	#define mthca_err(mdev, format, arg...) \
303	dev_err(&mdev->pdev->dev, format, ## arg)
304	#define mthca_info(mdev, format, arg...) \
305	dev_info(&mdev->pdev->dev, format, ## arg)
306	#define mthca_warn(mdev, format, arg...) \
307	dev_warn(&mdev->pdev->dev, format, ## arg)
308
309	extern void __buggy_use_of_MTHCA_GET(void);
310	extern void __buggy_use_of_MTHCA_PUT(void);
311
312	#define MTHCA_GET(dest, source, offset) \
313	do { \
314	void __p = (char ) (source) + (offset); \
315	switch (sizeof (dest)) { \
316	case 1: (dest) = (u8 ) __p; break; \
317	case 2: (dest) = be16_to_cpup(__p); break; \
318	case 4: (dest) = be32_to_cpup(__p); break; \
319	case 8: (dest) = be64_to_cpup(__p); break; \
320	default: __buggy_use_of_MTHCA_GET(); \
321	} \
322	} while (0)
323
324	#define MTHCA_PUT(dest, source, offset) \
325	do { \
326	__typeof__(source) *__p = \
327	(__typeof__(source) ) ((char ) (dest) + (offset)); \
328	switch (sizeof(source)) { \
329	case 1: *__p = (source); break; \
330	case 2: *__p = cpu_to_be16(source); break; \
331	case 4: *__p = cpu_to_be32(source); break; \
332	case 8: *__p = cpu_to_be64(source); break; \
333	default: __buggy_use_of_MTHCA_PUT(); \
334	} \
335	} while (0)
336
337	int mthca_reset(struct mthca_dev *mdev);
338
339	u32 mthca_alloc(struct mthca_alloc *alloc);
340	void mthca_free(struct mthca_alloc *alloc, u32 obj);
341	int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
342	u32 reserved);
343	void mthca_alloc_cleanup(struct mthca_alloc *alloc);
344	void mthca_array_get(struct mthca_array array, int index);
345	int mthca_array_set(struct mthca_array array, int index, void value);
346	void mthca_array_clear(struct mthca_array *array, int index);
347	int mthca_array_init(struct mthca_array *array, int nent);
348	void mthca_array_cleanup(struct mthca_array *array, int nent);
349
350	int mthca_init_uar_table(struct mthca_dev *dev);
351	int mthca_init_pd_table(struct mthca_dev *dev);
352	int mthca_init_mr_table(struct mthca_dev *dev);
353	int mthca_init_eq_table(struct mthca_dev *dev);
354	int mthca_init_cq_table(struct mthca_dev *dev);
355	int mthca_init_qp_table(struct mthca_dev *dev);
356	int mthca_init_av_table(struct mthca_dev *dev);
357	int mthca_init_mcg_table(struct mthca_dev *dev);
358
359	void mthca_cleanup_uar_table(struct mthca_dev *dev);
360	void mthca_cleanup_pd_table(struct mthca_dev *dev);
361	void mthca_cleanup_mr_table(struct mthca_dev *dev);
362	void mthca_cleanup_eq_table(struct mthca_dev *dev);
363	void mthca_cleanup_cq_table(struct mthca_dev *dev);
364	void mthca_cleanup_qp_table(struct mthca_dev *dev);
365	void mthca_cleanup_av_table(struct mthca_dev *dev);
366	void mthca_cleanup_mcg_table(struct mthca_dev *dev);
367
368	int mthca_register_device(struct mthca_dev *dev);
369	void mthca_unregister_device(struct mthca_dev *dev);
370
371	int mthca_uar_alloc(struct mthca_dev dev, struct mthca_uar uar);
372	void mthca_uar_free(struct mthca_dev dev, struct mthca_uar uar);
373
374	int mthca_pd_alloc(struct mthca_dev dev, struct mthca_pd pd);
375	void mthca_pd_free(struct mthca_dev dev, struct mthca_pd pd);
376
377	int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
378	u32 access, struct mthca_mr *mr);
379	int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
380	u64 *buffer_list, int buffer_size_shift,
381	int list_len, u64 iova, u64 total_size,
382	u32 access, struct mthca_mr *mr);
383	void mthca_free_mr(struct mthca_dev dev, struct mthca_mr mr);
384
385	int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
386	void mthca_unmap_eq_icm(struct mthca_dev *dev);
387
388	int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
389	struct ib_wc *entry);
390	int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
391	int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
392	int mthca_init_cq(struct mthca_dev *dev, int nent,
393	struct mthca_cq *cq);
394	void mthca_free_cq(struct mthca_dev *dev,
395	struct mthca_cq *cq);
396	void mthca_cq_event(struct mthca_dev *dev, u32 cqn);
397	void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn);
398
399	void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
400	enum ib_event_type event_type);
401	int mthca_modify_qp(struct ib_qp ibqp, struct ib_qp_attr attr, int attr_mask);
402	int mthca_tavor_post_send(struct ib_qp ibqp, struct ib_send_wr wr,
403	struct ib_send_wr **bad_wr);
404	int mthca_tavor_post_receive(struct ib_qp ibqp, struct ib_recv_wr wr,
405	struct ib_recv_wr **bad_wr);
406	int mthca_arbel_post_send(struct ib_qp ibqp, struct ib_send_wr wr,
407	struct ib_send_wr **bad_wr);
408	int mthca_arbel_post_receive(struct ib_qp ibqp, struct ib_recv_wr wr,
409	struct ib_recv_wr **bad_wr);
410	int mthca_free_err_wqe(struct mthca_dev dev, struct mthca_qp qp, int is_send,
411	int index, int dbd, u32 new_wqe);
412	int mthca_alloc_qp(struct mthca_dev *dev,
413	struct mthca_pd *pd,
414	struct mthca_cq *send_cq,
415	struct mthca_cq *recv_cq,
416	enum ib_qp_type type,
417	enum ib_sig_type send_policy,
418	struct mthca_qp *qp);
419	int mthca_alloc_sqp(struct mthca_dev *dev,
420	struct mthca_pd *pd,
421	struct mthca_cq *send_cq,
422	struct mthca_cq *recv_cq,
423	enum ib_sig_type send_policy,
424	int qpn,
425	int port,
426	struct mthca_sqp *sqp);
427	void mthca_free_qp(struct mthca_dev dev, struct mthca_qp qp);
428	int mthca_create_ah(struct mthca_dev *dev,
429	struct mthca_pd *pd,
430	struct ib_ah_attr *ah_attr,
431	struct mthca_ah *ah);
432	int mthca_destroy_ah(struct mthca_dev dev, struct mthca_ah ah);
433	int mthca_read_ah(struct mthca_dev dev, struct mthca_ah ah,
434	struct ib_ud_header *header);
435
436	int mthca_multicast_attach(struct ib_qp ibqp, union ib_gid gid, u16 lid);
437	int mthca_multicast_detach(struct ib_qp ibqp, union ib_gid gid, u16 lid);
438
439	int mthca_process_mad(struct ib_device *ibdev,
440	int mad_flags,
441	u8 port_num,
442	struct ib_wc *in_wc,
443	struct ib_grh *in_grh,
444	struct ib_mad *in_mad,
445	struct ib_mad *out_mad);
446	int mthca_create_agents(struct mthca_dev *dev);
447	void mthca_free_agents(struct mthca_dev *dev);
448
449	static inline struct mthca_dev to_mdev(struct ib_device ibdev)
450	{
451	return container_of(ibdev, struct mthca_dev, ib_dev);
452	}
453
454	#endif /* MTHCA_DEV_H */