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IB/cache: Use correct pointer to calculate size
[linux-block.git] / drivers / infiniband / hw / mthca / mthca_dev.h
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
cd4e8fb4 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4885bf64 4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
2a1d9b7f
RD		 5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
1da177e4
LT		 7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 *
36 * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
37 */
38
39#ifndef MTHCA_DEV_H
40#define MTHCA_DEV_H
41
42#include <linux/spinlock.h>
43#include <linux/kernel.h>
44#include <linux/pci.h>
45#include <linux/dma-mapping.h>
de25968c 46#include <linux/timer.h>
fd9cfdd1
RD		 47#include <linux/mutex.h>
48
1da177e4
LT		 49#include <asm/semaphore.h>
50
51#include "mthca_provider.h"
52#include "mthca_doorbell.h"
53
54#define DRV_NAME "ib_mthca"
55#define PFX DRV_NAME ": "
00df1b2c
RD		 56#define DRV_VERSION "0.08"
57#define DRV_RELDATE "February 14, 2006"
1da177e4 58
1da177e4
LT		 59enum {
60 MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
61 MTHCA_FLAG_SRQ = 1 << 2,
62 MTHCA_FLAG_MSI = 1 << 3,
63 MTHCA_FLAG_MSI_X = 1 << 4,
e0f5fdca 64 MTHCA_FLAG_NO_LAM = 1 << 5,
68a3c212
RD		 65 MTHCA_FLAG_FMR = 1 << 6,
66 MTHCA_FLAG_MEMFREE = 1 << 7,
651eaac9
EC		 67 MTHCA_FLAG_PCIE = 1 << 8,
68 MTHCA_FLAG_SINAI_OPT = 1 << 9
1da177e4
LT		 69};
70
71enum {
72 MTHCA_MAX_PORTS = 2
73};
74
2e8b981c
MT		 75enum {
76 MTHCA_BOARD_ID_LEN = 64
77};
78
1da177e4
LT		 79enum {
80 MTHCA_EQ_CONTEXT_SIZE = 0x40,
81 MTHCA_CQ_CONTEXT_SIZE = 0x40,
82 MTHCA_QP_CONTEXT_SIZE = 0x200,
83 MTHCA_RDB_ENTRY_SIZE = 0x20,
84 MTHCA_AV_SIZE = 0x20,
85 MTHCA_MGM_ENTRY_SIZE = 0x40,
86
87 /* Arbel FW gives us these, but we need them for Tavor */
88 MTHCA_MPT_ENTRY_SIZE = 0x40,
89 MTHCA_MTT_SEG_SIZE = 0x40,
efaae8f7
JM		 90
91 MTHCA_QP_PER_MGM = 4 * (MTHCA_MGM_ENTRY_SIZE / 16 - 2)
1da177e4
LT		 92};
93
94enum {
95 MTHCA_EQ_CMD,
96 MTHCA_EQ_ASYNC,
97 MTHCA_EQ_COMP,
98 MTHCA_NUM_EQ
99};
100
2a4443a6
MT		 101enum {
102 MTHCA_OPCODE_NOP = 0x00,
103 MTHCA_OPCODE_RDMA_WRITE = 0x08,
104 MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
105 MTHCA_OPCODE_SEND = 0x0a,
106 MTHCA_OPCODE_SEND_IMM = 0x0b,
107 MTHCA_OPCODE_RDMA_READ = 0x10,
108 MTHCA_OPCODE_ATOMIC_CS = 0x11,
109 MTHCA_OPCODE_ATOMIC_FA = 0x12,
110 MTHCA_OPCODE_BIND_MW = 0x18,
111 MTHCA_OPCODE_INVALID = 0xff
112};
113
14abdffc
EC		 114enum {
115 MTHCA_CMD_USE_EVENTS = 1 << 0,
116 MTHCA_CMD_POST_DOORBELLS = 1 << 1
117};
118
119enum {
120 MTHCA_CMD_NUM_DBELL_DWORDS = 8
121};
122
1da177e4 123struct mthca_cmd {
ed878458 124 struct pci_pool *pool;
fd9cfdd1 125 struct mutex hcr_mutex;
1da177e4
LT		 126 struct semaphore poll_sem;
127 struct semaphore event_sem;
128 int max_cmds;
129 spinlock_t context_lock;
130 int free_head;
131 struct mthca_cmd_context *context;
132 u16 token_mask;
14abdffc
EC		 133 u32 flags;
134 void __iomem *dbell_map;
135 u16 dbell_offsets[MTHCA_CMD_NUM_DBELL_DWORDS];
1da177e4
LT		 136};
137
138struct mthca_limits {
139 int num_ports;
140 int vl_cap;
141 int mtu_cap;
142 int gid_table_len;
143 int pkey_table_len;
144 int local_ca_ack_delay;
145 int num_uars;
146 int max_sg;
147 int num_qps;
efaae8f7 148 int max_wqes;
77369ed3 149 int max_desc_sz;
efaae8f7 150 int max_qp_init_rdma;
1da177e4
LT		 151 int reserved_qps;
152 int num_srqs;
efaae8f7 153 int max_srq_wqes;
1da177e4
LT		 154 int reserved_srqs;
155 int num_eecs;
156 int reserved_eecs;
157 int num_cqs;
efaae8f7 158 int max_cqes;
1da177e4
LT		 159 int reserved_cqs;
160 int num_eqs;
161 int reserved_eqs;
162 int num_mpts;
163 int num_mtt_segs;
e0f5fdca 164 int fmr_reserved_mtts;
1da177e4
LT		 165 int reserved_mtts;
166 int reserved_mrws;
167 int reserved_uars;
168 int num_mgms;
169 int num_amgms;
170 int reserved_mcgs;
171 int num_pds;
172 int reserved_pds;
0f69ce1e 173 u32 page_size_cap;
33033b79 174 u32 flags;
bf6a9e31 175 u16 stat_rate_support;
da6561c2 176 u8 port_width_cap;
1da177e4
LT		 177};
178
179struct mthca_alloc {
180 u32 last;
181 u32 top;
182 u32 max;
183 u32 mask;
184 spinlock_t lock;
185 unsigned long *table;
186};
187
188struct mthca_array {
189 struct {
190 void **page;
191 int used;
192 } *page_list;
193};
194
195struct mthca_uar_table {
196 struct mthca_alloc alloc;
197 u64 uarc_base;
198 int uarc_size;
199};
200
201struct mthca_pd_table {
202 struct mthca_alloc alloc;
203};
204
9095e208
MT		 205struct mthca_buddy {
206 unsigned long **bits;
207 int max_order;
208 spinlock_t lock;
209};
210
1da177e4
LT		 211struct mthca_mr_table {
212 struct mthca_alloc mpt_alloc;
e0f5fdca
MT		 213 struct mthca_buddy mtt_buddy;
214 struct mthca_buddy *fmr_mtt_buddy;
1da177e4 215 u64 mtt_base;
e0f5fdca 216 u64 mpt_base;
1da177e4
LT		 217 struct mthca_icm_table *mtt_table;
218 struct mthca_icm_table *mpt_table;
e0f5fdca
MT		 219 struct {
220 void __iomem *mpt_base;
221 void __iomem *mtt_base;
222 struct mthca_buddy mtt_buddy;
223 } tavor_fmr;
1da177e4
LT		 224};
225
226struct mthca_eq_table {
227 struct mthca_alloc alloc;
228 void __iomem *clr_int;
229 u32 clr_mask;
230 u32 arm_mask;
231 struct mthca_eq eq[MTHCA_NUM_EQ];
232 u64 icm_virt;
233 struct page *icm_page;
234 dma_addr_t icm_dma;
235 int have_irq;
236 u8 inta_pin;
237};
238
239struct mthca_cq_table {
240 struct mthca_alloc alloc;
241 spinlock_t lock;
242 struct mthca_array cq;
243 struct mthca_icm_table *table;
244};
245
ec34a922
RD		 246struct mthca_srq_table {
247 struct mthca_alloc alloc;
248 spinlock_t lock;
249 struct mthca_array srq;
250 struct mthca_icm_table *table;
251};
252
1da177e4
LT		 253struct mthca_qp_table {
254 struct mthca_alloc alloc;
255 u32 rdb_base;
256 int rdb_shift;
257 int sqp_start;
258 spinlock_t lock;
259 struct mthca_array qp;
260 struct mthca_icm_table *qp_table;
261 struct mthca_icm_table *eqp_table;
08aeb14e 262 struct mthca_icm_table *rdb_table;
1da177e4
LT		 263};
264
265struct mthca_av_table {
266 struct pci_pool *pool;
267 int num_ddr_avs;
268 u64 ddr_av_base;
269 void __iomem *av_map;
270 struct mthca_alloc alloc;
271};
272
273struct mthca_mcg_table {
fd9cfdd1 274 struct mutex mutex;
1da177e4
LT		 275 struct mthca_alloc alloc;
276 struct mthca_icm_table *table;
277};
278
3d155f8c
RD		 279struct mthca_catas_err {
280 u64 addr;
281 u32 __iomem *map;
282 unsigned long stop;
283 u32 size;
284 struct timer_list timer;
285};
286
1da177e4
LT		 287struct mthca_dev {
288 struct ib_device ib_dev;
289 struct pci_dev *pdev;
290
291 int hca_type;
292 unsigned long mthca_flags;
293 unsigned long device_cap_flags;
294
295 u32 rev_id;
2e8b981c 296 char board_id[MTHCA_BOARD_ID_LEN];
1da177e4
LT		 297
298 /* firmware info */
299 u64 fw_ver;
300 union {
301 struct {
302 u64 fw_start;
303 u64 fw_end;
304 } tavor;
305 struct {
306 u64 clr_int_base;
307 u64 eq_arm_base;
308 u64 eq_set_ci_base;
309 struct mthca_icm *fw_icm;
310 struct mthca_icm *aux_icm;
311 u16 fw_pages;
312 } arbel;
313 } fw;
314
315 u64 ddr_start;
316 u64 ddr_end;
317
318 MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
fd9cfdd1 319 struct mutex cap_mask_mutex;
1da177e4
LT		 320
321 void __iomem *hcr;
322 void __iomem *kar;
323 void __iomem *clr_base;
324 union {
325 struct {
326 void __iomem *ecr_base;
327 } tavor;
328 struct {
329 void __iomem *eq_arm;
330 void __iomem *eq_set_ci_base;
331 } arbel;
332 } eq_regs;
333
334 struct mthca_cmd cmd;
335 struct mthca_limits limits;
336
337 struct mthca_uar_table uar_table;
338 struct mthca_pd_table pd_table;
339 struct mthca_mr_table mr_table;
340 struct mthca_eq_table eq_table;
341 struct mthca_cq_table cq_table;
ec34a922 342 struct mthca_srq_table srq_table;
1da177e4
LT		 343 struct mthca_qp_table qp_table;
344 struct mthca_av_table av_table;
345 struct mthca_mcg_table mcg_table;
346
3d155f8c
RD		 347 struct mthca_catas_err catas_err;
348
1da177e4
LT		 349 struct mthca_uar driver_uar;
350 struct mthca_db_table *db_tab;
351 struct mthca_pd driver_pd;
352 struct mthca_mr driver_mr;
353
354 struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
355 struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
356 spinlock_t sm_lock;
bf6a9e31 357 u8 rate[MTHCA_MAX_PORTS];
1da177e4
LT		 358};
359
227c939b
RD		 360#ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
361extern int mthca_debug_level;
362
363#define mthca_dbg(mdev, format, arg...) \
364 do { \
365 if (mthca_debug_level) \
366 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
367 } while (0)
368
369#else /* CONFIG_INFINIBAND_MTHCA_DEBUG */
370
371#define mthca_dbg(mdev, format, arg...) do { (void) mdev; } while (0)
372
373#endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
374
1da177e4
LT		 375#define mthca_err(mdev, format, arg...) \
376 dev_err(&mdev->pdev->dev, format, ## arg)
377#define mthca_info(mdev, format, arg...) \
378 dev_info(&mdev->pdev->dev, format, ## arg)
379#define mthca_warn(mdev, format, arg...) \
380 dev_warn(&mdev->pdev->dev, format, ## arg)
381
382extern void __buggy_use_of_MTHCA_GET(void);
383extern void __buggy_use_of_MTHCA_PUT(void);
384
385#define MTHCA_GET(dest, source, offset) \
386 do { \
387 void *__p = (char *) (source) + (offset); \
388 switch (sizeof (dest)) { \
389 case 1: (dest) = *(u8 *) __p; break; \
390 case 2: (dest) = be16_to_cpup(__p); break; \
391 case 4: (dest) = be32_to_cpup(__p); break; \
392 case 8: (dest) = be64_to_cpup(__p); break; \
393 default: __buggy_use_of_MTHCA_GET(); \
394 } \
395 } while (0)
396
397#define MTHCA_PUT(dest, source, offset) \
398 do { \
97f52eb4 399 void *__d = ((char *) (dest) + (offset)); \
1da177e4 400 switch (sizeof(source)) { \
97f52eb4
SH		 401 case 1: *(u8 *) __d = (source); break; \
402 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
403 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
404 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
405 default: __buggy_use_of_MTHCA_PUT(); \
1da177e4
LT		 406 } \
407 } while (0)
408
409int mthca_reset(struct mthca_dev *mdev);
410
411u32 mthca_alloc(struct mthca_alloc *alloc);
412void mthca_free(struct mthca_alloc *alloc, u32 obj);
413int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
414 u32 reserved);
415void mthca_alloc_cleanup(struct mthca_alloc *alloc);
416void *mthca_array_get(struct mthca_array *array, int index);
417int mthca_array_set(struct mthca_array *array, int index, void *value);
418void mthca_array_clear(struct mthca_array *array, int index);
419int mthca_array_init(struct mthca_array *array, int nent);
420void mthca_array_cleanup(struct mthca_array *array, int nent);
87b81670
RD		 421int mthca_buf_alloc(struct mthca_dev *dev, int size, int max_direct,
422 union mthca_buf *buf, int *is_direct, struct mthca_pd *pd,
423 int hca_write, struct mthca_mr *mr);
424void mthca_buf_free(struct mthca_dev *dev, int size, union mthca_buf *buf,
425 int is_direct, struct mthca_mr *mr);
1da177e4
LT		 426
427int mthca_init_uar_table(struct mthca_dev *dev);
428int mthca_init_pd_table(struct mthca_dev *dev);
429int mthca_init_mr_table(struct mthca_dev *dev);
430int mthca_init_eq_table(struct mthca_dev *dev);
431int mthca_init_cq_table(struct mthca_dev *dev);
ec34a922 432int mthca_init_srq_table(struct mthca_dev *dev);
1da177e4
LT		 433int mthca_init_qp_table(struct mthca_dev *dev);
434int mthca_init_av_table(struct mthca_dev *dev);
435int mthca_init_mcg_table(struct mthca_dev *dev);
436
437void mthca_cleanup_uar_table(struct mthca_dev *dev);
438void mthca_cleanup_pd_table(struct mthca_dev *dev);
439void mthca_cleanup_mr_table(struct mthca_dev *dev);
440void mthca_cleanup_eq_table(struct mthca_dev *dev);
441void mthca_cleanup_cq_table(struct mthca_dev *dev);
ec34a922 442void mthca_cleanup_srq_table(struct mthca_dev *dev);
1da177e4
LT		 443void mthca_cleanup_qp_table(struct mthca_dev *dev);
444void mthca_cleanup_av_table(struct mthca_dev *dev);
445void mthca_cleanup_mcg_table(struct mthca_dev *dev);
446
447int mthca_register_device(struct mthca_dev *dev);
448void mthca_unregister_device(struct mthca_dev *dev);
449
3d155f8c
RD		 450void mthca_start_catas_poll(struct mthca_dev *dev);
451void mthca_stop_catas_poll(struct mthca_dev *dev);
452
1da177e4
LT		 453int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
454void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);
455
99264c1e 456int mthca_pd_alloc(struct mthca_dev *dev, int privileged, struct mthca_pd *pd);
1da177e4
LT		 457void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);
458
d56d6f95
RD		 459struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size);
460void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt);
461int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
462 int start_index, u64 *buffer_list, int list_len);
463int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
464 u64 iova, u64 total_size, u32 access, struct mthca_mr *mr);
1da177e4
LT		 465int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
466 u32 access, struct mthca_mr *mr);
467int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
468 u64 *buffer_list, int buffer_size_shift,
469 int list_len, u64 iova, u64 total_size,
470 u32 access, struct mthca_mr *mr);
e0f5fdca
MT		 471void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr);
472
473int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
474 u32 access, struct mthca_fmr *fmr);
475int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
476 int list_len, u64 iova);
477void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
478int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
479 int list_len, u64 iova);
480void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
481int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr);
1da177e4
LT		 482
483int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
484void mthca_unmap_eq_icm(struct mthca_dev *dev);
485
486int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
487 struct ib_wc *entry);
488int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
489int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
490int mthca_init_cq(struct mthca_dev *dev, int nent,
74c2174e 491 struct mthca_ucontext *ctx, u32 pdn,
1da177e4
LT		 492 struct mthca_cq *cq);
493void mthca_free_cq(struct mthca_dev *dev,
494 struct mthca_cq *cq);
affcd505
MT		 495void mthca_cq_completion(struct mthca_dev *dev, u32 cqn);
496void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
497 enum ib_event_type event_type);
ec34a922
RD		 498void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn,
499 struct mthca_srq *srq);
4885bf64
RD		 500void mthca_cq_resize_copy_cqes(struct mthca_cq *cq);
501int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent);
502void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe);
ec34a922
RD		 503
504int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,
505 struct ib_srq_attr *attr, struct mthca_srq *srq);
506void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq);
90f104da
RD		 507int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
508 enum ib_srq_attr_mask attr_mask);
8ebe5077 509int mthca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr);
ec34a922
RD		 510void mthca_srq_event(struct mthca_dev *dev, u32 srqn,
511 enum ib_event_type event_type);
512void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr);
513int mthca_tavor_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
514 struct ib_recv_wr **bad_wr);
515int mthca_arbel_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
516 struct ib_recv_wr **bad_wr);
1da177e4
LT		 517
518void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
519 enum ib_event_type event_type);
8ebe5077
EC		 520int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
521 struct ib_qp_init_attr *qp_init_attr);
1da177e4
LT		 522int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask);
523int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
524 struct ib_send_wr **bad_wr);
525int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
526 struct ib_recv_wr **bad_wr);
527int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
528 struct ib_send_wr **bad_wr);
529int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
530 struct ib_recv_wr **bad_wr);
d9b98b0f
RD		 531void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
532 int index, int *dbd, __be32 *new_wqe);
1da177e4
LT		 533int mthca_alloc_qp(struct mthca_dev *dev,
534 struct mthca_pd *pd,
535 struct mthca_cq *send_cq,
536 struct mthca_cq *recv_cq,
537 enum ib_qp_type type,
538 enum ib_sig_type send_policy,
80c8ec2c 539 struct ib_qp_cap *cap,
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LT		 540 struct mthca_qp *qp);
541int mthca_alloc_sqp(struct mthca_dev *dev,
542 struct mthca_pd *pd,
543 struct mthca_cq *send_cq,
544 struct mthca_cq *recv_cq,
545 enum ib_sig_type send_policy,
80c8ec2c 546 struct ib_qp_cap *cap,
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LT		 547 int qpn,
548 int port,
549 struct mthca_sqp *sqp);
550void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
551int mthca_create_ah(struct mthca_dev *dev,
552 struct mthca_pd *pd,
553 struct ib_ah_attr *ah_attr,
554 struct mthca_ah *ah);
555int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
556int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
557 struct ib_ud_header *header);
1d89b1ae 558int mthca_ah_query(struct ib_ah *ibah, struct ib_ah_attr *attr);
9eacee2a 559int mthca_ah_grh_present(struct mthca_ah *ah);
bf6a9e31
JM		 560u8 mthca_get_rate(struct mthca_dev *dev, int static_rate, u8 port);
561enum ib_rate mthca_rate_to_ib(struct mthca_dev *dev, u8 mthca_rate, u8 port);
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LT		 562
563int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
564int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
565
566int mthca_process_mad(struct ib_device *ibdev,
567 int mad_flags,
568 u8 port_num,
569 struct ib_wc *in_wc,
570 struct ib_grh *in_grh,
571 struct ib_mad *in_mad,
572 struct ib_mad *out_mad);
573int mthca_create_agents(struct mthca_dev *dev);
574void mthca_free_agents(struct mthca_dev *dev);
575
576static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
577{
578 return container_of(ibdev, struct mthca_dev, ib_dev);
579}
580
d10ddbf6
RD		 581static inline int mthca_is_memfree(struct mthca_dev *dev)
582{
68a3c212 583 return dev->mthca_flags & MTHCA_FLAG_MEMFREE;
d10ddbf6
RD		 584}
585
1da177e4 586#endif /* MTHCA_DEV_H */
Linux 6.x block layer and io_uring tree(s)