[linux-block.git] / drivers / infiniband / hw / mthca / mthca_dev.h

/*
 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
 * Copyright (c) 2005, 2006 Cisco Systems.  All rights reserved.
 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
 */

#ifndef MTHCA_DEV_H
#define MTHCA_DEV_H

#include <linux/spinlock.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/timer.h>
#include <linux/mutex.h>
#include <linux/list.h>

#include <asm/semaphore.h>

#include "mthca_provider.h"
#include "mthca_doorbell.h"

#define DRV_NAME	"ib_mthca"
#define PFX		DRV_NAME ": "
#define DRV_VERSION	"0.08"
#define DRV_RELDATE	"February 14, 2006"

enum {
	MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
	MTHCA_FLAG_SRQ        = 1 << 2,
	MTHCA_FLAG_MSI_X      = 1 << 3,
	MTHCA_FLAG_NO_LAM     = 1 << 4,
	MTHCA_FLAG_FMR        = 1 << 5,
	MTHCA_FLAG_MEMFREE    = 1 << 6,
	MTHCA_FLAG_PCIE       = 1 << 7,
	MTHCA_FLAG_SINAI_OPT  = 1 << 8
};

enum {
	MTHCA_MAX_PORTS = 2
};

enum {
	MTHCA_BOARD_ID_LEN = 64
};

enum {
	MTHCA_EQ_CONTEXT_SIZE =  0x40,
	MTHCA_CQ_CONTEXT_SIZE =  0x40,
	MTHCA_QP_CONTEXT_SIZE = 0x200,
	MTHCA_RDB_ENTRY_SIZE  =  0x20,
	MTHCA_AV_SIZE         =  0x20,
	MTHCA_MGM_ENTRY_SIZE  = 0x100,

	/* Arbel FW gives us these, but we need them for Tavor */
	MTHCA_MPT_ENTRY_SIZE  =  0x40,
	MTHCA_MTT_SEG_SIZE    =  0x40,

	MTHCA_QP_PER_MGM      = 4 * (MTHCA_MGM_ENTRY_SIZE / 16 - 2)
};

enum {
	MTHCA_EQ_CMD,
	MTHCA_EQ_ASYNC,
	MTHCA_EQ_COMP,
	MTHCA_NUM_EQ
};

enum {
	MTHCA_OPCODE_NOP            = 0x00,
	MTHCA_OPCODE_RDMA_WRITE     = 0x08,
	MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
	MTHCA_OPCODE_SEND           = 0x0a,
	MTHCA_OPCODE_SEND_IMM       = 0x0b,
	MTHCA_OPCODE_RDMA_READ      = 0x10,
	MTHCA_OPCODE_ATOMIC_CS      = 0x11,
	MTHCA_OPCODE_ATOMIC_FA      = 0x12,
	MTHCA_OPCODE_BIND_MW        = 0x18,
	MTHCA_OPCODE_INVALID        = 0xff
};

enum {
	MTHCA_CMD_USE_EVENTS         = 1 << 0,
	MTHCA_CMD_POST_DOORBELLS     = 1 << 1
};

enum {
	MTHCA_CMD_NUM_DBELL_DWORDS = 8
};

struct mthca_cmd {
	struct pci_pool          *pool;
	struct mutex              hcr_mutex;
	struct semaphore 	  poll_sem;
	struct semaphore 	  event_sem;
	int              	  max_cmds;
	spinlock_t                context_lock;
	int                       free_head;
	struct mthca_cmd_context *context;
	u16                       token_mask;
	u32                       flags;
	void __iomem             *dbell_map;
	u16                       dbell_offsets[MTHCA_CMD_NUM_DBELL_DWORDS];
};

struct mthca_limits {
	int      num_ports;
	int      vl_cap;
	int      mtu_cap;
	int      gid_table_len;
	int      pkey_table_len;
	int      local_ca_ack_delay;
	int      num_uars;
	int      max_sg;
	int      num_qps;
	int      max_wqes;
	int	 max_desc_sz;
	int	 max_qp_init_rdma;
	int      reserved_qps;
	int      num_srqs;
	int      max_srq_wqes;
	int      max_srq_sge;
	int      reserved_srqs;
	int      num_eecs;
	int      reserved_eecs;
	int      num_cqs;
	int      max_cqes;
	int      reserved_cqs;
	int      num_eqs;
	int      reserved_eqs;
	int      num_mpts;
	int      num_mtt_segs;
	int      fmr_reserved_mtts;
	int      reserved_mtts;
	int      reserved_mrws;
	int      reserved_uars;
	int      num_mgms;
	int      num_amgms;
	int      reserved_mcgs;
	int      num_pds;
	int      reserved_pds;
	u32      page_size_cap;
	u32      flags;
	u16      stat_rate_support;
	u8       port_width_cap;
};

struct mthca_alloc {
	u32            last;
	u32            top;
	u32            max;
	u32            mask;
	spinlock_t     lock;
	unsigned long *table;
};

struct mthca_array {
	struct {
		void    **page;
		int       used;
	} *page_list;
};

struct mthca_uar_table {
	struct mthca_alloc alloc;
	u64                uarc_base;
	int                uarc_size;
};

struct mthca_pd_table {
	struct mthca_alloc alloc;
};

struct mthca_buddy {
	unsigned long **bits;
	int             max_order;
	spinlock_t      lock;
};

struct mthca_mr_table {
	struct mthca_alloc      mpt_alloc;
	struct mthca_buddy      mtt_buddy;
	struct mthca_buddy     *fmr_mtt_buddy;
	u64                     mtt_base;
	u64                     mpt_base;
	struct mthca_icm_table *mtt_table;
	struct mthca_icm_table *mpt_table;
	struct {
		void __iomem   *mpt_base;
		void __iomem   *mtt_base;
		struct mthca_buddy mtt_buddy;
	} tavor_fmr;
};

struct mthca_eq_table {
	struct mthca_alloc alloc;
	void __iomem      *clr_int;
	u32                clr_mask;
	u32                arm_mask;
	struct mthca_eq    eq[MTHCA_NUM_EQ];
	u64                icm_virt;
	struct page       *icm_page;
	dma_addr_t         icm_dma;
	int                have_irq;
	u8                 inta_pin;
};

struct mthca_cq_table {
	struct mthca_alloc 	alloc;
	spinlock_t         	lock;
	struct mthca_array      cq;
	struct mthca_icm_table *table;
};

struct mthca_srq_table {
	struct mthca_alloc 	alloc;
	spinlock_t         	lock;
	struct mthca_array      srq;
	struct mthca_icm_table *table;
};

struct mthca_qp_table {
	struct mthca_alloc     	alloc;
	u32                    	rdb_base;
	int                    	rdb_shift;
	int                    	sqp_start;
	spinlock_t             	lock;
	struct mthca_array     	qp;
	struct mthca_icm_table *qp_table;
	struct mthca_icm_table *eqp_table;
	struct mthca_icm_table *rdb_table;
};

struct mthca_av_table {
	struct pci_pool   *pool;
	int                num_ddr_avs;
	u64                ddr_av_base;
	void __iomem      *av_map;
	struct mthca_alloc alloc;
};

struct mthca_mcg_table {
	struct mutex		mutex;
	struct mthca_alloc 	alloc;
	struct mthca_icm_table *table;
};

struct mthca_catas_err {
	u64			addr;
	u32 __iomem	       *map;
	unsigned long		stop;
	u32			size;
	struct timer_list	timer;
	struct list_head	list;
};

extern struct mutex mthca_device_mutex;

struct mthca_dev {
	struct ib_device  ib_dev;
	struct pci_dev   *pdev;

	int          	 hca_type;
	unsigned long	 mthca_flags;
	unsigned long    device_cap_flags;

	u32              rev_id;
	char             board_id[MTHCA_BOARD_ID_LEN];

	/* firmware info */
	u64              fw_ver;
	union {
		struct {
			u64 fw_start;
			u64 fw_end;
		}        tavor;
		struct {
			u64 clr_int_base;
			u64 eq_arm_base;
			u64 eq_set_ci_base;
			struct mthca_icm *fw_icm;
			struct mthca_icm *aux_icm;
			u16 fw_pages;
		}        arbel;
	}                fw;

	u64              ddr_start;
	u64              ddr_end;

	MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
	struct mutex cap_mask_mutex;

	void __iomem    *hcr;
	void __iomem    *kar;
	void __iomem    *clr_base;
	union {
		struct {
			void __iomem *ecr_base;
		} tavor;
		struct {
			void __iomem *eq_arm;
			void __iomem *eq_set_ci_base;
		} arbel;
	} eq_regs;

	struct mthca_cmd    cmd;
	struct mthca_limits limits;

	struct mthca_uar_table uar_table;
	struct mthca_pd_table  pd_table;
	struct mthca_mr_table  mr_table;
	struct mthca_eq_table  eq_table;
	struct mthca_cq_table  cq_table;
	struct mthca_srq_table srq_table;
	struct mthca_qp_table  qp_table;
	struct mthca_av_table  av_table;
	struct mthca_mcg_table mcg_table;

	struct mthca_catas_err catas_err;

	struct mthca_uar       driver_uar;
	struct mthca_db_table *db_tab;
	struct mthca_pd        driver_pd;
	struct mthca_mr        driver_mr;

	struct ib_mad_agent  *send_agent[MTHCA_MAX_PORTS][2];
	struct ib_ah         *sm_ah[MTHCA_MAX_PORTS];
	spinlock_t            sm_lock;
	u8                    rate[MTHCA_MAX_PORTS];
};

#ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
extern int mthca_debug_level;

#define mthca_dbg(mdev, format, arg...)					\
	do {								\
		if (mthca_debug_level)					\
			dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
	} while (0)

#else /* CONFIG_INFINIBAND_MTHCA_DEBUG */

#define mthca_dbg(mdev, format, arg...) do { (void) mdev; } while (0)

#endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */

#define mthca_err(mdev, format, arg...) \
	dev_err(&mdev->pdev->dev, format, ## arg)
#define mthca_info(mdev, format, arg...) \
	dev_info(&mdev->pdev->dev, format, ## arg)
#define mthca_warn(mdev, format, arg...) \
	dev_warn(&mdev->pdev->dev, format, ## arg)

extern void __buggy_use_of_MTHCA_GET(void);
extern void __buggy_use_of_MTHCA_PUT(void);

#define MTHCA_GET(dest, source, offset)                               \
	do {                                                          \
		void *__p = (char *) (source) + (offset);             \
		switch (sizeof (dest)) {                              \
			case 1: (dest) = *(u8 *) __p;       break;    \
			case 2: (dest) = be16_to_cpup(__p); break;    \
			case 4: (dest) = be32_to_cpup(__p); break;    \
			case 8: (dest) = be64_to_cpup(__p); break;    \
			default: __buggy_use_of_MTHCA_GET();          \
		}                                                     \
	} while (0)

#define MTHCA_PUT(dest, source, offset)                               \
	do {                                                          \
		void *__d = ((char *) (dest) + (offset));	      \
		switch (sizeof(source)) {                             \
		case 1: *(u8 *) __d = (source);                break; \
		case 2:	*(__be16 *) __d = cpu_to_be16(source); break; \
		case 4:	*(__be32 *) __d = cpu_to_be32(source); break; \
		case 8:	*(__be64 *) __d = cpu_to_be64(source); break; \
		default: __buggy_use_of_MTHCA_PUT();		      \
		}                                                     \
	} while (0)

int mthca_reset(struct mthca_dev *mdev);

u32 mthca_alloc(struct mthca_alloc *alloc);
void mthca_free(struct mthca_alloc *alloc, u32 obj);
int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
		     u32 reserved);
void mthca_alloc_cleanup(struct mthca_alloc *alloc);
void *mthca_array_get(struct mthca_array *array, int index);
int mthca_array_set(struct mthca_array *array, int index, void *value);
void mthca_array_clear(struct mthca_array *array, int index);
int mthca_array_init(struct mthca_array *array, int nent);
void mthca_array_cleanup(struct mthca_array *array, int nent);
int mthca_buf_alloc(struct mthca_dev *dev, int size, int max_direct,
		    union mthca_buf *buf, int *is_direct, struct mthca_pd *pd,
		    int hca_write, struct mthca_mr *mr);
void mthca_buf_free(struct mthca_dev *dev, int size, union mthca_buf *buf,
		    int is_direct, struct mthca_mr *mr);

int mthca_init_uar_table(struct mthca_dev *dev);
int mthca_init_pd_table(struct mthca_dev *dev);
int mthca_init_mr_table(struct mthca_dev *dev);
int mthca_init_eq_table(struct mthca_dev *dev);
int mthca_init_cq_table(struct mthca_dev *dev);
int mthca_init_srq_table(struct mthca_dev *dev);
int mthca_init_qp_table(struct mthca_dev *dev);
int mthca_init_av_table(struct mthca_dev *dev);
int mthca_init_mcg_table(struct mthca_dev *dev);

void mthca_cleanup_uar_table(struct mthca_dev *dev);
void mthca_cleanup_pd_table(struct mthca_dev *dev);
void mthca_cleanup_mr_table(struct mthca_dev *dev);
void mthca_cleanup_eq_table(struct mthca_dev *dev);
void mthca_cleanup_cq_table(struct mthca_dev *dev);
void mthca_cleanup_srq_table(struct mthca_dev *dev);
void mthca_cleanup_qp_table(struct mthca_dev *dev);
void mthca_cleanup_av_table(struct mthca_dev *dev);
void mthca_cleanup_mcg_table(struct mthca_dev *dev);

int mthca_register_device(struct mthca_dev *dev);
void mthca_unregister_device(struct mthca_dev *dev);

void mthca_start_catas_poll(struct mthca_dev *dev);
void mthca_stop_catas_poll(struct mthca_dev *dev);
int __mthca_restart_one(struct pci_dev *pdev);
int mthca_catas_init(void);
void mthca_catas_cleanup(void);

int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);

int mthca_pd_alloc(struct mthca_dev *dev, int privileged, struct mthca_pd *pd);
void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);

int mthca_write_mtt_size(struct mthca_dev *dev);

struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size);
void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt);
int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
		    int start_index, u64 *buffer_list, int list_len);
int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
		   u64 iova, u64 total_size, u32 access, struct mthca_mr *mr);
int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
			   u32 access, struct mthca_mr *mr);
int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
			u64 *buffer_list, int buffer_size_shift,
			int list_len, u64 iova, u64 total_size,
			u32 access, struct mthca_mr *mr);
void mthca_free_mr(struct mthca_dev *dev,  struct mthca_mr *mr);

int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
		    u32 access, struct mthca_fmr *fmr);
int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
			     int list_len, u64 iova);
void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
			     int list_len, u64 iova);
void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
int mthca_free_fmr(struct mthca_dev *dev,  struct mthca_fmr *fmr);

int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
void mthca_unmap_eq_icm(struct mthca_dev *dev);

int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
		  struct ib_wc *entry);
int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
int mthca_init_cq(struct mthca_dev *dev, int nent,
		  struct mthca_ucontext *ctx, u32 pdn,
		  struct mthca_cq *cq);
void mthca_free_cq(struct mthca_dev *dev,
		   struct mthca_cq *cq);
void mthca_cq_completion(struct mthca_dev *dev, u32 cqn);
void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
		    enum ib_event_type event_type);
void mthca_cq_clean(struct mthca_dev *dev, struct mthca_cq *cq, u32 qpn,
		    struct mthca_srq *srq);
void mthca_cq_resize_copy_cqes(struct mthca_cq *cq);
int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent);
void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe);

int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,
		    struct ib_srq_attr *attr, struct mthca_srq *srq);
void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq);
int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
		     enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
int mthca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr);
int mthca_max_srq_sge(struct mthca_dev *dev);
void mthca_srq_event(struct mthca_dev *dev, u32 srqn,
		     enum ib_event_type event_type);
void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr);
int mthca_tavor_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
			      struct ib_recv_wr **bad_wr);
int mthca_arbel_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
			      struct ib_recv_wr **bad_wr);

void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
		    enum ib_event_type event_type);
int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
		   struct ib_qp_init_attr *qp_init_attr);
int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
		    struct ib_udata *udata);
int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
			  struct ib_send_wr **bad_wr);
int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
			     struct ib_recv_wr **bad_wr);
int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
			  struct ib_send_wr **bad_wr);
int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
			     struct ib_recv_wr **bad_wr);
void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
			int index, int *dbd, __be32 *new_wqe);
int mthca_alloc_qp(struct mthca_dev *dev,
		   struct mthca_pd *pd,
		   struct mthca_cq *send_cq,
		   struct mthca_cq *recv_cq,
		   enum ib_qp_type type,
		   enum ib_sig_type send_policy,
		   struct ib_qp_cap *cap,
		   struct mthca_qp *qp);
int mthca_alloc_sqp(struct mthca_dev *dev,
		    struct mthca_pd *pd,
		    struct mthca_cq *send_cq,
		    struct mthca_cq *recv_cq,
		    enum ib_sig_type send_policy,
		    struct ib_qp_cap *cap,
		    int qpn,
		    int port,
		    struct mthca_sqp *sqp);
void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
int mthca_create_ah(struct mthca_dev *dev,
		    struct mthca_pd *pd,
		    struct ib_ah_attr *ah_attr,
		    struct mthca_ah *ah);
int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
		  struct ib_ud_header *header);
int mthca_ah_query(struct ib_ah *ibah, struct ib_ah_attr *attr);
int mthca_ah_grh_present(struct mthca_ah *ah);
u8 mthca_get_rate(struct mthca_dev *dev, int static_rate, u8 port);
enum ib_rate mthca_rate_to_ib(struct mthca_dev *dev, u8 mthca_rate, u8 port);

int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);

int mthca_process_mad(struct ib_device *ibdev,
		      int mad_flags,
		      u8 port_num,
		      struct ib_wc *in_wc,
		      struct ib_grh *in_grh,
		      struct ib_mad *in_mad,
		      struct ib_mad *out_mad);
int mthca_create_agents(struct mthca_dev *dev);
void mthca_free_agents(struct mthca_dev *dev);

static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
{
	return container_of(ibdev, struct mthca_dev, ib_dev);
}

static inline int mthca_is_memfree(struct mthca_dev *dev)
{
	return dev->mthca_flags & MTHCA_FLAG_MEMFREE;
}

#endif /* MTHCA_DEV_H */
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
cd4e8fb4	3	* Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4885bf64	4	* Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
2a1d9b7f RD	5	* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
2a1d9b7f RD	6	* Copyright (c) 2004 Voltaire, Inc. All rights reserved.
1da177e4 LT	7	*
	8	* This software is available to you under a choice of one of two
	9	* licenses. You may choose to be licensed under the terms of the GNU
	10	* General Public License (GPL) Version 2, available from the file
	11	* COPYING in the main directory of this source tree, or the
	12	* OpenIB.org BSD license below:
	13	*
	14	* Redistribution and use in source and binary forms, with or
	15	* without modification, are permitted provided that the following
	16	* conditions are met:
	17	*
	18	* - Redistributions of source code must retain the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer.
	21	*
	22	* - Redistributions in binary form must reproduce the above
	23	* copyright notice, this list of conditions and the following
	24	* disclaimer in the documentation and/or other materials
	25	* provided with the distribution.
	26	*
	27	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	28	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	29	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	30	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	31	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	32	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	33	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	34	* SOFTWARE.
	35	*
	36	* $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
	37	*/
	38
	39	#ifndef MTHCA_DEV_H
	40	#define MTHCA_DEV_H
	41
	42	#include <linux/spinlock.h>
	43	#include <linux/kernel.h>
	44	#include <linux/pci.h>
	45	#include <linux/dma-mapping.h>
de25968c	46	#include <linux/timer.h>
fd9cfdd1	47	#include <linux/mutex.h>
b3b30f5e	48	#include <linux/list.h>
fd9cfdd1	49
1da177e4 LT	50	#include <asm/semaphore.h>
	51
	52	#include "mthca_provider.h"
	53	#include "mthca_doorbell.h"
	54
	55	#define DRV_NAME "ib_mthca"
	56	#define PFX DRV_NAME ": "
00df1b2c RD	57	#define DRV_VERSION "0.08"
00df1b2c RD	58	#define DRV_RELDATE "February 14, 2006"
1da177e4	59
1da177e4 LT	60	enum {
	61	MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
	62	MTHCA_FLAG_SRQ = 1 << 2,
e57895d3 AB	63	MTHCA_FLAG_MSI_X = 1 << 3,
	64	MTHCA_FLAG_NO_LAM = 1 << 4,
	65	MTHCA_FLAG_FMR = 1 << 5,
	66	MTHCA_FLAG_MEMFREE = 1 << 6,
	67	MTHCA_FLAG_PCIE = 1 << 7,
	68	MTHCA_FLAG_SINAI_OPT = 1 << 8
1da177e4 LT	69	};
	70
	71	enum {
	72	MTHCA_MAX_PORTS = 2
	73	};
	74
2e8b981c MT	75	enum {
	76	MTHCA_BOARD_ID_LEN = 64
	77	};
	78
1da177e4 LT	79	enum {
	80	MTHCA_EQ_CONTEXT_SIZE = 0x40,
	81	MTHCA_CQ_CONTEXT_SIZE = 0x40,
	82	MTHCA_QP_CONTEXT_SIZE = 0x200,
	83	MTHCA_RDB_ENTRY_SIZE = 0x20,
	84	MTHCA_AV_SIZE = 0x20,
1a1eb6a6	85	MTHCA_MGM_ENTRY_SIZE = 0x100,
1da177e4 LT	86
	87	/* Arbel FW gives us these, but we need them for Tavor */
	88	MTHCA_MPT_ENTRY_SIZE = 0x40,
	89	MTHCA_MTT_SEG_SIZE = 0x40,
efaae8f7 JM	90
efaae8f7 JM	91	MTHCA_QP_PER_MGM = 4 * (MTHCA_MGM_ENTRY_SIZE / 16 - 2)
1da177e4 LT	92	};
	93
	94	enum {
	95	MTHCA_EQ_CMD,
	96	MTHCA_EQ_ASYNC,
	97	MTHCA_EQ_COMP,
	98	MTHCA_NUM_EQ
	99	};
	100
2a4443a6 MT	101	enum {
	102	MTHCA_OPCODE_NOP = 0x00,
	103	MTHCA_OPCODE_RDMA_WRITE = 0x08,
	104	MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
	105	MTHCA_OPCODE_SEND = 0x0a,
	106	MTHCA_OPCODE_SEND_IMM = 0x0b,
	107	MTHCA_OPCODE_RDMA_READ = 0x10,
	108	MTHCA_OPCODE_ATOMIC_CS = 0x11,
	109	MTHCA_OPCODE_ATOMIC_FA = 0x12,
	110	MTHCA_OPCODE_BIND_MW = 0x18,
	111	MTHCA_OPCODE_INVALID = 0xff
	112	};
	113
14abdffc EC	114	enum {
	115	MTHCA_CMD_USE_EVENTS = 1 << 0,
	116	MTHCA_CMD_POST_DOORBELLS = 1 << 1
	117	};
	118
	119	enum {
	120	MTHCA_CMD_NUM_DBELL_DWORDS = 8
	121	};
	122
1da177e4	123	struct mthca_cmd {
ed878458	124	struct pci_pool *pool;
fd9cfdd1	125	struct mutex hcr_mutex;
1da177e4 LT	126	struct semaphore poll_sem;
	127	struct semaphore event_sem;
	128	int max_cmds;
	129	spinlock_t context_lock;
	130	int free_head;
	131	struct mthca_cmd_context *context;
	132	u16 token_mask;
14abdffc EC	133	u32 flags;
	134	void __iomem *dbell_map;
	135	u16 dbell_offsets[MTHCA_CMD_NUM_DBELL_DWORDS];
1da177e4 LT	136	};
	137
	138	struct mthca_limits {
	139	int num_ports;
	140	int vl_cap;
	141	int mtu_cap;
	142	int gid_table_len;
	143	int pkey_table_len;
	144	int local_ca_ack_delay;
	145	int num_uars;
	146	int max_sg;
	147	int num_qps;
efaae8f7	148	int max_wqes;
77369ed3	149	int max_desc_sz;
efaae8f7	150	int max_qp_init_rdma;
1da177e4 LT	151	int reserved_qps;
1da177e4 LT	152	int num_srqs;
efaae8f7	153	int max_srq_wqes;
59fef3b1	154	int max_srq_sge;
1da177e4 LT	155	int reserved_srqs;
	156	int num_eecs;
	157	int reserved_eecs;
	158	int num_cqs;
efaae8f7	159	int max_cqes;
1da177e4 LT	160	int reserved_cqs;
	161	int num_eqs;
	162	int reserved_eqs;
	163	int num_mpts;
	164	int num_mtt_segs;
e0f5fdca	165	int fmr_reserved_mtts;
1da177e4 LT	166	int reserved_mtts;
	167	int reserved_mrws;
	168	int reserved_uars;
	169	int num_mgms;
	170	int num_amgms;
	171	int reserved_mcgs;
	172	int num_pds;
	173	int reserved_pds;
0f69ce1e	174	u32 page_size_cap;
33033b79	175	u32 flags;
bf6a9e31	176	u16 stat_rate_support;
da6561c2	177	u8 port_width_cap;
1da177e4 LT	178	};
	179
	180	struct mthca_alloc {
	181	u32 last;
	182	u32 top;
	183	u32 max;
	184	u32 mask;
	185	spinlock_t lock;
	186	unsigned long *table;
	187	};
	188
	189	struct mthca_array {
	190	struct {
	191	void **page;
	192	int used;
	193	} *page_list;
	194	};
	195
	196	struct mthca_uar_table {
	197	struct mthca_alloc alloc;
	198	u64 uarc_base;
	199	int uarc_size;
	200	};
	201
	202	struct mthca_pd_table {
	203	struct mthca_alloc alloc;
	204	};
	205
9095e208 MT	206	struct mthca_buddy {
	207	unsigned long **bits;
	208	int max_order;
	209	spinlock_t lock;
	210	};
	211
1da177e4 LT	212	struct mthca_mr_table {
1da177e4 LT	213	struct mthca_alloc mpt_alloc;
e0f5fdca MT	214	struct mthca_buddy mtt_buddy;
e0f5fdca MT	215	struct mthca_buddy *fmr_mtt_buddy;
1da177e4	216	u64 mtt_base;
e0f5fdca	217	u64 mpt_base;
1da177e4 LT	218	struct mthca_icm_table *mtt_table;
1da177e4 LT	219	struct mthca_icm_table *mpt_table;
e0f5fdca MT	220	struct {
	221	void __iomem *mpt_base;
	222	void __iomem *mtt_base;
	223	struct mthca_buddy mtt_buddy;
	224	} tavor_fmr;
1da177e4 LT	225	};
	226
	227	struct mthca_eq_table {
	228	struct mthca_alloc alloc;
	229	void __iomem *clr_int;
	230	u32 clr_mask;
	231	u32 arm_mask;
	232	struct mthca_eq eq[MTHCA_NUM_EQ];
	233	u64 icm_virt;
	234	struct page *icm_page;
	235	dma_addr_t icm_dma;
	236	int have_irq;
	237	u8 inta_pin;
	238	};
	239
	240	struct mthca_cq_table {
	241	struct mthca_alloc alloc;
	242	spinlock_t lock;
	243	struct mthca_array cq;
	244	struct mthca_icm_table *table;
	245	};
	246
ec34a922 RD	247	struct mthca_srq_table {
	248	struct mthca_alloc alloc;
	249	spinlock_t lock;
	250	struct mthca_array srq;
	251	struct mthca_icm_table *table;
	252	};
	253
1da177e4 LT	254	struct mthca_qp_table {
	255	struct mthca_alloc alloc;
	256	u32 rdb_base;
	257	int rdb_shift;
	258	int sqp_start;
	259	spinlock_t lock;
	260	struct mthca_array qp;
	261	struct mthca_icm_table *qp_table;
	262	struct mthca_icm_table *eqp_table;
08aeb14e	263	struct mthca_icm_table *rdb_table;
1da177e4 LT	264	};
	265
	266	struct mthca_av_table {
	267	struct pci_pool *pool;
	268	int num_ddr_avs;
	269	u64 ddr_av_base;
	270	void __iomem *av_map;
	271	struct mthca_alloc alloc;
	272	};
	273
	274	struct mthca_mcg_table {
fd9cfdd1	275	struct mutex mutex;
1da177e4 LT	276	struct mthca_alloc alloc;
	277	struct mthca_icm_table *table;
	278	};
	279
3d155f8c RD	280	struct mthca_catas_err {
	281	u64 addr;
	282	u32 __iomem *map;
	283	unsigned long stop;
	284	u32 size;
	285	struct timer_list timer;
b3b30f5e	286	struct list_head list;
3d155f8c RD	287	};
3d155f8c RD	288
b3b30f5e JM	289	extern struct mutex mthca_device_mutex;
b3b30f5e JM	290
1da177e4 LT	291	struct mthca_dev {
	292	struct ib_device ib_dev;
	293	struct pci_dev *pdev;
	294
	295	int hca_type;
	296	unsigned long mthca_flags;
	297	unsigned long device_cap_flags;
	298
	299	u32 rev_id;
2e8b981c	300	char board_id[MTHCA_BOARD_ID_LEN];
1da177e4 LT	301
	302	/* firmware info */
	303	u64 fw_ver;
	304	union {
	305	struct {
	306	u64 fw_start;
	307	u64 fw_end;
	308	} tavor;
	309	struct {
	310	u64 clr_int_base;
	311	u64 eq_arm_base;
	312	u64 eq_set_ci_base;
	313	struct mthca_icm *fw_icm;
	314	struct mthca_icm *aux_icm;
	315	u16 fw_pages;
	316	} arbel;
	317	} fw;
	318
	319	u64 ddr_start;
	320	u64 ddr_end;
	321
	322	MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
fd9cfdd1	323	struct mutex cap_mask_mutex;
1da177e4 LT	324
	325	void __iomem *hcr;
	326	void __iomem *kar;
	327	void __iomem *clr_base;
	328	union {
	329	struct {
	330	void __iomem *ecr_base;
	331	} tavor;
	332	struct {
	333	void __iomem *eq_arm;
	334	void __iomem *eq_set_ci_base;
	335	} arbel;
	336	} eq_regs;
	337
	338	struct mthca_cmd cmd;
	339	struct mthca_limits limits;
	340
	341	struct mthca_uar_table uar_table;
	342	struct mthca_pd_table pd_table;
	343	struct mthca_mr_table mr_table;
	344	struct mthca_eq_table eq_table;
	345	struct mthca_cq_table cq_table;
ec34a922	346	struct mthca_srq_table srq_table;
1da177e4 LT	347	struct mthca_qp_table qp_table;
	348	struct mthca_av_table av_table;
	349	struct mthca_mcg_table mcg_table;
	350
3d155f8c RD	351	struct mthca_catas_err catas_err;
3d155f8c RD	352
1da177e4 LT	353	struct mthca_uar driver_uar;
	354	struct mthca_db_table *db_tab;
	355	struct mthca_pd driver_pd;
	356	struct mthca_mr driver_mr;
	357
	358	struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
	359	struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
	360	spinlock_t sm_lock;
bf6a9e31	361	u8 rate[MTHCA_MAX_PORTS];
1da177e4 LT	362	};
1da177e4 LT	363
227c939b RD	364	#ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
	365	extern int mthca_debug_level;
	366
	367	#define mthca_dbg(mdev, format, arg...) \
	368	do { \
	369	if (mthca_debug_level) \
	370	dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
	371	} while (0)
	372
	373	#else /* CONFIG_INFINIBAND_MTHCA_DEBUG */
	374
	375	#define mthca_dbg(mdev, format, arg...) do { (void) mdev; } while (0)
	376
	377	#endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
	378
1da177e4 LT	379	#define mthca_err(mdev, format, arg...) \
	380	dev_err(&mdev->pdev->dev, format, ## arg)
	381	#define mthca_info(mdev, format, arg...) \
	382	dev_info(&mdev->pdev->dev, format, ## arg)
	383	#define mthca_warn(mdev, format, arg...) \
	384	dev_warn(&mdev->pdev->dev, format, ## arg)
	385
	386	extern void __buggy_use_of_MTHCA_GET(void);
	387	extern void __buggy_use_of_MTHCA_PUT(void);
	388
	389	#define MTHCA_GET(dest, source, offset) \
	390	do { \
	391	void __p = (char ) (source) + (offset); \
	392	switch (sizeof (dest)) { \
	393	case 1: (dest) = (u8 ) __p; break; \
	394	case 2: (dest) = be16_to_cpup(__p); break; \
	395	case 4: (dest) = be32_to_cpup(__p); break; \
	396	case 8: (dest) = be64_to_cpup(__p); break; \
	397	default: __buggy_use_of_MTHCA_GET(); \
	398	} \
	399	} while (0)
	400
	401	#define MTHCA_PUT(dest, source, offset) \
	402	do { \
97f52eb4	403	void __d = ((char ) (dest) + (offset)); \
1da177e4	404	switch (sizeof(source)) { \
97f52eb4 SH	405	case 1: (u8 ) __d = (source); break; \
	406	case 2: (__be16 ) __d = cpu_to_be16(source); break; \
	407	case 4: (__be32 ) __d = cpu_to_be32(source); break; \
	408	case 8: (__be64 ) __d = cpu_to_be64(source); break; \
	409	default: __buggy_use_of_MTHCA_PUT(); \
1da177e4 LT	410	} \
	411	} while (0)
	412
	413	int mthca_reset(struct mthca_dev *mdev);
	414
	415	u32 mthca_alloc(struct mthca_alloc *alloc);
	416	void mthca_free(struct mthca_alloc *alloc, u32 obj);
	417	int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
	418	u32 reserved);
	419	void mthca_alloc_cleanup(struct mthca_alloc *alloc);
	420	void mthca_array_get(struct mthca_array array, int index);
	421	int mthca_array_set(struct mthca_array array, int index, void value);
	422	void mthca_array_clear(struct mthca_array *array, int index);
	423	int mthca_array_init(struct mthca_array *array, int nent);
	424	void mthca_array_cleanup(struct mthca_array *array, int nent);
87b81670 RD	425	int mthca_buf_alloc(struct mthca_dev *dev, int size, int max_direct,
	426	union mthca_buf buf, int is_direct, struct mthca_pd *pd,
	427	int hca_write, struct mthca_mr *mr);
	428	void mthca_buf_free(struct mthca_dev dev, int size, union mthca_buf buf,
	429	int is_direct, struct mthca_mr *mr);
1da177e4 LT	430
	431	int mthca_init_uar_table(struct mthca_dev *dev);
	432	int mthca_init_pd_table(struct mthca_dev *dev);
	433	int mthca_init_mr_table(struct mthca_dev *dev);
	434	int mthca_init_eq_table(struct mthca_dev *dev);
	435	int mthca_init_cq_table(struct mthca_dev *dev);
ec34a922	436	int mthca_init_srq_table(struct mthca_dev *dev);
1da177e4 LT	437	int mthca_init_qp_table(struct mthca_dev *dev);
	438	int mthca_init_av_table(struct mthca_dev *dev);
	439	int mthca_init_mcg_table(struct mthca_dev *dev);
	440
	441	void mthca_cleanup_uar_table(struct mthca_dev *dev);
	442	void mthca_cleanup_pd_table(struct mthca_dev *dev);
	443	void mthca_cleanup_mr_table(struct mthca_dev *dev);
	444	void mthca_cleanup_eq_table(struct mthca_dev *dev);
	445	void mthca_cleanup_cq_table(struct mthca_dev *dev);
ec34a922	446	void mthca_cleanup_srq_table(struct mthca_dev *dev);
1da177e4 LT	447	void mthca_cleanup_qp_table(struct mthca_dev *dev);
	448	void mthca_cleanup_av_table(struct mthca_dev *dev);
	449	void mthca_cleanup_mcg_table(struct mthca_dev *dev);
	450
	451	int mthca_register_device(struct mthca_dev *dev);
	452	void mthca_unregister_device(struct mthca_dev *dev);
	453
3d155f8c RD	454	void mthca_start_catas_poll(struct mthca_dev *dev);
3d155f8c RD	455	void mthca_stop_catas_poll(struct mthca_dev *dev);
b3b30f5e JM	456	int __mthca_restart_one(struct pci_dev *pdev);
	457	int mthca_catas_init(void);
	458	void mthca_catas_cleanup(void);
3d155f8c	459
1da177e4 LT	460	int mthca_uar_alloc(struct mthca_dev dev, struct mthca_uar uar);
	461	void mthca_uar_free(struct mthca_dev dev, struct mthca_uar uar);
	462
99264c1e	463	int mthca_pd_alloc(struct mthca_dev dev, int privileged, struct mthca_pd pd);
1da177e4 LT	464	void mthca_pd_free(struct mthca_dev dev, struct mthca_pd pd);
1da177e4 LT	465
b2875d4c MT	466	int mthca_write_mtt_size(struct mthca_dev *dev);
b2875d4c MT	467
d56d6f95 RD	468	struct mthca_mtt mthca_alloc_mtt(struct mthca_dev dev, int size);
	469	void mthca_free_mtt(struct mthca_dev dev, struct mthca_mtt mtt);
	470	int mthca_write_mtt(struct mthca_dev dev, struct mthca_mtt mtt,
	471	int start_index, u64 *buffer_list, int list_len);
	472	int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
	473	u64 iova, u64 total_size, u32 access, struct mthca_mr *mr);
1da177e4 LT	474	int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
	475	u32 access, struct mthca_mr *mr);
	476	int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
	477	u64 *buffer_list, int buffer_size_shift,
	478	int list_len, u64 iova, u64 total_size,
	479	u32 access, struct mthca_mr *mr);
e0f5fdca MT	480	void mthca_free_mr(struct mthca_dev dev, struct mthca_mr mr);
	481
	482	int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
	483	u32 access, struct mthca_fmr *fmr);
	484	int mthca_tavor_map_phys_fmr(struct ib_fmr ibfmr, u64 page_list,
	485	int list_len, u64 iova);
	486	void mthca_tavor_fmr_unmap(struct mthca_dev dev, struct mthca_fmr fmr);
	487	int mthca_arbel_map_phys_fmr(struct ib_fmr ibfmr, u64 page_list,
	488	int list_len, u64 iova);
	489	void mthca_arbel_fmr_unmap(struct mthca_dev dev, struct mthca_fmr fmr);
	490	int mthca_free_fmr(struct mthca_dev dev, struct mthca_fmr fmr);
1da177e4 LT	491
	492	int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
	493	void mthca_unmap_eq_icm(struct mthca_dev *dev);
	494
	495	int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
	496	struct ib_wc *entry);
ed23a727 RD	497	int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
ed23a727 RD	498	int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
1da177e4	499	int mthca_init_cq(struct mthca_dev *dev, int nent,
74c2174e	500	struct mthca_ucontext *ctx, u32 pdn,
1da177e4 LT	501	struct mthca_cq *cq);
	502	void mthca_free_cq(struct mthca_dev *dev,
	503	struct mthca_cq *cq);
affcd505 MT	504	void mthca_cq_completion(struct mthca_dev *dev, u32 cqn);
	505	void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
	506	enum ib_event_type event_type);
a3285aa4	507	void mthca_cq_clean(struct mthca_dev dev, struct mthca_cq cq, u32 qpn,
ec34a922	508	struct mthca_srq *srq);
4885bf64 RD	509	void mthca_cq_resize_copy_cqes(struct mthca_cq *cq);
	510	int mthca_alloc_cq_buf(struct mthca_dev dev, struct mthca_cq_buf buf, int nent);
	511	void mthca_free_cq_buf(struct mthca_dev dev, struct mthca_cq_buf buf, int cqe);
ec34a922 RD	512
	513	int mthca_alloc_srq(struct mthca_dev dev, struct mthca_pd pd,
	514	struct ib_srq_attr attr, struct mthca_srq srq);
	515	void mthca_free_srq(struct mthca_dev dev, struct mthca_srq srq);
90f104da	516	int mthca_modify_srq(struct ib_srq ibsrq, struct ib_srq_attr attr,
9bc57e2d	517	enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
8ebe5077	518	int mthca_query_srq(struct ib_srq srq, struct ib_srq_attr srq_attr);
59fef3b1	519	int mthca_max_srq_sge(struct mthca_dev *dev);
ec34a922 RD	520	void mthca_srq_event(struct mthca_dev *dev, u32 srqn,
	521	enum ib_event_type event_type);
	522	void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr);
	523	int mthca_tavor_post_srq_recv(struct ib_srq srq, struct ib_recv_wr wr,
	524	struct ib_recv_wr **bad_wr);
	525	int mthca_arbel_post_srq_recv(struct ib_srq srq, struct ib_recv_wr wr,
	526	struct ib_recv_wr **bad_wr);
1da177e4 LT	527
	528	void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
	529	enum ib_event_type event_type);
8ebe5077 EC	530	int mthca_query_qp(struct ib_qp ibqp, struct ib_qp_attr qp_attr, int qp_attr_mask,
8ebe5077 EC	531	struct ib_qp_init_attr *qp_init_attr);
9bc57e2d RC	532	int mthca_modify_qp(struct ib_qp ibqp, struct ib_qp_attr attr, int attr_mask,
9bc57e2d RC	533	struct ib_udata *udata);
1da177e4 LT	534	int mthca_tavor_post_send(struct ib_qp ibqp, struct ib_send_wr wr,
	535	struct ib_send_wr **bad_wr);
	536	int mthca_tavor_post_receive(struct ib_qp ibqp, struct ib_recv_wr wr,
	537	struct ib_recv_wr **bad_wr);
	538	int mthca_arbel_post_send(struct ib_qp ibqp, struct ib_send_wr wr,
	539	struct ib_send_wr **bad_wr);
	540	int mthca_arbel_post_receive(struct ib_qp ibqp, struct ib_recv_wr wr,
	541	struct ib_recv_wr **bad_wr);
d9b98b0f RD	542	void mthca_free_err_wqe(struct mthca_dev dev, struct mthca_qp qp, int is_send,
d9b98b0f RD	543	int index, int dbd, __be32 new_wqe);
1da177e4 LT	544	int mthca_alloc_qp(struct mthca_dev *dev,
	545	struct mthca_pd *pd,
	546	struct mthca_cq *send_cq,
	547	struct mthca_cq *recv_cq,
	548	enum ib_qp_type type,
	549	enum ib_sig_type send_policy,
80c8ec2c	550	struct ib_qp_cap *cap,
1da177e4 LT	551	struct mthca_qp *qp);
	552	int mthca_alloc_sqp(struct mthca_dev *dev,
	553	struct mthca_pd *pd,
	554	struct mthca_cq *send_cq,
	555	struct mthca_cq *recv_cq,
	556	enum ib_sig_type send_policy,
80c8ec2c	557	struct ib_qp_cap *cap,
1da177e4 LT	558	int qpn,
	559	int port,
	560	struct mthca_sqp *sqp);
	561	void mthca_free_qp(struct mthca_dev dev, struct mthca_qp qp);
	562	int mthca_create_ah(struct mthca_dev *dev,
	563	struct mthca_pd *pd,
	564	struct ib_ah_attr *ah_attr,
	565	struct mthca_ah *ah);
	566	int mthca_destroy_ah(struct mthca_dev dev, struct mthca_ah ah);
	567	int mthca_read_ah(struct mthca_dev dev, struct mthca_ah ah,
	568	struct ib_ud_header *header);
1d89b1ae	569	int mthca_ah_query(struct ib_ah ibah, struct ib_ah_attr attr);
9eacee2a	570	int mthca_ah_grh_present(struct mthca_ah *ah);
bf6a9e31 JM	571	u8 mthca_get_rate(struct mthca_dev *dev, int static_rate, u8 port);
bf6a9e31 JM	572	enum ib_rate mthca_rate_to_ib(struct mthca_dev *dev, u8 mthca_rate, u8 port);
1da177e4 LT	573
	574	int mthca_multicast_attach(struct ib_qp ibqp, union ib_gid gid, u16 lid);
	575	int mthca_multicast_detach(struct ib_qp ibqp, union ib_gid gid, u16 lid);
	576
	577	int mthca_process_mad(struct ib_device *ibdev,
	578	int mad_flags,
	579	u8 port_num,
	580	struct ib_wc *in_wc,
	581	struct ib_grh *in_grh,
	582	struct ib_mad *in_mad,
	583	struct ib_mad *out_mad);
	584	int mthca_create_agents(struct mthca_dev *dev);
	585	void mthca_free_agents(struct mthca_dev *dev);
	586
	587	static inline struct mthca_dev to_mdev(struct ib_device ibdev)
	588	{
	589	return container_of(ibdev, struct mthca_dev, ib_dev);
	590	}
	591
d10ddbf6 RD	592	static inline int mthca_is_memfree(struct mthca_dev *dev)
d10ddbf6 RD	593	{
68a3c212	594	return dev->mthca_flags & MTHCA_FLAG_MEMFREE;
d10ddbf6 RD	595	}
d10ddbf6 RD	596
1da177e4	597	#endif /* MTHCA_DEV_H */