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[PATCH] IB/mthca: Handle context tables smaller than our chunk size
[linux-2.6-block.git] / drivers / infiniband / hw / mthca / mthca_cq.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
cd4e8fb4 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
74c2174e 4 * Copyright (c) 2005 Cisco Systems, Inc. All rights reserved.
2a1d9b7f
RD		 5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
1da177e4
LT		 7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 *
36 * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
37 */
38
39#include <linux/init.h>
40#include <linux/hardirq.h>
41
42#include <ib_pack.h>
43
44#include "mthca_dev.h"
45#include "mthca_cmd.h"
46#include "mthca_memfree.h"
47
48enum {
49 MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
50};
51
52enum {
53 MTHCA_CQ_ENTRY_SIZE = 0x20
54};
55
56/*
57 * Must be packed because start is 64 bits but only aligned to 32 bits.
58 */
59struct mthca_cq_context {
97f52eb4
SH		 60 __be32 flags;
61 __be64 start;
62 __be32 logsize_usrpage;
63 __be32 error_eqn; /* Tavor only */
64 __be32 comp_eqn;
65 __be32 pd;
66 __be32 lkey;
67 __be32 last_notified_index;
68 __be32 solicit_producer_index;
69 __be32 consumer_index;
70 __be32 producer_index;
71 __be32 cqn;
72 __be32 ci_db; /* Arbel only */
73 __be32 state_db; /* Arbel only */
74 u32 reserved;
1da177e4
LT		 75} __attribute__((packed));
76
77#define MTHCA_CQ_STATUS_OK ( 0 << 28)
78#define MTHCA_CQ_STATUS_OVERFLOW ( 9 << 28)
79#define MTHCA_CQ_STATUS_WRITE_FAIL (10 << 28)
80#define MTHCA_CQ_FLAG_TR ( 1 << 18)
81#define MTHCA_CQ_FLAG_OI ( 1 << 17)
82#define MTHCA_CQ_STATE_DISARMED ( 0 << 8)
83#define MTHCA_CQ_STATE_ARMED ( 1 << 8)
84#define MTHCA_CQ_STATE_ARMED_SOL ( 4 << 8)
85#define MTHCA_EQ_STATE_FIRED (10 << 8)
86
87enum {
88 MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
89};
90
91enum {
92 SYNDROME_LOCAL_LENGTH_ERR = 0x01,
93 SYNDROME_LOCAL_QP_OP_ERR = 0x02,
94 SYNDROME_LOCAL_EEC_OP_ERR = 0x03,
95 SYNDROME_LOCAL_PROT_ERR = 0x04,
96 SYNDROME_WR_FLUSH_ERR = 0x05,
97 SYNDROME_MW_BIND_ERR = 0x06,
98 SYNDROME_BAD_RESP_ERR = 0x10,
99 SYNDROME_LOCAL_ACCESS_ERR = 0x11,
100 SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
101 SYNDROME_REMOTE_ACCESS_ERR = 0x13,
102 SYNDROME_REMOTE_OP_ERR = 0x14,
103 SYNDROME_RETRY_EXC_ERR = 0x15,
104 SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
105 SYNDROME_LOCAL_RDD_VIOL_ERR = 0x20,
106 SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
107 SYNDROME_REMOTE_ABORTED_ERR = 0x22,
108 SYNDROME_INVAL_EECN_ERR = 0x23,
109 SYNDROME_INVAL_EEC_STATE_ERR = 0x24
110};
111
112struct mthca_cqe {
97f52eb4
SH		 113 __be32 my_qpn;
114 __be32 my_ee;
115 __be32 rqpn;
116 __be16 sl_g_mlpath;
117 __be16 rlid;
118 __be32 imm_etype_pkey_eec;
119 __be32 byte_cnt;
120 __be32 wqe;
121 u8 opcode;
122 u8 is_send;
123 u8 reserved;
124 u8 owner;
1da177e4
LT		 125};
126
127struct mthca_err_cqe {
97f52eb4
SH		 128 __be32 my_qpn;
129 u32 reserved1[3];
130 u8 syndrome;
131 u8 reserved2;
132 __be16 db_cnt;
133 u32 reserved3;
134 __be32 wqe;
135 u8 opcode;
136 u8 reserved4[2];
137 u8 owner;
1da177e4
LT		 138};
139
140#define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7)
141#define MTHCA_CQ_ENTRY_OWNER_HW (1 << 7)
142
143#define MTHCA_TAVOR_CQ_DB_INC_CI (1 << 24)
144#define MTHCA_TAVOR_CQ_DB_REQ_NOT (2 << 24)
145#define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL (3 << 24)
146#define MTHCA_TAVOR_CQ_DB_SET_CI (4 << 24)
147#define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
148
149#define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL (1 << 24)
150#define MTHCA_ARBEL_CQ_DB_REQ_NOT (2 << 24)
151#define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
152
153static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
154{
155 if (cq->is_direct)
156 return cq->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE);
157 else
158 return cq->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf
159 + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE;
160}
161
162static inline struct mthca_cqe *cqe_sw(struct mthca_cq *cq, int i)
163{
164 struct mthca_cqe *cqe = get_cqe(cq, i);
165 return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
166}
167
168static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
169{
170 return cqe_sw(cq, cq->cons_index & cq->ibcq.cqe);
171}
172
173static inline void set_cqe_hw(struct mthca_cqe *cqe)
174{
175 cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
176}
177
bb2af78b
RD		 178static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr)
179{
180 __be32 *cqe = cqe_ptr;
181
182 (void) cqe; /* avoid warning if mthca_dbg compiled away... */
183 mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
184 be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]),
185 be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]),
186 be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7]));
187}
188
1da177e4
LT		 189/*
190 * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
191 * should be correct before calling update_cons_index().
192 */
193static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
194 int incr)
195{
97f52eb4 196 __be32 doorbell[2];
1da177e4 197
d10ddbf6 198 if (mthca_is_memfree(dev)) {
1da177e4
LT		 199 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
200 wmb();
201 } else {
202 doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn);
203 doorbell[1] = cpu_to_be32(incr - 1);
204
205 mthca_write64(doorbell,
206 dev->kar + MTHCA_CQ_DOORBELL,
207 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
208 }
209}
210
211void mthca_cq_event(struct mthca_dev *dev, u32 cqn)
212{
213 struct mthca_cq *cq;
214
215 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
216
217 if (!cq) {
218 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
219 return;
220 }
221
222 ++cq->arm_sn;
223
224 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
225}
226
227void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn)
228{
229 struct mthca_cq *cq;
230 struct mthca_cqe *cqe;
231 int prod_index;
232 int nfreed = 0;
233
234 spin_lock_irq(&dev->cq_table.lock);
235 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
236 if (cq)
237 atomic_inc(&cq->refcount);
238 spin_unlock_irq(&dev->cq_table.lock);
239
240 if (!cq)
241 return;
242
243 spin_lock_irq(&cq->lock);
244
245 /*
246 * First we need to find the current producer index, so we
247 * know where to start cleaning from. It doesn't matter if HW
248 * adds new entries after this loop -- the QP we're worried
249 * about is already in RESET, so the new entries won't come
250 * from our QP and therefore don't need to be checked.
251 */
252 for (prod_index = cq->cons_index;
253 cqe_sw(cq, prod_index & cq->ibcq.cqe);
254 ++prod_index)
255 if (prod_index == cq->cons_index + cq->ibcq.cqe)
256 break;
257
258 if (0)
259 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
260 qpn, cqn, cq->cons_index, prod_index);
261
262 /*
263 * Now sweep backwards through the CQ, removing CQ entries
264 * that match our QP by copying older entries on top of them.
265 */
266 while (prod_index > cq->cons_index) {
267 cqe = get_cqe(cq, (prod_index - 1) & cq->ibcq.cqe);
268 if (cqe->my_qpn == cpu_to_be32(qpn))
269 ++nfreed;
270 else if (nfreed)
271 memcpy(get_cqe(cq, (prod_index - 1 + nfreed) &
272 cq->ibcq.cqe),
273 cqe,
274 MTHCA_CQ_ENTRY_SIZE);
275 --prod_index;
276 }
277
278 if (nfreed) {
279 wmb();
280 cq->cons_index += nfreed;
281 update_cons_index(dev, cq, nfreed);
282 }
283
284 spin_unlock_irq(&cq->lock);
285 if (atomic_dec_and_test(&cq->refcount))
286 wake_up(&cq->wait);
287}
288
289static int handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
290 struct mthca_qp *qp, int wqe_index, int is_send,
291 struct mthca_err_cqe *cqe,
292 struct ib_wc *entry, int *free_cqe)
293{
294 int err;
295 int dbd;
97f52eb4 296 __be32 new_wqe;
1da177e4 297
bb2af78b
RD		 298 if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) {
299 mthca_dbg(dev, "local QP operation err "
300 "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
301 be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe),
302 cq->cqn, cq->cons_index);
303 dump_cqe(dev, cqe);
1da177e4
LT		 304 }
305
306 /*
307 * For completions in error, only work request ID, status (and
308 * freed resource count for RD) have to be set.
309 */
310 switch (cqe->syndrome) {
311 case SYNDROME_LOCAL_LENGTH_ERR:
312 entry->status = IB_WC_LOC_LEN_ERR;
313 break;
314 case SYNDROME_LOCAL_QP_OP_ERR:
315 entry->status = IB_WC_LOC_QP_OP_ERR;
316 break;
317 case SYNDROME_LOCAL_EEC_OP_ERR:
318 entry->status = IB_WC_LOC_EEC_OP_ERR;
319 break;
320 case SYNDROME_LOCAL_PROT_ERR:
321 entry->status = IB_WC_LOC_PROT_ERR;
322 break;
323 case SYNDROME_WR_FLUSH_ERR:
324 entry->status = IB_WC_WR_FLUSH_ERR;
325 break;
326 case SYNDROME_MW_BIND_ERR:
327 entry->status = IB_WC_MW_BIND_ERR;
328 break;
329 case SYNDROME_BAD_RESP_ERR:
330 entry->status = IB_WC_BAD_RESP_ERR;
331 break;
332 case SYNDROME_LOCAL_ACCESS_ERR:
333 entry->status = IB_WC_LOC_ACCESS_ERR;
334 break;
335 case SYNDROME_REMOTE_INVAL_REQ_ERR:
336 entry->status = IB_WC_REM_INV_REQ_ERR;
337 break;
338 case SYNDROME_REMOTE_ACCESS_ERR:
339 entry->status = IB_WC_REM_ACCESS_ERR;
340 break;
341 case SYNDROME_REMOTE_OP_ERR:
342 entry->status = IB_WC_REM_OP_ERR;
343 break;
344 case SYNDROME_RETRY_EXC_ERR:
345 entry->status = IB_WC_RETRY_EXC_ERR;
346 break;
347 case SYNDROME_RNR_RETRY_EXC_ERR:
348 entry->status = IB_WC_RNR_RETRY_EXC_ERR;
349 break;
350 case SYNDROME_LOCAL_RDD_VIOL_ERR:
351 entry->status = IB_WC_LOC_RDD_VIOL_ERR;
352 break;
353 case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
354 entry->status = IB_WC_REM_INV_RD_REQ_ERR;
355 break;
356 case SYNDROME_REMOTE_ABORTED_ERR:
357 entry->status = IB_WC_REM_ABORT_ERR;
358 break;
359 case SYNDROME_INVAL_EECN_ERR:
360 entry->status = IB_WC_INV_EECN_ERR;
361 break;
362 case SYNDROME_INVAL_EEC_STATE_ERR:
363 entry->status = IB_WC_INV_EEC_STATE_ERR;
364 break;
365 default:
366 entry->status = IB_WC_GENERAL_ERR;
367 break;
368 }
369
288bdeb4
RD		 370 /*
371 * Mem-free HCAs always generate one CQE per WQE, even in the
372 * error case, so we don't have to check the doorbell count, etc.
373 */
374 if (mthca_is_memfree(dev))
375 return 0;
376
1da177e4
LT		 377 err = mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
378 if (err)
379 return err;
380
381 /*
382 * If we're at the end of the WQE chain, or we've used up our
383 * doorbell count, free the CQE. Otherwise just update it for
384 * the next poll operation.
385 */
288bdeb4 386 if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
1da177e4
LT		 387 return 0;
388
389 cqe->db_cnt = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd);
390 cqe->wqe = new_wqe;
391 cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
392
393 *free_cqe = 0;
394
395 return 0;
396}
397
1da177e4
LT		 398static inline int mthca_poll_one(struct mthca_dev *dev,
399 struct mthca_cq *cq,
400 struct mthca_qp **cur_qp,
401 int *freed,
402 struct ib_wc *entry)
403{
404 struct mthca_wq *wq;
405 struct mthca_cqe *cqe;
406 int wqe_index;
407 int is_error;
408 int is_send;
409 int free_cqe = 1;
410 int err = 0;
411
412 cqe = next_cqe_sw(cq);
413 if (!cqe)
414 return -EAGAIN;
415
416 /*
417 * Make sure we read CQ entry contents after we've checked the
418 * ownership bit.
419 */
420 rmb();
421
422 if (0) {
423 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n",
424 cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn),
425 be32_to_cpu(cqe->wqe));
bb2af78b 426 dump_cqe(dev, cqe);
1da177e4
LT		 427 }
428
429 is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
430 MTHCA_ERROR_CQE_OPCODE_MASK;
431 is_send = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
432
433 if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) {
434 /*
435 * We do not have to take the QP table lock here,
436 * because CQs will be locked while QPs are removed
437 * from the table.
438 */
439 *cur_qp = mthca_array_get(&dev->qp_table.qp,
440 be32_to_cpu(cqe->my_qpn) &
441 (dev->limits.num_qps - 1));
442 if (!*cur_qp) {
443 mthca_warn(dev, "CQ entry for unknown QP %06x\n",
444 be32_to_cpu(cqe->my_qpn) & 0xffffff);
445 err = -EINVAL;
446 goto out;
447 }
448 }
449
450 entry->qp_num = (*cur_qp)->qpn;
451
452 if (is_send) {
453 wq = &(*cur_qp)->sq;
454 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset)
455 >> wq->wqe_shift);
456 entry->wr_id = (*cur_qp)->wrid[wqe_index +
457 (*cur_qp)->rq.max];
458 } else {
459 wq = &(*cur_qp)->rq;
460 wqe_index = be32_to_cpu(cqe->wqe) >> wq->wqe_shift;
461 entry->wr_id = (*cur_qp)->wrid[wqe_index];
462 }
463
464 if (wq->last_comp < wqe_index)
465 wq->tail += wqe_index - wq->last_comp;
466 else
467 wq->tail += wqe_index + wq->max - wq->last_comp;
468
469 wq->last_comp = wqe_index;
470
471 if (0)
472 mthca_dbg(dev, "%s completion for QP %06x, index %d (nr %d)\n",
473 is_send ? "Send" : "Receive",
474 (*cur_qp)->qpn, wqe_index, wq->max);
475
476 if (is_error) {
477 err = handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
478 (struct mthca_err_cqe *) cqe,
479 entry, &free_cqe);
480 goto out;
481 }
482
483 if (is_send) {
2a4443a6
MT		 484 entry->wc_flags = 0;
485 switch (cqe->opcode) {
486 case MTHCA_OPCODE_RDMA_WRITE:
487 entry->opcode = IB_WC_RDMA_WRITE;
488 break;
489 case MTHCA_OPCODE_RDMA_WRITE_IMM:
490 entry->opcode = IB_WC_RDMA_WRITE;
491 entry->wc_flags |= IB_WC_WITH_IMM;
492 break;
493 case MTHCA_OPCODE_SEND:
494 entry->opcode = IB_WC_SEND;
495 break;
496 case MTHCA_OPCODE_SEND_IMM:
497 entry->opcode = IB_WC_SEND;
498 entry->wc_flags |= IB_WC_WITH_IMM;
499 break;
500 case MTHCA_OPCODE_RDMA_READ:
501 entry->opcode = IB_WC_RDMA_READ;
502 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
503 break;
504 case MTHCA_OPCODE_ATOMIC_CS:
505 entry->opcode = IB_WC_COMP_SWAP;
506 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
507 break;
508 case MTHCA_OPCODE_ATOMIC_FA:
509 entry->opcode = IB_WC_FETCH_ADD;
510 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
511 break;
512 case MTHCA_OPCODE_BIND_MW:
513 entry->opcode = IB_WC_BIND_MW;
514 break;
515 default:
516 entry->opcode = MTHCA_OPCODE_INVALID;
517 break;
518 }
1da177e4
LT		 519 } else {
520 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
521 switch (cqe->opcode & 0x1f) {
522 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
523 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
524 entry->wc_flags = IB_WC_WITH_IMM;
525 entry->imm_data = cqe->imm_etype_pkey_eec;
526 entry->opcode = IB_WC_RECV;
527 break;
528 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
529 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
530 entry->wc_flags = IB_WC_WITH_IMM;
531 entry->imm_data = cqe->imm_etype_pkey_eec;
532 entry->opcode = IB_WC_RECV_RDMA_WITH_IMM;
533 break;
534 default:
535 entry->wc_flags = 0;
536 entry->opcode = IB_WC_RECV;
537 break;
538 }
539 entry->slid = be16_to_cpu(cqe->rlid);
540 entry->sl = be16_to_cpu(cqe->sl_g_mlpath) >> 12;
541 entry->src_qp = be32_to_cpu(cqe->rqpn) & 0xffffff;
542 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f;
543 entry->pkey_index = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16;
544 entry->wc_flags |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ?
545 IB_WC_GRH : 0;
546 }
547
548 entry->status = IB_WC_SUCCESS;
549
550 out:
551 if (likely(free_cqe)) {
552 set_cqe_hw(cqe);
553 ++(*freed);
554 ++cq->cons_index;
555 }
556
557 return err;
558}
559
560int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
561 struct ib_wc *entry)
562{
563 struct mthca_dev *dev = to_mdev(ibcq->device);
564 struct mthca_cq *cq = to_mcq(ibcq);
565 struct mthca_qp *qp = NULL;
566 unsigned long flags;
567 int err = 0;
568 int freed = 0;
569 int npolled;
570
571 spin_lock_irqsave(&cq->lock, flags);
572
573 for (npolled = 0; npolled < num_entries; ++npolled) {
574 err = mthca_poll_one(dev, cq, &qp,
575 &freed, entry + npolled);
576 if (err)
577 break;
578 }
579
580 if (freed) {
581 wmb();
582 update_cons_index(dev, cq, freed);
583 }
584
585 spin_unlock_irqrestore(&cq->lock, flags);
586
587 return err == 0 || err == -EAGAIN ? npolled : err;
588}
589
590int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
591{
97f52eb4 592 __be32 doorbell[2];
1da177e4
LT		 593
594 doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ?
595 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
596 MTHCA_TAVOR_CQ_DB_REQ_NOT) |
597 to_mcq(cq)->cqn);
97f52eb4 598 doorbell[1] = (__force __be32) 0xffffffff;
1da177e4
LT		 599
600 mthca_write64(doorbell,
601 to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
602 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
603
604 return 0;
605}
606
607int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
608{
609 struct mthca_cq *cq = to_mcq(ibcq);
97f52eb4 610 __be32 doorbell[2];
1da177e4 611 u32 sn;
97f52eb4 612 __be32 ci;
1da177e4
LT		 613
614 sn = cq->arm_sn & 3;
615 ci = cpu_to_be32(cq->cons_index);
616
617 doorbell[0] = ci;
618 doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
619 (notify == IB_CQ_SOLICITED ? 1 : 2));
620
621 mthca_write_db_rec(doorbell, cq->arm_db);
622
623 /*
624 * Make sure that the doorbell record in host memory is
625 * written before ringing the doorbell via PCI MMIO.
626 */
627 wmb();
628
629 doorbell[0] = cpu_to_be32((sn << 28) |
630 (notify == IB_CQ_SOLICITED ?
631 MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
632 MTHCA_ARBEL_CQ_DB_REQ_NOT) |
633 cq->cqn);
634 doorbell[1] = ci;
635
636 mthca_write64(doorbell,
637 to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
638 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
639
640 return 0;
641}
642
643static void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq *cq)
644{
87b81670
RD		 645 mthca_buf_free(dev, (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE,
646 &cq->queue, cq->is_direct, &cq->mr);
1da177e4
LT		 647}
648
649int mthca_init_cq(struct mthca_dev *dev, int nent,
74c2174e 650 struct mthca_ucontext *ctx, u32 pdn,
1da177e4
LT		 651 struct mthca_cq *cq)
652{
653 int size = nent * MTHCA_CQ_ENTRY_SIZE;
ed878458 654 struct mthca_mailbox *mailbox;
1da177e4
LT		 655 struct mthca_cq_context *cq_context;
656 int err = -ENOMEM;
657 u8 status;
658 int i;
659
660 might_sleep();
661
74c2174e
RD		 662 cq->ibcq.cqe = nent - 1;
663 cq->is_kernel = !ctx;
1da177e4
LT		 664
665 cq->cqn = mthca_alloc(&dev->cq_table.alloc);
666 if (cq->cqn == -1)
667 return -ENOMEM;
668
d10ddbf6 669 if (mthca_is_memfree(dev)) {
1da177e4
LT		 670 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
671 if (err)
672 goto err_out;
673
74c2174e
RD		 674 if (cq->is_kernel) {
675 cq->arm_sn = 1;
676
677 err = -ENOMEM;
1da177e4 678
74c2174e
RD		 679 cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
680 cq->cqn, &cq->set_ci_db);
681 if (cq->set_ci_db_index < 0)
682 goto err_out_icm;
1da177e4 683
74c2174e
RD		 684 cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
685 cq->cqn, &cq->arm_db);
686 if (cq->arm_db_index < 0)
687 goto err_out_ci;
688 }
1da177e4
LT		 689 }
690
ed878458
RD		 691 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
692 if (IS_ERR(mailbox))
693 goto err_out_arm;
1da177e4 694
ed878458 695 cq_context = mailbox->buf;
1da177e4 696
74c2174e 697 if (cq->is_kernel) {
87b81670
RD		 698 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_CQ_SIZE,
699 &cq->queue, &cq->is_direct,
700 &dev->driver_pd, 1, &cq->mr);
74c2174e
RD		 701 if (err)
702 goto err_out_mailbox;
1da177e4 703
74c2174e
RD		 704 for (i = 0; i < nent; ++i)
705 set_cqe_hw(get_cqe(cq, i));
706 }
1da177e4
LT		 707
708 spin_lock_init(&cq->lock);
709 atomic_set(&cq->refcount, 1);
710 init_waitqueue_head(&cq->wait);
711
712 memset(cq_context, 0, sizeof *cq_context);
713 cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK |
714 MTHCA_CQ_STATE_DISARMED |
715 MTHCA_CQ_FLAG_TR);
74c2174e
RD		 716 cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24);
717 if (ctx)
718 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index);
719 else
720 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
1da177e4
LT		 721 cq_context->error_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
722 cq_context->comp_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
74c2174e 723 cq_context->pd = cpu_to_be32(pdn);
1da177e4
LT		 724 cq_context->lkey = cpu_to_be32(cq->mr.ibmr.lkey);
725 cq_context->cqn = cpu_to_be32(cq->cqn);
726
d10ddbf6 727 if (mthca_is_memfree(dev)) {
1da177e4
LT		 728 cq_context->ci_db = cpu_to_be32(cq->set_ci_db_index);
729 cq_context->state_db = cpu_to_be32(cq->arm_db_index);
730 }
731
ed878458 732 err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status);
1da177e4
LT		 733 if (err) {
734 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err);
735 goto err_out_free_mr;
736 }
737
738 if (status) {
739 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n",
740 status);
741 err = -EINVAL;
742 goto err_out_free_mr;
743 }
744
745 spin_lock_irq(&dev->cq_table.lock);
746 if (mthca_array_set(&dev->cq_table.cq,
747 cq->cqn & (dev->limits.num_cqs - 1),
748 cq)) {
749 spin_unlock_irq(&dev->cq_table.lock);
750 goto err_out_free_mr;
751 }
752 spin_unlock_irq(&dev->cq_table.lock);
753
754 cq->cons_index = 0;
755
ed878458 756 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 757
758 return 0;
759
760err_out_free_mr:
87b81670 761 if (cq->is_kernel)
74c2174e 762 mthca_free_cq_buf(dev, cq);
1da177e4
LT		 763
764err_out_mailbox:
ed878458 765 mthca_free_mailbox(dev, mailbox);
1da177e4 766
ed878458 767err_out_arm:
74c2174e 768 if (cq->is_kernel && mthca_is_memfree(dev))
b635fa21 769 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
1da177e4
LT		 770
771err_out_ci:
74c2174e 772 if (cq->is_kernel && mthca_is_memfree(dev))
b635fa21 773 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
1da177e4
LT		 774
775err_out_icm:
776 mthca_table_put(dev, dev->cq_table.table, cq->cqn);
777
778err_out:
779 mthca_free(&dev->cq_table.alloc, cq->cqn);
780
781 return err;
782}
783
784void mthca_free_cq(struct mthca_dev *dev,
785 struct mthca_cq *cq)
786{
ed878458 787 struct mthca_mailbox *mailbox;
1da177e4
LT		 788 int err;
789 u8 status;
790
791 might_sleep();
792
ed878458
RD		 793 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
794 if (IS_ERR(mailbox)) {
1da177e4
LT		 795 mthca_warn(dev, "No memory for mailbox to free CQ.\n");
796 return;
797 }
798
ed878458 799 err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status);
1da177e4
LT		 800 if (err)
801 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err);
802 else if (status)
ed878458 803 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status);
1da177e4
LT		 804
805 if (0) {
97f52eb4 806 __be32 *ctx = mailbox->buf;
1da177e4
LT		 807 int j;
808
809 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",
74c2174e
RD		 810 cq->cqn, cq->cons_index,
811 cq->is_kernel ? !!next_cqe_sw(cq) : 0);
1da177e4
LT		 812 for (j = 0; j < 16; ++j)
813 printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j]));
814 }
815
816 spin_lock_irq(&dev->cq_table.lock);
817 mthca_array_clear(&dev->cq_table.cq,
818 cq->cqn & (dev->limits.num_cqs - 1));
819 spin_unlock_irq(&dev->cq_table.lock);
820
821 if (dev->mthca_flags & MTHCA_FLAG_MSI_X)
822 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector);
823 else
824 synchronize_irq(dev->pdev->irq);
825
826 atomic_dec(&cq->refcount);
827 wait_event(cq->wait, !atomic_read(&cq->refcount));
828
74c2174e 829 if (cq->is_kernel) {
74c2174e
RD		 830 mthca_free_cq_buf(dev, cq);
831 if (mthca_is_memfree(dev)) {
832 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
833 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
834 }
1da177e4
LT		 835 }
836
a03a5a67 837 mthca_table_put(dev, dev->cq_table.table, cq->cqn);
1da177e4 838 mthca_free(&dev->cq_table.alloc, cq->cqn);
ed878458 839 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 840}
841
842int __devinit mthca_init_cq_table(struct mthca_dev *dev)
843{
844 int err;
845
846 spin_lock_init(&dev->cq_table.lock);
847
848 err = mthca_alloc_init(&dev->cq_table.alloc,
849 dev->limits.num_cqs,
850 (1 << 24) - 1,
851 dev->limits.reserved_cqs);
852 if (err)
853 return err;
854
855 err = mthca_array_init(&dev->cq_table.cq,
856 dev->limits.num_cqs);
857 if (err)
858 mthca_alloc_cleanup(&dev->cq_table.alloc);
859
860 return err;
861}
862
863void __devexit mthca_cleanup_cq_table(struct mthca_dev *dev)
864{
865 mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
866 mthca_alloc_cleanup(&dev->cq_table.alloc);
867}
Linux 6.x block layer and io_uring tree(s)