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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
2a1d9b7f | 3 | * Copyright (c) 2005 Mellanox Technologies. All rights reserved. |
4885bf64 | 4 | * Copyright (c) 2006 Cisco Systems. All rights reserved. |
1da177e4 LT |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | * | |
34 | * $Id: mthca_cmd.h 1349 2004-12-16 21:09:43Z roland $ | |
35 | */ | |
36 | ||
37 | #ifndef MTHCA_CMD_H | |
38 | #define MTHCA_CMD_H | |
39 | ||
a4d61e84 | 40 | #include <rdma/ib_verbs.h> |
1da177e4 | 41 | |
ed878458 | 42 | #define MTHCA_MAILBOX_SIZE 4096 |
1da177e4 LT |
43 | |
44 | enum { | |
45 | /* command completed successfully: */ | |
46 | MTHCA_CMD_STAT_OK = 0x00, | |
47 | /* Internal error (such as a bus error) occurred while processing command: */ | |
48 | MTHCA_CMD_STAT_INTERNAL_ERR = 0x01, | |
49 | /* Operation/command not supported or opcode modifier not supported: */ | |
50 | MTHCA_CMD_STAT_BAD_OP = 0x02, | |
51 | /* Parameter not supported or parameter out of range: */ | |
52 | MTHCA_CMD_STAT_BAD_PARAM = 0x03, | |
53 | /* System not enabled or bad system state: */ | |
54 | MTHCA_CMD_STAT_BAD_SYS_STATE = 0x04, | |
55 | /* Attempt to access reserved or unallocaterd resource: */ | |
56 | MTHCA_CMD_STAT_BAD_RESOURCE = 0x05, | |
57 | /* Requested resource is currently executing a command, or is otherwise busy: */ | |
58 | MTHCA_CMD_STAT_RESOURCE_BUSY = 0x06, | |
59 | /* memory error: */ | |
60 | MTHCA_CMD_STAT_DDR_MEM_ERR = 0x07, | |
61 | /* Required capability exceeds device limits: */ | |
62 | MTHCA_CMD_STAT_EXCEED_LIM = 0x08, | |
63 | /* Resource is not in the appropriate state or ownership: */ | |
64 | MTHCA_CMD_STAT_BAD_RES_STATE = 0x09, | |
65 | /* Index out of range: */ | |
66 | MTHCA_CMD_STAT_BAD_INDEX = 0x0a, | |
67 | /* FW image corrupted: */ | |
68 | MTHCA_CMD_STAT_BAD_NVMEM = 0x0b, | |
69 | /* Attempt to modify a QP/EE which is not in the presumed state: */ | |
70 | MTHCA_CMD_STAT_BAD_QPEE_STATE = 0x10, | |
71 | /* Bad segment parameters (Address/Size): */ | |
72 | MTHCA_CMD_STAT_BAD_SEG_PARAM = 0x20, | |
73 | /* Memory Region has Memory Windows bound to: */ | |
74 | MTHCA_CMD_STAT_REG_BOUND = 0x21, | |
75 | /* HCA local attached memory not present: */ | |
76 | MTHCA_CMD_STAT_LAM_NOT_PRE = 0x22, | |
2fa5e2eb | 77 | /* Bad management packet (silently discarded): */ |
1da177e4 | 78 | MTHCA_CMD_STAT_BAD_PKT = 0x30, |
2fa5e2eb | 79 | /* More outstanding CQEs in CQ than new CQ size: */ |
1da177e4 LT |
80 | MTHCA_CMD_STAT_BAD_SIZE = 0x40 |
81 | }; | |
82 | ||
83 | enum { | |
84 | MTHCA_TRANS_INVALID = 0, | |
85 | MTHCA_TRANS_RST2INIT, | |
86 | MTHCA_TRANS_INIT2INIT, | |
87 | MTHCA_TRANS_INIT2RTR, | |
88 | MTHCA_TRANS_RTR2RTS, | |
89 | MTHCA_TRANS_RTS2RTS, | |
90 | MTHCA_TRANS_SQERR2RTS, | |
91 | MTHCA_TRANS_ANY2ERR, | |
92 | MTHCA_TRANS_RTS2SQD, | |
93 | MTHCA_TRANS_SQD2SQD, | |
94 | MTHCA_TRANS_SQD2RTS, | |
95 | MTHCA_TRANS_ANY2RST, | |
96 | }; | |
97 | ||
98 | enum { | |
99 | DEV_LIM_FLAG_RC = 1 << 0, | |
100 | DEV_LIM_FLAG_UC = 1 << 1, | |
101 | DEV_LIM_FLAG_UD = 1 << 2, | |
102 | DEV_LIM_FLAG_RD = 1 << 3, | |
103 | DEV_LIM_FLAG_RAW_IPV6 = 1 << 4, | |
104 | DEV_LIM_FLAG_RAW_ETHER = 1 << 5, | |
105 | DEV_LIM_FLAG_SRQ = 1 << 6, | |
106 | DEV_LIM_FLAG_BAD_PKEY_CNTR = 1 << 8, | |
107 | DEV_LIM_FLAG_BAD_QKEY_CNTR = 1 << 9, | |
108 | DEV_LIM_FLAG_MW = 1 << 16, | |
109 | DEV_LIM_FLAG_AUTO_PATH_MIG = 1 << 17, | |
110 | DEV_LIM_FLAG_ATOMIC = 1 << 18, | |
111 | DEV_LIM_FLAG_RAW_MULTI = 1 << 19, | |
112 | DEV_LIM_FLAG_UD_AV_PORT_ENFORCE = 1 << 20, | |
113 | DEV_LIM_FLAG_UD_MULTI = 1 << 21, | |
114 | }; | |
115 | ||
ed878458 RD |
116 | struct mthca_mailbox { |
117 | dma_addr_t dma; | |
118 | void *buf; | |
119 | }; | |
120 | ||
1da177e4 LT |
121 | struct mthca_dev_lim { |
122 | int max_srq_sz; | |
123 | int max_qp_sz; | |
124 | int reserved_qps; | |
125 | int max_qps; | |
126 | int reserved_srqs; | |
127 | int max_srqs; | |
128 | int reserved_eecs; | |
129 | int max_eecs; | |
130 | int max_cq_sz; | |
131 | int reserved_cqs; | |
132 | int max_cqs; | |
133 | int max_mpts; | |
134 | int reserved_eqs; | |
135 | int max_eqs; | |
136 | int reserved_mtts; | |
137 | int max_mrw_sz; | |
138 | int reserved_mrws; | |
139 | int max_mtt_seg; | |
140 | int max_requester_per_qp; | |
141 | int max_responder_per_qp; | |
142 | int max_rdma_global; | |
143 | int local_ca_ack_delay; | |
144 | int max_mtu; | |
145 | int max_port_width; | |
146 | int max_vl; | |
147 | int num_ports; | |
148 | int max_gids; | |
bf6a9e31 | 149 | u16 stat_rate_support; |
1da177e4 LT |
150 | int max_pkeys; |
151 | u32 flags; | |
152 | int reserved_uars; | |
153 | int uar_size; | |
154 | int min_page_sz; | |
155 | int max_sg; | |
156 | int max_desc_sz; | |
157 | int max_qp_per_mcg; | |
158 | int reserved_mgms; | |
159 | int max_mcgs; | |
160 | int reserved_pds; | |
161 | int max_pds; | |
162 | int reserved_rdds; | |
163 | int max_rdds; | |
164 | int eec_entry_sz; | |
165 | int qpc_entry_sz; | |
166 | int eeec_entry_sz; | |
167 | int eqpc_entry_sz; | |
168 | int eqc_entry_sz; | |
169 | int cqc_entry_sz; | |
170 | int srq_entry_sz; | |
171 | int uar_scratch_entry_sz; | |
1da177e4 LT |
172 | int mpt_entry_sz; |
173 | union { | |
174 | struct { | |
175 | int max_avs; | |
176 | } tavor; | |
177 | struct { | |
178 | int resize_srq; | |
179 | int max_pbl_sz; | |
180 | u8 bmme_flags; | |
181 | u32 reserved_lkey; | |
182 | int lam_required; | |
183 | u64 max_icm_sz; | |
184 | } arbel; | |
185 | } hca; | |
186 | }; | |
187 | ||
188 | struct mthca_adapter { | |
2e8b981c MT |
189 | u32 vendor_id; |
190 | u32 device_id; | |
191 | u32 revision_id; | |
192 | char board_id[MTHCA_BOARD_ID_LEN]; | |
193 | u8 inta_pin; | |
1da177e4 LT |
194 | }; |
195 | ||
196 | struct mthca_init_hca_param { | |
197 | u64 qpc_base; | |
198 | u64 eec_base; | |
199 | u64 srqc_base; | |
200 | u64 cqc_base; | |
201 | u64 eqpc_base; | |
202 | u64 eeec_base; | |
203 | u64 eqc_base; | |
204 | u64 rdb_base; | |
205 | u64 mc_base; | |
206 | u64 mpt_base; | |
207 | u64 mtt_base; | |
208 | u64 uar_scratch_base; | |
209 | u64 uarc_base; | |
210 | u16 log_mc_entry_sz; | |
211 | u16 mc_hash_sz; | |
212 | u8 log_num_qps; | |
213 | u8 log_num_eecs; | |
214 | u8 log_num_srqs; | |
215 | u8 log_num_cqs; | |
216 | u8 log_num_eqs; | |
217 | u8 log_mc_table_sz; | |
218 | u8 mtt_seg_sz; | |
219 | u8 log_mpt_sz; | |
220 | u8 log_uar_sz; | |
221 | u8 log_uarc_sz; | |
222 | }; | |
223 | ||
224 | struct mthca_init_ib_param { | |
da6561c2 | 225 | int port_width; |
1da177e4 LT |
226 | int vl_cap; |
227 | int mtu_cap; | |
228 | u16 gid_cap; | |
229 | u16 pkey_cap; | |
230 | int set_guid0; | |
231 | u64 guid0; | |
232 | int set_node_guid; | |
233 | u64 node_guid; | |
234 | int set_si_guid; | |
235 | u64 si_guid; | |
236 | }; | |
237 | ||
238 | struct mthca_set_ib_param { | |
239 | int set_si_guid; | |
240 | int reset_qkey_viol; | |
241 | u64 si_guid; | |
242 | u32 cap_mask; | |
243 | }; | |
244 | ||
80fd8238 RD |
245 | int mthca_cmd_init(struct mthca_dev *dev); |
246 | void mthca_cmd_cleanup(struct mthca_dev *dev); | |
1da177e4 LT |
247 | int mthca_cmd_use_events(struct mthca_dev *dev); |
248 | void mthca_cmd_use_polling(struct mthca_dev *dev); | |
249 | void mthca_cmd_event(struct mthca_dev *dev, u16 token, | |
250 | u8 status, u64 out_param); | |
251 | ||
ed878458 | 252 | struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev, |
87b750dc | 253 | gfp_t gfp_mask); |
ed878458 RD |
254 | void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox); |
255 | ||
1da177e4 LT |
256 | int mthca_SYS_EN(struct mthca_dev *dev, u8 *status); |
257 | int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status); | |
258 | int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status); | |
259 | int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status); | |
260 | int mthca_RUN_FW(struct mthca_dev *dev, u8 *status); | |
261 | int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status); | |
262 | int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status); | |
263 | int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status); | |
264 | int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status); | |
265 | int mthca_QUERY_DEV_LIM(struct mthca_dev *dev, | |
266 | struct mthca_dev_lim *dev_lim, u8 *status); | |
267 | int mthca_QUERY_ADAPTER(struct mthca_dev *dev, | |
268 | struct mthca_adapter *adapter, u8 *status); | |
269 | int mthca_INIT_HCA(struct mthca_dev *dev, | |
270 | struct mthca_init_hca_param *param, | |
271 | u8 *status); | |
272 | int mthca_INIT_IB(struct mthca_dev *dev, | |
273 | struct mthca_init_ib_param *param, | |
274 | int port, u8 *status); | |
275 | int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status); | |
276 | int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status); | |
277 | int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param, | |
278 | int port, u8 *status); | |
279 | int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status); | |
280 | int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status); | |
281 | int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status); | |
282 | int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status); | |
283 | int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status); | |
284 | int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages, | |
285 | u8 *status); | |
ed878458 | 286 | int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 | 287 | int mpt_index, u8 *status); |
ed878458 | 288 | int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 | 289 | int mpt_index, u8 *status); |
ed878458 | 290 | int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 | 291 | int num_mtt, u8 *status); |
b8ca06f6 | 292 | int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status); |
1da177e4 LT |
293 | int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap, |
294 | int eq_num, u8 *status); | |
ed878458 | 295 | int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 | 296 | int eq_num, u8 *status); |
ed878458 | 297 | int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 | 298 | int eq_num, u8 *status); |
ed878458 | 299 | int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 | 300 | int cq_num, u8 *status); |
ed878458 | 301 | int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 | 302 | int cq_num, u8 *status); |
4885bf64 RD |
303 | int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size, |
304 | u8 *status); | |
ec34a922 RD |
305 | int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
306 | int srq_num, u8 *status); | |
307 | int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, | |
308 | int srq_num, u8 *status); | |
8ebe5077 EC |
309 | int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num, |
310 | struct mthca_mailbox *mailbox, u8 *status); | |
ec34a922 | 311 | int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status); |
d844183d RD |
312 | int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur, |
313 | enum ib_qp_state next, u32 num, int is_ee, | |
314 | struct mthca_mailbox *mailbox, u32 optmask, | |
1da177e4 LT |
315 | u8 *status); |
316 | int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee, | |
ed878458 | 317 | struct mthca_mailbox *mailbox, u8 *status); |
1da177e4 LT |
318 | int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn, |
319 | u8 *status); | |
320 | int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey, | |
ed878458 | 321 | int port, struct ib_wc *in_wc, struct ib_grh *in_grh, |
1da177e4 | 322 | void *in_mad, void *response_mad, u8 *status); |
ed878458 RD |
323 | int mthca_READ_MGM(struct mthca_dev *dev, int index, |
324 | struct mthca_mailbox *mailbox, u8 *status); | |
325 | int mthca_WRITE_MGM(struct mthca_dev *dev, int index, | |
326 | struct mthca_mailbox *mailbox, u8 *status); | |
327 | int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox, | |
328 | u16 *hash, u8 *status); | |
1da177e4 LT |
329 | int mthca_NOP(struct mthca_dev *dev, u8 *status); |
330 | ||
1da177e4 | 331 | #endif /* MTHCA_CMD_H */ |