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Merge tag 'sched-core-2024-09-19' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
b572ebe6 1// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
e126ba97 2/*
b572ebe6 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
90da7dc8 4 * Copyright (c) 2020, Intel Corporation. All rights reserved.
e126ba97
EC		 5 */
6
fe248c3a 7#include <linux/debugfs.h>
adec640e 8#include <linux/highmem.h>
e126ba97
EC		 9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/errno.h>
12#include <linux/pci.h>
13#include <linux/dma-mapping.h>
14#include <linux/slab.h>
24da0016 15#include <linux/bitmap.h>
e126ba97 16#include <linux/sched.h>
6e84f315 17#include <linux/sched/mm.h>
0881e7bd 18#include <linux/sched/task.h>
7c2344c3 19#include <linux/delay.h>
e126ba97 20#include <rdma/ib_user_verbs.h>
3f89a643 21#include <rdma/ib_addr.h>
2811ba51 22#include <rdma/ib_cache.h>
ada68c31 23#include <linux/mlx5/port.h>
1b5daf11 24#include <linux/mlx5/vport.h>
72c7fe90 25#include <linux/mlx5/fs.h>
cecae747 26#include <linux/mlx5/eswitch.h>
0d293714 27#include <linux/mlx5/driver.h>
7c2344c3 28#include <linux/list.h>
e126ba97 29#include <rdma/ib_smi.h>
ca7ef7ad 30#include <rdma/ib_umem_odp.h>
cfc1a89e 31#include <rdma/lag.h>
038d2ef8
MG		 32#include <linux/in.h>
33#include <linux/etherdevice.h>
e126ba97 34#include "mlx5_ib.h"
fc385b7a 35#include "ib_rep.h"
e1f24a79 36#include "cmd.h"
d8b7515e 37#include "devx.h"
831df883 38#include "dm.h"
f7c4ffda 39#include "fs.h"
f3da6577 40#include "srq.h"
333fbaa0 41#include "qp.h"
029e88fd 42#include "wr.h"
b572ebe6 43#include "restrack.h"
64825827 44#include "counters.h"
04876c12 45#include "umr.h"
8c84660b 46#include <rdma/uverbs_std_types.h>
2904bb37 47#include <rdma/uverbs_ioctl.h>
c6475a0b
AY		 48#include <rdma/mlx5_user_ioctl_verbs.h>
49#include <rdma/mlx5_user_ioctl_cmds.h>
758ce14a 50#include "macsec.h"
8c84660b
MB		 51
52#define UVERBS_MODULE_NAME mlx5_ib
53#include <rdma/uverbs_named_ioctl.h>
e126ba97 54
e126ba97 55MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
daeee976 56MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver");
e126ba97 57MODULE_LICENSE("Dual BSD/GPL");
e126ba97 58
d69a24e0
DJ		 59struct mlx5_ib_event_work {
60 struct work_struct work;
df097a27
SM		 61 union {
62 struct mlx5_ib_dev *dev;
63 struct mlx5_ib_multiport_info *mpi;
64 };
65 bool is_slave;
134e9349 66 unsigned int event;
df097a27 67 void *param;
d69a24e0
DJ		 68};
69
da7525d2
EBE		 70enum {
71 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
72};
73
d69a24e0 74static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 75static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
76static LIST_HEAD(mlx5_ib_dev_list);
77/*
78 * This mutex should be held when accessing either of the above lists
79 */
80static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
81
82struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
83{
84 struct mlx5_ib_dev *dev;
85
86 mutex_lock(&mlx5_ib_multiport_mutex);
87 dev = mpi->ibdev;
88 mutex_unlock(&mlx5_ib_multiport_mutex);
89 return dev;
90}
91
1b5daf11 92static enum rdma_link_layer
ebd61f68 93mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 94{
ebd61f68 95 switch (port_type_cap) {
1b5daf11
MD		 96 case MLX5_CAP_PORT_TYPE_IB:
97 return IB_LINK_LAYER_INFINIBAND;
98 case MLX5_CAP_PORT_TYPE_ETH:
99 return IB_LINK_LAYER_ETHERNET;
100 default:
101 return IB_LINK_LAYER_UNSPECIFIED;
102 }
103}
104
ebd61f68 105static enum rdma_link_layer
1fb7f897 106mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num)
ebd61f68
AS		 107{
108 struct mlx5_ib_dev *dev = to_mdev(device);
109 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
110
111 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
112}
113
fd65f1b8 114static int get_port_state(struct ib_device *ibdev,
1fb7f897 115 u32 port_num,
fd65f1b8
MS		 116 enum ib_port_state *state)
117{
118 struct ib_port_attr attr;
119 int ret;
120
121 memset(&attr, 0, sizeof(attr));
3023a1e9 122 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 123 if (!ret)
124 *state = attr.state;
125 return ret;
126}
127
35b0aa67
MB		 128static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
129 struct net_device *ndev,
c446d9da 130 struct net_device *upper,
1fb7f897 131 u32 *port_num)
35b0aa67 132{
35b0aa67
MB		 133 struct net_device *rep_ndev;
134 struct mlx5_ib_port *port;
135 int i;
136
137 for (i = 0; i < dev->num_ports; i++) {
138 port = &dev->port[i];
139 if (!port->rep)
140 continue;
141
c446d9da
MB		 142 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) {
143 *port_num = i + 1;
144 return &port->roce;
145 }
146
147 if (upper && port->rep->vport == MLX5_VPORT_UPLINK)
148 continue;
149
35b0aa67 150 read_lock(&port->roce.netdev_lock);
658cfceb 151 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw,
35b0aa67
MB		 152 port->rep->vport);
153 if (rep_ndev == ndev) {
154 read_unlock(&port->roce.netdev_lock);
155 *port_num = i + 1;
156 return &port->roce;
157 }
158 read_unlock(&port->roce.netdev_lock);
159 }
160
161 return NULL;
162}
163
fc24fc5e
AS		 164static int mlx5_netdev_event(struct notifier_block *this,
165 unsigned long event, void *ptr)
166{
7fd8aefb 167 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 168 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
1fb7f897 169 u32 port_num = roce->native_port_num;
7fd8aefb
DJ		 170 struct mlx5_core_dev *mdev;
171 struct mlx5_ib_dev *ibdev;
172
173 ibdev = roce->dev;
32f69e4b
DJ		 174 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
175 if (!mdev)
176 return NOTIFY_DONE;
fc24fc5e 177
5ec8c83e
AH		 178 switch (event) {
179 case NETDEV_REGISTER:
35b0aa67
MB		 180 /* Should already be registered during the load */
181 if (ibdev->is_rep)
182 break;
7fd8aefb 183 write_lock(&roce->netdev_lock);
dce45af5 184 if (ndev->dev.parent == mdev->device)
842a9c83 185 roce->netdev = ndev;
7fd8aefb 186 write_unlock(&roce->netdev_lock);
5ec8c83e 187 break;
fc24fc5e 188
842a9c83 189 case NETDEV_UNREGISTER:
35b0aa67 190 /* In case of reps, ib device goes away before the netdevs */
842a9c83
OG		 191 write_lock(&roce->netdev_lock);
192 if (roce->netdev == ndev)
193 roce->netdev = NULL;
194 write_unlock(&roce->netdev_lock);
195 break;
196
fd65f1b8 197 case NETDEV_CHANGE:
5ec8c83e 198 case NETDEV_UP:
88621dfe 199 case NETDEV_DOWN: {
7fd8aefb 200 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 201 struct net_device *upper = NULL;
202
203 if (lag_ndev) {
204 upper = netdev_master_upper_dev_get(lag_ndev);
205 dev_put(lag_ndev);
206 }
207
35b0aa67 208 if (ibdev->is_rep)
c446d9da 209 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num);
35b0aa67
MB		 210 if (!roce)
211 return NOTIFY_DONE;
c446d9da
MB		 212 if ((upper == ndev ||
213 ((!upper || ibdev->is_rep) && ndev == roce->netdev)) &&
214 ibdev->ib_active) {
626bc02d 215 struct ib_event ibev = { };
fd65f1b8 216 enum ib_port_state port_state;
5ec8c83e 217
7fd8aefb
DJ		 218 if (get_port_state(&ibdev->ib_dev, port_num,
219 &port_state))
220 goto done;
fd65f1b8 221
7fd8aefb
DJ		 222 if (roce->last_port_state == port_state)
223 goto done;
fd65f1b8 224
7fd8aefb 225 roce->last_port_state = port_state;
5ec8c83e 226 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 227 if (port_state == IB_PORT_DOWN)
228 ibev.event = IB_EVENT_PORT_ERR;
229 else if (port_state == IB_PORT_ACTIVE)
230 ibev.event = IB_EVENT_PORT_ACTIVE;
231 else
7fd8aefb 232 goto done;
fd65f1b8 233
7fd8aefb 234 ibev.element.port_num = port_num;
5ec8c83e
AH		 235 ib_dispatch_event(&ibev);
236 }
237 break;
88621dfe 238 }
fc24fc5e 239
5ec8c83e
AH		 240 default:
241 break;
242 }
7fd8aefb 243done:
32f69e4b 244 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 245 return NOTIFY_DONE;
246}
247
248static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
1fb7f897 249 u32 port_num)
fc24fc5e
AS		 250{
251 struct mlx5_ib_dev *ibdev = to_mdev(device);
252 struct net_device *ndev;
32f69e4b
DJ		 253 struct mlx5_core_dev *mdev;
254
255 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
256 if (!mdev)
257 return NULL;
fc24fc5e 258
32f69e4b 259 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 260 if (ndev)
32f69e4b 261 goto out;
88621dfe 262
fc24fc5e
AS		 263 /* Ensure ndev does not disappear before we invoke dev_hold()
264 */
95579e78
MB		 265 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
266 ndev = ibdev->port[port_num - 1].roce.netdev;
82e96613 267 dev_hold(ndev);
95579e78 268 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
fc24fc5e 269
32f69e4b
DJ		 270out:
271 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 272 return ndev;
273}
274
32f69e4b 275struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
1fb7f897
MB		 276 u32 ib_port_num,
277 u32 *native_port_num)
32f69e4b
DJ		 278{
279 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
280 ib_port_num);
281 struct mlx5_core_dev *mdev = NULL;
282 struct mlx5_ib_multiport_info *mpi;
283 struct mlx5_ib_port *port;
284
026a4259
MZ		 285 if (ibdev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) {
286 if (native_port_num)
287 *native_port_num = smi_to_native_portnum(ibdev,
288 ib_port_num);
289 return ibdev->mdev;
290
291 }
292
210b1f78
MB		 293 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
294 ll != IB_LINK_LAYER_ETHERNET) {
295 if (native_port_num)
296 *native_port_num = ib_port_num;
297 return ibdev->mdev;
298 }
299
32f69e4b
DJ		 300 if (native_port_num)
301 *native_port_num = 1;
302
32f69e4b 303 port = &ibdev->port[ib_port_num - 1];
32f69e4b
DJ		 304 spin_lock(&port->mp.mpi_lock);
305 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
306 if (mpi && !mpi->unaffiliate) {
307 mdev = mpi->mdev;
308 /* If it's the master no need to refcount, it'll exist
309 * as long as the ib_dev exists.
310 */
311 if (!mpi->is_master)
312 mpi->mdev_refcnt++;
313 }
314 spin_unlock(&port->mp.mpi_lock);
315
316 return mdev;
317}
318
1fb7f897 319void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num)
32f69e4b
DJ		 320{
321 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
322 port_num);
323 struct mlx5_ib_multiport_info *mpi;
324 struct mlx5_ib_port *port;
325
326 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
327 return;
328
329 port = &ibdev->port[port_num - 1];
330
331 spin_lock(&port->mp.mpi_lock);
332 mpi = ibdev->port[port_num - 1].mp.mpi;
333 if (mpi->is_master)
334 goto out;
335
336 mpi->mdev_refcnt--;
337 if (mpi->unaffiliate)
338 complete(&mpi->unref_comp);
339out:
340 spin_unlock(&port->mp.mpi_lock);
341}
342
639bf441
AL		 343static int translate_eth_legacy_proto_oper(u32 eth_proto_oper,
344 u16 *active_speed, u8 *active_width)
f1b65df5
NO		 345{
346 switch (eth_proto_oper) {
347 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
348 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
349 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
350 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
351 *active_width = IB_WIDTH_1X;
352 *active_speed = IB_SPEED_SDR;
353 break;
354 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
355 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
356 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
357 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
358 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
359 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
360 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
361 *active_width = IB_WIDTH_1X;
362 *active_speed = IB_SPEED_QDR;
363 break;
364 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
365 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
366 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
367 *active_width = IB_WIDTH_1X;
368 *active_speed = IB_SPEED_EDR;
369 break;
370 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
371 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
372 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
373 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
374 *active_width = IB_WIDTH_4X;
375 *active_speed = IB_SPEED_QDR;
376 break;
377 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
378 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
379 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
380 *active_width = IB_WIDTH_1X;
381 *active_speed = IB_SPEED_HDR;
382 break;
383 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
384 *active_width = IB_WIDTH_4X;
385 *active_speed = IB_SPEED_FDR;
386 break;
387 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
388 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
389 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
390 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
391 *active_width = IB_WIDTH_4X;
392 *active_speed = IB_SPEED_EDR;
393 break;
394 default:
395 return -EINVAL;
396 }
397
398 return 0;
399}
400
639bf441 401static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
08e8676f
AL		 402 u8 *active_width)
403{
404 switch (eth_proto_oper) {
405 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
406 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
407 *active_width = IB_WIDTH_1X;
408 *active_speed = IB_SPEED_SDR;
409 break;
410 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
411 *active_width = IB_WIDTH_1X;
412 *active_speed = IB_SPEED_DDR;
413 break;
414 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
415 *active_width = IB_WIDTH_1X;
416 *active_speed = IB_SPEED_QDR;
417 break;
418 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
419 *active_width = IB_WIDTH_4X;
420 *active_speed = IB_SPEED_QDR;
421 break;
422 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
423 *active_width = IB_WIDTH_1X;
424 *active_speed = IB_SPEED_EDR;
425 break;
426 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
cd272875
AL		 427 *active_width = IB_WIDTH_2X;
428 *active_speed = IB_SPEED_EDR;
429 break;
08e8676f
AL		 430 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
431 *active_width = IB_WIDTH_1X;
432 *active_speed = IB_SPEED_HDR;
433 break;
cd272875
AL		 434 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
435 *active_width = IB_WIDTH_4X;
436 *active_speed = IB_SPEED_EDR;
437 break;
08e8676f
AL		 438 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
439 *active_width = IB_WIDTH_2X;
440 *active_speed = IB_SPEED_HDR;
441 break;
f946e45f
ML		 442 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR):
443 *active_width = IB_WIDTH_1X;
444 *active_speed = IB_SPEED_NDR;
445 break;
08e8676f
AL		 446 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
447 *active_width = IB_WIDTH_4X;
448 *active_speed = IB_SPEED_HDR;
449 break;
f946e45f
ML		 450 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2):
451 *active_width = IB_WIDTH_2X;
452 *active_speed = IB_SPEED_NDR;
453 break;
b28ad324 454 case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8):
88c9483f
MS		 455 *active_width = IB_WIDTH_8X;
456 *active_speed = IB_SPEED_HDR;
457 break;
f946e45f
ML		 458 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4):
459 *active_width = IB_WIDTH_4X;
460 *active_speed = IB_SPEED_NDR;
461 break;
948f0bf5
PH		 462 case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8):
463 *active_width = IB_WIDTH_8X;
464 *active_speed = IB_SPEED_NDR;
465 break;
08e8676f
AL		 466 default:
467 return -EINVAL;
468 }
469
470 return 0;
471}
472
639bf441 473static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed,
08e8676f
AL		 474 u8 *active_width, bool ext)
475{
476 return ext ?
477 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
478 active_width) :
479 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
480 active_width);
481}
482
1fb7f897 483static int mlx5_query_port_roce(struct ib_device *device, u32 port_num,
095b0927 484 struct ib_port_attr *props)
3f89a643
AS		 485{
486 struct mlx5_ib_dev *dev = to_mdev(device);
bc4e12ff 487 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
da005f9f 488 struct mlx5_core_dev *mdev;
88621dfe 489 struct net_device *ndev, *upper;
3f89a643 490 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 491 bool put_mdev = true;
f1b65df5 492 u32 eth_prot_oper;
1fb7f897 493 u32 mdev_port_num;
08e8676f 494 bool ext;
095b0927 495 int err;
3f89a643 496
b3cbd6f0
DJ		 497 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
498 if (!mdev) {
499 /* This means the port isn't affiliated yet. Get the
500 * info for the master port instead.
501 */
502 put_mdev = false;
503 mdev = dev->mdev;
504 mdev_port_num = 1;
505 port_num = 1;
506 }
507
f1b65df5
NO		 508 /* Possible bad flows are checked before filling out props so in case
509 * of an error it will still be zeroed out.
26628e2d 510 * Use native port in case of reps
50f22fd8 511 */
26628e2d
MB		 512 if (dev->is_rep)
513 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
3b43399b 514 1, 0);
26628e2d
MB		 515 else
516 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
3b43399b 517 mdev_port_num, 0);
095b0927 518 if (err)
b3cbd6f0 519 goto out;
530c8632 520 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
08e8676f 521 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
f1b65df5 522
7672ed33
HL		 523 props->active_width = IB_WIDTH_4X;
524 props->active_speed = IB_SPEED_QDR;
525
f1b65df5 526 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
08e8676f 527 &props->active_width, ext);
3f89a643 528
7852546f 529 if (!dev->is_rep && dev->mdev->roce.roce_en) {
7a58779e 530 u16 qkey_viol_cntr;
3f89a643 531
7a58779e
PP		 532 props->port_cap_flags |= IB_PORT_CM_SUP;
533 props->ip_gids = true;
534 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
535 roce_address_table_size);
536 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
537 props->qkey_viol_cntr = qkey_viol_cntr;
538 }
3f89a643
AS		 539 props->max_mtu = IB_MTU_4096;
540 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
541 props->pkey_tbl_len = 1;
542 props->state = IB_PORT_DOWN;
72a7720f 543 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
3f89a643 544
b3cbd6f0
DJ		 545 /* If this is a stub query for an unaffiliated port stop here */
546 if (!put_mdev)
547 goto out;
548
3f89a643
AS		 549 ndev = mlx5_ib_get_netdev(device, port_num);
550 if (!ndev)
b3cbd6f0 551 goto out;
3f89a643 552
7c34ec19 553 if (dev->lag_active) {
88621dfe
AH		 554 rcu_read_lock();
555 upper = netdev_master_upper_dev_get_rcu(ndev);
556 if (upper) {
557 dev_put(ndev);
558 ndev = upper;
559 dev_hold(ndev);
560 }
561 rcu_read_unlock();
562 }
563
3f89a643
AS		 564 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
565 props->state = IB_PORT_ACTIVE;
72a7720f 566 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
3f89a643
AS		 567 }
568
569 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
570
571 dev_put(ndev);
572
573 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 574out:
575 if (put_mdev)
576 mlx5_ib_put_native_port_mdev(dev, port_num);
577 return err;
3f89a643
AS		 578}
579
758ce14a
PH		 580int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num,
581 unsigned int index, const union ib_gid *gid,
582 const struct ib_gid_attr *attr)
3cca2606 583{
dedbc2d3 584 enum ib_gid_type gid_type;
a70c0739 585 u16 vlan_id = 0xffff;
095b0927
IT		 586 u8 roce_version = 0;
587 u8 roce_l3_type = 0;
095b0927 588 u8 mac[ETH_ALEN];
a70c0739 589 int ret;
095b0927 590
dedbc2d3 591 gid_type = attr->gid_type;
095b0927 592 if (gid) {
a70c0739
PP		 593 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
594 if (ret)
595 return ret;
3cca2606
AS		 596 }
597
095b0927 598 switch (gid_type) {
1c15b4f2 599 case IB_GID_TYPE_ROCE:
095b0927 600 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 601 break;
602 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927 603 roce_version = MLX5_ROCE_VERSION_2;
dedbc2d3 604 if (gid && ipv6_addr_v4mapped((void *)gid))
095b0927
IT		 605 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
606 else
607 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 608 break;
609
610 default:
095b0927 611 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 612 }
613
095b0927 614 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
cf34e1fe 615 roce_l3_type, gid->raw, mac,
a70c0739 616 vlan_id < VLAN_CFI_MASK, vlan_id,
cf34e1fe 617 port_num);
3cca2606
AS		 618}
619
f4df9a7c 620static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 621 __always_unused void **context)
622{
758ce14a
PH		 623 int ret;
624
625 ret = mlx5r_add_gid_macsec_operations(attr);
626 if (ret)
627 return ret;
628
414448d2 629 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 630 attr->index, &attr->gid, attr);
3cca2606
AS		 631}
632
414448d2
PP		 633static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
634 __always_unused void **context)
3cca2606 635{
758ce14a
PH		 636 int ret;
637
638 ret = set_roce_addr(to_mdev(attr->device), attr->port_num,
639 attr->index, NULL, attr);
640 if (ret)
641 return ret;
642
643 mlx5r_del_gid_macsec_operations(attr);
644 return 0;
3cca2606
AS		 645}
646
5ac55dfc
MZ		 647__be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
648 const struct ib_gid_attr *attr)
2811ba51 649{
47ec3866 650 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 651 return 0;
652
653 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
654}
655
1b5daf11
MD		 656static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
657{
7fae6655
NO		 658 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
659 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
660 return 0;
1b5daf11
MD		 661}
662
663enum {
664 MLX5_VPORT_ACCESS_METHOD_MAD,
665 MLX5_VPORT_ACCESS_METHOD_HCA,
666 MLX5_VPORT_ACCESS_METHOD_NIC,
667};
668
669static int mlx5_get_vport_access_method(struct ib_device *ibdev)
670{
671 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
672 return MLX5_VPORT_ACCESS_METHOD_MAD;
673
ebd61f68 674 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 675 IB_LINK_LAYER_ETHERNET)
676 return MLX5_VPORT_ACCESS_METHOD_NIC;
677
678 return MLX5_VPORT_ACCESS_METHOD_HCA;
679}
680
da7525d2 681static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 682 u8 atomic_size_qp,
da7525d2
EBE		 683 struct ib_device_attr *props)
684{
685 u8 tmp;
686 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 687 u8 atomic_req_8B_endianness_mode =
bd10838a 688 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 689
690 /* Check if HW supports 8 bytes standard atomic operations and capable
691 * of host endianness respond
692 */
693 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
694 if (((atomic_operations & tmp) == tmp) &&
695 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
696 (atomic_req_8B_endianness_mode)) {
697 props->atomic_cap = IB_ATOMIC_HCA;
698 } else {
699 props->atomic_cap = IB_ATOMIC_NONE;
700 }
701}
702
776a3906
MS		 703static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
704 struct ib_device_attr *props)
705{
706 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
707
708 get_atomic_caps(dev, atomic_size_qp, props);
709}
710
1b5daf11
MD		 711static int mlx5_query_system_image_guid(struct ib_device *ibdev,
712 __be64 *sys_image_guid)
713{
714 struct mlx5_ib_dev *dev = to_mdev(ibdev);
715 struct mlx5_core_dev *mdev = dev->mdev;
716 u64 tmp;
717 int err;
718
719 switch (mlx5_get_vport_access_method(ibdev)) {
720 case MLX5_VPORT_ACCESS_METHOD_MAD:
721 return mlx5_query_mad_ifc_system_image_guid(ibdev,
722 sys_image_guid);
723
724 case MLX5_VPORT_ACCESS_METHOD_HCA:
725 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 726 break;
727
728 case MLX5_VPORT_ACCESS_METHOD_NIC:
729 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
730 break;
1b5daf11
MD		 731
732 default:
733 return -EINVAL;
734 }
3f89a643
AS		 735
736 if (!err)
737 *sys_image_guid = cpu_to_be64(tmp);
738
739 return err;
740
1b5daf11
MD		 741}
742
743static int mlx5_query_max_pkeys(struct ib_device *ibdev,
744 u16 *max_pkeys)
745{
746 struct mlx5_ib_dev *dev = to_mdev(ibdev);
747 struct mlx5_core_dev *mdev = dev->mdev;
748
749 switch (mlx5_get_vport_access_method(ibdev)) {
750 case MLX5_VPORT_ACCESS_METHOD_MAD:
751 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
752
753 case MLX5_VPORT_ACCESS_METHOD_HCA:
754 case MLX5_VPORT_ACCESS_METHOD_NIC:
755 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
756 pkey_table_size));
757 return 0;
758
759 default:
760 return -EINVAL;
761 }
762}
763
764static int mlx5_query_vendor_id(struct ib_device *ibdev,
765 u32 *vendor_id)
766{
767 struct mlx5_ib_dev *dev = to_mdev(ibdev);
768
769 switch (mlx5_get_vport_access_method(ibdev)) {
770 case MLX5_VPORT_ACCESS_METHOD_MAD:
771 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
772
773 case MLX5_VPORT_ACCESS_METHOD_HCA:
774 case MLX5_VPORT_ACCESS_METHOD_NIC:
775 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
776
777 default:
778 return -EINVAL;
779 }
780}
781
782static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
783 __be64 *node_guid)
784{
785 u64 tmp;
786 int err;
787
788 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
789 case MLX5_VPORT_ACCESS_METHOD_MAD:
790 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
791
792 case MLX5_VPORT_ACCESS_METHOD_HCA:
793 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 794 break;
795
796 case MLX5_VPORT_ACCESS_METHOD_NIC:
797 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
798 break;
1b5daf11
MD		 799
800 default:
801 return -EINVAL;
802 }
3f89a643
AS		 803
804 if (!err)
805 *node_guid = cpu_to_be64(tmp);
806
807 return err;
1b5daf11
MD		 808}
809
810struct mlx5_reg_node_desc {
bd99fdea 811 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 812};
813
814static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
815{
816 struct mlx5_reg_node_desc in;
817
818 if (mlx5_use_mad_ifc(dev))
819 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
820
821 memset(&in, 0, sizeof(in));
822
823 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
824 sizeof(struct mlx5_reg_node_desc),
825 MLX5_REG_NODE_DESC, 0, 0);
826}
827
d727d27d
MB		 828static void fill_esw_mgr_reg_c0(struct mlx5_core_dev *mdev,
829 struct mlx5_ib_query_device_resp *resp)
830{
831 struct mlx5_eswitch *esw = mdev->priv.eswitch;
832 u16 vport = mlx5_eswitch_manager_vport(mdev);
833
834 resp->reg_c0.value = mlx5_eswitch_get_vport_metadata_for_match(esw,
835 vport);
836 resp->reg_c0.mask = mlx5_eswitch_get_vport_metadata_mask();
837}
838
e126ba97 839static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 840 struct ib_device_attr *props,
841 struct ib_udata *uhw)
e126ba97 842{
48357091 843 size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
e126ba97 844 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 845 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 846 int err = -ENOMEM;
288c01b7 847 int max_sq_desc;
e126ba97
EC		 848 int max_rq_sg;
849 int max_sq_sg;
e0238a6a 850 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 851 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 852 struct mlx5_ib_query_device_resp resp = {};
853 size_t resp_len;
854 u64 max_tso;
e126ba97 855
402ca536 856 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
48357091 857 if (uhw_outlen && uhw_outlen < resp_len)
402ca536 858 return -EINVAL;
6f26b2ac
EA		 859
860 resp.response_length = resp_len;
402ca536 861
48357091 862 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 863 return -EINVAL;
864
1b5daf11
MD		 865 memset(props, 0, sizeof(*props));
866 err = mlx5_query_system_image_guid(ibdev,
867 &props->sys_image_guid);
868 if (err)
869 return err;
e126ba97 870
2019d70e 871 props->max_pkeys = dev->pkey_table_len;
e126ba97 872
1b5daf11
MD		 873 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
874 if (err)
875 return err;
e126ba97 876
9603b61d
JM		 877 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
878 (fw_rev_min(dev->mdev) << 16) |
879 fw_rev_sub(dev->mdev);
e126ba97
EC		 880 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
881 IB_DEVICE_PORT_ACTIVE_EVENT |
882 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 883 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 884
885 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 886 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 887 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 888 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 889 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 890 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 891 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 892 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 893 if (MLX5_CAP_GEN(mdev, imaicl)) {
894 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
895 IB_DEVICE_MEM_WINDOW_TYPE_2B;
896 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316 897 /* We support 'Gappy' memory registration too */
e945c653 898 props->kernel_cap_flags |= IBK_SG_GAPS_REG;
d2370e0a 899 }
0ec52f01
JG		 900 /* IB_WR_REG_MR always requires changing the entity size with UMR */
901 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
902 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 903 if (MLX5_CAP_GEN(mdev, sho)) {
e945c653 904 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER;
2dea9094
SG		 905 /* At this stage no support for signature handover */
906 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
907 IB_PROT_T10DIF_TYPE_2 |
908 IB_PROT_T10DIF_TYPE_3;
909 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
910 IB_GUARD_T10DIF_CSUM;
911 }
938fe83c 912 if (MLX5_CAP_GEN(mdev, block_lb_mc))
e945c653 913 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK;
e126ba97 914
85c7c014 915 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 916 if (MLX5_CAP_ETH(mdev, csum_cap)) {
917 /* Legacy bit to support old userspace libraries */
88115fe7 918 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 919 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
920 }
921
922 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
923 props->raw_packet_caps |=
924 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 925
a762d460 926 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
402ca536
BW		 927 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
928 if (max_tso) {
929 resp.tso_caps.max_tso = 1 << max_tso;
930 resp.tso_caps.supported_qpts |=
931 1 << IB_QPT_RAW_PACKET;
932 resp.response_length += sizeof(resp.tso_caps);
933 }
934 }
31f69a82 935
a762d460 936 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
31f69a82
YH		 937 resp.rss_caps.rx_hash_function =
938 MLX5_RX_HASH_FUNC_TOEPLITZ;
939 resp.rss_caps.rx_hash_fields_mask =
940 MLX5_RX_HASH_SRC_IPV4 |
941 MLX5_RX_HASH_DST_IPV4 |
942 MLX5_RX_HASH_SRC_IPV6 |
943 MLX5_RX_HASH_DST_IPV6 |
944 MLX5_RX_HASH_SRC_PORT_TCP |
945 MLX5_RX_HASH_DST_PORT_TCP |
946 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 947 MLX5_RX_HASH_DST_PORT_UDP |
948 MLX5_RX_HASH_INNER;
31f69a82
YH		 949 resp.response_length += sizeof(resp.rss_caps);
950 }
951 } else {
a762d460 952 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
31f69a82 953 resp.response_length += sizeof(resp.tso_caps);
a762d460 954 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
31f69a82 955 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 956 }
957
f0313965
ES		 958 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
959 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
e945c653 960 props->kernel_cap_flags |= IBK_UD_TSO;
f0313965
ES		 961 }
962
03404e8a 963 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 964 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
965 raw_support)
03404e8a
MG		 966 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
967
1d54f890
YH		 968 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
969 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
970 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
971
cff5a0f3 972 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 973 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
974 raw_support) {
e8161334 975 /* Legacy bit to support old userspace libraries */
cff5a0f3 976 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 977 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
978 }
cff5a0f3 979
24da0016
AL		 980 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
981 props->max_dm_size =
982 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
983 }
984
da6d6ba3
MG		 985 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
986 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
987
b1383aa6
NO		 988 if (MLX5_CAP_GEN(mdev, end_pad))
989 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
990
1b5daf11
MD		 991 props->vendor_part_id = mdev->pdev->device;
992 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 993
994 props->max_mr_size = ~0ull;
e0238a6a 995 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 996 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
997 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
998 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
999 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 1000 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
1001 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
1002 sizeof(struct mlx5_wqe_raddr_seg)) /
1003 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 1004 props->max_send_sge = max_sq_sg;
1005 props->max_recv_sge = max_rq_sg;
986ef95e 1006 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 1007 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 1008 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 1009 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1010 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
1011 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
1012 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
1013 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
1014 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
1015 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 1016 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 1017 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 1018 props->max_fast_reg_page_list_len =
1019 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
62e3c379
MG		 1020 props->max_pi_fast_reg_page_list_len =
1021 props->max_fast_reg_page_list_len / 2;
36609056
YF		 1022 props->max_sgl_rd =
1023 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
776a3906 1024 get_atomic_caps_qp(dev, props);
81bea28f 1025 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 1026 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1027 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 1028 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1029 props->max_mcast_grp;
86695a65 1030 props->max_ah = INT_MAX;
7c60bcbb
MB		 1031 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1032 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 1033
e502b8b0 1034 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
00815752 1035 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
e945c653 1036 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING;
e502b8b0 1037 props->odp_caps = dev->odp_caps;
a73a8955
MS		 1038 if (!uhw) {
1039 /* ODP for kernel QPs is not implemented for receive
1040 * WQEs and SRQ WQEs
1041 */
1042 props->odp_caps.per_transport_caps.rc_odp_caps &=
1043 ~(IB_ODP_SUPPORT_READ |
1044 IB_ODP_SUPPORT_SRQ_RECV);
1045 props->odp_caps.per_transport_caps.uc_odp_caps &=
1046 ~(IB_ODP_SUPPORT_READ |
1047 IB_ODP_SUPPORT_SRQ_RECV);
1048 props->odp_caps.per_transport_caps.ud_odp_caps &=
1049 ~(IB_ODP_SUPPORT_READ |
1050 IB_ODP_SUPPORT_SRQ_RECV);
1051 props->odp_caps.per_transport_caps.xrc_odp_caps &=
1052 ~(IB_ODP_SUPPORT_READ |
1053 IB_ODP_SUPPORT_SRQ_RECV);
1054 }
e502b8b0 1055 }
8cdd312c 1056
e53a9d26 1057 if (mlx5_core_is_vf(mdev))
e945c653 1058 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION;
eff901d3 1059
31f69a82 1060 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 1061 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 1062 props->rss_caps.max_rwq_indirection_tables =
1063 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1064 props->rss_caps.max_rwq_indirection_table_size =
1065 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1066 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1067 props->max_wq_type_rq =
1068 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1069 }
1070
eb761894 1071 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0 1072 props->tm_caps.max_num_tags =
eb761894 1073 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0 1074 props->tm_caps.max_ops =
eb761894 1075 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 1076 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 1077 }
1078
89705e92
DG		 1079 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1080 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1081 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1082 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1083 }
1084
87ab3f52
YC		 1085 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1086 props->cq_caps.max_cq_moderation_count =
1087 MLX5_MAX_CQ_COUNT;
1088 props->cq_caps.max_cq_moderation_period =
1089 MLX5_MAX_CQ_PERIOD;
1090 }
1091
a762d460 1092 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
7e43a2a5 1093 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 1094
1095 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1096 resp.cqe_comp_caps.max_num =
1097 MLX5_CAP_GEN(dev->mdev,
1098 cqe_compression_max_num);
1099
1100 resp.cqe_comp_caps.supported_format =
1101 MLX5_IB_CQE_RES_FORMAT_HASH |
1102 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 1103
1104 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1105 resp.cqe_comp_caps.supported_format |=
1106 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 1107 }
7e43a2a5
BW		 1108 }
1109
a762d460 1110 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
85c7c014 1111 raw_support) {
d949167d
BW		 1112 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1113 MLX5_CAP_GEN(mdev, qos)) {
1114 resp.packet_pacing_caps.qp_rate_limit_max =
1115 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1116 resp.packet_pacing_caps.qp_rate_limit_min =
1117 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1118 resp.packet_pacing_caps.supported_qpts |=
1119 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 1120 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1121 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1122 resp.packet_pacing_caps.cap_flags |=
1123 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 1124 }
1125 resp.response_length += sizeof(resp.packet_pacing_caps);
1126 }
1127
a762d460
LR		 1128 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1129 uhw_outlen) {
795b609c
BW		 1130 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1131 resp.mlx5_ib_support_multi_pkt_send_wqes =
1132 MLX5_IB_ALLOW_MPW;
050da902
BW		 1133
1134 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1135 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1136 MLX5_IB_SUPPORT_EMPW;
1137
9f885201
LR		 1138 resp.response_length +=
1139 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1140 }
1141
a762d460 1142 if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
de57f2ad 1143 resp.response_length += sizeof(resp.flags);
7a0c8f42 1144
de57f2ad
GL		 1145 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1146 resp.flags |=
1147 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1148
1149 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1150 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
7e11b911
DG		 1151 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1152 resp.flags |=
1153 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
7249c8ea
GL		 1154
1155 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
de57f2ad 1156 }
9f885201 1157
a762d460 1158 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
96dc3fc5
NO		 1159 resp.response_length += sizeof(resp.sw_parsing_caps);
1160 if (MLX5_CAP_ETH(mdev, swp)) {
1161 resp.sw_parsing_caps.sw_parsing_offloads |=
1162 MLX5_IB_SW_PARSING;
1163
1164 if (MLX5_CAP_ETH(mdev, swp_csum))
1165 resp.sw_parsing_caps.sw_parsing_offloads |=
1166 MLX5_IB_SW_PARSING_CSUM;
1167
1168 if (MLX5_CAP_ETH(mdev, swp_lso))
1169 resp.sw_parsing_caps.sw_parsing_offloads |=
1170 MLX5_IB_SW_PARSING_LSO;
1171
1172 if (resp.sw_parsing_caps.sw_parsing_offloads)
1173 resp.sw_parsing_caps.supported_qpts =
1174 BIT(IB_QPT_RAW_PACKET);
1175 }
1176 }
1177
a762d460 1178 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
85c7c014 1179 raw_support) {
b4f34597
NO		 1180 resp.response_length += sizeof(resp.striding_rq_caps);
1181 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1182 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1183 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1184 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1185 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
c16339b6
MZ		 1186 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1187 resp.striding_rq_caps
1188 .min_single_wqe_log_num_of_strides =
1189 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1190 else
1191 resp.striding_rq_caps
1192 .min_single_wqe_log_num_of_strides =
1193 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
b4f34597
NO		 1194 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1195 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1196 resp.striding_rq_caps.supported_qpts =
1197 BIT(IB_QPT_RAW_PACKET);
1198 }
1199 }
1200
a762d460 1201 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
f95ef6cb
MG		 1202 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1203 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1204 resp.tunnel_offloads_caps |=
1205 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1206 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1207 resp.tunnel_offloads_caps |=
1208 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1209 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1210 resp.tunnel_offloads_caps |=
1211 MLX5_IB_TUNNELED_OFFLOADS_GRE;
41e684ef 1212 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
e818e255
AL		 1213 resp.tunnel_offloads_caps |=
1214 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
41e684ef 1215 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
e818e255
AL		 1216 resp.tunnel_offloads_caps |=
1217 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1218 }
1219
11656f59
LN		 1220 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) {
1221 resp.response_length += sizeof(resp.dci_streams_caps);
1222
1223 resp.dci_streams_caps.max_log_num_concurent =
1224 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels);
1225
1226 resp.dci_streams_caps.max_log_num_errored =
1227 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams);
1228 }
1229
d727d27d
MB		 1230 if (offsetofend(typeof(resp), reserved) <= uhw_outlen)
1231 resp.response_length += sizeof(resp.reserved);
1232
1233 if (offsetofend(typeof(resp), reg_c0) <= uhw_outlen) {
1234 struct mlx5_eswitch *esw = mdev->priv.eswitch;
1235
1236 resp.response_length += sizeof(resp.reg_c0);
1237
1238 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS &&
1239 mlx5_eswitch_vport_match_metadata_enabled(esw))
1240 fill_esw_mgr_reg_c0(mdev, &resp);
1241 }
1242
48357091 1243 if (uhw_outlen) {
402ca536
BW		 1244 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1245
1246 if (err)
1247 return err;
1248 }
1249
1b5daf11 1250 return 0;
e126ba97
EC		 1251}
1252
639bf441
AL		 1253static void translate_active_width(struct ib_device *ibdev, u16 active_width,
1254 u8 *ib_width)
e126ba97
EC		 1255{
1256 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11 1257
e27014bd 1258 if (active_width & MLX5_PTYS_WIDTH_1X)
1b5daf11 1259 *ib_width = IB_WIDTH_1X;
e27014bd 1260 else if (active_width & MLX5_PTYS_WIDTH_2X)
d764970b 1261 *ib_width = IB_WIDTH_2X;
e27014bd 1262 else if (active_width & MLX5_PTYS_WIDTH_4X)
1b5daf11 1263 *ib_width = IB_WIDTH_4X;
e27014bd 1264 else if (active_width & MLX5_PTYS_WIDTH_8X)
1b5daf11 1265 *ib_width = IB_WIDTH_8X;
e27014bd 1266 else if (active_width & MLX5_PTYS_WIDTH_12X)
1b5daf11 1267 *ib_width = IB_WIDTH_12X;
db7a691a
MG		 1268 else {
1269 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
e27014bd 1270 active_width);
db7a691a 1271 *ib_width = IB_WIDTH_4X;
e126ba97
EC		 1272 }
1273
db7a691a 1274 return;
1b5daf11 1275}
e126ba97 1276
1b5daf11
MD		 1277static int mlx5_mtu_to_ib_mtu(int mtu)
1278{
1279 switch (mtu) {
1280 case 256: return 1;
1281 case 512: return 2;
1282 case 1024: return 3;
1283 case 2048: return 4;
1284 case 4096: return 5;
1285 default:
1286 pr_warn("invalid mtu\n");
1287 return -1;
e126ba97 1288 }
1b5daf11 1289}
e126ba97 1290
1b5daf11
MD		 1291enum ib_max_vl_num {
1292 __IB_MAX_VL_0 = 1,
1293 __IB_MAX_VL_0_1 = 2,
1294 __IB_MAX_VL_0_3 = 3,
1295 __IB_MAX_VL_0_7 = 4,
1296 __IB_MAX_VL_0_14 = 5,
1297};
e126ba97 1298
1b5daf11
MD		 1299enum mlx5_vl_hw_cap {
1300 MLX5_VL_HW_0 = 1,
1301 MLX5_VL_HW_0_1 = 2,
1302 MLX5_VL_HW_0_2 = 3,
1303 MLX5_VL_HW_0_3 = 4,
1304 MLX5_VL_HW_0_4 = 5,
1305 MLX5_VL_HW_0_5 = 6,
1306 MLX5_VL_HW_0_6 = 7,
1307 MLX5_VL_HW_0_7 = 8,
1308 MLX5_VL_HW_0_14 = 15
1309};
e126ba97 1310
1b5daf11
MD		 1311static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1312 u8 *max_vl_num)
1313{
1314 switch (vl_hw_cap) {
1315 case MLX5_VL_HW_0:
1316 *max_vl_num = __IB_MAX_VL_0;
1317 break;
1318 case MLX5_VL_HW_0_1:
1319 *max_vl_num = __IB_MAX_VL_0_1;
1320 break;
1321 case MLX5_VL_HW_0_3:
1322 *max_vl_num = __IB_MAX_VL_0_3;
1323 break;
1324 case MLX5_VL_HW_0_7:
1325 *max_vl_num = __IB_MAX_VL_0_7;
1326 break;
1327 case MLX5_VL_HW_0_14:
1328 *max_vl_num = __IB_MAX_VL_0_14;
1329 break;
e126ba97 1330
1b5daf11
MD		 1331 default:
1332 return -EINVAL;
e126ba97 1333 }
e126ba97 1334
1b5daf11 1335 return 0;
e126ba97
EC		 1336}
1337
1fb7f897 1338static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port,
1b5daf11 1339 struct ib_port_attr *props)
e126ba97 1340{
1b5daf11
MD		 1341 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1342 struct mlx5_core_dev *mdev = dev->mdev;
1343 struct mlx5_hca_vport_context *rep;
3b43399b 1344 u8 vl_hw_cap, plane_index = 0;
046339ea
SM		 1345 u16 max_mtu;
1346 u16 oper_mtu;
1b5daf11 1347 int err;
639bf441 1348 u16 ib_link_width_oper;
e126ba97 1349
1b5daf11
MD		 1350 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1351 if (!rep) {
1352 err = -ENOMEM;
e126ba97 1353 goto out;
e126ba97 1354 }
e126ba97 1355
c4550c63 1356 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1357
3b43399b
MZ		 1358 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) {
1359 plane_index = port;
026a4259 1360 port = smi_to_native_portnum(dev, port);
3b43399b 1361 }
026a4259 1362
1b5daf11 1363 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1364 if (err)
1365 goto out;
1366
1b5daf11
MD		 1367 props->lid = rep->lid;
1368 props->lmc = rep->lmc;
1369 props->sm_lid = rep->sm_lid;
1370 props->sm_sl = rep->sm_sl;
1371 props->state = rep->vport_state;
1372 props->phys_state = rep->port_physical_state;
2a5db20f
MZ		 1373
1374 props->port_cap_flags = rep->cap_mask1;
1375 if (dev->num_plane) {
1376 props->port_cap_flags |= IB_PORT_SM_DISABLED;
1377 props->port_cap_flags &= ~IB_PORT_SM;
026a4259
MZ		 1378 } else if (ibdev->type == RDMA_DEVICE_TYPE_SMI)
1379 props->port_cap_flags &= ~IB_PORT_CM_SUP;
2a5db20f 1380
1b5daf11
MD		 1381 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1382 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1383 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1384 props->bad_pkey_cntr = rep->pkey_violation_counter;
1385 props->qkey_viol_cntr = rep->qkey_violation_counter;
1386 props->subnet_timeout = rep->subnet_timeout;
1387 props->init_type_reply = rep->init_type_reply;
e126ba97 1388
4106a758
MG		 1389 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1390 props->port_cap_flags2 = rep->cap_mask2;
1391
639bf441 1392 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
3b43399b 1393 &props->active_speed, port, plane_index);
1b5daf11 1394 if (err)
e126ba97 1395 goto out;
e126ba97 1396
db7a691a
MG		 1397 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1398
facc9699 1399 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1400
1b5daf11 1401 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1402
facc9699 1403 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1404
1b5daf11 1405 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1406
1b5daf11
MD		 1407 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1408 if (err)
1409 goto out;
e126ba97 1410
1b5daf11
MD		 1411 err = translate_max_vl_num(ibdev, vl_hw_cap,
1412 &props->max_vl_num);
e126ba97 1413out:
1b5daf11 1414 kfree(rep);
e126ba97
EC		 1415 return err;
1416}
1417
1fb7f897 1418int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1b5daf11 1419 struct ib_port_attr *props)
e126ba97 1420{
095b0927
IT		 1421 unsigned int count;
1422 int ret;
1423
1b5daf11
MD		 1424 switch (mlx5_get_vport_access_method(ibdev)) {
1425 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1426 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1427 break;
e126ba97 1428
1b5daf11 1429 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1430 ret = mlx5_query_hca_port(ibdev, port, props);
1431 break;
e126ba97 1432
3f89a643 1433 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1434 ret = mlx5_query_port_roce(ibdev, port, props);
1435 break;
3f89a643 1436
1b5daf11 1437 default:
095b0927
IT		 1438 ret = -EINVAL;
1439 }
1440
1441 if (!ret && props) {
b3cbd6f0
DJ		 1442 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1443 struct mlx5_core_dev *mdev;
1444 bool put_mdev = true;
1445
1446 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1447 if (!mdev) {
1448 /* If the port isn't affiliated yet query the master.
1449 * The master and slave will have the same values.
1450 */
1451 mdev = dev->mdev;
1452 port = 1;
1453 put_mdev = false;
1454 }
1455 count = mlx5_core_reserved_gids_count(mdev);
1456 if (put_mdev)
1457 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1458 props->gid_tbl_len -= count;
1b5daf11 1459 }
095b0927 1460 return ret;
1b5daf11 1461}
e126ba97 1462
1fb7f897 1463static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port,
8e6efa3a
MB		 1464 struct ib_port_attr *props)
1465{
7a58779e 1466 return mlx5_query_port_roce(ibdev, port, props);
8e6efa3a
MB		 1467}
1468
1fb7f897 1469static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
d6fd59e1
PP		 1470 u16 *pkey)
1471{
1472 /* Default special Pkey for representor device port as per the
1473 * IB specification 1.3 section 10.9.1.2.
1474 */
1475 *pkey = 0xffff;
1476 return 0;
1477}
1478
1fb7f897 1479static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index,
1b5daf11
MD		 1480 union ib_gid *gid)
1481{
1482 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1483 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1484
1b5daf11
MD		 1485 switch (mlx5_get_vport_access_method(ibdev)) {
1486 case MLX5_VPORT_ACCESS_METHOD_MAD:
1487 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1488
1b5daf11
MD		 1489 case MLX5_VPORT_ACCESS_METHOD_HCA:
1490 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1491
1492 default:
1493 return -EINVAL;
1494 }
e126ba97 1495
e126ba97
EC		 1496}
1497
1fb7f897 1498static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port,
b3cbd6f0 1499 u16 index, u16 *pkey)
1b5daf11
MD		 1500{
1501 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1502 struct mlx5_core_dev *mdev;
1503 bool put_mdev = true;
1fb7f897 1504 u32 mdev_port_num;
b3cbd6f0 1505 int err;
1b5daf11 1506
b3cbd6f0
DJ		 1507 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1508 if (!mdev) {
1509 /* The port isn't affiliated yet, get the PKey from the master
1510 * port. For RoCE the PKey tables will be the same.
1511 */
1512 put_mdev = false;
1513 mdev = dev->mdev;
1514 mdev_port_num = 1;
1515 }
1516
1517 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1518 index, pkey);
1519 if (put_mdev)
1520 mlx5_ib_put_native_port_mdev(dev, port);
1521
1522 return err;
1523}
1524
1fb7f897 1525static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
b3cbd6f0
DJ		 1526 u16 *pkey)
1527{
1b5daf11
MD		 1528 switch (mlx5_get_vport_access_method(ibdev)) {
1529 case MLX5_VPORT_ACCESS_METHOD_MAD:
1530 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1531
1532 case MLX5_VPORT_ACCESS_METHOD_HCA:
1533 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1534 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1535 default:
1536 return -EINVAL;
1537 }
1538}
e126ba97
EC		 1539
1540static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1541 struct ib_device_modify *props)
1542{
1543 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1544 struct mlx5_reg_node_desc in;
1545 struct mlx5_reg_node_desc out;
1546 int err;
1547
1548 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1549 return -EOPNOTSUPP;
1550
1551 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1552 return 0;
1553
1554 /*
1555 * If possible, pass node desc to FW, so it can generate
1556 * a 144 trap. If cmd fails, just ignore.
1557 */
bd99fdea 1558 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1559 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1560 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1561 if (err)
1562 return err;
1563
bd99fdea 1564 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1565
1566 return err;
1567}
1568
1fb7f897 1569static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask,
cdbe33d0
EC		 1570 u32 value)
1571{
1572 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0 1573 struct mlx5_core_dev *mdev;
1fb7f897 1574 u32 mdev_port_num;
cdbe33d0
EC		 1575 int err;
1576
b3cbd6f0
DJ		 1577 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1578 if (!mdev)
1579 return -ENODEV;
1580
1581 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1582 if (err)
b3cbd6f0 1583 goto out;
cdbe33d0
EC		 1584
1585 if (~ctx.cap_mask1_perm & mask) {
1586 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1587 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1588 err = -EINVAL;
1589 goto out;
cdbe33d0
EC		 1590 }
1591
1592 ctx.cap_mask1 = value;
1593 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1594 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1595 0, &ctx);
1596
1597out:
1598 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1599
1600 return err;
1601}
1602
1fb7f897 1603static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask,
e126ba97
EC		 1604 struct ib_port_modify *props)
1605{
1606 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1607 struct ib_port_attr attr;
1608 u32 tmp;
1609 int err;
cdbe33d0
EC		 1610 u32 change_mask;
1611 u32 value;
1612 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1613 IB_LINK_LAYER_INFINIBAND);
1614
ec255879
MD		 1615 /* CM layer calls ib_modify_port() regardless of the link layer. For
1616 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1617 */
1618 if (!is_ib)
1619 return 0;
1620
cdbe33d0
EC		 1621 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1622 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1623 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1624 return set_port_caps_atomic(dev, port, change_mask, value);
1625 }
e126ba97
EC		 1626
1627 mutex_lock(&dev->cap_mask_mutex);
1628
c4550c63 1629 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1630 if (err)
1631 goto out;
1632
1633 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1634 ~props->clr_port_cap_mask;
1635
9603b61d 1636 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1637
1638out:
1639 mutex_unlock(&dev->cap_mask_mutex);
1640 return err;
1641}
1642
30aa60b3
EC		 1643static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1644{
1645 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1646 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1647}
1648
31a78a5a
YH		 1649static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1650{
1651 /* Large page with non 4k uar support might limit the dynamic size */
1652 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1653 return MLX5_MIN_DYN_BFREGS;
1654
1655 return MLX5_MAX_DYN_BFREGS;
1656}
1657
b037c29a
EC		 1658static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1659 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1660 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1661{
1662 int uars_per_sys_page;
1663 int bfregs_per_sys_page;
1664 int ref_bfregs = req->total_num_bfregs;
1665
1666 if (req->total_num_bfregs == 0)
1667 return -EINVAL;
1668
1669 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1670 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1671
1672 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1673 return -ENOMEM;
1674
1675 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1676 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1677 /* This holds the required static allocation asked by the user */
b037c29a 1678 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1679 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1680 return -EINVAL;
1681
31a78a5a
YH		 1682 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1683 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1684 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1685 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1686
1687 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1688 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1689 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1690 req->total_num_bfregs, bfregi->total_num_bfregs,
1691 bfregi->num_sys_pages);
b037c29a
EC		 1692
1693 return 0;
1694}
1695
1696static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1697{
1698 struct mlx5_bfreg_info *bfregi;
1699 int err;
1700 int i;
1701
1702 bfregi = &context->bfregi;
31a78a5a 1703 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
d2c8a155
ML		 1704 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i],
1705 context->devx_uid);
b037c29a
EC		 1706 if (err)
1707 goto error;
1708
1709 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1710 }
4ed131d0
YH		 1711
1712 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1713 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1714
b037c29a
EC		 1715 return 0;
1716
1717error:
1718 for (--i; i >= 0; i--)
d2c8a155
ML		 1719 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i],
1720 context->devx_uid))
b037c29a
EC		 1721 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1722
1723 return err;
1724}
1725
15177999
LR		 1726static void deallocate_uars(struct mlx5_ib_dev *dev,
1727 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1728{
1729 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1730 int i;
1731
1732 bfregi = &context->bfregi;
15177999 1733 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1734 if (i < bfregi->num_static_sys_pages ||
15177999 1735 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
d2c8a155
ML		 1736 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i],
1737 context->devx_uid);
b037c29a
EC		 1738}
1739
0042f9e4 1740int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1741{
1742 int err = 0;
1743
1744 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1745 if (td)
1746 dev->lb.user_td++;
1747 if (qp)
1748 dev->lb.qps++;
1749
1750 if (dev->lb.user_td == 2 ||
1751 dev->lb.qps == 1) {
1752 if (!dev->lb.enabled) {
1753 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1754 dev->lb.enabled = true;
1755 }
1756 }
a560f1d9
MB		 1757
1758 mutex_unlock(&dev->lb.mutex);
1759
1760 return err;
1761}
1762
0042f9e4 1763void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1764{
1765 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1766 if (td)
1767 dev->lb.user_td--;
1768 if (qp)
1769 dev->lb.qps--;
1770
1771 if (dev->lb.user_td == 1 &&
1772 dev->lb.qps == 0) {
1773 if (dev->lb.enabled) {
1774 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1775 dev->lb.enabled = false;
1776 }
1777 }
a560f1d9
MB		 1778
1779 mutex_unlock(&dev->lb.mutex);
1780}
1781
d2d19121
YH		 1782static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1783 u16 uid)
c85023e1
HN		 1784{
1785 int err;
1786
cfdeb893
LR		 1787 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1788 return 0;
1789
d2d19121 1790 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1791 if (err)
1792 return err;
1793
1794 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1795 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1796 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1797 return err;
1798
0042f9e4 1799 return mlx5_ib_enable_lb(dev, true, false);
c85023e1
HN		 1800}
1801
d2d19121
YH		 1802static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1803 u16 uid)
c85023e1 1804{
cfdeb893
LR		 1805 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1806 return;
1807
d2d19121 1808 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1809
1810 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1811 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1812 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1813 return;
1814
0042f9e4 1815 mlx5_ib_disable_lb(dev, true, false);
c85023e1
HN		 1816}
1817
45ec21c9
YH		 1818static int set_ucontext_resp(struct ib_ucontext *uctx,
1819 struct mlx5_ib_alloc_ucontext_resp *resp)
1820{
1821 struct ib_device *ibdev = uctx->device;
1822 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1823 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1824 struct mlx5_bfreg_info *bfregi = &context->bfregi;
45ec21c9
YH		 1825
1826 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
594cac11 1827 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey;
45ec21c9
YH		 1828 resp->comp_mask |=
1829 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1830 }
1831
1832 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
d98995b4 1833 if (mlx5_wc_support_get(dev->mdev))
45ec21c9
YH		 1834 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
1835 log_bf_reg_size);
1836 resp->cache_line_size = cache_line_size();
1837 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1838 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1839 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1840 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1841 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1842 resp->cqe_version = context->cqe_version;
1843 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1844 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1845 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1846 MLX5_CAP_GEN(dev->mdev,
1847 num_of_uars_per_page) : 1;
45ec21c9
YH		 1848 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 :
1849 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs;
1850 resp->num_ports = dev->num_ports;
1851 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1852 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1853
1854 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1855 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
1856 resp->eth_min_inline++;
1857 }
1858
1859 if (dev->mdev->clock_info)
1860 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1861
1862 /*
1863 * We don't want to expose information from the PCI bar that is located
1864 * after 4096 bytes, so if the arch only supports larger pages, let's
1865 * pretend we don't support reading the HCA's core clock. This is also
1866 * forced by mmap function.
1867 */
1868 if (PAGE_SIZE <= 4096) {
1869 resp->comp_mask |=
1870 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1871 resp->hca_core_clock_offset =
1872 offsetof(struct mlx5_init_seg,
1873 internal_timer_h) % PAGE_SIZE;
1874 }
1875
1876 if (MLX5_CAP_GEN(dev->mdev, ece_support))
1877 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
1878
33652951
AL		 1879 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) &&
1880 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) &&
1881 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format)))
1882 resp->comp_mask |=
1883 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS;
1884
45ec21c9 1885 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
c906b86e
SG		 1886
1887 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
1888 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
1889
13ad1125
AL		 1890 resp->comp_mask |=
1891 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG;
1892
45ec21c9
YH		 1893 return 0;
1894}
1895
a2a074ef
LR		 1896static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1897 struct ib_udata *udata)
e126ba97 1898{
a2a074ef 1899 struct ib_device *ibdev = uctx->device;
e126ba97 1900 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1901 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1902 struct mlx5_ib_alloc_ucontext_resp resp = {};
a2a074ef 1903 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
2f5ff264 1904 struct mlx5_bfreg_info *bfregi;
78c0f98c 1905 int ver;
e126ba97 1906 int err;
a168a41c
MD		 1907 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1908 max_cqe_version);
b037c29a 1909 bool lib_uar_4k;
0a2fd01c 1910 bool lib_uar_dyn;
e126ba97
EC		 1911
1912 if (!dev->ib_active)
a2a074ef 1913 return -EAGAIN;
e126ba97 1914
e093111d 1915 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1916 ver = 0;
e093111d 1917 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1918 ver = 2;
1919 else
a2a074ef 1920 return -EINVAL;
78c0f98c 1921
e093111d 1922 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97 1923 if (err)
a2a074ef 1924 return err;
e126ba97 1925
a8b92ca1 1926 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
a2a074ef 1927 return -EOPNOTSUPP;
78c0f98c 1928
f72300c5 1929 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
a2a074ef 1930 return -EOPNOTSUPP;
b368d7cb 1931
2f5ff264
EC		 1932 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1933 MLX5_NON_FP_BFREGS_PER_UAR);
1934 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
a2a074ef 1935 return -EINVAL;
e126ba97 1936
d2c8a155
ML		 1937 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1938 err = mlx5_ib_devx_create(dev, true);
1939 if (err < 0)
1940 goto out_ctx;
1941 context->devx_uid = err;
1942 }
1943
30aa60b3 1944 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
0a2fd01c 1945 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
2f5ff264 1946 bfregi = &context->bfregi;
b037c29a 1947
0a2fd01c
YH		 1948 if (lib_uar_dyn) {
1949 bfregi->lib_uar_dyn = lib_uar_dyn;
1950 goto uar_done;
1951 }
1952
b037c29a 1953 /* updates req->total_num_bfregs */
31a78a5a 1954 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1955 if (err)
d2c8a155 1956 goto out_devx;
e126ba97 1957
b037c29a
EC		 1958 mutex_init(&bfregi->lock);
1959 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1960 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1961 GFP_KERNEL);
b037c29a 1962 if (!bfregi->count) {
e126ba97 1963 err = -ENOMEM;
d2c8a155 1964 goto out_devx;
e126ba97
EC		 1965 }
1966
b037c29a
EC		 1967 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1968 sizeof(*bfregi->sys_pages),
1969 GFP_KERNEL);
1970 if (!bfregi->sys_pages) {
e126ba97 1971 err = -ENOMEM;
b037c29a 1972 goto out_count;
e126ba97
EC		 1973 }
1974
b037c29a
EC		 1975 err = allocate_uars(dev, context);
1976 if (err)
1977 goto out_sys_pages;
e126ba97 1978
0a2fd01c 1979uar_done:
d2d19121
YH		 1980 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1981 context->devx_uid);
1982 if (err)
d2c8a155 1983 goto out_uars;
d2d19121 1984
e126ba97
EC		 1985 INIT_LIST_HEAD(&context->db_page_list);
1986 mutex_init(&context->db_page_mutex);
1987
45ec21c9
YH		 1988 context->cqe_version = min_t(__u8,
1989 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1990 req.max_cqe_version);
25bb36e7 1991
45ec21c9
YH		 1992 err = set_ucontext_resp(uctx, &resp);
1993 if (err)
1994 goto out_mdev;
5f62a521 1995
45ec21c9 1996 resp.response_length = min(udata->outlen, sizeof(resp));
b368d7cb 1997 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1998 if (err)
a8b92ca1 1999 goto out_mdev;
e126ba97 2000
2f5ff264
EC		 2001 bfregi->ver = ver;
2002 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
30aa60b3
EC		 2003 context->lib_caps = req.lib_caps;
2004 print_lib_caps(dev, context->lib_caps);
f72300c5 2005
802dcc7f 2006 if (mlx5_ib_lag_should_assign_affinity(dev)) {
1fb7f897 2007 u32 port = mlx5_core_native_port_num(dev->mdev) - 1;
c6a21c38
MD		 2008
2009 atomic_set(&context->tx_port_affinity,
2010 atomic_add_return(
95579e78 2011 1, &dev->port[port].roce.tx_port_affinity));
c6a21c38
MD		 2012 }
2013
a2a074ef 2014 return 0;
e126ba97 2015
a8b92ca1 2016out_mdev:
d2d19121 2017 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
146d2f1a 2018
e126ba97 2019out_uars:
b037c29a 2020 deallocate_uars(dev, context);
e126ba97 2021
b037c29a
EC		 2022out_sys_pages:
2023 kfree(bfregi->sys_pages);
e126ba97 2024
b037c29a
EC		 2025out_count:
2026 kfree(bfregi->count);
e126ba97 2027
d2c8a155
ML		 2028out_devx:
2029 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
2030 mlx5_ib_devx_destroy(dev, context->devx_uid);
2031
e126ba97 2032out_ctx:
a2a074ef 2033 return err;
e126ba97
EC		 2034}
2035
0fb556b2
YH		 2036static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext,
2037 struct uverbs_attr_bundle *attrs)
2038{
2039 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {};
2040 int ret;
2041
2042 ret = set_ucontext_resp(ibcontext, &uctx_resp);
2043 if (ret)
2044 return ret;
2045
2046 uctx_resp.response_length =
2047 min_t(size_t,
2048 uverbs_attr_get_len(attrs,
2049 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX),
2050 sizeof(uctx_resp));
2051
2052 ret = uverbs_copy_to_struct_or_zero(attrs,
2053 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
2054 &uctx_resp,
2055 sizeof(uctx_resp));
2056 return ret;
2057}
2058
a2a074ef 2059static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
e126ba97
EC		 2060{
2061 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2062 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 2063 struct mlx5_bfreg_info *bfregi;
e126ba97 2064
b037c29a 2065 bfregi = &context->bfregi;
d2d19121
YH		 2066 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2067
b037c29a
EC		 2068 deallocate_uars(dev, context);
2069 kfree(bfregi->sys_pages);
2f5ff264 2070 kfree(bfregi->count);
d2c8a155
ML		 2071
2072 if (context->devx_uid)
2073 mlx5_ib_devx_destroy(dev, context->devx_uid);
e126ba97
EC		 2074}
2075
b037c29a 2076static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 2077 int uar_idx)
e126ba97 2078{
b037c29a
EC		 2079 int fw_uars_per_page;
2080
2081 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2082
aa8106f1 2083 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 2084}
2085
342ee59d
YH		 2086static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2087 int uar_idx)
2088{
2089 unsigned int fw_uars_per_page;
2090
2091 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2092 MLX5_UARS_IN_PAGE : 1;
2093
2094 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2095}
2096
e126ba97
EC		 2097static int get_command(unsigned long offset)
2098{
2099 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2100}
2101
2102static int get_arg(unsigned long offset)
2103{
2104 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2105}
2106
2107static int get_index(unsigned long offset)
2108{
2109 return get_arg(offset);
2110}
2111
4ed131d0
YH		 2112/* Index resides in an extra byte to enable larger values than 255 */
2113static int get_extended_index(unsigned long offset)
2114{
2115 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2116}
2117
7c2344c3
MG		 2118
2119static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2120{
7c2344c3
MG		 2121}
2122
37aa5c36
GL		 2123static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2124{
2125 switch (cmd) {
2126 case MLX5_IB_MMAP_WC_PAGE:
2127 return "WC";
2128 case MLX5_IB_MMAP_REGULAR_PAGE:
2129 return "best effort WC";
2130 case MLX5_IB_MMAP_NC_PAGE:
2131 return "NC";
24da0016
AL		 2132 case MLX5_IB_MMAP_DEVICE_MEM:
2133 return "Device Memory";
37aa5c36 2134 default:
dab994bc 2135 return "Unknown";
37aa5c36
GL		 2136 }
2137}
2138
5c99eaec
FD		 2139static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2140 struct vm_area_struct *vma,
2141 struct mlx5_ib_ucontext *context)
2142{
4eb6ab13
JG		 2143 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2144 !(vma->vm_flags & VM_SHARED))
5c99eaec
FD		 2145 return -EINVAL;
2146
2147 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2148 return -EOPNOTSUPP;
2149
4eb6ab13 2150 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
5c99eaec 2151 return -EPERM;
1c71222e 2152 vm_flags_clear(vma, VM_MAYWRITE);
5c99eaec 2153
ddcdc368 2154 if (!dev->mdev->clock_info)
5c99eaec
FD		 2155 return -EOPNOTSUPP;
2156
4eb6ab13
JG		 2157 return vm_insert_page(vma, vma->vm_start,
2158 virt_to_page(dev->mdev->clock_info));
5c99eaec
FD		 2159}
2160
dc2316eb
YH		 2161static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2162{
2163 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2164 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
7be76bef 2165 struct mlx5_var_table *var_table = &dev->var_table;
d2c8a155 2166 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext);
dc2316eb
YH		 2167
2168 switch (mentry->mmap_flag) {
2169 case MLX5_IB_MMAP_TYPE_MEMIC:
cea85fa5
MG		 2170 case MLX5_IB_MMAP_TYPE_MEMIC_OP:
2171 mlx5_ib_dm_mmap_free(dev, mentry);
dc2316eb 2172 break;
7be76bef
YH		 2173 case MLX5_IB_MMAP_TYPE_VAR:
2174 mutex_lock(&var_table->bitmap_lock);
2175 clear_bit(mentry->page_idx, var_table->bitmap);
2176 mutex_unlock(&var_table->bitmap_lock);
2177 kfree(mentry);
2178 break;
342ee59d
YH		 2179 case MLX5_IB_MMAP_TYPE_UAR_WC:
2180 case MLX5_IB_MMAP_TYPE_UAR_NC:
d2c8a155
ML		 2181 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx,
2182 context->devx_uid);
342ee59d
YH		 2183 kfree(mentry);
2184 break;
dc2316eb
YH		 2185 default:
2186 WARN_ON(true);
2187 }
2188}
2189
37aa5c36 2190static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2191 struct vm_area_struct *vma,
2192 struct mlx5_ib_ucontext *context)
37aa5c36 2193{
2f5ff264 2194 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2195 int err;
2196 unsigned long idx;
aa09ea6e 2197 phys_addr_t pfn;
37aa5c36 2198 pgprot_t prot;
4ed131d0
YH		 2199 u32 bfreg_dyn_idx = 0;
2200 u32 uar_index;
2201 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2202 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2203 bfregi->num_static_sys_pages;
b037c29a 2204
0a2fd01c
YH		 2205 if (bfregi->lib_uar_dyn)
2206 return -EINVAL;
2207
b037c29a
EC		 2208 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2209 return -EINVAL;
2210
4ed131d0
YH		 2211 if (dyn_uar)
2212 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2213 else
2214 idx = get_index(vma->vm_pgoff);
2215
2216 if (idx >= max_valid_idx) {
2217 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2218 idx, max_valid_idx);
b037c29a
EC		 2219 return -EINVAL;
2220 }
37aa5c36
GL		 2221
2222 switch (cmd) {
2223 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2224 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2225 case MLX5_IB_MMAP_REGULAR_PAGE:
2226 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2227 prot = pgprot_writecombine(vma->vm_page_prot);
2228 break;
2229 case MLX5_IB_MMAP_NC_PAGE:
2230 prot = pgprot_noncached(vma->vm_page_prot);
2231 break;
2232 default:
2233 return -EINVAL;
2234 }
2235
4ed131d0
YH		 2236 if (dyn_uar) {
2237 int uars_per_page;
2238
2239 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2240 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2241 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2242 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2243 bfreg_dyn_idx, bfregi->total_num_bfregs);
2244 return -EINVAL;
2245 }
2246
2247 mutex_lock(&bfregi->lock);
2248 /* Fail if uar already allocated, first bfreg index of each
2249 * page holds its count.
2250 */
2251 if (bfregi->count[bfreg_dyn_idx]) {
2252 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2253 mutex_unlock(&bfregi->lock);
2254 return -EINVAL;
2255 }
2256
2257 bfregi->count[bfreg_dyn_idx]++;
2258 mutex_unlock(&bfregi->lock);
2259
d2c8a155
ML		 2260 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index,
2261 context->devx_uid);
4ed131d0
YH		 2262 if (err) {
2263 mlx5_ib_warn(dev, "UAR alloc failed\n");
2264 goto free_bfreg;
2265 }
2266 } else {
2267 uar_index = bfregi->sys_pages[idx];
2268 }
2269
2270 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2271 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2272
e2cd1d1a 2273 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
c043ff2c 2274 prot, NULL);
37aa5c36 2275 if (err) {
8f062287 2276 mlx5_ib_err(dev,
e2cd1d1a 2277 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
8f062287 2278 err, mmap_cmd2str(cmd));
4ed131d0 2279 goto err;
37aa5c36
GL		 2280 }
2281
4ed131d0
YH		 2282 if (dyn_uar)
2283 bfregi->sys_pages[idx] = uar_index;
2284 return 0;
2285
2286err:
2287 if (!dyn_uar)
2288 return err;
2289
d2c8a155 2290 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid);
4ed131d0
YH		 2291
2292free_bfreg:
2293 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2294
2295 return err;
37aa5c36
GL		 2296}
2297
dc2316eb
YH		 2298static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2299{
2300 unsigned long idx;
2301 u8 command;
2302
2303 command = get_command(vma->vm_pgoff);
2304 idx = get_extended_index(vma->vm_pgoff);
2305
2306 return (command << 16 | idx);
2307}
2308
2309static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2310 struct vm_area_struct *vma,
2311 struct ib_ucontext *ucontext)
24da0016 2312{
dc2316eb
YH		 2313 struct mlx5_user_mmap_entry *mentry;
2314 struct rdma_user_mmap_entry *entry;
2315 unsigned long pgoff;
2316 pgprot_t prot;
24da0016 2317 phys_addr_t pfn;
dc2316eb 2318 int ret;
24da0016 2319
dc2316eb
YH		 2320 pgoff = mlx5_vma_to_pgoff(vma);
2321 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2322 if (!entry)
24da0016
AL		 2323 return -EINVAL;
2324
dc2316eb
YH		 2325 mentry = to_mmmap(entry);
2326 pfn = (mentry->address >> PAGE_SHIFT);
342ee59d
YH		 2327 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2328 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
3f59b6c3
YH		 2329 prot = pgprot_noncached(vma->vm_page_prot);
2330 else
2331 prot = pgprot_writecombine(vma->vm_page_prot);
dc2316eb
YH		 2332 ret = rdma_user_mmap_io(ucontext, vma, pfn,
2333 entry->npages * PAGE_SIZE,
2334 prot,
2335 entry);
2336 rdma_user_mmap_entry_put(&mentry->rdma_entry);
2337 return ret;
24da0016
AL		 2338}
2339
7be76bef
YH		 2340static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2341{
9b6d3bbc
LR		 2342 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2343 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
7be76bef
YH		 2344
2345 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2346 (index & 0xFF)) << PAGE_SHIFT;
2347}
2348
e126ba97
EC		 2349static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2350{
2351 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2352 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2353 unsigned long command;
e126ba97
EC		 2354 phys_addr_t pfn;
2355
2356 command = get_command(vma->vm_pgoff);
2357 switch (command) {
37aa5c36 2358 case MLX5_IB_MMAP_WC_PAGE:
1f3db161 2359 case MLX5_IB_MMAP_ALLOC_WC:
d98995b4 2360 if (!mlx5_wc_support_get(dev->mdev))
1f3db161
YH		 2361 return -EPERM;
2362 fallthrough;
37aa5c36 2363 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2364 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 2365 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2366
2367 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2368 return -ENOSYS;
2369
d69e3bcf 2370 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2371 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2372 return -EINVAL;
2373
6cbac1e4 2374 if (vma->vm_flags & VM_WRITE)
d69e3bcf 2375 return -EPERM;
1c71222e 2376 vm_flags_clear(vma, VM_MAYWRITE);
d69e3bcf
MB		 2377
2378 /* Don't expose to user-space information it shouldn't have */
2379 if (PAGE_SIZE > 4096)
2380 return -EOPNOTSUPP;
2381
d69e3bcf
MB		 2382 pfn = (dev->mdev->iseg_base +
2383 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2384 PAGE_SHIFT;
d5e560d3
JG		 2385 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2386 PAGE_SIZE,
c043ff2c
MK		 2387 pgprot_noncached(vma->vm_page_prot),
2388 NULL);
5c99eaec
FD		 2389 case MLX5_IB_MMAP_CLOCK_INFO:
2390 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2391
e126ba97 2392 default:
dc2316eb 2393 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
e126ba97
EC		 2394 }
2395
2396 return 0;
2397}
2398
ff23dfa1 2399static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
e126ba97 2400{
21a428a0
LR		 2401 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2402 struct ib_device *ibdev = ibpd->device;
e126ba97 2403 struct mlx5_ib_alloc_pd_resp resp;
e126ba97 2404 int err;
a1069c1c 2405 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
31578def 2406 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
a1069c1c 2407 u16 uid = 0;
ff23dfa1
SR		 2408 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2409 udata, struct mlx5_ib_ucontext, ibucontext);
e126ba97 2410
ff23dfa1 2411 uid = context ? context->devx_uid : 0;
a1069c1c
YH		 2412 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2413 MLX5_SET(alloc_pd_in, in, uid, uid);
31578def 2414 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out);
21a428a0
LR		 2415 if (err)
2416 return err;
e126ba97 2417
a1069c1c
YH		 2418 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2419 pd->uid = uid;
ff23dfa1 2420 if (udata) {
e126ba97
EC		 2421 resp.pdn = pd->pdn;
2422 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
a1069c1c 2423 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
21a428a0 2424 return -EFAULT;
e126ba97 2425 }
e126ba97
EC		 2426 }
2427
21a428a0 2428 return 0;
e126ba97
EC		 2429}
2430
91a7c58f 2431static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
e126ba97
EC		 2432{
2433 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2434 struct mlx5_ib_pd *mpd = to_mpd(pd);
2435
91a7c58f 2436 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
e126ba97
EC		 2437}
2438
2439static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
038d2ef8 2440{
e126ba97 2441 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 2442 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97 2443 int err;
539ec982 2444 u16 uid;
466fa6d2 2445
539ec982
YH		 2446 uid = ibqp->pd ?
2447 to_mpd(ibqp->pd)->uid : 0;
038d2ef8 2448
2be08c30 2449 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
81e30880
YH		 2450 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2451 return -EOPNOTSUPP;
2452 }
6113cc44 2453
539ec982 2454 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 2455 if (err)
2456 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2457 ibqp->qp_num, gid->raw);
6113cc44 2458
6113cc44 2459 return err;
038d2ef8
MG		 2460}
2461
e126ba97 2462static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2d1e697e 2463{
e126ba97
EC		 2464 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2465 int err;
539ec982 2466 u16 uid;
2d1e697e 2467
539ec982
YH		 2468 uid = ibqp->pd ?
2469 to_mpd(ibqp->pd)->uid : 0;
2470 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 2471 if (err)
2472 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2473 ibqp->qp_num, gid->raw);
2474
2475 return err;
ca0d4753
MG		 2476}
2477
e126ba97 2478static int init_node_data(struct mlx5_ib_dev *dev)
71c6e863 2479{
1b5daf11 2480 int err;
71c6e863 2481
1b5daf11 2482 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2483 if (err)
1b5daf11 2484 return err;
71c6e863 2485
1b5daf11 2486 dev->mdev->rev_id = dev->mdev->pdev->revision;
71c6e863 2487
1b5daf11 2488 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
802c2125
AY		 2489}
2490
508a523f
PP		 2491static ssize_t fw_pages_show(struct device *device,
2492 struct device_attribute *attr, char *buf)
e126ba97
EC		 2493{
2494 struct mlx5_ib_dev *dev =
54747231 2495 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2d1e697e 2496
1c7fd726 2497 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97 2498}
508a523f 2499static DEVICE_ATTR_RO(fw_pages);
466fa6d2 2500
508a523f 2501static ssize_t reg_pages_show(struct device *device,
e126ba97
EC		 2502 struct device_attribute *attr, char *buf)
2503{
2504 struct mlx5_ib_dev *dev =
54747231 2505 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
038d2ef8 2506
1c7fd726 2507 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97 2508}
508a523f 2509static DEVICE_ATTR_RO(reg_pages);
038d2ef8 2510
508a523f
PP		 2511static ssize_t hca_type_show(struct device *device,
2512 struct device_attribute *attr, char *buf)
e126ba97
EC		 2513{
2514 struct mlx5_ib_dev *dev =
54747231 2515 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
038d2ef8 2516
1c7fd726 2517 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97 2518}
508a523f 2519static DEVICE_ATTR_RO(hca_type);
026bae0c 2520
508a523f
PP		 2521static ssize_t hw_rev_show(struct device *device,
2522 struct device_attribute *attr, char *buf)
e126ba97
EC		 2523{
2524 struct mlx5_ib_dev *dev =
54747231 2525 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
026bae0c 2526
1c7fd726 2527 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id);
e126ba97 2528}
508a523f 2529static DEVICE_ATTR_RO(hw_rev);
466fa6d2 2530
508a523f
PP		 2531static ssize_t board_id_show(struct device *device,
2532 struct device_attribute *attr, char *buf)
e126ba97
EC		 2533{
2534 struct mlx5_ib_dev *dev =
54747231 2535 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2d1e697e 2536
1c7fd726
JP		 2537 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2538 dev->mdev->board_id);
e126ba97 2539}
508a523f 2540static DEVICE_ATTR_RO(board_id);
038d2ef8 2541
508a523f
PP		 2542static struct attribute *mlx5_class_attributes[] = {
2543 &dev_attr_hw_rev.attr,
2544 &dev_attr_hca_type.attr,
2545 &dev_attr_board_id.attr,
2546 &dev_attr_fw_pages.attr,
2547 &dev_attr_reg_pages.attr,
2548 NULL,
2549};
038d2ef8 2550
508a523f
PP		 2551static const struct attribute_group mlx5_attr_group = {
2552 .attrs = mlx5_class_attributes,
e126ba97 2553};
038d2ef8 2554
7722f47e
HE		 2555static void pkey_change_handler(struct work_struct *work)
2556{
2557 struct mlx5_ib_port_resources *ports =
2558 container_of(work, struct mlx5_ib_port_resources,
2559 pkey_change_work);
038d2ef8 2560
8c9e7f03
LR		 2561 if (!ports->gsi)
2562 /*
2563 * We got this event before device was fully configured
2564 * and MAD registration code wasn't called/finished yet.
2565 */
2566 return;
2567
7722f47e 2568 mlx5_ib_gsi_pkey_change(ports->gsi);
7722f47e 2569}
038d2ef8 2570
89ea94a7
MG		 2571static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2572{
2573 struct mlx5_ib_qp *mqp;
2574 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2575 struct mlx5_core_cq *mcq;
2576 struct list_head cq_armed_list;
2577 unsigned long flags_qp;
2578 unsigned long flags_cq;
2579 unsigned long flags;
038d2ef8 2580
89ea94a7 2581 INIT_LIST_HEAD(&cq_armed_list);
da2f22ae 2582
89ea94a7
MG		 2583 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2584 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2585 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2586 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2587 if (mqp->sq.tail != mqp->sq.head) {
2588 send_mcq = to_mcq(mqp->ibqp.send_cq);
2589 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2590 if (send_mcq->mcq.comp &&
2591 mqp->ibqp.send_cq->comp_handler) {
2592 if (!send_mcq->mcq.reset_notify_added) {
2593 send_mcq->mcq.reset_notify_added = 1;
2594 list_add_tail(&send_mcq->mcq.reset_notify,
2595 &cq_armed_list);
2596 }
71c6e863 2597 }
89ea94a7 2598 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
71c6e863 2599 }
89ea94a7
MG		 2600 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2601 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2602 /* no handling is needed for SRQ */
2603 if (!mqp->ibqp.srq) {
2604 if (mqp->rq.tail != mqp->rq.head) {
2605 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2606 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2607 if (recv_mcq->mcq.comp &&
2608 mqp->ibqp.recv_cq->comp_handler) {
2609 if (!recv_mcq->mcq.reset_notify_added) {
2610 recv_mcq->mcq.reset_notify_added = 1;
2611 list_add_tail(&recv_mcq->mcq.reset_notify,
2612 &cq_armed_list);
2613 }
2614 }
2615 spin_unlock_irqrestore(&recv_mcq->lock,
2616 flags_cq);
2617 }
2618 }
2619 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
81e30880 2620 }
89ea94a7
MG		 2621 /*At that point all inflight post send were put to be executed as of we
2622 * lock/unlock above locks Now need to arm all involved CQs.
2623 */
2624 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4e0e2ea1 2625 mcq->comp(mcq, NULL);
81e30880 2626 }
89ea94a7 2627 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
038d2ef8
MG		 2628}
2629
03404e8a 2630static void delay_drop_handler(struct work_struct *work)
802c2125 2631{
03404e8a
MG		 2632 int err;
2633 struct mlx5_ib_delay_drop *delay_drop =
2634 container_of(work, struct mlx5_ib_delay_drop,
2635 delay_drop_work);
0f750966 2636
fe248c3a 2637 atomic_inc(&delay_drop->events_cnt);
19cc7524 2638
03404e8a 2639 mutex_lock(&delay_drop->lock);
333fbaa0 2640 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout);
03404e8a
MG		 2641 if (err) {
2642 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2643 delay_drop->timeout);
2644 delay_drop->activate = false;
0f750966 2645 }
03404e8a 2646 mutex_unlock(&delay_drop->lock);
0f750966
AL		 2647}
2648
09e574fa
SM		 2649static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2650 struct ib_event *ibev)
0f750966 2651{
1fb7f897 2652 u32 port = (eqe->data.port.port >> 4) & 0xf;
038d2ef8 2653
09e574fa
SM		 2654 switch (eqe->sub_type) {
2655 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
6cfdc7e4
AL		 2656 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2657 IB_LINK_LAYER_ETHERNET)
2658 schedule_work(&ibdev->delay_drop.delay_drop_work);
09e574fa
SM		 2659 break;
2660 default: /* do nothing */
2661 return;
038d2ef8
MG		 2662 }
2663}
2664
134e9349
SM		 2665static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2666 struct ib_event *ibev)
3b3233fb 2667{
1fb7f897 2668 u32 port = (eqe->data.port.port >> 4) & 0xf;
3b3233fb 2669
134e9349 2670 ibev->element.port_num = port;
3b3233fb 2671
134e9349
SM		 2672 switch (eqe->sub_type) {
2673 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
2674 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
2675 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
2676 /* In RoCE, port up/down events are handled in
2677 * mlx5_netdev_event().
2678 */
2679 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2680 IB_LINK_LAYER_ETHERNET)
2681 return -EINVAL;
2682
2683 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
2684 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2685 break;
038d2ef8 2686
134e9349
SM		 2687 case MLX5_PORT_CHANGE_SUBTYPE_LID:
2688 ibev->event = IB_EVENT_LID_CHANGE;
2689 break;
038d2ef8 2690
134e9349
SM		 2691 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
2692 ibev->event = IB_EVENT_PKEY_CHANGE;
2693 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2694 break;
038d2ef8 2695
134e9349
SM		 2696 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
2697 ibev->event = IB_EVENT_GID_CHANGE;
2698 break;
038d2ef8 2699
134e9349
SM		 2700 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
2701 ibev->event = IB_EVENT_CLIENT_REREGISTER;
2702 break;
2703 default:
2704 return -EINVAL;
2705 }
038d2ef8
MG		 2706
2707 return 0;
2708}
2709
d69a24e0 2710static void mlx5_ib_handle_event(struct work_struct *_work)
d4be3f44 2711{
d69a24e0
DJ		 2712 struct mlx5_ib_event_work *work =
2713 container_of(_work, struct mlx5_ib_event_work, work);
2714 struct mlx5_ib_dev *ibdev;
e126ba97 2715 struct ib_event ibev;
dbaaff2a 2716 bool fatal = false;
d4be3f44 2717
df097a27
SM		 2718 if (work->is_slave) {
2719 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
d69a24e0
DJ		 2720 if (!ibdev)
2721 goto out;
2722 } else {
df097a27 2723 ibdev = work->dev;
038d2ef8
MG		 2724 }
2725
d69a24e0 2726 switch (work->event) {
e126ba97 2727 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 2728 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2729 mlx5_ib_handle_internal_error(ibdev);
134e9349 2730 ibev.element.port_num = (u8)(unsigned long)work->param;
dbaaff2a 2731 fatal = true;
e126ba97 2732 break;
134e9349
SM		 2733 case MLX5_EVENT_TYPE_PORT_CHANGE:
2734 if (handle_port_change(ibdev, work->param, &ibev))
d69a24e0 2735 goto out;
e126ba97 2736 break;
09e574fa
SM		 2737 case MLX5_EVENT_TYPE_GENERAL_EVENT:
2738 handle_general_event(ibdev, work->param, &ibev);
df561f66 2739 fallthrough;
bdc37924 2740 default:
03404e8a 2741 goto out;
e126ba97 2742 }
038d2ef8 2743
134e9349 2744 ibev.device = &ibdev->ib_dev;
a550ddfc 2745
134e9349
SM		 2746 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
2747 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
03404e8a 2748 goto out;
a550ddfc 2749 }
a550ddfc 2750
e126ba97
EC		 2751 if (ibdev->ib_active)
2752 ib_dispatch_event(&ibev);
5e95af5f 2753
dbaaff2a
EC		 2754 if (fatal)
2755 ibdev->ib_active = false;
03404e8a 2756out:
d69a24e0 2757 kfree(work);
5e95af5f
RS		 2758}
2759
df097a27
SM		 2760static int mlx5_ib_event(struct notifier_block *nb,
2761 unsigned long event, void *param)
3b3233fb 2762{
d69a24e0 2763 struct mlx5_ib_event_work *work;
3b3233fb 2764
d69a24e0 2765 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 2766 if (!work)
df097a27 2767 return NOTIFY_DONE;
3b3233fb 2768
10bea9c8 2769 INIT_WORK(&work->work, mlx5_ib_handle_event);
df097a27
SM		 2770 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
2771 work->is_slave = false;
10bea9c8 2772 work->param = param;
10bea9c8 2773 work->event = event;
3b3233fb 2774
10bea9c8 2775 queue_work(mlx5_ib_event_wq, &work->work);
3b3233fb 2776
df097a27 2777 return NOTIFY_OK;
3b3233fb
RS		 2778}
2779
df097a27
SM		 2780static int mlx5_ib_event_slave_port(struct notifier_block *nb,
2781 unsigned long event, void *param)
3b3233fb 2782{
df097a27 2783 struct mlx5_ib_event_work *work;
7c34ec19 2784
df097a27
SM		 2785 work = kmalloc(sizeof(*work), GFP_ATOMIC);
2786 if (!work)
2787 return NOTIFY_DONE;
9ef9c640 2788
df097a27
SM		 2789 INIT_WORK(&work->work, mlx5_ib_handle_event);
2790 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
2791 work->is_slave = true;
2792 work->param = param;
2793 work->event = event;
2794 queue_work(mlx5_ib_event_wq, &work->work);
2795
2796 return NOTIFY_OK;
9ef9c640
AH		 2797}
2798
2a5db20f
MZ		 2799static int mlx5_ib_get_plane_num(struct mlx5_core_dev *mdev, u8 *num_plane)
2800{
2801 struct mlx5_hca_vport_context vport_ctx;
2802 int err;
2803
2804 *num_plane = 0;
2805 if (!MLX5_CAP_GEN(mdev, ib_virt))
2806 return 0;
2807
2808 err = mlx5_query_hca_vport_context(mdev, 0, 1, 0, &vport_ctx);
2809 if (err)
2810 return err;
2811
2812 *num_plane = vport_ctx.num_plane;
2813 return 0;
2814}
2815
c43f1112 2816static int set_has_smi_cap(struct mlx5_ib_dev *dev)
d012f5d6 2817{
c43f1112 2818 struct mlx5_hca_vport_context vport_ctx;
d012f5d6 2819 int err;
c43f1112 2820 int port;
d012f5d6 2821
4b83c3ca
MB		 2822 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB)
2823 return 0;
2824
2825 for (port = 1; port <= dev->num_ports; port++) {
2a5db20f
MZ		 2826 if (dev->num_plane) {
2827 dev->port_caps[port - 1].has_smi = false;
2828 continue;
026a4259
MZ		 2829 } else if (!MLX5_CAP_GEN(dev->mdev, ib_virt) ||
2830 dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) {
4b83c3ca
MB		 2831 dev->port_caps[port - 1].has_smi = true;
2832 continue;
c43f1112 2833 }
2a5db20f 2834
4b83c3ca
MB		 2835 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0,
2836 &vport_ctx);
2837 if (err) {
2838 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2839 port, err);
2840 return err;
2841 }
2842 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi;
d012f5d6 2843 }
4b83c3ca 2844
d012f5d6
OG		 2845 return 0;
2846}
2847
e126ba97 2848static void get_ext_port_caps(struct mlx5_ib_dev *dev)
5ec8c83e 2849{
13179652 2850 unsigned int port;
e126ba97 2851
13179652 2852 rdma_for_each_port (&dev->ib_dev, port)
e126ba97 2853 mlx5_query_ext_port_caps(dev, port);
5ec8c83e
AH		 2854}
2855
6e8484c5
MG		 2856static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2857{
2858 switch (umr_fence_cap) {
2859 case MLX5_CAP_UMR_FENCE_NONE:
2860 return MLX5_FENCE_MODE_NONE;
2861 case MLX5_CAP_UMR_FENCE_SMALL:
2862 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2863 default:
2864 return MLX5_FENCE_MODE_STRONG_ORDERING;
2865 }
2866}
7c16f477 2867
5895e70f 2868int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev)
e126ba97 2869{
1e2b5a90 2870 struct mlx5_ib_resources *devr = &dev->devr;
bcf4c1ea 2871 struct ib_cq_init_attr cq_attr = {.cqe = 1};
5895e70f
JL		 2872 struct ib_device *ibdev;
2873 struct ib_pd *pd;
2874 struct ib_cq *cq;
e126ba97 2875 int ret = 0;
7c16f477 2876
7c16f477 2877
5895e70f
JL		 2878 /*
2879 * devr->c0 is set once, never changed until device unload.
2880 * Avoid taking the mutex if initialization is already done.
2881 */
2882 if (devr->c0)
2883 return 0;
7c16f477 2884
5895e70f
JL		 2885 mutex_lock(&devr->cq_lock);
2886 if (devr->c0)
2887 goto unlock;
d7fab916 2888
5895e70f
JL		 2889 ibdev = &dev->ib_dev;
2890 pd = ib_alloc_pd(ibdev, 0);
2891 if (IS_ERR(pd)) {
2892 ret = PTR_ERR(pd);
2893 mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%d\n", ret);
2894 goto unlock;
e126ba97 2895 }
9f876f3d 2896
5895e70f
JL		 2897 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr);
2898 if (IS_ERR(cq)) {
2899 ret = PTR_ERR(cq);
2900 mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%d\n", ret);
2901 ib_dealloc_pd(pd);
2902 goto unlock;
2903 }
0837e86a 2904
5895e70f
JL		 2905 devr->p0 = pd;
2906 devr->c0 = cq;
2907
2908unlock:
2909 mutex_unlock(&devr->cq_lock);
2910 return ret;
2911}
2912
2913int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev)
2914{
2915 struct mlx5_ib_resources *devr = &dev->devr;
2916 struct ib_srq_init_attr attr;
2917 struct ib_srq *s0, *s1;
2918 int ret = 0;
2919
2920 /*
2921 * devr->s1 is set once, never changed until device unload.
2922 * Avoid taking the mutex if initialization is already done.
2923 */
2924 if (devr->s1)
2925 return 0;
2926
2927 mutex_lock(&devr->srq_lock);
2928 if (devr->s1)
2929 goto unlock;
2930
2931 ret = mlx5_ib_dev_res_cq_init(dev);
f4375443 2932 if (ret)
5895e70f 2933 goto unlock;
3e1f000f 2934
e126ba97
EC		 2935 memset(&attr, 0, sizeof(attr));
2936 attr.attr.max_sge = 1;
2937 attr.attr.max_wr = 1;
2938 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 2939 attr.ext.cq = devr->c0;
66247fbb 2940
5895e70f
JL		 2941 s0 = ib_create_srq(devr->p0, &attr);
2942 if (IS_ERR(s0)) {
2943 ret = PTR_ERR(s0);
2944 mlx5_ib_err(dev, "Couldn't create SRQ 0 for res init, err=%d\n", ret);
2945 goto unlock;
20da44df 2946 }
7c16f477 2947
4aa17b28
HA		 2948 memset(&attr, 0, sizeof(attr));
2949 attr.attr.max_sge = 1;
2950 attr.attr.max_wr = 1;
2951 attr.srq_type = IB_SRQT_BASIC;
58dcb60a 2952
5895e70f
JL		 2953 s1 = ib_create_srq(devr->p0, &attr);
2954 if (IS_ERR(s1)) {
2955 ret = PTR_ERR(s1);
2956 mlx5_ib_err(dev, "Couldn't create SRQ 1 for res init, err=%d\n", ret);
2957 ib_destroy_srq(s0);
2958 }
2959
2960 devr->s0 = s0;
2961 devr->s1 = s1;
2962
2963unlock:
2964 mutex_unlock(&devr->srq_lock);
2965 return ret;
2966}
2967
2968static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
2969{
2970 struct mlx5_ib_resources *devr = &dev->devr;
2971 int port;
2972 int ret;
2973
2974 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2975 return -EOPNOTSUPP;
2976
2977 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
2978 if (ret)
2979 return ret;
2980
2981 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
2982 if (ret) {
2983 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2984 return ret;
20da44df 2985 }
7c16f477 2986
f8225e34 2987 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
7722f47e
HE		 2988 INIT_WORK(&devr->ports[port].pkey_change_work,
2989 pkey_change_handler);
7c16f477 2990
5895e70f
JL		 2991 mutex_init(&devr->cq_lock);
2992 mutex_init(&devr->srq_lock);
7c16f477 2993
5895e70f 2994 return 0;
7c16f477
KH		 2995}
2996
1e2b5a90 2997static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev)
7c16f477 2998{
1e2b5a90 2999 struct mlx5_ib_resources *devr = &dev->devr;
7722f47e 3000 int port;
d7fab916 3001
b0791dbf
LR		 3002 /*
3003 * Make sure no change P_Key work items are still executing.
3004 *
3005 * At this stage, the mlx5_ib_event should be unregistered
3006 * and it ensures that no new works are added.
3007 */
5d8f6a0e 3008 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
7722f47e 3009 cancel_work_sync(&devr->ports[port].pkey_change_work);
b0791dbf 3010
5895e70f
JL		 3011 /* After s0/s1 init, they are not unset during the device lifetime. */
3012 if (devr->s1) {
3013 ib_destroy_srq(devr->s1);
3014 ib_destroy_srq(devr->s0);
3015 }
f4375443
LR		 3016 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
3017 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
5895e70f
JL		 3018 /* After p0/c0 init, they are not unset during the device lifetime. */
3019 if (devr->c0) {
3020 ib_destroy_cq(devr->c0);
3021 ib_dealloc_pd(devr->p0);
3022 }
3023 mutex_destroy(&devr->cq_lock);
3024 mutex_destroy(&devr->srq_lock);
0837e86a
MB		 3025}
3026
b02289b3
AK		 3027static u32 get_core_cap_flags(struct ib_device *ibdev,
3028 struct mlx5_hca_vport_context *rep)
0837e86a 3029{
e53505a8
AS		 3030 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3031 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3032 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3033 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 3034 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8 3035 u32 ret = 0;
aac4492e 3036
b02289b3
AK		 3037 if (rep->grh_required)
3038 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
7c16f477 3039
2a5db20f
MZ		 3040 if (dev->num_plane)
3041 return ret | RDMA_CORE_CAP_PROT_IB | RDMA_CORE_CAP_IB_MAD |
3042 RDMA_CORE_CAP_IB_CM | RDMA_CORE_CAP_IB_SA |
3043 RDMA_CORE_CAP_AF_IB;
026a4259
MZ		 3044 else if (ibdev->type == RDMA_DEVICE_TYPE_SMI)
3045 return ret | RDMA_CORE_CAP_IB_MAD | RDMA_CORE_CAP_IB_SMI;
2a5db20f 3046
e53505a8 3047 if (ll == IB_LINK_LAYER_INFINIBAND)
b02289b3 3048 return ret | RDMA_CORE_PORT_IBA_IB;
bfd745f8 3049
85c7c014 3050 if (raw_support)
b02289b3 3051 ret |= RDMA_CORE_PORT_RAW_PACKET;
bfd745f8 3052
e53505a8 3053 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 3054 return ret;
0837e86a 3055
e53505a8 3056 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 3057 return ret;
0837e86a 3058
e53505a8
AS		 3059 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3060 ret |= RDMA_CORE_PORT_IBA_ROCE;
3e1f000f 3061
e53505a8
AS		 3062 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3063 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3e1f000f 3064
e53505a8 3065 return ret;
3e1f000f
PP		 3066}
3067
1fb7f897 3068static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num,
7738613e 3069 struct ib_port_immutable *immutable)
0ad17a8f 3070{
7738613e 3071 struct ib_port_attr attr;
7c16f477 3072 struct mlx5_ib_dev *dev = to_mdev(ibdev);
ca5b91d6 3073 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
b02289b3 3074 struct mlx5_hca_vport_context rep = {0};
7738613e 3075 int err;
0ad17a8f 3076
c4550c63 3077 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 3078 if (err)
3079 return err;
3080
b02289b3 3081 if (ll == IB_LINK_LAYER_INFINIBAND) {
026a4259
MZ		 3082 if (ibdev->type == RDMA_DEVICE_TYPE_SMI)
3083 port_num = smi_to_native_portnum(dev, port_num);
3084
b02289b3
AK		 3085 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
3086 &rep);
3087 if (err)
3088 return err;
3089 }
0ad17a8f 3090
7738613e
IW		 3091 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3092 immutable->gid_tbl_len = attr.gid_tbl_len;
b02289b3 3093 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
94de879c 3094 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3e1f000f 3095
7738613e 3096 return 0;
0ad17a8f
MB		 3097}
3098
1fb7f897 3099static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num,
8e6efa3a 3100 struct ib_port_immutable *immutable)
0ad17a8f 3101{
8e6efa3a
MB		 3102 struct ib_port_attr attr;
3103 int err;
0ad17a8f 3104
8e6efa3a 3105 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
0ad17a8f 3106
8e6efa3a
MB		 3107 err = ib_query_port(ibdev, port_num, &attr);
3108 if (err)
3109 return err;
3110
3111 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3112 immutable->gid_tbl_len = attr.gid_tbl_len;
3113 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
7c16f477 3114
66247fbb 3115 return 0;
e1f24a79
PP		 3116}
3117
9abb0d1b 3118static void get_dev_fw_str(struct ib_device *ibdev, char *str)
9f876f3d 3119{
c7342823
IW		 3120 struct mlx5_ib_dev *dev =
3121 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 3122 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3123 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3124 fw_rev_sub(dev->mdev));
9f876f3d
TB		 3125}
3126
45f95acd 3127static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
e1f24a79 3128{
9ef9c640
AH		 3129 struct mlx5_core_dev *mdev = dev->mdev;
3130 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3131 MLX5_FLOW_NAMESPACE_LAG);
3132 struct mlx5_flow_table *ft;
3133 int err;
e1f24a79 3134
c446d9da 3135 if (!ns || !mlx5_lag_is_active(mdev))
9ef9c640 3136 return 0;
aac4492e 3137
9ef9c640
AH		 3138 err = mlx5_cmd_create_vport_lag(mdev);
3139 if (err)
3140 return err;
e1f24a79 3141
9ef9c640
AH		 3142 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3143 if (IS_ERR(ft)) {
3144 err = PTR_ERR(ft);
3145 goto err_destroy_vport_lag;
9f876f3d
TB		 3146 }
3147
9a4ca38d 3148 dev->flow_db->lag_demux_ft = ft;
34a30d76 3149 dev->lag_ports = mlx5_lag_get_num_ports(mdev);
7c34ec19 3150 dev->lag_active = true;
9ef9c640 3151 return 0;
e1f24a79 3152
9ef9c640
AH		 3153err_destroy_vport_lag:
3154 mlx5_cmd_destroy_vport_lag(mdev);
3155 return err;
0ad17a8f
MB		 3156}
3157
45f95acd 3158static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
18d422ce 3159{
9ef9c640 3160 struct mlx5_core_dev *mdev = dev->mdev;
18d422ce 3161
7c34ec19
AH		 3162 if (dev->lag_active) {
3163 dev->lag_active = false;
18d422ce 3164
9a4ca38d
MB		 3165 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
3166 dev->flow_db->lag_demux_ft = NULL;
18d422ce 3167
9ef9c640
AH		 3168 mlx5_cmd_destroy_vport_lag(mdev);
3169 }
18d422ce
MZ		 3170}
3171
dca55da0
JP		 3172static void mlx5_netdev_notifier_register(struct mlx5_roce *roce,
3173 struct net_device *netdev)
66247fbb 3174{
d012f5d6 3175 int err;
66247fbb 3176
dca55da0
JP		 3177 if (roce->tracking_netdev)
3178 return;
3179 roce->tracking_netdev = netdev;
3180 roce->nb.notifier_call = mlx5_netdev_event;
3181 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn);
3182 WARN_ON(err);
3183}
66247fbb 3184
dca55da0
JP		 3185static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce)
3186{
3187 if (!roce->tracking_netdev)
3188 return;
3189 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb,
3190 &roce->nn);
3191 roce->tracking_netdev = NULL;
66247fbb
LR		 3192}
3193
dca55da0
JP		 3194static int mlx5e_mdev_notifier_event(struct notifier_block *nb,
3195 unsigned long event, void *data)
45842fc6 3196{
dca55da0
JP		 3197 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb);
3198 struct net_device *netdev = data;
3199
3200 switch (event) {
3201 case MLX5_DRIVER_EVENT_UPLINK_NETDEV:
3202 if (netdev)
3203 mlx5_netdev_notifier_register(roce, netdev);
3204 else
3205 mlx5_netdev_notifier_unregister(roce);
3206 break;
3207 default:
3208 return NOTIFY_DONE;
5ec8c83e 3209 }
dca55da0
JP		 3210
3211 return NOTIFY_OK;
3212}
3213
3214static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num)
3215{
3216 struct mlx5_roce *roce = &dev->port[port_num].roce;
3217
3218 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event;
3219 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb);
3220 mlx5_core_uplink_netdev_event_replay(dev->mdev);
3221}
3222
3223static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num)
3224{
3225 struct mlx5_roce *roce = &dev->port[port_num].roce;
3226
3227 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb);
3228 mlx5_netdev_notifier_unregister(roce);
5ec8c83e 3229}
45842fc6 3230
e3f1ed1f 3231static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3232{
e53505a8 3233 int err;
bfd745f8 3234
c446d9da
MB		 3235 if (!dev->is_rep && dev->profile != &raw_eth_profile) {
3236 err = mlx5_nic_vport_enable_roce(dev->mdev);
3237 if (err)
3238 return err;
3239 }
45842fc6 3240
45f95acd 3241 err = mlx5_eth_lag_init(dev);
45842fc6 3242 if (err)
9ef9c640 3243 goto err_disable_roce;
45842fc6
MZ		 3244
3245 return 0;
3246
9ef9c640 3247err_disable_roce:
c446d9da
MB		 3248 if (!dev->is_rep && dev->profile != &raw_eth_profile)
3249 mlx5_nic_vport_disable_roce(dev->mdev);
45842fc6
MZ		 3250
3251 return err;
3252}
3253
45f95acd 3254static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
45842fc6 3255{
45f95acd 3256 mlx5_eth_lag_cleanup(dev);
c446d9da
MB		 3257 if (!dev->is_rep && dev->profile != &raw_eth_profile)
3258 mlx5_nic_vport_disable_roce(dev->mdev);
45842fc6
MZ		 3259}
3260
1fb7f897 3261static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num,
f6a8a19b
DD		 3262 enum rdma_netdev_t type,
3263 struct rdma_netdev_alloc_params *params)
693dfd5a
ES		 3264{
3265 if (type != RDMA_NETDEV_IPOIB)
f6a8a19b 3266 return -EOPNOTSUPP;
693dfd5a 3267
f6a8a19b 3268 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
693dfd5a
ES		 3269}
3270
fe248c3a
MG		 3271static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3272 size_t count, loff_t *pos)
3273{
3274 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3275 char lbuf[20];
3276 int len;
3277
3278 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3279 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3280}
3281
3282static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3283 size_t count, loff_t *pos)
3284{
3285 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3286 u32 timeout;
3287 u32 var;
3288
3289 if (kstrtouint_from_user(buf, count, 0, &var))
3290 return -EFAULT;
3291
3292 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3293 1000);
3294 if (timeout != var)
3295 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3296 timeout);
3297
3298 delay_drop->timeout = timeout;
3299
3300 return count;
3301}
3302
3303static const struct file_operations fops_delay_drop_timeout = {
3304 .owner = THIS_MODULE,
3305 .open = simple_open,
3306 .write = delay_drop_timeout_write,
3307 .read = delay_drop_timeout_read,
3308};
3309
32f69e4b
DJ		 3310static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
3311 struct mlx5_ib_multiport_info *mpi)
3312{
1fb7f897 3313 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
32f69e4b
DJ		 3314 struct mlx5_ib_port *port = &ibdev->port[port_num];
3315 int comps;
3316 int err;
3317 int i;
3318
9dc4cfff
LR		 3319 lockdep_assert_held(&mlx5_ib_multiport_mutex);
3320
0d293714
PH		 3321 mlx5_core_mp_event_replay(ibdev->mdev,
3322 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED,
3323 NULL);
3324 mlx5_core_mp_event_replay(mpi->mdev,
3325 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED,
3326 NULL);
3327
a9e546e7
PP		 3328 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
3329
32f69e4b
DJ		 3330 spin_lock(&port->mp.mpi_lock);
3331 if (!mpi->ibdev) {
3332 spin_unlock(&port->mp.mpi_lock);
3333 return;
3334 }
df097a27 3335
32f69e4b
DJ		 3336 mpi->ibdev = NULL;
3337
3338 spin_unlock(&port->mp.mpi_lock);
23eaf3b5
LR		 3339 if (mpi->mdev_events.notifier_call)
3340 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
3341 mpi->mdev_events.notifier_call = NULL;
dca55da0 3342 mlx5_mdev_netdev_untrack(ibdev, port_num);
32f69e4b
DJ		 3343 spin_lock(&port->mp.mpi_lock);
3344
3345 comps = mpi->mdev_refcnt;
3346 if (comps) {
3347 mpi->unaffiliate = true;
3348 init_completion(&mpi->unref_comp);
3349 spin_unlock(&port->mp.mpi_lock);
3350
3351 for (i = 0; i < comps; i++)
3352 wait_for_completion(&mpi->unref_comp);
3353
3354 spin_lock(&port->mp.mpi_lock);
3355 mpi->unaffiliate = false;
3356 }
3357
3358 port->mp.mpi = NULL;
3359
32f69e4b
DJ		 3360 spin_unlock(&port->mp.mpi_lock);
3361
3362 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
3363
1fb7f897 3364 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1);
32f69e4b
DJ		 3365 /* Log an error, still needed to cleanup the pointers and add
3366 * it back to the list.
3367 */
3368 if (err)
3369 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
3370 port_num + 1);
3371
95579e78 3372 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 3373}
3374
32f69e4b
DJ		 3375static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
3376 struct mlx5_ib_multiport_info *mpi)
3377{
1fb7f897 3378 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
0d293714 3379 u64 key;
32f69e4b
DJ		 3380 int err;
3381
9dc4cfff
LR		 3382 lockdep_assert_held(&mlx5_ib_multiport_mutex);
3383
32f69e4b
DJ		 3384 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
3385 if (ibdev->port[port_num].mp.mpi) {
1fb7f897 3386 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n",
2577188e 3387 port_num + 1);
32f69e4b
DJ		 3388 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3389 return false;
3390 }
3391
3392 ibdev->port[port_num].mp.mpi = mpi;
3393 mpi->ibdev = ibdev;
df097a27 3394 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 3395 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3396
3397 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
3398 if (err)
3399 goto unbind;
3400
dca55da0 3401 mlx5_mdev_netdev_track(ibdev, port_num);
32f69e4b 3402
df097a27
SM		 3403 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
3404 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
3405
73eb8f03 3406 mlx5_ib_init_cong_debugfs(ibdev, port_num);
a9e546e7 3407
02e7d139 3408 key = mpi->mdev->priv.adev_idx;
0d293714
PH		 3409 mlx5_core_mp_event_replay(mpi->mdev,
3410 MLX5_DRIVER_EVENT_AFFILIATION_DONE,
3411 &key);
3412 mlx5_core_mp_event_replay(ibdev->mdev,
3413 MLX5_DRIVER_EVENT_AFFILIATION_DONE,
3414 &key);
3415
32f69e4b
DJ		 3416 return true;
3417
3418unbind:
3419 mlx5_ib_unbind_slave_port(ibdev, mpi);
3420 return false;
3421}
3422
3423static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
3424{
1fb7f897 3425 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
32f69e4b
DJ		 3426 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3427 port_num + 1);
3428 struct mlx5_ib_multiport_info *mpi;
3429 int err;
1fb7f897 3430 u32 i;
32f69e4b
DJ		 3431
3432 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3433 return 0;
3434
3435 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
3436 &dev->sys_image_guid);
3437 if (err)
3438 return err;
3439
3440 err = mlx5_nic_vport_enable_roce(dev->mdev);
3441 if (err)
3442 return err;
3443
3444 mutex_lock(&mlx5_ib_multiport_mutex);
3445 for (i = 0; i < dev->num_ports; i++) {
3446 bool bound = false;
3447
3448 /* build a stub multiport info struct for the native port. */
3449 if (i == port_num) {
3450 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
3451 if (!mpi) {
3452 mutex_unlock(&mlx5_ib_multiport_mutex);
3453 mlx5_nic_vport_disable_roce(dev->mdev);
3454 return -ENOMEM;
3455 }
3456
3457 mpi->is_master = true;
3458 mpi->mdev = dev->mdev;
3459 mpi->sys_image_guid = dev->sys_image_guid;
3460 dev->port[i].mp.mpi = mpi;
3461 mpi->ibdev = dev;
3462 mpi = NULL;
3463 continue;
3464 }
3465
3466 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
3467 list) {
3468 if (dev->sys_image_guid == mpi->sys_image_guid &&
3469 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
3470 bound = mlx5_ib_bind_slave_port(dev, mpi);
3471 }
3472
3473 if (bound) {
c42260f1
VP		 3474 dev_dbg(mpi->mdev->device,
3475 "removing port from unaffiliated list.\n");
32f69e4b
DJ		 3476 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
3477 list_del(&mpi->list);
3478 break;
3479 }
3480 }
7416790e 3481 if (!bound)
32f69e4b
DJ		 3482 mlx5_ib_dbg(dev, "no free port found for port %d\n",
3483 i + 1);
32f69e4b
DJ		 3484 }
3485
3486 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
3487 mutex_unlock(&mlx5_ib_multiport_mutex);
3488 return err;
3489}
3490
3491static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
3492{
1fb7f897 3493 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
32f69e4b
DJ		 3494 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3495 port_num + 1);
1fb7f897 3496 u32 i;
32f69e4b
DJ		 3497
3498 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3499 return;
3500
3501 mutex_lock(&mlx5_ib_multiport_mutex);
3502 for (i = 0; i < dev->num_ports; i++) {
3503 if (dev->port[i].mp.mpi) {
3504 /* Destroy the native port stub */
3505 if (i == port_num) {
3506 kfree(dev->port[i].mp.mpi);
3507 dev->port[i].mp.mpi = NULL;
3508 } else {
1fb7f897
MB		 3509 mlx5_ib_dbg(dev, "unbinding port_num: %u\n",
3510 i + 1);
7ce6095e
LR		 3511 list_add_tail(&dev->port[i].mp.mpi->list,
3512 &mlx5_ib_unaffiliated_port_list);
4a754d76
LR		 3513 mlx5_ib_unbind_slave_port(dev,
3514 dev->port[i].mp.mpi);
32f69e4b
DJ		 3515 }
3516 }
3517 }
3518
3519 mlx5_ib_dbg(dev, "removing from devlist\n");
3520 list_del(&dev->ib_dev_list);
3521 mutex_unlock(&mlx5_ib_multiport_mutex);
3522
3523 mlx5_nic_vport_disable_roce(dev->mdev);
3524}
3525
342ee59d
YH		 3526static int mmap_obj_cleanup(struct ib_uobject *uobject,
3527 enum rdma_remove_reason why,
3528 struct uverbs_attr_bundle *attrs)
7be76bef
YH		 3529{
3530 struct mlx5_user_mmap_entry *obj = uobject->object;
3531
3532 rdma_user_mmap_entry_remove(&obj->rdma_entry);
3533 return 0;
3534}
3535
342ee59d
YH		 3536static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
3537 struct mlx5_user_mmap_entry *entry,
3538 size_t length)
3539{
3540 return rdma_user_mmap_entry_insert_range(
3541 &c->ibucontext, &entry->rdma_entry, length,
3542 (MLX5_IB_MMAP_OFFSET_START << 16),
3543 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
3544}
3545
7be76bef
YH		 3546static struct mlx5_user_mmap_entry *
3547alloc_var_entry(struct mlx5_ib_ucontext *c)
3548{
3549 struct mlx5_user_mmap_entry *entry;
3550 struct mlx5_var_table *var_table;
3551 u32 page_idx;
3552 int err;
3553
3554 var_table = &to_mdev(c->ibucontext.device)->var_table;
3555 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3556 if (!entry)
3557 return ERR_PTR(-ENOMEM);
3558
3559 mutex_lock(&var_table->bitmap_lock);
3560 page_idx = find_first_zero_bit(var_table->bitmap,
3561 var_table->num_var_hw_entries);
3562 if (page_idx >= var_table->num_var_hw_entries) {
3563 err = -ENOSPC;
3564 mutex_unlock(&var_table->bitmap_lock);
3565 goto end;
3566 }
3567
3568 set_bit(page_idx, var_table->bitmap);
3569 mutex_unlock(&var_table->bitmap_lock);
3570
3571 entry->address = var_table->hw_start_addr +
3572 (page_idx * var_table->stride_size);
3573 entry->page_idx = page_idx;
3574 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
3575
342ee59d
YH		 3576 err = mlx5_rdma_user_mmap_entry_insert(c, entry,
3577 var_table->stride_size);
7be76bef
YH		 3578 if (err)
3579 goto err_insert;
3580
3581 return entry;
3582
3583err_insert:
3584 mutex_lock(&var_table->bitmap_lock);
3585 clear_bit(page_idx, var_table->bitmap);
3586 mutex_unlock(&var_table->bitmap_lock);
3587end:
3588 kfree(entry);
3589 return ERR_PTR(err);
3590}
3591
3592static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
3593 struct uverbs_attr_bundle *attrs)
3594{
3595 struct ib_uobject *uobj = uverbs_attr_get_uobject(
3596 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3597 struct mlx5_ib_ucontext *c;
3598 struct mlx5_user_mmap_entry *entry;
3599 u64 mmap_offset;
3600 u32 length;
3601 int err;
3602
3603 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3604 if (IS_ERR(c))
3605 return PTR_ERR(c);
3606
3607 entry = alloc_var_entry(c);
3608 if (IS_ERR(entry))
3609 return PTR_ERR(entry);
3610
3611 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3612 length = entry->rdma_entry.npages * PAGE_SIZE;
3613 uobj->object = entry;
0ac8903c 3614 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
7be76bef
YH		 3615
3616 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3617 &mmap_offset, sizeof(mmap_offset));
3618 if (err)
0ac8903c 3619 return err;
7be76bef
YH		 3620
3621 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3622 &entry->page_idx, sizeof(entry->page_idx));
3623 if (err)
0ac8903c 3624 return err;
7be76bef
YH		 3625
3626 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3627 &length, sizeof(length));
7be76bef
YH		 3628 return err;
3629}
3630
3631DECLARE_UVERBS_NAMED_METHOD(
3632 MLX5_IB_METHOD_VAR_OBJ_ALLOC,
3633 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
3634 MLX5_IB_OBJECT_VAR,
3635 UVERBS_ACCESS_NEW,
3636 UA_MANDATORY),
3637 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3638 UVERBS_ATTR_TYPE(u32),
3639 UA_MANDATORY),
3640 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3641 UVERBS_ATTR_TYPE(u32),
3642 UA_MANDATORY),
3643 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3644 UVERBS_ATTR_TYPE(u64),
3645 UA_MANDATORY));
3646
3647DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3648 MLX5_IB_METHOD_VAR_OBJ_DESTROY,
3649 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
3650 MLX5_IB_OBJECT_VAR,
3651 UVERBS_ACCESS_DESTROY,
3652 UA_MANDATORY));
3653
3654DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
342ee59d 3655 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
7be76bef
YH		 3656 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
3657 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
3658
3659static bool var_is_supported(struct ib_device *device)
3660{
3661 struct mlx5_ib_dev *dev = to_mdev(device);
3662
3663 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3664 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
3665}
3666
342ee59d
YH		 3667static struct mlx5_user_mmap_entry *
3668alloc_uar_entry(struct mlx5_ib_ucontext *c,
3669 enum mlx5_ib_uapi_uar_alloc_type alloc_type)
3670{
3671 struct mlx5_user_mmap_entry *entry;
3672 struct mlx5_ib_dev *dev;
3673 u32 uar_index;
3674 int err;
3675
3676 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3677 if (!entry)
3678 return ERR_PTR(-ENOMEM);
3679
3680 dev = to_mdev(c->ibucontext.device);
d2c8a155 3681 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid);
342ee59d
YH		 3682 if (err)
3683 goto end;
3684
3685 entry->page_idx = uar_index;
3686 entry->address = uar_index2paddress(dev, uar_index);
3687 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3688 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
3689 else
3690 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
3691
3692 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
3693 if (err)
3694 goto err_insert;
3695
3696 return entry;
3697
3698err_insert:
d2c8a155 3699 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid);
342ee59d
YH		 3700end:
3701 kfree(entry);
3702 return ERR_PTR(err);
3703}
3704
3705static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
3706 struct uverbs_attr_bundle *attrs)
3707{
3708 struct ib_uobject *uobj = uverbs_attr_get_uobject(
3709 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3710 enum mlx5_ib_uapi_uar_alloc_type alloc_type;
3711 struct mlx5_ib_ucontext *c;
3712 struct mlx5_user_mmap_entry *entry;
3713 u64 mmap_offset;
3714 u32 length;
3715 int err;
3716
3717 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3718 if (IS_ERR(c))
3719 return PTR_ERR(c);
3720
3721 err = uverbs_get_const(&alloc_type, attrs,
3722 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
3723 if (err)
3724 return err;
3725
3726 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
3727 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
3728 return -EOPNOTSUPP;
3729
d98995b4 3730 if (!mlx5_wc_support_get(to_mdev(c->ibucontext.device)->mdev) &&
342ee59d
YH		 3731 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3732 return -EOPNOTSUPP;
3733
3734 entry = alloc_uar_entry(c, alloc_type);
3735 if (IS_ERR(entry))
3736 return PTR_ERR(entry);
3737
3738 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3739 length = entry->rdma_entry.npages * PAGE_SIZE;
3740 uobj->object = entry;
0ac8903c 3741 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
342ee59d
YH		 3742
3743 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3744 &mmap_offset, sizeof(mmap_offset));
3745 if (err)
0ac8903c 3746 return err;
342ee59d
YH		 3747
3748 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3749 &entry->page_idx, sizeof(entry->page_idx));
3750 if (err)
0ac8903c 3751 return err;
342ee59d
YH		 3752
3753 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3754 &length, sizeof(length));
342ee59d
YH		 3755 return err;
3756}
3757
3758DECLARE_UVERBS_NAMED_METHOD(
3759 MLX5_IB_METHOD_UAR_OBJ_ALLOC,
3760 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
3761 MLX5_IB_OBJECT_UAR,
3762 UVERBS_ACCESS_NEW,
3763 UA_MANDATORY),
3764 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
3765 enum mlx5_ib_uapi_uar_alloc_type,
3766 UA_MANDATORY),
3767 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3768 UVERBS_ATTR_TYPE(u32),
3769 UA_MANDATORY),
3770 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3771 UVERBS_ATTR_TYPE(u32),
3772 UA_MANDATORY),
3773 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3774 UVERBS_ATTR_TYPE(u64),
3775 UA_MANDATORY));
3776
3777DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3778 MLX5_IB_METHOD_UAR_OBJ_DESTROY,
3779 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
3780 MLX5_IB_OBJECT_UAR,
3781 UVERBS_ACCESS_DESTROY,
3782 UA_MANDATORY));
3783
3784DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
3785 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3786 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
3787 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
3788
0fb556b2
YH		 3789ADD_UVERBS_ATTRIBUTES_SIMPLE(
3790 mlx5_ib_query_context,
3791 UVERBS_OBJECT_DEVICE,
3792 UVERBS_METHOD_QUERY_CONTEXT,
3793 UVERBS_ATTR_PTR_OUT(
3794 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
3795 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp,
3796 dump_fill_mkey),
3797 UA_MANDATORY));
3798
0cbf432d 3799static const struct uapi_definition mlx5_ib_defs[] = {
36e235c8 3800 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
0cbf432d 3801 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
30f2fe40 3802 UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
05f71ef9 3803 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs),
831df883 3804 UAPI_DEF_CHAIN(mlx5_ib_dm_defs),
589b844f 3805 UAPI_DEF_CHAIN(mlx5_ib_create_cq_defs),
8c84660b 3806
0fb556b2 3807 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context),
7be76bef
YH		 3808 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
3809 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
342ee59d 3810 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
0cbf432d
JG		 3811 {}
3812};
8c84660b 3813
fb652d32 3814static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 3815{
32f69e4b 3816 mlx5_ib_cleanup_multiport_master(dev);
806b101b 3817 WARN_ON(!xa_empty(&dev->odp_mkeys));
ab40530a 3818 mutex_destroy(&dev->cap_mask_mutex);
50211ec9 3819 WARN_ON(!xa_empty(&dev->sig_mrs));
4056b12e 3820 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
758ce14a 3821 mlx5r_macsec_dealloc_gids(dev);
16c1975f
MB		 3822}
3823
fb652d32 3824static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 3825{
3826 struct mlx5_core_dev *mdev = dev->mdev;
758ce14a 3827 int err, i;
e126ba97 3828
13179652
PP		 3829 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3830 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3831 dev->ib_dev.phys_port_cnt = dev->num_ports;
3832 dev->ib_dev.dev.parent = mdev->device;
3833 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES;
3834
32f69e4b
DJ		 3835 for (i = 0; i < dev->num_ports; i++) {
3836 spin_lock_init(&dev->port[i].mp.mpi_lock);
95579e78 3837 rwlock_init(&dev->port[i].roce.netdev_lock);
d3b5cc1c
MB		 3838 dev->port[i].roce.dev = dev;
3839 dev->port[i].roce.native_port_num = i + 1;
3840 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 3841 }
3842
594cac11
OHT		 3843 err = mlx5r_cmd_query_special_mkeys(dev);
3844 if (err)
3845 return err;
3846
58dbd642 3847 err = mlx5r_macsec_init_gids_and_devlist(dev);
e126ba97 3848 if (err)
da796ccb 3849 return err;
e126ba97 3850
758ce14a
PH		 3851 err = mlx5_ib_init_multiport_master(dev);
3852 if (err)
3853 goto err;
3854
a989ea01
MB		 3855 err = set_has_smi_cap(dev);
3856 if (err)
2cb091f6 3857 goto err_mp;
e126ba97 3858
2019d70e
PP		 3859 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len);
3860 if (err)
3861 goto err_mp;
3862
1b5daf11
MD		 3863 if (mlx5_use_mad_ifc(dev))
3864 get_ext_port_caps(dev);
e126ba97 3865
674dd4e2 3866 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev);
e126ba97 3867
3cc297db
MB		 3868 mutex_init(&dev->cap_mask_mutex);
3869 INIT_LIST_HEAD(&dev->qp_list);
3870 spin_lock_init(&dev->reset_flow_resource_lock);
806b101b 3871 xa_init(&dev->odp_mkeys);
50211ec9 3872 xa_init(&dev->sig_mrs);
f743ff3b 3873 atomic_set(&dev->mkey_var, 0);
3cc297db 3874
3b113a1e
AL		 3875 spin_lock_init(&dev->dm.lock);
3876 dev->dm.dev = mdev;
16c1975f 3877 return 0;
32f69e4b
DJ		 3878err_mp:
3879 mlx5_ib_cleanup_multiport_master(dev);
81497c14
YH		 3880err:
3881 mlx5r_macsec_dealloc_gids(dev);
d286ac1d 3882 return err;
16c1975f
MB		 3883}
3884
026a4259
MZ		 3885static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent,
3886 enum rdma_nl_dev_type type,
3887 const char *name);
3888static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev);
3889
96458233 3890static const struct ib_device_ops mlx5_ib_dev_ops = {
7a154142 3891 .owner = THIS_MODULE,
b9560a41 3892 .driver_id = RDMA_DRIVER_MLX5,
72c6ec18 3893 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
b9560a41 3894
96458233 3895 .add_gid = mlx5_ib_add_gid,
026a4259 3896 .add_sub_dev = mlx5_ib_add_sub_dev,
96458233 3897 .alloc_mr = mlx5_ib_alloc_mr,
6c984472 3898 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
96458233
KH		 3899 .alloc_pd = mlx5_ib_alloc_pd,
3900 .alloc_ucontext = mlx5_ib_alloc_ucontext,
3901 .attach_mcast = mlx5_ib_mcg_attach,
3902 .check_mr_status = mlx5_ib_check_mr_status,
3903 .create_ah = mlx5_ib_create_ah,
96458233 3904 .create_cq = mlx5_ib_create_cq,
96458233
KH		 3905 .create_qp = mlx5_ib_create_qp,
3906 .create_srq = mlx5_ib_create_srq,
676a80ad 3907 .create_user_ah = mlx5_ib_create_ah,
96458233
KH		 3908 .dealloc_pd = mlx5_ib_dealloc_pd,
3909 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
3910 .del_gid = mlx5_ib_del_gid,
026a4259 3911 .del_sub_dev = mlx5_ib_del_sub_dev,
96458233
KH		 3912 .dereg_mr = mlx5_ib_dereg_mr,
3913 .destroy_ah = mlx5_ib_destroy_ah,
96458233 3914 .destroy_cq = mlx5_ib_destroy_cq,
96458233
KH		 3915 .destroy_qp = mlx5_ib_destroy_qp,
3916 .destroy_srq = mlx5_ib_destroy_srq,
3917 .detach_mcast = mlx5_ib_mcg_detach,
3918 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
3919 .drain_rq = mlx5_ib_drain_rq,
3920 .drain_sq = mlx5_ib_drain_sq,
915e4af5 3921 .device_group = &mlx5_attr_group,
96458233
KH		 3922 .get_dev_fw_str = get_dev_fw_str,
3923 .get_dma_mr = mlx5_ib_get_dma_mr,
3924 .get_link_layer = mlx5_ib_port_link_layer,
3925 .map_mr_sg = mlx5_ib_map_mr_sg,
6c984472 3926 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
96458233 3927 .mmap = mlx5_ib_mmap,
dc2316eb 3928 .mmap_free = mlx5_ib_mmap_free,
96458233
KH		 3929 .modify_cq = mlx5_ib_modify_cq,
3930 .modify_device = mlx5_ib_modify_device,
3931 .modify_port = mlx5_ib_modify_port,
3932 .modify_qp = mlx5_ib_modify_qp,
3933 .modify_srq = mlx5_ib_modify_srq,
3934 .poll_cq = mlx5_ib_poll_cq,
029e88fd
LR		 3935 .post_recv = mlx5_ib_post_recv_nodrain,
3936 .post_send = mlx5_ib_post_send_nodrain,
96458233
KH		 3937 .post_srq_recv = mlx5_ib_post_srq_recv,
3938 .process_mad = mlx5_ib_process_mad,
3939 .query_ah = mlx5_ib_query_ah,
3940 .query_device = mlx5_ib_query_device,
3941 .query_gid = mlx5_ib_query_gid,
3942 .query_pkey = mlx5_ib_query_pkey,
3943 .query_qp = mlx5_ib_query_qp,
3944 .query_srq = mlx5_ib_query_srq,
0fb556b2 3945 .query_ucontext = mlx5_ib_query_ucontext,
96458233 3946 .reg_user_mr = mlx5_ib_reg_user_mr,
90da7dc8 3947 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf,
96458233
KH		 3948 .req_notify_cq = mlx5_ib_arm_cq,
3949 .rereg_user_mr = mlx5_ib_rereg_user_mr,
3950 .resize_cq = mlx5_ib_resize_cq,
d3456914
LR		 3951
3952 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
3b023e1b 3953 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs),
e39afe3d 3954 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
21a428a0 3955 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
514aee66 3956 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp),
68e326de 3957 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
a2a074ef 3958 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
96458233
KH		 3959};
3960
96458233
KH		 3961static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
3962 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
3963};
3964
3965static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
3966 .get_vf_config = mlx5_ib_get_vf_config,
9c0015ef 3967 .get_vf_guid = mlx5_ib_get_vf_guid,
96458233
KH		 3968 .get_vf_stats = mlx5_ib_get_vf_stats,
3969 .set_vf_guid = mlx5_ib_set_vf_guid,
3970 .set_vf_link_state = mlx5_ib_set_vf_link_state,
3971};
3972
3973static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
3974 .alloc_mw = mlx5_ib_alloc_mw,
3975 .dealloc_mw = mlx5_ib_dealloc_mw,
d18bb3e1
LR		 3976
3977 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw),
96458233
KH		 3978};
3979
3980static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
3981 .alloc_xrcd = mlx5_ib_alloc_xrcd,
3982 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
28ad5f65
LR		 3983
3984 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd),
96458233
KH		 3985};
3986
f164be8c
YH		 3987static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
3988{
3989 struct mlx5_core_dev *mdev = dev->mdev;
3990 struct mlx5_var_table *var_table = &dev->var_table;
3991 u8 log_doorbell_bar_size;
3992 u8 log_doorbell_stride;
3993 u64 bar_size;
3994
3995 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3996 log_doorbell_bar_size);
3997 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3998 log_doorbell_stride);
3999 var_table->hw_start_addr = dev->mdev->bar_addr +
4000 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
4001 doorbell_bar_offset);
4002 bar_size = (1ULL << log_doorbell_bar_size) * 4096;
4003 var_table->stride_size = 1ULL << log_doorbell_stride;
91b74bf5
AL		 4004 var_table->num_var_hw_entries = div_u64(bar_size,
4005 var_table->stride_size);
f164be8c
YH		 4006 mutex_init(&var_table->bitmap_lock);
4007 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
4008 GFP_KERNEL);
4009 return (var_table->bitmap) ? 0 : -ENOMEM;
4010}
4011
4012static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
4013{
4014 bitmap_free(dev->var_table.bitmap);
4015}
4016
fb652d32 4017static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 4018{
4019 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 4020 int err;
4021
f6a8a19b
DD		 4022 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
4023 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
96458233
KH		 4024 ib_set_device_ops(&dev->ib_dev,
4025 &mlx5_ib_dev_ipoib_enhanced_ops);
8e959601 4026
96458233
KH		 4027 if (mlx5_core_is_pf(mdev))
4028 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
7c2344c3 4029
6e8484c5
MG		 4030 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4031
44ce37bc 4032 if (MLX5_CAP_GEN(mdev, imaicl))
96458233 4033 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
d2370e0a 4034
44ce37bc 4035 if (MLX5_CAP_GEN(mdev, xrc))
96458233 4036 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
e126ba97 4037
25c13324
AL		 4038 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
4039 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
4040 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
96458233 4041 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
24da0016 4042
96458233 4043 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
81e30880 4044
36e235c8
JG		 4045 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
4046 dev->ib_dev.driver_def = mlx5_ib_defs;
81e30880 4047
e126ba97
EC		 4048 err = init_node_data(dev);
4049 if (err)
16c1975f 4050 return err;
e126ba97 4051
c8b89924 4052 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 4053 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
4054 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
a560f1d9 4055 mutex_init(&dev->lb.mutex);
c8b89924 4056
f164be8c
YH		 4057 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
4058 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
4059 err = mlx5_ib_init_var_table(dev);
4060 if (err)
4061 return err;
4062 }
4063
96e2fd73
LR		 4064 dev->ib_dev.use_cq_dim = true;
4065
16c1975f
MB		 4066 return 0;
4067}
4068
96458233
KH		 4069static const struct ib_device_ops mlx5_ib_dev_port_ops = {
4070 .get_port_immutable = mlx5_port_immutable,
4071 .query_port = mlx5_ib_query_port,
4072};
4073
8e6efa3a
MB		 4074static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
4075{
96458233 4076 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
8e6efa3a
MB		 4077 return 0;
4078}
4079
96458233
KH		 4080static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
4081 .get_port_immutable = mlx5_port_rep_immutable,
4082 .query_port = mlx5_ib_rep_query_port,
d6fd59e1 4083 .query_pkey = mlx5_ib_rep_query_pkey,
96458233
KH		 4084};
4085
b5a498ba 4086static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a 4087{
96458233 4088 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
8e6efa3a
MB		 4089 return 0;
4090}
4091
96458233
KH		 4092static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
4093 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
4094 .create_wq = mlx5_ib_create_wq,
4095 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
4096 .destroy_wq = mlx5_ib_destroy_wq,
4097 .get_netdev = mlx5_ib_get_netdev,
4098 .modify_wq = mlx5_ib_modify_wq,
c0a6b5ec
LR		 4099
4100 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table,
4101 ib_rwq_ind_tbl),
96458233
KH		 4102};
4103
1e2b5a90 4104static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 4105{
4106 struct mlx5_core_dev *mdev = dev->mdev;
4107 enum rdma_link_layer ll;
4108 int port_type_cap;
1fb7f897 4109 u32 port_num = 0;
16c1975f
MB		 4110 int err;
4111
4112 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4113 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4114
fc24fc5e 4115 if (ll == IB_LINK_LAYER_ETHERNET) {
1e2b5a90
LR		 4116 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
4117
4118 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4119
4120 /* Register only for native ports */
dca55da0 4121 mlx5_mdev_netdev_track(dev, port_num);
7fd8aefb 4122
e3f1ed1f 4123 err = mlx5_enable_eth(dev);
fc24fc5e 4124 if (err)
8e6efa3a 4125 goto cleanup;
fc24fc5e
AS		 4126 }
4127
16c1975f 4128 return 0;
8e6efa3a 4129cleanup:
dca55da0 4130 mlx5_mdev_netdev_untrack(dev, port_num);
8e6efa3a 4131 return err;
16c1975f 4132}
e126ba97 4133
1e2b5a90 4134static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 4135{
4136 struct mlx5_core_dev *mdev = dev->mdev;
4137 enum rdma_link_layer ll;
4138 int port_type_cap;
1fb7f897 4139 u32 port_num;
e126ba97 4140
16c1975f
MB		 4141 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4142 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4143
4144 if (ll == IB_LINK_LAYER_ETHERNET) {
c446d9da 4145 mlx5_disable_eth(dev);
5e1e7612 4146
1e2b5a90 4147 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
dca55da0 4148 mlx5_mdev_netdev_untrack(dev, port_num);
5e1e7612 4149 }
16c1975f
MB		 4150}
4151
4152static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4153{
73eb8f03
GKH		 4154 mlx5_ib_init_cong_debugfs(dev,
4155 mlx5_core_native_port_num(dev->mdev) - 1);
4156 return 0;
16c1975f
MB		 4157}
4158
4159static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4160{
a9e546e7
PP		 4161 mlx5_ib_cleanup_cong_debugfs(dev,
4162 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 4163}
4164
4165static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4166{
5fe9dec0 4167 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 4168 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 4169}
4170
4171static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4172{
4173 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4174}
4175
fb652d32 4176static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 4177{
4178 int err;
5fe9dec0
EC		 4179
4180 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4181 if (err)
16c1975f 4182 return err;
5fe9dec0
EC		 4183
4184 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4185 if (err)
1c3aa6bd 4186 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
5fe9dec0 4187
16c1975f
MB		 4188 return err;
4189}
0837e86a 4190
fb652d32 4191static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 4192{
4193 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4194 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4195}
e126ba97 4196
fb652d32 4197static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f 4198{
e349f858
JG		 4199 const char *name;
4200
af48f954 4201 if (dev->sub_dev_name) {
026a4259 4202 name = dev->sub_dev_name;
af48f954
MZ		 4203 ib_mark_name_assigned_by_user(&dev->ib_dev);
4204 } else if (!mlx5_lag_is_active(dev->mdev))
e349f858
JG		 4205 name = "mlx5_%d";
4206 else
4207 name = "mlx5_bond_%d";
e0477b34 4208 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
16c1975f
MB		 4209}
4210
fb652d32 4211static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 4212{
85f9e38a 4213 mlx5_mkey_cache_cleanup(dev);
04876c12 4214 mlx5r_umr_resource_cleanup(dev);
63842011 4215 mlx5r_umr_cleanup(dev);
16c1975f
MB		 4216}
4217
fb652d32 4218static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 4219{
42cea83f 4220 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 4221}
4222
fb652d32 4223static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 4224{
1e2b5a90
LR		 4225 int ret;
4226
63842011 4227 ret = mlx5r_umr_init(dev);
04876c12
AL		 4228 if (ret)
4229 return ret;
1e2b5a90 4230
01137808 4231 ret = mlx5_mkey_cache_init(dev);
2ef422f0 4232 if (ret)
1e2b5a90 4233 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
1e2b5a90 4234 return ret;
16c1975f
MB		 4235}
4236
4237static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4238{
1e2b5a90
LR		 4239 struct dentry *root;
4240
4241 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4242 return 0;
4243
4244 mutex_init(&dev->delay_drop.lock);
4245 dev->delay_drop.dev = dev;
4246 dev->delay_drop.activate = false;
4247 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4248 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4249 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4250 atomic_set(&dev->delay_drop.events_cnt, 0);
4251
4252 if (!mlx5_debugfs_root)
4253 return 0;
03404e8a 4254
66771a1c 4255 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev));
1e2b5a90 4256 dev->delay_drop.dir_debugfs = root;
03404e8a 4257
1e2b5a90
LR		 4258 debugfs_create_atomic_t("num_timeout_events", 0400, root,
4259 &dev->delay_drop.events_cnt);
4260 debugfs_create_atomic_t("num_rqs", 0400, root,
4261 &dev->delay_drop.rqs_cnt);
4262 debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
4263 &fops_delay_drop_timeout);
16c1975f
MB		 4264 return 0;
4265}
4266
4267static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4268{
1e2b5a90
LR		 4269 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4270 return;
4271
4272 cancel_work_sync(&dev->delay_drop.delay_drop_work);
4273 if (!dev->delay_drop.dir_debugfs)
4274 return;
4275
4276 debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
4277 dev->delay_drop.dir_debugfs = NULL;
16c1975f
MB		 4278}
4279
df097a27
SM		 4280static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
4281{
4282 dev->mdev_events.notifier_call = mlx5_ib_event;
4283 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
58dbd642
PH		 4284
4285 mlx5r_macsec_event_register(dev);
4286
df097a27
SM		 4287 return 0;
4288}
4289
4290static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
4291{
58dbd642 4292 mlx5r_macsec_event_unregister(dev);
df097a27
SM		 4293 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
4294}
4295
b5ca15ad
MB		 4296void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4297 const struct mlx5_ib_profile *profile,
4298 int stage)
16c1975f 4299{
4cca96a8
PP		 4300 dev->ib_active = false;
4301
16c1975f
MB		 4302 /* Number of stages to cleanup */
4303 while (stage) {
4304 stage--;
4305 if (profile->stage[stage].cleanup)
4306 profile->stage[stage].cleanup(dev);
4307 }
4a6dc855 4308
da796ccb 4309 kfree(dev->port);
4a6dc855 4310 ib_dealloc_device(&dev->ib_dev);
16c1975f 4311}
e126ba97 4312
93f82444
LR		 4313int __mlx5_ib_add(struct mlx5_ib_dev *dev,
4314 const struct mlx5_ib_profile *profile)
16c1975f 4315{
16c1975f
MB		 4316 int err;
4317 int i;
5fe9dec0 4318
8d93efb8
MB		 4319 dev->profile = profile;
4320
16c1975f
MB		 4321 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4322 if (profile->stage[i].init) {
4323 err = profile->stage[i].init(dev);
4324 if (err)
4325 goto err_out;
4326 }
4327 }
0837e86a 4328
16c1975f 4329 dev->ib_active = true;
93f82444 4330 return 0;
e126ba97 4331
16c1975f 4332err_out:
93f82444
LR		 4333 /* Clean up stages which were initialized */
4334 while (i) {
4335 i--;
4336 if (profile->stage[i].cleanup)
4337 profile->stage[i].cleanup(dev);
4338 }
4339 return -ENOMEM;
16c1975f 4340}
0837e86a 4341
16c1975f
MB		 4342static const struct mlx5_ib_profile pf_profile = {
4343 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4344 mlx5_ib_stage_init_init,
4345 mlx5_ib_stage_init_cleanup),
f7c4ffda
LR		 4346 STAGE_CREATE(MLX5_IB_STAGE_FS,
4347 mlx5_ib_fs_init,
4348 mlx5_ib_fs_cleanup),
16c1975f
MB		 4349 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4350 mlx5_ib_stage_caps_init,
f164be8c 4351 mlx5_ib_stage_caps_cleanup),
8e6efa3a
MB		 4352 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4353 mlx5_ib_stage_non_default_cb,
4354 NULL),
16c1975f 4355 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
1e2b5a90
LR		 4356 mlx5_ib_roce_init,
4357 mlx5_ib_roce_cleanup),
333fbaa0
LR		 4358 STAGE_CREATE(MLX5_IB_STAGE_QP,
4359 mlx5_init_qp_table,
4360 mlx5_cleanup_qp_table),
f3da6577
LR		 4361 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4362 mlx5_init_srq_table,
4363 mlx5_cleanup_srq_table),
16c1975f 4364 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
1e2b5a90
LR		 4365 mlx5_ib_dev_res_init,
4366 mlx5_ib_dev_res_cleanup),
df097a27
SM		 4367 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4368 mlx5_ib_stage_dev_notifier_init,
4369 mlx5_ib_stage_dev_notifier_cleanup),
16c1975f 4370 STAGE_CREATE(MLX5_IB_STAGE_ODP,
1e2b5a90
LR		 4371 mlx5_ib_odp_init_one,
4372 mlx5_ib_odp_cleanup_one),
16c1975f 4373 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
64825827
LR		 4374 mlx5_ib_counters_init,
4375 mlx5_ib_counters_cleanup),
16c1975f
MB		 4376 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4377 mlx5_ib_stage_cong_debugfs_init,
4378 mlx5_ib_stage_cong_debugfs_cleanup),
4379 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4380 mlx5_ib_stage_uar_init,
4381 mlx5_ib_stage_uar_cleanup),
4382 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4383 mlx5_ib_stage_bfrag_init,
4384 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 4385 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4386 NULL,
4387 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
81773ce5 4388 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
d8b7515e
LR		 4389 mlx5_ib_devx_init,
4390 mlx5_ib_devx_cleanup),
16c1975f
MB		 4391 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4392 mlx5_ib_stage_ib_reg_init,
4393 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 4394 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4395 mlx5_ib_stage_post_ib_reg_umr_init,
4396 NULL),
16c1975f
MB		 4397 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4398 mlx5_ib_stage_delay_drop_init,
4399 mlx5_ib_stage_delay_drop_cleanup),
b572ebe6
LR		 4400 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4401 mlx5_ib_restrack_init,
4402 NULL),
16c1975f 4403};
e126ba97 4404
b5a498ba 4405const struct mlx5_ib_profile raw_eth_profile = {
b5ca15ad
MB		 4406 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4407 mlx5_ib_stage_init_init,
4408 mlx5_ib_stage_init_cleanup),
f7c4ffda
LR		 4409 STAGE_CREATE(MLX5_IB_STAGE_FS,
4410 mlx5_ib_fs_init,
4411 mlx5_ib_fs_cleanup),
b5ca15ad
MB		 4412 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4413 mlx5_ib_stage_caps_init,
f164be8c 4414 mlx5_ib_stage_caps_cleanup),
b5ca15ad 4415 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
b5a498ba 4416 mlx5_ib_stage_raw_eth_non_default_cb,
b5ca15ad
MB		 4417 NULL),
4418 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
1e2b5a90
LR		 4419 mlx5_ib_roce_init,
4420 mlx5_ib_roce_cleanup),
333fbaa0
LR		 4421 STAGE_CREATE(MLX5_IB_STAGE_QP,
4422 mlx5_init_qp_table,
4423 mlx5_cleanup_qp_table),
f3da6577
LR		 4424 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4425 mlx5_init_srq_table,
4426 mlx5_cleanup_srq_table),
b5ca15ad 4427 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
1e2b5a90
LR		 4428 mlx5_ib_dev_res_init,
4429 mlx5_ib_dev_res_cleanup),
df097a27
SM		 4430 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4431 mlx5_ib_stage_dev_notifier_init,
4432 mlx5_ib_stage_dev_notifier_cleanup),
b5ca15ad 4433 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
64825827
LR		 4434 mlx5_ib_counters_init,
4435 mlx5_ib_counters_cleanup),
79db784e
PP		 4436 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4437 mlx5_ib_stage_cong_debugfs_init,
4438 mlx5_ib_stage_cong_debugfs_cleanup),
b5ca15ad
MB		 4439 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4440 mlx5_ib_stage_uar_init,
4441 mlx5_ib_stage_uar_cleanup),
4442 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4443 mlx5_ib_stage_bfrag_init,
4444 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 4445 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4446 NULL,
4447 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
7f575103 4448 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
d8b7515e
LR		 4449 mlx5_ib_devx_init,
4450 mlx5_ib_devx_cleanup),
b5ca15ad
MB		 4451 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4452 mlx5_ib_stage_ib_reg_init,
4453 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 4454 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4455 mlx5_ib_stage_post_ib_reg_umr_init,
4456 NULL),
ee4d269e
MS		 4457 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4458 mlx5_ib_stage_delay_drop_init,
4459 mlx5_ib_stage_delay_drop_cleanup),
b572ebe6
LR		 4460 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4461 mlx5_ib_restrack_init,
4462 NULL),
b5ca15ad
MB		 4463};
4464
026a4259
MZ		 4465static const struct mlx5_ib_profile plane_profile = {
4466 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4467 mlx5_ib_stage_init_init,
4468 mlx5_ib_stage_init_cleanup),
4469 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4470 mlx5_ib_stage_caps_init,
4471 mlx5_ib_stage_caps_cleanup),
4472 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4473 mlx5_ib_stage_non_default_cb,
4474 NULL),
4475 STAGE_CREATE(MLX5_IB_STAGE_QP,
4476 mlx5_init_qp_table,
4477 mlx5_cleanup_qp_table),
4478 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4479 mlx5_init_srq_table,
4480 mlx5_cleanup_srq_table),
4481 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4482 mlx5_ib_dev_res_init,
4483 mlx5_ib_dev_res_cleanup),
4484 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4485 mlx5_ib_stage_bfrag_init,
4486 mlx5_ib_stage_bfrag_cleanup),
4487 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4488 mlx5_ib_stage_ib_reg_init,
4489 mlx5_ib_stage_ib_reg_cleanup),
4490};
4491
4492static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent,
4493 enum rdma_nl_dev_type type,
4494 const char *name)
4495{
4496 struct mlx5_ib_dev *mparent = to_mdev(parent), *mplane;
4497 enum rdma_link_layer ll;
4498 int ret;
4499
4500 if (mparent->smi_dev)
4501 return ERR_PTR(-EEXIST);
4502
4503 ll = mlx5_port_type_cap_to_rdma_ll(MLX5_CAP_GEN(mparent->mdev,
4504 port_type));
4505 if (type != RDMA_DEVICE_TYPE_SMI || !mparent->num_plane ||
4506 ll != IB_LINK_LAYER_INFINIBAND ||
4507 !MLX5_CAP_GEN_2(mparent->mdev, multiplane_qp_ud))
4508 return ERR_PTR(-EOPNOTSUPP);
4509
4510 mplane = ib_alloc_device(mlx5_ib_dev, ib_dev);
4511 if (!mplane)
4512 return ERR_PTR(-ENOMEM);
4513
4514 mplane->port = kcalloc(mparent->num_plane * mparent->num_ports,
4515 sizeof(*mplane->port), GFP_KERNEL);
4516 if (!mplane->port) {
4517 ret = -ENOMEM;
4518 goto fail_kcalloc;
4519 }
4520
4521 mplane->ib_dev.type = type;
4522 mplane->mdev = mparent->mdev;
4523 mplane->num_ports = mparent->num_plane;
4524 mplane->sub_dev_name = name;
4525
4526 ret = __mlx5_ib_add(mplane, &plane_profile);
4527 if (ret)
4528 goto fail_ib_add;
4529
4530 mparent->smi_dev = mplane;
4531 return &mplane->ib_dev;
4532
4533fail_ib_add:
4534 kfree(mplane->port);
4535fail_kcalloc:
4536 ib_dealloc_device(&mplane->ib_dev);
4537 return ERR_PTR(ret);
4538}
4539
4540static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev)
4541{
4542 struct mlx5_ib_dev *mdev = to_mdev(sub_dev);
4543
4544 to_mdev(sub_dev->parent)->smi_dev = NULL;
4545 __mlx5_ib_remove(mdev, mdev->profile, MLX5_IB_STAGE_MAX);
4546}
4547
93f82444
LR		 4548static int mlx5r_mp_probe(struct auxiliary_device *adev,
4549 const struct auxiliary_device_id *id)
32f69e4b 4550{
93f82444
LR		 4551 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4552 struct mlx5_core_dev *mdev = idev->mdev;
32f69e4b
DJ		 4553 struct mlx5_ib_multiport_info *mpi;
4554 struct mlx5_ib_dev *dev;
4555 bool bound = false;
4556 int err;
4557
4558 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4559 if (!mpi)
93f82444 4560 return -ENOMEM;
32f69e4b
DJ		 4561
4562 mpi->mdev = mdev;
32f69e4b
DJ		 4563 err = mlx5_query_nic_vport_system_image_guid(mdev,
4564 &mpi->sys_image_guid);
4565 if (err) {
4566 kfree(mpi);
93f82444 4567 return err;
32f69e4b
DJ		 4568 }
4569
4570 mutex_lock(&mlx5_ib_multiport_mutex);
4571 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
4572 if (dev->sys_image_guid == mpi->sys_image_guid)
4573 bound = mlx5_ib_bind_slave_port(dev, mpi);
4574
4575 if (bound) {
4576 rdma_roce_rescan_device(&dev->ib_dev);
97f30d32 4577 mpi->ibdev->ib_active = true;
32f69e4b
DJ		 4578 break;
4579 }
4580 }
4581
4582 if (!bound) {
4583 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
c42260f1
VP		 4584 dev_dbg(mdev->device,
4585 "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 4586 }
4587 mutex_unlock(&mlx5_ib_multiport_mutex);
4588
27963d3d 4589 auxiliary_set_drvdata(adev, mpi);
93f82444
LR		 4590 return 0;
4591}
4592
4593static void mlx5r_mp_remove(struct auxiliary_device *adev)
4594{
4595 struct mlx5_ib_multiport_info *mpi;
4596
27963d3d 4597 mpi = auxiliary_get_drvdata(adev);
93f82444
LR		 4598 mutex_lock(&mlx5_ib_multiport_mutex);
4599 if (mpi->ibdev)
4600 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
da78fe5f
MG		 4601 else
4602 list_del(&mpi->list);
93f82444
LR		 4603 mutex_unlock(&mlx5_ib_multiport_mutex);
4604 kfree(mpi);
32f69e4b
DJ		 4605}
4606
93f82444
LR		 4607static int mlx5r_probe(struct auxiliary_device *adev,
4608 const struct auxiliary_device_id *id)
16c1975f 4609{
93f82444
LR		 4610 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4611 struct mlx5_core_dev *mdev = idev->mdev;
94de879c 4612 const struct mlx5_ib_profile *profile;
93f82444 4613 int port_type_cap, num_ports, ret;
32f69e4b 4614 enum rdma_link_layer ll;
b5ca15ad 4615 struct mlx5_ib_dev *dev;
f0666f1f 4616
32f69e4b
DJ		 4617 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4618 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4619
da796ccb
MB		 4620 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4621 MLX5_CAP_GEN(mdev, num_vhca_ports));
459cc69f 4622 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
b5ca15ad 4623 if (!dev)
93f82444 4624 return -ENOMEM;
2a5db20f
MZ		 4625
4626 if (ll == IB_LINK_LAYER_INFINIBAND) {
4627 ret = mlx5_ib_get_plane_num(mdev, &dev->num_plane);
4628 if (ret)
4629 goto fail;
4630 }
4631
da796ccb
MB		 4632 dev->port = kcalloc(num_ports, sizeof(*dev->port),
4633 GFP_KERNEL);
4634 if (!dev->port) {
2a5db20f
MZ		 4635 ret = -ENOMEM;
4636 goto fail;
da796ccb 4637 }
b5ca15ad
MB		 4638
4639 dev->mdev = mdev;
da796ccb 4640 dev->num_ports = num_ports;
b5ca15ad 4641
9ca05b0f 4642 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev))
94de879c
MG		 4643 profile = &raw_eth_profile;
4644 else
4645 profile = &pf_profile;
4646
93f82444 4647 ret = __mlx5_ib_add(dev, profile);
2a5db20f
MZ		 4648 if (ret)
4649 goto fail_ib_add;
93f82444 4650
27963d3d 4651 auxiliary_set_drvdata(adev, dev);
93f82444 4652 return 0;
2a5db20f
MZ		 4653
4654fail_ib_add:
4655 kfree(dev->port);
4656fail:
4657 ib_dealloc_device(&dev->ib_dev);
4658 return ret;
e126ba97
EC		 4659}
4660
93f82444 4661static void mlx5r_remove(struct auxiliary_device *adev)
e126ba97 4662{
32f69e4b
DJ		 4663 struct mlx5_ib_dev *dev;
4664
27963d3d 4665 dev = auxiliary_get_drvdata(adev);
f0666f1f 4666 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 4667}
4668
93f82444
LR		 4669static const struct auxiliary_device_id mlx5r_mp_id_table[] = {
4670 { .name = MLX5_ADEV_NAME ".multiport", },
4671 {},
4672};
4673
4674static const struct auxiliary_device_id mlx5r_id_table[] = {
4675 { .name = MLX5_ADEV_NAME ".rdma", },
4676 {},
4677};
4678
4679MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table);
4680MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table);
4681
4682static struct auxiliary_driver mlx5r_mp_driver = {
4683 .name = "multiport",
4684 .probe = mlx5r_mp_probe,
4685 .remove = mlx5r_mp_remove,
4686 .id_table = mlx5r_mp_id_table,
4687};
4688
4689static struct auxiliary_driver mlx5r_driver = {
4690 .name = "rdma",
4691 .probe = mlx5r_probe,
4692 .remove = mlx5r_remove,
4693 .id_table = mlx5r_id_table,
e126ba97
EC		 4694};
4695
4696static int __init mlx5_ib_init(void)
4697{
93f82444 4698 int ret;
6aec21f6 4699
8010d74b 4700 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL);
c44ef998
IL		 4701 if (!xlt_emergency_page)
4702 return -ENOMEM;
4703
d69a24e0 4704 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998 4705 if (!mlx5_ib_event_wq) {
8010d74b 4706 free_page((unsigned long)xlt_emergency_page);
d69a24e0 4707 return -ENOMEM;
c44ef998 4708 }
d69a24e0 4709
312b8f79
MZ		 4710 ret = mlx5_ib_qp_event_init();
4711 if (ret)
4712 goto qp_event_err;
4713
81713d37 4714 mlx5_ib_odp_init();
93f82444
LR		 4715 ret = mlx5r_rep_init();
4716 if (ret)
4717 goto rep_err;
4718 ret = auxiliary_driver_register(&mlx5r_mp_driver);
4719 if (ret)
4720 goto mp_err;
4721 ret = auxiliary_driver_register(&mlx5r_driver);
4722 if (ret)
4723 goto drv_err;
4724 return 0;
9603b61d 4725
93f82444
LR		 4726drv_err:
4727 auxiliary_driver_unregister(&mlx5r_mp_driver);
4728mp_err:
4729 mlx5r_rep_cleanup();
4730rep_err:
312b8f79
MZ		 4731 mlx5_ib_qp_event_cleanup();
4732qp_event_err:
93f82444
LR		 4733 destroy_workqueue(mlx5_ib_event_wq);
4734 free_page((unsigned long)xlt_emergency_page);
4735 return ret;
e126ba97
EC		 4736}
4737
4738static void __exit mlx5_ib_cleanup(void)
4739{
93f82444
LR		 4740 auxiliary_driver_unregister(&mlx5r_driver);
4741 auxiliary_driver_unregister(&mlx5r_mp_driver);
4742 mlx5r_rep_cleanup();
4743
312b8f79 4744 mlx5_ib_qp_event_cleanup();
d69a24e0 4745 destroy_workqueue(mlx5_ib_event_wq);
8010d74b 4746 free_page((unsigned long)xlt_emergency_page);
e126ba97
EC		 4747}
4748
4749module_init(mlx5_ib_init);
4750module_exit(mlx5_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)