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IB/mlx5: Set network_hdr_type upon RoCE responder completion
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/sched.h>
42#include <rdma/ib_user_verbs.h>
3f89a643 43#include <rdma/ib_addr.h>
1b5daf11 44#include <linux/mlx5/vport.h>
e126ba97
EC		 45#include <rdma/ib_smi.h>
46#include <rdma/ib_umem.h>
47#include "user.h"
48#include "mlx5_ib.h"
49
50#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 51#define DRIVER_VERSION "2.2-1"
52#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 53
54MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
55MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
56MODULE_LICENSE("Dual BSD/GPL");
57MODULE_VERSION(DRIVER_VERSION);
58
9603b61d
JM		 59static int deprecated_prof_sel = 2;
60module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
61MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 62
63static char mlx5_version[] =
64 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
65 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
66
1b5daf11 67static enum rdma_link_layer
ebd61f68 68mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 69{
ebd61f68 70 switch (port_type_cap) {
1b5daf11
MD		 71 case MLX5_CAP_PORT_TYPE_IB:
72 return IB_LINK_LAYER_INFINIBAND;
73 case MLX5_CAP_PORT_TYPE_ETH:
74 return IB_LINK_LAYER_ETHERNET;
75 default:
76 return IB_LINK_LAYER_UNSPECIFIED;
77 }
78}
79
ebd61f68
AS		 80static enum rdma_link_layer
81mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
82{
83 struct mlx5_ib_dev *dev = to_mdev(device);
84 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
85
86 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
87}
88
fc24fc5e
AS		 89static int mlx5_netdev_event(struct notifier_block *this,
90 unsigned long event, void *ptr)
91{
92 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
93 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
94 roce.nb);
95
96 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
97 return NOTIFY_DONE;
98
99 write_lock(&ibdev->roce.netdev_lock);
100 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
101 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
102 write_unlock(&ibdev->roce.netdev_lock);
103
104 return NOTIFY_DONE;
105}
106
107static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
108 u8 port_num)
109{
110 struct mlx5_ib_dev *ibdev = to_mdev(device);
111 struct net_device *ndev;
112
113 /* Ensure ndev does not disappear before we invoke dev_hold()
114 */
115 read_lock(&ibdev->roce.netdev_lock);
116 ndev = ibdev->roce.netdev;
117 if (ndev)
118 dev_hold(ndev);
119 read_unlock(&ibdev->roce.netdev_lock);
120
121 return ndev;
122}
123
3f89a643
AS		 124static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
125 struct ib_port_attr *props)
126{
127 struct mlx5_ib_dev *dev = to_mdev(device);
128 struct net_device *ndev;
129 enum ib_mtu ndev_ib_mtu;
130
131 memset(props, 0, sizeof(*props));
132
133 props->port_cap_flags |= IB_PORT_CM_SUP;
134 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
135
136 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
137 roce_address_table_size);
138 props->max_mtu = IB_MTU_4096;
139 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
140 props->pkey_tbl_len = 1;
141 props->state = IB_PORT_DOWN;
142 props->phys_state = 3;
143
144 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev,
145 (u16 *)&props->qkey_viol_cntr);
146
147 ndev = mlx5_ib_get_netdev(device, port_num);
148 if (!ndev)
149 return 0;
150
151 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
152 props->state = IB_PORT_ACTIVE;
153 props->phys_state = 5;
154 }
155
156 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
157
158 dev_put(ndev);
159
160 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
161
162 props->active_width = IB_WIDTH_4X; /* TODO */
163 props->active_speed = IB_SPEED_QDR; /* TODO */
164
165 return 0;
166}
167
1b5daf11
MD		 168static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
169{
170 return !dev->mdev->issi;
171}
172
173enum {
174 MLX5_VPORT_ACCESS_METHOD_MAD,
175 MLX5_VPORT_ACCESS_METHOD_HCA,
176 MLX5_VPORT_ACCESS_METHOD_NIC,
177};
178
179static int mlx5_get_vport_access_method(struct ib_device *ibdev)
180{
181 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
182 return MLX5_VPORT_ACCESS_METHOD_MAD;
183
ebd61f68 184 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 185 IB_LINK_LAYER_ETHERNET)
186 return MLX5_VPORT_ACCESS_METHOD_NIC;
187
188 return MLX5_VPORT_ACCESS_METHOD_HCA;
189}
190
191static int mlx5_query_system_image_guid(struct ib_device *ibdev,
192 __be64 *sys_image_guid)
193{
194 struct mlx5_ib_dev *dev = to_mdev(ibdev);
195 struct mlx5_core_dev *mdev = dev->mdev;
196 u64 tmp;
197 int err;
198
199 switch (mlx5_get_vport_access_method(ibdev)) {
200 case MLX5_VPORT_ACCESS_METHOD_MAD:
201 return mlx5_query_mad_ifc_system_image_guid(ibdev,
202 sys_image_guid);
203
204 case MLX5_VPORT_ACCESS_METHOD_HCA:
205 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 206 break;
207
208 case MLX5_VPORT_ACCESS_METHOD_NIC:
209 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
210 break;
1b5daf11
MD		 211
212 default:
213 return -EINVAL;
214 }
3f89a643
AS		 215
216 if (!err)
217 *sys_image_guid = cpu_to_be64(tmp);
218
219 return err;
220
1b5daf11
MD		 221}
222
223static int mlx5_query_max_pkeys(struct ib_device *ibdev,
224 u16 *max_pkeys)
225{
226 struct mlx5_ib_dev *dev = to_mdev(ibdev);
227 struct mlx5_core_dev *mdev = dev->mdev;
228
229 switch (mlx5_get_vport_access_method(ibdev)) {
230 case MLX5_VPORT_ACCESS_METHOD_MAD:
231 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
232
233 case MLX5_VPORT_ACCESS_METHOD_HCA:
234 case MLX5_VPORT_ACCESS_METHOD_NIC:
235 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
236 pkey_table_size));
237 return 0;
238
239 default:
240 return -EINVAL;
241 }
242}
243
244static int mlx5_query_vendor_id(struct ib_device *ibdev,
245 u32 *vendor_id)
246{
247 struct mlx5_ib_dev *dev = to_mdev(ibdev);
248
249 switch (mlx5_get_vport_access_method(ibdev)) {
250 case MLX5_VPORT_ACCESS_METHOD_MAD:
251 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
252
253 case MLX5_VPORT_ACCESS_METHOD_HCA:
254 case MLX5_VPORT_ACCESS_METHOD_NIC:
255 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
256
257 default:
258 return -EINVAL;
259 }
260}
261
262static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
263 __be64 *node_guid)
264{
265 u64 tmp;
266 int err;
267
268 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
269 case MLX5_VPORT_ACCESS_METHOD_MAD:
270 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
271
272 case MLX5_VPORT_ACCESS_METHOD_HCA:
273 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 274 break;
275
276 case MLX5_VPORT_ACCESS_METHOD_NIC:
277 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
278 break;
1b5daf11
MD		 279
280 default:
281 return -EINVAL;
282 }
3f89a643
AS		 283
284 if (!err)
285 *node_guid = cpu_to_be64(tmp);
286
287 return err;
1b5daf11
MD		 288}
289
290struct mlx5_reg_node_desc {
291 u8 desc[64];
292};
293
294static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
295{
296 struct mlx5_reg_node_desc in;
297
298 if (mlx5_use_mad_ifc(dev))
299 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
300
301 memset(&in, 0, sizeof(in));
302
303 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
304 sizeof(struct mlx5_reg_node_desc),
305 MLX5_REG_NODE_DESC, 0, 0);
306}
307
e126ba97 308static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 309 struct ib_device_attr *props,
310 struct ib_udata *uhw)
e126ba97
EC		 311{
312 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 313 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 314 int err = -ENOMEM;
315 int max_rq_sg;
316 int max_sq_sg;
e0238a6a 317 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
e126ba97 318
2528e33e
MB		 319 if (uhw->inlen || uhw->outlen)
320 return -EINVAL;
321
1b5daf11
MD		 322 memset(props, 0, sizeof(*props));
323 err = mlx5_query_system_image_guid(ibdev,
324 &props->sys_image_guid);
325 if (err)
326 return err;
e126ba97 327
1b5daf11 328 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 329 if (err)
1b5daf11 330 return err;
e126ba97 331
1b5daf11
MD		 332 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
333 if (err)
334 return err;
e126ba97 335
9603b61d
JM		 336 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
337 (fw_rev_min(dev->mdev) << 16) |
338 fw_rev_sub(dev->mdev);
e126ba97
EC		 339 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
340 IB_DEVICE_PORT_ACTIVE_EVENT |
341 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 342 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 343
344 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 345 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 346 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 347 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 348 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 349 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 350 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97
EC		 351 props->device_cap_flags |= IB_DEVICE_XRC;
352 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 353 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 354 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
355 /* At this stage no support for signature handover */
356 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
357 IB_PROT_T10DIF_TYPE_2 |
358 IB_PROT_T10DIF_TYPE_3;
359 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
360 IB_GUARD_T10DIF_CSUM;
361 }
938fe83c 362 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 363 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 364
1b5daf11
MD		 365 props->vendor_part_id = mdev->pdev->device;
366 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 367
368 props->max_mr_size = ~0ull;
e0238a6a 369 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 370 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
371 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
372 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
373 sizeof(struct mlx5_wqe_data_seg);
374 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
375 sizeof(struct mlx5_wqe_ctrl_seg)) /
376 sizeof(struct mlx5_wqe_data_seg);
e126ba97 377 props->max_sge = min(max_rq_sg, max_sq_sg);
18ebd407 378 props->max_sge_rd = props->max_sge;
938fe83c
SM		 379 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
380 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_eq_sz)) - 1;
381 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
382 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
383 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
384 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
385 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
386 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
387 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 388 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97
EC		 389 props->max_srq_sge = max_rq_sg - 1;
390 props->max_fast_reg_page_list_len = (unsigned int)-1;
81bea28f
EC		 391 props->atomic_cap = IB_ATOMIC_NONE;
392 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 393 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
394 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 395 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
396 props->max_mcast_grp;
397 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
398
8cdd312c 399#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 400 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 401 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
402 props->odp_caps = dev->odp_caps;
403#endif
404
1b5daf11 405 return 0;
e126ba97
EC		 406}
407
1b5daf11
MD		 408enum mlx5_ib_width {
409 MLX5_IB_WIDTH_1X = 1 << 0,
410 MLX5_IB_WIDTH_2X = 1 << 1,
411 MLX5_IB_WIDTH_4X = 1 << 2,
412 MLX5_IB_WIDTH_8X = 1 << 3,
413 MLX5_IB_WIDTH_12X = 1 << 4
414};
415
416static int translate_active_width(struct ib_device *ibdev, u8 active_width,
417 u8 *ib_width)
e126ba97
EC		 418{
419 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 420 int err = 0;
421
422 if (active_width & MLX5_IB_WIDTH_1X) {
423 *ib_width = IB_WIDTH_1X;
424 } else if (active_width & MLX5_IB_WIDTH_2X) {
425 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
426 (int)active_width);
427 err = -EINVAL;
428 } else if (active_width & MLX5_IB_WIDTH_4X) {
429 *ib_width = IB_WIDTH_4X;
430 } else if (active_width & MLX5_IB_WIDTH_8X) {
431 *ib_width = IB_WIDTH_8X;
432 } else if (active_width & MLX5_IB_WIDTH_12X) {
433 *ib_width = IB_WIDTH_12X;
434 } else {
435 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
436 (int)active_width);
437 err = -EINVAL;
e126ba97
EC		 438 }
439
1b5daf11
MD		 440 return err;
441}
e126ba97 442
1b5daf11
MD		 443static int mlx5_mtu_to_ib_mtu(int mtu)
444{
445 switch (mtu) {
446 case 256: return 1;
447 case 512: return 2;
448 case 1024: return 3;
449 case 2048: return 4;
450 case 4096: return 5;
451 default:
452 pr_warn("invalid mtu\n");
453 return -1;
e126ba97 454 }
1b5daf11 455}
e126ba97 456
1b5daf11
MD		 457enum ib_max_vl_num {
458 __IB_MAX_VL_0 = 1,
459 __IB_MAX_VL_0_1 = 2,
460 __IB_MAX_VL_0_3 = 3,
461 __IB_MAX_VL_0_7 = 4,
462 __IB_MAX_VL_0_14 = 5,
463};
e126ba97 464
1b5daf11
MD		 465enum mlx5_vl_hw_cap {
466 MLX5_VL_HW_0 = 1,
467 MLX5_VL_HW_0_1 = 2,
468 MLX5_VL_HW_0_2 = 3,
469 MLX5_VL_HW_0_3 = 4,
470 MLX5_VL_HW_0_4 = 5,
471 MLX5_VL_HW_0_5 = 6,
472 MLX5_VL_HW_0_6 = 7,
473 MLX5_VL_HW_0_7 = 8,
474 MLX5_VL_HW_0_14 = 15
475};
e126ba97 476
1b5daf11
MD		 477static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
478 u8 *max_vl_num)
479{
480 switch (vl_hw_cap) {
481 case MLX5_VL_HW_0:
482 *max_vl_num = __IB_MAX_VL_0;
483 break;
484 case MLX5_VL_HW_0_1:
485 *max_vl_num = __IB_MAX_VL_0_1;
486 break;
487 case MLX5_VL_HW_0_3:
488 *max_vl_num = __IB_MAX_VL_0_3;
489 break;
490 case MLX5_VL_HW_0_7:
491 *max_vl_num = __IB_MAX_VL_0_7;
492 break;
493 case MLX5_VL_HW_0_14:
494 *max_vl_num = __IB_MAX_VL_0_14;
495 break;
e126ba97 496
1b5daf11
MD		 497 default:
498 return -EINVAL;
e126ba97 499 }
e126ba97 500
1b5daf11 501 return 0;
e126ba97
EC		 502}
503
1b5daf11
MD		 504static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
505 struct ib_port_attr *props)
e126ba97 506{
1b5daf11
MD		 507 struct mlx5_ib_dev *dev = to_mdev(ibdev);
508 struct mlx5_core_dev *mdev = dev->mdev;
509 struct mlx5_hca_vport_context *rep;
510 int max_mtu;
511 int oper_mtu;
512 int err;
513 u8 ib_link_width_oper;
514 u8 vl_hw_cap;
e126ba97 515
1b5daf11
MD		 516 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
517 if (!rep) {
518 err = -ENOMEM;
e126ba97 519 goto out;
e126ba97 520 }
e126ba97 521
1b5daf11 522 memset(props, 0, sizeof(*props));
e126ba97 523
1b5daf11 524 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 525 if (err)
526 goto out;
527
1b5daf11
MD		 528 props->lid = rep->lid;
529 props->lmc = rep->lmc;
530 props->sm_lid = rep->sm_lid;
531 props->sm_sl = rep->sm_sl;
532 props->state = rep->vport_state;
533 props->phys_state = rep->port_physical_state;
534 props->port_cap_flags = rep->cap_mask1;
535 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
536 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
537 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
538 props->bad_pkey_cntr = rep->pkey_violation_counter;
539 props->qkey_viol_cntr = rep->qkey_violation_counter;
540 props->subnet_timeout = rep->subnet_timeout;
541 props->init_type_reply = rep->init_type_reply;
e126ba97 542
1b5daf11
MD		 543 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
544 if (err)
e126ba97 545 goto out;
e126ba97 546
1b5daf11
MD		 547 err = translate_active_width(ibdev, ib_link_width_oper,
548 &props->active_width);
549 if (err)
550 goto out;
551 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
552 port);
e126ba97
EC		 553 if (err)
554 goto out;
555
facc9699 556 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 557
1b5daf11 558 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 559
facc9699 560 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 561
1b5daf11 562 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 563
1b5daf11
MD		 564 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
565 if (err)
566 goto out;
e126ba97 567
1b5daf11
MD		 568 err = translate_max_vl_num(ibdev, vl_hw_cap,
569 &props->max_vl_num);
e126ba97 570out:
1b5daf11 571 kfree(rep);
e126ba97
EC		 572 return err;
573}
574
1b5daf11
MD		 575int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
576 struct ib_port_attr *props)
e126ba97 577{
1b5daf11
MD		 578 switch (mlx5_get_vport_access_method(ibdev)) {
579 case MLX5_VPORT_ACCESS_METHOD_MAD:
580 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 581
1b5daf11
MD		 582 case MLX5_VPORT_ACCESS_METHOD_HCA:
583 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 584
3f89a643
AS		 585 case MLX5_VPORT_ACCESS_METHOD_NIC:
586 return mlx5_query_port_roce(ibdev, port, props);
587
1b5daf11
MD		 588 default:
589 return -EINVAL;
590 }
591}
e126ba97 592
1b5daf11
MD		 593static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
594 union ib_gid *gid)
595{
596 struct mlx5_ib_dev *dev = to_mdev(ibdev);
597 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 598
1b5daf11
MD		 599 switch (mlx5_get_vport_access_method(ibdev)) {
600 case MLX5_VPORT_ACCESS_METHOD_MAD:
601 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 602
1b5daf11
MD		 603 case MLX5_VPORT_ACCESS_METHOD_HCA:
604 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
605
606 default:
607 return -EINVAL;
608 }
e126ba97 609
e126ba97
EC		 610}
611
1b5daf11
MD		 612static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
613 u16 *pkey)
614{
615 struct mlx5_ib_dev *dev = to_mdev(ibdev);
616 struct mlx5_core_dev *mdev = dev->mdev;
617
618 switch (mlx5_get_vport_access_method(ibdev)) {
619 case MLX5_VPORT_ACCESS_METHOD_MAD:
620 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
621
622 case MLX5_VPORT_ACCESS_METHOD_HCA:
623 case MLX5_VPORT_ACCESS_METHOD_NIC:
624 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
625 pkey);
626 default:
627 return -EINVAL;
628 }
629}
e126ba97
EC		 630
631static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
632 struct ib_device_modify *props)
633{
634 struct mlx5_ib_dev *dev = to_mdev(ibdev);
635 struct mlx5_reg_node_desc in;
636 struct mlx5_reg_node_desc out;
637 int err;
638
639 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
640 return -EOPNOTSUPP;
641
642 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
643 return 0;
644
645 /*
646 * If possible, pass node desc to FW, so it can generate
647 * a 144 trap. If cmd fails, just ignore.
648 */
649 memcpy(&in, props->node_desc, 64);
9603b61d 650 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 651 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
652 if (err)
653 return err;
654
655 memcpy(ibdev->node_desc, props->node_desc, 64);
656
657 return err;
658}
659
660static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
661 struct ib_port_modify *props)
662{
663 struct mlx5_ib_dev *dev = to_mdev(ibdev);
664 struct ib_port_attr attr;
665 u32 tmp;
666 int err;
667
668 mutex_lock(&dev->cap_mask_mutex);
669
670 err = mlx5_ib_query_port(ibdev, port, &attr);
671 if (err)
672 goto out;
673
674 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
675 ~props->clr_port_cap_mask;
676
9603b61d 677 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 678
679out:
680 mutex_unlock(&dev->cap_mask_mutex);
681 return err;
682}
683
684static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
685 struct ib_udata *udata)
686{
687 struct mlx5_ib_dev *dev = to_mdev(ibdev);
78c0f98c 688 struct mlx5_ib_alloc_ucontext_req_v2 req;
e126ba97
EC		 689 struct mlx5_ib_alloc_ucontext_resp resp;
690 struct mlx5_ib_ucontext *context;
691 struct mlx5_uuar_info *uuari;
692 struct mlx5_uar *uars;
c1be5232 693 int gross_uuars;
e126ba97 694 int num_uars;
78c0f98c 695 int ver;
e126ba97
EC		 696 int uuarn;
697 int err;
698 int i;
f241e749 699 size_t reqlen;
e126ba97
EC		 700
701 if (!dev->ib_active)
702 return ERR_PTR(-EAGAIN);
703
78c0f98c
EC		 704 memset(&req, 0, sizeof(req));
705 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
706 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
707 ver = 0;
708 else if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req_v2))
709 ver = 2;
710 else
711 return ERR_PTR(-EINVAL);
712
713 err = ib_copy_from_udata(&req, udata, reqlen);
e126ba97
EC		 714 if (err)
715 return ERR_PTR(err);
716
78c0f98c
EC		 717 if (req.flags || req.reserved)
718 return ERR_PTR(-EINVAL);
719
e126ba97
EC		 720 if (req.total_num_uuars > MLX5_MAX_UUARS)
721 return ERR_PTR(-ENOMEM);
722
723 if (req.total_num_uuars == 0)
724 return ERR_PTR(-EINVAL);
725
c1be5232
EC		 726 req.total_num_uuars = ALIGN(req.total_num_uuars,
727 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 728 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
729 return ERR_PTR(-EINVAL);
730
c1be5232
EC		 731 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
732 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c
SM		 733 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
734 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
735 resp.cache_line_size = L1_CACHE_BYTES;
736 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
737 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
738 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
739 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
740 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
e126ba97
EC		 741
742 context = kzalloc(sizeof(*context), GFP_KERNEL);
743 if (!context)
744 return ERR_PTR(-ENOMEM);
745
746 uuari = &context->uuari;
747 mutex_init(&uuari->lock);
748 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
749 if (!uars) {
750 err = -ENOMEM;
751 goto out_ctx;
752 }
753
c1be5232 754 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 755 sizeof(*uuari->bitmap),
756 GFP_KERNEL);
757 if (!uuari->bitmap) {
758 err = -ENOMEM;
759 goto out_uar_ctx;
760 }
761 /*
762 * clear all fast path uuars
763 */
c1be5232 764 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 765 uuarn = i & 3;
766 if (uuarn == 2 || uuarn == 3)
767 set_bit(i, uuari->bitmap);
768 }
769
c1be5232 770 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 771 if (!uuari->count) {
772 err = -ENOMEM;
773 goto out_bitmap;
774 }
775
776 for (i = 0; i < num_uars; i++) {
9603b61d 777 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 778 if (err)
779 goto out_count;
780 }
781
b4cfe447
HE		 782#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
783 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
784#endif
785
e126ba97
EC		 786 INIT_LIST_HEAD(&context->db_page_list);
787 mutex_init(&context->db_page_mutex);
788
789 resp.tot_uuars = req.total_num_uuars;
938fe83c 790 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
92b0ca7c
DC		 791 err = ib_copy_to_udata(udata, &resp,
792 sizeof(resp) - sizeof(resp.reserved));
e126ba97
EC		 793 if (err)
794 goto out_uars;
795
78c0f98c 796 uuari->ver = ver;
e126ba97
EC		 797 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
798 uuari->uars = uars;
799 uuari->num_uars = num_uars;
800 return &context->ibucontext;
801
802out_uars:
803 for (i--; i >= 0; i--)
9603b61d 804 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 805out_count:
806 kfree(uuari->count);
807
808out_bitmap:
809 kfree(uuari->bitmap);
810
811out_uar_ctx:
812 kfree(uars);
813
814out_ctx:
815 kfree(context);
816 return ERR_PTR(err);
817}
818
819static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
820{
821 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
822 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
823 struct mlx5_uuar_info *uuari = &context->uuari;
824 int i;
825
826 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 827 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 828 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
829 }
830
831 kfree(uuari->count);
832 kfree(uuari->bitmap);
833 kfree(uuari->uars);
834 kfree(context);
835
836 return 0;
837}
838
839static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
840{
9603b61d 841 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 842}
843
844static int get_command(unsigned long offset)
845{
846 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
847}
848
849static int get_arg(unsigned long offset)
850{
851 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
852}
853
854static int get_index(unsigned long offset)
855{
856 return get_arg(offset);
857}
858
859static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
860{
861 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
862 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
863 struct mlx5_uuar_info *uuari = &context->uuari;
864 unsigned long command;
865 unsigned long idx;
866 phys_addr_t pfn;
867
868 command = get_command(vma->vm_pgoff);
869 switch (command) {
870 case MLX5_IB_MMAP_REGULAR_PAGE:
871 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
872 return -EINVAL;
873
874 idx = get_index(vma->vm_pgoff);
1c3ce90d
EC		 875 if (idx >= uuari->num_uars)
876 return -EINVAL;
877
e126ba97
EC		 878 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
879 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
880 (unsigned long long)pfn);
881
e126ba97
EC		 882 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
883 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
884 PAGE_SIZE, vma->vm_page_prot))
885 return -EAGAIN;
886
887 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
888 vma->vm_start,
889 (unsigned long long)pfn << PAGE_SHIFT);
890 break;
891
892 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
893 return -ENOSYS;
894
895 default:
896 return -EINVAL;
897 }
898
899 return 0;
900}
901
e126ba97
EC		 902static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
903 struct ib_ucontext *context,
904 struct ib_udata *udata)
905{
906 struct mlx5_ib_alloc_pd_resp resp;
907 struct mlx5_ib_pd *pd;
908 int err;
909
910 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
911 if (!pd)
912 return ERR_PTR(-ENOMEM);
913
9603b61d 914 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 915 if (err) {
916 kfree(pd);
917 return ERR_PTR(err);
918 }
919
920 if (context) {
921 resp.pdn = pd->pdn;
922 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 923 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 924 kfree(pd);
925 return ERR_PTR(-EFAULT);
926 }
e126ba97
EC		 927 }
928
929 return &pd->ibpd;
930}
931
932static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
933{
934 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
935 struct mlx5_ib_pd *mpd = to_mpd(pd);
936
9603b61d 937 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 938 kfree(mpd);
939
940 return 0;
941}
942
943static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
944{
945 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
946 int err;
947
9603b61d 948 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 949 if (err)
950 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
951 ibqp->qp_num, gid->raw);
952
953 return err;
954}
955
956static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
957{
958 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
959 int err;
960
9603b61d 961 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 962 if (err)
963 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
964 ibqp->qp_num, gid->raw);
965
966 return err;
967}
968
969static int init_node_data(struct mlx5_ib_dev *dev)
970{
1b5daf11 971 int err;
e126ba97 972
1b5daf11 973 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 974 if (err)
1b5daf11 975 return err;
e126ba97 976
1b5daf11 977 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 978
1b5daf11 979 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 980}
981
982static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
983 char *buf)
984{
985 struct mlx5_ib_dev *dev =
986 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
987
9603b61d 988 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 989}
990
991static ssize_t show_reg_pages(struct device *device,
992 struct device_attribute *attr, char *buf)
993{
994 struct mlx5_ib_dev *dev =
995 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
996
6aec21f6 997 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 998}
999
1000static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1001 char *buf)
1002{
1003 struct mlx5_ib_dev *dev =
1004 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1005 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 1006}
1007
1008static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1009 char *buf)
1010{
1011 struct mlx5_ib_dev *dev =
1012 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d
JM		 1013 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
1014 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
e126ba97
EC		 1015}
1016
1017static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1018 char *buf)
1019{
1020 struct mlx5_ib_dev *dev =
1021 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1022 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 1023}
1024
1025static ssize_t show_board(struct device *device, struct device_attribute *attr,
1026 char *buf)
1027{
1028 struct mlx5_ib_dev *dev =
1029 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1030 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 1031 dev->mdev->board_id);
e126ba97
EC		 1032}
1033
1034static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
1035static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
1036static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1037static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
1038static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
1039static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
1040
1041static struct device_attribute *mlx5_class_attributes[] = {
1042 &dev_attr_hw_rev,
1043 &dev_attr_fw_ver,
1044 &dev_attr_hca_type,
1045 &dev_attr_board_id,
1046 &dev_attr_fw_pages,
1047 &dev_attr_reg_pages,
1048};
1049
9603b61d 1050static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 1051 enum mlx5_dev_event event, unsigned long param)
e126ba97 1052{
9603b61d 1053 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 1054 struct ib_event ibev;
9603b61d 1055
e126ba97
EC		 1056 u8 port = 0;
1057
1058 switch (event) {
1059 case MLX5_DEV_EVENT_SYS_ERROR:
1060 ibdev->ib_active = false;
1061 ibev.event = IB_EVENT_DEVICE_FATAL;
1062 break;
1063
1064 case MLX5_DEV_EVENT_PORT_UP:
1065 ibev.event = IB_EVENT_PORT_ACTIVE;
4d2f9bbb 1066 port = (u8)param;
e126ba97
EC		 1067 break;
1068
1069 case MLX5_DEV_EVENT_PORT_DOWN:
1070 ibev.event = IB_EVENT_PORT_ERR;
4d2f9bbb 1071 port = (u8)param;
e126ba97
EC		 1072 break;
1073
1074 case MLX5_DEV_EVENT_PORT_INITIALIZED:
1075 /* not used by ULPs */
1076 return;
1077
1078 case MLX5_DEV_EVENT_LID_CHANGE:
1079 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 1080 port = (u8)param;
e126ba97
EC		 1081 break;
1082
1083 case MLX5_DEV_EVENT_PKEY_CHANGE:
1084 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 1085 port = (u8)param;
e126ba97
EC		 1086 break;
1087
1088 case MLX5_DEV_EVENT_GUID_CHANGE:
1089 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 1090 port = (u8)param;
e126ba97
EC		 1091 break;
1092
1093 case MLX5_DEV_EVENT_CLIENT_REREG:
1094 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 1095 port = (u8)param;
e126ba97
EC		 1096 break;
1097 }
1098
1099 ibev.device = &ibdev->ib_dev;
1100 ibev.element.port_num = port;
1101
a0c84c32
EC		 1102 if (port < 1 || port > ibdev->num_ports) {
1103 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
1104 return;
1105 }
1106
e126ba97
EC		 1107 if (ibdev->ib_active)
1108 ib_dispatch_event(&ibev);
1109}
1110
1111static void get_ext_port_caps(struct mlx5_ib_dev *dev)
1112{
1113 int port;
1114
938fe83c 1115 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 1116 mlx5_query_ext_port_caps(dev, port);
1117}
1118
1119static int get_port_caps(struct mlx5_ib_dev *dev)
1120{
1121 struct ib_device_attr *dprops = NULL;
1122 struct ib_port_attr *pprops = NULL;
f614fc15 1123 int err = -ENOMEM;
e126ba97 1124 int port;
2528e33e 1125 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 1126
1127 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
1128 if (!pprops)
1129 goto out;
1130
1131 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
1132 if (!dprops)
1133 goto out;
1134
2528e33e 1135 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 1136 if (err) {
1137 mlx5_ib_warn(dev, "query_device failed %d\n", err);
1138 goto out;
1139 }
1140
938fe83c 1141 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 1142 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
1143 if (err) {
938fe83c
SM		 1144 mlx5_ib_warn(dev, "query_port %d failed %d\n",
1145 port, err);
e126ba97
EC		 1146 break;
1147 }
938fe83c
SM		 1148 dev->mdev->port_caps[port - 1].pkey_table_len =
1149 dprops->max_pkeys;
1150 dev->mdev->port_caps[port - 1].gid_table_len =
1151 pprops->gid_tbl_len;
e126ba97
EC		 1152 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
1153 dprops->max_pkeys, pprops->gid_tbl_len);
1154 }
1155
1156out:
1157 kfree(pprops);
1158 kfree(dprops);
1159
1160 return err;
1161}
1162
1163static void destroy_umrc_res(struct mlx5_ib_dev *dev)
1164{
1165 int err;
1166
1167 err = mlx5_mr_cache_cleanup(dev);
1168 if (err)
1169 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
1170
1171 mlx5_ib_destroy_qp(dev->umrc.qp);
1172 ib_destroy_cq(dev->umrc.cq);
e126ba97
EC		 1173 ib_dealloc_pd(dev->umrc.pd);
1174}
1175
1176enum {
1177 MAX_UMR_WR = 128,
1178};
1179
1180static int create_umr_res(struct mlx5_ib_dev *dev)
1181{
1182 struct ib_qp_init_attr *init_attr = NULL;
1183 struct ib_qp_attr *attr = NULL;
1184 struct ib_pd *pd;
1185 struct ib_cq *cq;
1186 struct ib_qp *qp;
8e37210b 1187 struct ib_cq_init_attr cq_attr = {};
e126ba97
EC		 1188 int ret;
1189
1190 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
1191 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
1192 if (!attr || !init_attr) {
1193 ret = -ENOMEM;
1194 goto error_0;
1195 }
1196
1197 pd = ib_alloc_pd(&dev->ib_dev);
1198 if (IS_ERR(pd)) {
1199 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
1200 ret = PTR_ERR(pd);
1201 goto error_0;
1202 }
1203
8e37210b
MB		 1204 cq_attr.cqe = 128;
1205 cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL,
1206 &cq_attr);
e126ba97
EC		 1207 if (IS_ERR(cq)) {
1208 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
1209 ret = PTR_ERR(cq);
1210 goto error_2;
1211 }
1212 ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
1213
1214 init_attr->send_cq = cq;
1215 init_attr->recv_cq = cq;
1216 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
1217 init_attr->cap.max_send_wr = MAX_UMR_WR;
1218 init_attr->cap.max_send_sge = 1;
1219 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
1220 init_attr->port_num = 1;
1221 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
1222 if (IS_ERR(qp)) {
1223 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
1224 ret = PTR_ERR(qp);
1225 goto error_3;
1226 }
1227 qp->device = &dev->ib_dev;
1228 qp->real_qp = qp;
1229 qp->uobject = NULL;
1230 qp->qp_type = MLX5_IB_QPT_REG_UMR;
1231
1232 attr->qp_state = IB_QPS_INIT;
1233 attr->port_num = 1;
1234 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
1235 IB_QP_PORT, NULL);
1236 if (ret) {
1237 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
1238 goto error_4;
1239 }
1240
1241 memset(attr, 0, sizeof(*attr));
1242 attr->qp_state = IB_QPS_RTR;
1243 attr->path_mtu = IB_MTU_256;
1244
1245 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1246 if (ret) {
1247 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
1248 goto error_4;
1249 }
1250
1251 memset(attr, 0, sizeof(*attr));
1252 attr->qp_state = IB_QPS_RTS;
1253 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1254 if (ret) {
1255 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
1256 goto error_4;
1257 }
1258
1259 dev->umrc.qp = qp;
1260 dev->umrc.cq = cq;
e126ba97
EC		 1261 dev->umrc.pd = pd;
1262
1263 sema_init(&dev->umrc.sem, MAX_UMR_WR);
1264 ret = mlx5_mr_cache_init(dev);
1265 if (ret) {
1266 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
1267 goto error_4;
1268 }
1269
1270 kfree(attr);
1271 kfree(init_attr);
1272
1273 return 0;
1274
1275error_4:
1276 mlx5_ib_destroy_qp(qp);
1277
1278error_3:
1279 ib_destroy_cq(cq);
1280
1281error_2:
e126ba97
EC		 1282 ib_dealloc_pd(pd);
1283
1284error_0:
1285 kfree(attr);
1286 kfree(init_attr);
1287 return ret;
1288}
1289
1290static int create_dev_resources(struct mlx5_ib_resources *devr)
1291{
1292 struct ib_srq_init_attr attr;
1293 struct mlx5_ib_dev *dev;
bcf4c1ea 1294 struct ib_cq_init_attr cq_attr = {.cqe = 1};
e126ba97
EC		 1295 int ret = 0;
1296
1297 dev = container_of(devr, struct mlx5_ib_dev, devr);
1298
1299 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
1300 if (IS_ERR(devr->p0)) {
1301 ret = PTR_ERR(devr->p0);
1302 goto error0;
1303 }
1304 devr->p0->device = &dev->ib_dev;
1305 devr->p0->uobject = NULL;
1306 atomic_set(&devr->p0->usecnt, 0);
1307
bcf4c1ea 1308 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 1309 if (IS_ERR(devr->c0)) {
1310 ret = PTR_ERR(devr->c0);
1311 goto error1;
1312 }
1313 devr->c0->device = &dev->ib_dev;
1314 devr->c0->uobject = NULL;
1315 devr->c0->comp_handler = NULL;
1316 devr->c0->event_handler = NULL;
1317 devr->c0->cq_context = NULL;
1318 atomic_set(&devr->c0->usecnt, 0);
1319
1320 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1321 if (IS_ERR(devr->x0)) {
1322 ret = PTR_ERR(devr->x0);
1323 goto error2;
1324 }
1325 devr->x0->device = &dev->ib_dev;
1326 devr->x0->inode = NULL;
1327 atomic_set(&devr->x0->usecnt, 0);
1328 mutex_init(&devr->x0->tgt_qp_mutex);
1329 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
1330
1331 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1332 if (IS_ERR(devr->x1)) {
1333 ret = PTR_ERR(devr->x1);
1334 goto error3;
1335 }
1336 devr->x1->device = &dev->ib_dev;
1337 devr->x1->inode = NULL;
1338 atomic_set(&devr->x1->usecnt, 0);
1339 mutex_init(&devr->x1->tgt_qp_mutex);
1340 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
1341
1342 memset(&attr, 0, sizeof(attr));
1343 attr.attr.max_sge = 1;
1344 attr.attr.max_wr = 1;
1345 attr.srq_type = IB_SRQT_XRC;
1346 attr.ext.xrc.cq = devr->c0;
1347 attr.ext.xrc.xrcd = devr->x0;
1348
1349 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
1350 if (IS_ERR(devr->s0)) {
1351 ret = PTR_ERR(devr->s0);
1352 goto error4;
1353 }
1354 devr->s0->device = &dev->ib_dev;
1355 devr->s0->pd = devr->p0;
1356 devr->s0->uobject = NULL;
1357 devr->s0->event_handler = NULL;
1358 devr->s0->srq_context = NULL;
1359 devr->s0->srq_type = IB_SRQT_XRC;
1360 devr->s0->ext.xrc.xrcd = devr->x0;
1361 devr->s0->ext.xrc.cq = devr->c0;
1362 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1363 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
1364 atomic_inc(&devr->p0->usecnt);
1365 atomic_set(&devr->s0->usecnt, 0);
1366
4aa17b28
HA		 1367 memset(&attr, 0, sizeof(attr));
1368 attr.attr.max_sge = 1;
1369 attr.attr.max_wr = 1;
1370 attr.srq_type = IB_SRQT_BASIC;
1371 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
1372 if (IS_ERR(devr->s1)) {
1373 ret = PTR_ERR(devr->s1);
1374 goto error5;
1375 }
1376 devr->s1->device = &dev->ib_dev;
1377 devr->s1->pd = devr->p0;
1378 devr->s1->uobject = NULL;
1379 devr->s1->event_handler = NULL;
1380 devr->s1->srq_context = NULL;
1381 devr->s1->srq_type = IB_SRQT_BASIC;
1382 devr->s1->ext.xrc.cq = devr->c0;
1383 atomic_inc(&devr->p0->usecnt);
1384 atomic_set(&devr->s0->usecnt, 0);
1385
e126ba97
EC		 1386 return 0;
1387
4aa17b28
HA		 1388error5:
1389 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 1390error4:
1391 mlx5_ib_dealloc_xrcd(devr->x1);
1392error3:
1393 mlx5_ib_dealloc_xrcd(devr->x0);
1394error2:
1395 mlx5_ib_destroy_cq(devr->c0);
1396error1:
1397 mlx5_ib_dealloc_pd(devr->p0);
1398error0:
1399 return ret;
1400}
1401
1402static void destroy_dev_resources(struct mlx5_ib_resources *devr)
1403{
4aa17b28 1404 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 1405 mlx5_ib_destroy_srq(devr->s0);
1406 mlx5_ib_dealloc_xrcd(devr->x0);
1407 mlx5_ib_dealloc_xrcd(devr->x1);
1408 mlx5_ib_destroy_cq(devr->c0);
1409 mlx5_ib_dealloc_pd(devr->p0);
1410}
1411
7738613e
IW		 1412static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
1413 struct ib_port_immutable *immutable)
1414{
1415 struct ib_port_attr attr;
1416 int err;
1417
1418 err = mlx5_ib_query_port(ibdev, port_num, &attr);
1419 if (err)
1420 return err;
1421
1422 immutable->pkey_tbl_len = attr.pkey_tbl_len;
1423 immutable->gid_tbl_len = attr.gid_tbl_len;
f9b22e35 1424 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
337877a4 1425 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 1426
1427 return 0;
1428}
1429
fc24fc5e
AS		 1430static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
1431{
1432 dev->roce.nb.notifier_call = mlx5_netdev_event;
1433 return register_netdevice_notifier(&dev->roce.nb);
1434}
1435
1436static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
1437{
1438 unregister_netdevice_notifier(&dev->roce.nb);
1439}
1440
9603b61d 1441static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 1442{
e126ba97 1443 struct mlx5_ib_dev *dev;
ebd61f68
AS		 1444 enum rdma_link_layer ll;
1445 int port_type_cap;
e126ba97
EC		 1446 int err;
1447 int i;
1448
ebd61f68
AS		 1449 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
1450 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
1451
647241ea 1452 /* don't create IB instance over Eth ports, no RoCE yet! */
ebd61f68 1453 if (ll == IB_LINK_LAYER_ETHERNET)
647241ea
MD		 1454 return NULL;
1455
e126ba97
EC		 1456 printk_once(KERN_INFO "%s", mlx5_version);
1457
1458 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
1459 if (!dev)
9603b61d 1460 return NULL;
e126ba97 1461
9603b61d 1462 dev->mdev = mdev;
e126ba97 1463
fc24fc5e 1464 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 1465 err = get_port_caps(dev);
1466 if (err)
9603b61d 1467 goto err_dealloc;
e126ba97 1468
1b5daf11
MD		 1469 if (mlx5_use_mad_ifc(dev))
1470 get_ext_port_caps(dev);
e126ba97 1471
e126ba97
EC		 1472 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
1473
1474 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
1475 dev->ib_dev.owner = THIS_MODULE;
1476 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 1477 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 1478 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 1479 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 1480 dev->ib_dev.num_comp_vectors =
1481 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 1482 dev->ib_dev.dma_device = &mdev->pdev->dev;
1483
1484 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
1485 dev->ib_dev.uverbs_cmd_mask =
1486 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
1487 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
1488 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
1489 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
1490 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
1491 (1ull << IB_USER_VERBS_CMD_REG_MR) |
1492 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
1493 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
1494 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
1495 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
1496 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
1497 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
1498 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
1499 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
1500 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
1501 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
1502 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
1503 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
1504 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
1505 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
1506 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
1507 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
1508 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a
HE		 1509 dev->ib_dev.uverbs_ex_cmd_mask =
1510 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE);
e126ba97
EC		 1511
1512 dev->ib_dev.query_device = mlx5_ib_query_device;
1513 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 1514 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 1515 if (ll == IB_LINK_LAYER_ETHERNET)
1516 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97
EC		 1517 dev->ib_dev.query_gid = mlx5_ib_query_gid;
1518 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
1519 dev->ib_dev.modify_device = mlx5_ib_modify_device;
1520 dev->ib_dev.modify_port = mlx5_ib_modify_port;
1521 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
1522 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
1523 dev->ib_dev.mmap = mlx5_ib_mmap;
1524 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
1525 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
1526 dev->ib_dev.create_ah = mlx5_ib_create_ah;
1527 dev->ib_dev.query_ah = mlx5_ib_query_ah;
1528 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
1529 dev->ib_dev.create_srq = mlx5_ib_create_srq;
1530 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
1531 dev->ib_dev.query_srq = mlx5_ib_query_srq;
1532 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
1533 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
1534 dev->ib_dev.create_qp = mlx5_ib_create_qp;
1535 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
1536 dev->ib_dev.query_qp = mlx5_ib_query_qp;
1537 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
1538 dev->ib_dev.post_send = mlx5_ib_post_send;
1539 dev->ib_dev.post_recv = mlx5_ib_post_recv;
1540 dev->ib_dev.create_cq = mlx5_ib_create_cq;
1541 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
1542 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
1543 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
1544 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
1545 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
1546 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
1547 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
1548 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
1549 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
1550 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
1551 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 1552 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 1553 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 1554 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 1555 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
e126ba97 1556
938fe83c 1557 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 1558
938fe83c 1559 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 1560 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
1561 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
1562 dev->ib_dev.uverbs_cmd_mask |=
1563 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
1564 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
1565 }
1566
1567 err = init_node_data(dev);
1568 if (err)
233d05d2 1569 goto err_dealloc;
e126ba97
EC		 1570
1571 mutex_init(&dev->cap_mask_mutex);
e126ba97 1572
fc24fc5e
AS		 1573 if (ll == IB_LINK_LAYER_ETHERNET) {
1574 err = mlx5_enable_roce(dev);
1575 if (err)
1576 goto err_dealloc;
1577 }
1578
e126ba97
EC		 1579 err = create_dev_resources(&dev->devr);
1580 if (err)
fc24fc5e 1581 goto err_disable_roce;
e126ba97 1582
6aec21f6 1583 err = mlx5_ib_odp_init_one(dev);
281d1a92 1584 if (err)
e126ba97
EC		 1585 goto err_rsrc;
1586
6aec21f6
HE		 1587 err = ib_register_device(&dev->ib_dev, NULL);
1588 if (err)
1589 goto err_odp;
1590
e126ba97
EC		 1591 err = create_umr_res(dev);
1592 if (err)
1593 goto err_dev;
1594
1595 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 1596 err = device_create_file(&dev->ib_dev.dev,
1597 mlx5_class_attributes[i]);
1598 if (err)
e126ba97
EC		 1599 goto err_umrc;
1600 }
1601
1602 dev->ib_active = true;
1603
9603b61d 1604 return dev;
e126ba97
EC		 1605
1606err_umrc:
1607 destroy_umrc_res(dev);
1608
1609err_dev:
1610 ib_unregister_device(&dev->ib_dev);
1611
6aec21f6
HE		 1612err_odp:
1613 mlx5_ib_odp_remove_one(dev);
1614
e126ba97
EC		 1615err_rsrc:
1616 destroy_dev_resources(&dev->devr);
1617
fc24fc5e
AS		 1618err_disable_roce:
1619 if (ll == IB_LINK_LAYER_ETHERNET)
1620 mlx5_disable_roce(dev);
1621
9603b61d 1622err_dealloc:
e126ba97
EC		 1623 ib_dealloc_device((struct ib_device *)dev);
1624
9603b61d 1625 return NULL;
e126ba97
EC		 1626}
1627
9603b61d 1628static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 1629{
9603b61d 1630 struct mlx5_ib_dev *dev = context;
fc24fc5e 1631 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 1632
e126ba97 1633 ib_unregister_device(&dev->ib_dev);
eefd56e5 1634 destroy_umrc_res(dev);
6aec21f6 1635 mlx5_ib_odp_remove_one(dev);
e126ba97 1636 destroy_dev_resources(&dev->devr);
fc24fc5e
AS		 1637 if (ll == IB_LINK_LAYER_ETHERNET)
1638 mlx5_disable_roce(dev);
e126ba97
EC		 1639 ib_dealloc_device(&dev->ib_dev);
1640}
1641
9603b61d
JM		 1642static struct mlx5_interface mlx5_ib_interface = {
1643 .add = mlx5_ib_add,
1644 .remove = mlx5_ib_remove,
1645 .event = mlx5_ib_event,
64613d94 1646 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 1647};
1648
1649static int __init mlx5_ib_init(void)
1650{
6aec21f6
HE		 1651 int err;
1652
9603b61d
JM		 1653 if (deprecated_prof_sel != 2)
1654 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
1655
6aec21f6
HE		 1656 err = mlx5_ib_odp_init();
1657 if (err)
1658 return err;
1659
1660 err = mlx5_register_interface(&mlx5_ib_interface);
1661 if (err)
1662 goto clean_odp;
1663
1664 return err;
1665
1666clean_odp:
1667 mlx5_ib_odp_cleanup();
1668 return err;
e126ba97
EC		 1669}
1670
1671static void __exit mlx5_ib_cleanup(void)
1672{
9603b61d 1673 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 1674 mlx5_ib_odp_cleanup();
e126ba97
EC		 1675}
1676
1677module_init(mlx5_ib_init);
1678module_exit(mlx5_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)