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IB/mlx5: Add support in TOS and protocol to flow steering
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
7c2344c3 45#include <linux/delay.h>
e126ba97 46#include <rdma/ib_user_verbs.h>
3f89a643 47#include <rdma/ib_addr.h>
2811ba51 48#include <rdma/ib_cache.h>
ada68c31 49#include <linux/mlx5/port.h>
1b5daf11 50#include <linux/mlx5/vport.h>
7c2344c3 51#include <linux/list.h>
e126ba97
EC		 52#include <rdma/ib_smi.h>
53#include <rdma/ib_umem.h>
038d2ef8
MG		 54#include <linux/in.h>
55#include <linux/etherdevice.h>
56#include <linux/mlx5/fs.h>
e126ba97
EC		 57#include "user.h"
58#include "mlx5_ib.h"
59
60#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 61#define DRIVER_VERSION "2.2-1"
62#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 63
64MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
65MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
66MODULE_LICENSE("Dual BSD/GPL");
67MODULE_VERSION(DRIVER_VERSION);
68
9603b61d
JM		 69static int deprecated_prof_sel = 2;
70module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
71MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 72
73static char mlx5_version[] =
74 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
75 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
76
da7525d2
EBE		 77enum {
78 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
79};
80
1b5daf11 81static enum rdma_link_layer
ebd61f68 82mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 83{
ebd61f68 84 switch (port_type_cap) {
1b5daf11
MD		 85 case MLX5_CAP_PORT_TYPE_IB:
86 return IB_LINK_LAYER_INFINIBAND;
87 case MLX5_CAP_PORT_TYPE_ETH:
88 return IB_LINK_LAYER_ETHERNET;
89 default:
90 return IB_LINK_LAYER_UNSPECIFIED;
91 }
92}
93
ebd61f68
AS		 94static enum rdma_link_layer
95mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
96{
97 struct mlx5_ib_dev *dev = to_mdev(device);
98 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
99
100 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
101}
102
fc24fc5e
AS		 103static int mlx5_netdev_event(struct notifier_block *this,
104 unsigned long event, void *ptr)
105{
106 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
107 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
108 roce.nb);
109
110 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
111 return NOTIFY_DONE;
112
113 write_lock(&ibdev->roce.netdev_lock);
114 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
115 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
116 write_unlock(&ibdev->roce.netdev_lock);
117
118 return NOTIFY_DONE;
119}
120
121static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
122 u8 port_num)
123{
124 struct mlx5_ib_dev *ibdev = to_mdev(device);
125 struct net_device *ndev;
126
127 /* Ensure ndev does not disappear before we invoke dev_hold()
128 */
129 read_lock(&ibdev->roce.netdev_lock);
130 ndev = ibdev->roce.netdev;
131 if (ndev)
132 dev_hold(ndev);
133 read_unlock(&ibdev->roce.netdev_lock);
134
135 return ndev;
136}
137
3f89a643
AS		 138static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
139 struct ib_port_attr *props)
140{
141 struct mlx5_ib_dev *dev = to_mdev(device);
142 struct net_device *ndev;
143 enum ib_mtu ndev_ib_mtu;
c876a1b7 144 u16 qkey_viol_cntr;
3f89a643
AS		 145
146 memset(props, 0, sizeof(*props));
147
148 props->port_cap_flags |= IB_PORT_CM_SUP;
149 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
150
151 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
152 roce_address_table_size);
153 props->max_mtu = IB_MTU_4096;
154 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
155 props->pkey_tbl_len = 1;
156 props->state = IB_PORT_DOWN;
157 props->phys_state = 3;
158
c876a1b7
LR		 159 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
160 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 161
162 ndev = mlx5_ib_get_netdev(device, port_num);
163 if (!ndev)
164 return 0;
165
166 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
167 props->state = IB_PORT_ACTIVE;
168 props->phys_state = 5;
169 }
170
171 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
172
173 dev_put(ndev);
174
175 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
176
177 props->active_width = IB_WIDTH_4X; /* TODO */
178 props->active_speed = IB_SPEED_QDR; /* TODO */
179
180 return 0;
181}
182
3cca2606
AS		 183static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
184 const struct ib_gid_attr *attr,
185 void *mlx5_addr)
186{
187#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
188 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
189 source_l3_address);
190 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
191 source_mac_47_32);
192
193 if (!gid)
194 return;
195
196 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
197
198 if (is_vlan_dev(attr->ndev)) {
199 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
200 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
201 }
202
203 switch (attr->gid_type) {
204 case IB_GID_TYPE_IB:
205 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
206 break;
207 case IB_GID_TYPE_ROCE_UDP_ENCAP:
208 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
209 break;
210
211 default:
212 WARN_ON(true);
213 }
214
215 if (attr->gid_type != IB_GID_TYPE_IB) {
216 if (ipv6_addr_v4mapped((void *)gid))
217 MLX5_SET_RA(mlx5_addr, roce_l3_type,
218 MLX5_ROCE_L3_TYPE_IPV4);
219 else
220 MLX5_SET_RA(mlx5_addr, roce_l3_type,
221 MLX5_ROCE_L3_TYPE_IPV6);
222 }
223
224 if ((attr->gid_type == IB_GID_TYPE_IB) ||
225 !ipv6_addr_v4mapped((void *)gid))
226 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
227 else
228 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
229}
230
231static int set_roce_addr(struct ib_device *device, u8 port_num,
232 unsigned int index,
233 const union ib_gid *gid,
234 const struct ib_gid_attr *attr)
235{
c4f287c4
SM		 236 struct mlx5_ib_dev *dev = to_mdev(device);
237 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
238 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
3cca2606
AS		 239 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
240 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
241
242 if (ll != IB_LINK_LAYER_ETHERNET)
243 return -EINVAL;
244
3cca2606
AS		 245 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
246
247 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
248 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
3cca2606
AS		 249 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
250}
251
252static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
253 unsigned int index, const union ib_gid *gid,
254 const struct ib_gid_attr *attr,
255 __always_unused void **context)
256{
257 return set_roce_addr(device, port_num, index, gid, attr);
258}
259
260static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
261 unsigned int index, __always_unused void **context)
262{
263 return set_roce_addr(device, port_num, index, NULL, NULL);
264}
265
2811ba51
AS		 266__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
267 int index)
268{
269 struct ib_gid_attr attr;
270 union ib_gid gid;
271
272 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
273 return 0;
274
275 if (!attr.ndev)
276 return 0;
277
278 dev_put(attr.ndev);
279
280 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
281 return 0;
282
283 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
284}
285
1b5daf11
MD		 286static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
287{
d603c809 288 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
1b5daf11
MD		 289}
290
291enum {
292 MLX5_VPORT_ACCESS_METHOD_MAD,
293 MLX5_VPORT_ACCESS_METHOD_HCA,
294 MLX5_VPORT_ACCESS_METHOD_NIC,
295};
296
297static int mlx5_get_vport_access_method(struct ib_device *ibdev)
298{
299 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
300 return MLX5_VPORT_ACCESS_METHOD_MAD;
301
ebd61f68 302 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 303 IB_LINK_LAYER_ETHERNET)
304 return MLX5_VPORT_ACCESS_METHOD_NIC;
305
306 return MLX5_VPORT_ACCESS_METHOD_HCA;
307}
308
da7525d2
EBE		 309static void get_atomic_caps(struct mlx5_ib_dev *dev,
310 struct ib_device_attr *props)
311{
312 u8 tmp;
313 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
314 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
315 u8 atomic_req_8B_endianness_mode =
316 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
317
318 /* Check if HW supports 8 bytes standard atomic operations and capable
319 * of host endianness respond
320 */
321 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
322 if (((atomic_operations & tmp) == tmp) &&
323 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
324 (atomic_req_8B_endianness_mode)) {
325 props->atomic_cap = IB_ATOMIC_HCA;
326 } else {
327 props->atomic_cap = IB_ATOMIC_NONE;
328 }
329}
330
1b5daf11
MD		 331static int mlx5_query_system_image_guid(struct ib_device *ibdev,
332 __be64 *sys_image_guid)
333{
334 struct mlx5_ib_dev *dev = to_mdev(ibdev);
335 struct mlx5_core_dev *mdev = dev->mdev;
336 u64 tmp;
337 int err;
338
339 switch (mlx5_get_vport_access_method(ibdev)) {
340 case MLX5_VPORT_ACCESS_METHOD_MAD:
341 return mlx5_query_mad_ifc_system_image_guid(ibdev,
342 sys_image_guid);
343
344 case MLX5_VPORT_ACCESS_METHOD_HCA:
345 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 346 break;
347
348 case MLX5_VPORT_ACCESS_METHOD_NIC:
349 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
350 break;
1b5daf11
MD		 351
352 default:
353 return -EINVAL;
354 }
3f89a643
AS		 355
356 if (!err)
357 *sys_image_guid = cpu_to_be64(tmp);
358
359 return err;
360
1b5daf11
MD		 361}
362
363static int mlx5_query_max_pkeys(struct ib_device *ibdev,
364 u16 *max_pkeys)
365{
366 struct mlx5_ib_dev *dev = to_mdev(ibdev);
367 struct mlx5_core_dev *mdev = dev->mdev;
368
369 switch (mlx5_get_vport_access_method(ibdev)) {
370 case MLX5_VPORT_ACCESS_METHOD_MAD:
371 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
372
373 case MLX5_VPORT_ACCESS_METHOD_HCA:
374 case MLX5_VPORT_ACCESS_METHOD_NIC:
375 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
376 pkey_table_size));
377 return 0;
378
379 default:
380 return -EINVAL;
381 }
382}
383
384static int mlx5_query_vendor_id(struct ib_device *ibdev,
385 u32 *vendor_id)
386{
387 struct mlx5_ib_dev *dev = to_mdev(ibdev);
388
389 switch (mlx5_get_vport_access_method(ibdev)) {
390 case MLX5_VPORT_ACCESS_METHOD_MAD:
391 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
392
393 case MLX5_VPORT_ACCESS_METHOD_HCA:
394 case MLX5_VPORT_ACCESS_METHOD_NIC:
395 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
396
397 default:
398 return -EINVAL;
399 }
400}
401
402static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
403 __be64 *node_guid)
404{
405 u64 tmp;
406 int err;
407
408 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
409 case MLX5_VPORT_ACCESS_METHOD_MAD:
410 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
411
412 case MLX5_VPORT_ACCESS_METHOD_HCA:
413 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 414 break;
415
416 case MLX5_VPORT_ACCESS_METHOD_NIC:
417 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
418 break;
1b5daf11
MD		 419
420 default:
421 return -EINVAL;
422 }
3f89a643
AS		 423
424 if (!err)
425 *node_guid = cpu_to_be64(tmp);
426
427 return err;
1b5daf11
MD		 428}
429
430struct mlx5_reg_node_desc {
431 u8 desc[64];
432};
433
434static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
435{
436 struct mlx5_reg_node_desc in;
437
438 if (mlx5_use_mad_ifc(dev))
439 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
440
441 memset(&in, 0, sizeof(in));
442
443 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
444 sizeof(struct mlx5_reg_node_desc),
445 MLX5_REG_NODE_DESC, 0, 0);
446}
447
e126ba97 448static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 449 struct ib_device_attr *props,
450 struct ib_udata *uhw)
e126ba97
EC		 451{
452 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 453 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 454 int err = -ENOMEM;
455 int max_rq_sg;
456 int max_sq_sg;
e0238a6a 457 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 458 struct mlx5_ib_query_device_resp resp = {};
459 size_t resp_len;
460 u64 max_tso;
e126ba97 461
402ca536
BW		 462 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
463 if (uhw->outlen && uhw->outlen < resp_len)
464 return -EINVAL;
465 else
466 resp.response_length = resp_len;
467
468 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 469 return -EINVAL;
470
1b5daf11
MD		 471 memset(props, 0, sizeof(*props));
472 err = mlx5_query_system_image_guid(ibdev,
473 &props->sys_image_guid);
474 if (err)
475 return err;
e126ba97 476
1b5daf11 477 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 478 if (err)
1b5daf11 479 return err;
e126ba97 480
1b5daf11
MD		 481 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
482 if (err)
483 return err;
e126ba97 484
9603b61d
JM		 485 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
486 (fw_rev_min(dev->mdev) << 16) |
487 fw_rev_sub(dev->mdev);
e126ba97
EC		 488 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
489 IB_DEVICE_PORT_ACTIVE_EVENT |
490 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 491 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 492
493 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 494 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 495 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 496 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 497 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 498 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 499 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 500 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 501 if (MLX5_CAP_GEN(mdev, imaicl)) {
502 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
503 IB_DEVICE_MEM_WINDOW_TYPE_2B;
504 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 505 /* We support 'Gappy' memory registration too */
506 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 507 }
e126ba97 508 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 509 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 510 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
511 /* At this stage no support for signature handover */
512 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
513 IB_PROT_T10DIF_TYPE_2 |
514 IB_PROT_T10DIF_TYPE_3;
515 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
516 IB_GUARD_T10DIF_CSUM;
517 }
938fe83c 518 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 519 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 520
402ca536
BW		 521 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
522 if (MLX5_CAP_ETH(mdev, csum_cap))
88115fe7
BW		 523 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
524
402ca536
BW		 525 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
526 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
527 if (max_tso) {
528 resp.tso_caps.max_tso = 1 << max_tso;
529 resp.tso_caps.supported_qpts |=
530 1 << IB_QPT_RAW_PACKET;
531 resp.response_length += sizeof(resp.tso_caps);
532 }
533 }
31f69a82
YH		 534
535 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
536 resp.rss_caps.rx_hash_function =
537 MLX5_RX_HASH_FUNC_TOEPLITZ;
538 resp.rss_caps.rx_hash_fields_mask =
539 MLX5_RX_HASH_SRC_IPV4 |
540 MLX5_RX_HASH_DST_IPV4 |
541 MLX5_RX_HASH_SRC_IPV6 |
542 MLX5_RX_HASH_DST_IPV6 |
543 MLX5_RX_HASH_SRC_PORT_TCP |
544 MLX5_RX_HASH_DST_PORT_TCP |
545 MLX5_RX_HASH_SRC_PORT_UDP |
546 MLX5_RX_HASH_DST_PORT_UDP;
547 resp.response_length += sizeof(resp.rss_caps);
548 }
549 } else {
550 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
551 resp.response_length += sizeof(resp.tso_caps);
552 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
553 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 554 }
555
f0313965
ES		 556 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
557 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
558 props->device_cap_flags |= IB_DEVICE_UD_TSO;
559 }
560
cff5a0f3
MD		 561 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
562 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
563 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
564
da6d6ba3
MG		 565 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
566 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
567
1b5daf11
MD		 568 props->vendor_part_id = mdev->pdev->device;
569 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 570
571 props->max_mr_size = ~0ull;
e0238a6a 572 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 573 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
574 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
575 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
576 sizeof(struct mlx5_wqe_data_seg);
577 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
578 sizeof(struct mlx5_wqe_ctrl_seg)) /
579 sizeof(struct mlx5_wqe_data_seg);
e126ba97 580 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 581 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 582 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 583 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 584 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
585 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
586 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
587 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
588 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
589 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
590 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 591 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 592 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 593 props->max_fast_reg_page_list_len =
594 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 595 get_atomic_caps(dev, props);
81bea28f 596 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 597 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
598 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 599 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
600 props->max_mcast_grp;
601 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
7c60bcbb
MB		 602 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
603 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 604
8cdd312c 605#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 606 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 607 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
608 props->odp_caps = dev->odp_caps;
609#endif
610
051f2630
LR		 611 if (MLX5_CAP_GEN(mdev, cd))
612 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
613
eff901d3
EC		 614 if (!mlx5_core_is_pf(mdev))
615 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
616
31f69a82
YH		 617 if (mlx5_ib_port_link_layer(ibdev, 1) ==
618 IB_LINK_LAYER_ETHERNET) {
619 props->rss_caps.max_rwq_indirection_tables =
620 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
621 props->rss_caps.max_rwq_indirection_table_size =
622 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
623 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
624 props->max_wq_type_rq =
625 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
626 }
627
402ca536
BW		 628 if (uhw->outlen) {
629 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
630
631 if (err)
632 return err;
633 }
634
1b5daf11 635 return 0;
e126ba97
EC		 636}
637
1b5daf11
MD		 638enum mlx5_ib_width {
639 MLX5_IB_WIDTH_1X = 1 << 0,
640 MLX5_IB_WIDTH_2X = 1 << 1,
641 MLX5_IB_WIDTH_4X = 1 << 2,
642 MLX5_IB_WIDTH_8X = 1 << 3,
643 MLX5_IB_WIDTH_12X = 1 << 4
644};
645
646static int translate_active_width(struct ib_device *ibdev, u8 active_width,
647 u8 *ib_width)
e126ba97
EC		 648{
649 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 650 int err = 0;
651
652 if (active_width & MLX5_IB_WIDTH_1X) {
653 *ib_width = IB_WIDTH_1X;
654 } else if (active_width & MLX5_IB_WIDTH_2X) {
655 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
656 (int)active_width);
657 err = -EINVAL;
658 } else if (active_width & MLX5_IB_WIDTH_4X) {
659 *ib_width = IB_WIDTH_4X;
660 } else if (active_width & MLX5_IB_WIDTH_8X) {
661 *ib_width = IB_WIDTH_8X;
662 } else if (active_width & MLX5_IB_WIDTH_12X) {
663 *ib_width = IB_WIDTH_12X;
664 } else {
665 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
666 (int)active_width);
667 err = -EINVAL;
e126ba97
EC		 668 }
669
1b5daf11
MD		 670 return err;
671}
e126ba97 672
1b5daf11
MD		 673static int mlx5_mtu_to_ib_mtu(int mtu)
674{
675 switch (mtu) {
676 case 256: return 1;
677 case 512: return 2;
678 case 1024: return 3;
679 case 2048: return 4;
680 case 4096: return 5;
681 default:
682 pr_warn("invalid mtu\n");
683 return -1;
e126ba97 684 }
1b5daf11 685}
e126ba97 686
1b5daf11
MD		 687enum ib_max_vl_num {
688 __IB_MAX_VL_0 = 1,
689 __IB_MAX_VL_0_1 = 2,
690 __IB_MAX_VL_0_3 = 3,
691 __IB_MAX_VL_0_7 = 4,
692 __IB_MAX_VL_0_14 = 5,
693};
e126ba97 694
1b5daf11
MD		 695enum mlx5_vl_hw_cap {
696 MLX5_VL_HW_0 = 1,
697 MLX5_VL_HW_0_1 = 2,
698 MLX5_VL_HW_0_2 = 3,
699 MLX5_VL_HW_0_3 = 4,
700 MLX5_VL_HW_0_4 = 5,
701 MLX5_VL_HW_0_5 = 6,
702 MLX5_VL_HW_0_6 = 7,
703 MLX5_VL_HW_0_7 = 8,
704 MLX5_VL_HW_0_14 = 15
705};
e126ba97 706
1b5daf11
MD		 707static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
708 u8 *max_vl_num)
709{
710 switch (vl_hw_cap) {
711 case MLX5_VL_HW_0:
712 *max_vl_num = __IB_MAX_VL_0;
713 break;
714 case MLX5_VL_HW_0_1:
715 *max_vl_num = __IB_MAX_VL_0_1;
716 break;
717 case MLX5_VL_HW_0_3:
718 *max_vl_num = __IB_MAX_VL_0_3;
719 break;
720 case MLX5_VL_HW_0_7:
721 *max_vl_num = __IB_MAX_VL_0_7;
722 break;
723 case MLX5_VL_HW_0_14:
724 *max_vl_num = __IB_MAX_VL_0_14;
725 break;
e126ba97 726
1b5daf11
MD		 727 default:
728 return -EINVAL;
e126ba97 729 }
e126ba97 730
1b5daf11 731 return 0;
e126ba97
EC		 732}
733
1b5daf11
MD		 734static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
735 struct ib_port_attr *props)
e126ba97 736{
1b5daf11
MD		 737 struct mlx5_ib_dev *dev = to_mdev(ibdev);
738 struct mlx5_core_dev *mdev = dev->mdev;
739 struct mlx5_hca_vport_context *rep;
046339ea
SM		 740 u16 max_mtu;
741 u16 oper_mtu;
1b5daf11
MD		 742 int err;
743 u8 ib_link_width_oper;
744 u8 vl_hw_cap;
e126ba97 745
1b5daf11
MD		 746 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
747 if (!rep) {
748 err = -ENOMEM;
e126ba97 749 goto out;
e126ba97 750 }
e126ba97 751
1b5daf11 752 memset(props, 0, sizeof(*props));
e126ba97 753
1b5daf11 754 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 755 if (err)
756 goto out;
757
1b5daf11
MD		 758 props->lid = rep->lid;
759 props->lmc = rep->lmc;
760 props->sm_lid = rep->sm_lid;
761 props->sm_sl = rep->sm_sl;
762 props->state = rep->vport_state;
763 props->phys_state = rep->port_physical_state;
764 props->port_cap_flags = rep->cap_mask1;
765 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
766 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
767 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
768 props->bad_pkey_cntr = rep->pkey_violation_counter;
769 props->qkey_viol_cntr = rep->qkey_violation_counter;
770 props->subnet_timeout = rep->subnet_timeout;
771 props->init_type_reply = rep->init_type_reply;
eff901d3 772 props->grh_required = rep->grh_required;
e126ba97 773
1b5daf11
MD		 774 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
775 if (err)
e126ba97 776 goto out;
e126ba97 777
1b5daf11
MD		 778 err = translate_active_width(ibdev, ib_link_width_oper,
779 &props->active_width);
780 if (err)
781 goto out;
d5beb7f2 782 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 783 if (err)
784 goto out;
785
facc9699 786 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 787
1b5daf11 788 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 789
facc9699 790 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 791
1b5daf11 792 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 793
1b5daf11
MD		 794 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
795 if (err)
796 goto out;
e126ba97 797
1b5daf11
MD		 798 err = translate_max_vl_num(ibdev, vl_hw_cap,
799 &props->max_vl_num);
e126ba97 800out:
1b5daf11 801 kfree(rep);
e126ba97
EC		 802 return err;
803}
804
1b5daf11
MD		 805int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
806 struct ib_port_attr *props)
e126ba97 807{
1b5daf11
MD		 808 switch (mlx5_get_vport_access_method(ibdev)) {
809 case MLX5_VPORT_ACCESS_METHOD_MAD:
810 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 811
1b5daf11
MD		 812 case MLX5_VPORT_ACCESS_METHOD_HCA:
813 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 814
3f89a643
AS		 815 case MLX5_VPORT_ACCESS_METHOD_NIC:
816 return mlx5_query_port_roce(ibdev, port, props);
817
1b5daf11
MD		 818 default:
819 return -EINVAL;
820 }
821}
e126ba97 822
1b5daf11
MD		 823static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
824 union ib_gid *gid)
825{
826 struct mlx5_ib_dev *dev = to_mdev(ibdev);
827 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 828
1b5daf11
MD		 829 switch (mlx5_get_vport_access_method(ibdev)) {
830 case MLX5_VPORT_ACCESS_METHOD_MAD:
831 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 832
1b5daf11
MD		 833 case MLX5_VPORT_ACCESS_METHOD_HCA:
834 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
835
836 default:
837 return -EINVAL;
838 }
e126ba97 839
e126ba97
EC		 840}
841
1b5daf11
MD		 842static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
843 u16 *pkey)
844{
845 struct mlx5_ib_dev *dev = to_mdev(ibdev);
846 struct mlx5_core_dev *mdev = dev->mdev;
847
848 switch (mlx5_get_vport_access_method(ibdev)) {
849 case MLX5_VPORT_ACCESS_METHOD_MAD:
850 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
851
852 case MLX5_VPORT_ACCESS_METHOD_HCA:
853 case MLX5_VPORT_ACCESS_METHOD_NIC:
854 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
855 pkey);
856 default:
857 return -EINVAL;
858 }
859}
e126ba97
EC		 860
861static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
862 struct ib_device_modify *props)
863{
864 struct mlx5_ib_dev *dev = to_mdev(ibdev);
865 struct mlx5_reg_node_desc in;
866 struct mlx5_reg_node_desc out;
867 int err;
868
869 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
870 return -EOPNOTSUPP;
871
872 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
873 return 0;
874
875 /*
876 * If possible, pass node desc to FW, so it can generate
877 * a 144 trap. If cmd fails, just ignore.
878 */
879 memcpy(&in, props->node_desc, 64);
9603b61d 880 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 881 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
882 if (err)
883 return err;
884
885 memcpy(ibdev->node_desc, props->node_desc, 64);
886
887 return err;
888}
889
890static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
891 struct ib_port_modify *props)
892{
893 struct mlx5_ib_dev *dev = to_mdev(ibdev);
894 struct ib_port_attr attr;
895 u32 tmp;
896 int err;
897
898 mutex_lock(&dev->cap_mask_mutex);
899
900 err = mlx5_ib_query_port(ibdev, port, &attr);
901 if (err)
902 goto out;
903
904 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
905 ~props->clr_port_cap_mask;
906
9603b61d 907 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 908
909out:
910 mutex_unlock(&dev->cap_mask_mutex);
911 return err;
912}
913
914static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
915 struct ib_udata *udata)
916{
917 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 918 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
919 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97
EC		 920 struct mlx5_ib_ucontext *context;
921 struct mlx5_uuar_info *uuari;
922 struct mlx5_uar *uars;
c1be5232 923 int gross_uuars;
e126ba97 924 int num_uars;
78c0f98c 925 int ver;
e126ba97
EC		 926 int uuarn;
927 int err;
928 int i;
f241e749 929 size_t reqlen;
a168a41c
MD		 930 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
931 max_cqe_version);
e126ba97
EC		 932
933 if (!dev->ib_active)
934 return ERR_PTR(-EAGAIN);
935
dfbee859
HA		 936 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
937 return ERR_PTR(-EINVAL);
938
78c0f98c
EC		 939 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
940 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
941 ver = 0;
a168a41c 942 else if (reqlen >= min_req_v2)
78c0f98c
EC		 943 ver = 2;
944 else
945 return ERR_PTR(-EINVAL);
946
b368d7cb 947 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
e126ba97
EC		 948 if (err)
949 return ERR_PTR(err);
950
b368d7cb 951 if (req.flags)
78c0f98c
EC		 952 return ERR_PTR(-EINVAL);
953
e126ba97
EC		 954 if (req.total_num_uuars > MLX5_MAX_UUARS)
955 return ERR_PTR(-ENOMEM);
956
957 if (req.total_num_uuars == 0)
958 return ERR_PTR(-EINVAL);
959
f72300c5 960 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 961 return ERR_PTR(-EOPNOTSUPP);
962
963 if (reqlen > sizeof(req) &&
964 !ib_is_udata_cleared(udata, sizeof(req),
dfbee859 965 reqlen - sizeof(req)))
b368d7cb
MB		 966 return ERR_PTR(-EOPNOTSUPP);
967
c1be5232
EC		 968 req.total_num_uuars = ALIGN(req.total_num_uuars,
969 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 970 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
971 return ERR_PTR(-EINVAL);
972
c1be5232
EC		 973 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
974 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c 975 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 976 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
977 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
938fe83c
SM		 978 resp.cache_line_size = L1_CACHE_BYTES;
979 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
980 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
981 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
982 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
983 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 984 resp.cqe_version = min_t(__u8,
985 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
986 req.max_cqe_version);
b368d7cb
MB		 987 resp.response_length = min(offsetof(typeof(resp), response_length) +
988 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 989
990 context = kzalloc(sizeof(*context), GFP_KERNEL);
991 if (!context)
992 return ERR_PTR(-ENOMEM);
993
994 uuari = &context->uuari;
995 mutex_init(&uuari->lock);
996 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
997 if (!uars) {
998 err = -ENOMEM;
999 goto out_ctx;
1000 }
1001
c1be5232 1002 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 1003 sizeof(*uuari->bitmap),
1004 GFP_KERNEL);
1005 if (!uuari->bitmap) {
1006 err = -ENOMEM;
1007 goto out_uar_ctx;
1008 }
1009 /*
1010 * clear all fast path uuars
1011 */
c1be5232 1012 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 1013 uuarn = i & 3;
1014 if (uuarn == 2 || uuarn == 3)
1015 set_bit(i, uuari->bitmap);
1016 }
1017
c1be5232 1018 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 1019 if (!uuari->count) {
1020 err = -ENOMEM;
1021 goto out_bitmap;
1022 }
1023
1024 for (i = 0; i < num_uars; i++) {
9603b61d 1025 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 1026 if (err)
1027 goto out_count;
1028 }
1029
b4cfe447
HE		 1030#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1031 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1032#endif
1033
146d2f1a 1034 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1035 err = mlx5_core_alloc_transport_domain(dev->mdev,
1036 &context->tdn);
1037 if (err)
1038 goto out_uars;
1039 }
1040
7c2344c3 1041 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 1042 INIT_LIST_HEAD(&context->db_page_list);
1043 mutex_init(&context->db_page_mutex);
1044
1045 resp.tot_uuars = req.total_num_uuars;
938fe83c 1046 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1047
f72300c5
HA		 1048 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1049 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1050
402ca536
BW		 1051 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1052 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1053 resp.response_length += sizeof(resp.cmds_supp_uhw);
1054 }
1055
bc5c6eed
NO		 1056 /*
1057 * We don't want to expose information from the PCI bar that is located
1058 * after 4096 bytes, so if the arch only supports larger pages, let's
1059 * pretend we don't support reading the HCA's core clock. This is also
1060 * forced by mmap function.
1061 */
1062 if (PAGE_SIZE <= 4096 &&
1063 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
b368d7cb
MB		 1064 resp.comp_mask |=
1065 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1066 resp.hca_core_clock_offset =
1067 offsetof(struct mlx5_init_seg, internal_timer_h) %
1068 PAGE_SIZE;
f72300c5 1069 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1070 sizeof(resp.reserved2);
b368d7cb
MB		 1071 }
1072
1073 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1074 if (err)
146d2f1a 1075 goto out_td;
e126ba97 1076
78c0f98c 1077 uuari->ver = ver;
e126ba97
EC		 1078 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1079 uuari->uars = uars;
1080 uuari->num_uars = num_uars;
f72300c5
HA		 1081 context->cqe_version = resp.cqe_version;
1082
e126ba97
EC		 1083 return &context->ibucontext;
1084
146d2f1a 1085out_td:
1086 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1087 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1088
e126ba97
EC		 1089out_uars:
1090 for (i--; i >= 0; i--)
9603b61d 1091 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 1092out_count:
1093 kfree(uuari->count);
1094
1095out_bitmap:
1096 kfree(uuari->bitmap);
1097
1098out_uar_ctx:
1099 kfree(uars);
1100
1101out_ctx:
1102 kfree(context);
1103 return ERR_PTR(err);
1104}
1105
1106static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1107{
1108 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1109 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1110 struct mlx5_uuar_info *uuari = &context->uuari;
1111 int i;
1112
146d2f1a 1113 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1114 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1115
e126ba97 1116 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 1117 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 1118 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1119 }
1120
1121 kfree(uuari->count);
1122 kfree(uuari->bitmap);
1123 kfree(uuari->uars);
1124 kfree(context);
1125
1126 return 0;
1127}
1128
1129static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1130{
9603b61d 1131 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 1132}
1133
1134static int get_command(unsigned long offset)
1135{
1136 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1137}
1138
1139static int get_arg(unsigned long offset)
1140{
1141 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1142}
1143
1144static int get_index(unsigned long offset)
1145{
1146 return get_arg(offset);
1147}
1148
7c2344c3
MG		 1149static void mlx5_ib_vma_open(struct vm_area_struct *area)
1150{
1151 /* vma_open is called when a new VMA is created on top of our VMA. This
1152 * is done through either mremap flow or split_vma (usually due to
1153 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1154 * as this VMA is strongly hardware related. Therefore we set the
1155 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1156 * calling us again and trying to do incorrect actions. We assume that
1157 * the original VMA size is exactly a single page, and therefore all
1158 * "splitting" operation will not happen to it.
1159 */
1160 area->vm_ops = NULL;
1161}
1162
1163static void mlx5_ib_vma_close(struct vm_area_struct *area)
1164{
1165 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1166
1167 /* It's guaranteed that all VMAs opened on a FD are closed before the
1168 * file itself is closed, therefore no sync is needed with the regular
1169 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1170 * However need a sync with accessing the vma as part of
1171 * mlx5_ib_disassociate_ucontext.
1172 * The close operation is usually called under mm->mmap_sem except when
1173 * process is exiting.
1174 * The exiting case is handled explicitly as part of
1175 * mlx5_ib_disassociate_ucontext.
1176 */
1177 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1178
1179 /* setting the vma context pointer to null in the mlx5_ib driver's
1180 * private data, to protect a race condition in
1181 * mlx5_ib_disassociate_ucontext().
1182 */
1183 mlx5_ib_vma_priv_data->vma = NULL;
1184 list_del(&mlx5_ib_vma_priv_data->list);
1185 kfree(mlx5_ib_vma_priv_data);
1186}
1187
1188static const struct vm_operations_struct mlx5_ib_vm_ops = {
1189 .open = mlx5_ib_vma_open,
1190 .close = mlx5_ib_vma_close
1191};
1192
1193static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1194 struct mlx5_ib_ucontext *ctx)
1195{
1196 struct mlx5_ib_vma_private_data *vma_prv;
1197 struct list_head *vma_head = &ctx->vma_private_list;
1198
1199 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1200 if (!vma_prv)
1201 return -ENOMEM;
1202
1203 vma_prv->vma = vma;
1204 vma->vm_private_data = vma_prv;
1205 vma->vm_ops = &mlx5_ib_vm_ops;
1206
1207 list_add(&vma_prv->list, vma_head);
1208
1209 return 0;
1210}
1211
1212static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1213{
1214 int ret;
1215 struct vm_area_struct *vma;
1216 struct mlx5_ib_vma_private_data *vma_private, *n;
1217 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1218 struct task_struct *owning_process = NULL;
1219 struct mm_struct *owning_mm = NULL;
1220
1221 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1222 if (!owning_process)
1223 return;
1224
1225 owning_mm = get_task_mm(owning_process);
1226 if (!owning_mm) {
1227 pr_info("no mm, disassociate ucontext is pending task termination\n");
1228 while (1) {
1229 put_task_struct(owning_process);
1230 usleep_range(1000, 2000);
1231 owning_process = get_pid_task(ibcontext->tgid,
1232 PIDTYPE_PID);
1233 if (!owning_process ||
1234 owning_process->state == TASK_DEAD) {
1235 pr_info("disassociate ucontext done, task was terminated\n");
1236 /* in case task was dead need to release the
1237 * task struct.
1238 */
1239 if (owning_process)
1240 put_task_struct(owning_process);
1241 return;
1242 }
1243 }
1244 }
1245
1246 /* need to protect from a race on closing the vma as part of
1247 * mlx5_ib_vma_close.
1248 */
1249 down_read(&owning_mm->mmap_sem);
1250 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1251 list) {
1252 vma = vma_private->vma;
1253 ret = zap_vma_ptes(vma, vma->vm_start,
1254 PAGE_SIZE);
1255 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1256 /* context going to be destroyed, should
1257 * not access ops any more.
1258 */
1259 vma->vm_ops = NULL;
1260 list_del(&vma_private->list);
1261 kfree(vma_private);
1262 }
1263 up_read(&owning_mm->mmap_sem);
1264 mmput(owning_mm);
1265 put_task_struct(owning_process);
1266}
1267
37aa5c36
GL		 1268static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1269{
1270 switch (cmd) {
1271 case MLX5_IB_MMAP_WC_PAGE:
1272 return "WC";
1273 case MLX5_IB_MMAP_REGULAR_PAGE:
1274 return "best effort WC";
1275 case MLX5_IB_MMAP_NC_PAGE:
1276 return "NC";
1277 default:
1278 return NULL;
1279 }
1280}
1281
1282static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1283 struct vm_area_struct *vma,
1284 struct mlx5_ib_ucontext *context)
37aa5c36 1285{
7c2344c3 1286 struct mlx5_uuar_info *uuari = &context->uuari;
37aa5c36
GL		 1287 int err;
1288 unsigned long idx;
1289 phys_addr_t pfn, pa;
1290 pgprot_t prot;
1291
1292 switch (cmd) {
1293 case MLX5_IB_MMAP_WC_PAGE:
1294/* Some architectures don't support WC memory */
1295#if defined(CONFIG_X86)
1296 if (!pat_enabled())
1297 return -EPERM;
1298#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1299 return -EPERM;
1300#endif
1301 /* fall through */
1302 case MLX5_IB_MMAP_REGULAR_PAGE:
1303 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1304 prot = pgprot_writecombine(vma->vm_page_prot);
1305 break;
1306 case MLX5_IB_MMAP_NC_PAGE:
1307 prot = pgprot_noncached(vma->vm_page_prot);
1308 break;
1309 default:
1310 return -EINVAL;
1311 }
1312
1313 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1314 return -EINVAL;
1315
1316 idx = get_index(vma->vm_pgoff);
1317 if (idx >= uuari->num_uars)
1318 return -EINVAL;
1319
1320 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1321 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1322
1323 vma->vm_page_prot = prot;
1324 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1325 PAGE_SIZE, vma->vm_page_prot);
1326 if (err) {
1327 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1328 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1329 return -EAGAIN;
1330 }
1331
1332 pa = pfn << PAGE_SHIFT;
1333 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1334 vma->vm_start, &pa);
1335
7c2344c3 1336 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1337}
1338
e126ba97
EC		 1339static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1340{
1341 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1342 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1343 unsigned long command;
e126ba97
EC		 1344 phys_addr_t pfn;
1345
1346 command = get_command(vma->vm_pgoff);
1347 switch (command) {
37aa5c36
GL		 1348 case MLX5_IB_MMAP_WC_PAGE:
1349 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1350 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1351 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1352
1353 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1354 return -ENOSYS;
1355
d69e3bcf 1356 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1357 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1358 return -EINVAL;
1359
6cbac1e4 1360 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1361 return -EPERM;
1362
1363 /* Don't expose to user-space information it shouldn't have */
1364 if (PAGE_SIZE > 4096)
1365 return -EOPNOTSUPP;
1366
1367 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1368 pfn = (dev->mdev->iseg_base +
1369 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1370 PAGE_SHIFT;
1371 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1372 PAGE_SIZE, vma->vm_page_prot))
1373 return -EAGAIN;
1374
1375 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1376 vma->vm_start,
1377 (unsigned long long)pfn << PAGE_SHIFT);
1378 break;
d69e3bcf 1379
e126ba97
EC		 1380 default:
1381 return -EINVAL;
1382 }
1383
1384 return 0;
1385}
1386
e126ba97
EC		 1387static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1388 struct ib_ucontext *context,
1389 struct ib_udata *udata)
1390{
1391 struct mlx5_ib_alloc_pd_resp resp;
1392 struct mlx5_ib_pd *pd;
1393 int err;
1394
1395 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1396 if (!pd)
1397 return ERR_PTR(-ENOMEM);
1398
9603b61d 1399 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1400 if (err) {
1401 kfree(pd);
1402 return ERR_PTR(err);
1403 }
1404
1405 if (context) {
1406 resp.pdn = pd->pdn;
1407 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1408 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1409 kfree(pd);
1410 return ERR_PTR(-EFAULT);
1411 }
e126ba97
EC		 1412 }
1413
1414 return &pd->ibpd;
1415}
1416
1417static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1418{
1419 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1420 struct mlx5_ib_pd *mpd = to_mpd(pd);
1421
9603b61d 1422 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1423 kfree(mpd);
1424
1425 return 0;
1426}
1427
038d2ef8
MG		 1428static bool outer_header_zero(u32 *match_criteria)
1429{
1430 int size = MLX5_ST_SZ_BYTES(fte_match_param);
1431 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria,
1432 outer_headers);
1433
1434 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c,
1435 outer_headers_c + 1,
1436 size - 1);
1437}
1438
ca0d4753
MG		 1439static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1440{
1441 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1442 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1443}
1444
1445static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1446{
1447 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1448 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1449 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1450 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1451}
1452
c47ac6ae
MG		 1453#define LAST_ETH_FIELD vlan_tag
1454#define LAST_IB_FIELD sl
ca0d4753 1455#define LAST_IPV4_FIELD tos
c47ac6ae
MG		 1456#define LAST_IPV6_FIELD dst_ip
1457#define LAST_TCP_UDP_FIELD src_port
1458
1459/* Field is the last supported field */
1460#define FIELDS_NOT_SUPPORTED(filter, field)\
1461 memchr_inv((void *)&filter.field +\
1462 sizeof(filter.field), 0,\
1463 sizeof(filter) -\
1464 offsetof(typeof(filter), field) -\
1465 sizeof(filter.field))
1466
038d2ef8 1467static int parse_flow_attr(u32 *match_c, u32 *match_v,
dd063d0e 1468 const union ib_flow_spec *ib_spec)
038d2ef8
MG		 1469{
1470 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1471 outer_headers);
1472 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1473 outer_headers);
1474 switch (ib_spec->type) {
1475 case IB_FLOW_SPEC_ETH:
c47ac6ae
MG		 1476 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1477 return -ENOTSUPP;
038d2ef8
MG		 1478
1479 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1480 dmac_47_16),
1481 ib_spec->eth.mask.dst_mac);
1482 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1483 dmac_47_16),
1484 ib_spec->eth.val.dst_mac);
1485
1486 if (ib_spec->eth.mask.vlan_tag) {
1487 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1488 vlan_tag, 1);
1489 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1490 vlan_tag, 1);
1491
1492 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1493 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1494 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1495 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1496
1497 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1498 first_cfi,
1499 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1500 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1501 first_cfi,
1502 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1503
1504 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1505 first_prio,
1506 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1507 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1508 first_prio,
1509 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1510 }
1511 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1512 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1513 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1514 ethertype, ntohs(ib_spec->eth.val.ether_type));
1515 break;
1516 case IB_FLOW_SPEC_IPV4:
c47ac6ae
MG		 1517 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1518 return -ENOTSUPP;
038d2ef8
MG		 1519
1520 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1521 ethertype, 0xffff);
1522 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1523 ethertype, ETH_P_IP);
1524
1525 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1526 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1527 &ib_spec->ipv4.mask.src_ip,
1528 sizeof(ib_spec->ipv4.mask.src_ip));
1529 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1530 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1531 &ib_spec->ipv4.val.src_ip,
1532 sizeof(ib_spec->ipv4.val.src_ip));
1533 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1534 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1535 &ib_spec->ipv4.mask.dst_ip,
1536 sizeof(ib_spec->ipv4.mask.dst_ip));
1537 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1538 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1539 &ib_spec->ipv4.val.dst_ip,
1540 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753
MG		 1541
1542 set_tos(outer_headers_c, outer_headers_v,
1543 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1544
1545 set_proto(outer_headers_c, outer_headers_v,
1546 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 1547 break;
026bae0c 1548 case IB_FLOW_SPEC_IPV6:
c47ac6ae
MG		 1549 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1550 return -ENOTSUPP;
026bae0c
MG		 1551
1552 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1553 ethertype, 0xffff);
1554 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1555 ethertype, ETH_P_IPV6);
1556
1557 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1558 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1559 &ib_spec->ipv6.mask.src_ip,
1560 sizeof(ib_spec->ipv6.mask.src_ip));
1561 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1562 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1563 &ib_spec->ipv6.val.src_ip,
1564 sizeof(ib_spec->ipv6.val.src_ip));
1565 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1566 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1567 &ib_spec->ipv6.mask.dst_ip,
1568 sizeof(ib_spec->ipv6.mask.dst_ip));
1569 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1570 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1571 &ib_spec->ipv6.val.dst_ip,
1572 sizeof(ib_spec->ipv6.val.dst_ip));
1573 break;
038d2ef8 1574 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 1575 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1576 LAST_TCP_UDP_FIELD))
1577 return -ENOTSUPP;
038d2ef8
MG		 1578
1579 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1580 0xff);
1581 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1582 IPPROTO_TCP);
1583
1584 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1585 ntohs(ib_spec->tcp_udp.mask.src_port));
1586 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1587 ntohs(ib_spec->tcp_udp.val.src_port));
1588
1589 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1590 ntohs(ib_spec->tcp_udp.mask.dst_port));
1591 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1592 ntohs(ib_spec->tcp_udp.val.dst_port));
1593 break;
1594 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 1595 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1596 LAST_TCP_UDP_FIELD))
1597 return -ENOTSUPP;
038d2ef8
MG		 1598
1599 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1600 0xff);
1601 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1602 IPPROTO_UDP);
1603
1604 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1605 ntohs(ib_spec->tcp_udp.mask.src_port));
1606 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1607 ntohs(ib_spec->tcp_udp.val.src_port));
1608
1609 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1610 ntohs(ib_spec->tcp_udp.mask.dst_port));
1611 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1612 ntohs(ib_spec->tcp_udp.val.dst_port));
1613 break;
1614 default:
1615 return -EINVAL;
1616 }
1617
1618 return 0;
1619}
1620
1621/* If a flow could catch both multicast and unicast packets,
1622 * it won't fall into the multicast flow steering table and this rule
1623 * could steal other multicast packets.
1624 */
1625static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1626{
1627 struct ib_flow_spec_eth *eth_spec;
1628
1629 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1630 ib_attr->size < sizeof(struct ib_flow_attr) +
1631 sizeof(struct ib_flow_spec_eth) ||
1632 ib_attr->num_of_specs < 1)
1633 return false;
1634
1635 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1636 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1637 eth_spec->size != sizeof(*eth_spec))
1638 return false;
1639
1640 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1641 is_multicast_ether_addr(eth_spec->val.dst_mac);
1642}
1643
dd063d0e 1644static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
038d2ef8
MG		 1645{
1646 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1647 bool has_ipv4_spec = false;
1648 bool eth_type_ipv4 = true;
1649 unsigned int spec_index;
1650
1651 /* Validate that ethertype is correct */
1652 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1653 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1654 ib_spec->eth.mask.ether_type) {
1655 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1656 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1657 eth_type_ipv4 = false;
1658 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1659 has_ipv4_spec = true;
1660 }
1661 ib_spec = (void *)ib_spec + ib_spec->size;
1662 }
1663 return !has_ipv4_spec || eth_type_ipv4;
1664}
1665
1666static void put_flow_table(struct mlx5_ib_dev *dev,
1667 struct mlx5_ib_flow_prio *prio, bool ft_added)
1668{
1669 prio->refcount -= !!ft_added;
1670 if (!prio->refcount) {
1671 mlx5_destroy_flow_table(prio->flow_table);
1672 prio->flow_table = NULL;
1673 }
1674}
1675
1676static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1677{
1678 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1679 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1680 struct mlx5_ib_flow_handler,
1681 ibflow);
1682 struct mlx5_ib_flow_handler *iter, *tmp;
1683
1684 mutex_lock(&dev->flow_db.lock);
1685
1686 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1687 mlx5_del_flow_rule(iter->rule);
cc0e5d42 1688 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 1689 list_del(&iter->list);
1690 kfree(iter);
1691 }
1692
1693 mlx5_del_flow_rule(handler->rule);
5497adc6 1694 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 1695 mutex_unlock(&dev->flow_db.lock);
1696
1697 kfree(handler);
1698
1699 return 0;
1700}
1701
35d19011
MG		 1702static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1703{
1704 priority *= 2;
1705 if (!dont_trap)
1706 priority++;
1707 return priority;
1708}
1709
cc0e5d42
MG		 1710enum flow_table_type {
1711 MLX5_IB_FT_RX,
1712 MLX5_IB_FT_TX
1713};
1714
038d2ef8
MG		 1715#define MLX5_FS_MAX_TYPES 10
1716#define MLX5_FS_MAX_ENTRIES 32000UL
1717static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 1718 struct ib_flow_attr *flow_attr,
1719 enum flow_table_type ft_type)
038d2ef8 1720{
35d19011 1721 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 1722 struct mlx5_flow_namespace *ns = NULL;
1723 struct mlx5_ib_flow_prio *prio;
1724 struct mlx5_flow_table *ft;
1725 int num_entries;
1726 int num_groups;
1727 int priority;
1728 int err = 0;
1729
1730 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 1731 if (flow_is_multicast_only(flow_attr) &&
1732 !dont_trap)
038d2ef8
MG		 1733 priority = MLX5_IB_FLOW_MCAST_PRIO;
1734 else
35d19011
MG		 1735 priority = ib_prio_to_core_prio(flow_attr->priority,
1736 dont_trap);
038d2ef8
MG		 1737 ns = mlx5_get_flow_namespace(dev->mdev,
1738 MLX5_FLOW_NAMESPACE_BYPASS);
1739 num_entries = MLX5_FS_MAX_ENTRIES;
1740 num_groups = MLX5_FS_MAX_TYPES;
1741 prio = &dev->flow_db.prios[priority];
1742 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1743 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1744 ns = mlx5_get_flow_namespace(dev->mdev,
1745 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1746 build_leftovers_ft_param(&priority,
1747 &num_entries,
1748 &num_groups);
1749 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 1750 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1751 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1752 allow_sniffer_and_nic_rx_shared_tir))
1753 return ERR_PTR(-ENOTSUPP);
1754
1755 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1756 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1757 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1758
1759 prio = &dev->flow_db.sniffer[ft_type];
1760 priority = 0;
1761 num_entries = 1;
1762 num_groups = 1;
038d2ef8
MG		 1763 }
1764
1765 if (!ns)
1766 return ERR_PTR(-ENOTSUPP);
1767
1768 ft = prio->flow_table;
1769 if (!ft) {
1770 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1771 num_entries,
d63cd286
MG		 1772 num_groups,
1773 0);
038d2ef8
MG		 1774
1775 if (!IS_ERR(ft)) {
1776 prio->refcount = 0;
1777 prio->flow_table = ft;
1778 } else {
1779 err = PTR_ERR(ft);
1780 }
1781 }
1782
1783 return err ? ERR_PTR(err) : prio;
1784}
1785
1786static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1787 struct mlx5_ib_flow_prio *ft_prio,
dd063d0e 1788 const struct ib_flow_attr *flow_attr,
038d2ef8
MG		 1789 struct mlx5_flow_destination *dst)
1790{
1791 struct mlx5_flow_table *ft = ft_prio->flow_table;
1792 struct mlx5_ib_flow_handler *handler;
c5bb1730 1793 struct mlx5_flow_spec *spec;
dd063d0e 1794 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 1795 unsigned int spec_index;
35d19011 1796 u32 action;
038d2ef8
MG		 1797 int err = 0;
1798
1799 if (!is_valid_attr(flow_attr))
1800 return ERR_PTR(-EINVAL);
1801
c5bb1730 1802 spec = mlx5_vzalloc(sizeof(*spec));
038d2ef8 1803 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 1804 if (!handler || !spec) {
038d2ef8
MG		 1805 err = -ENOMEM;
1806 goto free;
1807 }
1808
1809 INIT_LIST_HEAD(&handler->list);
1810
1811 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
c5bb1730
MG		 1812 err = parse_flow_attr(spec->match_criteria,
1813 spec->match_value, ib_flow);
038d2ef8
MG		 1814 if (err < 0)
1815 goto free;
1816
1817 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1818 }
1819
1820 /* Outer header support only */
c5bb1730
MG		 1821 spec->match_criteria_enable = (!outer_header_zero(spec->match_criteria))
1822 << 0;
35d19011
MG		 1823 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1824 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
c5bb1730 1825 handler->rule = mlx5_add_flow_rule(ft, spec,
35d19011 1826 action,
038d2ef8
MG		 1827 MLX5_FS_DEFAULT_FLOW_TAG,
1828 dst);
1829
1830 if (IS_ERR(handler->rule)) {
1831 err = PTR_ERR(handler->rule);
1832 goto free;
1833 }
1834
d9d4980a 1835 ft_prio->refcount++;
5497adc6 1836 handler->prio = ft_prio;
038d2ef8
MG		 1837
1838 ft_prio->flow_table = ft;
1839free:
1840 if (err)
1841 kfree(handler);
c5bb1730 1842 kvfree(spec);
038d2ef8
MG		 1843 return err ? ERR_PTR(err) : handler;
1844}
1845
35d19011
MG		 1846static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1847 struct mlx5_ib_flow_prio *ft_prio,
1848 struct ib_flow_attr *flow_attr,
1849 struct mlx5_flow_destination *dst)
1850{
1851 struct mlx5_ib_flow_handler *handler_dst = NULL;
1852 struct mlx5_ib_flow_handler *handler = NULL;
1853
1854 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1855 if (!IS_ERR(handler)) {
1856 handler_dst = create_flow_rule(dev, ft_prio,
1857 flow_attr, dst);
1858 if (IS_ERR(handler_dst)) {
1859 mlx5_del_flow_rule(handler->rule);
d9d4980a 1860 ft_prio->refcount--;
35d19011
MG		 1861 kfree(handler);
1862 handler = handler_dst;
1863 } else {
1864 list_add(&handler_dst->list, &handler->list);
1865 }
1866 }
1867
1868 return handler;
1869}
038d2ef8
MG		 1870enum {
1871 LEFTOVERS_MC,
1872 LEFTOVERS_UC,
1873};
1874
1875static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1876 struct mlx5_ib_flow_prio *ft_prio,
1877 struct ib_flow_attr *flow_attr,
1878 struct mlx5_flow_destination *dst)
1879{
1880 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1881 struct mlx5_ib_flow_handler *handler = NULL;
1882
1883 static struct {
1884 struct ib_flow_attr flow_attr;
1885 struct ib_flow_spec_eth eth_flow;
1886 } leftovers_specs[] = {
1887 [LEFTOVERS_MC] = {
1888 .flow_attr = {
1889 .num_of_specs = 1,
1890 .size = sizeof(leftovers_specs[0])
1891 },
1892 .eth_flow = {
1893 .type = IB_FLOW_SPEC_ETH,
1894 .size = sizeof(struct ib_flow_spec_eth),
1895 .mask = {.dst_mac = {0x1} },
1896 .val = {.dst_mac = {0x1} }
1897 }
1898 },
1899 [LEFTOVERS_UC] = {
1900 .flow_attr = {
1901 .num_of_specs = 1,
1902 .size = sizeof(leftovers_specs[0])
1903 },
1904 .eth_flow = {
1905 .type = IB_FLOW_SPEC_ETH,
1906 .size = sizeof(struct ib_flow_spec_eth),
1907 .mask = {.dst_mac = {0x1} },
1908 .val = {.dst_mac = {} }
1909 }
1910 }
1911 };
1912
1913 handler = create_flow_rule(dev, ft_prio,
1914 &leftovers_specs[LEFTOVERS_MC].flow_attr,
1915 dst);
1916 if (!IS_ERR(handler) &&
1917 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1918 handler_ucast = create_flow_rule(dev, ft_prio,
1919 &leftovers_specs[LEFTOVERS_UC].flow_attr,
1920 dst);
1921 if (IS_ERR(handler_ucast)) {
7055a294 1922 mlx5_del_flow_rule(handler->rule);
d9d4980a 1923 ft_prio->refcount--;
038d2ef8
MG		 1924 kfree(handler);
1925 handler = handler_ucast;
1926 } else {
1927 list_add(&handler_ucast->list, &handler->list);
1928 }
1929 }
1930
1931 return handler;
1932}
1933
cc0e5d42
MG		 1934static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
1935 struct mlx5_ib_flow_prio *ft_rx,
1936 struct mlx5_ib_flow_prio *ft_tx,
1937 struct mlx5_flow_destination *dst)
1938{
1939 struct mlx5_ib_flow_handler *handler_rx;
1940 struct mlx5_ib_flow_handler *handler_tx;
1941 int err;
1942 static const struct ib_flow_attr flow_attr = {
1943 .num_of_specs = 0,
1944 .size = sizeof(flow_attr)
1945 };
1946
1947 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
1948 if (IS_ERR(handler_rx)) {
1949 err = PTR_ERR(handler_rx);
1950 goto err;
1951 }
1952
1953 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
1954 if (IS_ERR(handler_tx)) {
1955 err = PTR_ERR(handler_tx);
1956 goto err_tx;
1957 }
1958
1959 list_add(&handler_tx->list, &handler_rx->list);
1960
1961 return handler_rx;
1962
1963err_tx:
1964 mlx5_del_flow_rule(handler_rx->rule);
1965 ft_rx->refcount--;
1966 kfree(handler_rx);
1967err:
1968 return ERR_PTR(err);
1969}
1970
038d2ef8
MG		 1971static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
1972 struct ib_flow_attr *flow_attr,
1973 int domain)
1974{
1975 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1976 struct mlx5_ib_flow_handler *handler = NULL;
1977 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 1978 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 1979 struct mlx5_ib_flow_prio *ft_prio;
1980 int err;
1981
1982 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
1983 return ERR_PTR(-ENOSPC);
1984
1985 if (domain != IB_FLOW_DOMAIN_USER ||
1986 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 1987 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 1988 return ERR_PTR(-EINVAL);
1989
1990 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
1991 if (!dst)
1992 return ERR_PTR(-ENOMEM);
1993
1994 mutex_lock(&dev->flow_db.lock);
1995
cc0e5d42 1996 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 1997 if (IS_ERR(ft_prio)) {
1998 err = PTR_ERR(ft_prio);
1999 goto unlock;
2000 }
cc0e5d42
MG		 2001 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2002 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2003 if (IS_ERR(ft_prio_tx)) {
2004 err = PTR_ERR(ft_prio_tx);
2005 ft_prio_tx = NULL;
2006 goto destroy_ft;
2007 }
2008 }
038d2ef8
MG		 2009
2010 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2011 dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
2012
2013 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2014 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2015 handler = create_dont_trap_rule(dev, ft_prio,
2016 flow_attr, dst);
2017 } else {
2018 handler = create_flow_rule(dev, ft_prio, flow_attr,
2019 dst);
2020 }
038d2ef8
MG		 2021 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2022 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2023 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2024 dst);
cc0e5d42
MG		 2025 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2026 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2027 } else {
2028 err = -EINVAL;
2029 goto destroy_ft;
2030 }
2031
2032 if (IS_ERR(handler)) {
2033 err = PTR_ERR(handler);
2034 handler = NULL;
2035 goto destroy_ft;
2036 }
2037
038d2ef8
MG		 2038 mutex_unlock(&dev->flow_db.lock);
2039 kfree(dst);
2040
2041 return &handler->ibflow;
2042
2043destroy_ft:
2044 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 2045 if (ft_prio_tx)
2046 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 2047unlock:
2048 mutex_unlock(&dev->flow_db.lock);
2049 kfree(dst);
2050 kfree(handler);
2051 return ERR_PTR(err);
2052}
2053
e126ba97
EC		 2054static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2055{
2056 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2057 int err;
2058
9603b61d 2059 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2060 if (err)
2061 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2062 ibqp->qp_num, gid->raw);
2063
2064 return err;
2065}
2066
2067static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2068{
2069 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2070 int err;
2071
9603b61d 2072 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2073 if (err)
2074 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2075 ibqp->qp_num, gid->raw);
2076
2077 return err;
2078}
2079
2080static int init_node_data(struct mlx5_ib_dev *dev)
2081{
1b5daf11 2082 int err;
e126ba97 2083
1b5daf11 2084 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2085 if (err)
1b5daf11 2086 return err;
e126ba97 2087
1b5daf11 2088 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 2089
1b5daf11 2090 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 2091}
2092
2093static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2094 char *buf)
2095{
2096 struct mlx5_ib_dev *dev =
2097 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2098
9603b61d 2099 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 2100}
2101
2102static ssize_t show_reg_pages(struct device *device,
2103 struct device_attribute *attr, char *buf)
2104{
2105 struct mlx5_ib_dev *dev =
2106 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2107
6aec21f6 2108 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 2109}
2110
2111static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2112 char *buf)
2113{
2114 struct mlx5_ib_dev *dev =
2115 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2116 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 2117}
2118
e126ba97
EC		 2119static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2120 char *buf)
2121{
2122 struct mlx5_ib_dev *dev =
2123 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2124 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 2125}
2126
2127static ssize_t show_board(struct device *device, struct device_attribute *attr,
2128 char *buf)
2129{
2130 struct mlx5_ib_dev *dev =
2131 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2132 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 2133 dev->mdev->board_id);
e126ba97
EC		 2134}
2135
2136static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 2137static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2138static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2139static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2140static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2141
2142static struct device_attribute *mlx5_class_attributes[] = {
2143 &dev_attr_hw_rev,
e126ba97
EC		 2144 &dev_attr_hca_type,
2145 &dev_attr_board_id,
2146 &dev_attr_fw_pages,
2147 &dev_attr_reg_pages,
2148};
2149
7722f47e
HE		 2150static void pkey_change_handler(struct work_struct *work)
2151{
2152 struct mlx5_ib_port_resources *ports =
2153 container_of(work, struct mlx5_ib_port_resources,
2154 pkey_change_work);
2155
2156 mutex_lock(&ports->devr->mutex);
2157 mlx5_ib_gsi_pkey_change(ports->gsi);
2158 mutex_unlock(&ports->devr->mutex);
2159}
2160
89ea94a7
MG		 2161static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2162{
2163 struct mlx5_ib_qp *mqp;
2164 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2165 struct mlx5_core_cq *mcq;
2166 struct list_head cq_armed_list;
2167 unsigned long flags_qp;
2168 unsigned long flags_cq;
2169 unsigned long flags;
2170
2171 INIT_LIST_HEAD(&cq_armed_list);
2172
2173 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2174 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2175 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2176 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2177 if (mqp->sq.tail != mqp->sq.head) {
2178 send_mcq = to_mcq(mqp->ibqp.send_cq);
2179 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2180 if (send_mcq->mcq.comp &&
2181 mqp->ibqp.send_cq->comp_handler) {
2182 if (!send_mcq->mcq.reset_notify_added) {
2183 send_mcq->mcq.reset_notify_added = 1;
2184 list_add_tail(&send_mcq->mcq.reset_notify,
2185 &cq_armed_list);
2186 }
2187 }
2188 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2189 }
2190 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2191 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2192 /* no handling is needed for SRQ */
2193 if (!mqp->ibqp.srq) {
2194 if (mqp->rq.tail != mqp->rq.head) {
2195 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2196 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2197 if (recv_mcq->mcq.comp &&
2198 mqp->ibqp.recv_cq->comp_handler) {
2199 if (!recv_mcq->mcq.reset_notify_added) {
2200 recv_mcq->mcq.reset_notify_added = 1;
2201 list_add_tail(&recv_mcq->mcq.reset_notify,
2202 &cq_armed_list);
2203 }
2204 }
2205 spin_unlock_irqrestore(&recv_mcq->lock,
2206 flags_cq);
2207 }
2208 }
2209 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2210 }
2211 /*At that point all inflight post send were put to be executed as of we
2212 * lock/unlock above locks Now need to arm all involved CQs.
2213 */
2214 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2215 mcq->comp(mcq);
2216 }
2217 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2218}
2219
9603b61d 2220static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2221 enum mlx5_dev_event event, unsigned long param)
e126ba97 2222{
9603b61d 2223 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2224 struct ib_event ibev;
9603b61d 2225
e126ba97
EC		 2226 u8 port = 0;
2227
2228 switch (event) {
2229 case MLX5_DEV_EVENT_SYS_ERROR:
2230 ibdev->ib_active = false;
2231 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2232 mlx5_ib_handle_internal_error(ibdev);
e126ba97
EC		 2233 break;
2234
2235 case MLX5_DEV_EVENT_PORT_UP:
2236 ibev.event = IB_EVENT_PORT_ACTIVE;
4d2f9bbb 2237 port = (u8)param;
e126ba97
EC		 2238 break;
2239
2240 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2241 case MLX5_DEV_EVENT_PORT_INITIALIZED:
e126ba97 2242 ibev.event = IB_EVENT_PORT_ERR;
4d2f9bbb 2243 port = (u8)param;
e126ba97
EC		 2244 break;
2245
e126ba97
EC		 2246 case MLX5_DEV_EVENT_LID_CHANGE:
2247 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2248 port = (u8)param;
e126ba97
EC		 2249 break;
2250
2251 case MLX5_DEV_EVENT_PKEY_CHANGE:
2252 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2253 port = (u8)param;
7722f47e
HE		 2254
2255 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2256 break;
2257
2258 case MLX5_DEV_EVENT_GUID_CHANGE:
2259 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2260 port = (u8)param;
e126ba97
EC		 2261 break;
2262
2263 case MLX5_DEV_EVENT_CLIENT_REREG:
2264 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2265 port = (u8)param;
e126ba97
EC		 2266 break;
2267 }
2268
2269 ibev.device = &ibdev->ib_dev;
2270 ibev.element.port_num = port;
2271
a0c84c32
EC		 2272 if (port < 1 || port > ibdev->num_ports) {
2273 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2274 return;
2275 }
2276
e126ba97
EC		 2277 if (ibdev->ib_active)
2278 ib_dispatch_event(&ibev);
2279}
2280
2281static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2282{
2283 int port;
2284
938fe83c 2285 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 2286 mlx5_query_ext_port_caps(dev, port);
2287}
2288
2289static int get_port_caps(struct mlx5_ib_dev *dev)
2290{
2291 struct ib_device_attr *dprops = NULL;
2292 struct ib_port_attr *pprops = NULL;
f614fc15 2293 int err = -ENOMEM;
e126ba97 2294 int port;
2528e33e 2295 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 2296
2297 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2298 if (!pprops)
2299 goto out;
2300
2301 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2302 if (!dprops)
2303 goto out;
2304
2528e33e 2305 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 2306 if (err) {
2307 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2308 goto out;
2309 }
2310
938fe83c 2311 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 2312 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2313 if (err) {
938fe83c
SM		 2314 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2315 port, err);
e126ba97
EC		 2316 break;
2317 }
938fe83c
SM		 2318 dev->mdev->port_caps[port - 1].pkey_table_len =
2319 dprops->max_pkeys;
2320 dev->mdev->port_caps[port - 1].gid_table_len =
2321 pprops->gid_tbl_len;
e126ba97
EC		 2322 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2323 dprops->max_pkeys, pprops->gid_tbl_len);
2324 }
2325
2326out:
2327 kfree(pprops);
2328 kfree(dprops);
2329
2330 return err;
2331}
2332
2333static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2334{
2335 int err;
2336
2337 err = mlx5_mr_cache_cleanup(dev);
2338 if (err)
2339 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2340
2341 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 2342 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 2343 ib_dealloc_pd(dev->umrc.pd);
2344}
2345
2346enum {
2347 MAX_UMR_WR = 128,
2348};
2349
2350static int create_umr_res(struct mlx5_ib_dev *dev)
2351{
2352 struct ib_qp_init_attr *init_attr = NULL;
2353 struct ib_qp_attr *attr = NULL;
2354 struct ib_pd *pd;
2355 struct ib_cq *cq;
2356 struct ib_qp *qp;
e126ba97
EC		 2357 int ret;
2358
2359 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2360 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2361 if (!attr || !init_attr) {
2362 ret = -ENOMEM;
2363 goto error_0;
2364 }
2365
ed082d36 2366 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 2367 if (IS_ERR(pd)) {
2368 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2369 ret = PTR_ERR(pd);
2370 goto error_0;
2371 }
2372
add08d76 2373 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 2374 if (IS_ERR(cq)) {
2375 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2376 ret = PTR_ERR(cq);
2377 goto error_2;
2378 }
e126ba97
EC		 2379
2380 init_attr->send_cq = cq;
2381 init_attr->recv_cq = cq;
2382 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2383 init_attr->cap.max_send_wr = MAX_UMR_WR;
2384 init_attr->cap.max_send_sge = 1;
2385 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2386 init_attr->port_num = 1;
2387 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2388 if (IS_ERR(qp)) {
2389 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2390 ret = PTR_ERR(qp);
2391 goto error_3;
2392 }
2393 qp->device = &dev->ib_dev;
2394 qp->real_qp = qp;
2395 qp->uobject = NULL;
2396 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2397
2398 attr->qp_state = IB_QPS_INIT;
2399 attr->port_num = 1;
2400 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2401 IB_QP_PORT, NULL);
2402 if (ret) {
2403 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2404 goto error_4;
2405 }
2406
2407 memset(attr, 0, sizeof(*attr));
2408 attr->qp_state = IB_QPS_RTR;
2409 attr->path_mtu = IB_MTU_256;
2410
2411 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2412 if (ret) {
2413 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2414 goto error_4;
2415 }
2416
2417 memset(attr, 0, sizeof(*attr));
2418 attr->qp_state = IB_QPS_RTS;
2419 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2420 if (ret) {
2421 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2422 goto error_4;
2423 }
2424
2425 dev->umrc.qp = qp;
2426 dev->umrc.cq = cq;
e126ba97
EC		 2427 dev->umrc.pd = pd;
2428
2429 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2430 ret = mlx5_mr_cache_init(dev);
2431 if (ret) {
2432 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2433 goto error_4;
2434 }
2435
2436 kfree(attr);
2437 kfree(init_attr);
2438
2439 return 0;
2440
2441error_4:
2442 mlx5_ib_destroy_qp(qp);
2443
2444error_3:
add08d76 2445 ib_free_cq(cq);
e126ba97
EC		 2446
2447error_2:
e126ba97
EC		 2448 ib_dealloc_pd(pd);
2449
2450error_0:
2451 kfree(attr);
2452 kfree(init_attr);
2453 return ret;
2454}
2455
2456static int create_dev_resources(struct mlx5_ib_resources *devr)
2457{
2458 struct ib_srq_init_attr attr;
2459 struct mlx5_ib_dev *dev;
bcf4c1ea 2460 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 2461 int port;
e126ba97
EC		 2462 int ret = 0;
2463
2464 dev = container_of(devr, struct mlx5_ib_dev, devr);
2465
d16e91da
HE		 2466 mutex_init(&devr->mutex);
2467
e126ba97
EC		 2468 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2469 if (IS_ERR(devr->p0)) {
2470 ret = PTR_ERR(devr->p0);
2471 goto error0;
2472 }
2473 devr->p0->device = &dev->ib_dev;
2474 devr->p0->uobject = NULL;
2475 atomic_set(&devr->p0->usecnt, 0);
2476
bcf4c1ea 2477 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 2478 if (IS_ERR(devr->c0)) {
2479 ret = PTR_ERR(devr->c0);
2480 goto error1;
2481 }
2482 devr->c0->device = &dev->ib_dev;
2483 devr->c0->uobject = NULL;
2484 devr->c0->comp_handler = NULL;
2485 devr->c0->event_handler = NULL;
2486 devr->c0->cq_context = NULL;
2487 atomic_set(&devr->c0->usecnt, 0);
2488
2489 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2490 if (IS_ERR(devr->x0)) {
2491 ret = PTR_ERR(devr->x0);
2492 goto error2;
2493 }
2494 devr->x0->device = &dev->ib_dev;
2495 devr->x0->inode = NULL;
2496 atomic_set(&devr->x0->usecnt, 0);
2497 mutex_init(&devr->x0->tgt_qp_mutex);
2498 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2499
2500 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2501 if (IS_ERR(devr->x1)) {
2502 ret = PTR_ERR(devr->x1);
2503 goto error3;
2504 }
2505 devr->x1->device = &dev->ib_dev;
2506 devr->x1->inode = NULL;
2507 atomic_set(&devr->x1->usecnt, 0);
2508 mutex_init(&devr->x1->tgt_qp_mutex);
2509 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2510
2511 memset(&attr, 0, sizeof(attr));
2512 attr.attr.max_sge = 1;
2513 attr.attr.max_wr = 1;
2514 attr.srq_type = IB_SRQT_XRC;
2515 attr.ext.xrc.cq = devr->c0;
2516 attr.ext.xrc.xrcd = devr->x0;
2517
2518 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2519 if (IS_ERR(devr->s0)) {
2520 ret = PTR_ERR(devr->s0);
2521 goto error4;
2522 }
2523 devr->s0->device = &dev->ib_dev;
2524 devr->s0->pd = devr->p0;
2525 devr->s0->uobject = NULL;
2526 devr->s0->event_handler = NULL;
2527 devr->s0->srq_context = NULL;
2528 devr->s0->srq_type = IB_SRQT_XRC;
2529 devr->s0->ext.xrc.xrcd = devr->x0;
2530 devr->s0->ext.xrc.cq = devr->c0;
2531 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2532 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2533 atomic_inc(&devr->p0->usecnt);
2534 atomic_set(&devr->s0->usecnt, 0);
2535
4aa17b28
HA		 2536 memset(&attr, 0, sizeof(attr));
2537 attr.attr.max_sge = 1;
2538 attr.attr.max_wr = 1;
2539 attr.srq_type = IB_SRQT_BASIC;
2540 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2541 if (IS_ERR(devr->s1)) {
2542 ret = PTR_ERR(devr->s1);
2543 goto error5;
2544 }
2545 devr->s1->device = &dev->ib_dev;
2546 devr->s1->pd = devr->p0;
2547 devr->s1->uobject = NULL;
2548 devr->s1->event_handler = NULL;
2549 devr->s1->srq_context = NULL;
2550 devr->s1->srq_type = IB_SRQT_BASIC;
2551 devr->s1->ext.xrc.cq = devr->c0;
2552 atomic_inc(&devr->p0->usecnt);
2553 atomic_set(&devr->s0->usecnt, 0);
2554
7722f47e
HE		 2555 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2556 INIT_WORK(&devr->ports[port].pkey_change_work,
2557 pkey_change_handler);
2558 devr->ports[port].devr = devr;
2559 }
2560
e126ba97
EC		 2561 return 0;
2562
4aa17b28
HA		 2563error5:
2564 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 2565error4:
2566 mlx5_ib_dealloc_xrcd(devr->x1);
2567error3:
2568 mlx5_ib_dealloc_xrcd(devr->x0);
2569error2:
2570 mlx5_ib_destroy_cq(devr->c0);
2571error1:
2572 mlx5_ib_dealloc_pd(devr->p0);
2573error0:
2574 return ret;
2575}
2576
2577static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2578{
7722f47e
HE		 2579 struct mlx5_ib_dev *dev =
2580 container_of(devr, struct mlx5_ib_dev, devr);
2581 int port;
2582
4aa17b28 2583 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 2584 mlx5_ib_destroy_srq(devr->s0);
2585 mlx5_ib_dealloc_xrcd(devr->x0);
2586 mlx5_ib_dealloc_xrcd(devr->x1);
2587 mlx5_ib_destroy_cq(devr->c0);
2588 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 2589
2590 /* Make sure no change P_Key work items are still executing */
2591 for (port = 0; port < dev->num_ports; ++port)
2592 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 2593}
2594
e53505a8
AS		 2595static u32 get_core_cap_flags(struct ib_device *ibdev)
2596{
2597 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2598 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2599 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2600 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2601 u32 ret = 0;
2602
2603 if (ll == IB_LINK_LAYER_INFINIBAND)
2604 return RDMA_CORE_PORT_IBA_IB;
2605
2606 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2607 return 0;
2608
2609 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2610 return 0;
2611
2612 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2613 ret |= RDMA_CORE_PORT_IBA_ROCE;
2614
2615 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2616 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2617
2618 return ret;
2619}
2620
7738613e
IW		 2621static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2622 struct ib_port_immutable *immutable)
2623{
2624 struct ib_port_attr attr;
2625 int err;
2626
2627 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2628 if (err)
2629 return err;
2630
2631 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2632 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 2633 immutable->core_cap_flags = get_core_cap_flags(ibdev);
337877a4 2634 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 2635
2636 return 0;
2637}
2638
c7342823
IW		 2639static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2640 size_t str_len)
2641{
2642 struct mlx5_ib_dev *dev =
2643 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2644 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2645 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2646}
2647
fc24fc5e
AS		 2648static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2649{
e53505a8
AS		 2650 int err;
2651
fc24fc5e 2652 dev->roce.nb.notifier_call = mlx5_netdev_event;
e53505a8
AS		 2653 err = register_netdevice_notifier(&dev->roce.nb);
2654 if (err)
2655 return err;
2656
2657 err = mlx5_nic_vport_enable_roce(dev->mdev);
2658 if (err)
2659 goto err_unregister_netdevice_notifier;
2660
2661 return 0;
2662
2663err_unregister_netdevice_notifier:
2664 unregister_netdevice_notifier(&dev->roce.nb);
2665 return err;
fc24fc5e
AS		 2666}
2667
2668static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2669{
e53505a8 2670 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 2671 unregister_netdevice_notifier(&dev->roce.nb);
2672}
2673
0837e86a
MB		 2674static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2675{
2676 unsigned int i;
2677
2678 for (i = 0; i < dev->num_ports; i++)
2679 mlx5_core_dealloc_q_counter(dev->mdev,
2680 dev->port[i].q_cnt_id);
2681}
2682
2683static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2684{
2685 int i;
2686 int ret;
2687
2688 for (i = 0; i < dev->num_ports; i++) {
2689 ret = mlx5_core_alloc_q_counter(dev->mdev,
2690 &dev->port[i].q_cnt_id);
2691 if (ret) {
2692 mlx5_ib_warn(dev,
2693 "couldn't allocate queue counter for port %d, err %d\n",
2694 i + 1, ret);
2695 goto dealloc_counters;
2696 }
2697 }
2698
2699 return 0;
2700
2701dealloc_counters:
2702 while (--i >= 0)
2703 mlx5_core_dealloc_q_counter(dev->mdev,
2704 dev->port[i].q_cnt_id);
2705
2706 return ret;
2707}
2708
61961500 2709static const char * const names[] = {
0ad17a8f
MB		 2710 "rx_write_requests",
2711 "rx_read_requests",
2712 "rx_atomic_requests",
2713 "out_of_buffer",
2714 "out_of_sequence",
2715 "duplicate_request",
2716 "rnr_nak_retry_err",
2717 "packet_seq_err",
2718 "implied_nak_seq_err",
2719 "local_ack_timeout_err",
2720};
2721
2722static const size_t stats_offsets[] = {
2723 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2724 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2725 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2726 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2727 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2728 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2729 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2730 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2731 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2732 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2733};
2734
2735static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2736 u8 port_num)
2737{
2738 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2739
2740 /* We support only per port stats */
2741 if (port_num == 0)
2742 return NULL;
2743
2744 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2745 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2746}
2747
2748static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2749 struct rdma_hw_stats *stats,
2750 u8 port, int index)
2751{
2752 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2753 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2754 void *out;
2755 __be32 val;
2756 int ret;
2757 int i;
2758
2759 if (!port || !stats)
2760 return -ENOSYS;
2761
2762 out = mlx5_vzalloc(outlen);
2763 if (!out)
2764 return -ENOMEM;
2765
2766 ret = mlx5_core_query_q_counter(dev->mdev,
2767 dev->port[port - 1].q_cnt_id, 0,
2768 out, outlen);
2769 if (ret)
2770 goto free;
2771
2772 for (i = 0; i < ARRAY_SIZE(names); i++) {
2773 val = *(__be32 *)(out + stats_offsets[i]);
2774 stats->value[i] = (u64)be32_to_cpu(val);
2775 }
2776free:
2777 kvfree(out);
2778 return ARRAY_SIZE(names);
2779}
2780
9603b61d 2781static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 2782{
e126ba97 2783 struct mlx5_ib_dev *dev;
ebd61f68
AS		 2784 enum rdma_link_layer ll;
2785 int port_type_cap;
e126ba97
EC		 2786 int err;
2787 int i;
2788
ebd61f68
AS		 2789 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2790 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2791
e53505a8 2792 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
647241ea
MD		 2793 return NULL;
2794
e126ba97
EC		 2795 printk_once(KERN_INFO "%s", mlx5_version);
2796
2797 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2798 if (!dev)
9603b61d 2799 return NULL;
e126ba97 2800
9603b61d 2801 dev->mdev = mdev;
e126ba97 2802
0837e86a
MB		 2803 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2804 GFP_KERNEL);
2805 if (!dev->port)
2806 goto err_dealloc;
2807
fc24fc5e 2808 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 2809 err = get_port_caps(dev);
2810 if (err)
0837e86a 2811 goto err_free_port;
e126ba97 2812
1b5daf11
MD		 2813 if (mlx5_use_mad_ifc(dev))
2814 get_ext_port_caps(dev);
e126ba97 2815
e126ba97
EC		 2816 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2817
2818 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
2819 dev->ib_dev.owner = THIS_MODULE;
2820 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 2821 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 2822 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 2823 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 2824 dev->ib_dev.num_comp_vectors =
2825 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 2826 dev->ib_dev.dma_device = &mdev->pdev->dev;
2827
2828 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
2829 dev->ib_dev.uverbs_cmd_mask =
2830 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2831 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2832 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2833 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2834 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2835 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 2836 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 2837 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2838 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2839 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2840 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2841 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2842 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2843 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2844 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2845 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2846 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2847 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2848 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2849 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2850 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2851 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2852 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2853 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 2854 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 2855 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2856 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2857 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
e126ba97
EC		 2858
2859 dev->ib_dev.query_device = mlx5_ib_query_device;
2860 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 2861 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 2862 if (ll == IB_LINK_LAYER_ETHERNET)
2863 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 2864 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 2865 dev->ib_dev.add_gid = mlx5_ib_add_gid;
2866 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 2867 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
2868 dev->ib_dev.modify_device = mlx5_ib_modify_device;
2869 dev->ib_dev.modify_port = mlx5_ib_modify_port;
2870 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
2871 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
2872 dev->ib_dev.mmap = mlx5_ib_mmap;
2873 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
2874 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
2875 dev->ib_dev.create_ah = mlx5_ib_create_ah;
2876 dev->ib_dev.query_ah = mlx5_ib_query_ah;
2877 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
2878 dev->ib_dev.create_srq = mlx5_ib_create_srq;
2879 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
2880 dev->ib_dev.query_srq = mlx5_ib_query_srq;
2881 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
2882 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
2883 dev->ib_dev.create_qp = mlx5_ib_create_qp;
2884 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
2885 dev->ib_dev.query_qp = mlx5_ib_query_qp;
2886 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
2887 dev->ib_dev.post_send = mlx5_ib_post_send;
2888 dev->ib_dev.post_recv = mlx5_ib_post_recv;
2889 dev->ib_dev.create_cq = mlx5_ib_create_cq;
2890 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
2891 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
2892 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
2893 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
2894 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
2895 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
2896 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 2897 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 2898 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
2899 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
2900 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
2901 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 2902 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 2903 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 2904 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 2905 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 2906 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
eff901d3
EC		 2907 if (mlx5_core_is_pf(mdev)) {
2908 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
2909 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
2910 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
2911 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
2912 }
e126ba97 2913
7c2344c3
MG		 2914 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
2915
938fe83c 2916 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 2917
d2370e0a
MB		 2918 if (MLX5_CAP_GEN(mdev, imaicl)) {
2919 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
2920 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
2921 dev->ib_dev.uverbs_cmd_mask |=
2922 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2923 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2924 }
2925
0ad17a8f
MB		 2926 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
2927 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
2928 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
2929 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
2930 }
2931
938fe83c 2932 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 2933 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
2934 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
2935 dev->ib_dev.uverbs_cmd_mask |=
2936 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2937 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2938 }
2939
048ccca8 2940 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8
MG		 2941 IB_LINK_LAYER_ETHERNET) {
2942 dev->ib_dev.create_flow = mlx5_ib_create_flow;
2943 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
79b20a6c
YH		 2944 dev->ib_dev.create_wq = mlx5_ib_create_wq;
2945 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
2946 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 2947 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
2948 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8
MG		 2949 dev->ib_dev.uverbs_ex_cmd_mask |=
2950 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
79b20a6c
YH		 2951 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
2952 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
2953 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 2954 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
2955 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
2956 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 2957 }
e126ba97
EC		 2958 err = init_node_data(dev);
2959 if (err)
233d05d2 2960 goto err_dealloc;
e126ba97 2961
038d2ef8 2962 mutex_init(&dev->flow_db.lock);
e126ba97 2963 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 2964 INIT_LIST_HEAD(&dev->qp_list);
2965 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 2966
fc24fc5e
AS		 2967 if (ll == IB_LINK_LAYER_ETHERNET) {
2968 err = mlx5_enable_roce(dev);
2969 if (err)
2970 goto err_dealloc;
2971 }
2972
e126ba97
EC		 2973 err = create_dev_resources(&dev->devr);
2974 if (err)
fc24fc5e 2975 goto err_disable_roce;
e126ba97 2976
6aec21f6 2977 err = mlx5_ib_odp_init_one(dev);
281d1a92 2978 if (err)
e126ba97
EC		 2979 goto err_rsrc;
2980
0837e86a 2981 err = mlx5_ib_alloc_q_counters(dev);
6aec21f6
HE		 2982 if (err)
2983 goto err_odp;
2984
0837e86a
MB		 2985 err = ib_register_device(&dev->ib_dev, NULL);
2986 if (err)
2987 goto err_q_cnt;
2988
e126ba97
EC		 2989 err = create_umr_res(dev);
2990 if (err)
2991 goto err_dev;
2992
2993 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 2994 err = device_create_file(&dev->ib_dev.dev,
2995 mlx5_class_attributes[i]);
2996 if (err)
e126ba97
EC		 2997 goto err_umrc;
2998 }
2999
3000 dev->ib_active = true;
3001
9603b61d 3002 return dev;
e126ba97
EC		 3003
3004err_umrc:
3005 destroy_umrc_res(dev);
3006
3007err_dev:
3008 ib_unregister_device(&dev->ib_dev);
3009
0837e86a
MB		 3010err_q_cnt:
3011 mlx5_ib_dealloc_q_counters(dev);
3012
6aec21f6
HE		 3013err_odp:
3014 mlx5_ib_odp_remove_one(dev);
3015
e126ba97
EC		 3016err_rsrc:
3017 destroy_dev_resources(&dev->devr);
3018
fc24fc5e
AS		 3019err_disable_roce:
3020 if (ll == IB_LINK_LAYER_ETHERNET)
3021 mlx5_disable_roce(dev);
3022
0837e86a
MB		 3023err_free_port:
3024 kfree(dev->port);
3025
9603b61d 3026err_dealloc:
e126ba97
EC		 3027 ib_dealloc_device((struct ib_device *)dev);
3028
9603b61d 3029 return NULL;
e126ba97
EC		 3030}
3031
9603b61d 3032static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 3033{
9603b61d 3034 struct mlx5_ib_dev *dev = context;
fc24fc5e 3035 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 3036
e126ba97 3037 ib_unregister_device(&dev->ib_dev);
0837e86a 3038 mlx5_ib_dealloc_q_counters(dev);
eefd56e5 3039 destroy_umrc_res(dev);
6aec21f6 3040 mlx5_ib_odp_remove_one(dev);
e126ba97 3041 destroy_dev_resources(&dev->devr);
fc24fc5e
AS		 3042 if (ll == IB_LINK_LAYER_ETHERNET)
3043 mlx5_disable_roce(dev);
0837e86a 3044 kfree(dev->port);
e126ba97
EC		 3045 ib_dealloc_device(&dev->ib_dev);
3046}
3047
9603b61d
JM		 3048static struct mlx5_interface mlx5_ib_interface = {
3049 .add = mlx5_ib_add,
3050 .remove = mlx5_ib_remove,
3051 .event = mlx5_ib_event,
64613d94 3052 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 3053};
3054
3055static int __init mlx5_ib_init(void)
3056{
6aec21f6
HE		 3057 int err;
3058
9603b61d
JM		 3059 if (deprecated_prof_sel != 2)
3060 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3061
6aec21f6
HE		 3062 err = mlx5_ib_odp_init();
3063 if (err)
3064 return err;
3065
3066 err = mlx5_register_interface(&mlx5_ib_interface);
3067 if (err)
3068 goto clean_odp;
3069
3070 return err;
3071
3072clean_odp:
3073 mlx5_ib_odp_cleanup();
3074 return err;
e126ba97
EC		 3075}
3076
3077static void __exit mlx5_ib_cleanup(void)
3078{
9603b61d 3079 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 3080 mlx5_ib_odp_cleanup();
e126ba97
EC		 3081}
3082
3083module_init(mlx5_ib_init);
3084module_exit(mlx5_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)