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RDMA/netdev: Use priv_destructor for netdev cleanup
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
7c2344c3 55#include <linux/list.h>
e126ba97
EC		 56#include <rdma/ib_smi.h>
57#include <rdma/ib_umem.h>
038d2ef8
MG		 58#include <linux/in.h>
59#include <linux/etherdevice.h>
e126ba97 60#include "mlx5_ib.h"
fc385b7a 61#include "ib_rep.h"
e1f24a79 62#include "cmd.h"
3346c487 63#include <linux/mlx5/fs_helpers.h>
c6475a0b 64#include <linux/mlx5/accel.h>
8c84660b 65#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 66#include <rdma/mlx5_user_ioctl_verbs.h>
67#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 68
69#define UVERBS_MODULE_NAME mlx5_ib
70#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 71
72#define DRIVER_NAME "mlx5_ib"
b359911d 73#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 74
75MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
77MODULE_LICENSE("Dual BSD/GPL");
e126ba97 78
e126ba97
EC		 79static char mlx5_version[] =
80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 81 DRIVER_VERSION "\n";
e126ba97 82
d69a24e0
DJ		 83struct mlx5_ib_event_work {
84 struct work_struct work;
85 struct mlx5_core_dev *dev;
86 void *context;
87 enum mlx5_dev_event event;
88 unsigned long param;
89};
90
da7525d2
EBE		 91enum {
92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
93};
94
d69a24e0 95static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 96static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
97static LIST_HEAD(mlx5_ib_dev_list);
98/*
99 * This mutex should be held when accessing either of the above lists
100 */
101static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
102
c44ef998
IL		 103/* We can't use an array for xlt_emergency_page because dma_map_single
104 * doesn't work on kernel modules memory
105 */
106static unsigned long xlt_emergency_page;
107static struct mutex xlt_emergency_page_mutex;
108
32f69e4b
DJ		 109struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
110{
111 struct mlx5_ib_dev *dev;
112
113 mutex_lock(&mlx5_ib_multiport_mutex);
114 dev = mpi->ibdev;
115 mutex_unlock(&mlx5_ib_multiport_mutex);
116 return dev;
117}
118
1b5daf11 119static enum rdma_link_layer
ebd61f68 120mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 121{
ebd61f68 122 switch (port_type_cap) {
1b5daf11
MD		 123 case MLX5_CAP_PORT_TYPE_IB:
124 return IB_LINK_LAYER_INFINIBAND;
125 case MLX5_CAP_PORT_TYPE_ETH:
126 return IB_LINK_LAYER_ETHERNET;
127 default:
128 return IB_LINK_LAYER_UNSPECIFIED;
129 }
130}
131
ebd61f68
AS		 132static enum rdma_link_layer
133mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
134{
135 struct mlx5_ib_dev *dev = to_mdev(device);
136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
137
138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
139}
140
fd65f1b8
MS		 141static int get_port_state(struct ib_device *ibdev,
142 u8 port_num,
143 enum ib_port_state *state)
144{
145 struct ib_port_attr attr;
146 int ret;
147
148 memset(&attr, 0, sizeof(attr));
8e6efa3a 149 ret = ibdev->query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 150 if (!ret)
151 *state = attr.state;
152 return ret;
153}
154
fc24fc5e
AS		 155static int mlx5_netdev_event(struct notifier_block *this,
156 unsigned long event, void *ptr)
157{
7fd8aefb 158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 160 u8 port_num = roce->native_port_num;
161 struct mlx5_core_dev *mdev;
162 struct mlx5_ib_dev *ibdev;
163
164 ibdev = roce->dev;
32f69e4b
DJ		 165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
166 if (!mdev)
167 return NOTIFY_DONE;
fc24fc5e 168
5ec8c83e
AH		 169 switch (event) {
170 case NETDEV_REGISTER:
171 case NETDEV_UNREGISTER:
7fd8aefb 172 write_lock(&roce->netdev_lock);
bcf87f1d
MB		 173 if (ibdev->rep) {
174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
175 struct net_device *rep_ndev;
176
177 rep_ndev = mlx5_ib_get_rep_netdev(esw,
178 ibdev->rep->vport);
179 if (rep_ndev == ndev)
180 roce->netdev = (event == NETDEV_UNREGISTER) ?
7fd8aefb 181 NULL : ndev;
84a6a7a9 182 } else if (ndev->dev.parent == &mdev->pdev->dev) {
bcf87f1d
MB		 183 roce->netdev = (event == NETDEV_UNREGISTER) ?
184 NULL : ndev;
185 }
7fd8aefb 186 write_unlock(&roce->netdev_lock);
5ec8c83e 187 break;
fc24fc5e 188
fd65f1b8 189 case NETDEV_CHANGE:
5ec8c83e 190 case NETDEV_UP:
88621dfe 191 case NETDEV_DOWN: {
7fd8aefb 192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 193 struct net_device *upper = NULL;
194
195 if (lag_ndev) {
196 upper = netdev_master_upper_dev_get(lag_ndev);
197 dev_put(lag_ndev);
198 }
199
7fd8aefb 200 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 201 && ibdev->ib_active) {
626bc02d 202 struct ib_event ibev = { };
fd65f1b8 203 enum ib_port_state port_state;
5ec8c83e 204
7fd8aefb
DJ		 205 if (get_port_state(&ibdev->ib_dev, port_num,
206 &port_state))
207 goto done;
fd65f1b8 208
7fd8aefb
DJ		 209 if (roce->last_port_state == port_state)
210 goto done;
fd65f1b8 211
7fd8aefb 212 roce->last_port_state = port_state;
5ec8c83e 213 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 214 if (port_state == IB_PORT_DOWN)
215 ibev.event = IB_EVENT_PORT_ERR;
216 else if (port_state == IB_PORT_ACTIVE)
217 ibev.event = IB_EVENT_PORT_ACTIVE;
218 else
7fd8aefb 219 goto done;
fd65f1b8 220
7fd8aefb 221 ibev.element.port_num = port_num;
5ec8c83e
AH		 222 ib_dispatch_event(&ibev);
223 }
224 break;
88621dfe 225 }
fc24fc5e 226
5ec8c83e
AH		 227 default:
228 break;
229 }
7fd8aefb 230done:
32f69e4b 231 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 232 return NOTIFY_DONE;
233}
234
235static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
236 u8 port_num)
237{
238 struct mlx5_ib_dev *ibdev = to_mdev(device);
239 struct net_device *ndev;
32f69e4b
DJ		 240 struct mlx5_core_dev *mdev;
241
242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
243 if (!mdev)
244 return NULL;
fc24fc5e 245
32f69e4b 246 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 247 if (ndev)
32f69e4b 248 goto out;
88621dfe 249
fc24fc5e
AS		 250 /* Ensure ndev does not disappear before we invoke dev_hold()
251 */
7fd8aefb
DJ		 252 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
253 ndev = ibdev->roce[port_num - 1].netdev;
fc24fc5e
AS		 254 if (ndev)
255 dev_hold(ndev);
7fd8aefb 256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
fc24fc5e 257
32f69e4b
DJ		 258out:
259 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 260 return ndev;
261}
262
32f69e4b
DJ		 263struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
264 u8 ib_port_num,
265 u8 *native_port_num)
266{
267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
268 ib_port_num);
269 struct mlx5_core_dev *mdev = NULL;
270 struct mlx5_ib_multiport_info *mpi;
271 struct mlx5_ib_port *port;
272
210b1f78
MB		 273 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
274 ll != IB_LINK_LAYER_ETHERNET) {
275 if (native_port_num)
276 *native_port_num = ib_port_num;
277 return ibdev->mdev;
278 }
279
32f69e4b
DJ		 280 if (native_port_num)
281 *native_port_num = 1;
282
32f69e4b
DJ		 283 port = &ibdev->port[ib_port_num - 1];
284 if (!port)
285 return NULL;
286
287 spin_lock(&port->mp.mpi_lock);
288 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
289 if (mpi && !mpi->unaffiliate) {
290 mdev = mpi->mdev;
291 /* If it's the master no need to refcount, it'll exist
292 * as long as the ib_dev exists.
293 */
294 if (!mpi->is_master)
295 mpi->mdev_refcnt++;
296 }
297 spin_unlock(&port->mp.mpi_lock);
298
299 return mdev;
300}
301
302void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
303{
304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
305 port_num);
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
310 return;
311
312 port = &ibdev->port[port_num - 1];
313
314 spin_lock(&port->mp.mpi_lock);
315 mpi = ibdev->port[port_num - 1].mp.mpi;
316 if (mpi->is_master)
317 goto out;
318
319 mpi->mdev_refcnt--;
320 if (mpi->unaffiliate)
321 complete(&mpi->unref_comp);
322out:
323 spin_unlock(&port->mp.mpi_lock);
324}
325
f1b65df5
NO		 326static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
327 u8 *active_width)
328{
329 switch (eth_proto_oper) {
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
334 *active_width = IB_WIDTH_1X;
335 *active_speed = IB_SPEED_SDR;
336 break;
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
344 *active_width = IB_WIDTH_1X;
345 *active_speed = IB_SPEED_QDR;
346 break;
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
350 *active_width = IB_WIDTH_1X;
351 *active_speed = IB_SPEED_EDR;
352 break;
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
357 *active_width = IB_WIDTH_4X;
358 *active_speed = IB_SPEED_QDR;
359 break;
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
363 *active_width = IB_WIDTH_1X;
364 *active_speed = IB_SPEED_HDR;
365 break;
366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
367 *active_width = IB_WIDTH_4X;
368 *active_speed = IB_SPEED_FDR;
369 break;
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
374 *active_width = IB_WIDTH_4X;
375 *active_speed = IB_SPEED_EDR;
376 break;
377 default:
378 return -EINVAL;
379 }
380
381 return 0;
382}
383
095b0927
IT		 384static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
385 struct ib_port_attr *props)
3f89a643
AS		 386{
387 struct mlx5_ib_dev *dev = to_mdev(device);
da005f9f 388 struct mlx5_core_dev *mdev;
88621dfe 389 struct net_device *ndev, *upper;
3f89a643 390 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 391 bool put_mdev = true;
c876a1b7 392 u16 qkey_viol_cntr;
f1b65df5 393 u32 eth_prot_oper;
b3cbd6f0 394 u8 mdev_port_num;
095b0927 395 int err;
3f89a643 396
b3cbd6f0
DJ		 397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
398 if (!mdev) {
399 /* This means the port isn't affiliated yet. Get the
400 * info for the master port instead.
401 */
402 put_mdev = false;
403 mdev = dev->mdev;
404 mdev_port_num = 1;
405 port_num = 1;
406 }
407
f1b65df5
NO		 408 /* Possible bad flows are checked before filling out props so in case
409 * of an error it will still be zeroed out.
50f22fd8 410 */
b3cbd6f0
DJ		 411 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
412 mdev_port_num);
095b0927 413 if (err)
b3cbd6f0 414 goto out;
f1b65df5 415
7672ed33
HL		 416 props->active_width = IB_WIDTH_4X;
417 props->active_speed = IB_SPEED_QDR;
418
f1b65df5
NO		 419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
420 &props->active_width);
3f89a643 421
2f944c0f
JG		 422 props->port_cap_flags |= IB_PORT_CM_SUP;
423 props->ip_gids = true;
3f89a643
AS		 424
425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
426 roce_address_table_size);
427 props->max_mtu = IB_MTU_4096;
428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
429 props->pkey_tbl_len = 1;
430 props->state = IB_PORT_DOWN;
431 props->phys_state = 3;
432
b3cbd6f0 433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 434 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 435
b3cbd6f0
DJ		 436 /* If this is a stub query for an unaffiliated port stop here */
437 if (!put_mdev)
438 goto out;
439
3f89a643
AS		 440 ndev = mlx5_ib_get_netdev(device, port_num);
441 if (!ndev)
b3cbd6f0 442 goto out;
3f89a643 443
88621dfe
AH		 444 if (mlx5_lag_is_active(dev->mdev)) {
445 rcu_read_lock();
446 upper = netdev_master_upper_dev_get_rcu(ndev);
447 if (upper) {
448 dev_put(ndev);
449 ndev = upper;
450 dev_hold(ndev);
451 }
452 rcu_read_unlock();
453 }
454
3f89a643
AS		 455 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
456 props->state = IB_PORT_ACTIVE;
457 props->phys_state = 5;
458 }
459
460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
461
462 dev_put(ndev);
463
464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 465out:
466 if (put_mdev)
467 mlx5_ib_put_native_port_mdev(dev, port_num);
468 return err;
3f89a643
AS		 469}
470
095b0927
IT		 471static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
472 unsigned int index, const union ib_gid *gid,
473 const struct ib_gid_attr *attr)
3cca2606 474{
095b0927
IT		 475 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
476 u8 roce_version = 0;
477 u8 roce_l3_type = 0;
478 bool vlan = false;
479 u8 mac[ETH_ALEN];
480 u16 vlan_id = 0;
481
482 if (gid) {
483 gid_type = attr->gid_type;
484 ether_addr_copy(mac, attr->ndev->dev_addr);
485
486 if (is_vlan_dev(attr->ndev)) {
487 vlan = true;
488 vlan_id = vlan_dev_vlan_id(attr->ndev);
489 }
3cca2606
AS		 490 }
491
095b0927 492 switch (gid_type) {
3cca2606 493 case IB_GID_TYPE_IB:
095b0927 494 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 495 break;
496 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 497 roce_version = MLX5_ROCE_VERSION_2;
498 if (ipv6_addr_v4mapped((void *)gid))
499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
500 else
501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 502 break;
503
504 default:
095b0927 505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 506 }
507
095b0927
IT		 508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
509 roce_l3_type, gid->raw, mac, vlan,
cfe4e37f 510 vlan_id, port_num);
3cca2606
AS		 511}
512
f4df9a7c 513static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 514 __always_unused void **context)
515{
414448d2 516 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 517 attr->index, &attr->gid, attr);
3cca2606
AS		 518}
519
414448d2
PP		 520static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
521 __always_unused void **context)
3cca2606 522{
414448d2
PP		 523 return set_roce_addr(to_mdev(attr->device), attr->port_num,
524 attr->index, NULL, NULL);
3cca2606
AS		 525}
526
47ec3866
PP		 527__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
528 const struct ib_gid_attr *attr)
2811ba51 529{
47ec3866 530 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 531 return 0;
532
533 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
534}
535
1b5daf11
MD		 536static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
537{
7fae6655
NO		 538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
539 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
540 return 0;
1b5daf11
MD		 541}
542
543enum {
544 MLX5_VPORT_ACCESS_METHOD_MAD,
545 MLX5_VPORT_ACCESS_METHOD_HCA,
546 MLX5_VPORT_ACCESS_METHOD_NIC,
547};
548
549static int mlx5_get_vport_access_method(struct ib_device *ibdev)
550{
551 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
552 return MLX5_VPORT_ACCESS_METHOD_MAD;
553
ebd61f68 554 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 555 IB_LINK_LAYER_ETHERNET)
556 return MLX5_VPORT_ACCESS_METHOD_NIC;
557
558 return MLX5_VPORT_ACCESS_METHOD_HCA;
559}
560
da7525d2 561static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 562 u8 atomic_size_qp,
da7525d2
EBE		 563 struct ib_device_attr *props)
564{
565 u8 tmp;
566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 567 u8 atomic_req_8B_endianness_mode =
bd10838a 568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 569
570 /* Check if HW supports 8 bytes standard atomic operations and capable
571 * of host endianness respond
572 */
573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
574 if (((atomic_operations & tmp) == tmp) &&
575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
576 (atomic_req_8B_endianness_mode)) {
577 props->atomic_cap = IB_ATOMIC_HCA;
578 } else {
579 props->atomic_cap = IB_ATOMIC_NONE;
580 }
581}
582
776a3906
MS		 583static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
584 struct ib_device_attr *props)
585{
586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
587
588 get_atomic_caps(dev, atomic_size_qp, props);
589}
590
591static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
592 struct ib_device_attr *props)
593{
594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
595
596 get_atomic_caps(dev, atomic_size_qp, props);
597}
598
599bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
600{
601 struct ib_device_attr props = {};
602
603 get_atomic_caps_dc(dev, &props);
604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
605}
1b5daf11
MD		 606static int mlx5_query_system_image_guid(struct ib_device *ibdev,
607 __be64 *sys_image_guid)
608{
609 struct mlx5_ib_dev *dev = to_mdev(ibdev);
610 struct mlx5_core_dev *mdev = dev->mdev;
611 u64 tmp;
612 int err;
613
614 switch (mlx5_get_vport_access_method(ibdev)) {
615 case MLX5_VPORT_ACCESS_METHOD_MAD:
616 return mlx5_query_mad_ifc_system_image_guid(ibdev,
617 sys_image_guid);
618
619 case MLX5_VPORT_ACCESS_METHOD_HCA:
620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 621 break;
622
623 case MLX5_VPORT_ACCESS_METHOD_NIC:
624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
625 break;
1b5daf11
MD		 626
627 default:
628 return -EINVAL;
629 }
3f89a643
AS		 630
631 if (!err)
632 *sys_image_guid = cpu_to_be64(tmp);
633
634 return err;
635
1b5daf11
MD		 636}
637
638static int mlx5_query_max_pkeys(struct ib_device *ibdev,
639 u16 *max_pkeys)
640{
641 struct mlx5_ib_dev *dev = to_mdev(ibdev);
642 struct mlx5_core_dev *mdev = dev->mdev;
643
644 switch (mlx5_get_vport_access_method(ibdev)) {
645 case MLX5_VPORT_ACCESS_METHOD_MAD:
646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
647
648 case MLX5_VPORT_ACCESS_METHOD_HCA:
649 case MLX5_VPORT_ACCESS_METHOD_NIC:
650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
651 pkey_table_size));
652 return 0;
653
654 default:
655 return -EINVAL;
656 }
657}
658
659static int mlx5_query_vendor_id(struct ib_device *ibdev,
660 u32 *vendor_id)
661{
662 struct mlx5_ib_dev *dev = to_mdev(ibdev);
663
664 switch (mlx5_get_vport_access_method(ibdev)) {
665 case MLX5_VPORT_ACCESS_METHOD_MAD:
666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
667
668 case MLX5_VPORT_ACCESS_METHOD_HCA:
669 case MLX5_VPORT_ACCESS_METHOD_NIC:
670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
671
672 default:
673 return -EINVAL;
674 }
675}
676
677static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
678 __be64 *node_guid)
679{
680 u64 tmp;
681 int err;
682
683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
684 case MLX5_VPORT_ACCESS_METHOD_MAD:
685 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
686
687 case MLX5_VPORT_ACCESS_METHOD_HCA:
688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 689 break;
690
691 case MLX5_VPORT_ACCESS_METHOD_NIC:
692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
693 break;
1b5daf11
MD		 694
695 default:
696 return -EINVAL;
697 }
3f89a643
AS		 698
699 if (!err)
700 *node_guid = cpu_to_be64(tmp);
701
702 return err;
1b5daf11
MD		 703}
704
705struct mlx5_reg_node_desc {
bd99fdea 706 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 707};
708
709static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
710{
711 struct mlx5_reg_node_desc in;
712
713 if (mlx5_use_mad_ifc(dev))
714 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
715
716 memset(&in, 0, sizeof(in));
717
718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
719 sizeof(struct mlx5_reg_node_desc),
720 MLX5_REG_NODE_DESC, 0, 0);
721}
722
e126ba97 723static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 724 struct ib_device_attr *props,
725 struct ib_udata *uhw)
e126ba97
EC		 726{
727 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 728 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 729 int err = -ENOMEM;
288c01b7 730 int max_sq_desc;
e126ba97
EC		 731 int max_rq_sg;
732 int max_sq_sg;
e0238a6a 733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 734 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 735 struct mlx5_ib_query_device_resp resp = {};
736 size_t resp_len;
737 u64 max_tso;
e126ba97 738
402ca536
BW		 739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
740 if (uhw->outlen && uhw->outlen < resp_len)
741 return -EINVAL;
742 else
743 resp.response_length = resp_len;
744
745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 746 return -EINVAL;
747
1b5daf11
MD		 748 memset(props, 0, sizeof(*props));
749 err = mlx5_query_system_image_guid(ibdev,
750 &props->sys_image_guid);
751 if (err)
752 return err;
e126ba97 753
1b5daf11 754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 755 if (err)
1b5daf11 756 return err;
e126ba97 757
1b5daf11
MD		 758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
759 if (err)
760 return err;
e126ba97 761
9603b61d
JM		 762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
763 (fw_rev_min(dev->mdev) << 16) |
764 fw_rev_sub(dev->mdev);
e126ba97
EC		 765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
766 IB_DEVICE_PORT_ACTIVE_EVENT |
767 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 768 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 769
770 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 772 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 774 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 776 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 777 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 778 if (MLX5_CAP_GEN(mdev, imaicl)) {
779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
780 IB_DEVICE_MEM_WINDOW_TYPE_2B;
781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 782 /* We support 'Gappy' memory registration too */
783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 784 }
e126ba97 785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 786 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
788 /* At this stage no support for signature handover */
789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
790 IB_PROT_T10DIF_TYPE_2 |
791 IB_PROT_T10DIF_TYPE_3;
792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
793 IB_GUARD_T10DIF_CSUM;
794 }
938fe83c 795 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 797
85c7c014 798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 799 if (MLX5_CAP_ETH(mdev, csum_cap)) {
800 /* Legacy bit to support old userspace libraries */
88115fe7 801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
803 }
804
805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
806 props->raw_packet_caps |=
807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 808
402ca536
BW		 809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
811 if (max_tso) {
812 resp.tso_caps.max_tso = 1 << max_tso;
813 resp.tso_caps.supported_qpts |=
814 1 << IB_QPT_RAW_PACKET;
815 resp.response_length += sizeof(resp.tso_caps);
816 }
817 }
31f69a82
YH		 818
819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
820 resp.rss_caps.rx_hash_function =
821 MLX5_RX_HASH_FUNC_TOEPLITZ;
822 resp.rss_caps.rx_hash_fields_mask =
823 MLX5_RX_HASH_SRC_IPV4 |
824 MLX5_RX_HASH_DST_IPV4 |
825 MLX5_RX_HASH_SRC_IPV6 |
826 MLX5_RX_HASH_DST_IPV6 |
827 MLX5_RX_HASH_SRC_PORT_TCP |
828 MLX5_RX_HASH_DST_PORT_TCP |
829 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 830 MLX5_RX_HASH_DST_PORT_UDP |
831 MLX5_RX_HASH_INNER;
2d93fc85
MB		 832 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
833 MLX5_ACCEL_IPSEC_CAP_DEVICE)
834 resp.rss_caps.rx_hash_fields_mask |=
835 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 836 resp.response_length += sizeof(resp.rss_caps);
837 }
838 } else {
839 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
840 resp.response_length += sizeof(resp.tso_caps);
841 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
842 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 843 }
844
f0313965
ES		 845 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
846 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
847 props->device_cap_flags |= IB_DEVICE_UD_TSO;
848 }
849
03404e8a 850 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 851 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
852 raw_support)
03404e8a
MG		 853 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
854
1d54f890
YH		 855 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
856 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
858
cff5a0f3 859 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 860 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
861 raw_support) {
e8161334 862 /* Legacy bit to support old userspace libraries */
cff5a0f3 863 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
865 }
cff5a0f3 866
24da0016
AL		 867 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
868 props->max_dm_size =
869 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
870 }
871
da6d6ba3
MG		 872 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
873 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
874
b1383aa6
NO		 875 if (MLX5_CAP_GEN(mdev, end_pad))
876 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
877
1b5daf11
MD		 878 props->vendor_part_id = mdev->pdev->device;
879 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 880
881 props->max_mr_size = ~0ull;
e0238a6a 882 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 883 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
884 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
885 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
886 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 887 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
888 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
889 sizeof(struct mlx5_wqe_raddr_seg)) /
890 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 891 props->max_send_sge = max_sq_sg;
892 props->max_recv_sge = max_rq_sg;
986ef95e 893 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 894 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 895 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 896 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
897 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
898 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
899 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
900 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
901 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
902 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 903 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 904 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 905 props->max_fast_reg_page_list_len =
906 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 907 get_atomic_caps_qp(dev, props);
81bea28f 908 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 909 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
910 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 911 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
912 props->max_mcast_grp;
913 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 914 props->max_ah = INT_MAX;
7c60bcbb
MB		 915 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
916 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 917
8cdd312c 918#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 919 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 920 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
921 props->odp_caps = dev->odp_caps;
922#endif
923
051f2630
LR		 924 if (MLX5_CAP_GEN(mdev, cd))
925 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
926
eff901d3
EC		 927 if (!mlx5_core_is_pf(mdev))
928 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
929
31f69a82 930 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 931 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 932 props->rss_caps.max_rwq_indirection_tables =
933 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
934 props->rss_caps.max_rwq_indirection_table_size =
935 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
936 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
937 props->max_wq_type_rq =
938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
939 }
940
eb761894 941 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 942 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
943 props->tm_caps.max_num_tags =
eb761894 944 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 945 props->tm_caps.flags = IB_TM_CAP_RC;
946 props->tm_caps.max_ops =
eb761894 947 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 948 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 949 }
950
87ab3f52
YC		 951 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
952 props->cq_caps.max_cq_moderation_count =
953 MLX5_MAX_CQ_COUNT;
954 props->cq_caps.max_cq_moderation_period =
955 MLX5_MAX_CQ_PERIOD;
956 }
957
7e43a2a5 958 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
7e43a2a5 959 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 960
961 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
962 resp.cqe_comp_caps.max_num =
963 MLX5_CAP_GEN(dev->mdev,
964 cqe_compression_max_num);
965
966 resp.cqe_comp_caps.supported_format =
967 MLX5_IB_CQE_RES_FORMAT_HASH |
968 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 969
970 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
971 resp.cqe_comp_caps.supported_format |=
972 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 973 }
7e43a2a5
BW		 974 }
975
85c7c014
DJ		 976 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
977 raw_support) {
d949167d
BW		 978 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
979 MLX5_CAP_GEN(mdev, qos)) {
980 resp.packet_pacing_caps.qp_rate_limit_max =
981 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
982 resp.packet_pacing_caps.qp_rate_limit_min =
983 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
984 resp.packet_pacing_caps.supported_qpts |=
985 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 986 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
987 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
988 resp.packet_pacing_caps.cap_flags |=
989 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 990 }
991 resp.response_length += sizeof(resp.packet_pacing_caps);
992 }
993
9f885201
LR		 994 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
995 uhw->outlen)) {
795b609c
BW		 996 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
997 resp.mlx5_ib_support_multi_pkt_send_wqes =
998 MLX5_IB_ALLOW_MPW;
050da902
BW		 999
1000 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1001 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1002 MLX5_IB_SUPPORT_EMPW;
1003
9f885201
LR		 1004 resp.response_length +=
1005 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1006 }
1007
de57f2ad
GL		 1008 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1009 resp.response_length += sizeof(resp.flags);
7a0c8f42 1010
de57f2ad
GL		 1011 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1012 resp.flags |=
1013 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1014
1015 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1016 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
de57f2ad 1017 }
9f885201 1018
96dc3fc5
NO		 1019 if (field_avail(typeof(resp), sw_parsing_caps,
1020 uhw->outlen)) {
1021 resp.response_length += sizeof(resp.sw_parsing_caps);
1022 if (MLX5_CAP_ETH(mdev, swp)) {
1023 resp.sw_parsing_caps.sw_parsing_offloads |=
1024 MLX5_IB_SW_PARSING;
1025
1026 if (MLX5_CAP_ETH(mdev, swp_csum))
1027 resp.sw_parsing_caps.sw_parsing_offloads |=
1028 MLX5_IB_SW_PARSING_CSUM;
1029
1030 if (MLX5_CAP_ETH(mdev, swp_lso))
1031 resp.sw_parsing_caps.sw_parsing_offloads |=
1032 MLX5_IB_SW_PARSING_LSO;
1033
1034 if (resp.sw_parsing_caps.sw_parsing_offloads)
1035 resp.sw_parsing_caps.supported_qpts =
1036 BIT(IB_QPT_RAW_PACKET);
1037 }
1038 }
1039
85c7c014
DJ		 1040 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1041 raw_support) {
b4f34597
NO		 1042 resp.response_length += sizeof(resp.striding_rq_caps);
1043 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1044 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1045 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1046 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1047 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1048 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1049 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1050 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1051 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1052 resp.striding_rq_caps.supported_qpts =
1053 BIT(IB_QPT_RAW_PACKET);
1054 }
1055 }
1056
f95ef6cb
MG		 1057 if (field_avail(typeof(resp), tunnel_offloads_caps,
1058 uhw->outlen)) {
1059 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1060 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1061 resp.tunnel_offloads_caps |=
1062 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1063 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1064 resp.tunnel_offloads_caps |=
1065 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1066 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1067 resp.tunnel_offloads_caps |=
1068 MLX5_IB_TUNNELED_OFFLOADS_GRE;
e818e255
AL		 1069 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1070 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1071 resp.tunnel_offloads_caps |=
1072 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1073 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1074 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1075 resp.tunnel_offloads_caps |=
1076 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1077 }
1078
402ca536
BW		 1079 if (uhw->outlen) {
1080 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1081
1082 if (err)
1083 return err;
1084 }
1085
1b5daf11 1086 return 0;
e126ba97
EC		 1087}
1088
1b5daf11
MD		 1089enum mlx5_ib_width {
1090 MLX5_IB_WIDTH_1X = 1 << 0,
1091 MLX5_IB_WIDTH_2X = 1 << 1,
1092 MLX5_IB_WIDTH_4X = 1 << 2,
1093 MLX5_IB_WIDTH_8X = 1 << 3,
1094 MLX5_IB_WIDTH_12X = 1 << 4
1095};
1096
1097static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1098 u8 *ib_width)
e126ba97
EC		 1099{
1100 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 1101 int err = 0;
1102
1103 if (active_width & MLX5_IB_WIDTH_1X) {
1104 *ib_width = IB_WIDTH_1X;
1105 } else if (active_width & MLX5_IB_WIDTH_2X) {
1106 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1107 (int)active_width);
1108 err = -EINVAL;
1109 } else if (active_width & MLX5_IB_WIDTH_4X) {
1110 *ib_width = IB_WIDTH_4X;
1111 } else if (active_width & MLX5_IB_WIDTH_8X) {
1112 *ib_width = IB_WIDTH_8X;
1113 } else if (active_width & MLX5_IB_WIDTH_12X) {
1114 *ib_width = IB_WIDTH_12X;
1115 } else {
1116 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1117 (int)active_width);
1118 err = -EINVAL;
e126ba97
EC		 1119 }
1120
1b5daf11
MD		 1121 return err;
1122}
e126ba97 1123
1b5daf11
MD		 1124static int mlx5_mtu_to_ib_mtu(int mtu)
1125{
1126 switch (mtu) {
1127 case 256: return 1;
1128 case 512: return 2;
1129 case 1024: return 3;
1130 case 2048: return 4;
1131 case 4096: return 5;
1132 default:
1133 pr_warn("invalid mtu\n");
1134 return -1;
e126ba97 1135 }
1b5daf11 1136}
e126ba97 1137
1b5daf11
MD		 1138enum ib_max_vl_num {
1139 __IB_MAX_VL_0 = 1,
1140 __IB_MAX_VL_0_1 = 2,
1141 __IB_MAX_VL_0_3 = 3,
1142 __IB_MAX_VL_0_7 = 4,
1143 __IB_MAX_VL_0_14 = 5,
1144};
e126ba97 1145
1b5daf11
MD		 1146enum mlx5_vl_hw_cap {
1147 MLX5_VL_HW_0 = 1,
1148 MLX5_VL_HW_0_1 = 2,
1149 MLX5_VL_HW_0_2 = 3,
1150 MLX5_VL_HW_0_3 = 4,
1151 MLX5_VL_HW_0_4 = 5,
1152 MLX5_VL_HW_0_5 = 6,
1153 MLX5_VL_HW_0_6 = 7,
1154 MLX5_VL_HW_0_7 = 8,
1155 MLX5_VL_HW_0_14 = 15
1156};
e126ba97 1157
1b5daf11
MD		 1158static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1159 u8 *max_vl_num)
1160{
1161 switch (vl_hw_cap) {
1162 case MLX5_VL_HW_0:
1163 *max_vl_num = __IB_MAX_VL_0;
1164 break;
1165 case MLX5_VL_HW_0_1:
1166 *max_vl_num = __IB_MAX_VL_0_1;
1167 break;
1168 case MLX5_VL_HW_0_3:
1169 *max_vl_num = __IB_MAX_VL_0_3;
1170 break;
1171 case MLX5_VL_HW_0_7:
1172 *max_vl_num = __IB_MAX_VL_0_7;
1173 break;
1174 case MLX5_VL_HW_0_14:
1175 *max_vl_num = __IB_MAX_VL_0_14;
1176 break;
e126ba97 1177
1b5daf11
MD		 1178 default:
1179 return -EINVAL;
e126ba97 1180 }
e126ba97 1181
1b5daf11 1182 return 0;
e126ba97
EC		 1183}
1184
1b5daf11
MD		 1185static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1186 struct ib_port_attr *props)
e126ba97 1187{
1b5daf11
MD		 1188 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1189 struct mlx5_core_dev *mdev = dev->mdev;
1190 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1191 u16 max_mtu;
1192 u16 oper_mtu;
1b5daf11
MD		 1193 int err;
1194 u8 ib_link_width_oper;
1195 u8 vl_hw_cap;
e126ba97 1196
1b5daf11
MD		 1197 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1198 if (!rep) {
1199 err = -ENOMEM;
e126ba97 1200 goto out;
e126ba97 1201 }
e126ba97 1202
c4550c63 1203 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1204
1b5daf11 1205 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1206 if (err)
1207 goto out;
1208
1b5daf11
MD		 1209 props->lid = rep->lid;
1210 props->lmc = rep->lmc;
1211 props->sm_lid = rep->sm_lid;
1212 props->sm_sl = rep->sm_sl;
1213 props->state = rep->vport_state;
1214 props->phys_state = rep->port_physical_state;
1215 props->port_cap_flags = rep->cap_mask1;
1216 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1217 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1218 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1219 props->bad_pkey_cntr = rep->pkey_violation_counter;
1220 props->qkey_viol_cntr = rep->qkey_violation_counter;
1221 props->subnet_timeout = rep->subnet_timeout;
1222 props->init_type_reply = rep->init_type_reply;
e126ba97 1223
1b5daf11
MD		 1224 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1225 if (err)
e126ba97 1226 goto out;
e126ba97 1227
1b5daf11
MD		 1228 err = translate_active_width(ibdev, ib_link_width_oper,
1229 &props->active_width);
1230 if (err)
1231 goto out;
d5beb7f2 1232 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1233 if (err)
1234 goto out;
1235
facc9699 1236 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1237
1b5daf11 1238 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1239
facc9699 1240 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1241
1b5daf11 1242 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1243
1b5daf11
MD		 1244 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1245 if (err)
1246 goto out;
e126ba97 1247
1b5daf11
MD		 1248 err = translate_max_vl_num(ibdev, vl_hw_cap,
1249 &props->max_vl_num);
e126ba97 1250out:
1b5daf11 1251 kfree(rep);
e126ba97
EC		 1252 return err;
1253}
1254
1b5daf11
MD		 1255int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1256 struct ib_port_attr *props)
e126ba97 1257{
095b0927
IT		 1258 unsigned int count;
1259 int ret;
1260
1b5daf11
MD		 1261 switch (mlx5_get_vport_access_method(ibdev)) {
1262 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1263 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1264 break;
e126ba97 1265
1b5daf11 1266 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1267 ret = mlx5_query_hca_port(ibdev, port, props);
1268 break;
e126ba97 1269
3f89a643 1270 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1271 ret = mlx5_query_port_roce(ibdev, port, props);
1272 break;
3f89a643 1273
1b5daf11 1274 default:
095b0927
IT		 1275 ret = -EINVAL;
1276 }
1277
1278 if (!ret && props) {
b3cbd6f0
DJ		 1279 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1280 struct mlx5_core_dev *mdev;
1281 bool put_mdev = true;
1282
1283 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1284 if (!mdev) {
1285 /* If the port isn't affiliated yet query the master.
1286 * The master and slave will have the same values.
1287 */
1288 mdev = dev->mdev;
1289 port = 1;
1290 put_mdev = false;
1291 }
1292 count = mlx5_core_reserved_gids_count(mdev);
1293 if (put_mdev)
1294 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1295 props->gid_tbl_len -= count;
1b5daf11 1296 }
095b0927 1297 return ret;
1b5daf11 1298}
e126ba97 1299
8e6efa3a
MB		 1300static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1301 struct ib_port_attr *props)
1302{
1303 int ret;
1304
1305 /* Only link layer == ethernet is valid for representors */
1306 ret = mlx5_query_port_roce(ibdev, port, props);
1307 if (ret || !props)
1308 return ret;
1309
1310 /* We don't support GIDS */
1311 props->gid_tbl_len = 0;
1312
1313 return ret;
1314}
1315
1b5daf11
MD		 1316static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1317 union ib_gid *gid)
1318{
1319 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1320 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1321
1b5daf11
MD		 1322 switch (mlx5_get_vport_access_method(ibdev)) {
1323 case MLX5_VPORT_ACCESS_METHOD_MAD:
1324 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1325
1b5daf11
MD		 1326 case MLX5_VPORT_ACCESS_METHOD_HCA:
1327 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1328
1329 default:
1330 return -EINVAL;
1331 }
e126ba97 1332
e126ba97
EC		 1333}
1334
b3cbd6f0
DJ		 1335static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1336 u16 index, u16 *pkey)
1b5daf11
MD		 1337{
1338 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1339 struct mlx5_core_dev *mdev;
1340 bool put_mdev = true;
1341 u8 mdev_port_num;
1342 int err;
1b5daf11 1343
b3cbd6f0
DJ		 1344 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1345 if (!mdev) {
1346 /* The port isn't affiliated yet, get the PKey from the master
1347 * port. For RoCE the PKey tables will be the same.
1348 */
1349 put_mdev = false;
1350 mdev = dev->mdev;
1351 mdev_port_num = 1;
1352 }
1353
1354 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1355 index, pkey);
1356 if (put_mdev)
1357 mlx5_ib_put_native_port_mdev(dev, port);
1358
1359 return err;
1360}
1361
1362static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1363 u16 *pkey)
1364{
1b5daf11
MD		 1365 switch (mlx5_get_vport_access_method(ibdev)) {
1366 case MLX5_VPORT_ACCESS_METHOD_MAD:
1367 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1368
1369 case MLX5_VPORT_ACCESS_METHOD_HCA:
1370 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1371 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1372 default:
1373 return -EINVAL;
1374 }
1375}
e126ba97
EC		 1376
1377static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1378 struct ib_device_modify *props)
1379{
1380 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1381 struct mlx5_reg_node_desc in;
1382 struct mlx5_reg_node_desc out;
1383 int err;
1384
1385 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1386 return -EOPNOTSUPP;
1387
1388 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1389 return 0;
1390
1391 /*
1392 * If possible, pass node desc to FW, so it can generate
1393 * a 144 trap. If cmd fails, just ignore.
1394 */
bd99fdea 1395 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1396 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1397 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1398 if (err)
1399 return err;
1400
bd99fdea 1401 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1402
1403 return err;
1404}
1405
cdbe33d0
EC		 1406static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1407 u32 value)
1408{
1409 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1410 struct mlx5_core_dev *mdev;
1411 u8 mdev_port_num;
cdbe33d0
EC		 1412 int err;
1413
b3cbd6f0
DJ		 1414 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1415 if (!mdev)
1416 return -ENODEV;
1417
1418 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1419 if (err)
b3cbd6f0 1420 goto out;
cdbe33d0
EC		 1421
1422 if (~ctx.cap_mask1_perm & mask) {
1423 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1424 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1425 err = -EINVAL;
1426 goto out;
cdbe33d0
EC		 1427 }
1428
1429 ctx.cap_mask1 = value;
1430 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1431 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1432 0, &ctx);
1433
1434out:
1435 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1436
1437 return err;
1438}
1439
e126ba97
EC		 1440static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1441 struct ib_port_modify *props)
1442{
1443 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1444 struct ib_port_attr attr;
1445 u32 tmp;
1446 int err;
cdbe33d0
EC		 1447 u32 change_mask;
1448 u32 value;
1449 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1450 IB_LINK_LAYER_INFINIBAND);
1451
ec255879
MD		 1452 /* CM layer calls ib_modify_port() regardless of the link layer. For
1453 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1454 */
1455 if (!is_ib)
1456 return 0;
1457
cdbe33d0
EC		 1458 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1459 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1460 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1461 return set_port_caps_atomic(dev, port, change_mask, value);
1462 }
e126ba97
EC		 1463
1464 mutex_lock(&dev->cap_mask_mutex);
1465
c4550c63 1466 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1467 if (err)
1468 goto out;
1469
1470 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1471 ~props->clr_port_cap_mask;
1472
9603b61d 1473 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1474
1475out:
1476 mutex_unlock(&dev->cap_mask_mutex);
1477 return err;
1478}
1479
30aa60b3
EC		 1480static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1481{
1482 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1483 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1484}
1485
31a78a5a
YH		 1486static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1487{
1488 /* Large page with non 4k uar support might limit the dynamic size */
1489 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1490 return MLX5_MIN_DYN_BFREGS;
1491
1492 return MLX5_MAX_DYN_BFREGS;
1493}
1494
b037c29a
EC		 1495static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1496 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1497 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1498{
1499 int uars_per_sys_page;
1500 int bfregs_per_sys_page;
1501 int ref_bfregs = req->total_num_bfregs;
1502
1503 if (req->total_num_bfregs == 0)
1504 return -EINVAL;
1505
1506 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1507 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1508
1509 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1510 return -ENOMEM;
1511
1512 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1513 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1514 /* This holds the required static allocation asked by the user */
b037c29a 1515 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1516 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1517 return -EINVAL;
1518
31a78a5a
YH		 1519 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1520 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1521 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1522 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1523
1524 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1525 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1526 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1527 req->total_num_bfregs, bfregi->total_num_bfregs,
1528 bfregi->num_sys_pages);
b037c29a
EC		 1529
1530 return 0;
1531}
1532
1533static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1534{
1535 struct mlx5_bfreg_info *bfregi;
1536 int err;
1537 int i;
1538
1539 bfregi = &context->bfregi;
31a78a5a 1540 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1541 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1542 if (err)
1543 goto error;
1544
1545 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1546 }
4ed131d0
YH		 1547
1548 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1549 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1550
b037c29a
EC		 1551 return 0;
1552
1553error:
1554 for (--i; i >= 0; i--)
1555 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1556 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1557
1558 return err;
1559}
1560
15177999
LR		 1561static void deallocate_uars(struct mlx5_ib_dev *dev,
1562 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1563{
1564 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1565 int i;
1566
1567 bfregi = &context->bfregi;
15177999 1568 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1569 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1570 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1571 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1572}
1573
c85023e1
HN		 1574static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1575{
1576 int err;
1577
cfdeb893
LR		 1578 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1579 return 0;
1580
c85023e1
HN		 1581 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1582 if (err)
1583 return err;
1584
1585 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1586 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1587 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1588 return err;
1589
1590 mutex_lock(&dev->lb_mutex);
1591 dev->user_td++;
1592
1593 if (dev->user_td == 2)
1594 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1595
1596 mutex_unlock(&dev->lb_mutex);
1597 return err;
1598}
1599
1600static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1601{
cfdeb893
LR		 1602 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1603 return;
1604
c85023e1
HN		 1605 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1606
1607 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1608 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1609 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1610 return;
1611
1612 mutex_lock(&dev->lb_mutex);
1613 dev->user_td--;
1614
1615 if (dev->user_td < 2)
1616 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1617
1618 mutex_unlock(&dev->lb_mutex);
1619}
1620
e126ba97
EC		 1621static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1622 struct ib_udata *udata)
1623{
1624 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1625 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1626 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1627 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1628 struct mlx5_ib_ucontext *context;
2f5ff264 1629 struct mlx5_bfreg_info *bfregi;
78c0f98c 1630 int ver;
e126ba97 1631 int err;
a168a41c
MD		 1632 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1633 max_cqe_version);
25bb36e7 1634 u32 dump_fill_mkey;
b037c29a 1635 bool lib_uar_4k;
e126ba97
EC		 1636
1637 if (!dev->ib_active)
1638 return ERR_PTR(-EAGAIN);
1639
e093111d 1640 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1641 ver = 0;
e093111d 1642 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1643 ver = 2;
1644 else
1645 return ERR_PTR(-EINVAL);
1646
e093111d 1647 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1648 if (err)
1649 return ERR_PTR(err);
1650
a8b92ca1
YH		 1651 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1652 return ERR_PTR(-EOPNOTSUPP);
78c0f98c 1653
f72300c5 1654 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1655 return ERR_PTR(-EOPNOTSUPP);
1656
2f5ff264
EC		 1657 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1658 MLX5_NON_FP_BFREGS_PER_UAR);
1659 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1660 return ERR_PTR(-EINVAL);
1661
938fe83c 1662 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1663 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1664 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1665 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1666 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1667 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1668 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1669 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1670 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1671 resp.cqe_version = min_t(__u8,
1672 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1673 req.max_cqe_version);
30aa60b3
EC		 1674 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1675 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1676 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1677 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1678 resp.response_length = min(offsetof(typeof(resp), response_length) +
1679 sizeof(resp.response_length), udata->outlen);
e126ba97 1680
c03faa56
MB		 1681 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1682 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1683 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1684 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1685 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1686 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1687 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1688 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1689 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1690 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1691 }
1692
e126ba97
EC		 1693 context = kzalloc(sizeof(*context), GFP_KERNEL);
1694 if (!context)
1695 return ERR_PTR(-ENOMEM);
1696
30aa60b3 1697 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1698 bfregi = &context->bfregi;
b037c29a
EC		 1699
1700 /* updates req->total_num_bfregs */
31a78a5a 1701 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1702 if (err)
e126ba97 1703 goto out_ctx;
e126ba97 1704
b037c29a
EC		 1705 mutex_init(&bfregi->lock);
1706 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1707 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1708 GFP_KERNEL);
b037c29a 1709 if (!bfregi->count) {
e126ba97 1710 err = -ENOMEM;
b037c29a 1711 goto out_ctx;
e126ba97
EC		 1712 }
1713
b037c29a
EC		 1714 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1715 sizeof(*bfregi->sys_pages),
1716 GFP_KERNEL);
1717 if (!bfregi->sys_pages) {
e126ba97 1718 err = -ENOMEM;
b037c29a 1719 goto out_count;
e126ba97
EC		 1720 }
1721
b037c29a
EC		 1722 err = allocate_uars(dev, context);
1723 if (err)
1724 goto out_sys_pages;
e126ba97 1725
b4cfe447
HE		 1726#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1727 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1728#endif
1729
cfdeb893
LR		 1730 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1731 if (err)
1732 goto out_uars;
146d2f1a 1733
a8b92ca1
YH		 1734 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1735 /* Block DEVX on Infiniband as of SELinux */
1736 if (mlx5_ib_port_link_layer(ibdev, 1) != IB_LINK_LAYER_ETHERNET) {
1737 err = -EPERM;
1738 goto out_td;
1739 }
1740
1741 err = mlx5_ib_devx_create(dev, context);
1742 if (err)
1743 goto out_td;
1744 }
1745
25bb36e7
YC		 1746 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1747 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1748 if (err)
8193abb6 1749 goto out_mdev;
25bb36e7
YC		 1750 }
1751
7c2344c3 1752 INIT_LIST_HEAD(&context->vma_private_list);
ad9a3668 1753 mutex_init(&context->vma_private_list_mutex);
e126ba97
EC		 1754 INIT_LIST_HEAD(&context->db_page_list);
1755 mutex_init(&context->db_page_mutex);
1756
2f5ff264 1757 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1758 resp.num_ports = dev->num_ports;
b368d7cb 1759
f72300c5
HA		 1760 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1761 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1762
402ca536 1763 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1764 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1765 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1766 resp.response_length += sizeof(resp.cmds_supp_uhw);
1767 }
1768
78984898
OG		 1769 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1770 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1771 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1772 resp.eth_min_inline++;
1773 }
1774 resp.response_length += sizeof(resp.eth_min_inline);
1775 }
1776
5c99eaec
FD		 1777 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1778 if (mdev->clock_info)
1779 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1780 resp.response_length += sizeof(resp.clock_info_versions);
1781 }
1782
bc5c6eed
NO		 1783 /*
1784 * We don't want to expose information from the PCI bar that is located
1785 * after 4096 bytes, so if the arch only supports larger pages, let's
1786 * pretend we don't support reading the HCA's core clock. This is also
1787 * forced by mmap function.
1788 */
de8d6e02
EC		 1789 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1790 if (PAGE_SIZE <= 4096) {
1791 resp.comp_mask |=
1792 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1793 resp.hca_core_clock_offset =
1794 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1795 }
5c99eaec 1796 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1797 }
1798
30aa60b3
EC		 1799 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1800 resp.response_length += sizeof(resp.log_uar_size);
1801
1802 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1803 resp.response_length += sizeof(resp.num_uars_per_page);
1804
31a78a5a
YH		 1805 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1806 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1807 resp.response_length += sizeof(resp.num_dyn_bfregs);
1808 }
1809
25bb36e7
YC		 1810 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1811 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1812 resp.dump_fill_mkey = dump_fill_mkey;
1813 resp.comp_mask |=
1814 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1815 }
1816 resp.response_length += sizeof(resp.dump_fill_mkey);
1817 }
1818
b368d7cb 1819 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1820 if (err)
a8b92ca1 1821 goto out_mdev;
e126ba97 1822
2f5ff264
EC		 1823 bfregi->ver = ver;
1824 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1825 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1826 context->lib_caps = req.lib_caps;
1827 print_lib_caps(dev, context->lib_caps);
f72300c5 1828
e126ba97
EC		 1829 return &context->ibucontext;
1830
a8b92ca1
YH		 1831out_mdev:
1832 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1833 mlx5_ib_devx_destroy(dev, context);
146d2f1a 1834out_td:
cfdeb893 1835 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1836
e126ba97 1837out_uars:
b037c29a 1838 deallocate_uars(dev, context);
e126ba97 1839
b037c29a
EC		 1840out_sys_pages:
1841 kfree(bfregi->sys_pages);
e126ba97 1842
b037c29a
EC		 1843out_count:
1844 kfree(bfregi->count);
e126ba97
EC		 1845
1846out_ctx:
1847 kfree(context);
b037c29a 1848
e126ba97
EC		 1849 return ERR_PTR(err);
1850}
1851
1852static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1853{
1854 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1855 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1856 struct mlx5_bfreg_info *bfregi;
e126ba97 1857
a8b92ca1
YH		 1858 if (context->devx_uid)
1859 mlx5_ib_devx_destroy(dev, context);
1860
b037c29a 1861 bfregi = &context->bfregi;
cfdeb893 1862 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1863
b037c29a
EC		 1864 deallocate_uars(dev, context);
1865 kfree(bfregi->sys_pages);
2f5ff264 1866 kfree(bfregi->count);
e126ba97
EC		 1867 kfree(context);
1868
1869 return 0;
1870}
1871
b037c29a 1872static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 1873 int uar_idx)
e126ba97 1874{
b037c29a
EC		 1875 int fw_uars_per_page;
1876
1877 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1878
4ed131d0 1879 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 1880}
1881
1882static int get_command(unsigned long offset)
1883{
1884 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1885}
1886
1887static int get_arg(unsigned long offset)
1888{
1889 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1890}
1891
1892static int get_index(unsigned long offset)
1893{
1894 return get_arg(offset);
1895}
1896
4ed131d0
YH		 1897/* Index resides in an extra byte to enable larger values than 255 */
1898static int get_extended_index(unsigned long offset)
1899{
1900 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1901}
1902
7c2344c3
MG		 1903static void mlx5_ib_vma_open(struct vm_area_struct *area)
1904{
1905 /* vma_open is called when a new VMA is created on top of our VMA. This
1906 * is done through either mremap flow or split_vma (usually due to
1907 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1908 * as this VMA is strongly hardware related. Therefore we set the
1909 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1910 * calling us again and trying to do incorrect actions. We assume that
1911 * the original VMA size is exactly a single page, and therefore all
1912 * "splitting" operation will not happen to it.
1913 */
1914 area->vm_ops = NULL;
1915}
1916
1917static void mlx5_ib_vma_close(struct vm_area_struct *area)
1918{
1919 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1920
1921 /* It's guaranteed that all VMAs opened on a FD are closed before the
1922 * file itself is closed, therefore no sync is needed with the regular
1923 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1924 * However need a sync with accessing the vma as part of
1925 * mlx5_ib_disassociate_ucontext.
1926 * The close operation is usually called under mm->mmap_sem except when
1927 * process is exiting.
1928 * The exiting case is handled explicitly as part of
1929 * mlx5_ib_disassociate_ucontext.
1930 */
1931 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1932
1933 /* setting the vma context pointer to null in the mlx5_ib driver's
1934 * private data, to protect a race condition in
1935 * mlx5_ib_disassociate_ucontext().
1936 */
1937 mlx5_ib_vma_priv_data->vma = NULL;
ad9a3668 1938 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3 1939 list_del(&mlx5_ib_vma_priv_data->list);
ad9a3668 1940 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3
MG		 1941 kfree(mlx5_ib_vma_priv_data);
1942}
1943
1944static const struct vm_operations_struct mlx5_ib_vm_ops = {
1945 .open = mlx5_ib_vma_open,
1946 .close = mlx5_ib_vma_close
1947};
1948
1949static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1950 struct mlx5_ib_ucontext *ctx)
1951{
1952 struct mlx5_ib_vma_private_data *vma_prv;
1953 struct list_head *vma_head = &ctx->vma_private_list;
1954
1955 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1956 if (!vma_prv)
1957 return -ENOMEM;
1958
1959 vma_prv->vma = vma;
ad9a3668 1960 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
7c2344c3
MG		 1961 vma->vm_private_data = vma_prv;
1962 vma->vm_ops = &mlx5_ib_vm_ops;
1963
ad9a3668 1964 mutex_lock(&ctx->vma_private_list_mutex);
7c2344c3 1965 list_add(&vma_prv->list, vma_head);
ad9a3668 1966 mutex_unlock(&ctx->vma_private_list_mutex);
7c2344c3
MG		 1967
1968 return 0;
1969}
1970
1971static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1972{
7c2344c3
MG		 1973 struct vm_area_struct *vma;
1974 struct mlx5_ib_vma_private_data *vma_private, *n;
1975 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
7c2344c3 1976
ad9a3668 1977 mutex_lock(&context->vma_private_list_mutex);
7c2344c3
MG		 1978 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1979 list) {
1980 vma = vma_private->vma;
2cb40791 1981 zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE);
7c2344c3
MG		 1982 /* context going to be destroyed, should
1983 * not access ops any more.
1984 */
13776612 1985 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1986 vma->vm_ops = NULL;
1987 list_del(&vma_private->list);
1988 kfree(vma_private);
1989 }
ad9a3668 1990 mutex_unlock(&context->vma_private_list_mutex);
7c2344c3
MG		 1991}
1992
37aa5c36
GL		 1993static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1994{
1995 switch (cmd) {
1996 case MLX5_IB_MMAP_WC_PAGE:
1997 return "WC";
1998 case MLX5_IB_MMAP_REGULAR_PAGE:
1999 return "best effort WC";
2000 case MLX5_IB_MMAP_NC_PAGE:
2001 return "NC";
24da0016
AL		 2002 case MLX5_IB_MMAP_DEVICE_MEM:
2003 return "Device Memory";
37aa5c36
GL		 2004 default:
2005 return NULL;
2006 }
2007}
2008
5c99eaec
FD		 2009static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2010 struct vm_area_struct *vma,
2011 struct mlx5_ib_ucontext *context)
2012{
2013 phys_addr_t pfn;
2014 int err;
2015
2016 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2017 return -EINVAL;
2018
2019 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2020 return -EOPNOTSUPP;
2021
2022 if (vma->vm_flags & VM_WRITE)
2023 return -EPERM;
2024
2025 if (!dev->mdev->clock_info_page)
2026 return -EOPNOTSUPP;
2027
2028 pfn = page_to_pfn(dev->mdev->clock_info_page);
2029 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2030 vma->vm_page_prot);
2031 if (err)
2032 return err;
2033
5c99eaec
FD		 2034 return mlx5_ib_set_vma_data(vma, context);
2035}
2036
37aa5c36 2037static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2038 struct vm_area_struct *vma,
2039 struct mlx5_ib_ucontext *context)
37aa5c36 2040{
2f5ff264 2041 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2042 int err;
2043 unsigned long idx;
aa09ea6e 2044 phys_addr_t pfn;
37aa5c36 2045 pgprot_t prot;
4ed131d0
YH		 2046 u32 bfreg_dyn_idx = 0;
2047 u32 uar_index;
2048 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2049 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2050 bfregi->num_static_sys_pages;
b037c29a
EC		 2051
2052 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2053 return -EINVAL;
2054
4ed131d0
YH		 2055 if (dyn_uar)
2056 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2057 else
2058 idx = get_index(vma->vm_pgoff);
2059
2060 if (idx >= max_valid_idx) {
2061 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2062 idx, max_valid_idx);
b037c29a
EC		 2063 return -EINVAL;
2064 }
37aa5c36
GL		 2065
2066 switch (cmd) {
2067 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2068 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2069/* Some architectures don't support WC memory */
2070#if defined(CONFIG_X86)
2071 if (!pat_enabled())
2072 return -EPERM;
2073#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2074 return -EPERM;
2075#endif
2076 /* fall through */
2077 case MLX5_IB_MMAP_REGULAR_PAGE:
2078 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2079 prot = pgprot_writecombine(vma->vm_page_prot);
2080 break;
2081 case MLX5_IB_MMAP_NC_PAGE:
2082 prot = pgprot_noncached(vma->vm_page_prot);
2083 break;
2084 default:
2085 return -EINVAL;
2086 }
2087
4ed131d0
YH		 2088 if (dyn_uar) {
2089 int uars_per_page;
2090
2091 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2092 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2093 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2094 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2095 bfreg_dyn_idx, bfregi->total_num_bfregs);
2096 return -EINVAL;
2097 }
2098
2099 mutex_lock(&bfregi->lock);
2100 /* Fail if uar already allocated, first bfreg index of each
2101 * page holds its count.
2102 */
2103 if (bfregi->count[bfreg_dyn_idx]) {
2104 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2105 mutex_unlock(&bfregi->lock);
2106 return -EINVAL;
2107 }
2108
2109 bfregi->count[bfreg_dyn_idx]++;
2110 mutex_unlock(&bfregi->lock);
2111
2112 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2113 if (err) {
2114 mlx5_ib_warn(dev, "UAR alloc failed\n");
2115 goto free_bfreg;
2116 }
2117 } else {
2118 uar_index = bfregi->sys_pages[idx];
2119 }
2120
2121 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2122 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2123
2124 vma->vm_page_prot = prot;
2125 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2126 PAGE_SIZE, vma->vm_page_prot);
2127 if (err) {
8f062287
LR		 2128 mlx5_ib_err(dev,
2129 "io_remap_pfn_range failed with error=%d, mmap_cmd=%s\n",
2130 err, mmap_cmd2str(cmd));
4ed131d0
YH		 2131 err = -EAGAIN;
2132 goto err;
37aa5c36
GL		 2133 }
2134
4ed131d0
YH		 2135 err = mlx5_ib_set_vma_data(vma, context);
2136 if (err)
2137 goto err;
2138
2139 if (dyn_uar)
2140 bfregi->sys_pages[idx] = uar_index;
2141 return 0;
2142
2143err:
2144 if (!dyn_uar)
2145 return err;
2146
2147 mlx5_cmd_free_uar(dev->mdev, idx);
2148
2149free_bfreg:
2150 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2151
2152 return err;
37aa5c36
GL		 2153}
2154
24da0016
AL		 2155static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2156{
2157 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2158 struct mlx5_ib_dev *dev = to_mdev(context->device);
2159 u16 page_idx = get_extended_index(vma->vm_pgoff);
2160 size_t map_size = vma->vm_end - vma->vm_start;
2161 u32 npages = map_size >> PAGE_SHIFT;
2162 phys_addr_t pfn;
2163 pgprot_t prot;
2164
2165 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2166 page_idx + npages)
2167 return -EINVAL;
2168
2169 pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2170 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2171 PAGE_SHIFT) +
2172 page_idx;
2173 prot = pgprot_writecombine(vma->vm_page_prot);
2174 vma->vm_page_prot = prot;
2175
2176 if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
2177 vma->vm_page_prot))
2178 return -EAGAIN;
2179
2180 return mlx5_ib_set_vma_data(vma, mctx);
2181}
2182
e126ba97
EC		 2183static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2184{
2185 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2186 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2187 unsigned long command;
e126ba97
EC		 2188 phys_addr_t pfn;
2189
2190 command = get_command(vma->vm_pgoff);
2191 switch (command) {
37aa5c36
GL		 2192 case MLX5_IB_MMAP_WC_PAGE:
2193 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2194 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2195 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2196 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2197
2198 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2199 return -ENOSYS;
2200
d69e3bcf 2201 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2202 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2203 return -EINVAL;
2204
6cbac1e4 2205 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 2206 return -EPERM;
2207
2208 /* Don't expose to user-space information it shouldn't have */
2209 if (PAGE_SIZE > 4096)
2210 return -EOPNOTSUPP;
2211
2212 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2213 pfn = (dev->mdev->iseg_base +
2214 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2215 PAGE_SHIFT;
2216 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2217 PAGE_SIZE, vma->vm_page_prot))
2218 return -EAGAIN;
d69e3bcf 2219 break;
5c99eaec
FD		 2220 case MLX5_IB_MMAP_CLOCK_INFO:
2221 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2222
24da0016
AL		 2223 case MLX5_IB_MMAP_DEVICE_MEM:
2224 return dm_mmap(ibcontext, vma);
2225
e126ba97
EC		 2226 default:
2227 return -EINVAL;
2228 }
2229
2230 return 0;
2231}
2232
24da0016
AL		 2233struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2234 struct ib_ucontext *context,
2235 struct ib_dm_alloc_attr *attr,
2236 struct uverbs_attr_bundle *attrs)
2237{
2238 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2239 struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2240 phys_addr_t memic_addr;
2241 struct mlx5_ib_dm *dm;
2242 u64 start_offset;
2243 u32 page_idx;
2244 int err;
2245
2246 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2247 if (!dm)
2248 return ERR_PTR(-ENOMEM);
2249
2250 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2251 attr->length, act_size, attr->alignment);
2252
2253 err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2254 act_size, attr->alignment);
2255 if (err)
2256 goto err_free;
2257
2258 start_offset = memic_addr & ~PAGE_MASK;
2259 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2260 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2261 PAGE_SHIFT;
2262
2263 err = uverbs_copy_to(attrs,
2264 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2265 &start_offset, sizeof(start_offset));
2266 if (err)
2267 goto err_dealloc;
2268
2269 err = uverbs_copy_to(attrs,
2270 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2271 &page_idx, sizeof(page_idx));
2272 if (err)
2273 goto err_dealloc;
2274
2275 bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2276 DIV_ROUND_UP(act_size, PAGE_SIZE));
2277
2278 dm->dev_addr = memic_addr;
2279
2280 return &dm->ibdm;
2281
2282err_dealloc:
2283 mlx5_cmd_dealloc_memic(memic, memic_addr,
2284 act_size);
2285err_free:
2286 kfree(dm);
2287 return ERR_PTR(err);
2288}
2289
2290int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2291{
2292 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2293 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2294 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2295 u32 page_idx;
2296 int ret;
2297
2298 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2299 if (ret)
2300 return ret;
2301
2302 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2303 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2304 PAGE_SHIFT;
2305 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2306 page_idx,
2307 DIV_ROUND_UP(act_size, PAGE_SIZE));
2308
2309 kfree(dm);
2310
2311 return 0;
2312}
2313
e126ba97
EC		 2314static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2315 struct ib_ucontext *context,
2316 struct ib_udata *udata)
2317{
2318 struct mlx5_ib_alloc_pd_resp resp;
2319 struct mlx5_ib_pd *pd;
2320 int err;
2321
2322 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2323 if (!pd)
2324 return ERR_PTR(-ENOMEM);
2325
9603b61d 2326 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 2327 if (err) {
2328 kfree(pd);
2329 return ERR_PTR(err);
2330 }
2331
2332 if (context) {
2333 resp.pdn = pd->pdn;
2334 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 2335 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 2336 kfree(pd);
2337 return ERR_PTR(-EFAULT);
2338 }
e126ba97
EC		 2339 }
2340
2341 return &pd->ibpd;
2342}
2343
2344static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2345{
2346 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2347 struct mlx5_ib_pd *mpd = to_mpd(pd);
2348
9603b61d 2349 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 2350 kfree(mpd);
2351
2352 return 0;
2353}
2354
466fa6d2
MG		 2355enum {
2356 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2357 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2358 MATCH_CRITERIA_ENABLE_INNER_BIT,
2359 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2360};
2361
2362#define HEADER_IS_ZERO(match_criteria, headers) \
2363 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2364 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2365
466fa6d2 2366static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2367{
466fa6d2 2368 u8 match_criteria_enable;
038d2ef8 2369
466fa6d2
MG		 2370 match_criteria_enable =
2371 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2372 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2373 match_criteria_enable |=
2374 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2375 MATCH_CRITERIA_ENABLE_MISC_BIT;
2376 match_criteria_enable |=
2377 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2378 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2379 match_criteria_enable |=
2380 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2381 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2382
2383 return match_criteria_enable;
038d2ef8
MG		 2384}
2385
ca0d4753
MG		 2386static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2387{
2388 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2389 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 2390}
2391
37da2a03 2392static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2393 bool inner)
2394{
2395 if (inner) {
2396 MLX5_SET(fte_match_set_misc,
2397 misc_c, inner_ipv6_flow_label, mask);
2398 MLX5_SET(fte_match_set_misc,
2399 misc_v, inner_ipv6_flow_label, val);
2400 } else {
2401 MLX5_SET(fte_match_set_misc,
2402 misc_c, outer_ipv6_flow_label, mask);
2403 MLX5_SET(fte_match_set_misc,
2404 misc_v, outer_ipv6_flow_label, val);
2405 }
2406}
2407
ca0d4753
MG		 2408static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2409{
2410 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2411 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2412 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2413 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2414}
2415
71c6e863
AL		 2416static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2417{
2418 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2419 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2420 return -EOPNOTSUPP;
2421
2422 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2423 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2424 return -EOPNOTSUPP;
2425
2426 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2427 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2428 return -EOPNOTSUPP;
2429
2430 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2431 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2432 return -EOPNOTSUPP;
2433
2434 return 0;
2435}
2436
c47ac6ae
MG		 2437#define LAST_ETH_FIELD vlan_tag
2438#define LAST_IB_FIELD sl
ca0d4753 2439#define LAST_IPV4_FIELD tos
466fa6d2 2440#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2441#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2442#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2443#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2444#define LAST_DROP_FIELD size
3b3233fb 2445#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2446
2447/* Field is the last supported field */
2448#define FIELDS_NOT_SUPPORTED(filter, field)\
2449 memchr_inv((void *)&filter.field +\
2450 sizeof(filter.field), 0,\
2451 sizeof(filter) -\
2452 offsetof(typeof(filter), field) -\
2453 sizeof(filter.field))
2454
802c2125
AY		 2455static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2456 const struct ib_flow_attr *flow_attr,
2457 struct mlx5_flow_act *action)
2458{
2459 struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2460
2461 switch (maction->ib_action.type) {
2462 case IB_FLOW_ACTION_ESP:
2463 /* Currently only AES_GCM keymat is supported by the driver */
2464 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2465 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2466 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2467 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2468 return 0;
2469 default:
2470 return -EOPNOTSUPP;
2471 }
2472}
2473
19cc7524
AL		 2474static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2475 u32 *match_v, const union ib_flow_spec *ib_spec,
802c2125 2476 const struct ib_flow_attr *flow_attr,
71c6e863 2477 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2478{
466fa6d2
MG		 2479 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2480 misc_parameters);
2481 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2482 misc_parameters);
71c6e863
AL		 2483 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2484 misc_parameters_2);
2485 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2486 misc_parameters_2);
2d1e697e
MR		 2487 void *headers_c;
2488 void *headers_v;
19cc7524 2489 int match_ipv;
802c2125 2490 int ret;
2d1e697e
MR		 2491
2492 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2493 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2494 inner_headers);
2495 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2496 inner_headers);
19cc7524
AL		 2497 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2498 ft_field_support.inner_ip_version);
2d1e697e
MR		 2499 } else {
2500 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2501 outer_headers);
2502 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2503 outer_headers);
19cc7524
AL		 2504 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2505 ft_field_support.outer_ip_version);
2d1e697e 2506 }
466fa6d2 2507
2d1e697e 2508 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2509 case IB_FLOW_SPEC_ETH:
c47ac6ae 2510 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2511 return -EOPNOTSUPP;
038d2ef8 2512
2d1e697e 2513 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2514 dmac_47_16),
2515 ib_spec->eth.mask.dst_mac);
2d1e697e 2516 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2517 dmac_47_16),
2518 ib_spec->eth.val.dst_mac);
2519
2d1e697e 2520 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2521 smac_47_16),
2522 ib_spec->eth.mask.src_mac);
2d1e697e 2523 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2524 smac_47_16),
2525 ib_spec->eth.val.src_mac);
2526
038d2ef8 2527 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2528 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2529 cvlan_tag, 1);
2d1e697e 2530 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2531 cvlan_tag, 1);
038d2ef8 2532
2d1e697e 2533 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2534 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2535 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2536 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2537
2d1e697e 2538 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2539 first_cfi,
2540 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2541 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2542 first_cfi,
2543 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2544
2d1e697e 2545 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2546 first_prio,
2547 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2548 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2549 first_prio,
2550 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2551 }
2d1e697e 2552 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2553 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2554 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2555 ethertype, ntohs(ib_spec->eth.val.ether_type));
2556 break;
2557 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2558 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2559 return -EOPNOTSUPP;
038d2ef8 2560
19cc7524
AL		 2561 if (match_ipv) {
2562 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2563 ip_version, 0xf);
2564 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2565 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2566 } else {
2567 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2568 ethertype, 0xffff);
2569 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2570 ethertype, ETH_P_IP);
2571 }
038d2ef8 2572
2d1e697e 2573 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2574 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2575 &ib_spec->ipv4.mask.src_ip,
2576 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2577 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2578 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2579 &ib_spec->ipv4.val.src_ip,
2580 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2581 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2582 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2583 &ib_spec->ipv4.mask.dst_ip,
2584 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2585 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2586 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2587 &ib_spec->ipv4.val.dst_ip,
2588 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2589
2d1e697e 2590 set_tos(headers_c, headers_v,
ca0d4753
MG		 2591 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2592
2d1e697e 2593 set_proto(headers_c, headers_v,
ca0d4753 2594 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2595 break;
026bae0c 2596 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2597 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2598 return -EOPNOTSUPP;
026bae0c 2599
19cc7524
AL		 2600 if (match_ipv) {
2601 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2602 ip_version, 0xf);
2603 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2604 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2605 } else {
2606 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2607 ethertype, 0xffff);
2608 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2609 ethertype, ETH_P_IPV6);
2610 }
026bae0c 2611
2d1e697e 2612 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2613 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2614 &ib_spec->ipv6.mask.src_ip,
2615 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2616 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2617 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2618 &ib_spec->ipv6.val.src_ip,
2619 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2620 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2621 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2622 &ib_spec->ipv6.mask.dst_ip,
2623 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2624 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2625 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2626 &ib_spec->ipv6.val.dst_ip,
2627 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2628
2d1e697e 2629 set_tos(headers_c, headers_v,
466fa6d2
MG		 2630 ib_spec->ipv6.mask.traffic_class,
2631 ib_spec->ipv6.val.traffic_class);
2632
2d1e697e 2633 set_proto(headers_c, headers_v,
466fa6d2
MG		 2634 ib_spec->ipv6.mask.next_hdr,
2635 ib_spec->ipv6.val.next_hdr);
2636
2d1e697e
MR		 2637 set_flow_label(misc_params_c, misc_params_v,
2638 ntohl(ib_spec->ipv6.mask.flow_label),
2639 ntohl(ib_spec->ipv6.val.flow_label),
2640 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2641 break;
2642 case IB_FLOW_SPEC_ESP:
2643 if (ib_spec->esp.mask.seq)
2644 return -EOPNOTSUPP;
2d1e697e 2645
802c2125
AY		 2646 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2647 ntohl(ib_spec->esp.mask.spi));
2648 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2649 ntohl(ib_spec->esp.val.spi));
026bae0c 2650 break;
038d2ef8 2651 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2652 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2653 LAST_TCP_UDP_FIELD))
1ffd3a26 2654 return -EOPNOTSUPP;
038d2ef8 2655
2d1e697e 2656 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2657 0xff);
2d1e697e 2658 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2659 IPPROTO_TCP);
2660
2d1e697e 2661 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2662 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2663 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2664 ntohs(ib_spec->tcp_udp.val.src_port));
2665
2d1e697e 2666 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2667 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2668 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2669 ntohs(ib_spec->tcp_udp.val.dst_port));
2670 break;
2671 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2672 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2673 LAST_TCP_UDP_FIELD))
1ffd3a26 2674 return -EOPNOTSUPP;
038d2ef8 2675
2d1e697e 2676 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2677 0xff);
2d1e697e 2678 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2679 IPPROTO_UDP);
2680
2d1e697e 2681 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2682 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2683 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2684 ntohs(ib_spec->tcp_udp.val.src_port));
2685
2d1e697e 2686 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2687 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2688 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2689 ntohs(ib_spec->tcp_udp.val.dst_port));
2690 break;
da2f22ae
AL		 2691 case IB_FLOW_SPEC_GRE:
2692 if (ib_spec->gre.mask.c_ks_res0_ver)
2693 return -EOPNOTSUPP;
2694
2695 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2696 0xff);
2697 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2698 IPPROTO_GRE);
2699
2700 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 2701 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 2702 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2703 ntohs(ib_spec->gre.val.protocol));
2704
2705 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2706 gre_key_h),
2707 &ib_spec->gre.mask.key,
2708 sizeof(ib_spec->gre.mask.key));
2709 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2710 gre_key_h),
2711 &ib_spec->gre.val.key,
2712 sizeof(ib_spec->gre.val.key));
2713 break;
71c6e863
AL		 2714 case IB_FLOW_SPEC_MPLS:
2715 switch (prev_type) {
2716 case IB_FLOW_SPEC_UDP:
2717 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2718 ft_field_support.outer_first_mpls_over_udp),
2719 &ib_spec->mpls.mask.tag))
2720 return -EOPNOTSUPP;
2721
2722 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2723 outer_first_mpls_over_udp),
2724 &ib_spec->mpls.val.tag,
2725 sizeof(ib_spec->mpls.val.tag));
2726 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2727 outer_first_mpls_over_udp),
2728 &ib_spec->mpls.mask.tag,
2729 sizeof(ib_spec->mpls.mask.tag));
2730 break;
2731 case IB_FLOW_SPEC_GRE:
2732 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2733 ft_field_support.outer_first_mpls_over_gre),
2734 &ib_spec->mpls.mask.tag))
2735 return -EOPNOTSUPP;
2736
2737 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2738 outer_first_mpls_over_gre),
2739 &ib_spec->mpls.val.tag,
2740 sizeof(ib_spec->mpls.val.tag));
2741 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2742 outer_first_mpls_over_gre),
2743 &ib_spec->mpls.mask.tag,
2744 sizeof(ib_spec->mpls.mask.tag));
2745 break;
2746 default:
2747 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2748 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2749 ft_field_support.inner_first_mpls),
2750 &ib_spec->mpls.mask.tag))
2751 return -EOPNOTSUPP;
2752
2753 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2754 inner_first_mpls),
2755 &ib_spec->mpls.val.tag,
2756 sizeof(ib_spec->mpls.val.tag));
2757 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2758 inner_first_mpls),
2759 &ib_spec->mpls.mask.tag,
2760 sizeof(ib_spec->mpls.mask.tag));
2761 } else {
2762 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2763 ft_field_support.outer_first_mpls),
2764 &ib_spec->mpls.mask.tag))
2765 return -EOPNOTSUPP;
2766
2767 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2768 outer_first_mpls),
2769 &ib_spec->mpls.val.tag,
2770 sizeof(ib_spec->mpls.val.tag));
2771 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2772 outer_first_mpls),
2773 &ib_spec->mpls.mask.tag,
2774 sizeof(ib_spec->mpls.mask.tag));
2775 }
2776 }
2777 break;
ffb30d8f
MR		 2778 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2779 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2780 LAST_TUNNEL_FIELD))
1ffd3a26 2781 return -EOPNOTSUPP;
ffb30d8f
MR		 2782
2783 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2784 ntohl(ib_spec->tunnel.mask.tunnel_id));
2785 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2786 ntohl(ib_spec->tunnel.val.tunnel_id));
2787 break;
2ac693f9
MR		 2788 case IB_FLOW_SPEC_ACTION_TAG:
2789 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2790 LAST_FLOW_TAG_FIELD))
2791 return -EOPNOTSUPP;
2792 if (ib_spec->flow_tag.tag_id >= BIT(24))
2793 return -EINVAL;
2794
075572d4 2795 action->flow_tag = ib_spec->flow_tag.tag_id;
a9db0ecf 2796 action->has_flow_tag = true;
2ac693f9 2797 break;
a22ed86c
SS		 2798 case IB_FLOW_SPEC_ACTION_DROP:
2799 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2800 LAST_DROP_FIELD))
2801 return -EOPNOTSUPP;
075572d4 2802 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 2803 break;
802c2125
AY		 2804 case IB_FLOW_SPEC_ACTION_HANDLE:
2805 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2806 if (ret)
2807 return ret;
2808 break;
3b3233fb
RS		 2809 case IB_FLOW_SPEC_ACTION_COUNT:
2810 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2811 LAST_COUNTERS_FIELD))
2812 return -EOPNOTSUPP;
2813
2814 /* for now support only one counters spec per flow */
2815 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2816 return -EINVAL;
2817
2818 action->counters = ib_spec->flow_count.counters;
2819 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2820 break;
038d2ef8
MG		 2821 default:
2822 return -EINVAL;
2823 }
2824
2825 return 0;
2826}
2827
2828/* If a flow could catch both multicast and unicast packets,
2829 * it won't fall into the multicast flow steering table and this rule
2830 * could steal other multicast packets.
2831 */
a550ddfc 2832static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2833{
81e30880 2834 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2835
2836 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2837 ib_attr->num_of_specs < 1)
2838 return false;
2839
81e30880
YH		 2840 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2841 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2842 struct ib_flow_spec_ipv4 *ipv4_spec;
2843
2844 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2845 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2846 return true;
2847
038d2ef8 2848 return false;
81e30880
YH		 2849 }
2850
2851 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2852 struct ib_flow_spec_eth *eth_spec;
2853
2854 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2855 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2856 is_multicast_ether_addr(eth_spec->val.dst_mac);
2857 }
038d2ef8 2858
81e30880 2859 return false;
038d2ef8
MG		 2860}
2861
802c2125
AY		 2862enum valid_spec {
2863 VALID_SPEC_INVALID,
2864 VALID_SPEC_VALID,
2865 VALID_SPEC_NA,
2866};
2867
2868static enum valid_spec
2869is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2870 const struct mlx5_flow_spec *spec,
2871 const struct mlx5_flow_act *flow_act,
2872 bool egress)
2873{
2874 const u32 *match_c = spec->match_criteria;
2875 bool is_crypto =
2876 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2877 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2878 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2879 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2880
2881 /*
2882 * Currently only crypto is supported in egress, when regular egress
2883 * rules would be supported, always return VALID_SPEC_NA.
2884 */
2885 if (!is_crypto)
2886 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
2887
2888 return is_crypto && is_ipsec &&
2889 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2890 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2891}
2892
2893static bool is_valid_spec(struct mlx5_core_dev *mdev,
2894 const struct mlx5_flow_spec *spec,
2895 const struct mlx5_flow_act *flow_act,
2896 bool egress)
2897{
2898 /* We curretly only support ipsec egress flow */
2899 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2900}
2901
19cc7524
AL		 2902static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2903 const struct ib_flow_attr *flow_attr,
0f750966 2904 bool check_inner)
038d2ef8
MG		 2905{
2906 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2907 int match_ipv = check_inner ?
2908 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2909 ft_field_support.inner_ip_version) :
2910 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2911 ft_field_support.outer_ip_version);
0f750966
AL		 2912 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2913 bool ipv4_spec_valid, ipv6_spec_valid;
2914 unsigned int ip_spec_type = 0;
2915 bool has_ethertype = false;
038d2ef8 2916 unsigned int spec_index;
0f750966
AL		 2917 bool mask_valid = true;
2918 u16 eth_type = 0;
2919 bool type_valid;
038d2ef8
MG		 2920
2921 /* Validate that ethertype is correct */
2922 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2923 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2924 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2925 mask_valid = (ib_spec->eth.mask.ether_type ==
2926 htons(0xffff));
2927 has_ethertype = true;
2928 eth_type = ntohs(ib_spec->eth.val.ether_type);
2929 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2930 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2931 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2932 }
2933 ib_spec = (void *)ib_spec + ib_spec->size;
2934 }
0f750966
AL		 2935
2936 type_valid = (!has_ethertype) || (!ip_spec_type);
2937 if (!type_valid && mask_valid) {
2938 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2939 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2940 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2941 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2942
2943 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2944 (((eth_type == ETH_P_MPLS_UC) ||
2945 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2946 }
2947
2948 return type_valid;
2949}
2950
19cc7524
AL		 2951static bool is_valid_attr(struct mlx5_core_dev *mdev,
2952 const struct ib_flow_attr *flow_attr)
0f750966 2953{
19cc7524
AL		 2954 return is_valid_ethertype(mdev, flow_attr, false) &&
2955 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2956}
2957
2958static void put_flow_table(struct mlx5_ib_dev *dev,
2959 struct mlx5_ib_flow_prio *prio, bool ft_added)
2960{
2961 prio->refcount -= !!ft_added;
2962 if (!prio->refcount) {
2963 mlx5_destroy_flow_table(prio->flow_table);
2964 prio->flow_table = NULL;
2965 }
2966}
2967
3b3233fb
RS		 2968static void counters_clear_description(struct ib_counters *counters)
2969{
2970 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2971
2972 mutex_lock(&mcounters->mcntrs_mutex);
2973 kfree(mcounters->counters_data);
2974 mcounters->counters_data = NULL;
2975 mcounters->cntrs_max_index = 0;
2976 mutex_unlock(&mcounters->mcntrs_mutex);
2977}
2978
038d2ef8
MG		 2979static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2980{
038d2ef8
MG		 2981 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2982 struct mlx5_ib_flow_handler,
2983 ibflow);
2984 struct mlx5_ib_flow_handler *iter, *tmp;
d4be3f44 2985 struct mlx5_ib_dev *dev = handler->dev;
038d2ef8 2986
9a4ca38d 2987 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 2988
2989 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2990 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2991 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2992 list_del(&iter->list);
2993 kfree(iter);
2994 }
2995
74491de9 2996 mlx5_del_flow_rules(handler->rule);
5497adc6 2997 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 2998 if (handler->ibcounters &&
2999 atomic_read(&handler->ibcounters->usecnt) == 1)
3000 counters_clear_description(handler->ibcounters);
038d2ef8 3001
3b3233fb 3002 mutex_unlock(&dev->flow_db->lock);
d4be3f44
YH		 3003 if (handler->flow_matcher)
3004 atomic_dec(&handler->flow_matcher->usecnt);
038d2ef8
MG		 3005 kfree(handler);
3006
3007 return 0;
3008}
3009
35d19011
MG		 3010static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3011{
3012 priority *= 2;
3013 if (!dont_trap)
3014 priority++;
3015 return priority;
3016}
3017
cc0e5d42
MG		 3018enum flow_table_type {
3019 MLX5_IB_FT_RX,
3020 MLX5_IB_FT_TX
3021};
3022
00b7c2ab
MG		 3023#define MLX5_FS_MAX_TYPES 6
3024#define MLX5_FS_MAX_ENTRIES BIT(16)
d4be3f44
YH		 3025
3026static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3027 struct mlx5_ib_flow_prio *prio,
3028 int priority,
3029 int num_entries, int num_groups)
3030{
3031 struct mlx5_flow_table *ft;
3032
3033 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3034 num_entries,
3035 num_groups,
3036 0, 0);
3037 if (IS_ERR(ft))
3038 return ERR_CAST(ft);
3039
3040 prio->flow_table = ft;
3041 prio->refcount = 0;
3042 return prio;
3043}
3044
038d2ef8 3045static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3046 struct ib_flow_attr *flow_attr,
3047 enum flow_table_type ft_type)
038d2ef8 3048{
35d19011 3049 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3050 struct mlx5_flow_namespace *ns = NULL;
3051 struct mlx5_ib_flow_prio *prio;
3052 struct mlx5_flow_table *ft;
dac388ef 3053 int max_table_size;
038d2ef8
MG		 3054 int num_entries;
3055 int num_groups;
3056 int priority;
038d2ef8 3057
dac388ef
MG		 3058 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3059 log_max_ft_size));
038d2ef8 3060 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
802c2125
AY		 3061 if (ft_type == MLX5_IB_FT_TX)
3062 priority = 0;
3063 else if (flow_is_multicast_only(flow_attr) &&
3064 !dont_trap)
038d2ef8
MG		 3065 priority = MLX5_IB_FLOW_MCAST_PRIO;
3066 else
35d19011
MG		 3067 priority = ib_prio_to_core_prio(flow_attr->priority,
3068 dont_trap);
038d2ef8 3069 ns = mlx5_get_flow_namespace(dev->mdev,
802c2125
AY		 3070 ft_type == MLX5_IB_FT_TX ?
3071 MLX5_FLOW_NAMESPACE_EGRESS :
038d2ef8
MG		 3072 MLX5_FLOW_NAMESPACE_BYPASS);
3073 num_entries = MLX5_FS_MAX_ENTRIES;
3074 num_groups = MLX5_FS_MAX_TYPES;
9a4ca38d 3075 prio = &dev->flow_db->prios[priority];
038d2ef8
MG		 3076 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3077 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3078 ns = mlx5_get_flow_namespace(dev->mdev,
3079 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3080 build_leftovers_ft_param(&priority,
3081 &num_entries,
3082 &num_groups);
9a4ca38d 3083 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3084 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3085 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3086 allow_sniffer_and_nic_rx_shared_tir))
3087 return ERR_PTR(-ENOTSUPP);
3088
3089 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3090 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3091 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3092
9a4ca38d 3093 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3094 priority = 0;
3095 num_entries = 1;
3096 num_groups = 1;
038d2ef8
MG		 3097 }
3098
3099 if (!ns)
3100 return ERR_PTR(-ENOTSUPP);
3101
dac388ef
MG		 3102 if (num_entries > max_table_size)
3103 return ERR_PTR(-ENOMEM);
3104
038d2ef8 3105 ft = prio->flow_table;
d4be3f44
YH		 3106 if (!ft)
3107 return _get_prio(ns, prio, priority, num_entries, num_groups);
038d2ef8 3108
d4be3f44 3109 return prio;
038d2ef8
MG		 3110}
3111
a550ddfc
YH		 3112static void set_underlay_qp(struct mlx5_ib_dev *dev,
3113 struct mlx5_flow_spec *spec,
3114 u32 underlay_qpn)
3115{
3116 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3117 spec->match_criteria,
3118 misc_parameters);
3119 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3120 misc_parameters);
3121
3122 if (underlay_qpn &&
3123 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3124 ft_field_support.bth_dst_qp)) {
3125 MLX5_SET(fte_match_set_misc,
3126 misc_params_v, bth_dst_qp, underlay_qpn);
3127 MLX5_SET(fte_match_set_misc,
3128 misc_params_c, bth_dst_qp, 0xffffff);
3129 }
3130}
3131
5e95af5f
RS		 3132static int read_flow_counters(struct ib_device *ibdev,
3133 struct mlx5_read_counters_attr *read_attr)
3134{
3135 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3136 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3137
3138 return mlx5_fc_query(dev->mdev, fc,
3139 &read_attr->out[IB_COUNTER_PACKETS],
3140 &read_attr->out[IB_COUNTER_BYTES]);
3141}
3142
3143/* flow counters currently expose two counters packets and bytes */
3144#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3145static int counters_set_description(struct ib_counters *counters,
3146 enum mlx5_ib_counters_type counters_type,
3147 struct mlx5_ib_flow_counters_desc *desc_data,
3148 u32 ncounters)
3149{
3150 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3151 u32 cntrs_max_index = 0;
3152 int i;
3153
3154 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3155 return -EINVAL;
3156
3157 /* init the fields for the object */
3158 mcounters->type = counters_type;
5e95af5f
RS		 3159 mcounters->read_counters = read_flow_counters;
3160 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3161 mcounters->ncounters = ncounters;
3162 /* each counter entry have both description and index pair */
3163 for (i = 0; i < ncounters; i++) {
3164 if (desc_data[i].description > IB_COUNTER_BYTES)
3165 return -EINVAL;
3166
3167 if (cntrs_max_index <= desc_data[i].index)
3168 cntrs_max_index = desc_data[i].index + 1;
3169 }
3170
3171 mutex_lock(&mcounters->mcntrs_mutex);
3172 mcounters->counters_data = desc_data;
3173 mcounters->cntrs_max_index = cntrs_max_index;
3174 mutex_unlock(&mcounters->mcntrs_mutex);
3175
3176 return 0;
3177}
3178
3179#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3180static int flow_counters_set_data(struct ib_counters *ibcounters,
3181 struct mlx5_ib_create_flow *ucmd)
3182{
3183 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3184 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3185 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3186 bool hw_hndl = false;
3187 int ret = 0;
3188
3189 if (ucmd && ucmd->ncounters_data != 0) {
3190 cntrs_data = ucmd->data;
3191 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3192 return -EINVAL;
3193
3194 desc_data = kcalloc(cntrs_data->ncounters,
3195 sizeof(*desc_data),
3196 GFP_KERNEL);
3197 if (!desc_data)
3198 return -ENOMEM;
3199
3200 if (copy_from_user(desc_data,
3201 u64_to_user_ptr(cntrs_data->counters_data),
3202 sizeof(*desc_data) * cntrs_data->ncounters)) {
3203 ret = -EFAULT;
3204 goto free;
3205 }
3206 }
3207
3208 if (!mcounters->hw_cntrs_hndl) {
3209 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3210 to_mdev(ibcounters->device)->mdev, false);
3211 if (!mcounters->hw_cntrs_hndl) {
3212 ret = -ENOMEM;
3213 goto free;
3214 }
3215 hw_hndl = true;
3216 }
3217
3218 if (desc_data) {
3219 /* counters already bound to at least one flow */
3220 if (mcounters->cntrs_max_index) {
3221 ret = -EINVAL;
3222 goto free_hndl;
3223 }
3224
3225 ret = counters_set_description(ibcounters,
3226 MLX5_IB_COUNTERS_FLOW,
3227 desc_data,
3228 cntrs_data->ncounters);
3229 if (ret)
3230 goto free_hndl;
3231
3232 } else if (!mcounters->cntrs_max_index) {
3233 /* counters not bound yet, must have udata passed */
3234 ret = -EINVAL;
3235 goto free_hndl;
3236 }
3237
3238 return 0;
3239
3240free_hndl:
3241 if (hw_hndl) {
3242 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3243 mcounters->hw_cntrs_hndl);
3244 mcounters->hw_cntrs_hndl = NULL;
3245 }
3246free:
3247 kfree(desc_data);
3248 return ret;
3249}
3250
a550ddfc
YH		 3251static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3252 struct mlx5_ib_flow_prio *ft_prio,
3253 const struct ib_flow_attr *flow_attr,
3254 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3255 u32 underlay_qpn,
3256 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3257{
3258 struct mlx5_flow_table *ft = ft_prio->flow_table;
3259 struct mlx5_ib_flow_handler *handler;
075572d4 3260 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
c5bb1730 3261 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3262 struct mlx5_flow_destination dest_arr[2] = {};
3263 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3264 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3265 unsigned int spec_index;
71c6e863 3266 u32 prev_type = 0;
038d2ef8 3267 int err = 0;
3b3233fb 3268 int dest_num = 0;
802c2125 3269 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3270
19cc7524 3271 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3272 return ERR_PTR(-EINVAL);
3273
1b9a07ee 3274 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3275 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3276 if (!handler || !spec) {
038d2ef8
MG		 3277 err = -ENOMEM;
3278 goto free;
3279 }
3280
3281 INIT_LIST_HEAD(&handler->list);
3b3233fb
RS		 3282 if (dst) {
3283 memcpy(&dest_arr[0], dst, sizeof(*dst));
3284 dest_num++;
3285 }
038d2ef8
MG		 3286
3287 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 3288 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c 3289 spec->match_value,
71c6e863
AL		 3290 ib_flow, flow_attr, &flow_act,
3291 prev_type);
038d2ef8
MG		 3292 if (err < 0)
3293 goto free;
3294
71c6e863 3295 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3296 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3297 }
3298
a550ddfc
YH		 3299 if (!flow_is_multicast_only(flow_attr))
3300 set_underlay_qp(dev, spec, underlay_qpn);
3301
018a94ee
MB		 3302 if (dev->rep) {
3303 void *misc;
3304
3305 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3306 misc_parameters);
3307 MLX5_SET(fte_match_set_misc, misc, source_port,
3308 dev->rep->vport);
3309 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3310 misc_parameters);
3311 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3312 }
3313
466fa6d2 3314 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3315
3316 if (is_egress &&
3317 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3318 err = -EINVAL;
3319 goto free;
3320 }
3321
3b3233fb
RS		 3322 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3323 err = flow_counters_set_data(flow_act.counters, ucmd);
3324 if (err)
3325 goto free;
3326
3327 handler->ibcounters = flow_act.counters;
3328 dest_arr[dest_num].type =
3329 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3330 dest_arr[dest_num].counter =
3331 to_mcounters(flow_act.counters)->hw_cntrs_hndl;
3332 dest_num++;
3333 }
3334
075572d4 3335 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3b3233fb
RS		 3336 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3337 rule_dst = NULL;
3338 dest_num = 0;
3339 }
a22ed86c 3340 } else {
802c2125
AY		 3341 if (is_egress)
3342 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3343 else
3344 flow_act.action |=
3b3233fb 3345 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3346 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3347 }
2ac693f9 3348
a9db0ecf 3349 if (flow_act.has_flow_tag &&
2ac693f9
MR		 3350 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3351 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3352 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
075572d4 3353 flow_act.flow_tag, flow_attr->type);
2ac693f9
MR		 3354 err = -EINVAL;
3355 goto free;
3356 }
74491de9 3357 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3358 &flow_act,
a22ed86c 3359 rule_dst, dest_num);
038d2ef8
MG		 3360
3361 if (IS_ERR(handler->rule)) {
3362 err = PTR_ERR(handler->rule);
3363 goto free;
3364 }
3365
d9d4980a 3366 ft_prio->refcount++;
5497adc6 3367 handler->prio = ft_prio;
d4be3f44 3368 handler->dev = dev;
038d2ef8
MG		 3369
3370 ft_prio->flow_table = ft;
3371free:
3b3233fb
RS		 3372 if (err && handler) {
3373 if (handler->ibcounters &&
3374 atomic_read(&handler->ibcounters->usecnt) == 1)
3375 counters_clear_description(handler->ibcounters);
038d2ef8 3376 kfree(handler);
3b3233fb 3377 }
c5bb1730 3378 kvfree(spec);
038d2ef8
MG		 3379 return err ? ERR_PTR(err) : handler;
3380}
3381
a550ddfc
YH		 3382static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3383 struct mlx5_ib_flow_prio *ft_prio,
3384 const struct ib_flow_attr *flow_attr,
3385 struct mlx5_flow_destination *dst)
3386{
3b3233fb 3387 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3388}
3389
35d19011
MG		 3390static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3391 struct mlx5_ib_flow_prio *ft_prio,
3392 struct ib_flow_attr *flow_attr,
3393 struct mlx5_flow_destination *dst)
3394{
3395 struct mlx5_ib_flow_handler *handler_dst = NULL;
3396 struct mlx5_ib_flow_handler *handler = NULL;
3397
3398 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3399 if (!IS_ERR(handler)) {
3400 handler_dst = create_flow_rule(dev, ft_prio,
3401 flow_attr, dst);
3402 if (IS_ERR(handler_dst)) {
74491de9 3403 mlx5_del_flow_rules(handler->rule);
d9d4980a 3404 ft_prio->refcount--;
35d19011
MG		 3405 kfree(handler);
3406 handler = handler_dst;
3407 } else {
3408 list_add(&handler_dst->list, &handler->list);
3409 }
3410 }
3411
3412 return handler;
3413}
038d2ef8
MG		 3414enum {
3415 LEFTOVERS_MC,
3416 LEFTOVERS_UC,
3417};
3418
3419static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3420 struct mlx5_ib_flow_prio *ft_prio,
3421 struct ib_flow_attr *flow_attr,
3422 struct mlx5_flow_destination *dst)
3423{
3424 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3425 struct mlx5_ib_flow_handler *handler = NULL;
3426
3427 static struct {
3428 struct ib_flow_attr flow_attr;
3429 struct ib_flow_spec_eth eth_flow;
3430 } leftovers_specs[] = {
3431 [LEFTOVERS_MC] = {
3432 .flow_attr = {
3433 .num_of_specs = 1,
3434 .size = sizeof(leftovers_specs[0])
3435 },
3436 .eth_flow = {
3437 .type = IB_FLOW_SPEC_ETH,
3438 .size = sizeof(struct ib_flow_spec_eth),
3439 .mask = {.dst_mac = {0x1} },
3440 .val = {.dst_mac = {0x1} }
3441 }
3442 },
3443 [LEFTOVERS_UC] = {
3444 .flow_attr = {
3445 .num_of_specs = 1,
3446 .size = sizeof(leftovers_specs[0])
3447 },
3448 .eth_flow = {
3449 .type = IB_FLOW_SPEC_ETH,
3450 .size = sizeof(struct ib_flow_spec_eth),
3451 .mask = {.dst_mac = {0x1} },
3452 .val = {.dst_mac = {} }
3453 }
3454 }
3455 };
3456
3457 handler = create_flow_rule(dev, ft_prio,
3458 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3459 dst);
3460 if (!IS_ERR(handler) &&
3461 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3462 handler_ucast = create_flow_rule(dev, ft_prio,
3463 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3464 dst);
3465 if (IS_ERR(handler_ucast)) {
74491de9 3466 mlx5_del_flow_rules(handler->rule);
d9d4980a 3467 ft_prio->refcount--;
038d2ef8
MG		 3468 kfree(handler);
3469 handler = handler_ucast;
3470 } else {
3471 list_add(&handler_ucast->list, &handler->list);
3472 }
3473 }
3474
3475 return handler;
3476}
3477
cc0e5d42
MG		 3478static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3479 struct mlx5_ib_flow_prio *ft_rx,
3480 struct mlx5_ib_flow_prio *ft_tx,
3481 struct mlx5_flow_destination *dst)
3482{
3483 struct mlx5_ib_flow_handler *handler_rx;
3484 struct mlx5_ib_flow_handler *handler_tx;
3485 int err;
3486 static const struct ib_flow_attr flow_attr = {
3487 .num_of_specs = 0,
3488 .size = sizeof(flow_attr)
3489 };
3490
3491 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3492 if (IS_ERR(handler_rx)) {
3493 err = PTR_ERR(handler_rx);
3494 goto err;
3495 }
3496
3497 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3498 if (IS_ERR(handler_tx)) {
3499 err = PTR_ERR(handler_tx);
3500 goto err_tx;
3501 }
3502
3503 list_add(&handler_tx->list, &handler_rx->list);
3504
3505 return handler_rx;
3506
3507err_tx:
74491de9 3508 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3509 ft_rx->refcount--;
3510 kfree(handler_rx);
3511err:
3512 return ERR_PTR(err);
3513}
3514
038d2ef8
MG		 3515static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3516 struct ib_flow_attr *flow_attr,
59082a32
MB		 3517 int domain,
3518 struct ib_udata *udata)
038d2ef8
MG		 3519{
3520 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3521 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3522 struct mlx5_ib_flow_handler *handler = NULL;
3523 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3524 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3525 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3526 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3527 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3528 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3529 int err;
a550ddfc 3530 int underlay_qpn;
038d2ef8 3531
3b3233fb
RS		 3532 if (udata && udata->inlen) {
3533 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3534 sizeof(ucmd_hdr.reserved);
3535 if (udata->inlen < min_ucmd_sz)
3536 return ERR_PTR(-EOPNOTSUPP);
3537
3538 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3539 if (err)
3540 return ERR_PTR(err);
3541
3542 /* currently supports only one counters data */
3543 if (ucmd_hdr.ncounters_data > 1)
3544 return ERR_PTR(-EINVAL);
3545
3546 required_ucmd_sz = min_ucmd_sz +
3547 sizeof(struct mlx5_ib_flow_counters_data) *
3548 ucmd_hdr.ncounters_data;
3549 if (udata->inlen > required_ucmd_sz &&
3550 !ib_is_udata_cleared(udata, required_ucmd_sz,
3551 udata->inlen - required_ucmd_sz))
3552 return ERR_PTR(-EOPNOTSUPP);
3553
3554 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3555 if (!ucmd)
3556 return ERR_PTR(-ENOMEM);
3557
3558 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3559 if (err) {
3560 kfree(ucmd);
3561 return ERR_PTR(err);
3562 }
3563 }
59082a32 3564
038d2ef8 3565 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 3566 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 3567
3568 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3569 flow_attr->port > dev->num_ports ||
802c2125
AY		 3570 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3571 IB_FLOW_ATTR_FLAGS_EGRESS)))
3572 return ERR_PTR(-EINVAL);
3573
3574 if (is_egress &&
3575 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3576 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT))
038d2ef8
MG		 3577 return ERR_PTR(-EINVAL);
3578
3579 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3580 if (!dst)
3581 return ERR_PTR(-ENOMEM);
3582
9a4ca38d 3583 mutex_lock(&dev->flow_db->lock);
038d2ef8 3584
802c2125
AY		 3585 ft_prio = get_flow_table(dev, flow_attr,
3586 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3587 if (IS_ERR(ft_prio)) {
3588 err = PTR_ERR(ft_prio);
3589 goto unlock;
3590 }
cc0e5d42
MG		 3591 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3592 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3593 if (IS_ERR(ft_prio_tx)) {
3594 err = PTR_ERR(ft_prio_tx);
3595 ft_prio_tx = NULL;
3596 goto destroy_ft;
3597 }
3598 }
038d2ef8 3599
802c2125
AY		 3600 if (is_egress) {
3601 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3602 } else {
3603 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3604 if (mqp->flags & MLX5_IB_QP_RSS)
3605 dst->tir_num = mqp->rss_qp.tirn;
3606 else
3607 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3608 }
038d2ef8
MG		 3609
3610 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3611 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3612 handler = create_dont_trap_rule(dev, ft_prio,
3613 flow_attr, dst);
3614 } else {
a550ddfc
YH		 3615 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3616 mqp->underlay_qpn : 0;
3617 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3618 dst, underlay_qpn, ucmd);
35d19011 3619 }
038d2ef8
MG		 3620 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3621 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3622 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3623 dst);
cc0e5d42
MG		 3624 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3625 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3626 } else {
3627 err = -EINVAL;
3628 goto destroy_ft;
3629 }
3630
3631 if (IS_ERR(handler)) {
3632 err = PTR_ERR(handler);
3633 handler = NULL;
3634 goto destroy_ft;
3635 }
3636
9a4ca38d 3637 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3638 kfree(dst);
3b3233fb 3639 kfree(ucmd);
038d2ef8
MG		 3640
3641 return &handler->ibflow;
3642
3643destroy_ft:
3644 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3645 if (ft_prio_tx)
3646 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3647unlock:
9a4ca38d 3648 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3649 kfree(dst);
3b3233fb 3650 kfree(ucmd);
038d2ef8
MG		 3651 kfree(handler);
3652 return ERR_PTR(err);
3653}
3654
d4be3f44
YH		 3655static struct mlx5_ib_flow_prio *_get_flow_table(struct mlx5_ib_dev *dev,
3656 int priority, bool mcast)
3657{
3658 int max_table_size;
3659 struct mlx5_flow_namespace *ns = NULL;
3660 struct mlx5_ib_flow_prio *prio;
3661
3662 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3663 log_max_ft_size));
3664 if (max_table_size < MLX5_FS_MAX_ENTRIES)
3665 return ERR_PTR(-ENOMEM);
3666
3667 if (mcast)
3668 priority = MLX5_IB_FLOW_MCAST_PRIO;
3669 else
3670 priority = ib_prio_to_core_prio(priority, false);
3671
3672 ns = mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS);
3673 if (!ns)
3674 return ERR_PTR(-ENOTSUPP);
3675
3676 prio = &dev->flow_db->prios[priority];
3677
3678 if (prio->flow_table)
3679 return prio;
3680
3681 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES,
3682 MLX5_FS_MAX_TYPES);
3683}
3684
3685static struct mlx5_ib_flow_handler *
3686_create_raw_flow_rule(struct mlx5_ib_dev *dev,
3687 struct mlx5_ib_flow_prio *ft_prio,
3688 struct mlx5_flow_destination *dst,
3689 struct mlx5_ib_flow_matcher *fs_matcher,
3690 void *cmd_in, int inlen)
3691{
3692 struct mlx5_ib_flow_handler *handler;
3693 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3694 struct mlx5_flow_spec *spec;
3695 struct mlx5_flow_table *ft = ft_prio->flow_table;
3696 int err = 0;
3697
3698 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3699 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3700 if (!handler || !spec) {
3701 err = -ENOMEM;
3702 goto free;
3703 }
3704
3705 INIT_LIST_HEAD(&handler->list);
3706
3707 memcpy(spec->match_value, cmd_in, inlen);
3708 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3709 fs_matcher->mask_len);
3710 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3711
3712 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3713 handler->rule = mlx5_add_flow_rules(ft, spec,
3714 &flow_act, dst, 1);
3715
3716 if (IS_ERR(handler->rule)) {
3717 err = PTR_ERR(handler->rule);
3718 goto free;
3719 }
3720
3721 ft_prio->refcount++;
3722 handler->prio = ft_prio;
3723 handler->dev = dev;
3724 ft_prio->flow_table = ft;
3725
3726free:
3727 if (err)
3728 kfree(handler);
3729 kvfree(spec);
3730 return err ? ERR_PTR(err) : handler;
3731}
3732
3733static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
3734 void *match_v)
3735{
3736 void *match_c;
3737 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
3738 void *dmac, *dmac_mask;
3739 void *ipv4, *ipv4_mask;
3740
3741 if (!(fs_matcher->match_criteria_enable &
3742 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
3743 return false;
3744
3745 match_c = fs_matcher->matcher_mask.match_params;
3746 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
3747 outer_headers);
3748 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
3749 outer_headers);
3750
3751 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3752 dmac_47_16);
3753 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3754 dmac_47_16);
3755
3756 if (is_multicast_ether_addr(dmac) &&
3757 is_multicast_ether_addr(dmac_mask))
3758 return true;
3759
3760 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3761 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3762
3763 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3764 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3765
3766 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
3767 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
3768 return true;
3769
3770 return false;
3771}
3772
32269441
YH		 3773struct mlx5_ib_flow_handler *
3774mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
3775 struct mlx5_ib_flow_matcher *fs_matcher,
3776 void *cmd_in, int inlen, int dest_id,
3777 int dest_type)
3778{
d4be3f44
YH		 3779 struct mlx5_flow_destination *dst;
3780 struct mlx5_ib_flow_prio *ft_prio;
3781 int priority = fs_matcher->priority;
3782 struct mlx5_ib_flow_handler *handler;
3783 bool mcast;
3784 int err;
3785
3786 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
3787 return ERR_PTR(-EOPNOTSUPP);
3788
3789 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
3790 return ERR_PTR(-ENOMEM);
3791
d4be3f44
YH		 3792 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3793 if (!dst)
3794 return ERR_PTR(-ENOMEM);
3795
3796 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
3797 mutex_lock(&dev->flow_db->lock);
3798
3799 ft_prio = _get_flow_table(dev, priority, mcast);
3800 if (IS_ERR(ft_prio)) {
3801 err = PTR_ERR(ft_prio);
3802 goto unlock;
3803 }
3804
6346f0bf
YH		 3805 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
3806 dst->type = dest_type;
3807 dst->tir_num = dest_id;
3808 } else {
3809 dst->type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
3810 dst->ft_num = dest_id;
3811 }
3812
d4be3f44
YH		 3813 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, cmd_in,
3814 inlen);
3815
3816 if (IS_ERR(handler)) {
3817 err = PTR_ERR(handler);
3818 goto destroy_ft;
3819 }
3820
3821 mutex_unlock(&dev->flow_db->lock);
3822 atomic_inc(&fs_matcher->usecnt);
3823 handler->flow_matcher = fs_matcher;
3824
3825 kfree(dst);
3826
3827 return handler;
3828
3829destroy_ft:
3830 put_flow_table(dev, ft_prio, false);
3831unlock:
3832 mutex_unlock(&dev->flow_db->lock);
3833 kfree(dst);
3834
3835 return ERR_PTR(err);
32269441
YH		 3836}
3837
c6475a0b
AY		 3838static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3839{
3840 u32 flags = 0;
3841
3842 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3843 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3844
3845 return flags;
3846}
3847
3848#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3849static struct ib_flow_action *
3850mlx5_ib_create_flow_action_esp(struct ib_device *device,
3851 const struct ib_flow_action_attrs_esp *attr,
3852 struct uverbs_attr_bundle *attrs)
3853{
3854 struct mlx5_ib_dev *mdev = to_mdev(device);
3855 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3856 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3857 struct mlx5_ib_flow_action *action;
3858 u64 action_flags;
3859 u64 flags;
3860 int err = 0;
3861
bccd0622
JG		 3862 err = uverbs_get_flags64(
3863 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3864 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
3865 if (err)
3866 return ERR_PTR(err);
c6475a0b
AY		 3867
3868 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3869
3870 /* We current only support a subset of the standard features. Only a
3871 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3872 * (with overlap). Full offload mode isn't supported.
3873 */
3874 if (!attr->keymat || attr->replay || attr->encap ||
3875 attr->spi || attr->seq || attr->tfc_pad ||
3876 attr->hard_limit_pkts ||
3877 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3878 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3879 return ERR_PTR(-EOPNOTSUPP);
3880
3881 if (attr->keymat->protocol !=
3882 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3883 return ERR_PTR(-EOPNOTSUPP);
3884
3885 aes_gcm = &attr->keymat->keymat.aes_gcm;
3886
3887 if (aes_gcm->icv_len != 16 ||
3888 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3889 return ERR_PTR(-EOPNOTSUPP);
3890
3891 action = kmalloc(sizeof(*action), GFP_KERNEL);
3892 if (!action)
3893 return ERR_PTR(-ENOMEM);
3894
3895 action->esp_aes_gcm.ib_flags = attr->flags;
3896 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3897 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3898 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3899 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3900 sizeof(accel_attrs.keymat.aes_gcm.salt));
3901 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3902 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3903 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3904 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3905 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3906
3907 accel_attrs.esn = attr->esn;
3908 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3909 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3910 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3911 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3912
3913 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3914 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3915
3916 action->esp_aes_gcm.ctx =
3917 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3918 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3919 err = PTR_ERR(action->esp_aes_gcm.ctx);
3920 goto err_parse;
3921 }
3922
3923 action->esp_aes_gcm.ib_flags = attr->flags;
3924
3925 return &action->ib_action;
3926
3927err_parse:
3928 kfree(action);
3929 return ERR_PTR(err);
3930}
3931
349705c1
MB		 3932static int
3933mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3934 const struct ib_flow_action_attrs_esp *attr,
3935 struct uverbs_attr_bundle *attrs)
3936{
3937 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3938 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3939 int err = 0;
3940
3941 if (attr->keymat || attr->replay || attr->encap ||
3942 attr->spi || attr->seq || attr->tfc_pad ||
3943 attr->hard_limit_pkts ||
3944 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3945 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3946 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3947 return -EOPNOTSUPP;
3948
3949 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3950 * be modified.
3951 */
3952 if (!(maction->esp_aes_gcm.ib_flags &
3953 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3954 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3955 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3956 return -EINVAL;
3957
3958 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3959 sizeof(accel_attrs));
3960
3961 accel_attrs.esn = attr->esn;
3962 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3963 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3964 else
3965 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3966
3967 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3968 &accel_attrs);
3969 if (err)
3970 return err;
3971
3972 maction->esp_aes_gcm.ib_flags &=
3973 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3974 maction->esp_aes_gcm.ib_flags |=
3975 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3976
3977 return 0;
3978}
3979
c6475a0b
AY		 3980static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
3981{
3982 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3983
3984 switch (action->type) {
3985 case IB_FLOW_ACTION_ESP:
3986 /*
3987 * We only support aes_gcm by now, so we implicitly know this is
3988 * the underline crypto.
3989 */
3990 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
3991 break;
3992 default:
3993 WARN_ON(true);
3994 break;
3995 }
3996
3997 kfree(maction);
3998 return 0;
3999}
4000
e126ba97
EC		 4001static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4002{
4003 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 4004 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 4005 int err;
4006
81e30880
YH		 4007 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4008 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4009 return -EOPNOTSUPP;
4010 }
4011
9603b61d 4012 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 4013 if (err)
4014 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4015 ibqp->qp_num, gid->raw);
4016
4017 return err;
4018}
4019
4020static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4021{
4022 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4023 int err;
4024
9603b61d 4025 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 4026 if (err)
4027 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4028 ibqp->qp_num, gid->raw);
4029
4030 return err;
4031}
4032
4033static int init_node_data(struct mlx5_ib_dev *dev)
4034{
1b5daf11 4035 int err;
e126ba97 4036
1b5daf11 4037 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 4038 if (err)
1b5daf11 4039 return err;
e126ba97 4040
1b5daf11 4041 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 4042
1b5daf11 4043 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 4044}
4045
4046static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
4047 char *buf)
4048{
4049 struct mlx5_ib_dev *dev =
4050 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4051
9603b61d 4052 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 4053}
4054
4055static ssize_t show_reg_pages(struct device *device,
4056 struct device_attribute *attr, char *buf)
4057{
4058 struct mlx5_ib_dev *dev =
4059 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4060
6aec21f6 4061 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 4062}
4063
4064static ssize_t show_hca(struct device *device, struct device_attribute *attr,
4065 char *buf)
4066{
4067 struct mlx5_ib_dev *dev =
4068 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 4069 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 4070}
4071
e126ba97
EC		 4072static ssize_t show_rev(struct device *device, struct device_attribute *attr,
4073 char *buf)
4074{
4075 struct mlx5_ib_dev *dev =
4076 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 4077 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 4078}
4079
4080static ssize_t show_board(struct device *device, struct device_attribute *attr,
4081 char *buf)
4082{
4083 struct mlx5_ib_dev *dev =
4084 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4085 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 4086 dev->mdev->board_id);
e126ba97
EC		 4087}
4088
4089static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 4090static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
4091static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
4092static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
4093static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
4094
4095static struct device_attribute *mlx5_class_attributes[] = {
4096 &dev_attr_hw_rev,
e126ba97
EC		 4097 &dev_attr_hca_type,
4098 &dev_attr_board_id,
4099 &dev_attr_fw_pages,
4100 &dev_attr_reg_pages,
4101};
4102
7722f47e
HE		 4103static void pkey_change_handler(struct work_struct *work)
4104{
4105 struct mlx5_ib_port_resources *ports =
4106 container_of(work, struct mlx5_ib_port_resources,
4107 pkey_change_work);
4108
4109 mutex_lock(&ports->devr->mutex);
4110 mlx5_ib_gsi_pkey_change(ports->gsi);
4111 mutex_unlock(&ports->devr->mutex);
4112}
4113
89ea94a7
MG		 4114static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4115{
4116 struct mlx5_ib_qp *mqp;
4117 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4118 struct mlx5_core_cq *mcq;
4119 struct list_head cq_armed_list;
4120 unsigned long flags_qp;
4121 unsigned long flags_cq;
4122 unsigned long flags;
4123
4124 INIT_LIST_HEAD(&cq_armed_list);
4125
4126 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4127 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4128 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4129 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4130 if (mqp->sq.tail != mqp->sq.head) {
4131 send_mcq = to_mcq(mqp->ibqp.send_cq);
4132 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4133 if (send_mcq->mcq.comp &&
4134 mqp->ibqp.send_cq->comp_handler) {
4135 if (!send_mcq->mcq.reset_notify_added) {
4136 send_mcq->mcq.reset_notify_added = 1;
4137 list_add_tail(&send_mcq->mcq.reset_notify,
4138 &cq_armed_list);
4139 }
4140 }
4141 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4142 }
4143 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4144 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4145 /* no handling is needed for SRQ */
4146 if (!mqp->ibqp.srq) {
4147 if (mqp->rq.tail != mqp->rq.head) {
4148 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4149 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4150 if (recv_mcq->mcq.comp &&
4151 mqp->ibqp.recv_cq->comp_handler) {
4152 if (!recv_mcq->mcq.reset_notify_added) {
4153 recv_mcq->mcq.reset_notify_added = 1;
4154 list_add_tail(&recv_mcq->mcq.reset_notify,
4155 &cq_armed_list);
4156 }
4157 }
4158 spin_unlock_irqrestore(&recv_mcq->lock,
4159 flags_cq);
4160 }
4161 }
4162 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4163 }
4164 /*At that point all inflight post send were put to be executed as of we
4165 * lock/unlock above locks Now need to arm all involved CQs.
4166 */
4167 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4168 mcq->comp(mcq);
4169 }
4170 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4171}
4172
03404e8a
MG		 4173static void delay_drop_handler(struct work_struct *work)
4174{
4175 int err;
4176 struct mlx5_ib_delay_drop *delay_drop =
4177 container_of(work, struct mlx5_ib_delay_drop,
4178 delay_drop_work);
4179
fe248c3a
MG		 4180 atomic_inc(&delay_drop->events_cnt);
4181
03404e8a
MG		 4182 mutex_lock(&delay_drop->lock);
4183 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4184 delay_drop->timeout);
4185 if (err) {
4186 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4187 delay_drop->timeout);
4188 delay_drop->activate = false;
4189 }
4190 mutex_unlock(&delay_drop->lock);
4191}
4192
d69a24e0 4193static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 4194{
d69a24e0
DJ		 4195 struct mlx5_ib_event_work *work =
4196 container_of(_work, struct mlx5_ib_event_work, work);
4197 struct mlx5_ib_dev *ibdev;
e126ba97 4198 struct ib_event ibev;
dbaaff2a 4199 bool fatal = false;
aba46213 4200 u8 port = (u8)work->param;
e126ba97 4201
d69a24e0
DJ		 4202 if (mlx5_core_is_mp_slave(work->dev)) {
4203 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
4204 if (!ibdev)
4205 goto out;
4206 } else {
4207 ibdev = work->context;
4208 }
4209
4210 switch (work->event) {
e126ba97 4211 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4212 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4213 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 4214 fatal = true;
e126ba97
EC		 4215 break;
4216
4217 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 4218 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 4219 case MLX5_DEV_EVENT_PORT_INITIALIZED:
5ec8c83e
AH		 4220 /* In RoCE, port up/down events are handled in
4221 * mlx5_netdev_event().
4222 */
4223 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4224 IB_LINK_LAYER_ETHERNET)
d69a24e0 4225 goto out;
5ec8c83e 4226
d69a24e0 4227 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
5ec8c83e 4228 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 4229 break;
4230
e126ba97
EC		 4231 case MLX5_DEV_EVENT_LID_CHANGE:
4232 ibev.event = IB_EVENT_LID_CHANGE;
e126ba97
EC		 4233 break;
4234
4235 case MLX5_DEV_EVENT_PKEY_CHANGE:
4236 ibev.event = IB_EVENT_PKEY_CHANGE;
7722f47e 4237 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 4238 break;
4239
4240 case MLX5_DEV_EVENT_GUID_CHANGE:
4241 ibev.event = IB_EVENT_GID_CHANGE;
e126ba97
EC		 4242 break;
4243
4244 case MLX5_DEV_EVENT_CLIENT_REREG:
4245 ibev.event = IB_EVENT_CLIENT_REREGISTER;
e126ba97 4246 break;
03404e8a
MG		 4247 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
4248 schedule_work(&ibdev->delay_drop.delay_drop_work);
4249 goto out;
bdc37924 4250 default:
03404e8a 4251 goto out;
e126ba97
EC		 4252 }
4253
4254 ibev.device = &ibdev->ib_dev;
4255 ibev.element.port_num = port;
4256
aba46213 4257 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
a0c84c32 4258 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 4259 goto out;
a0c84c32
EC		 4260 }
4261
e126ba97
EC		 4262 if (ibdev->ib_active)
4263 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4264
4265 if (fatal)
4266 ibdev->ib_active = false;
03404e8a 4267out:
d69a24e0
DJ		 4268 kfree(work);
4269}
4270
4271static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4272 enum mlx5_dev_event event, unsigned long param)
4273{
4274 struct mlx5_ib_event_work *work;
4275
4276 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4277 if (!work)
d69a24e0 4278 return;
d69a24e0 4279
10bea9c8
LR		 4280 INIT_WORK(&work->work, mlx5_ib_handle_event);
4281 work->dev = dev;
4282 work->param = param;
4283 work->context = context;
4284 work->event = event;
4285
4286 queue_work(mlx5_ib_event_wq, &work->work);
e126ba97
EC		 4287}
4288
c43f1112
MG		 4289static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4290{
4291 struct mlx5_hca_vport_context vport_ctx;
4292 int err;
4293 int port;
4294
508562d6 4295 for (port = 1; port <= dev->num_ports; port++) {
c43f1112
MG		 4296 dev->mdev->port_caps[port - 1].has_smi = false;
4297 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4298 MLX5_CAP_PORT_TYPE_IB) {
4299 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4300 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4301 port, 0,
4302 &vport_ctx);
4303 if (err) {
4304 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4305 port, err);
4306 return err;
4307 }
4308 dev->mdev->port_caps[port - 1].has_smi =
4309 vport_ctx.has_smi;
4310 } else {
4311 dev->mdev->port_caps[port - 1].has_smi = true;
4312 }
4313 }
4314 }
4315 return 0;
4316}
4317
e126ba97
EC		 4318static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4319{
4320 int port;
4321
508562d6 4322 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4323 mlx5_query_ext_port_caps(dev, port);
4324}
4325
32f69e4b 4326static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4327{
4328 struct ib_device_attr *dprops = NULL;
4329 struct ib_port_attr *pprops = NULL;
f614fc15 4330 int err = -ENOMEM;
2528e33e 4331 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 4332
4333 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4334 if (!pprops)
4335 goto out;
4336
4337 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4338 if (!dprops)
4339 goto out;
4340
c43f1112
MG		 4341 err = set_has_smi_cap(dev);
4342 if (err)
4343 goto out;
4344
2528e33e 4345 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 4346 if (err) {
4347 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4348 goto out;
4349 }
4350
32f69e4b
DJ		 4351 memset(pprops, 0, sizeof(*pprops));
4352 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4353 if (err) {
4354 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4355 port, err);
4356 goto out;
e126ba97
EC		 4357 }
4358
32f69e4b
DJ		 4359 dev->mdev->port_caps[port - 1].pkey_table_len =
4360 dprops->max_pkeys;
4361 dev->mdev->port_caps[port - 1].gid_table_len =
4362 pprops->gid_tbl_len;
4363 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4364 port, dprops->max_pkeys, pprops->gid_tbl_len);
4365
e126ba97
EC		 4366out:
4367 kfree(pprops);
4368 kfree(dprops);
4369
4370 return err;
4371}
4372
4373static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4374{
4375 int err;
4376
4377 err = mlx5_mr_cache_cleanup(dev);
4378 if (err)
4379 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4380
32927e28
MB		 4381 if (dev->umrc.qp)
4382 mlx5_ib_destroy_qp(dev->umrc.qp);
4383 if (dev->umrc.cq)
4384 ib_free_cq(dev->umrc.cq);
4385 if (dev->umrc.pd)
4386 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4387}
4388
4389enum {
4390 MAX_UMR_WR = 128,
4391};
4392
4393static int create_umr_res(struct mlx5_ib_dev *dev)
4394{
4395 struct ib_qp_init_attr *init_attr = NULL;
4396 struct ib_qp_attr *attr = NULL;
4397 struct ib_pd *pd;
4398 struct ib_cq *cq;
4399 struct ib_qp *qp;
e126ba97
EC		 4400 int ret;
4401
4402 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4403 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4404 if (!attr || !init_attr) {
4405 ret = -ENOMEM;
4406 goto error_0;
4407 }
4408
ed082d36 4409 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4410 if (IS_ERR(pd)) {
4411 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4412 ret = PTR_ERR(pd);
4413 goto error_0;
4414 }
4415
add08d76 4416 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4417 if (IS_ERR(cq)) {
4418 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4419 ret = PTR_ERR(cq);
4420 goto error_2;
4421 }
e126ba97
EC		 4422
4423 init_attr->send_cq = cq;
4424 init_attr->recv_cq = cq;
4425 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4426 init_attr->cap.max_send_wr = MAX_UMR_WR;
4427 init_attr->cap.max_send_sge = 1;
4428 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4429 init_attr->port_num = 1;
4430 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4431 if (IS_ERR(qp)) {
4432 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4433 ret = PTR_ERR(qp);
4434 goto error_3;
4435 }
4436 qp->device = &dev->ib_dev;
4437 qp->real_qp = qp;
4438 qp->uobject = NULL;
4439 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4440 qp->send_cq = init_attr->send_cq;
4441 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4442
4443 attr->qp_state = IB_QPS_INIT;
4444 attr->port_num = 1;
4445 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4446 IB_QP_PORT, NULL);
4447 if (ret) {
4448 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4449 goto error_4;
4450 }
4451
4452 memset(attr, 0, sizeof(*attr));
4453 attr->qp_state = IB_QPS_RTR;
4454 attr->path_mtu = IB_MTU_256;
4455
4456 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4457 if (ret) {
4458 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4459 goto error_4;
4460 }
4461
4462 memset(attr, 0, sizeof(*attr));
4463 attr->qp_state = IB_QPS_RTS;
4464 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4465 if (ret) {
4466 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4467 goto error_4;
4468 }
4469
4470 dev->umrc.qp = qp;
4471 dev->umrc.cq = cq;
e126ba97
EC		 4472 dev->umrc.pd = pd;
4473
4474 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4475 ret = mlx5_mr_cache_init(dev);
4476 if (ret) {
4477 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4478 goto error_4;
4479 }
4480
4481 kfree(attr);
4482 kfree(init_attr);
4483
4484 return 0;
4485
4486error_4:
4487 mlx5_ib_destroy_qp(qp);
32927e28 4488 dev->umrc.qp = NULL;
e126ba97
EC		 4489
4490error_3:
add08d76 4491 ib_free_cq(cq);
32927e28 4492 dev->umrc.cq = NULL;
e126ba97
EC		 4493
4494error_2:
e126ba97 4495 ib_dealloc_pd(pd);
32927e28 4496 dev->umrc.pd = NULL;
e126ba97
EC		 4497
4498error_0:
4499 kfree(attr);
4500 kfree(init_attr);
4501 return ret;
4502}
4503
6e8484c5
MG		 4504static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4505{
4506 switch (umr_fence_cap) {
4507 case MLX5_CAP_UMR_FENCE_NONE:
4508 return MLX5_FENCE_MODE_NONE;
4509 case MLX5_CAP_UMR_FENCE_SMALL:
4510 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4511 default:
4512 return MLX5_FENCE_MODE_STRONG_ORDERING;
4513 }
4514}
4515
e126ba97
EC		 4516static int create_dev_resources(struct mlx5_ib_resources *devr)
4517{
4518 struct ib_srq_init_attr attr;
4519 struct mlx5_ib_dev *dev;
bcf4c1ea 4520 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4521 int port;
e126ba97
EC		 4522 int ret = 0;
4523
4524 dev = container_of(devr, struct mlx5_ib_dev, devr);
4525
d16e91da
HE		 4526 mutex_init(&devr->mutex);
4527
e126ba97
EC		 4528 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4529 if (IS_ERR(devr->p0)) {
4530 ret = PTR_ERR(devr->p0);
4531 goto error0;
4532 }
4533 devr->p0->device = &dev->ib_dev;
4534 devr->p0->uobject = NULL;
4535 atomic_set(&devr->p0->usecnt, 0);
4536
bcf4c1ea 4537 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 4538 if (IS_ERR(devr->c0)) {
4539 ret = PTR_ERR(devr->c0);
4540 goto error1;
4541 }
4542 devr->c0->device = &dev->ib_dev;
4543 devr->c0->uobject = NULL;
4544 devr->c0->comp_handler = NULL;
4545 devr->c0->event_handler = NULL;
4546 devr->c0->cq_context = NULL;
4547 atomic_set(&devr->c0->usecnt, 0);
4548
4549 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4550 if (IS_ERR(devr->x0)) {
4551 ret = PTR_ERR(devr->x0);
4552 goto error2;
4553 }
4554 devr->x0->device = &dev->ib_dev;
4555 devr->x0->inode = NULL;
4556 atomic_set(&devr->x0->usecnt, 0);
4557 mutex_init(&devr->x0->tgt_qp_mutex);
4558 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4559
4560 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4561 if (IS_ERR(devr->x1)) {
4562 ret = PTR_ERR(devr->x1);
4563 goto error3;
4564 }
4565 devr->x1->device = &dev->ib_dev;
4566 devr->x1->inode = NULL;
4567 atomic_set(&devr->x1->usecnt, 0);
4568 mutex_init(&devr->x1->tgt_qp_mutex);
4569 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4570
4571 memset(&attr, 0, sizeof(attr));
4572 attr.attr.max_sge = 1;
4573 attr.attr.max_wr = 1;
4574 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4575 attr.ext.cq = devr->c0;
e126ba97
EC		 4576 attr.ext.xrc.xrcd = devr->x0;
4577
4578 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4579 if (IS_ERR(devr->s0)) {
4580 ret = PTR_ERR(devr->s0);
4581 goto error4;
4582 }
4583 devr->s0->device = &dev->ib_dev;
4584 devr->s0->pd = devr->p0;
4585 devr->s0->uobject = NULL;
4586 devr->s0->event_handler = NULL;
4587 devr->s0->srq_context = NULL;
4588 devr->s0->srq_type = IB_SRQT_XRC;
4589 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 4590 devr->s0->ext.cq = devr->c0;
e126ba97 4591 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 4592 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 4593 atomic_inc(&devr->p0->usecnt);
4594 atomic_set(&devr->s0->usecnt, 0);
4595
4aa17b28
HA		 4596 memset(&attr, 0, sizeof(attr));
4597 attr.attr.max_sge = 1;
4598 attr.attr.max_wr = 1;
4599 attr.srq_type = IB_SRQT_BASIC;
4600 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4601 if (IS_ERR(devr->s1)) {
4602 ret = PTR_ERR(devr->s1);
4603 goto error5;
4604 }
4605 devr->s1->device = &dev->ib_dev;
4606 devr->s1->pd = devr->p0;
4607 devr->s1->uobject = NULL;
4608 devr->s1->event_handler = NULL;
4609 devr->s1->srq_context = NULL;
4610 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 4611 devr->s1->ext.cq = devr->c0;
4aa17b28 4612 atomic_inc(&devr->p0->usecnt);
1a56ff6d 4613 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 4614
7722f47e
HE		 4615 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4616 INIT_WORK(&devr->ports[port].pkey_change_work,
4617 pkey_change_handler);
4618 devr->ports[port].devr = devr;
4619 }
4620
e126ba97
EC		 4621 return 0;
4622
4aa17b28
HA		 4623error5:
4624 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 4625error4:
4626 mlx5_ib_dealloc_xrcd(devr->x1);
4627error3:
4628 mlx5_ib_dealloc_xrcd(devr->x0);
4629error2:
4630 mlx5_ib_destroy_cq(devr->c0);
4631error1:
4632 mlx5_ib_dealloc_pd(devr->p0);
4633error0:
4634 return ret;
4635}
4636
4637static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4638{
7722f47e
HE		 4639 struct mlx5_ib_dev *dev =
4640 container_of(devr, struct mlx5_ib_dev, devr);
4641 int port;
4642
4aa17b28 4643 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 4644 mlx5_ib_destroy_srq(devr->s0);
4645 mlx5_ib_dealloc_xrcd(devr->x0);
4646 mlx5_ib_dealloc_xrcd(devr->x1);
4647 mlx5_ib_destroy_cq(devr->c0);
4648 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 4649
4650 /* Make sure no change P_Key work items are still executing */
4651 for (port = 0; port < dev->num_ports; ++port)
4652 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 4653}
4654
b02289b3
AK		 4655static u32 get_core_cap_flags(struct ib_device *ibdev,
4656 struct mlx5_hca_vport_context *rep)
e53505a8
AS		 4657{
4658 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4659 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4660 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4661 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 4662 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 4663 u32 ret = 0;
4664
b02289b3
AK		 4665 if (rep->grh_required)
4666 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
4667
e53505a8 4668 if (ll == IB_LINK_LAYER_INFINIBAND)
b02289b3 4669 return ret | RDMA_CORE_PORT_IBA_IB;
e53505a8 4670
85c7c014 4671 if (raw_support)
b02289b3 4672 ret |= RDMA_CORE_PORT_RAW_PACKET;
72cd5717 4673
e53505a8 4674 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 4675 return ret;
e53505a8
AS		 4676
4677 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 4678 return ret;
e53505a8
AS		 4679
4680 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4681 ret |= RDMA_CORE_PORT_IBA_ROCE;
4682
4683 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4684 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4685
4686 return ret;
4687}
4688
7738613e
IW		 4689static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4690 struct ib_port_immutable *immutable)
4691{
4692 struct ib_port_attr attr;
ca5b91d6
OG		 4693 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4694 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
b02289b3 4695 struct mlx5_hca_vport_context rep = {0};
7738613e
IW		 4696 int err;
4697
c4550c63 4698 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 4699 if (err)
4700 return err;
4701
b02289b3
AK		 4702 if (ll == IB_LINK_LAYER_INFINIBAND) {
4703 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
4704 &rep);
4705 if (err)
4706 return err;
4707 }
4708
7738613e
IW		 4709 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4710 immutable->gid_tbl_len = attr.gid_tbl_len;
b02289b3 4711 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
ca5b91d6
OG		 4712 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4713 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 4714
4715 return 0;
4716}
4717
8e6efa3a
MB		 4718static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4719 struct ib_port_immutable *immutable)
4720{
4721 struct ib_port_attr attr;
4722 int err;
4723
4724 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4725
4726 err = ib_query_port(ibdev, port_num, &attr);
4727 if (err)
4728 return err;
4729
4730 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4731 immutable->gid_tbl_len = attr.gid_tbl_len;
4732 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4733
4734 return 0;
4735}
4736
9abb0d1b 4737static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 4738{
4739 struct mlx5_ib_dev *dev =
4740 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 4741 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4742 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4743 fw_rev_sub(dev->mdev));
c7342823
IW		 4744}
4745
45f95acd 4746static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4747{
4748 struct mlx5_core_dev *mdev = dev->mdev;
4749 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4750 MLX5_FLOW_NAMESPACE_LAG);
4751 struct mlx5_flow_table *ft;
4752 int err;
4753
4754 if (!ns || !mlx5_lag_is_active(mdev))
4755 return 0;
4756
4757 err = mlx5_cmd_create_vport_lag(mdev);
4758 if (err)
4759 return err;
4760
4761 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4762 if (IS_ERR(ft)) {
4763 err = PTR_ERR(ft);
4764 goto err_destroy_vport_lag;
4765 }
4766
9a4ca38d 4767 dev->flow_db->lag_demux_ft = ft;
9ef9c640
AH		 4768 return 0;
4769
4770err_destroy_vport_lag:
4771 mlx5_cmd_destroy_vport_lag(mdev);
4772 return err;
4773}
4774
45f95acd 4775static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4776{
4777 struct mlx5_core_dev *mdev = dev->mdev;
4778
9a4ca38d
MB		 4779 if (dev->flow_db->lag_demux_ft) {
4780 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4781 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 4782
4783 mlx5_cmd_destroy_vport_lag(mdev);
4784 }
4785}
4786
7fd8aefb 4787static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 4788{
4789 int err;
4790
7fd8aefb
DJ		 4791 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4792 err = register_netdevice_notifier(&dev->roce[port_num].nb);
d012f5d6 4793 if (err) {
7fd8aefb 4794 dev->roce[port_num].nb.notifier_call = NULL;
d012f5d6
OG		 4795 return err;
4796 }
4797
4798 return 0;
4799}
4800
7fd8aefb 4801static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 4802{
7fd8aefb
DJ		 4803 if (dev->roce[port_num].nb.notifier_call) {
4804 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4805 dev->roce[port_num].nb.notifier_call = NULL;
5ec8c83e
AH		 4806 }
4807}
4808
e3f1ed1f 4809static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4810{
e53505a8
AS		 4811 int err;
4812
ca5b91d6
OG		 4813 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4814 err = mlx5_nic_vport_enable_roce(dev->mdev);
4815 if (err)
8e6efa3a 4816 return err;
ca5b91d6 4817 }
e53505a8 4818
45f95acd 4819 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 4820 if (err)
4821 goto err_disable_roce;
4822
e53505a8
AS		 4823 return 0;
4824
9ef9c640 4825err_disable_roce:
ca5b91d6
OG		 4826 if (MLX5_CAP_GEN(dev->mdev, roce))
4827 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 4828
e53505a8 4829 return err;
fc24fc5e
AS		 4830}
4831
45f95acd 4832static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4833{
45f95acd 4834 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 4835 if (MLX5_CAP_GEN(dev->mdev, roce))
4836 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 4837}
4838
e1f24a79 4839struct mlx5_ib_counter {
7c16f477
KH		 4840 const char *name;
4841 size_t offset;
4842};
4843
4844#define INIT_Q_COUNTER(_name) \
4845 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4846
e1f24a79 4847static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 4848 INIT_Q_COUNTER(rx_write_requests),
4849 INIT_Q_COUNTER(rx_read_requests),
4850 INIT_Q_COUNTER(rx_atomic_requests),
4851 INIT_Q_COUNTER(out_of_buffer),
4852};
4853
e1f24a79 4854static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 4855 INIT_Q_COUNTER(out_of_sequence),
4856};
4857
e1f24a79 4858static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 4859 INIT_Q_COUNTER(duplicate_request),
4860 INIT_Q_COUNTER(rnr_nak_retry_err),
4861 INIT_Q_COUNTER(packet_seq_err),
4862 INIT_Q_COUNTER(implied_nak_seq_err),
4863 INIT_Q_COUNTER(local_ack_timeout_err),
4864};
4865
e1f24a79
PP		 4866#define INIT_CONG_COUNTER(_name) \
4867 { .name = #_name, .offset = \
4868 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4869
4870static const struct mlx5_ib_counter cong_cnts[] = {
4871 INIT_CONG_COUNTER(rp_cnp_ignored),
4872 INIT_CONG_COUNTER(rp_cnp_handled),
4873 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4874 INIT_CONG_COUNTER(np_cnp_sent),
4875};
4876
58dcb60a
PP		 4877static const struct mlx5_ib_counter extended_err_cnts[] = {
4878 INIT_Q_COUNTER(resp_local_length_error),
4879 INIT_Q_COUNTER(resp_cqe_error),
4880 INIT_Q_COUNTER(req_cqe_error),
4881 INIT_Q_COUNTER(req_remote_invalid_request),
4882 INIT_Q_COUNTER(req_remote_access_errors),
4883 INIT_Q_COUNTER(resp_remote_access_errors),
4884 INIT_Q_COUNTER(resp_cqe_flush_error),
4885 INIT_Q_COUNTER(req_cqe_flush_error),
4886};
4887
9f876f3d
TB		 4888#define INIT_EXT_PPCNT_COUNTER(_name) \
4889 { .name = #_name, .offset = \
4890 MLX5_BYTE_OFF(ppcnt_reg, \
4891 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
4892
4893static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
4894 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
4895};
4896
e1f24a79 4897static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 4898{
aac4492e 4899 int i;
0837e86a 4900
7c16f477 4901 for (i = 0; i < dev->num_ports; i++) {
921c0f5b 4902 if (dev->port[i].cnts.set_id_valid)
aac4492e
DJ		 4903 mlx5_core_dealloc_q_counter(dev->mdev,
4904 dev->port[i].cnts.set_id);
e1f24a79
PP		 4905 kfree(dev->port[i].cnts.names);
4906 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 4907 }
4908}
4909
e1f24a79
PP		 4910static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4911 struct mlx5_ib_counters *cnts)
7c16f477
KH		 4912{
4913 u32 num_counters;
4914
4915 num_counters = ARRAY_SIZE(basic_q_cnts);
4916
4917 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4918 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4919
4920 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4921 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 4922
4923 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4924 num_counters += ARRAY_SIZE(extended_err_cnts);
4925
e1f24a79 4926 cnts->num_q_counters = num_counters;
7c16f477 4927
e1f24a79
PP		 4928 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4929 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4930 num_counters += ARRAY_SIZE(cong_cnts);
4931 }
9f876f3d
TB		 4932 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4933 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
4934 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
4935 }
e1f24a79
PP		 4936 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4937 if (!cnts->names)
7c16f477
KH		 4938 return -ENOMEM;
4939
e1f24a79
PP		 4940 cnts->offsets = kcalloc(num_counters,
4941 sizeof(cnts->offsets), GFP_KERNEL);
4942 if (!cnts->offsets)
7c16f477
KH		 4943 goto err_names;
4944
7c16f477
KH		 4945 return 0;
4946
4947err_names:
e1f24a79 4948 kfree(cnts->names);
aac4492e 4949 cnts->names = NULL;
7c16f477
KH		 4950 return -ENOMEM;
4951}
4952
e1f24a79
PP		 4953static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4954 const char **names,
4955 size_t *offsets)
7c16f477
KH		 4956{
4957 int i;
4958 int j = 0;
4959
4960 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4961 names[j] = basic_q_cnts[i].name;
4962 offsets[j] = basic_q_cnts[i].offset;
4963 }
4964
4965 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4966 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4967 names[j] = out_of_seq_q_cnts[i].name;
4968 offsets[j] = out_of_seq_q_cnts[i].offset;
4969 }
4970 }
4971
4972 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4973 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4974 names[j] = retrans_q_cnts[i].name;
4975 offsets[j] = retrans_q_cnts[i].offset;
4976 }
4977 }
e1f24a79 4978
58dcb60a
PP		 4979 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4980 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4981 names[j] = extended_err_cnts[i].name;
4982 offsets[j] = extended_err_cnts[i].offset;
4983 }
4984 }
4985
e1f24a79
PP		 4986 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4987 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4988 names[j] = cong_cnts[i].name;
4989 offsets[j] = cong_cnts[i].offset;
4990 }
4991 }
9f876f3d
TB		 4992
4993 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4994 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
4995 names[j] = ext_ppcnt_cnts[i].name;
4996 offsets[j] = ext_ppcnt_cnts[i].offset;
4997 }
4998 }
0837e86a
MB		 4999}
5000
e1f24a79 5001static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5002{
aac4492e 5003 int err = 0;
0837e86a 5004 int i;
0837e86a
MB		 5005
5006 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 5007 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5008 if (err)
5009 goto err_alloc;
5010
5011 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5012 dev->port[i].cnts.offsets);
7c16f477 5013
aac4492e
DJ		 5014 err = mlx5_core_alloc_q_counter(dev->mdev,
5015 &dev->port[i].cnts.set_id);
5016 if (err) {
0837e86a
MB		 5017 mlx5_ib_warn(dev,
5018 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 5019 i + 1, err);
5020 goto err_alloc;
0837e86a 5021 }
aac4492e 5022 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 5023 }
5024
5025 return 0;
5026
aac4492e
DJ		 5027err_alloc:
5028 mlx5_ib_dealloc_counters(dev);
5029 return err;
0837e86a
MB		 5030}
5031
0ad17a8f
MB		 5032static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5033 u8 port_num)
5034{
7c16f477
KH		 5035 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5036 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 5037
5038 /* We support only per port stats */
5039 if (port_num == 0)
5040 return NULL;
5041
e1f24a79
PP		 5042 return rdma_alloc_hw_stats_struct(port->cnts.names,
5043 port->cnts.num_q_counters +
9f876f3d
TB		 5044 port->cnts.num_cong_counters +
5045 port->cnts.num_ext_ppcnt_counters,
0ad17a8f
MB		 5046 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5047}
5048
aac4492e 5049static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
e1f24a79
PP		 5050 struct mlx5_ib_port *port,
5051 struct rdma_hw_stats *stats)
0ad17a8f 5052{
0ad17a8f
MB		 5053 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5054 void *out;
5055 __be32 val;
e1f24a79 5056 int ret, i;
0ad17a8f 5057
1b9a07ee 5058 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 5059 if (!out)
5060 return -ENOMEM;
5061
aac4492e 5062 ret = mlx5_core_query_q_counter(mdev,
e1f24a79 5063 port->cnts.set_id, 0,
0ad17a8f
MB		 5064 out, outlen);
5065 if (ret)
5066 goto free;
5067
e1f24a79
PP		 5068 for (i = 0; i < port->cnts.num_q_counters; i++) {
5069 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 5070 stats->value[i] = (u64)be32_to_cpu(val);
5071 }
7c16f477 5072
0ad17a8f
MB		 5073free:
5074 kvfree(out);
e1f24a79
PP		 5075 return ret;
5076}
5077
9f876f3d
TB		 5078static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5079 struct mlx5_ib_port *port,
5080 struct rdma_hw_stats *stats)
5081{
5082 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5083 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5084 int ret, i;
5085 void *out;
5086
5087 out = kvzalloc(sz, GFP_KERNEL);
5088 if (!out)
5089 return -ENOMEM;
5090
5091 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5092 if (ret)
5093 goto free;
5094
5095 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5096 stats->value[i + offset] =
5097 be64_to_cpup((__be64 *)(out +
5098 port->cnts.offsets[i + offset]));
5099 }
5100
5101free:
5102 kvfree(out);
5103 return ret;
5104}
5105
e1f24a79
PP		 5106static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5107 struct rdma_hw_stats *stats,
5108 u8 port_num, int index)
5109{
5110 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5111 struct mlx5_ib_port *port = &dev->port[port_num - 1];
aac4492e 5112 struct mlx5_core_dev *mdev;
e1f24a79 5113 int ret, num_counters;
aac4492e 5114 u8 mdev_port_num;
e1f24a79
PP		 5115
5116 if (!stats)
5117 return -EINVAL;
5118
9f876f3d
TB		 5119 num_counters = port->cnts.num_q_counters +
5120 port->cnts.num_cong_counters +
5121 port->cnts.num_ext_ppcnt_counters;
aac4492e
DJ		 5122
5123 /* q_counters are per IB device, query the master mdev */
5124 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
e1f24a79
PP		 5125 if (ret)
5126 return ret;
e1f24a79 5127
9f876f3d
TB		 5128 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5129 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5130 if (ret)
5131 return ret;
5132 }
5133
e1f24a79 5134 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 5135 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5136 &mdev_port_num);
5137 if (!mdev) {
5138 /* If port is not affiliated yet, its in down state
5139 * which doesn't have any counters yet, so it would be
5140 * zero. So no need to read from the HCA.
5141 */
5142 goto done;
5143 }
71a0ff65
MD		 5144 ret = mlx5_lag_query_cong_counters(dev->mdev,
5145 stats->value +
5146 port->cnts.num_q_counters,
5147 port->cnts.num_cong_counters,
5148 port->cnts.offsets +
5149 port->cnts.num_q_counters);
aac4492e
DJ		 5150
5151 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 5152 if (ret)
5153 return ret;
e1f24a79
PP		 5154 }
5155
aac4492e 5156done:
e1f24a79 5157 return num_counters;
0ad17a8f
MB		 5158}
5159
693dfd5a
ES		 5160static struct net_device*
5161mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
5162 u8 port_num,
5163 enum rdma_netdev_t type,
5164 const char *name,
5165 unsigned char name_assign_type,
5166 void (*setup)(struct net_device *))
5167{
8e959601 5168 struct net_device *netdev;
8e959601 5169
693dfd5a
ES		 5170 if (type != RDMA_NETDEV_IPOIB)
5171 return ERR_PTR(-EOPNOTSUPP);
5172
8e959601
NV		 5173 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
5174 name, setup);
8e959601 5175 return netdev;
693dfd5a
ES		 5176}
5177
fe248c3a
MG		 5178static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5179{
5180 if (!dev->delay_drop.dbg)
5181 return;
5182 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5183 kfree(dev->delay_drop.dbg);
5184 dev->delay_drop.dbg = NULL;
5185}
5186
03404e8a
MG		 5187static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5188{
5189 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5190 return;
5191
5192 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 5193 delay_drop_debugfs_cleanup(dev);
5194}
5195
5196static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5197 size_t count, loff_t *pos)
5198{
5199 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5200 char lbuf[20];
5201 int len;
5202
5203 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5204 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5205}
5206
5207static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5208 size_t count, loff_t *pos)
5209{
5210 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5211 u32 timeout;
5212 u32 var;
5213
5214 if (kstrtouint_from_user(buf, count, 0, &var))
5215 return -EFAULT;
5216
5217 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5218 1000);
5219 if (timeout != var)
5220 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5221 timeout);
5222
5223 delay_drop->timeout = timeout;
5224
5225 return count;
5226}
5227
5228static const struct file_operations fops_delay_drop_timeout = {
5229 .owner = THIS_MODULE,
5230 .open = simple_open,
5231 .write = delay_drop_timeout_write,
5232 .read = delay_drop_timeout_read,
5233};
5234
5235static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5236{
5237 struct mlx5_ib_dbg_delay_drop *dbg;
5238
5239 if (!mlx5_debugfs_root)
5240 return 0;
5241
5242 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5243 if (!dbg)
5244 return -ENOMEM;
5245
cbafad87
SM		 5246 dev->delay_drop.dbg = dbg;
5247
fe248c3a
MG		 5248 dbg->dir_debugfs =
5249 debugfs_create_dir("delay_drop",
5250 dev->mdev->priv.dbg_root);
5251 if (!dbg->dir_debugfs)
cbafad87 5252 goto out_debugfs;
fe248c3a
MG		 5253
5254 dbg->events_cnt_debugfs =
5255 debugfs_create_atomic_t("num_timeout_events", 0400,
5256 dbg->dir_debugfs,
5257 &dev->delay_drop.events_cnt);
5258 if (!dbg->events_cnt_debugfs)
5259 goto out_debugfs;
5260
5261 dbg->rqs_cnt_debugfs =
5262 debugfs_create_atomic_t("num_rqs", 0400,
5263 dbg->dir_debugfs,
5264 &dev->delay_drop.rqs_cnt);
5265 if (!dbg->rqs_cnt_debugfs)
5266 goto out_debugfs;
5267
5268 dbg->timeout_debugfs =
5269 debugfs_create_file("timeout", 0600,
5270 dbg->dir_debugfs,
5271 &dev->delay_drop,
5272 &fops_delay_drop_timeout);
5273 if (!dbg->timeout_debugfs)
5274 goto out_debugfs;
5275
5276 return 0;
5277
5278out_debugfs:
5279 delay_drop_debugfs_cleanup(dev);
5280 return -ENOMEM;
03404e8a
MG		 5281}
5282
5283static void init_delay_drop(struct mlx5_ib_dev *dev)
5284{
5285 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5286 return;
5287
5288 mutex_init(&dev->delay_drop.lock);
5289 dev->delay_drop.dev = dev;
5290 dev->delay_drop.activate = false;
5291 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5292 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5293 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5294 atomic_set(&dev->delay_drop.events_cnt, 0);
5295
5296 if (delay_drop_debugfs_init(dev))
5297 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 5298}
5299
84305d71
LR		 5300static const struct cpumask *
5301mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 5302{
5303 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5304
6082d9c9 5305 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
40b24403
SG		 5306}
5307
32f69e4b
DJ		 5308/* The mlx5_ib_multiport_mutex should be held when calling this function */
5309static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5310 struct mlx5_ib_multiport_info *mpi)
5311{
5312 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5313 struct mlx5_ib_port *port = &ibdev->port[port_num];
5314 int comps;
5315 int err;
5316 int i;
5317
a9e546e7
PP		 5318 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5319
32f69e4b
DJ		 5320 spin_lock(&port->mp.mpi_lock);
5321 if (!mpi->ibdev) {
5322 spin_unlock(&port->mp.mpi_lock);
5323 return;
5324 }
5325 mpi->ibdev = NULL;
5326
5327 spin_unlock(&port->mp.mpi_lock);
5328 mlx5_remove_netdev_notifier(ibdev, port_num);
5329 spin_lock(&port->mp.mpi_lock);
5330
5331 comps = mpi->mdev_refcnt;
5332 if (comps) {
5333 mpi->unaffiliate = true;
5334 init_completion(&mpi->unref_comp);
5335 spin_unlock(&port->mp.mpi_lock);
5336
5337 for (i = 0; i < comps; i++)
5338 wait_for_completion(&mpi->unref_comp);
5339
5340 spin_lock(&port->mp.mpi_lock);
5341 mpi->unaffiliate = false;
5342 }
5343
5344 port->mp.mpi = NULL;
5345
5346 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5347
5348 spin_unlock(&port->mp.mpi_lock);
5349
5350 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5351
5352 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5353 /* Log an error, still needed to cleanup the pointers and add
5354 * it back to the list.
5355 */
5356 if (err)
5357 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5358 port_num + 1);
5359
5360 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5361}
5362
5363/* The mlx5_ib_multiport_mutex should be held when calling this function */
5364static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5365 struct mlx5_ib_multiport_info *mpi)
5366{
5367 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5368 int err;
5369
5370 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5371 if (ibdev->port[port_num].mp.mpi) {
2577188e
QH		 5372 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5373 port_num + 1);
32f69e4b
DJ		 5374 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5375 return false;
5376 }
5377
5378 ibdev->port[port_num].mp.mpi = mpi;
5379 mpi->ibdev = ibdev;
5380 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5381
5382 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5383 if (err)
5384 goto unbind;
5385
5386 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5387 if (err)
5388 goto unbind;
5389
5390 err = mlx5_add_netdev_notifier(ibdev, port_num);
5391 if (err) {
5392 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5393 port_num + 1);
5394 goto unbind;
5395 }
5396
a9e546e7
PP		 5397 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5398 if (err)
5399 goto unbind;
5400
32f69e4b
DJ		 5401 return true;
5402
5403unbind:
5404 mlx5_ib_unbind_slave_port(ibdev, mpi);
5405 return false;
5406}
5407
5408static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5409{
5410 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5411 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5412 port_num + 1);
5413 struct mlx5_ib_multiport_info *mpi;
5414 int err;
5415 int i;
5416
5417 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5418 return 0;
5419
5420 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5421 &dev->sys_image_guid);
5422 if (err)
5423 return err;
5424
5425 err = mlx5_nic_vport_enable_roce(dev->mdev);
5426 if (err)
5427 return err;
5428
5429 mutex_lock(&mlx5_ib_multiport_mutex);
5430 for (i = 0; i < dev->num_ports; i++) {
5431 bool bound = false;
5432
5433 /* build a stub multiport info struct for the native port. */
5434 if (i == port_num) {
5435 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5436 if (!mpi) {
5437 mutex_unlock(&mlx5_ib_multiport_mutex);
5438 mlx5_nic_vport_disable_roce(dev->mdev);
5439 return -ENOMEM;
5440 }
5441
5442 mpi->is_master = true;
5443 mpi->mdev = dev->mdev;
5444 mpi->sys_image_guid = dev->sys_image_guid;
5445 dev->port[i].mp.mpi = mpi;
5446 mpi->ibdev = dev;
5447 mpi = NULL;
5448 continue;
5449 }
5450
5451 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5452 list) {
5453 if (dev->sys_image_guid == mpi->sys_image_guid &&
5454 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5455 bound = mlx5_ib_bind_slave_port(dev, mpi);
5456 }
5457
5458 if (bound) {
5459 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5460 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5461 list_del(&mpi->list);
5462 break;
5463 }
5464 }
5465 if (!bound) {
5466 get_port_caps(dev, i + 1);
5467 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5468 i + 1);
5469 }
5470 }
5471
5472 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5473 mutex_unlock(&mlx5_ib_multiport_mutex);
5474 return err;
5475}
5476
5477static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5478{
5479 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5480 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5481 port_num + 1);
5482 int i;
5483
5484 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5485 return;
5486
5487 mutex_lock(&mlx5_ib_multiport_mutex);
5488 for (i = 0; i < dev->num_ports; i++) {
5489 if (dev->port[i].mp.mpi) {
5490 /* Destroy the native port stub */
5491 if (i == port_num) {
5492 kfree(dev->port[i].mp.mpi);
5493 dev->port[i].mp.mpi = NULL;
5494 } else {
5495 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5496 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5497 }
5498 }
5499 }
5500
5501 mlx5_ib_dbg(dev, "removing from devlist\n");
5502 list_del(&dev->ib_dev_list);
5503 mutex_unlock(&mlx5_ib_multiport_mutex);
5504
5505 mlx5_nic_vport_disable_roce(dev->mdev);
5506}
5507
9a119cd5
JG		 5508ADD_UVERBS_ATTRIBUTES_SIMPLE(
5509 mlx5_ib_dm,
5510 UVERBS_OBJECT_DM,
5511 UVERBS_METHOD_DM_ALLOC,
5512 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5513 UVERBS_ATTR_TYPE(u64),
83bb4442 5514 UA_MANDATORY),
9a119cd5
JG		 5515 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5516 UVERBS_ATTR_TYPE(u16),
83bb4442 5517 UA_MANDATORY));
9a119cd5
JG		 5518
5519ADD_UVERBS_ATTRIBUTES_SIMPLE(
5520 mlx5_ib_flow_action,
5521 UVERBS_OBJECT_FLOW_ACTION,
5522 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
bccd0622
JG		 5523 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5524 enum mlx5_ib_uapi_flow_action_flags));
c6475a0b 5525
cb80fb18 5526#define NUM_TREES 5
8c84660b
MB		 5527static int populate_specs_root(struct mlx5_ib_dev *dev)
5528{
5529 const struct uverbs_object_tree_def *default_root[NUM_TREES + 1] = {
5530 uverbs_default_get_objects()};
5531 size_t num_trees = 1;
5532
c6475a0b
AY		 5533 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE &&
5534 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
5535 default_root[num_trees++] = &mlx5_ib_flow_action;
5536
24da0016
AL		 5537 if (MLX5_CAP_DEV_MEM(dev->mdev, memic) &&
5538 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
5539 default_root[num_trees++] = &mlx5_ib_dm;
5540
c59450c4
YH		 5541 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
5542 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX &&
5543 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
5544 default_root[num_trees++] = mlx5_ib_get_devx_tree();
5545
cb80fb18
YH		 5546 num_trees += mlx5_ib_get_flow_trees(default_root + num_trees);
5547
87fc2a62 5548 dev->ib_dev.driver_specs_root =
8c84660b
MB		 5549 uverbs_alloc_spec_tree(num_trees, default_root);
5550
87fc2a62 5551 return PTR_ERR_OR_ZERO(dev->ib_dev.driver_specs_root);
8c84660b
MB		 5552}
5553
5554static void depopulate_specs_root(struct mlx5_ib_dev *dev)
5555{
87fc2a62 5556 uverbs_free_spec_tree(dev->ib_dev.driver_specs_root);
8c84660b
MB		 5557}
5558
1a1e03dc
RS		 5559static int mlx5_ib_read_counters(struct ib_counters *counters,
5560 struct ib_counters_read_attr *read_attr,
5561 struct uverbs_attr_bundle *attrs)
5562{
5563 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5564 struct mlx5_read_counters_attr mread_attr = {};
5565 struct mlx5_ib_flow_counters_desc *desc;
5566 int ret, i;
5567
5568 mutex_lock(&mcounters->mcntrs_mutex);
5569 if (mcounters->cntrs_max_index > read_attr->ncounters) {
5570 ret = -EINVAL;
5571 goto err_bound;
5572 }
5573
5574 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5575 GFP_KERNEL);
5576 if (!mread_attr.out) {
5577 ret = -ENOMEM;
5578 goto err_bound;
5579 }
5580
5581 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5582 mread_attr.flags = read_attr->flags;
5583 ret = mcounters->read_counters(counters->device, &mread_attr);
5584 if (ret)
5585 goto err_read;
5586
5587 /* do the pass over the counters data array to assign according to the
5588 * descriptions and indexing pairs
5589 */
5590 desc = mcounters->counters_data;
5591 for (i = 0; i < mcounters->ncounters; i++)
5592 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5593
5594err_read:
5595 kfree(mread_attr.out);
5596err_bound:
5597 mutex_unlock(&mcounters->mcntrs_mutex);
5598 return ret;
5599}
5600
b29e2a13
RS		 5601static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5602{
5603 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5604
3b3233fb
RS		 5605 counters_clear_description(counters);
5606 if (mcounters->hw_cntrs_hndl)
5607 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5608 mcounters->hw_cntrs_hndl);
5609
b29e2a13
RS		 5610 kfree(mcounters);
5611
5612 return 0;
5613}
5614
5615static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5616 struct uverbs_attr_bundle *attrs)
5617{
5618 struct mlx5_ib_mcounters *mcounters;
5619
5620 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5621 if (!mcounters)
5622 return ERR_PTR(-ENOMEM);
5623
3b3233fb
RS		 5624 mutex_init(&mcounters->mcntrs_mutex);
5625
b29e2a13
RS		 5626 return &mcounters->ibcntrs;
5627}
5628
b5ca15ad 5629void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 5630{
32f69e4b 5631 mlx5_ib_cleanup_multiport_master(dev);
3cc297db
MB		 5632#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5633 cleanup_srcu_struct(&dev->mr_srcu);
5634#endif
16c1975f
MB		 5635 kfree(dev->port);
5636}
5637
b5ca15ad 5638int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5639{
5640 struct mlx5_core_dev *mdev = dev->mdev;
4babcf97 5641 const char *name;
e126ba97 5642 int err;
32f69e4b 5643 int i;
e126ba97 5644
508562d6 5645 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
0837e86a
MB		 5646 GFP_KERNEL);
5647 if (!dev->port)
16c1975f 5648 return -ENOMEM;
0837e86a 5649
32f69e4b
DJ		 5650 for (i = 0; i < dev->num_ports; i++) {
5651 spin_lock_init(&dev->port[i].mp.mpi_lock);
5652 rwlock_init(&dev->roce[i].netdev_lock);
5653 }
5654
5655 err = mlx5_ib_init_multiport_master(dev);
e126ba97 5656 if (err)
0837e86a 5657 goto err_free_port;
e126ba97 5658
32f69e4b 5659 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 5660 for (i = 1; i <= dev->num_ports; i++) {
5661 err = get_port_caps(dev, i);
5662 if (err)
5663 break;
5664 }
5665 } else {
5666 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5667 }
5668 if (err)
5669 goto err_mp;
5670
1b5daf11
MD		 5671 if (mlx5_use_mad_ifc(dev))
5672 get_ext_port_caps(dev);
e126ba97 5673
4babcf97
AH		 5674 if (!mlx5_lag_is_active(mdev))
5675 name = "mlx5_%d";
5676 else
5677 name = "mlx5_bond_%d";
5678
5679 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 5680 dev->ib_dev.owner = THIS_MODULE;
5681 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 5682 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 5683 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 5684 dev->ib_dev.num_comp_vectors =
5685 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 5686 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97 5687
3cc297db
MB		 5688 mutex_init(&dev->cap_mask_mutex);
5689 INIT_LIST_HEAD(&dev->qp_list);
5690 spin_lock_init(&dev->reset_flow_resource_lock);
5691
24da0016
AL		 5692 spin_lock_init(&dev->memic.memic_lock);
5693 dev->memic.dev = mdev;
5694
3cc297db
MB		 5695#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5696 err = init_srcu_struct(&dev->mr_srcu);
5697 if (err)
5698 goto err_free_port;
5699#endif
5700
16c1975f 5701 return 0;
32f69e4b
DJ		 5702err_mp:
5703 mlx5_ib_cleanup_multiport_master(dev);
16c1975f
MB		 5704
5705err_free_port:
5706 kfree(dev->port);
5707
5708 return -ENOMEM;
5709}
5710
9a4ca38d
MB		 5711static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5712{
5713 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5714
5715 if (!dev->flow_db)
5716 return -ENOMEM;
5717
5718 mutex_init(&dev->flow_db->lock);
5719
5720 return 0;
5721}
5722
b5ca15ad
MB		 5723int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5724{
5725 struct mlx5_ib_dev *nic_dev;
5726
5727 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5728
5729 if (!nic_dev)
5730 return -EINVAL;
5731
5732 dev->flow_db = nic_dev->flow_db;
5733
5734 return 0;
5735}
5736
9a4ca38d
MB		 5737static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5738{
5739 kfree(dev->flow_db);
5740}
5741
b5ca15ad 5742int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5743{
5744 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 5745 int err;
5746
e126ba97
EC		 5747 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
5748 dev->ib_dev.uverbs_cmd_mask =
5749 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
5750 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
5751 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
5752 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
5753 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 5754 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
5755 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 5756 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 5757 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 5758 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
5759 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5760 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
5761 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
5762 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
5763 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
5764 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
5765 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
5766 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
5767 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
5768 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
5769 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
5770 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5771 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5772 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5773 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5774 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 5775 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 5776 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5777 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 5778 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d
YC		 5779 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
5780 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
e126ba97
EC		 5781
5782 dev->ib_dev.query_device = mlx5_ib_query_device;
ebd61f68 5783 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
e126ba97 5784 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 5785 dev->ib_dev.add_gid = mlx5_ib_add_gid;
5786 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 5787 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
5788 dev->ib_dev.modify_device = mlx5_ib_modify_device;
5789 dev->ib_dev.modify_port = mlx5_ib_modify_port;
5790 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
5791 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
5792 dev->ib_dev.mmap = mlx5_ib_mmap;
5793 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
5794 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
5795 dev->ib_dev.create_ah = mlx5_ib_create_ah;
5796 dev->ib_dev.query_ah = mlx5_ib_query_ah;
5797 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
5798 dev->ib_dev.create_srq = mlx5_ib_create_srq;
5799 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
5800 dev->ib_dev.query_srq = mlx5_ib_query_srq;
5801 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
5802 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
5803 dev->ib_dev.create_qp = mlx5_ib_create_qp;
5804 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
5805 dev->ib_dev.query_qp = mlx5_ib_query_qp;
5806 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
d0e84c0a
YH		 5807 dev->ib_dev.drain_sq = mlx5_ib_drain_sq;
5808 dev->ib_dev.drain_rq = mlx5_ib_drain_rq;
e126ba97
EC		 5809 dev->ib_dev.post_send = mlx5_ib_post_send;
5810 dev->ib_dev.post_recv = mlx5_ib_post_recv;
5811 dev->ib_dev.create_cq = mlx5_ib_create_cq;
5812 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
5813 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
5814 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
5815 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
5816 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
5817 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
5818 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 5819 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 5820 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
5821 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
5822 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
5823 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 5824 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 5825 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 5826 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
c7342823 5827 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 5828 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 5829 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 5830 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 5831
eff901d3
EC		 5832 if (mlx5_core_is_pf(mdev)) {
5833 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
5834 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
5835 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
5836 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
5837 }
e126ba97 5838
7c2344c3
MG		 5839 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5840
6e8484c5
MG		 5841 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5842
d2370e0a
MB		 5843 if (MLX5_CAP_GEN(mdev, imaicl)) {
5844 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
5845 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
5846 dev->ib_dev.uverbs_cmd_mask |=
5847 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
5848 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5849 }
5850
938fe83c 5851 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 5852 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5853 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5854 dev->ib_dev.uverbs_cmd_mask |=
5855 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5856 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5857 }
5858
24da0016
AL		 5859 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5860 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5861 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
6c29f57e 5862 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
24da0016
AL		 5863 }
5864
81e30880
YH		 5865 dev->ib_dev.create_flow = mlx5_ib_create_flow;
5866 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5867 dev->ib_dev.uverbs_ex_cmd_mask |=
5868 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5869 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
c6475a0b
AY		 5870 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5871 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
349705c1 5872 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
0ede73bc 5873 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
b29e2a13
RS		 5874 dev->ib_dev.create_counters = mlx5_ib_create_counters;
5875 dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters;
1a1e03dc 5876 dev->ib_dev.read_counters = mlx5_ib_read_counters;
81e30880 5877
e126ba97
EC		 5878 err = init_node_data(dev);
5879 if (err)
16c1975f 5880 return err;
e126ba97 5881
c8b89924 5882 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 5883 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5884 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c8b89924
MB		 5885 mutex_init(&dev->lb_mutex);
5886
16c1975f
MB		 5887 return 0;
5888}
5889
8e6efa3a
MB		 5890static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5891{
5892 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
5893 dev->ib_dev.query_port = mlx5_ib_query_port;
5894
5895 return 0;
5896}
5897
b5ca15ad 5898int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 5899{
5900 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
5901 dev->ib_dev.query_port = mlx5_ib_rep_query_port;
5902
5903 return 0;
5904}
5905
e3f1ed1f 5906static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a 5907{
e3f1ed1f 5908 u8 port_num;
8e6efa3a
MB		 5909 int i;
5910
5911 for (i = 0; i < dev->num_ports; i++) {
5912 dev->roce[i].dev = dev;
5913 dev->roce[i].native_port_num = i + 1;
5914 dev->roce[i].last_port_state = IB_PORT_DOWN;
5915 }
5916
5917 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
5918 dev->ib_dev.create_wq = mlx5_ib_create_wq;
5919 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
5920 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
5921 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5922 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5923
5924 dev->ib_dev.uverbs_ex_cmd_mask |=
5925 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5926 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5927 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5928 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5929 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5930
e3f1ed1f
LR		 5931 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5932
8e6efa3a
MB		 5933 return mlx5_add_netdev_notifier(dev, port_num);
5934}
5935
5936static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5937{
5938 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5939
5940 mlx5_remove_netdev_notifier(dev, port_num);
5941}
5942
5943int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5944{
5945 struct mlx5_core_dev *mdev = dev->mdev;
5946 enum rdma_link_layer ll;
5947 int port_type_cap;
5948 int err = 0;
8e6efa3a 5949
8e6efa3a
MB		 5950 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5951 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5952
5953 if (ll == IB_LINK_LAYER_ETHERNET)
e3f1ed1f 5954 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 5955
5956 return err;
5957}
5958
5959void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5960{
5961 mlx5_ib_stage_common_roce_cleanup(dev);
5962}
5963
16c1975f
MB		 5964static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5965{
5966 struct mlx5_core_dev *mdev = dev->mdev;
5967 enum rdma_link_layer ll;
5968 int port_type_cap;
5969 int err;
5970
5971 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5972 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5973
fc24fc5e 5974 if (ll == IB_LINK_LAYER_ETHERNET) {
e3f1ed1f 5975 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 5976 if (err)
5977 return err;
7fd8aefb 5978
e3f1ed1f 5979 err = mlx5_enable_eth(dev);
fc24fc5e 5980 if (err)
8e6efa3a 5981 goto cleanup;
fc24fc5e
AS		 5982 }
5983
16c1975f 5984 return 0;
8e6efa3a
MB		 5985cleanup:
5986 mlx5_ib_stage_common_roce_cleanup(dev);
5987
5988 return err;
16c1975f 5989}
e126ba97 5990
16c1975f
MB		 5991static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
5992{
5993 struct mlx5_core_dev *mdev = dev->mdev;
5994 enum rdma_link_layer ll;
5995 int port_type_cap;
e126ba97 5996
16c1975f
MB		 5997 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5998 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5999
6000 if (ll == IB_LINK_LAYER_ETHERNET) {
6001 mlx5_disable_eth(dev);
8e6efa3a 6002 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 6003 }
16c1975f 6004}
6aec21f6 6005
b5ca15ad 6006int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6007{
6008 return create_dev_resources(&dev->devr);
6009}
6010
b5ca15ad 6011void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6012{
6013 destroy_dev_resources(&dev->devr);
6014}
6015
6016static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6017{
07321b3c
MB		 6018 mlx5_ib_internal_fill_odp_caps(dev);
6019
16c1975f
MB		 6020 return mlx5_ib_odp_init_one(dev);
6021}
4a2da0b8 6022
b5ca15ad 6023int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 6024{
5e1e7612
MB		 6025 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6026 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
6027 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
6028
6029 return mlx5_ib_alloc_counters(dev);
6030 }
16c1975f
MB		 6031
6032 return 0;
6033}
6034
b5ca15ad 6035void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6036{
6037 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6038 mlx5_ib_dealloc_counters(dev);
6039}
6040
6041static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6042{
a9e546e7
PP		 6043 return mlx5_ib_init_cong_debugfs(dev,
6044 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6045}
6046
6047static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6048{
a9e546e7
PP		 6049 mlx5_ib_cleanup_cong_debugfs(dev,
6050 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6051}
6052
6053static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6054{
5fe9dec0 6055 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 6056 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 6057}
6058
6059static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6060{
6061 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6062}
6063
b5ca15ad 6064int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6065{
6066 int err;
5fe9dec0
EC		 6067
6068 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6069 if (err)
16c1975f 6070 return err;
5fe9dec0
EC		 6071
6072 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6073 if (err)
16c1975f 6074 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 6075
16c1975f
MB		 6076 return err;
6077}
0837e86a 6078
b5ca15ad 6079void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6080{
6081 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6082 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6083}
e126ba97 6084
8c84660b
MB		 6085static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
6086{
6087 return populate_specs_root(dev);
6088}
6089
b5ca15ad 6090int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6091{
6092 return ib_register_device(&dev->ib_dev, NULL);
6093}
6094
8c84660b
MB		 6095static void mlx5_ib_stage_depopulate_specs(struct mlx5_ib_dev *dev)
6096{
6097 depopulate_specs_root(dev);
6098}
6099
03fe2deb 6100void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6101{
42cea83f 6102 destroy_umrc_res(dev);
16c1975f
MB		 6103}
6104
03fe2deb 6105void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6106{
42cea83f 6107 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 6108}
6109
03fe2deb 6110int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 6111{
42cea83f 6112 return create_umr_res(dev);
16c1975f
MB		 6113}
6114
6115static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6116{
03404e8a
MG		 6117 init_delay_drop(dev);
6118
16c1975f
MB		 6119 return 0;
6120}
6121
6122static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6123{
6124 cancel_delay_drop(dev);
6125}
6126
b5ca15ad 6127int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6128{
6129 int err;
6130 int i;
6131
e126ba97 6132 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 6133 err = device_create_file(&dev->ib_dev.dev,
6134 mlx5_class_attributes[i]);
6135 if (err)
16c1975f 6136 return err;
e126ba97
EC		 6137 }
6138
16c1975f
MB		 6139 return 0;
6140}
6141
fc385b7a
MB		 6142static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
6143{
6144 mlx5_ib_register_vport_reps(dev);
6145
6146 return 0;
6147}
6148
6149static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
6150{
6151 mlx5_ib_unregister_vport_reps(dev);
6152}
6153
b5ca15ad
MB		 6154void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6155 const struct mlx5_ib_profile *profile,
6156 int stage)
16c1975f
MB		 6157{
6158 /* Number of stages to cleanup */
6159 while (stage) {
6160 stage--;
6161 if (profile->stage[stage].cleanup)
6162 profile->stage[stage].cleanup(dev);
6163 }
e126ba97 6164
16c1975f
MB		 6165 ib_dealloc_device((struct ib_device *)dev);
6166}
e126ba97 6167
b5ca15ad
MB		 6168void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6169 const struct mlx5_ib_profile *profile)
16c1975f 6170{
16c1975f
MB		 6171 int err;
6172 int i;
e126ba97 6173
16c1975f 6174 printk_once(KERN_INFO "%s", mlx5_version);
5fe9dec0 6175
16c1975f
MB		 6176 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6177 if (profile->stage[i].init) {
6178 err = profile->stage[i].init(dev);
6179 if (err)
6180 goto err_out;
6181 }
6182 }
0837e86a 6183
16c1975f
MB		 6184 dev->profile = profile;
6185 dev->ib_active = true;
6aec21f6 6186
16c1975f 6187 return dev;
e126ba97 6188
16c1975f
MB		 6189err_out:
6190 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 6191
16c1975f
MB		 6192 return NULL;
6193}
0837e86a 6194
16c1975f
MB		 6195static const struct mlx5_ib_profile pf_profile = {
6196 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6197 mlx5_ib_stage_init_init,
6198 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 6199 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6200 mlx5_ib_stage_flow_db_init,
6201 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 6202 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6203 mlx5_ib_stage_caps_init,
6204 NULL),
8e6efa3a
MB		 6205 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6206 mlx5_ib_stage_non_default_cb,
6207 NULL),
16c1975f
MB		 6208 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6209 mlx5_ib_stage_roce_init,
6210 mlx5_ib_stage_roce_cleanup),
6211 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6212 mlx5_ib_stage_dev_res_init,
6213 mlx5_ib_stage_dev_res_cleanup),
6214 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6215 mlx5_ib_stage_odp_init,
3cc297db 6216 NULL),
16c1975f
MB		 6217 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6218 mlx5_ib_stage_counters_init,
6219 mlx5_ib_stage_counters_cleanup),
6220 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6221 mlx5_ib_stage_cong_debugfs_init,
6222 mlx5_ib_stage_cong_debugfs_cleanup),
6223 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6224 mlx5_ib_stage_uar_init,
6225 mlx5_ib_stage_uar_cleanup),
6226 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6227 mlx5_ib_stage_bfrag_init,
6228 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 6229 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6230 NULL,
6231 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 6232 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6233 mlx5_ib_stage_populate_specs,
6234 mlx5_ib_stage_depopulate_specs),
16c1975f
MB		 6235 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6236 mlx5_ib_stage_ib_reg_init,
6237 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 6238 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6239 mlx5_ib_stage_post_ib_reg_umr_init,
6240 NULL),
16c1975f
MB		 6241 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6242 mlx5_ib_stage_delay_drop_init,
6243 mlx5_ib_stage_delay_drop_cleanup),
6244 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6245 mlx5_ib_stage_class_attr_init,
6246 NULL),
16c1975f 6247};
e126ba97 6248
b5ca15ad
MB		 6249static const struct mlx5_ib_profile nic_rep_profile = {
6250 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6251 mlx5_ib_stage_init_init,
6252 mlx5_ib_stage_init_cleanup),
6253 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6254 mlx5_ib_stage_flow_db_init,
6255 mlx5_ib_stage_flow_db_cleanup),
6256 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6257 mlx5_ib_stage_caps_init,
6258 NULL),
6259 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6260 mlx5_ib_stage_rep_non_default_cb,
6261 NULL),
6262 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6263 mlx5_ib_stage_rep_roce_init,
6264 mlx5_ib_stage_rep_roce_cleanup),
6265 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6266 mlx5_ib_stage_dev_res_init,
6267 mlx5_ib_stage_dev_res_cleanup),
6268 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6269 mlx5_ib_stage_counters_init,
6270 mlx5_ib_stage_counters_cleanup),
6271 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6272 mlx5_ib_stage_uar_init,
6273 mlx5_ib_stage_uar_cleanup),
6274 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6275 mlx5_ib_stage_bfrag_init,
6276 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 6277 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6278 NULL,
6279 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 6280 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6281 mlx5_ib_stage_populate_specs,
6282 mlx5_ib_stage_depopulate_specs),
b5ca15ad
MB		 6283 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6284 mlx5_ib_stage_ib_reg_init,
6285 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 6286 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6287 mlx5_ib_stage_post_ib_reg_umr_init,
6288 NULL),
b5ca15ad
MB		 6289 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6290 mlx5_ib_stage_class_attr_init,
6291 NULL),
6292 STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
6293 mlx5_ib_stage_rep_reg_init,
6294 mlx5_ib_stage_rep_reg_cleanup),
6295};
6296
e3f1ed1f 6297static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
32f69e4b
DJ		 6298{
6299 struct mlx5_ib_multiport_info *mpi;
6300 struct mlx5_ib_dev *dev;
6301 bool bound = false;
6302 int err;
6303
6304 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6305 if (!mpi)
6306 return NULL;
6307
6308 mpi->mdev = mdev;
6309
6310 err = mlx5_query_nic_vport_system_image_guid(mdev,
6311 &mpi->sys_image_guid);
6312 if (err) {
6313 kfree(mpi);
6314 return NULL;
6315 }
6316
6317 mutex_lock(&mlx5_ib_multiport_mutex);
6318 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6319 if (dev->sys_image_guid == mpi->sys_image_guid)
6320 bound = mlx5_ib_bind_slave_port(dev, mpi);
6321
6322 if (bound) {
6323 rdma_roce_rescan_device(&dev->ib_dev);
6324 break;
6325 }
6326 }
6327
6328 if (!bound) {
6329 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6330 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 6331 }
6332 mutex_unlock(&mlx5_ib_multiport_mutex);
6333
6334 return mpi;
6335}
6336
16c1975f
MB		 6337static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6338{
32f69e4b 6339 enum rdma_link_layer ll;
b5ca15ad 6340 struct mlx5_ib_dev *dev;
32f69e4b
DJ		 6341 int port_type_cap;
6342
b5ca15ad
MB		 6343 printk_once(KERN_INFO "%s", mlx5_version);
6344
32f69e4b
DJ		 6345 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6346 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6347
e3f1ed1f
LR		 6348 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6349 return mlx5_ib_add_slave_port(mdev);
32f69e4b 6350
b5ca15ad
MB		 6351 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6352 if (!dev)
6353 return NULL;
6354
6355 dev->mdev = mdev;
6356 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6357 MLX5_CAP_GEN(mdev, num_vhca_ports));
6358
6359 if (MLX5_VPORT_MANAGER(mdev) &&
6360 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6361 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
6362
6363 return __mlx5_ib_add(dev, &nic_rep_profile);
6364 }
6365
6366 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 6367}
6368
9603b61d 6369static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 6370{
32f69e4b
DJ		 6371 struct mlx5_ib_multiport_info *mpi;
6372 struct mlx5_ib_dev *dev;
6373
6374 if (mlx5_core_is_mp_slave(mdev)) {
6375 mpi = context;
6376 mutex_lock(&mlx5_ib_multiport_mutex);
6377 if (mpi->ibdev)
6378 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6379 list_del(&mpi->list);
6380 mutex_unlock(&mlx5_ib_multiport_mutex);
6381 return;
6382 }
6aec21f6 6383
32f69e4b 6384 dev = context;
16c1975f 6385 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 6386}
6387
9603b61d
JM		 6388static struct mlx5_interface mlx5_ib_interface = {
6389 .add = mlx5_ib_add,
6390 .remove = mlx5_ib_remove,
6391 .event = mlx5_ib_event,
d9aaed83
AK		 6392#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
6393 .pfault = mlx5_ib_pfault,
6394#endif
64613d94 6395 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 6396};
6397
c44ef998
IL		 6398unsigned long mlx5_ib_get_xlt_emergency_page(void)
6399{
6400 mutex_lock(&xlt_emergency_page_mutex);
6401 return xlt_emergency_page;
6402}
6403
6404void mlx5_ib_put_xlt_emergency_page(void)
6405{
6406 mutex_unlock(&xlt_emergency_page_mutex);
6407}
6408
e126ba97
EC		 6409static int __init mlx5_ib_init(void)
6410{
6aec21f6
HE		 6411 int err;
6412
c44ef998
IL		 6413 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6414 if (!xlt_emergency_page)
6415 return -ENOMEM;
6416
6417 mutex_init(&xlt_emergency_page_mutex);
6418
d69a24e0 6419 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 6420 if (!mlx5_ib_event_wq) {
6421 free_page(xlt_emergency_page);
d69a24e0 6422 return -ENOMEM;
c44ef998 6423 }
d69a24e0 6424
81713d37 6425 mlx5_ib_odp_init();
9603b61d 6426
6aec21f6 6427 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 6428
6aec21f6 6429 return err;
e126ba97
EC		 6430}
6431
6432static void __exit mlx5_ib_cleanup(void)
6433{
9603b61d 6434 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 6435 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 6436 mutex_destroy(&xlt_emergency_page_mutex);
6437 free_page(xlt_emergency_page);
e126ba97
EC		 6438}
6439
6440module_init(mlx5_ib_init);
6441module_exit(mlx5_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)