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IB/mlx5: Avoid using the MAD_IFC command under ISSI > 0 mode
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/sched.h>
42#include <rdma/ib_user_verbs.h>
1b5daf11 43#include <linux/mlx5/vport.h>
e126ba97
EC		 44#include <rdma/ib_smi.h>
45#include <rdma/ib_umem.h>
46#include "user.h"
47#include "mlx5_ib.h"
48
49#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 50#define DRIVER_VERSION "2.2-1"
51#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 52
53MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
54MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRIVER_VERSION);
57
9603b61d
JM		 58static int deprecated_prof_sel = 2;
59module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
60MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 61
62static char mlx5_version[] =
63 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
64 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
65
1b5daf11
MD		 66static enum rdma_link_layer
67mlx5_ib_port_link_layer(struct ib_device *device)
68{
69 struct mlx5_ib_dev *dev = to_mdev(device);
70
71 switch (MLX5_CAP_GEN(dev->mdev, port_type)) {
72 case MLX5_CAP_PORT_TYPE_IB:
73 return IB_LINK_LAYER_INFINIBAND;
74 case MLX5_CAP_PORT_TYPE_ETH:
75 return IB_LINK_LAYER_ETHERNET;
76 default:
77 return IB_LINK_LAYER_UNSPECIFIED;
78 }
79}
80
81static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
82{
83 return !dev->mdev->issi;
84}
85
86enum {
87 MLX5_VPORT_ACCESS_METHOD_MAD,
88 MLX5_VPORT_ACCESS_METHOD_HCA,
89 MLX5_VPORT_ACCESS_METHOD_NIC,
90};
91
92static int mlx5_get_vport_access_method(struct ib_device *ibdev)
93{
94 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
95 return MLX5_VPORT_ACCESS_METHOD_MAD;
96
97 if (mlx5_ib_port_link_layer(ibdev) ==
98 IB_LINK_LAYER_ETHERNET)
99 return MLX5_VPORT_ACCESS_METHOD_NIC;
100
101 return MLX5_VPORT_ACCESS_METHOD_HCA;
102}
103
104static int mlx5_query_system_image_guid(struct ib_device *ibdev,
105 __be64 *sys_image_guid)
106{
107 struct mlx5_ib_dev *dev = to_mdev(ibdev);
108 struct mlx5_core_dev *mdev = dev->mdev;
109 u64 tmp;
110 int err;
111
112 switch (mlx5_get_vport_access_method(ibdev)) {
113 case MLX5_VPORT_ACCESS_METHOD_MAD:
114 return mlx5_query_mad_ifc_system_image_guid(ibdev,
115 sys_image_guid);
116
117 case MLX5_VPORT_ACCESS_METHOD_HCA:
118 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
119 if (!err)
120 *sys_image_guid = cpu_to_be64(tmp);
121 return err;
122
123 default:
124 return -EINVAL;
125 }
126}
127
128static int mlx5_query_max_pkeys(struct ib_device *ibdev,
129 u16 *max_pkeys)
130{
131 struct mlx5_ib_dev *dev = to_mdev(ibdev);
132 struct mlx5_core_dev *mdev = dev->mdev;
133
134 switch (mlx5_get_vport_access_method(ibdev)) {
135 case MLX5_VPORT_ACCESS_METHOD_MAD:
136 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
137
138 case MLX5_VPORT_ACCESS_METHOD_HCA:
139 case MLX5_VPORT_ACCESS_METHOD_NIC:
140 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
141 pkey_table_size));
142 return 0;
143
144 default:
145 return -EINVAL;
146 }
147}
148
149static int mlx5_query_vendor_id(struct ib_device *ibdev,
150 u32 *vendor_id)
151{
152 struct mlx5_ib_dev *dev = to_mdev(ibdev);
153
154 switch (mlx5_get_vport_access_method(ibdev)) {
155 case MLX5_VPORT_ACCESS_METHOD_MAD:
156 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
157
158 case MLX5_VPORT_ACCESS_METHOD_HCA:
159 case MLX5_VPORT_ACCESS_METHOD_NIC:
160 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
161
162 default:
163 return -EINVAL;
164 }
165}
166
167static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
168 __be64 *node_guid)
169{
170 u64 tmp;
171 int err;
172
173 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
174 case MLX5_VPORT_ACCESS_METHOD_MAD:
175 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
176
177 case MLX5_VPORT_ACCESS_METHOD_HCA:
178 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
179 if (!err)
180 *node_guid = cpu_to_be64(tmp);
181 return err;
182
183 default:
184 return -EINVAL;
185 }
186}
187
188struct mlx5_reg_node_desc {
189 u8 desc[64];
190};
191
192static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
193{
194 struct mlx5_reg_node_desc in;
195
196 if (mlx5_use_mad_ifc(dev))
197 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
198
199 memset(&in, 0, sizeof(in));
200
201 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
202 sizeof(struct mlx5_reg_node_desc),
203 MLX5_REG_NODE_DESC, 0, 0);
204}
205
e126ba97
EC		 206static int mlx5_ib_query_device(struct ib_device *ibdev,
207 struct ib_device_attr *props)
208{
209 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 210 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 211 int err = -ENOMEM;
212 int max_rq_sg;
213 int max_sq_sg;
e126ba97 214
1b5daf11
MD		 215 memset(props, 0, sizeof(*props));
216 err = mlx5_query_system_image_guid(ibdev,
217 &props->sys_image_guid);
218 if (err)
219 return err;
e126ba97 220
1b5daf11 221 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 222 if (err)
1b5daf11 223 return err;
e126ba97 224
1b5daf11
MD		 225 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
226 if (err)
227 return err;
e126ba97 228
9603b61d
JM		 229 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
230 (fw_rev_min(dev->mdev) << 16) |
231 fw_rev_sub(dev->mdev);
e126ba97
EC		 232 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
233 IB_DEVICE_PORT_ACTIVE_EVENT |
234 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 235 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 236
237 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 238 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 239 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 240 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 241 if (MLX5_CAP_GEN(mdev, apm))
e126ba97
EC		 242 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
243 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
938fe83c 244 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97
EC		 245 props->device_cap_flags |= IB_DEVICE_XRC;
246 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 247 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 248 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
249 /* At this stage no support for signature handover */
250 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
251 IB_PROT_T10DIF_TYPE_2 |
252 IB_PROT_T10DIF_TYPE_3;
253 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
254 IB_GUARD_T10DIF_CSUM;
255 }
938fe83c 256 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 257 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 258
1b5daf11
MD		 259 props->vendor_part_id = mdev->pdev->device;
260 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 261
262 props->max_mr_size = ~0ull;
938fe83c
SM		 263 props->page_size_cap = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
264 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
265 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
266 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
267 sizeof(struct mlx5_wqe_data_seg);
268 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
269 sizeof(struct mlx5_wqe_ctrl_seg)) /
270 sizeof(struct mlx5_wqe_data_seg);
e126ba97 271 props->max_sge = min(max_rq_sg, max_sq_sg);
938fe83c
SM		 272 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
273 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_eq_sz)) - 1;
274 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
275 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
276 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
277 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
278 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
279 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
280 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 281 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97
EC		 282 props->max_srq_sge = max_rq_sg - 1;
283 props->max_fast_reg_page_list_len = (unsigned int)-1;
81bea28f
EC		 284 props->atomic_cap = IB_ATOMIC_NONE;
285 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 286 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
287 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 288 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
289 props->max_mcast_grp;
290 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
291
8cdd312c 292#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 293 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 294 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
295 props->odp_caps = dev->odp_caps;
296#endif
297
1b5daf11 298 return 0;
e126ba97
EC		 299}
300
1b5daf11
MD		 301enum mlx5_ib_width {
302 MLX5_IB_WIDTH_1X = 1 << 0,
303 MLX5_IB_WIDTH_2X = 1 << 1,
304 MLX5_IB_WIDTH_4X = 1 << 2,
305 MLX5_IB_WIDTH_8X = 1 << 3,
306 MLX5_IB_WIDTH_12X = 1 << 4
307};
308
309static int translate_active_width(struct ib_device *ibdev, u8 active_width,
310 u8 *ib_width)
e126ba97
EC		 311{
312 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 313 int err = 0;
314
315 if (active_width & MLX5_IB_WIDTH_1X) {
316 *ib_width = IB_WIDTH_1X;
317 } else if (active_width & MLX5_IB_WIDTH_2X) {
318 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
319 (int)active_width);
320 err = -EINVAL;
321 } else if (active_width & MLX5_IB_WIDTH_4X) {
322 *ib_width = IB_WIDTH_4X;
323 } else if (active_width & MLX5_IB_WIDTH_8X) {
324 *ib_width = IB_WIDTH_8X;
325 } else if (active_width & MLX5_IB_WIDTH_12X) {
326 *ib_width = IB_WIDTH_12X;
327 } else {
328 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
329 (int)active_width);
330 err = -EINVAL;
331 }
e126ba97 332
1b5daf11
MD		 333 return err;
334}
335
336static int mlx5_mtu_to_ib_mtu(int mtu)
337{
338 switch (mtu) {
339 case 256: return 1;
340 case 512: return 2;
341 case 1024: return 3;
342 case 2048: return 4;
343 case 4096: return 5;
344 default:
345 pr_warn("invalid mtu\n");
346 return -1;
e126ba97 347 }
1b5daf11 348}
e126ba97 349
1b5daf11
MD		 350enum ib_max_vl_num {
351 __IB_MAX_VL_0 = 1,
352 __IB_MAX_VL_0_1 = 2,
353 __IB_MAX_VL_0_3 = 3,
354 __IB_MAX_VL_0_7 = 4,
355 __IB_MAX_VL_0_14 = 5,
356};
e126ba97 357
1b5daf11
MD		 358enum mlx5_vl_hw_cap {
359 MLX5_VL_HW_0 = 1,
360 MLX5_VL_HW_0_1 = 2,
361 MLX5_VL_HW_0_2 = 3,
362 MLX5_VL_HW_0_3 = 4,
363 MLX5_VL_HW_0_4 = 5,
364 MLX5_VL_HW_0_5 = 6,
365 MLX5_VL_HW_0_6 = 7,
366 MLX5_VL_HW_0_7 = 8,
367 MLX5_VL_HW_0_14 = 15
368};
e126ba97 369
1b5daf11
MD		 370static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
371 u8 *max_vl_num)
372{
373 switch (vl_hw_cap) {
374 case MLX5_VL_HW_0:
375 *max_vl_num = __IB_MAX_VL_0;
376 break;
377 case MLX5_VL_HW_0_1:
378 *max_vl_num = __IB_MAX_VL_0_1;
379 break;
380 case MLX5_VL_HW_0_3:
381 *max_vl_num = __IB_MAX_VL_0_3;
382 break;
383 case MLX5_VL_HW_0_7:
384 *max_vl_num = __IB_MAX_VL_0_7;
385 break;
386 case MLX5_VL_HW_0_14:
387 *max_vl_num = __IB_MAX_VL_0_14;
388 break;
e126ba97 389
1b5daf11
MD		 390 default:
391 return -EINVAL;
e126ba97
EC		 392 }
393
1b5daf11
MD		 394 return 0;
395}
e126ba97 396
1b5daf11
MD		 397static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
398 struct ib_port_attr *props)
399{
400 struct mlx5_ib_dev *dev = to_mdev(ibdev);
401 struct mlx5_core_dev *mdev = dev->mdev;
402 struct mlx5_hca_vport_context *rep;
403 int max_mtu;
404 int oper_mtu;
405 int err;
406 u8 ib_link_width_oper;
407 u8 vl_hw_cap;
e126ba97 408
1b5daf11
MD		 409 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
410 if (!rep) {
411 err = -ENOMEM;
412 goto out;
e126ba97
EC		 413 }
414
1b5daf11 415 memset(props, 0, sizeof(*props));
e126ba97 416
1b5daf11
MD		 417 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
418 if (err)
419 goto out;
e126ba97 420
1b5daf11
MD		 421 props->lid = rep->lid;
422 props->lmc = rep->lmc;
423 props->sm_lid = rep->sm_lid;
424 props->sm_sl = rep->sm_sl;
425 props->state = rep->vport_state;
426 props->phys_state = rep->port_physical_state;
427 props->port_cap_flags = rep->cap_mask1;
428 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
429 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
430 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
431 props->bad_pkey_cntr = rep->pkey_violation_counter;
432 props->qkey_viol_cntr = rep->qkey_violation_counter;
433 props->subnet_timeout = rep->subnet_timeout;
434 props->init_type_reply = rep->init_type_reply;
e126ba97 435
1b5daf11
MD		 436 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
437 if (err)
e126ba97
EC		 438 goto out;
439
1b5daf11
MD		 440 err = translate_active_width(ibdev, ib_link_width_oper,
441 &props->active_width);
442 if (err)
443 goto out;
444 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
445 port);
e126ba97
EC		 446 if (err)
447 goto out;
448
1b5daf11
MD		 449 err = mlx5_query_port_max_mtu(mdev, &max_mtu, port);
450 if (err)
451 goto out;
e126ba97 452
1b5daf11 453 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 454
1b5daf11 455 err = mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97
EC		 456 if (err)
457 goto out;
458
1b5daf11
MD		 459 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
460
461 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
462 if (err)
463 goto out;
e126ba97 464
1b5daf11
MD		 465 err = translate_max_vl_num(ibdev, vl_hw_cap,
466 &props->max_vl_num);
e126ba97 467out:
1b5daf11 468 kfree(rep);
e126ba97
EC		 469 return err;
470}
471
1b5daf11
MD		 472int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
473 struct ib_port_attr *props)
e126ba97 474{
1b5daf11
MD		 475 switch (mlx5_get_vport_access_method(ibdev)) {
476 case MLX5_VPORT_ACCESS_METHOD_MAD:
477 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 478
1b5daf11
MD		 479 case MLX5_VPORT_ACCESS_METHOD_HCA:
480 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 481
1b5daf11
MD		 482 default:
483 return -EINVAL;
484 }
485}
e126ba97 486
1b5daf11
MD		 487static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
488 union ib_gid *gid)
489{
490 struct mlx5_ib_dev *dev = to_mdev(ibdev);
491 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 492
1b5daf11
MD		 493 switch (mlx5_get_vport_access_method(ibdev)) {
494 case MLX5_VPORT_ACCESS_METHOD_MAD:
495 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
496
497 case MLX5_VPORT_ACCESS_METHOD_HCA:
498 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
499
500 default:
501 return -EINVAL;
502 }
e126ba97 503
e126ba97
EC		 504}
505
1b5daf11
MD		 506static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
507 u16 *pkey)
508{
509 struct mlx5_ib_dev *dev = to_mdev(ibdev);
510 struct mlx5_core_dev *mdev = dev->mdev;
511
512 switch (mlx5_get_vport_access_method(ibdev)) {
513 case MLX5_VPORT_ACCESS_METHOD_MAD:
514 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
515
516 case MLX5_VPORT_ACCESS_METHOD_HCA:
517 case MLX5_VPORT_ACCESS_METHOD_NIC:
518 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
519 pkey);
520 default:
521 return -EINVAL;
522 }
523}
e126ba97
EC		 524
525static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
526 struct ib_device_modify *props)
527{
528 struct mlx5_ib_dev *dev = to_mdev(ibdev);
529 struct mlx5_reg_node_desc in;
530 struct mlx5_reg_node_desc out;
531 int err;
532
533 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
534 return -EOPNOTSUPP;
535
536 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
537 return 0;
538
539 /*
540 * If possible, pass node desc to FW, so it can generate
541 * a 144 trap. If cmd fails, just ignore.
542 */
543 memcpy(&in, props->node_desc, 64);
9603b61d 544 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 545 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
546 if (err)
547 return err;
548
549 memcpy(ibdev->node_desc, props->node_desc, 64);
550
551 return err;
552}
553
554static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
555 struct ib_port_modify *props)
556{
557 struct mlx5_ib_dev *dev = to_mdev(ibdev);
558 struct ib_port_attr attr;
559 u32 tmp;
560 int err;
561
562 mutex_lock(&dev->cap_mask_mutex);
563
564 err = mlx5_ib_query_port(ibdev, port, &attr);
565 if (err)
566 goto out;
567
568 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
569 ~props->clr_port_cap_mask;
570
9603b61d 571 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 572
573out:
574 mutex_unlock(&dev->cap_mask_mutex);
575 return err;
576}
577
578static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
579 struct ib_udata *udata)
580{
581 struct mlx5_ib_dev *dev = to_mdev(ibdev);
78c0f98c 582 struct mlx5_ib_alloc_ucontext_req_v2 req;
e126ba97
EC		 583 struct mlx5_ib_alloc_ucontext_resp resp;
584 struct mlx5_ib_ucontext *context;
585 struct mlx5_uuar_info *uuari;
586 struct mlx5_uar *uars;
c1be5232 587 int gross_uuars;
e126ba97 588 int num_uars;
78c0f98c 589 int ver;
e126ba97
EC		 590 int uuarn;
591 int err;
592 int i;
f241e749 593 size_t reqlen;
e126ba97
EC		 594
595 if (!dev->ib_active)
596 return ERR_PTR(-EAGAIN);
597
78c0f98c
EC		 598 memset(&req, 0, sizeof(req));
599 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
600 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
601 ver = 0;
602 else if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req_v2))
603 ver = 2;
604 else
605 return ERR_PTR(-EINVAL);
606
607 err = ib_copy_from_udata(&req, udata, reqlen);
e126ba97
EC		 608 if (err)
609 return ERR_PTR(err);
610
78c0f98c
EC		 611 if (req.flags || req.reserved)
612 return ERR_PTR(-EINVAL);
613
e126ba97
EC		 614 if (req.total_num_uuars > MLX5_MAX_UUARS)
615 return ERR_PTR(-ENOMEM);
616
617 if (req.total_num_uuars == 0)
618 return ERR_PTR(-EINVAL);
619
c1be5232
EC		 620 req.total_num_uuars = ALIGN(req.total_num_uuars,
621 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 622 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
623 return ERR_PTR(-EINVAL);
624
c1be5232
EC		 625 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
626 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c
SM		 627 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
628 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
629 resp.cache_line_size = L1_CACHE_BYTES;
630 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
631 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
632 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
633 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
634 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
e126ba97
EC		 635
636 context = kzalloc(sizeof(*context), GFP_KERNEL);
637 if (!context)
638 return ERR_PTR(-ENOMEM);
639
640 uuari = &context->uuari;
641 mutex_init(&uuari->lock);
642 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
643 if (!uars) {
644 err = -ENOMEM;
645 goto out_ctx;
646 }
647
c1be5232 648 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 649 sizeof(*uuari->bitmap),
650 GFP_KERNEL);
651 if (!uuari->bitmap) {
652 err = -ENOMEM;
653 goto out_uar_ctx;
654 }
655 /*
656 * clear all fast path uuars
657 */
c1be5232 658 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 659 uuarn = i & 3;
660 if (uuarn == 2 || uuarn == 3)
661 set_bit(i, uuari->bitmap);
662 }
663
c1be5232 664 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 665 if (!uuari->count) {
666 err = -ENOMEM;
667 goto out_bitmap;
668 }
669
670 for (i = 0; i < num_uars; i++) {
9603b61d 671 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 672 if (err)
673 goto out_count;
674 }
675
b4cfe447
HE		 676#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
677 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
678#endif
679
e126ba97
EC		 680 INIT_LIST_HEAD(&context->db_page_list);
681 mutex_init(&context->db_page_mutex);
682
683 resp.tot_uuars = req.total_num_uuars;
938fe83c 684 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
92b0ca7c
DC		 685 err = ib_copy_to_udata(udata, &resp,
686 sizeof(resp) - sizeof(resp.reserved));
e126ba97
EC		 687 if (err)
688 goto out_uars;
689
78c0f98c 690 uuari->ver = ver;
e126ba97
EC		 691 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
692 uuari->uars = uars;
693 uuari->num_uars = num_uars;
694 return &context->ibucontext;
695
696out_uars:
697 for (i--; i >= 0; i--)
9603b61d 698 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 699out_count:
700 kfree(uuari->count);
701
702out_bitmap:
703 kfree(uuari->bitmap);
704
705out_uar_ctx:
706 kfree(uars);
707
708out_ctx:
709 kfree(context);
710 return ERR_PTR(err);
711}
712
713static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
714{
715 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
716 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
717 struct mlx5_uuar_info *uuari = &context->uuari;
718 int i;
719
720 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 721 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 722 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
723 }
724
725 kfree(uuari->count);
726 kfree(uuari->bitmap);
727 kfree(uuari->uars);
728 kfree(context);
729
730 return 0;
731}
732
733static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
734{
9603b61d 735 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 736}
737
738static int get_command(unsigned long offset)
739{
740 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
741}
742
743static int get_arg(unsigned long offset)
744{
745 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
746}
747
748static int get_index(unsigned long offset)
749{
750 return get_arg(offset);
751}
752
753static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
754{
755 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
756 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
757 struct mlx5_uuar_info *uuari = &context->uuari;
758 unsigned long command;
759 unsigned long idx;
760 phys_addr_t pfn;
761
762 command = get_command(vma->vm_pgoff);
763 switch (command) {
764 case MLX5_IB_MMAP_REGULAR_PAGE:
765 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
766 return -EINVAL;
767
768 idx = get_index(vma->vm_pgoff);
1c3ce90d
EC		 769 if (idx >= uuari->num_uars)
770 return -EINVAL;
771
e126ba97
EC		 772 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
773 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
774 (unsigned long long)pfn);
775
e126ba97
EC		 776 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
777 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
778 PAGE_SIZE, vma->vm_page_prot))
779 return -EAGAIN;
780
781 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
782 vma->vm_start,
783 (unsigned long long)pfn << PAGE_SHIFT);
784 break;
785
786 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
787 return -ENOSYS;
788
789 default:
790 return -EINVAL;
791 }
792
793 return 0;
794}
795
796static int alloc_pa_mkey(struct mlx5_ib_dev *dev, u32 *key, u32 pdn)
797{
798 struct mlx5_create_mkey_mbox_in *in;
799 struct mlx5_mkey_seg *seg;
800 struct mlx5_core_mr mr;
801 int err;
802
803 in = kzalloc(sizeof(*in), GFP_KERNEL);
804 if (!in)
805 return -ENOMEM;
806
807 seg = &in->seg;
808 seg->flags = MLX5_PERM_LOCAL_READ | MLX5_ACCESS_MODE_PA;
809 seg->flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
810 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
811 seg->start_addr = 0;
812
9603b61d 813 err = mlx5_core_create_mkey(dev->mdev, &mr, in, sizeof(*in),
746b5583 814 NULL, NULL, NULL);
e126ba97
EC		 815 if (err) {
816 mlx5_ib_warn(dev, "failed to create mkey, %d\n", err);
817 goto err_in;
818 }
819
820 kfree(in);
821 *key = mr.key;
822
823 return 0;
824
825err_in:
826 kfree(in);
827
828 return err;
829}
830
831static void free_pa_mkey(struct mlx5_ib_dev *dev, u32 key)
832{
833 struct mlx5_core_mr mr;
834 int err;
835
836 memset(&mr, 0, sizeof(mr));
837 mr.key = key;
9603b61d 838 err = mlx5_core_destroy_mkey(dev->mdev, &mr);
e126ba97
EC		 839 if (err)
840 mlx5_ib_warn(dev, "failed to destroy mkey 0x%x\n", key);
841}
842
843static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
844 struct ib_ucontext *context,
845 struct ib_udata *udata)
846{
847 struct mlx5_ib_alloc_pd_resp resp;
848 struct mlx5_ib_pd *pd;
849 int err;
850
851 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
852 if (!pd)
853 return ERR_PTR(-ENOMEM);
854
9603b61d 855 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 856 if (err) {
857 kfree(pd);
858 return ERR_PTR(err);
859 }
860
861 if (context) {
862 resp.pdn = pd->pdn;
863 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 864 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 865 kfree(pd);
866 return ERR_PTR(-EFAULT);
867 }
868 } else {
869 err = alloc_pa_mkey(to_mdev(ibdev), &pd->pa_lkey, pd->pdn);
870 if (err) {
9603b61d 871 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 872 kfree(pd);
873 return ERR_PTR(err);
874 }
875 }
876
877 return &pd->ibpd;
878}
879
880static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
881{
882 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
883 struct mlx5_ib_pd *mpd = to_mpd(pd);
884
885 if (!pd->uobject)
886 free_pa_mkey(mdev, mpd->pa_lkey);
887
9603b61d 888 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 889 kfree(mpd);
890
891 return 0;
892}
893
894static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
895{
896 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
897 int err;
898
9603b61d 899 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 900 if (err)
901 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
902 ibqp->qp_num, gid->raw);
903
904 return err;
905}
906
907static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
908{
909 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
910 int err;
911
9603b61d 912 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 913 if (err)
914 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
915 ibqp->qp_num, gid->raw);
916
917 return err;
918}
919
920static int init_node_data(struct mlx5_ib_dev *dev)
921{
1b5daf11 922 int err;
e126ba97 923
1b5daf11 924 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 925 if (err)
1b5daf11 926 return err;
e126ba97 927
1b5daf11 928 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 929
1b5daf11 930 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 931}
932
933static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
934 char *buf)
935{
936 struct mlx5_ib_dev *dev =
937 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
938
9603b61d 939 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 940}
941
942static ssize_t show_reg_pages(struct device *device,
943 struct device_attribute *attr, char *buf)
944{
945 struct mlx5_ib_dev *dev =
946 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
947
6aec21f6 948 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 949}
950
951static ssize_t show_hca(struct device *device, struct device_attribute *attr,
952 char *buf)
953{
954 struct mlx5_ib_dev *dev =
955 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 956 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 957}
958
959static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
960 char *buf)
961{
962 struct mlx5_ib_dev *dev =
963 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d
JM		 964 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
965 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
e126ba97
EC		 966}
967
968static ssize_t show_rev(struct device *device, struct device_attribute *attr,
969 char *buf)
970{
971 struct mlx5_ib_dev *dev =
972 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 973 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 974}
975
976static ssize_t show_board(struct device *device, struct device_attribute *attr,
977 char *buf)
978{
979 struct mlx5_ib_dev *dev =
980 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
981 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 982 dev->mdev->board_id);
e126ba97
EC		 983}
984
985static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
986static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
987static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
988static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
989static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
990static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
991
992static struct device_attribute *mlx5_class_attributes[] = {
993 &dev_attr_hw_rev,
994 &dev_attr_fw_ver,
995 &dev_attr_hca_type,
996 &dev_attr_board_id,
997 &dev_attr_fw_pages,
998 &dev_attr_reg_pages,
999};
1000
9603b61d 1001static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 1002 enum mlx5_dev_event event, unsigned long param)
e126ba97 1003{
9603b61d 1004 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 1005 struct ib_event ibev;
9603b61d 1006
e126ba97
EC		 1007 u8 port = 0;
1008
1009 switch (event) {
1010 case MLX5_DEV_EVENT_SYS_ERROR:
1011 ibdev->ib_active = false;
1012 ibev.event = IB_EVENT_DEVICE_FATAL;
1013 break;
1014
1015 case MLX5_DEV_EVENT_PORT_UP:
1016 ibev.event = IB_EVENT_PORT_ACTIVE;
4d2f9bbb 1017 port = (u8)param;
e126ba97
EC		 1018 break;
1019
1020 case MLX5_DEV_EVENT_PORT_DOWN:
1021 ibev.event = IB_EVENT_PORT_ERR;
4d2f9bbb 1022 port = (u8)param;
e126ba97
EC		 1023 break;
1024
1025 case MLX5_DEV_EVENT_PORT_INITIALIZED:
1026 /* not used by ULPs */
1027 return;
1028
1029 case MLX5_DEV_EVENT_LID_CHANGE:
1030 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 1031 port = (u8)param;
e126ba97
EC		 1032 break;
1033
1034 case MLX5_DEV_EVENT_PKEY_CHANGE:
1035 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 1036 port = (u8)param;
e126ba97
EC		 1037 break;
1038
1039 case MLX5_DEV_EVENT_GUID_CHANGE:
1040 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 1041 port = (u8)param;
e126ba97
EC		 1042 break;
1043
1044 case MLX5_DEV_EVENT_CLIENT_REREG:
1045 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 1046 port = (u8)param;
e126ba97
EC		 1047 break;
1048 }
1049
1050 ibev.device = &ibdev->ib_dev;
1051 ibev.element.port_num = port;
1052
a0c84c32
EC		 1053 if (port < 1 || port > ibdev->num_ports) {
1054 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
1055 return;
1056 }
1057
e126ba97
EC		 1058 if (ibdev->ib_active)
1059 ib_dispatch_event(&ibev);
1060}
1061
1062static void get_ext_port_caps(struct mlx5_ib_dev *dev)
1063{
1064 int port;
1065
938fe83c 1066 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 1067 mlx5_query_ext_port_caps(dev, port);
1068}
1069
1070static int get_port_caps(struct mlx5_ib_dev *dev)
1071{
1072 struct ib_device_attr *dprops = NULL;
1073 struct ib_port_attr *pprops = NULL;
f614fc15 1074 int err = -ENOMEM;
e126ba97
EC		 1075 int port;
1076
1077 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
1078 if (!pprops)
1079 goto out;
1080
1081 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
1082 if (!dprops)
1083 goto out;
1084
1085 err = mlx5_ib_query_device(&dev->ib_dev, dprops);
1086 if (err) {
1087 mlx5_ib_warn(dev, "query_device failed %d\n", err);
1088 goto out;
1089 }
1090
938fe83c 1091 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 1092 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
1093 if (err) {
938fe83c
SM		 1094 mlx5_ib_warn(dev, "query_port %d failed %d\n",
1095 port, err);
e126ba97
EC		 1096 break;
1097 }
938fe83c
SM		 1098 dev->mdev->port_caps[port - 1].pkey_table_len =
1099 dprops->max_pkeys;
1100 dev->mdev->port_caps[port - 1].gid_table_len =
1101 pprops->gid_tbl_len;
e126ba97
EC		 1102 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
1103 dprops->max_pkeys, pprops->gid_tbl_len);
1104 }
1105
1106out:
1107 kfree(pprops);
1108 kfree(dprops);
1109
1110 return err;
1111}
1112
1113static void destroy_umrc_res(struct mlx5_ib_dev *dev)
1114{
1115 int err;
1116
1117 err = mlx5_mr_cache_cleanup(dev);
1118 if (err)
1119 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
1120
1121 mlx5_ib_destroy_qp(dev->umrc.qp);
1122 ib_destroy_cq(dev->umrc.cq);
1123 ib_dereg_mr(dev->umrc.mr);
1124 ib_dealloc_pd(dev->umrc.pd);
1125}
1126
1127enum {
1128 MAX_UMR_WR = 128,
1129};
1130
1131static int create_umr_res(struct mlx5_ib_dev *dev)
1132{
1133 struct ib_qp_init_attr *init_attr = NULL;
1134 struct ib_qp_attr *attr = NULL;
1135 struct ib_pd *pd;
1136 struct ib_cq *cq;
1137 struct ib_qp *qp;
1138 struct ib_mr *mr;
1139 int ret;
1140
1141 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
1142 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
1143 if (!attr || !init_attr) {
1144 ret = -ENOMEM;
1145 goto error_0;
1146 }
1147
1148 pd = ib_alloc_pd(&dev->ib_dev);
1149 if (IS_ERR(pd)) {
1150 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
1151 ret = PTR_ERR(pd);
1152 goto error_0;
1153 }
1154
1155 mr = ib_get_dma_mr(pd, IB_ACCESS_LOCAL_WRITE);
1156 if (IS_ERR(mr)) {
1157 mlx5_ib_dbg(dev, "Couldn't create DMA MR for sync UMR QP\n");
1158 ret = PTR_ERR(mr);
1159 goto error_1;
1160 }
1161
1162 cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL, 128,
1163 0);
1164 if (IS_ERR(cq)) {
1165 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
1166 ret = PTR_ERR(cq);
1167 goto error_2;
1168 }
1169 ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
1170
1171 init_attr->send_cq = cq;
1172 init_attr->recv_cq = cq;
1173 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
1174 init_attr->cap.max_send_wr = MAX_UMR_WR;
1175 init_attr->cap.max_send_sge = 1;
1176 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
1177 init_attr->port_num = 1;
1178 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
1179 if (IS_ERR(qp)) {
1180 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
1181 ret = PTR_ERR(qp);
1182 goto error_3;
1183 }
1184 qp->device = &dev->ib_dev;
1185 qp->real_qp = qp;
1186 qp->uobject = NULL;
1187 qp->qp_type = MLX5_IB_QPT_REG_UMR;
1188
1189 attr->qp_state = IB_QPS_INIT;
1190 attr->port_num = 1;
1191 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
1192 IB_QP_PORT, NULL);
1193 if (ret) {
1194 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
1195 goto error_4;
1196 }
1197
1198 memset(attr, 0, sizeof(*attr));
1199 attr->qp_state = IB_QPS_RTR;
1200 attr->path_mtu = IB_MTU_256;
1201
1202 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1203 if (ret) {
1204 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
1205 goto error_4;
1206 }
1207
1208 memset(attr, 0, sizeof(*attr));
1209 attr->qp_state = IB_QPS_RTS;
1210 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1211 if (ret) {
1212 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
1213 goto error_4;
1214 }
1215
1216 dev->umrc.qp = qp;
1217 dev->umrc.cq = cq;
1218 dev->umrc.mr = mr;
1219 dev->umrc.pd = pd;
1220
1221 sema_init(&dev->umrc.sem, MAX_UMR_WR);
1222 ret = mlx5_mr_cache_init(dev);
1223 if (ret) {
1224 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
1225 goto error_4;
1226 }
1227
1228 kfree(attr);
1229 kfree(init_attr);
1230
1231 return 0;
1232
1233error_4:
1234 mlx5_ib_destroy_qp(qp);
1235
1236error_3:
1237 ib_destroy_cq(cq);
1238
1239error_2:
1240 ib_dereg_mr(mr);
1241
1242error_1:
1243 ib_dealloc_pd(pd);
1244
1245error_0:
1246 kfree(attr);
1247 kfree(init_attr);
1248 return ret;
1249}
1250
1251static int create_dev_resources(struct mlx5_ib_resources *devr)
1252{
1253 struct ib_srq_init_attr attr;
1254 struct mlx5_ib_dev *dev;
1255 int ret = 0;
1256
1257 dev = container_of(devr, struct mlx5_ib_dev, devr);
1258
1259 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
1260 if (IS_ERR(devr->p0)) {
1261 ret = PTR_ERR(devr->p0);
1262 goto error0;
1263 }
1264 devr->p0->device = &dev->ib_dev;
1265 devr->p0->uobject = NULL;
1266 atomic_set(&devr->p0->usecnt, 0);
1267
1268 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, 1, 0, NULL, NULL);
1269 if (IS_ERR(devr->c0)) {
1270 ret = PTR_ERR(devr->c0);
1271 goto error1;
1272 }
1273 devr->c0->device = &dev->ib_dev;
1274 devr->c0->uobject = NULL;
1275 devr->c0->comp_handler = NULL;
1276 devr->c0->event_handler = NULL;
1277 devr->c0->cq_context = NULL;
1278 atomic_set(&devr->c0->usecnt, 0);
1279
1280 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1281 if (IS_ERR(devr->x0)) {
1282 ret = PTR_ERR(devr->x0);
1283 goto error2;
1284 }
1285 devr->x0->device = &dev->ib_dev;
1286 devr->x0->inode = NULL;
1287 atomic_set(&devr->x0->usecnt, 0);
1288 mutex_init(&devr->x0->tgt_qp_mutex);
1289 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
1290
1291 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1292 if (IS_ERR(devr->x1)) {
1293 ret = PTR_ERR(devr->x1);
1294 goto error3;
1295 }
1296 devr->x1->device = &dev->ib_dev;
1297 devr->x1->inode = NULL;
1298 atomic_set(&devr->x1->usecnt, 0);
1299 mutex_init(&devr->x1->tgt_qp_mutex);
1300 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
1301
1302 memset(&attr, 0, sizeof(attr));
1303 attr.attr.max_sge = 1;
1304 attr.attr.max_wr = 1;
1305 attr.srq_type = IB_SRQT_XRC;
1306 attr.ext.xrc.cq = devr->c0;
1307 attr.ext.xrc.xrcd = devr->x0;
1308
1309 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
1310 if (IS_ERR(devr->s0)) {
1311 ret = PTR_ERR(devr->s0);
1312 goto error4;
1313 }
1314 devr->s0->device = &dev->ib_dev;
1315 devr->s0->pd = devr->p0;
1316 devr->s0->uobject = NULL;
1317 devr->s0->event_handler = NULL;
1318 devr->s0->srq_context = NULL;
1319 devr->s0->srq_type = IB_SRQT_XRC;
1320 devr->s0->ext.xrc.xrcd = devr->x0;
1321 devr->s0->ext.xrc.cq = devr->c0;
1322 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1323 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
1324 atomic_inc(&devr->p0->usecnt);
1325 atomic_set(&devr->s0->usecnt, 0);
1326
1327 return 0;
1328
1329error4:
1330 mlx5_ib_dealloc_xrcd(devr->x1);
1331error3:
1332 mlx5_ib_dealloc_xrcd(devr->x0);
1333error2:
1334 mlx5_ib_destroy_cq(devr->c0);
1335error1:
1336 mlx5_ib_dealloc_pd(devr->p0);
1337error0:
1338 return ret;
1339}
1340
1341static void destroy_dev_resources(struct mlx5_ib_resources *devr)
1342{
1343 mlx5_ib_destroy_srq(devr->s0);
1344 mlx5_ib_dealloc_xrcd(devr->x0);
1345 mlx5_ib_dealloc_xrcd(devr->x1);
1346 mlx5_ib_destroy_cq(devr->c0);
1347 mlx5_ib_dealloc_pd(devr->p0);
1348}
1349
9603b61d 1350static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 1351{
e126ba97
EC		 1352 struct mlx5_ib_dev *dev;
1353 int err;
1354 int i;
1355
1356 printk_once(KERN_INFO "%s", mlx5_version);
1357
1358 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
1359 if (!dev)
9603b61d 1360 return NULL;
e126ba97 1361
9603b61d 1362 dev->mdev = mdev;
e126ba97
EC		 1363
1364 err = get_port_caps(dev);
1365 if (err)
9603b61d 1366 goto err_dealloc;
e126ba97 1367
1b5daf11
MD		 1368 if (mlx5_use_mad_ifc(dev))
1369 get_ext_port_caps(dev);
e126ba97 1370
e126ba97
EC		 1371 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
1372
1373 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
1374 dev->ib_dev.owner = THIS_MODULE;
1375 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
938fe83c
SM		 1376 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
1377 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 1378 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 1379 dev->ib_dev.num_comp_vectors =
1380 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 1381 dev->ib_dev.dma_device = &mdev->pdev->dev;
1382
1383 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
1384 dev->ib_dev.uverbs_cmd_mask =
1385 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
1386 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
1387 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
1388 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
1389 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
1390 (1ull << IB_USER_VERBS_CMD_REG_MR) |
1391 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
1392 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
1393 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
1394 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
1395 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
1396 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
1397 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
1398 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
1399 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
1400 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
1401 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
1402 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
1403 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
1404 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
1405 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
1406 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
1407 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a
HE		 1408 dev->ib_dev.uverbs_ex_cmd_mask =
1409 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE);
e126ba97
EC		 1410
1411 dev->ib_dev.query_device = mlx5_ib_query_device;
1412 dev->ib_dev.query_port = mlx5_ib_query_port;
1413 dev->ib_dev.query_gid = mlx5_ib_query_gid;
1414 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
1415 dev->ib_dev.modify_device = mlx5_ib_modify_device;
1416 dev->ib_dev.modify_port = mlx5_ib_modify_port;
1417 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
1418 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
1419 dev->ib_dev.mmap = mlx5_ib_mmap;
1420 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
1421 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
1422 dev->ib_dev.create_ah = mlx5_ib_create_ah;
1423 dev->ib_dev.query_ah = mlx5_ib_query_ah;
1424 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
1425 dev->ib_dev.create_srq = mlx5_ib_create_srq;
1426 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
1427 dev->ib_dev.query_srq = mlx5_ib_query_srq;
1428 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
1429 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
1430 dev->ib_dev.create_qp = mlx5_ib_create_qp;
1431 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
1432 dev->ib_dev.query_qp = mlx5_ib_query_qp;
1433 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
1434 dev->ib_dev.post_send = mlx5_ib_post_send;
1435 dev->ib_dev.post_recv = mlx5_ib_post_recv;
1436 dev->ib_dev.create_cq = mlx5_ib_create_cq;
1437 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
1438 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
1439 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
1440 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
1441 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
1442 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
1443 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
1444 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3121e3c4 1445 dev->ib_dev.destroy_mr = mlx5_ib_destroy_mr;
e126ba97
EC		 1446 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
1447 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
1448 dev->ib_dev.process_mad = mlx5_ib_process_mad;
3121e3c4 1449 dev->ib_dev.create_mr = mlx5_ib_create_mr;
e126ba97
EC		 1450 dev->ib_dev.alloc_fast_reg_mr = mlx5_ib_alloc_fast_reg_mr;
1451 dev->ib_dev.alloc_fast_reg_page_list = mlx5_ib_alloc_fast_reg_page_list;
1452 dev->ib_dev.free_fast_reg_page_list = mlx5_ib_free_fast_reg_page_list;
d5436ba0 1453 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
e126ba97 1454
938fe83c 1455 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 1456
938fe83c 1457 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 1458 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
1459 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
1460 dev->ib_dev.uverbs_cmd_mask |=
1461 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
1462 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
1463 }
1464
1465 err = init_node_data(dev);
1466 if (err)
233d05d2 1467 goto err_dealloc;
e126ba97
EC		 1468
1469 mutex_init(&dev->cap_mask_mutex);
e126ba97
EC		 1470
1471 err = create_dev_resources(&dev->devr);
1472 if (err)
233d05d2 1473 goto err_dealloc;
e126ba97 1474
6aec21f6 1475 err = mlx5_ib_odp_init_one(dev);
281d1a92 1476 if (err)
e126ba97
EC		 1477 goto err_rsrc;
1478
6aec21f6
HE		 1479 err = ib_register_device(&dev->ib_dev, NULL);
1480 if (err)
1481 goto err_odp;
1482
e126ba97
EC		 1483 err = create_umr_res(dev);
1484 if (err)
1485 goto err_dev;
1486
1487 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 1488 err = device_create_file(&dev->ib_dev.dev,
1489 mlx5_class_attributes[i]);
1490 if (err)
e126ba97
EC		 1491 goto err_umrc;
1492 }
1493
1494 dev->ib_active = true;
1495
9603b61d 1496 return dev;
e126ba97
EC		 1497
1498err_umrc:
1499 destroy_umrc_res(dev);
1500
1501err_dev:
1502 ib_unregister_device(&dev->ib_dev);
1503
6aec21f6
HE		 1504err_odp:
1505 mlx5_ib_odp_remove_one(dev);
1506
e126ba97
EC		 1507err_rsrc:
1508 destroy_dev_resources(&dev->devr);
1509
9603b61d 1510err_dealloc:
e126ba97
EC		 1511 ib_dealloc_device((struct ib_device *)dev);
1512
9603b61d 1513 return NULL;
e126ba97
EC		 1514}
1515
9603b61d 1516static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 1517{
9603b61d 1518 struct mlx5_ib_dev *dev = context;
6aec21f6 1519
e126ba97 1520 ib_unregister_device(&dev->ib_dev);
eefd56e5 1521 destroy_umrc_res(dev);
6aec21f6 1522 mlx5_ib_odp_remove_one(dev);
e126ba97 1523 destroy_dev_resources(&dev->devr);
e126ba97
EC		 1524 ib_dealloc_device(&dev->ib_dev);
1525}
1526
9603b61d
JM		 1527static struct mlx5_interface mlx5_ib_interface = {
1528 .add = mlx5_ib_add,
1529 .remove = mlx5_ib_remove,
1530 .event = mlx5_ib_event,
64613d94 1531 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 1532};
1533
1534static int __init mlx5_ib_init(void)
1535{
6aec21f6
HE		 1536 int err;
1537
9603b61d
JM		 1538 if (deprecated_prof_sel != 2)
1539 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
1540
6aec21f6
HE		 1541 err = mlx5_ib_odp_init();
1542 if (err)
1543 return err;
1544
1545 err = mlx5_register_interface(&mlx5_ib_interface);
1546 if (err)
1547 goto clean_odp;
1548
1549 return err;
1550
1551clean_odp:
1552 mlx5_ib_odp_cleanup();
1553 return err;
e126ba97
EC		 1554}
1555
1556static void __exit mlx5_ib_cleanup(void)
1557{
9603b61d 1558 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 1559 mlx5_ib_odp_cleanup();
e126ba97
EC		 1560}
1561
1562module_init(mlx5_ib_init);
1563module_exit(mlx5_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)