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Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c
JM		 34#include <linux/log2.h>
35
225c7b1f
RD		 36#include <rdma/ib_cache.h>
37#include <rdma/ib_pack.h>
38
39#include <linux/mlx4/qp.h>
40
41#include "mlx4_ib.h"
42#include "user.h"
43
44enum {
45 MLX4_IB_ACK_REQ_FREQ = 8,
46};
47
48enum {
49 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
50 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
51};
52
53enum {
54 /*
55 * Largest possible UD header: send with GRH and immediate data.
56 */
57 MLX4_IB_UD_HEADER_SIZE = 72
58};
59
60struct mlx4_ib_sqp {
61 struct mlx4_ib_qp qp;
62 int pkey_index;
63 u32 qkey;
64 u32 send_psn;
65 struct ib_ud_header ud_header;
66 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
67};
68
83904132
JM		 69enum {
70 MLX4_IB_MIN_SQ_STRIDE = 6
71};
72
225c7b1f
RD		 73static const __be32 mlx4_ib_opcode[] = {
74 [IB_WR_SEND] = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
b832be1e 75 [IB_WR_LSO] = __constant_cpu_to_be32(MLX4_OPCODE_LSO),
225c7b1f
RD		 76 [IB_WR_SEND_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
77 [IB_WR_RDMA_WRITE] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
78 [IB_WR_RDMA_WRITE_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
79 [IB_WR_RDMA_READ] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
80 [IB_WR_ATOMIC_CMP_AND_SWP] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
81 [IB_WR_ATOMIC_FETCH_AND_ADD] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
95d04f07
RD		 82 [IB_WR_SEND_WITH_INV] = __constant_cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
83 [IB_WR_LOCAL_INV] = __constant_cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
84 [IB_WR_FAST_REG_MR] = __constant_cpu_to_be32(MLX4_OPCODE_FMR),
225c7b1f
RD		 85};
86
87static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
88{
89 return container_of(mqp, struct mlx4_ib_sqp, qp);
90}
91
92static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
93{
94 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
95 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
96}
97
98static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
99{
100 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
101 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
102}
103
104static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
105{
1c69fc2a 106 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 107}
108
109static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
110{
111 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
112}
113
114static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
115{
116 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
117}
118
0e6e7416
RD		 119/*
120 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 121 * first four bytes of every 64 byte chunk with
122 * 0x7FFFFFF | (invalid_ownership_value << 31).
123 *
124 * When the max work request size is less than or equal to the WQE
125 * basic block size, as an optimization, we can stamp all WQEs with
126 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 127 */
ea54b10c 128static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 129{
d2ae16d5 130 __be32 *wqe;
0e6e7416 131 int i;
ea54b10c
JM		 132 int s;
133 int ind;
134 void *buf;
135 __be32 stamp;
9670e553 136 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 137
ea54b10c 138 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 139 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 140 for (i = 0; i < s; i += 64) {
141 ind = (i >> qp->sq.wqe_shift) + n;
142 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
143 cpu_to_be32(0xffffffff);
144 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
145 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
146 *wqe = stamp;
147 }
148 } else {
9670e553
EC		 149 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
150 s = (ctrl->fence_size & 0x3f) << 4;
ea54b10c
JM		 151 for (i = 64; i < s; i += 64) {
152 wqe = buf + i;
d2ae16d5 153 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 154 }
155 }
156}
157
158static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
159{
160 struct mlx4_wqe_ctrl_seg *ctrl;
161 struct mlx4_wqe_inline_seg *inl;
162 void *wqe;
163 int s;
164
165 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
166 s = sizeof(struct mlx4_wqe_ctrl_seg);
167
168 if (qp->ibqp.qp_type == IB_QPT_UD) {
169 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
170 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
171 memset(dgram, 0, sizeof *dgram);
172 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
173 s += sizeof(struct mlx4_wqe_datagram_seg);
174 }
175
176 /* Pad the remainder of the WQE with an inline data segment. */
177 if (size > s) {
178 inl = wqe + s;
179 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
180 }
181 ctrl->srcrb_flags = 0;
182 ctrl->fence_size = size / 16;
183 /*
184 * Make sure descriptor is fully written before setting ownership bit
185 * (because HW can start executing as soon as we do).
186 */
187 wmb();
188
189 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
190 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 191
ea54b10c
JM		 192 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
193}
194
195/* Post NOP WQE to prevent wrap-around in the middle of WR */
196static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
197{
198 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
199 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
200 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
201 ind += s;
202 }
203 return ind;
0e6e7416
RD		 204}
205
225c7b1f
RD		 206static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
207{
208 struct ib_event event;
209 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
210
211 if (type == MLX4_EVENT_TYPE_PATH_MIG)
212 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
213
214 if (ibqp->event_handler) {
215 event.device = ibqp->device;
216 event.element.qp = ibqp;
217 switch (type) {
218 case MLX4_EVENT_TYPE_PATH_MIG:
219 event.event = IB_EVENT_PATH_MIG;
220 break;
221 case MLX4_EVENT_TYPE_COMM_EST:
222 event.event = IB_EVENT_COMM_EST;
223 break;
224 case MLX4_EVENT_TYPE_SQ_DRAINED:
225 event.event = IB_EVENT_SQ_DRAINED;
226 break;
227 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
228 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
229 break;
230 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
231 event.event = IB_EVENT_QP_FATAL;
232 break;
233 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
234 event.event = IB_EVENT_PATH_MIG_ERR;
235 break;
236 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
237 event.event = IB_EVENT_QP_REQ_ERR;
238 break;
239 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
240 event.event = IB_EVENT_QP_ACCESS_ERR;
241 break;
242 default:
243 printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
244 "on QP %06x\n", type, qp->qpn);
245 return;
246 }
247
248 ibqp->event_handler(&event, ibqp->qp_context);
249 }
250}
251
b832be1e 252static int send_wqe_overhead(enum ib_qp_type type, u32 flags)
225c7b1f
RD		 253{
254 /*
255 * UD WQEs must have a datagram segment.
256 * RC and UC WQEs might have a remote address segment.
257 * MLX WQEs need two extra inline data segments (for the UD
258 * header and space for the ICRC).
259 */
260 switch (type) {
261 case IB_QPT_UD:
262 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e
EC		 263 sizeof (struct mlx4_wqe_datagram_seg) +
264 ((flags & MLX4_IB_QP_LSO) ? 64 : 0);
225c7b1f
RD		 265 case IB_QPT_UC:
266 return sizeof (struct mlx4_wqe_ctrl_seg) +
267 sizeof (struct mlx4_wqe_raddr_seg);
268 case IB_QPT_RC:
269 return sizeof (struct mlx4_wqe_ctrl_seg) +
270 sizeof (struct mlx4_wqe_atomic_seg) +
271 sizeof (struct mlx4_wqe_raddr_seg);
272 case IB_QPT_SMI:
273 case IB_QPT_GSI:
274 return sizeof (struct mlx4_wqe_ctrl_seg) +
275 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 276 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
277 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 278 sizeof (struct mlx4_wqe_inline_seg),
279 sizeof (struct mlx4_wqe_data_seg)) +
280 ALIGN(4 +
281 sizeof (struct mlx4_wqe_inline_seg),
282 sizeof (struct mlx4_wqe_data_seg));
283 default:
284 return sizeof (struct mlx4_wqe_ctrl_seg);
285 }
286}
287
2446304d 288static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
a4cd7ed8 289 int is_user, int has_srq, struct mlx4_ib_qp *qp)
225c7b1f 290{
2446304d
EC		 291 /* Sanity check RQ size before proceeding */
292 if (cap->max_recv_wr > dev->dev->caps.max_wqes ||
293 cap->max_recv_sge > dev->dev->caps.max_rq_sg)
294 return -EINVAL;
295
a4cd7ed8
RD		 296 if (has_srq) {
297 /* QPs attached to an SRQ should have no RQ */
298 if (cap->max_recv_wr)
299 return -EINVAL;
2446304d 300
0e6e7416 301 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 302 } else {
303 /* HW requires >= 1 RQ entry with >= 1 gather entry */
304 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
305 return -EINVAL;
306
0e6e7416 307 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 308 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 309 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
310 }
2446304d 311
0e6e7416 312 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
2446304d
EC		 313 cap->max_recv_sge = qp->rq.max_gs;
314
315 return 0;
316}
317
318static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
319 enum ib_qp_type type, struct mlx4_ib_qp *qp)
320{
ea54b10c
JM		 321 int s;
322
2446304d 323 /* Sanity check SQ size before proceeding */
225c7b1f 324 if (cap->max_send_wr > dev->dev->caps.max_wqes ||
225c7b1f 325 cap->max_send_sge > dev->dev->caps.max_sq_sg ||
b832be1e 326 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 327 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
328 return -EINVAL;
329
330 /*
331 * For MLX transport we need 2 extra S/G entries:
332 * one for the header and one for the checksum at the end
333 */
334 if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
335 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
336 return -EINVAL;
337
ea54b10c
JM		 338 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
339 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 340 send_wqe_overhead(type, qp->flags);
225c7b1f 341
cd155c1c
RD		 342 if (s > dev->dev->caps.max_sq_desc_sz)
343 return -EINVAL;
344
0e6e7416 345 /*
ea54b10c
JM		 346 * Hermon supports shrinking WQEs, such that a single work
347 * request can include multiple units of 1 << wqe_shift. This
348 * way, work requests can differ in size, and do not have to
349 * be a power of 2 in size, saving memory and speeding up send
350 * WR posting. Unfortunately, if we do this then the
351 * wqe_index field in CQEs can't be used to look up the WR ID
352 * anymore, so we do this only if selective signaling is off.
353 *
354 * Further, on 32-bit platforms, we can't use vmap() to make
355 * the QP buffer virtually contigious. Thus we have to use
356 * constant-sized WRs to make sure a WR is always fully within
357 * a single page-sized chunk.
358 *
359 * Finally, we use NOP work requests to pad the end of the
360 * work queue, to avoid wrap-around in the middle of WR. We
361 * set NEC bit to avoid getting completions with error for
362 * these NOP WRs, but since NEC is only supported starting
363 * with firmware 2.2.232, we use constant-sized WRs for older
364 * firmware.
365 *
366 * And, since MLX QPs only support SEND, we use constant-sized
367 * WRs in this case.
368 *
369 * We look for the smallest value of wqe_shift such that the
370 * resulting number of wqes does not exceed device
371 * capabilities.
372 *
373 * We set WQE size to at least 64 bytes, this way stamping
374 * invalidates each WQE.
0e6e7416 375 */
ea54b10c
JM		 376 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
377 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
378 type != IB_QPT_SMI && type != IB_QPT_GSI)
379 qp->sq.wqe_shift = ilog2(64);
380 else
381 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
382
383 for (;;) {
ea54b10c
JM		 384 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
385
386 /*
387 * We need to leave 2 KB + 1 WR of headroom in the SQ to
388 * allow HW to prefetch.
389 */
390 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
391 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
392 qp->sq_max_wqes_per_wr +
393 qp->sq_spare_wqes);
394
395 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
396 break;
397
398 if (qp->sq_max_wqes_per_wr <= 1)
399 return -EINVAL;
400
401 ++qp->sq.wqe_shift;
402 }
403
cd155c1c
RD		 404 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
405 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 406 send_wqe_overhead(type, qp->flags)) /
407 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 408
409 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
410 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 411 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
412 qp->rq.offset = 0;
0e6e7416 413 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 414 } else {
0e6e7416 415 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 416 qp->sq.offset = 0;
417 }
418
ea54b10c
JM		 419 cap->max_send_wr = qp->sq.max_post =
420 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 421 cap->max_send_sge = min(qp->sq.max_gs,
422 min(dev->dev->caps.max_sq_sg,
423 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 424 /* We don't support inline sends for kernel QPs (yet) */
425 cap->max_inline_data = 0;
225c7b1f
RD		 426
427 return 0;
428}
429
83904132
JM		 430static int set_user_sq_size(struct mlx4_ib_dev *dev,
431 struct mlx4_ib_qp *qp,
2446304d
EC		 432 struct mlx4_ib_create_qp *ucmd)
433{
83904132
JM		 434 /* Sanity check SQ size before proceeding */
435 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
436 ucmd->log_sq_stride >
437 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
438 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
439 return -EINVAL;
440
0e6e7416 441 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 442 qp->sq.wqe_shift = ucmd->log_sq_stride;
443
0e6e7416
RD		 444 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
445 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 446
447 return 0;
448}
449
225c7b1f
RD		 450static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
451 struct ib_qp_init_attr *init_attr,
452 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
453{
225c7b1f 454 int err;
225c7b1f
RD		 455
456 mutex_init(&qp->mutex);
457 spin_lock_init(&qp->sq.lock);
458 spin_lock_init(&qp->rq.lock);
459
460 qp->state = IB_QPS_RESET;
ea54b10c
JM		 461 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
462 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 463
a4cd7ed8 464 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
225c7b1f
RD		 465 if (err)
466 goto err;
467
468 if (pd->uobject) {
469 struct mlx4_ib_create_qp ucmd;
470
471 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
472 err = -EFAULT;
473 goto err;
474 }
475
0e6e7416
RD		 476 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
477
83904132 478 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 479 if (err)
480 goto err;
481
225c7b1f 482 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 483 qp->buf_size, 0, 0);
225c7b1f
RD		 484 if (IS_ERR(qp->umem)) {
485 err = PTR_ERR(qp->umem);
486 goto err;
487 }
488
489 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
490 ilog2(qp->umem->page_size), &qp->mtt);
491 if (err)
492 goto err_buf;
493
494 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
495 if (err)
496 goto err_mtt;
497
02d89b87
RD		 498 if (!init_attr->srq) {
499 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
500 ucmd.db_addr, &qp->db);
501 if (err)
502 goto err_mtt;
503 }
225c7b1f 504 } else {
0e6e7416
RD		 505 qp->sq_no_prefetch = 0;
506
521e575b
RL		 507 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
508 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
509
b832be1e
EC		 510 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
511 qp->flags |= MLX4_IB_QP_LSO;
512
2446304d
EC		 513 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
514 if (err)
515 goto err;
516
02d89b87 517 if (!init_attr->srq) {
6296883c 518 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 519 if (err)
520 goto err;
225c7b1f 521
02d89b87
RD		 522 *qp->db.db = 0;
523 }
225c7b1f
RD		 524
525 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
526 err = -ENOMEM;
527 goto err_db;
528 }
529
530 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
531 &qp->mtt);
532 if (err)
533 goto err_buf;
534
535 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
536 if (err)
537 goto err_mtt;
538
0e6e7416
RD		 539 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
540 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
225c7b1f
RD		 541
542 if (!qp->sq.wrid || !qp->rq.wrid) {
543 err = -ENOMEM;
544 goto err_wrid;
545 }
225c7b1f
RD		 546 }
547
548 err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
549 if (err)
550 goto err_wrid;
551
552 /*
553 * Hardware wants QPN written in big-endian order (after
554 * shifting) for send doorbell. Precompute this value to save
555 * a little bit when posting sends.
556 */
557 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
558
225c7b1f
RD		 559 qp->mqp.event = mlx4_ib_qp_event;
560
561 return 0;
562
563err_wrid:
23f1b384
RD		 564 if (pd->uobject) {
565 if (!init_attr->srq)
566 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context),
567 &qp->db);
568 } else {
225c7b1f
RD		 569 kfree(qp->sq.wrid);
570 kfree(qp->rq.wrid);
571 }
572
573err_mtt:
574 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
575
576err_buf:
577 if (pd->uobject)
578 ib_umem_release(qp->umem);
579 else
580 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
581
582err_db:
02d89b87 583 if (!pd->uobject && !init_attr->srq)
6296883c 584 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 585
586err:
587 return err;
588}
589
590static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
591{
592 switch (state) {
593 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
594 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
595 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
596 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
597 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
598 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
599 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
600 default: return -1;
601 }
602}
603
604static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
605{
606 if (send_cq == recv_cq)
607 spin_lock_irq(&send_cq->lock);
608 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
609 spin_lock_irq(&send_cq->lock);
610 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
611 } else {
612 spin_lock_irq(&recv_cq->lock);
613 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
614 }
615}
616
617static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
618{
619 if (send_cq == recv_cq)
620 spin_unlock_irq(&send_cq->lock);
621 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
622 spin_unlock(&recv_cq->lock);
623 spin_unlock_irq(&send_cq->lock);
624 } else {
625 spin_unlock(&send_cq->lock);
626 spin_unlock_irq(&recv_cq->lock);
627 }
628}
629
630static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
631 int is_user)
632{
633 struct mlx4_ib_cq *send_cq, *recv_cq;
634
635 if (qp->state != IB_QPS_RESET)
636 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
637 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
638 printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
639 qp->mqp.qpn);
640
641 send_cq = to_mcq(qp->ibqp.send_cq);
642 recv_cq = to_mcq(qp->ibqp.recv_cq);
643
644 mlx4_ib_lock_cqs(send_cq, recv_cq);
645
646 if (!is_user) {
647 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
648 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
649 if (send_cq != recv_cq)
650 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
651 }
652
653 mlx4_qp_remove(dev->dev, &qp->mqp);
654
655 mlx4_ib_unlock_cqs(send_cq, recv_cq);
656
657 mlx4_qp_free(dev->dev, &qp->mqp);
658 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
659
660 if (is_user) {
02d89b87
RD		 661 if (!qp->ibqp.srq)
662 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
663 &qp->db);
225c7b1f
RD		 664 ib_umem_release(qp->umem);
665 } else {
666 kfree(qp->sq.wrid);
667 kfree(qp->rq.wrid);
668 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
02d89b87 669 if (!qp->ibqp.srq)
6296883c 670 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 671 }
672}
673
674struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
675 struct ib_qp_init_attr *init_attr,
676 struct ib_udata *udata)
677{
678 struct mlx4_ib_dev *dev = to_mdev(pd->device);
679 struct mlx4_ib_sqp *sqp;
680 struct mlx4_ib_qp *qp;
681 int err;
682
521e575b
RL		 683 /*
684 * We only support LSO and multicast loopback blocking, and
685 * only for kernel UD QPs.
686 */
687 if (init_attr->create_flags & ~(IB_QP_CREATE_IPOIB_UD_LSO |
688 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
b832be1e 689 return ERR_PTR(-EINVAL);
521e575b
RL		 690
691 if (init_attr->create_flags &&
b832be1e 692 (pd->uobject || init_attr->qp_type != IB_QPT_UD))
b846f25a
EC		 693 return ERR_PTR(-EINVAL);
694
225c7b1f
RD		 695 switch (init_attr->qp_type) {
696 case IB_QPT_RC:
697 case IB_QPT_UC:
698 case IB_QPT_UD:
699 {
f507d28b 700 qp = kzalloc(sizeof *qp, GFP_KERNEL);
225c7b1f
RD		 701 if (!qp)
702 return ERR_PTR(-ENOMEM);
703
704 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
705 if (err) {
706 kfree(qp);
707 return ERR_PTR(err);
708 }
709
710 qp->ibqp.qp_num = qp->mqp.qpn;
711
712 break;
713 }
714 case IB_QPT_SMI:
715 case IB_QPT_GSI:
716 {
717 /* Userspace is not allowed to create special QPs: */
718 if (pd->uobject)
719 return ERR_PTR(-EINVAL);
720
f507d28b 721 sqp = kzalloc(sizeof *sqp, GFP_KERNEL);
225c7b1f
RD		 722 if (!sqp)
723 return ERR_PTR(-ENOMEM);
724
725 qp = &sqp->qp;
726
727 err = create_qp_common(dev, pd, init_attr, udata,
728 dev->dev->caps.sqp_start +
729 (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
730 init_attr->port_num - 1,
731 qp);
732 if (err) {
733 kfree(sqp);
734 return ERR_PTR(err);
735 }
736
737 qp->port = init_attr->port_num;
738 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
739
740 break;
741 }
742 default:
743 /* Don't support raw QPs */
744 return ERR_PTR(-EINVAL);
745 }
746
747 return &qp->ibqp;
748}
749
750int mlx4_ib_destroy_qp(struct ib_qp *qp)
751{
752 struct mlx4_ib_dev *dev = to_mdev(qp->device);
753 struct mlx4_ib_qp *mqp = to_mqp(qp);
754
755 if (is_qp0(dev, mqp))
756 mlx4_CLOSE_PORT(dev->dev, mqp->port);
757
758 destroy_qp_common(dev, mqp, !!qp->pd->uobject);
759
760 if (is_sqp(dev, mqp))
761 kfree(to_msqp(mqp));
762 else
763 kfree(mqp);
764
765 return 0;
766}
767
225c7b1f
RD		 768static int to_mlx4_st(enum ib_qp_type type)
769{
770 switch (type) {
771 case IB_QPT_RC: return MLX4_QP_ST_RC;
772 case IB_QPT_UC: return MLX4_QP_ST_UC;
773 case IB_QPT_UD: return MLX4_QP_ST_UD;
774 case IB_QPT_SMI:
775 case IB_QPT_GSI: return MLX4_QP_ST_MLX;
776 default: return -1;
777 }
778}
779
65adfa91 780static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 781 int attr_mask)
782{
783 u8 dest_rd_atomic;
784 u32 access_flags;
785 u32 hw_access_flags = 0;
786
787 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
788 dest_rd_atomic = attr->max_dest_rd_atomic;
789 else
790 dest_rd_atomic = qp->resp_depth;
791
792 if (attr_mask & IB_QP_ACCESS_FLAGS)
793 access_flags = attr->qp_access_flags;
794 else
795 access_flags = qp->atomic_rd_en;
796
797 if (!dest_rd_atomic)
798 access_flags &= IB_ACCESS_REMOTE_WRITE;
799
800 if (access_flags & IB_ACCESS_REMOTE_READ)
801 hw_access_flags |= MLX4_QP_BIT_RRE;
802 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
803 hw_access_flags |= MLX4_QP_BIT_RAE;
804 if (access_flags & IB_ACCESS_REMOTE_WRITE)
805 hw_access_flags |= MLX4_QP_BIT_RWE;
806
807 return cpu_to_be32(hw_access_flags);
808}
809
65adfa91 810static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 811 int attr_mask)
812{
813 if (attr_mask & IB_QP_PKEY_INDEX)
814 sqp->pkey_index = attr->pkey_index;
815 if (attr_mask & IB_QP_QKEY)
816 sqp->qkey = attr->qkey;
817 if (attr_mask & IB_QP_SQ_PSN)
818 sqp->send_psn = attr->sq_psn;
819}
820
821static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
822{
823 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
824}
825
65adfa91 826static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
225c7b1f
RD		 827 struct mlx4_qp_path *path, u8 port)
828{
829 path->grh_mylmc = ah->src_path_bits & 0x7f;
830 path->rlid = cpu_to_be16(ah->dlid);
831 if (ah->static_rate) {
832 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
833 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
834 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
835 --path->static_rate;
836 } else
837 path->static_rate = 0;
838 path->counter_index = 0xff;
839
840 if (ah->ah_flags & IB_AH_GRH) {
5ae2a7a8 841 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
225c7b1f 842 printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
5ae2a7a8 843 ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 844 return -1;
845 }
846
847 path->grh_mylmc |= 1 << 7;
848 path->mgid_index = ah->grh.sgid_index;
849 path->hop_limit = ah->grh.hop_limit;
850 path->tclass_flowlabel =
851 cpu_to_be32((ah->grh.traffic_class << 20) |
852 (ah->grh.flow_label));
853 memcpy(path->rgid, ah->grh.dgid.raw, 16);
854 }
855
856 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
857 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
858
859 return 0;
860}
861
65adfa91
MT		 862static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
863 const struct ib_qp_attr *attr, int attr_mask,
864 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 865{
866 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
867 struct mlx4_ib_qp *qp = to_mqp(ibqp);
868 struct mlx4_qp_context *context;
869 enum mlx4_qp_optpar optpar = 0;
225c7b1f
RD		 870 int sqd_event;
871 int err = -EINVAL;
872
873 context = kzalloc(sizeof *context, GFP_KERNEL);
874 if (!context)
875 return -ENOMEM;
876
225c7b1f
RD		 877 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
878 (to_mlx4_st(ibqp->qp_type) << 16));
879 context->flags |= cpu_to_be32(1 << 8); /* DE? */
880
881 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
882 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
883 else {
884 optpar |= MLX4_QP_OPTPAR_PM_STATE;
885 switch (attr->path_mig_state) {
886 case IB_MIG_MIGRATED:
887 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
888 break;
889 case IB_MIG_REARM:
890 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
891 break;
892 case IB_MIG_ARMED:
893 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
894 break;
895 }
896 }
897
b832be1e 898 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 899 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
b832be1e
EC		 900 else if (ibqp->qp_type == IB_QPT_UD) {
901 if (qp->flags & MLX4_IB_QP_LSO)
902 context->mtu_msgmax = (IB_MTU_4096 << 5) |
903 ilog2(dev->dev->caps.max_gso_sz);
904 else
6e0d733d 905 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 906 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f
RD		 907 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
908 printk(KERN_ERR "path MTU (%u) is invalid\n",
909 attr->path_mtu);
f5b40431 910 goto out;
225c7b1f 911 }
d1f2cd89
EC		 912 context->mtu_msgmax = (attr->path_mtu << 5) |
913 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 914 }
915
0e6e7416
RD		 916 if (qp->rq.wqe_cnt)
917 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 918 context->rq_size_stride |= qp->rq.wqe_shift - 4;
919
0e6e7416
RD		 920 if (qp->sq.wqe_cnt)
921 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 922 context->sq_size_stride |= qp->sq.wqe_shift - 4;
923
0e6e7416
RD		 924 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
925 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
926
225c7b1f
RD		 927 if (qp->ibqp.uobject)
928 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
929 else
930 context->usr_page = cpu_to_be32(dev->priv_uar.index);
931
932 if (attr_mask & IB_QP_DEST_QPN)
933 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
934
935 if (attr_mask & IB_QP_PORT) {
936 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
937 !(attr_mask & IB_QP_AV)) {
938 mlx4_set_sched(&context->pri_path, attr->port_num);
939 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
940 }
941 }
942
943 if (attr_mask & IB_QP_PKEY_INDEX) {
944 context->pri_path.pkey_index = attr->pkey_index;
945 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
946 }
947
225c7b1f
RD		 948 if (attr_mask & IB_QP_AV) {
949 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
f5b40431 950 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
225c7b1f 951 goto out;
225c7b1f
RD		 952
953 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
954 MLX4_QP_OPTPAR_SCHED_QUEUE);
955 }
956
957 if (attr_mask & IB_QP_TIMEOUT) {
958 context->pri_path.ackto = attr->timeout << 3;
959 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
960 }
961
962 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 963 if (attr->alt_port_num == 0 ||
964 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 965 goto out;
225c7b1f 966
5ae2a7a8
RD		 967 if (attr->alt_pkey_index >=
968 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 969 goto out;
5ae2a7a8 970
225c7b1f
RD		 971 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
972 attr->alt_port_num))
f5b40431 973 goto out;
225c7b1f
RD		 974
975 context->alt_path.pkey_index = attr->alt_pkey_index;
976 context->alt_path.ackto = attr->alt_timeout << 3;
977 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
978 }
979
980 context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
981 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 982
95d04f07
RD		 983 /* Set "fast registration enabled" for all kernel QPs */
984 if (!qp->ibqp.uobject)
985 context->params1 |= cpu_to_be32(1 << 11);
986
57f01b53
JM		 987 if (attr_mask & IB_QP_RNR_RETRY) {
988 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
989 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
990 }
991
225c7b1f
RD		 992 if (attr_mask & IB_QP_RETRY_CNT) {
993 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
994 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
995 }
996
997 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
998 if (attr->max_rd_atomic)
999 context->params1 |=
1000 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1001 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1002 }
1003
1004 if (attr_mask & IB_QP_SQ_PSN)
1005 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1006
1007 context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
1008
1009 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1010 if (attr->max_dest_rd_atomic)
1011 context->params2 |=
1012 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1013 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1014 }
1015
1016 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1017 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1018 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1019 }
1020
1021 if (ibqp->srq)
1022 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1023
1024 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1025 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1026 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1027 }
1028 if (attr_mask & IB_QP_RQ_PSN)
1029 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1030
1031 context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
1032
1033 if (attr_mask & IB_QP_QKEY) {
1034 context->qkey = cpu_to_be32(attr->qkey);
1035 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1036 }
1037
1038 if (ibqp->srq)
1039 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1040
02d89b87 1041 if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1042 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1043
1044 if (cur_state == IB_QPS_INIT &&
1045 new_state == IB_QPS_RTR &&
1046 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1047 ibqp->qp_type == IB_QPT_UD)) {
1048 context->pri_path.sched_queue = (qp->port - 1) << 6;
1049 if (is_qp0(dev, qp))
1050 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1051 else
1052 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1053 }
1054
1055 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1056 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1057 sqd_event = 1;
1058 else
1059 sqd_event = 0;
1060
d57f5f72
VS		 1061 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1062 context->rlkey |= (1 << 4);
1063
c0be5fb5
EC		 1064 /*
1065 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1066 * ownership bits of the send queue are set and the SQ
1067 * headroom is stamped so that the hardware doesn't start
1068 * processing stale work requests.
c0be5fb5
EC		 1069 */
1070 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1071 struct mlx4_wqe_ctrl_seg *ctrl;
1072 int i;
1073
0e6e7416 1074 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1075 ctrl = get_send_wqe(qp, i);
1076 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553
EC		 1077 if (qp->sq_max_wqes_per_wr == 1)
1078 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
0e6e7416 1079
ea54b10c 1080 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 1081 }
1082 }
1083
225c7b1f
RD		 1084 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1085 to_mlx4_state(new_state), context, optpar,
1086 sqd_event, &qp->mqp);
1087 if (err)
1088 goto out;
1089
1090 qp->state = new_state;
1091
1092 if (attr_mask & IB_QP_ACCESS_FLAGS)
1093 qp->atomic_rd_en = attr->qp_access_flags;
1094 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1095 qp->resp_depth = attr->max_dest_rd_atomic;
1096 if (attr_mask & IB_QP_PORT)
1097 qp->port = attr->port_num;
1098 if (attr_mask & IB_QP_ALT_PATH)
1099 qp->alt_port = attr->alt_port_num;
1100
1101 if (is_sqp(dev, qp))
1102 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1103
1104 /*
1105 * If we moved QP0 to RTR, bring the IB link up; if we moved
1106 * QP0 to RESET or ERROR, bring the link back down.
1107 */
1108 if (is_qp0(dev, qp)) {
1109 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8
RD		 1110 if (mlx4_INIT_PORT(dev->dev, qp->port))
1111 printk(KERN_WARNING "INIT_PORT failed for port %d\n",
1112 qp->port);
225c7b1f
RD		 1113
1114 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1115 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1116 mlx4_CLOSE_PORT(dev->dev, qp->port);
1117 }
1118
1119 /*
1120 * If we moved a kernel QP to RESET, clean up all old CQ
1121 * entries and reinitialize the QP.
1122 */
1123 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1124 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
1125 ibqp->srq ? to_msrq(ibqp->srq): NULL);
1126 if (ibqp->send_cq != ibqp->recv_cq)
1127 mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
1128
1129 qp->rq.head = 0;
1130 qp->rq.tail = 0;
1131 qp->sq.head = 0;
1132 qp->sq.tail = 0;
ea54b10c 1133 qp->sq_next_wqe = 0;
02d89b87
RD		 1134 if (!ibqp->srq)
1135 *qp->db.db = 0;
225c7b1f
RD		 1136 }
1137
1138out:
225c7b1f
RD		 1139 kfree(context);
1140 return err;
1141}
1142
65adfa91
MT		 1143int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1144 int attr_mask, struct ib_udata *udata)
1145{
1146 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1147 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1148 enum ib_qp_state cur_state, new_state;
1149 int err = -EINVAL;
1150
1151 mutex_lock(&qp->mutex);
1152
1153 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1154 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1155
1156 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1157 goto out;
1158
65adfa91
MT		 1159 if ((attr_mask & IB_QP_PORT) &&
1160 (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1161 goto out;
1162 }
1163
5ae2a7a8
RD		 1164 if (attr_mask & IB_QP_PKEY_INDEX) {
1165 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1166 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1167 goto out;
1168 }
1169
65adfa91
MT		 1170 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1171 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1172 goto out;
1173 }
1174
1175 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1176 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1177 goto out;
1178 }
1179
1180 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1181 err = 0;
1182 goto out;
1183 }
1184
65adfa91
MT		 1185 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1186
1187out:
1188 mutex_unlock(&qp->mutex);
1189 return err;
1190}
1191
225c7b1f 1192static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
f438000f 1193 void *wqe, unsigned *mlx_seg_len)
225c7b1f
RD		 1194{
1195 struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1196 struct mlx4_wqe_mlx_seg *mlx = wqe;
1197 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1198 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1199 u16 pkey;
1200 int send_size;
1201 int header_size;
e61ef241 1202 int spc;
225c7b1f
RD		 1203 int i;
1204
1205 send_size = 0;
1206 for (i = 0; i < wr->num_sge; ++i)
1207 send_size += wr->sg_list[i].length;
1208
1209 ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1210
1211 sqp->ud_header.lrh.service_level =
1212 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1213 sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1214 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.g_slid & 0x7f);
1215 if (mlx4_ib_ah_grh_present(ah)) {
1216 sqp->ud_header.grh.traffic_class =
1217 (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1218 sqp->ud_header.grh.flow_label =
1219 ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
15261303 1220 sqp->ud_header.grh.hop_limit = ah->av.hop_limit;
225c7b1f
RD		 1221 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1222 ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1223 memcpy(sqp->ud_header.grh.destination_gid.raw,
1224 ah->av.dgid, 16);
1225 }
1226
1227 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1228 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1229 (sqp->ud_header.lrh.destination_lid ==
1230 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1231 (sqp->ud_header.lrh.service_level << 8));
1232 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1233
1234 switch (wr->opcode) {
1235 case IB_WR_SEND:
1236 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1237 sqp->ud_header.immediate_present = 0;
1238 break;
1239 case IB_WR_SEND_WITH_IMM:
1240 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1241 sqp->ud_header.immediate_present = 1;
0f39cf3d 1242 sqp->ud_header.immediate_data = wr->ex.imm_data;
225c7b1f
RD		 1243 break;
1244 default:
1245 return -EINVAL;
1246 }
1247
1248 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1249 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1250 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1251 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1252 if (!sqp->qp.ibqp.qp_num)
1253 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1254 else
1255 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1256 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1257 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1258 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1259 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1260 sqp->qkey : wr->wr.ud.remote_qkey);
1261 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1262
1263 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1264
1265 if (0) {
1266 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1267 for (i = 0; i < header_size / 4; ++i) {
1268 if (i % 8 == 0)
1269 printk(" [%02x] ", i * 4);
1270 printk(" %08x",
1271 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1272 if ((i + 1) % 8 == 0)
1273 printk("\n");
1274 }
1275 printk("\n");
1276 }
1277
e61ef241
RD		 1278 /*
1279 * Inline data segments may not cross a 64 byte boundary. If
1280 * our UD header is bigger than the space available up to the
1281 * next 64 byte boundary in the WQE, use two inline data
1282 * segments to hold the UD header.
1283 */
1284 spc = MLX4_INLINE_ALIGN -
1285 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1286 if (header_size <= spc) {
1287 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1288 memcpy(inl + 1, sqp->header_buf, header_size);
1289 i = 1;
1290 } else {
1291 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1292 memcpy(inl + 1, sqp->header_buf, spc);
1293
1294 inl = (void *) (inl + 1) + spc;
1295 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1296 /*
1297 * Need a barrier here to make sure all the data is
1298 * visible before the byte_count field is set.
1299 * Otherwise the HCA prefetcher could grab the 64-byte
1300 * chunk with this inline segment and get a valid (!=
1301 * 0xffffffff) byte count but stale data, and end up
1302 * generating a packet with bad headers.
1303 *
1304 * The first inline segment's byte_count field doesn't
1305 * need a barrier, because it comes after a
1306 * control/MLX segment and therefore is at an offset
1307 * of 16 mod 64.
1308 */
1309 wmb();
1310 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1311 i = 2;
1312 }
225c7b1f 1313
f438000f
RD		 1314 *mlx_seg_len =
1315 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1316 return 0;
225c7b1f
RD		 1317}
1318
1319static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1320{
1321 unsigned cur;
1322 struct mlx4_ib_cq *cq;
1323
1324 cur = wq->head - wq->tail;
0e6e7416 1325 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 1326 return 0;
1327
1328 cq = to_mcq(ib_cq);
1329 spin_lock(&cq->lock);
1330 cur = wq->head - wq->tail;
1331 spin_unlock(&cq->lock);
1332
0e6e7416 1333 return cur + nreq >= wq->max_post;
225c7b1f
RD		 1334}
1335
95d04f07
RD		 1336static __be32 convert_access(int acc)
1337{
1338 return (acc & IB_ACCESS_REMOTE_ATOMIC ? cpu_to_be32(MLX4_WQE_FMR_PERM_ATOMIC) : 0) |
1339 (acc & IB_ACCESS_REMOTE_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_WRITE) : 0) |
1340 (acc & IB_ACCESS_REMOTE_READ ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_READ) : 0) |
1341 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
1342 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
1343}
1344
1345static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
1346{
1347 struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
29bdc883
VS		 1348 int i;
1349
1350 for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
1351 wr->wr.fast_reg.page_list->page_list[i] =
1352 cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
1353 MLX4_MTT_FLAG_PRESENT);
95d04f07
RD		 1354
1355 fseg->flags = convert_access(wr->wr.fast_reg.access_flags);
1356 fseg->mem_key = cpu_to_be32(wr->wr.fast_reg.rkey);
1357 fseg->buf_list = cpu_to_be64(mfrpl->map);
1358 fseg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1359 fseg->reg_len = cpu_to_be64(wr->wr.fast_reg.length);
1360 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
1361 fseg->page_size = cpu_to_be32(wr->wr.fast_reg.page_shift);
1362 fseg->reserved[0] = 0;
1363 fseg->reserved[1] = 0;
1364}
1365
1366static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
1367{
1368 iseg->flags = 0;
1369 iseg->mem_key = cpu_to_be32(rkey);
1370 iseg->guest_id = 0;
1371 iseg->pa = 0;
1372}
1373
0fbfa6a9
RD		 1374static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1375 u64 remote_addr, u32 rkey)
1376{
1377 rseg->raddr = cpu_to_be64(remote_addr);
1378 rseg->rkey = cpu_to_be32(rkey);
1379 rseg->reserved = 0;
1380}
1381
1382static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1383{
1384 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1385 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1386 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
1387 } else {
1388 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1389 aseg->compare = 0;
1390 }
1391
1392}
1393
1394static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1395 struct ib_send_wr *wr)
1396{
1397 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1398 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1399 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
0fbfa6a9
RD		 1400}
1401
6e694ea3
JM		 1402static void set_mlx_icrc_seg(void *dseg)
1403{
1404 u32 *t = dseg;
1405 struct mlx4_wqe_inline_seg *iseg = dseg;
1406
1407 t[1] = 0;
1408
1409 /*
1410 * Need a barrier here before writing the byte_count field to
1411 * make sure that all the data is visible before the
1412 * byte_count field is set. Otherwise, if the segment begins
1413 * a new cacheline, the HCA prefetcher could grab the 64-byte
1414 * chunk and get a valid (!= * 0xffffffff) byte count but
1415 * stale data, and end up sending the wrong data.
1416 */
1417 wmb();
1418
1419 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1420}
1421
1422static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 1423{
d420d9e3
RD		 1424 dseg->lkey = cpu_to_be32(sg->lkey);
1425 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 1426
1427 /*
1428 * Need a barrier here before writing the byte_count field to
1429 * make sure that all the data is visible before the
1430 * byte_count field is set. Otherwise, if the segment begins
1431 * a new cacheline, the HCA prefetcher could grab the 64-byte
1432 * chunk and get a valid (!= * 0xffffffff) byte count but
1433 * stale data, and end up sending the wrong data.
1434 */
1435 wmb();
1436
1437 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 1438}
1439
2242fa4f
RD		 1440static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1441{
1442 dseg->byte_count = cpu_to_be32(sg->length);
1443 dseg->lkey = cpu_to_be32(sg->lkey);
1444 dseg->addr = cpu_to_be64(sg->addr);
1445}
1446
47b37475 1447static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
b832be1e
EC		 1448 struct mlx4_ib_qp *qp, unsigned *lso_seg_len)
1449{
1450 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
1451
1452 /*
1453 * This is a temporary limitation and will be removed in
1454 * a forthcoming FW release:
1455 */
1456 if (unlikely(halign > 64))
1457 return -EINVAL;
1458
1459 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
1460 wr->num_sge > qp->sq.max_gs - (halign >> 4)))
1461 return -EINVAL;
1462
1463 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
1464
1465 /* make sure LSO header is written before overwriting stamping */
1466 wmb();
1467
1468 wqe->mss_hdr_size = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
1469 wr->wr.ud.hlen);
1470
1471 *lso_seg_len = halign;
1472 return 0;
1473}
1474
95d04f07
RD		 1475static __be32 send_ieth(struct ib_send_wr *wr)
1476{
1477 switch (wr->opcode) {
1478 case IB_WR_SEND_WITH_IMM:
1479 case IB_WR_RDMA_WRITE_WITH_IMM:
1480 return wr->ex.imm_data;
1481
1482 case IB_WR_SEND_WITH_INV:
1483 return cpu_to_be32(wr->ex.invalidate_rkey);
1484
1485 default:
1486 return 0;
1487 }
1488}
1489
225c7b1f
RD		 1490int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1491 struct ib_send_wr **bad_wr)
1492{
1493 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1494 void *wqe;
1495 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 1496 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 1497 unsigned long flags;
1498 int nreq;
1499 int err = 0;
ea54b10c
JM		 1500 unsigned ind;
1501 int uninitialized_var(stamp);
1502 int uninitialized_var(size);
a3d8e159 1503 unsigned uninitialized_var(seglen);
225c7b1f
RD		 1504 int i;
1505
96db0e03 1506 spin_lock_irqsave(&qp->sq.lock, flags);
225c7b1f 1507
ea54b10c 1508 ind = qp->sq_next_wqe;
225c7b1f
RD		 1509
1510 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1511 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1512 err = -ENOMEM;
1513 *bad_wr = wr;
1514 goto out;
1515 }
1516
1517 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1518 err = -EINVAL;
1519 *bad_wr = wr;
1520 goto out;
1521 }
1522
0e6e7416 1523 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 1524 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 1525
1526 ctrl->srcrb_flags =
1527 (wr->send_flags & IB_SEND_SIGNALED ?
1528 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1529 (wr->send_flags & IB_SEND_SOLICITED ?
1530 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 1531 ((wr->send_flags & IB_SEND_IP_CSUM) ?
1532 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
1533 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 1534 qp->sq_signal_bits;
1535
95d04f07 1536 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 1537
1538 wqe += sizeof *ctrl;
1539 size = sizeof *ctrl / 16;
1540
1541 switch (ibqp->qp_type) {
1542 case IB_QPT_RC:
1543 case IB_QPT_UC:
1544 switch (wr->opcode) {
1545 case IB_WR_ATOMIC_CMP_AND_SWP:
1546 case IB_WR_ATOMIC_FETCH_AND_ADD:
0fbfa6a9
RD		 1547 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1548 wr->wr.atomic.rkey);
225c7b1f
RD		 1549 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1550
0fbfa6a9 1551 set_atomic_seg(wqe, wr);
225c7b1f 1552 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 1553
225c7b1f
RD		 1554 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1555 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1556
1557 break;
1558
1559 case IB_WR_RDMA_READ:
1560 case IB_WR_RDMA_WRITE:
1561 case IB_WR_RDMA_WRITE_WITH_IMM:
0fbfa6a9
RD		 1562 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1563 wr->wr.rdma.rkey);
225c7b1f
RD		 1564 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1565 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 1566 break;
95d04f07
RD		 1567
1568 case IB_WR_LOCAL_INV:
1569 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
1570 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
1571 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
1572 break;
1573
1574 case IB_WR_FAST_REG_MR:
1575 set_fmr_seg(wqe, wr);
1576 wqe += sizeof (struct mlx4_wqe_fmr_seg);
1577 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
1578 break;
225c7b1f
RD		 1579
1580 default:
1581 /* No extra segments required for sends */
1582 break;
1583 }
1584 break;
1585
1586 case IB_QPT_UD:
0fbfa6a9 1587 set_datagram_seg(wqe, wr);
225c7b1f
RD		 1588 wqe += sizeof (struct mlx4_wqe_datagram_seg);
1589 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 1590
1591 if (wr->opcode == IB_WR_LSO) {
1592 err = build_lso_seg(wqe, wr, qp, &seglen);
1593 if (unlikely(err)) {
1594 *bad_wr = wr;
1595 goto out;
1596 }
1597 wqe += seglen;
1598 size += seglen / 16;
1599 }
225c7b1f
RD		 1600 break;
1601
1602 case IB_QPT_SMI:
1603 case IB_QPT_GSI:
f438000f
RD		 1604 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
1605 if (unlikely(err)) {
225c7b1f
RD		 1606 *bad_wr = wr;
1607 goto out;
1608 }
f438000f
RD		 1609 wqe += seglen;
1610 size += seglen / 16;
225c7b1f
RD		 1611 break;
1612
1613 default:
1614 break;
1615 }
1616
6e694ea3
JM		 1617 /*
1618 * Write data segments in reverse order, so as to
1619 * overwrite cacheline stamp last within each
1620 * cacheline. This avoids issues with WQE
1621 * prefetching.
1622 */
225c7b1f 1623
6e694ea3
JM		 1624 dseg = wqe;
1625 dseg += wr->num_sge - 1;
1626 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 1627
1628 /* Add one more inline data segment for ICRC for MLX sends */
6e694ea3
JM		 1629 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1630 qp->ibqp.qp_type == IB_QPT_GSI)) {
1631 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 1632 size += sizeof (struct mlx4_wqe_data_seg) / 16;
1633 }
1634
6e694ea3
JM		 1635 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
1636 set_data_seg(dseg, wr->sg_list + i);
1637
225c7b1f
RD		 1638 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1639 MLX4_WQE_CTRL_FENCE : 0) | size;
1640
1641 /*
1642 * Make sure descriptor is fully written before
1643 * setting ownership bit (because HW can start
1644 * executing as soon as we do).
1645 */
1646 wmb();
1647
59b0ed12 1648 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
225c7b1f
RD		 1649 err = -EINVAL;
1650 goto out;
1651 }
1652
1653 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
0e6e7416
RD		 1654 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
1655
ea54b10c
JM		 1656 stamp = ind + qp->sq_spare_wqes;
1657 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
1658
0e6e7416
RD		 1659 /*
1660 * We can improve latency by not stamping the last
1661 * send queue WQE until after ringing the doorbell, so
1662 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 1663 *
1664 * Same optimization applies to padding with NOP wqe
1665 * in case of WQE shrinking (used to prevent wrap-around
1666 * in the middle of WR).
0e6e7416 1667 */
ea54b10c
JM		 1668 if (wr->next) {
1669 stamp_send_wqe(qp, stamp, size * 16);
1670 ind = pad_wraparound(qp, ind);
1671 }
225c7b1f 1672
225c7b1f
RD		 1673 }
1674
1675out:
1676 if (likely(nreq)) {
1677 qp->sq.head += nreq;
1678
1679 /*
1680 * Make sure that descriptors are written before
1681 * doorbell record.
1682 */
1683 wmb();
1684
1685 writel(qp->doorbell_qpn,
1686 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1687
1688 /*
1689 * Make sure doorbells don't leak out of SQ spinlock
1690 * and reach the HCA out of order.
1691 */
1692 mmiowb();
0e6e7416 1693
ea54b10c
JM		 1694 stamp_send_wqe(qp, stamp, size * 16);
1695
1696 ind = pad_wraparound(qp, ind);
1697 qp->sq_next_wqe = ind;
225c7b1f
RD		 1698 }
1699
96db0e03 1700 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 1701
1702 return err;
1703}
1704
1705int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1706 struct ib_recv_wr **bad_wr)
1707{
1708 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1709 struct mlx4_wqe_data_seg *scat;
1710 unsigned long flags;
1711 int err = 0;
1712 int nreq;
1713 int ind;
1714 int i;
1715
1716 spin_lock_irqsave(&qp->rq.lock, flags);
1717
0e6e7416 1718 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 1719
1720 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1721 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1722 err = -ENOMEM;
1723 *bad_wr = wr;
1724 goto out;
1725 }
1726
1727 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1728 err = -EINVAL;
1729 *bad_wr = wr;
1730 goto out;
1731 }
1732
1733 scat = get_recv_wqe(qp, ind);
1734
2242fa4f
RD		 1735 for (i = 0; i < wr->num_sge; ++i)
1736 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f
RD		 1737
1738 if (i < qp->rq.max_gs) {
1739 scat[i].byte_count = 0;
1740 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
1741 scat[i].addr = 0;
1742 }
1743
1744 qp->rq.wrid[ind] = wr->wr_id;
1745
0e6e7416 1746 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 1747 }
1748
1749out:
1750 if (likely(nreq)) {
1751 qp->rq.head += nreq;
1752
1753 /*
1754 * Make sure that descriptors are written before
1755 * doorbell record.
1756 */
1757 wmb();
1758
1759 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1760 }
1761
1762 spin_unlock_irqrestore(&qp->rq.lock, flags);
1763
1764 return err;
1765}
6a775e2b
JM		 1766
1767static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
1768{
1769 switch (mlx4_state) {
1770 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
1771 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
1772 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
1773 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
1774 case MLX4_QP_STATE_SQ_DRAINING:
1775 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
1776 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
1777 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
1778 default: return -1;
1779 }
1780}
1781
1782static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
1783{
1784 switch (mlx4_mig_state) {
1785 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
1786 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
1787 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
1788 default: return -1;
1789 }
1790}
1791
1792static int to_ib_qp_access_flags(int mlx4_flags)
1793{
1794 int ib_flags = 0;
1795
1796 if (mlx4_flags & MLX4_QP_BIT_RRE)
1797 ib_flags |= IB_ACCESS_REMOTE_READ;
1798 if (mlx4_flags & MLX4_QP_BIT_RWE)
1799 ib_flags |= IB_ACCESS_REMOTE_WRITE;
1800 if (mlx4_flags & MLX4_QP_BIT_RAE)
1801 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
1802
1803 return ib_flags;
1804}
1805
1806static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr,
1807 struct mlx4_qp_path *path)
1808{
8fcea95a 1809 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 1810 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
1811
1812 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
1813 return;
1814
1815 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
1816 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
1817 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
1818 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
1819 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
1820 if (ib_ah_attr->ah_flags) {
1821 ib_ah_attr->grh.sgid_index = path->mgid_index;
1822 ib_ah_attr->grh.hop_limit = path->hop_limit;
1823 ib_ah_attr->grh.traffic_class =
1824 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
1825 ib_ah_attr->grh.flow_label =
586bb586 1826 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 1827 memcpy(ib_ah_attr->grh.dgid.raw,
1828 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
1829 }
1830}
1831
1832int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1833 struct ib_qp_init_attr *qp_init_attr)
1834{
1835 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1836 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1837 struct mlx4_qp_context context;
1838 int mlx4_state;
0df67030
DB		 1839 int err = 0;
1840
1841 mutex_lock(&qp->mutex);
6a775e2b
JM		 1842
1843 if (qp->state == IB_QPS_RESET) {
1844 qp_attr->qp_state = IB_QPS_RESET;
1845 goto done;
1846 }
1847
1848 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 1849 if (err) {
1850 err = -EINVAL;
1851 goto out;
1852 }
6a775e2b
JM		 1853
1854 mlx4_state = be32_to_cpu(context.flags) >> 28;
1855
0df67030
DB		 1856 qp->state = to_ib_qp_state(mlx4_state);
1857 qp_attr->qp_state = qp->state;
6a775e2b
JM		 1858 qp_attr->path_mtu = context.mtu_msgmax >> 5;
1859 qp_attr->path_mig_state =
1860 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
1861 qp_attr->qkey = be32_to_cpu(context.qkey);
1862 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
1863 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
1864 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
1865 qp_attr->qp_access_flags =
1866 to_ib_qp_access_flags(be32_to_cpu(context.params2));
1867
1868 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
1869 to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path);
1870 to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path);
1871 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
1872 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
1873 }
1874
1875 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 1876 if (qp_attr->qp_state == IB_QPS_INIT)
1877 qp_attr->port_num = qp->port;
1878 else
1879 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 1880
1881 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
1882 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
1883
1884 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
1885
1886 qp_attr->max_dest_rd_atomic =
1887 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
1888 qp_attr->min_rnr_timer =
1889 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
1890 qp_attr->timeout = context.pri_path.ackto >> 3;
1891 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
1892 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
1893 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
1894
1895done:
1896 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 1897 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
1898 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
1899
6a775e2b 1900 if (!ibqp->uobject) {
7f5eb9bb
RD		 1901 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
1902 qp_attr->cap.max_send_sge = qp->sq.max_gs;
1903 } else {
1904 qp_attr->cap.max_send_wr = 0;
1905 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 1906 }
1907
7f5eb9bb
RD		 1908 /*
1909 * We don't support inline sends for kernel QPs (yet), and we
1910 * don't know what userspace's value should be.
1911 */
1912 qp_attr->cap.max_inline_data = 0;
1913
1914 qp_init_attr->cap = qp_attr->cap;
1915
521e575b
RL		 1916 qp_init_attr->create_flags = 0;
1917 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1918 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
1919
1920 if (qp->flags & MLX4_IB_QP_LSO)
1921 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
1922
0df67030
DB		 1923out:
1924 mutex_unlock(&qp->mutex);
1925 return err;
6a775e2b
JM		 1926}
1927
Linux 6.x block layer and io_uring tree(s)