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IB/mlx4: Implement ib_device callbacks
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
5a0e3ad6 35#include <linux/slab.h>
fa417f7b 36#include <linux/netdevice.h>
ea54b10c 37
225c7b1f
RD		 38#include <rdma/ib_cache.h>
39#include <rdma/ib_pack.h>
4c3eb3ca 40#include <rdma/ib_addr.h>
1ffeb2eb 41#include <rdma/ib_mad.h>
225c7b1f 42
2f48485d 43#include <linux/mlx4/driver.h>
225c7b1f
RD		 44#include <linux/mlx4/qp.h>
45
46#include "mlx4_ib.h"
47#include "user.h"
48
35f05dab
YH		 49static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
50 struct mlx4_ib_cq *recv_cq);
51static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
52 struct mlx4_ib_cq *recv_cq);
53
225c7b1f
RD		 54enum {
55 MLX4_IB_ACK_REQ_FREQ = 8,
56};
57
58enum {
59 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 60 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
61 MLX4_IB_LINK_TYPE_IB = 0,
62 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 63};
64
65enum {
66 /*
fa417f7b 67 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 68 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
69 * tag. (LRH would only use 8 bytes, so Ethernet is the
70 * biggest case)
225c7b1f 71 */
4c3eb3ca 72 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 73 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 74};
75
fa417f7b
EC		 76enum {
77 MLX4_IB_IBOE_ETHERTYPE = 0x8915
78};
79
225c7b1f
RD		 80struct mlx4_ib_sqp {
81 struct mlx4_ib_qp qp;
82 int pkey_index;
83 u32 qkey;
84 u32 send_psn;
85 struct ib_ud_header ud_header;
86 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
87};
88
83904132 89enum {
417608c2
EC		 90 MLX4_IB_MIN_SQ_STRIDE = 6,
91 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 92};
93
3987a2d3
OG		 94enum {
95 MLX4_RAW_QP_MTU = 7,
96 MLX4_RAW_QP_MSGMAX = 31,
97};
98
297e0dad
MS		 99#ifndef ETH_ALEN
100#define ETH_ALEN 6
101#endif
297e0dad 102
225c7b1f 103static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
114 [IB_WR_FAST_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
6ff63e19 117 [IB_WR_BIND_MW] = cpu_to_be32(MLX4_OPCODE_BIND_MW),
225c7b1f
RD		 118};
119
120static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
121{
122 return container_of(mqp, struct mlx4_ib_sqp, qp);
123}
124
1ffeb2eb
JM		 125static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
126{
127 if (!mlx4_is_master(dev->dev))
128 return 0;
129
47605df9
JM		 130 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
131 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
132 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 133}
134
225c7b1f
RD		 135static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
136{
47605df9
JM		 137 int proxy_sqp = 0;
138 int real_sqp = 0;
139 int i;
140 /* PPF or Native -- real SQP */
141 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
142 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
143 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
144 if (real_sqp)
145 return 1;
146 /* VF or PF -- proxy SQP */
147 if (mlx4_is_mfunc(dev->dev)) {
148 for (i = 0; i < dev->dev->caps.num_ports; i++) {
149 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
150 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
151 proxy_sqp = 1;
152 break;
153 }
154 }
155 }
156 return proxy_sqp;
225c7b1f
RD		 157}
158
1ffeb2eb 159/* used for INIT/CLOSE port logic */
225c7b1f
RD		 160static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
161{
47605df9
JM		 162 int proxy_qp0 = 0;
163 int real_qp0 = 0;
164 int i;
165 /* PPF or Native -- real QP0 */
166 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
167 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
168 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
169 if (real_qp0)
170 return 1;
171 /* VF or PF -- proxy QP0 */
172 if (mlx4_is_mfunc(dev->dev)) {
173 for (i = 0; i < dev->dev->caps.num_ports; i++) {
174 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
175 proxy_qp0 = 1;
176 break;
177 }
178 }
179 }
180 return proxy_qp0;
225c7b1f
RD		 181}
182
183static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
184{
1c69fc2a 185 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 186}
187
188static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
189{
190 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
191}
192
193static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
194{
195 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
196}
197
0e6e7416
RD		 198/*
199 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 200 * first four bytes of every 64 byte chunk with
201 * 0x7FFFFFF | (invalid_ownership_value << 31).
202 *
203 * When the max work request size is less than or equal to the WQE
204 * basic block size, as an optimization, we can stamp all WQEs with
205 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 206 */
ea54b10c 207static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 208{
d2ae16d5 209 __be32 *wqe;
0e6e7416 210 int i;
ea54b10c
JM		 211 int s;
212 int ind;
213 void *buf;
214 __be32 stamp;
9670e553 215 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 216
ea54b10c 217 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 218 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 219 for (i = 0; i < s; i += 64) {
220 ind = (i >> qp->sq.wqe_shift) + n;
221 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
222 cpu_to_be32(0xffffffff);
223 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
224 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
225 *wqe = stamp;
226 }
227 } else {
9670e553
EC		 228 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
229 s = (ctrl->fence_size & 0x3f) << 4;
ea54b10c
JM		 230 for (i = 64; i < s; i += 64) {
231 wqe = buf + i;
d2ae16d5 232 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 233 }
234 }
235}
236
237static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
238{
239 struct mlx4_wqe_ctrl_seg *ctrl;
240 struct mlx4_wqe_inline_seg *inl;
241 void *wqe;
242 int s;
243
244 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
245 s = sizeof(struct mlx4_wqe_ctrl_seg);
246
247 if (qp->ibqp.qp_type == IB_QPT_UD) {
248 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
249 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
250 memset(dgram, 0, sizeof *dgram);
251 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
252 s += sizeof(struct mlx4_wqe_datagram_seg);
253 }
254
255 /* Pad the remainder of the WQE with an inline data segment. */
256 if (size > s) {
257 inl = wqe + s;
258 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
259 }
260 ctrl->srcrb_flags = 0;
261 ctrl->fence_size = size / 16;
262 /*
263 * Make sure descriptor is fully written before setting ownership bit
264 * (because HW can start executing as soon as we do).
265 */
266 wmb();
267
268 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
269 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 270
ea54b10c
JM		 271 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
272}
273
274/* Post NOP WQE to prevent wrap-around in the middle of WR */
275static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
276{
277 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
278 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
279 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
280 ind += s;
281 }
282 return ind;
0e6e7416
RD		 283}
284
225c7b1f
RD		 285static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
286{
287 struct ib_event event;
288 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
289
290 if (type == MLX4_EVENT_TYPE_PATH_MIG)
291 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
292
293 if (ibqp->event_handler) {
294 event.device = ibqp->device;
295 event.element.qp = ibqp;
296 switch (type) {
297 case MLX4_EVENT_TYPE_PATH_MIG:
298 event.event = IB_EVENT_PATH_MIG;
299 break;
300 case MLX4_EVENT_TYPE_COMM_EST:
301 event.event = IB_EVENT_COMM_EST;
302 break;
303 case MLX4_EVENT_TYPE_SQ_DRAINED:
304 event.event = IB_EVENT_SQ_DRAINED;
305 break;
306 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
307 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
308 break;
309 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
310 event.event = IB_EVENT_QP_FATAL;
311 break;
312 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
313 event.event = IB_EVENT_PATH_MIG_ERR;
314 break;
315 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
316 event.event = IB_EVENT_QP_REQ_ERR;
317 break;
318 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
319 event.event = IB_EVENT_QP_ACCESS_ERR;
320 break;
321 default:
987c8f8f 322 pr_warn("Unexpected event type %d "
225c7b1f
RD		 323 "on QP %06x\n", type, qp->qpn);
324 return;
325 }
326
327 ibqp->event_handler(&event, ibqp->qp_context);
328 }
329}
330
1ffeb2eb 331static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 332{
333 /*
334 * UD WQEs must have a datagram segment.
335 * RC and UC WQEs might have a remote address segment.
336 * MLX WQEs need two extra inline data segments (for the UD
337 * header and space for the ICRC).
338 */
339 switch (type) {
1ffeb2eb 340 case MLX4_IB_QPT_UD:
225c7b1f 341 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 342 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 343 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 344 case MLX4_IB_QPT_PROXY_SMI_OWNER:
345 case MLX4_IB_QPT_PROXY_SMI:
346 case MLX4_IB_QPT_PROXY_GSI:
347 return sizeof (struct mlx4_wqe_ctrl_seg) +
348 sizeof (struct mlx4_wqe_datagram_seg) + 64;
349 case MLX4_IB_QPT_TUN_SMI_OWNER:
350 case MLX4_IB_QPT_TUN_GSI:
351 return sizeof (struct mlx4_wqe_ctrl_seg) +
352 sizeof (struct mlx4_wqe_datagram_seg);
353
354 case MLX4_IB_QPT_UC:
225c7b1f
RD		 355 return sizeof (struct mlx4_wqe_ctrl_seg) +
356 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 357 case MLX4_IB_QPT_RC:
225c7b1f
RD		 358 return sizeof (struct mlx4_wqe_ctrl_seg) +
359 sizeof (struct mlx4_wqe_atomic_seg) +
360 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 361 case MLX4_IB_QPT_SMI:
362 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 363 return sizeof (struct mlx4_wqe_ctrl_seg) +
364 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 365 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
366 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 367 sizeof (struct mlx4_wqe_inline_seg),
368 sizeof (struct mlx4_wqe_data_seg)) +
369 ALIGN(4 +
370 sizeof (struct mlx4_wqe_inline_seg),
371 sizeof (struct mlx4_wqe_data_seg));
372 default:
373 return sizeof (struct mlx4_wqe_ctrl_seg);
374 }
375}
376
2446304d 377static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
0a1405da 378 int is_user, int has_rq, struct mlx4_ib_qp *qp)
225c7b1f 379{
2446304d 380 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 381 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
382 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 383 return -EINVAL;
384
0a1405da 385 if (!has_rq) {
a4cd7ed8
RD		 386 if (cap->max_recv_wr)
387 return -EINVAL;
2446304d 388
0e6e7416 389 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 390 } else {
391 /* HW requires >= 1 RQ entry with >= 1 gather entry */
392 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
393 return -EINVAL;
394
0e6e7416 395 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 396 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 397 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
398 }
2446304d 399
fc2d0044
SG		 400 /* leave userspace return values as they were, so as not to break ABI */
401 if (is_user) {
402 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
403 cap->max_recv_sge = qp->rq.max_gs;
404 } else {
405 cap->max_recv_wr = qp->rq.max_post =
406 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
407 cap->max_recv_sge = min(qp->rq.max_gs,
408 min(dev->dev->caps.max_sq_sg,
409 dev->dev->caps.max_rq_sg));
410 }
2446304d
EC		 411
412 return 0;
413}
414
415static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
1ffeb2eb 416 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 417{
ea54b10c
JM		 418 int s;
419
2446304d 420 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 421 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
422 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 423 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 424 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
425 return -EINVAL;
426
427 /*
428 * For MLX transport we need 2 extra S/G entries:
429 * one for the header and one for the checksum at the end
430 */
1ffeb2eb
JM		 431 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
432 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 433 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
434 return -EINVAL;
435
ea54b10c
JM		 436 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
437 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 438 send_wqe_overhead(type, qp->flags);
225c7b1f 439
cd155c1c
RD		 440 if (s > dev->dev->caps.max_sq_desc_sz)
441 return -EINVAL;
442
0e6e7416 443 /*
ea54b10c
JM		 444 * Hermon supports shrinking WQEs, such that a single work
445 * request can include multiple units of 1 << wqe_shift. This
446 * way, work requests can differ in size, and do not have to
447 * be a power of 2 in size, saving memory and speeding up send
448 * WR posting. Unfortunately, if we do this then the
449 * wqe_index field in CQEs can't be used to look up the WR ID
450 * anymore, so we do this only if selective signaling is off.
451 *
452 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 453 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 454 * constant-sized WRs to make sure a WR is always fully within
455 * a single page-sized chunk.
456 *
457 * Finally, we use NOP work requests to pad the end of the
458 * work queue, to avoid wrap-around in the middle of WR. We
459 * set NEC bit to avoid getting completions with error for
460 * these NOP WRs, but since NEC is only supported starting
461 * with firmware 2.2.232, we use constant-sized WRs for older
462 * firmware.
463 *
464 * And, since MLX QPs only support SEND, we use constant-sized
465 * WRs in this case.
466 *
467 * We look for the smallest value of wqe_shift such that the
468 * resulting number of wqes does not exceed device
469 * capabilities.
470 *
471 * We set WQE size to at least 64 bytes, this way stamping
472 * invalidates each WQE.
0e6e7416 473 */
ea54b10c
JM		 474 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
475 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 476 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
477 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
478 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 479 qp->sq.wqe_shift = ilog2(64);
480 else
481 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
482
483 for (;;) {
ea54b10c
JM		 484 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
485
486 /*
487 * We need to leave 2 KB + 1 WR of headroom in the SQ to
488 * allow HW to prefetch.
489 */
490 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
491 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
492 qp->sq_max_wqes_per_wr +
493 qp->sq_spare_wqes);
494
495 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
496 break;
497
498 if (qp->sq_max_wqes_per_wr <= 1)
499 return -EINVAL;
500
501 ++qp->sq.wqe_shift;
502 }
503
cd155c1c
RD		 504 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
505 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 506 send_wqe_overhead(type, qp->flags)) /
507 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 508
509 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
510 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 511 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
512 qp->rq.offset = 0;
0e6e7416 513 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 514 } else {
0e6e7416 515 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 516 qp->sq.offset = 0;
517 }
518
ea54b10c
JM		 519 cap->max_send_wr = qp->sq.max_post =
520 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 521 cap->max_send_sge = min(qp->sq.max_gs,
522 min(dev->dev->caps.max_sq_sg,
523 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 524 /* We don't support inline sends for kernel QPs (yet) */
525 cap->max_inline_data = 0;
225c7b1f
RD		 526
527 return 0;
528}
529
83904132
JM		 530static int set_user_sq_size(struct mlx4_ib_dev *dev,
531 struct mlx4_ib_qp *qp,
2446304d
EC		 532 struct mlx4_ib_create_qp *ucmd)
533{
83904132
JM		 534 /* Sanity check SQ size before proceeding */
535 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
536 ucmd->log_sq_stride >
537 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
538 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
539 return -EINVAL;
540
0e6e7416 541 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 542 qp->sq.wqe_shift = ucmd->log_sq_stride;
543
0e6e7416
RD		 544 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
545 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 546
547 return 0;
548}
549
1ffeb2eb
JM		 550static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
551{
552 int i;
553
554 qp->sqp_proxy_rcv =
555 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
556 GFP_KERNEL);
557 if (!qp->sqp_proxy_rcv)
558 return -ENOMEM;
559 for (i = 0; i < qp->rq.wqe_cnt; i++) {
560 qp->sqp_proxy_rcv[i].addr =
561 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
562 GFP_KERNEL);
563 if (!qp->sqp_proxy_rcv[i].addr)
564 goto err;
565 qp->sqp_proxy_rcv[i].map =
566 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
567 sizeof (struct mlx4_ib_proxy_sqp_hdr),
568 DMA_FROM_DEVICE);
cc47d369
SO		 569 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
570 kfree(qp->sqp_proxy_rcv[i].addr);
571 goto err;
572 }
1ffeb2eb
JM		 573 }
574 return 0;
575
576err:
577 while (i > 0) {
578 --i;
579 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
580 sizeof (struct mlx4_ib_proxy_sqp_hdr),
581 DMA_FROM_DEVICE);
582 kfree(qp->sqp_proxy_rcv[i].addr);
583 }
584 kfree(qp->sqp_proxy_rcv);
585 qp->sqp_proxy_rcv = NULL;
586 return -ENOMEM;
587}
588
589static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
590{
591 int i;
592
593 for (i = 0; i < qp->rq.wqe_cnt; i++) {
594 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
595 sizeof (struct mlx4_ib_proxy_sqp_hdr),
596 DMA_FROM_DEVICE);
597 kfree(qp->sqp_proxy_rcv[i].addr);
598 }
599 kfree(qp->sqp_proxy_rcv);
600}
601
0a1405da
SH		 602static int qp_has_rq(struct ib_qp_init_attr *attr)
603{
604 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
605 return 0;
606
607 return !attr->srq;
608}
609
99ec41d0
JM		 610static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
611{
612 int i;
613 for (i = 0; i < dev->caps.num_ports; i++) {
614 if (qpn == dev->caps.qp0_proxy[i])
615 return !!dev->caps.qp0_qkey[i];
616 }
617 return 0;
618}
619
225c7b1f
RD		 620static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
621 struct ib_qp_init_attr *init_attr,
40f2287b
JK		 622 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
623 gfp_t gfp)
225c7b1f 624{
a3cdcbfa 625 int qpn;
225c7b1f 626 int err;
1ffeb2eb
JM		 627 struct mlx4_ib_sqp *sqp;
628 struct mlx4_ib_qp *qp;
629 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 630 struct mlx4_ib_cq *mcq;
631 unsigned long flags;
1ffeb2eb
JM		 632
633 /* When tunneling special qps, we use a plain UD qp */
634 if (sqpn) {
635 if (mlx4_is_mfunc(dev->dev) &&
636 (!mlx4_is_master(dev->dev) ||
637 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
638 if (init_attr->qp_type == IB_QPT_GSI)
639 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 640 else {
641 if (mlx4_is_master(dev->dev) ||
642 qp0_enabled_vf(dev->dev, sqpn))
643 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
644 else
645 qp_type = MLX4_IB_QPT_PROXY_SMI;
646 }
1ffeb2eb
JM		 647 }
648 qpn = sqpn;
649 /* add extra sg entry for tunneling */
650 init_attr->cap.max_recv_sge++;
651 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
652 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
653 container_of(init_attr,
654 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
655 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
656 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
657 !mlx4_is_master(dev->dev))
658 return -EINVAL;
659 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
660 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 661 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
662 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
663 tnl_init->port))
1ffeb2eb
JM		 664 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
665 else
666 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 667 /* we are definitely in the PPF here, since we are creating
668 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
669 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
670 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 671 sqpn = qpn;
672 }
673
674 if (!*caller_qp) {
675 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
676 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
677 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6fcd8d0d 678 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
1ffeb2eb
JM		 679 if (!sqp)
680 return -ENOMEM;
681 qp = &sqp->qp;
2f5bb473
JM		 682 qp->pri.vid = 0xFFFF;
683 qp->alt.vid = 0xFFFF;
1ffeb2eb 684 } else {
6fcd8d0d 685 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
1ffeb2eb
JM		 686 if (!qp)
687 return -ENOMEM;
2f5bb473
JM		 688 qp->pri.vid = 0xFFFF;
689 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 690 }
691 } else
692 qp = *caller_qp;
693
694 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 695
696 mutex_init(&qp->mutex);
697 spin_lock_init(&qp->sq.lock);
698 spin_lock_init(&qp->rq.lock);
fa417f7b 699 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 700 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 701
702 qp->state = IB_QPS_RESET;
ea54b10c
JM		 703 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
704 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 705
0a1405da 706 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
225c7b1f
RD		 707 if (err)
708 goto err;
709
710 if (pd->uobject) {
711 struct mlx4_ib_create_qp ucmd;
712
713 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
714 err = -EFAULT;
715 goto err;
716 }
717
0e6e7416
RD		 718 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
719
83904132 720 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 721 if (err)
722 goto err;
723
225c7b1f 724 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 725 qp->buf_size, 0, 0);
225c7b1f
RD		 726 if (IS_ERR(qp->umem)) {
727 err = PTR_ERR(qp->umem);
728 goto err;
729 }
730
731 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
732 ilog2(qp->umem->page_size), &qp->mtt);
733 if (err)
734 goto err_buf;
735
736 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
737 if (err)
738 goto err_mtt;
739
0a1405da 740 if (qp_has_rq(init_attr)) {
02d89b87
RD		 741 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
742 ucmd.db_addr, &qp->db);
743 if (err)
744 goto err_mtt;
745 }
225c7b1f 746 } else {
0e6e7416
RD		 747 qp->sq_no_prefetch = 0;
748
521e575b
RL		 749 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
750 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
751
b832be1e
EC		 752 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
753 qp->flags |= MLX4_IB_QP_LSO;
754
c1c98501
MB		 755 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
756 if (dev->steering_support ==
757 MLX4_STEERING_MODE_DEVICE_MANAGED)
758 qp->flags |= MLX4_IB_QP_NETIF;
759 else
760 goto err;
761 }
762
1ffeb2eb 763 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 764 if (err)
765 goto err;
766
0a1405da 767 if (qp_has_rq(init_attr)) {
40f2287b 768 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
02d89b87
RD		 769 if (err)
770 goto err;
225c7b1f 771
02d89b87
RD		 772 *qp->db.db = 0;
773 }
225c7b1f 774
40f2287b 775 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
225c7b1f
RD		 776 err = -ENOMEM;
777 goto err_db;
778 }
779
780 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
781 &qp->mtt);
782 if (err)
783 goto err_buf;
784
40f2287b 785 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
225c7b1f
RD		 786 if (err)
787 goto err_mtt;
788
40f2287b
JK		 789 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), gfp);
790 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), gfp);
225c7b1f
RD		 791 if (!qp->sq.wrid || !qp->rq.wrid) {
792 err = -ENOMEM;
793 goto err_wrid;
794 }
225c7b1f
RD		 795 }
796
a3cdcbfa 797 if (sqpn) {
1ffeb2eb
JM		 798 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
799 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
800 if (alloc_proxy_bufs(pd->device, qp)) {
801 err = -ENOMEM;
802 goto err_wrid;
803 }
804 }
a3cdcbfa 805 } else {
ddae0349
EE		 806 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
807 * otherwise, the WQE BlueFlame setup flow wrongly causes
808 * VLAN insertion. */
3987a2d3 809 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 810 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 811 (init_attr->cap.max_send_wr ?
812 MLX4_RESERVE_ETH_BF_QP : 0) |
813 (init_attr->cap.max_recv_wr ?
814 MLX4_RESERVE_A0_QP : 0));
3987a2d3 815 else
c1c98501
MB		 816 if (qp->flags & MLX4_IB_QP_NETIF)
817 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
818 else
819 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
ddae0349 820 &qpn, 0);
a3cdcbfa 821 if (err)
1ffeb2eb 822 goto err_proxy;
a3cdcbfa
YP		 823 }
824
40f2287b 825 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
225c7b1f 826 if (err)
a3cdcbfa 827 goto err_qpn;
225c7b1f 828
0a1405da
SH		 829 if (init_attr->qp_type == IB_QPT_XRC_TGT)
830 qp->mqp.qpn |= (1 << 23);
831
225c7b1f
RD		 832 /*
833 * Hardware wants QPN written in big-endian order (after
834 * shifting) for send doorbell. Precompute this value to save
835 * a little bit when posting sends.
836 */
837 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
838
225c7b1f 839 qp->mqp.event = mlx4_ib_qp_event;
1ffeb2eb
JM		 840 if (!*caller_qp)
841 *caller_qp = qp;
35f05dab
YH		 842
843 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
844 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
845 to_mcq(init_attr->recv_cq));
846 /* Maintain device to QPs access, needed for further handling
847 * via reset flow
848 */
849 list_add_tail(&qp->qps_list, &dev->qp_list);
850 /* Maintain CQ to QPs access, needed for further handling
851 * via reset flow
852 */
853 mcq = to_mcq(init_attr->send_cq);
854 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
855 mcq = to_mcq(init_attr->recv_cq);
856 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
857 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
858 to_mcq(init_attr->recv_cq));
859 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 860 return 0;
861
a3cdcbfa 862err_qpn:
c1c98501
MB		 863 if (!sqpn) {
864 if (qp->flags & MLX4_IB_QP_NETIF)
865 mlx4_ib_steer_qp_free(dev, qpn, 1);
866 else
867 mlx4_qp_release_range(dev->dev, qpn, 1);
868 }
1ffeb2eb
JM		 869err_proxy:
870 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
871 free_proxy_bufs(pd->device, qp);
225c7b1f 872err_wrid:
23f1b384 873 if (pd->uobject) {
0a1405da
SH		 874 if (qp_has_rq(init_attr))
875 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 876 } else {
225c7b1f
RD		 877 kfree(qp->sq.wrid);
878 kfree(qp->rq.wrid);
879 }
880
881err_mtt:
882 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
883
884err_buf:
885 if (pd->uobject)
886 ib_umem_release(qp->umem);
887 else
888 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
889
890err_db:
0a1405da 891 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 892 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 893
894err:
1ffeb2eb
JM		 895 if (!*caller_qp)
896 kfree(qp);
225c7b1f
RD		 897 return err;
898}
899
900static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
901{
902 switch (state) {
903 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
904 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
905 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
906 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
907 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
908 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
909 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
910 default: return -1;
911 }
912}
913
914static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 915 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 916{
338a8fad 917 if (send_cq == recv_cq) {
35f05dab 918 spin_lock(&send_cq->lock);
338a8fad
RD		 919 __acquire(&recv_cq->lock);
920 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 921 spin_lock(&send_cq->lock);
225c7b1f
RD		 922 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
923 } else {
35f05dab 924 spin_lock(&recv_cq->lock);
225c7b1f
RD		 925 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
926 }
927}
928
929static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 930 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 931{
338a8fad
RD		 932 if (send_cq == recv_cq) {
933 __release(&recv_cq->lock);
35f05dab 934 spin_unlock(&send_cq->lock);
338a8fad 935 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 936 spin_unlock(&recv_cq->lock);
35f05dab 937 spin_unlock(&send_cq->lock);
225c7b1f
RD		 938 } else {
939 spin_unlock(&send_cq->lock);
35f05dab 940 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 941 }
942}
943
fa417f7b
EC		 944static void del_gid_entries(struct mlx4_ib_qp *qp)
945{
946 struct mlx4_ib_gid_entry *ge, *tmp;
947
948 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
949 list_del(&ge->list);
950 kfree(ge);
951 }
952}
953
0a1405da
SH		 954static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
955{
956 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
957 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
958 else
959 return to_mpd(qp->ibqp.pd);
960}
961
962static void get_cqs(struct mlx4_ib_qp *qp,
963 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
964{
965 switch (qp->ibqp.qp_type) {
966 case IB_QPT_XRC_TGT:
967 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
968 *recv_cq = *send_cq;
969 break;
970 case IB_QPT_XRC_INI:
971 *send_cq = to_mcq(qp->ibqp.send_cq);
972 *recv_cq = *send_cq;
973 break;
974 default:
975 *send_cq = to_mcq(qp->ibqp.send_cq);
976 *recv_cq = to_mcq(qp->ibqp.recv_cq);
977 break;
978 }
979}
980
225c7b1f
RD		 981static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
982 int is_user)
983{
984 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 985 unsigned long flags;
225c7b1f 986
2f5bb473 987 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 988 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
989 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 990 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 991 qp->mqp.qpn);
25476b02 992 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 993 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
994 qp->pri.smac = 0;
25476b02 995 qp->pri.smac_port = 0;
2f5bb473
JM		 996 }
997 if (qp->alt.smac) {
998 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
999 qp->alt.smac = 0;
1000 }
1001 if (qp->pri.vid < 0x1000) {
1002 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1003 qp->pri.vid = 0xFFFF;
1004 qp->pri.candidate_vid = 0xFFFF;
1005 qp->pri.update_vid = 0;
1006 }
1007 if (qp->alt.vid < 0x1000) {
1008 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1009 qp->alt.vid = 0xFFFF;
1010 qp->alt.candidate_vid = 0xFFFF;
1011 qp->alt.update_vid = 0;
1012 }
1013 }
225c7b1f 1014
0a1405da 1015 get_cqs(qp, &send_cq, &recv_cq);
225c7b1f 1016
35f05dab 1017 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1018 mlx4_ib_lock_cqs(send_cq, recv_cq);
1019
35f05dab
YH		 1020 /* del from lists under both locks above to protect reset flow paths */
1021 list_del(&qp->qps_list);
1022 list_del(&qp->cq_send_list);
1023 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1024 if (!is_user) {
1025 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1026 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1027 if (send_cq != recv_cq)
1028 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1029 }
1030
1031 mlx4_qp_remove(dev->dev, &qp->mqp);
1032
1033 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1034 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1035
1036 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1037
c1c98501
MB		 1038 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1039 if (qp->flags & MLX4_IB_QP_NETIF)
1040 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1041 else
1042 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1043 }
a3cdcbfa 1044
225c7b1f
RD		 1045 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1046
1047 if (is_user) {
0a1405da 1048 if (qp->rq.wqe_cnt)
02d89b87
RD		 1049 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1050 &qp->db);
225c7b1f
RD		 1051 ib_umem_release(qp->umem);
1052 } else {
1053 kfree(qp->sq.wrid);
1054 kfree(qp->rq.wrid);
1ffeb2eb
JM		 1055 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1056 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1057 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1058 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1059 if (qp->rq.wqe_cnt)
6296883c 1060 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1061 }
fa417f7b
EC		 1062
1063 del_gid_entries(qp);
225c7b1f
RD		 1064}
1065
47605df9
JM		 1066static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1067{
1068 /* Native or PPF */
1069 if (!mlx4_is_mfunc(dev->dev) ||
1070 (mlx4_is_master(dev->dev) &&
1071 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1072 return dev->dev->phys_caps.base_sqpn +
1073 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1074 attr->port_num - 1;
1075 }
1076 /* PF or VF -- creating proxies */
1077 if (attr->qp_type == IB_QPT_SMI)
1078 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1079 else
1080 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1081}
1082
225c7b1f
RD		 1083struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1084 struct ib_qp_init_attr *init_attr,
1085 struct ib_udata *udata)
1086{
1ffeb2eb 1087 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1088 int err;
0a1405da 1089 u16 xrcdn = 0;
40f2287b 1090 gfp_t gfp;
225c7b1f 1091
40f2287b
JK		 1092 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1093 GFP_NOIO : GFP_KERNEL;
521e575b 1094 /*
1ffeb2eb
JM		 1095 * We only support LSO, vendor flag1, and multicast loopback blocking,
1096 * and only for kernel UD QPs.
521e575b 1097 */
1ffeb2eb
JM		 1098 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1099 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1100 MLX4_IB_SRIOV_TUNNEL_QP |
1101 MLX4_IB_SRIOV_SQP |
40f2287b
JK		 1102 MLX4_IB_QP_NETIF |
1103 MLX4_IB_QP_CREATE_USE_GFP_NOIO))
b832be1e 1104 return ERR_PTR(-EINVAL);
521e575b 1105
c1c98501
MB		 1106 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1107 if (init_attr->qp_type != IB_QPT_UD)
1108 return ERR_PTR(-EINVAL);
1109 }
1110
521e575b 1111 if (init_attr->create_flags &&
1ffeb2eb 1112 (udata ||
40f2287b 1113 ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | MLX4_IB_QP_CREATE_USE_GFP_NOIO)) &&
1ffeb2eb
JM		 1114 init_attr->qp_type != IB_QPT_UD) ||
1115 ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1116 init_attr->qp_type > IB_QPT_GSI)))
b846f25a
EC		 1117 return ERR_PTR(-EINVAL);
1118
225c7b1f 1119 switch (init_attr->qp_type) {
0a1405da
SH		 1120 case IB_QPT_XRC_TGT:
1121 pd = to_mxrcd(init_attr->xrcd)->pd;
1122 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1123 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1124 /* fall through */
1125 case IB_QPT_XRC_INI:
1126 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1127 return ERR_PTR(-ENOSYS);
1128 init_attr->recv_cq = init_attr->send_cq;
1129 /* fall through */
225c7b1f
RD		 1130 case IB_QPT_RC:
1131 case IB_QPT_UC:
3987a2d3 1132 case IB_QPT_RAW_PACKET:
40f2287b 1133 qp = kzalloc(sizeof *qp, gfp);
225c7b1f
RD		 1134 if (!qp)
1135 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1136 qp->pri.vid = 0xFFFF;
1137 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1138 /* fall through */
1139 case IB_QPT_UD:
1140 {
1141 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
40f2287b 1142 udata, 0, &qp, gfp);
1ffeb2eb 1143 if (err)
225c7b1f 1144 return ERR_PTR(err);
225c7b1f
RD		 1145
1146 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1147 qp->xrcdn = xrcdn;
225c7b1f
RD		 1148
1149 break;
1150 }
1151 case IB_QPT_SMI:
1152 case IB_QPT_GSI:
1153 {
1154 /* Userspace is not allowed to create special QPs: */
0a1405da 1155 if (udata)
225c7b1f
RD		 1156 return ERR_PTR(-EINVAL);
1157
0a1405da 1158 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
47605df9 1159 get_sqp_num(to_mdev(pd->device), init_attr),
40f2287b 1160 &qp, gfp);
1ffeb2eb 1161 if (err)
225c7b1f 1162 return ERR_PTR(err);
225c7b1f
RD		 1163
1164 qp->port = init_attr->port_num;
1165 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1166
1167 break;
1168 }
1169 default:
1170 /* Don't support raw QPs */
1171 return ERR_PTR(-EINVAL);
1172 }
1173
1174 return &qp->ibqp;
1175}
1176
1177int mlx4_ib_destroy_qp(struct ib_qp *qp)
1178{
1179 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1180 struct mlx4_ib_qp *mqp = to_mqp(qp);
0a1405da 1181 struct mlx4_ib_pd *pd;
225c7b1f
RD		 1182
1183 if (is_qp0(dev, mqp))
1184 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1185
9433c188
MB		 1186 if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1187 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1188 dev->qp1_proxy[mqp->port - 1] = NULL;
1189 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1190 }
1191
0a1405da
SH		 1192 pd = get_pd(mqp);
1193 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
225c7b1f
RD		 1194
1195 if (is_sqp(dev, mqp))
1196 kfree(to_msqp(mqp));
1197 else
1198 kfree(mqp);
1199
1200 return 0;
1201}
1202
1ffeb2eb 1203static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1204{
1205 switch (type) {
1ffeb2eb
JM		 1206 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1207 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1208 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1209 case MLX4_IB_QPT_XRC_INI:
1210 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1211 case MLX4_IB_QPT_SMI:
1212 case MLX4_IB_QPT_GSI:
1213 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1214
1215 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1216 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1217 MLX4_QP_ST_MLX : -1);
1218 case MLX4_IB_QPT_PROXY_SMI:
1219 case MLX4_IB_QPT_TUN_SMI:
1220 case MLX4_IB_QPT_PROXY_GSI:
1221 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1222 MLX4_QP_ST_UD : -1);
1223 default: return -1;
225c7b1f
RD		 1224 }
1225}
1226
65adfa91 1227static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1228 int attr_mask)
1229{
1230 u8 dest_rd_atomic;
1231 u32 access_flags;
1232 u32 hw_access_flags = 0;
1233
1234 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1235 dest_rd_atomic = attr->max_dest_rd_atomic;
1236 else
1237 dest_rd_atomic = qp->resp_depth;
1238
1239 if (attr_mask & IB_QP_ACCESS_FLAGS)
1240 access_flags = attr->qp_access_flags;
1241 else
1242 access_flags = qp->atomic_rd_en;
1243
1244 if (!dest_rd_atomic)
1245 access_flags &= IB_ACCESS_REMOTE_WRITE;
1246
1247 if (access_flags & IB_ACCESS_REMOTE_READ)
1248 hw_access_flags |= MLX4_QP_BIT_RRE;
1249 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1250 hw_access_flags |= MLX4_QP_BIT_RAE;
1251 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1252 hw_access_flags |= MLX4_QP_BIT_RWE;
1253
1254 return cpu_to_be32(hw_access_flags);
1255}
1256
65adfa91 1257static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1258 int attr_mask)
1259{
1260 if (attr_mask & IB_QP_PKEY_INDEX)
1261 sqp->pkey_index = attr->pkey_index;
1262 if (attr_mask & IB_QP_QKEY)
1263 sqp->qkey = attr->qkey;
1264 if (attr_mask & IB_QP_SQ_PSN)
1265 sqp->send_psn = attr->sq_psn;
1266}
1267
1268static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1269{
1270 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1271}
1272
297e0dad
MS		 1273static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1274 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1275 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1276{
fa417f7b
EC		 1277 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1278 IB_LINK_LAYER_ETHERNET;
4c3eb3ca 1279 int vidx;
297e0dad 1280 int smac_index;
2f5bb473 1281 int err;
297e0dad 1282
fa417f7b 1283
225c7b1f
RD		 1284 path->grh_mylmc = ah->src_path_bits & 0x7f;
1285 path->rlid = cpu_to_be16(ah->dlid);
1286 if (ah->static_rate) {
1287 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1288 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1289 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1290 --path->static_rate;
1291 } else
1292 path->static_rate = 0;
225c7b1f
RD		 1293
1294 if (ah->ah_flags & IB_AH_GRH) {
5ae2a7a8 1295 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1296 pr_err("sgid_index (%u) too large. max is %d\n",
5ae2a7a8 1297 ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1298 return -1;
1299 }
1300
1301 path->grh_mylmc |= 1 << 7;
1302 path->mgid_index = ah->grh.sgid_index;
1303 path->hop_limit = ah->grh.hop_limit;
1304 path->tclass_flowlabel =
1305 cpu_to_be32((ah->grh.traffic_class << 20) |
1306 (ah->grh.flow_label));
1307 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1308 }
1309
fa417f7b
EC		 1310 if (is_eth) {
1311 if (!(ah->ah_flags & IB_AH_GRH))
1312 return -1;
1313
2f5bb473
JM		 1314 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1315 ((port - 1) << 6) | ((ah->sl & 7) << 3);
4c3eb3ca 1316
297e0dad 1317 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1318 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1319 if (smac_info->vid < 0x1000) {
1320 /* both valid vlan ids */
1321 if (smac_info->vid != vlan_tag) {
1322 /* different VIDs. unreg old and reg new */
1323 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1324 if (err)
1325 return err;
1326 smac_info->candidate_vid = vlan_tag;
1327 smac_info->candidate_vlan_index = vidx;
1328 smac_info->candidate_vlan_port = port;
1329 smac_info->update_vid = 1;
1330 path->vlan_index = vidx;
1331 } else {
1332 path->vlan_index = smac_info->vlan_index;
1333 }
1334 } else {
1335 /* no current vlan tag in qp */
1336 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1337 if (err)
1338 return err;
1339 smac_info->candidate_vid = vlan_tag;
1340 smac_info->candidate_vlan_index = vidx;
1341 smac_info->candidate_vlan_port = port;
1342 smac_info->update_vid = 1;
1343 path->vlan_index = vidx;
1344 }
297e0dad 1345 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1346 path->fl = 1 << 6;
1347 } else {
1348 /* have current vlan tag. unregister it at modify-qp success */
1349 if (smac_info->vid < 0x1000) {
1350 smac_info->candidate_vid = 0xFFFF;
1351 smac_info->update_vid = 1;
1352 }
4c3eb3ca 1353 }
2f5bb473
JM		 1354
1355 /* get smac_index for RoCE use.
1356 * If no smac was yet assigned, register one.
1357 * If one was already assigned, but the new mac differs,
1358 * unregister the old one and register the new one.
1359 */
25476b02
JM		 1360 if ((!smac_info->smac && !smac_info->smac_port) ||
1361 smac_info->smac != smac) {
2f5bb473
JM		 1362 /* register candidate now, unreg if needed, after success */
1363 smac_index = mlx4_register_mac(dev->dev, port, smac);
1364 if (smac_index >= 0) {
1365 smac_info->candidate_smac_index = smac_index;
1366 smac_info->candidate_smac = smac;
1367 smac_info->candidate_smac_port = port;
1368 } else {
1369 return -EINVAL;
1370 }
1371 } else {
1372 smac_index = smac_info->smac_index;
1373 }
1374
1375 memcpy(path->dmac, ah->dmac, 6);
1376 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1377 /* put MAC table smac index for IBoE */
1378 path->grh_mylmc = (u8) (smac_index) | 0x80;
1379 } else {
4c3eb3ca
EC		 1380 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1381 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
2f5bb473 1382 }
fa417f7b 1383
225c7b1f
RD		 1384 return 0;
1385}
1386
297e0dad
MS		 1387static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1388 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1389 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1390 struct mlx4_qp_path *path, u8 port)
1391{
1392 return _mlx4_set_path(dev, &qp->ah_attr,
1393 mlx4_mac_to_u64((u8 *)qp->smac),
1394 (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff,
2f5bb473 1395 path, &mqp->pri, port);
297e0dad
MS		 1396}
1397
1398static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1399 const struct ib_qp_attr *qp,
1400 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1401 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1402 struct mlx4_qp_path *path, u8 port)
1403{
1404 return _mlx4_set_path(dev, &qp->alt_ah_attr,
1405 mlx4_mac_to_u64((u8 *)qp->alt_smac),
1406 (qp_attr_mask & IB_QP_ALT_VID) ?
1407 qp->alt_vlan_id : 0xffff,
2f5bb473 1408 path, &mqp->alt, port);
297e0dad
MS		 1409}
1410
fa417f7b
EC		 1411static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1412{
1413 struct mlx4_ib_gid_entry *ge, *tmp;
1414
1415 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1416 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1417 ge->added = 1;
1418 ge->port = qp->port;
1419 }
1420 }
1421}
1422
2f5bb473
JM		 1423static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, u8 *smac,
1424 struct mlx4_qp_context *context)
1425{
2f5bb473
JM		 1426 u64 u64_mac;
1427 int smac_index;
1428
3e0629cb 1429 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1430
1431 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1432 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1433 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1434 if (smac_index >= 0) {
1435 qp->pri.candidate_smac_index = smac_index;
1436 qp->pri.candidate_smac = u64_mac;
1437 qp->pri.candidate_smac_port = qp->port;
1438 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1439 } else {
1440 return -ENOENT;
1441 }
1442 }
1443 return 0;
1444}
1445
65adfa91
MT		 1446static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1447 const struct ib_qp_attr *attr, int attr_mask,
1448 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 1449{
1450 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1451 struct mlx4_ib_qp *qp = to_mqp(ibqp);
0a1405da
SH		 1452 struct mlx4_ib_pd *pd;
1453 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 1454 struct mlx4_qp_context *context;
1455 enum mlx4_qp_optpar optpar = 0;
225c7b1f 1456 int sqd_event;
c1c98501 1457 int steer_qp = 0;
225c7b1f
RD		 1458 int err = -EINVAL;
1459
3dec4878
JM		 1460 /* APM is not supported under RoCE */
1461 if (attr_mask & IB_QP_ALT_PATH &&
1462 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1463 IB_LINK_LAYER_ETHERNET)
1464 return -ENOTSUPP;
1465
225c7b1f
RD		 1466 context = kzalloc(sizeof *context, GFP_KERNEL);
1467 if (!context)
1468 return -ENOMEM;
1469
225c7b1f 1470 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 1471 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 1472
1473 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1474 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1475 else {
1476 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1477 switch (attr->path_mig_state) {
1478 case IB_MIG_MIGRATED:
1479 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1480 break;
1481 case IB_MIG_REARM:
1482 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1483 break;
1484 case IB_MIG_ARMED:
1485 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1486 break;
1487 }
1488 }
1489
b832be1e 1490 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 1491 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
3987a2d3
OG		 1492 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1493 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
b832be1e
EC		 1494 else if (ibqp->qp_type == IB_QPT_UD) {
1495 if (qp->flags & MLX4_IB_QP_LSO)
1496 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1497 ilog2(dev->dev->caps.max_gso_sz);
1498 else
6e0d733d 1499 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 1500 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 1501 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 1502 pr_err("path MTU (%u) is invalid\n",
225c7b1f 1503 attr->path_mtu);
f5b40431 1504 goto out;
225c7b1f 1505 }
d1f2cd89
EC		 1506 context->mtu_msgmax = (attr->path_mtu << 5) |
1507 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 1508 }
1509
0e6e7416
RD		 1510 if (qp->rq.wqe_cnt)
1511 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 1512 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1513
0e6e7416
RD		 1514 if (qp->sq.wqe_cnt)
1515 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 1516 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1517
0a1405da 1518 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 1519 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 1520 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
02d7ef6f
DB		 1521 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1522 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 1523 }
0e6e7416 1524
225c7b1f
RD		 1525 if (qp->ibqp.uobject)
1526 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1527 else
1528 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1529
1530 if (attr_mask & IB_QP_DEST_QPN)
1531 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1532
1533 if (attr_mask & IB_QP_PORT) {
1534 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1535 !(attr_mask & IB_QP_AV)) {
1536 mlx4_set_sched(&context->pri_path, attr->port_num);
1537 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1538 }
1539 }
1540
cfcde11c 1541 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
c3abb51b 1542 if (dev->counters[qp->port - 1].index != -1) {
cfcde11c 1543 context->pri_path.counter_index =
c3abb51b 1544 dev->counters[qp->port - 1].index;
cfcde11c
OG		 1545 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1546 } else
47d8417f
EBE		 1547 context->pri_path.counter_index =
1548 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 1549
1550 if (qp->flags & MLX4_IB_QP_NETIF) {
1551 mlx4_ib_steer_qp_reg(dev, qp, 1);
1552 steer_qp = 1;
1553 }
cfcde11c
OG		 1554 }
1555
225c7b1f 1556 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 1557 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1558 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 1559 context->pri_path.pkey_index = attr->pkey_index;
1560 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1561 }
1562
225c7b1f 1563 if (attr_mask & IB_QP_AV) {
2f5bb473 1564 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1ffeb2eb
JM		 1565 attr_mask & IB_QP_PORT ?
1566 attr->port_num : qp->port))
225c7b1f 1567 goto out;
225c7b1f
RD		 1568
1569 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1570 MLX4_QP_OPTPAR_SCHED_QUEUE);
1571 }
1572
1573 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 1574 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 1575 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1576 }
1577
1578 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 1579 if (attr->alt_port_num == 0 ||
1580 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 1581 goto out;
225c7b1f 1582
5ae2a7a8
RD		 1583 if (attr->alt_pkey_index >=
1584 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 1585 goto out;
5ae2a7a8 1586
2f5bb473
JM		 1587 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1588 &context->alt_path,
297e0dad 1589 attr->alt_port_num))
f5b40431 1590 goto out;
225c7b1f
RD		 1591
1592 context->alt_path.pkey_index = attr->alt_pkey_index;
1593 context->alt_path.ackto = attr->alt_timeout << 3;
1594 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1595 }
1596
0a1405da
SH		 1597 pd = get_pd(qp);
1598 get_cqs(qp, &send_cq, &recv_cq);
1599 context->pd = cpu_to_be32(pd->pdn);
1600 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1601 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1602 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 1603
95d04f07
RD		 1604 /* Set "fast registration enabled" for all kernel QPs */
1605 if (!qp->ibqp.uobject)
1606 context->params1 |= cpu_to_be32(1 << 11);
1607
57f01b53
JM		 1608 if (attr_mask & IB_QP_RNR_RETRY) {
1609 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1610 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1611 }
1612
225c7b1f
RD		 1613 if (attr_mask & IB_QP_RETRY_CNT) {
1614 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1615 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1616 }
1617
1618 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1619 if (attr->max_rd_atomic)
1620 context->params1 |=
1621 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1622 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1623 }
1624
1625 if (attr_mask & IB_QP_SQ_PSN)
1626 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1627
225c7b1f
RD		 1628 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1629 if (attr->max_dest_rd_atomic)
1630 context->params2 |=
1631 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1632 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1633 }
1634
1635 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1636 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1637 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1638 }
1639
1640 if (ibqp->srq)
1641 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1642
1643 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1644 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1645 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1646 }
1647 if (attr_mask & IB_QP_RQ_PSN)
1648 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1649
1ffeb2eb 1650 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 1651 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 1652 if (qp->mlx4_ib_qp_type &
1653 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1654 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1655 else {
1656 if (mlx4_is_mfunc(dev->dev) &&
1657 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1658 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1659 MLX4_RESERVED_QKEY_BASE) {
1660 pr_err("Cannot use reserved QKEY"
1661 " 0x%x (range 0xffff0000..0xffffffff"
1662 " is reserved)\n", attr->qkey);
1663 err = -EINVAL;
1664 goto out;
1665 }
1666 context->qkey = cpu_to_be32(attr->qkey);
1667 }
225c7b1f
RD		 1668 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1669 }
1670
1671 if (ibqp->srq)
1672 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1673
0a1405da 1674 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1675 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1676
1677 if (cur_state == IB_QPS_INIT &&
1678 new_state == IB_QPS_RTR &&
1679 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
3987a2d3
OG		 1680 ibqp->qp_type == IB_QPT_UD ||
1681 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 1682 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 1683 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1684 qp->mlx4_ib_qp_type &
1685 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 1686 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 1687 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1688 context->pri_path.fl = 0x80;
1689 } else {
1690 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1691 context->pri_path.fl = 0x80;
225c7b1f 1692 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 1693 }
2f5bb473
JM		 1694 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1695 IB_LINK_LAYER_ETHERNET) {
1696 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1697 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1698 context->pri_path.feup = 1 << 7; /* don't fsm */
1699 /* handle smac_index */
1700 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1701 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1702 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1703 err = handle_eth_ud_smac_index(dev, qp, (u8 *)attr->smac, context);
bede98e7
MD		 1704 if (err) {
1705 err = -EINVAL;
1706 goto out;
1707 }
9433c188
MB		 1708 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1709 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 1710 }
1711 }
225c7b1f
RD		 1712 }
1713
d2fce8a9 1714 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 1715 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1716 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 1717 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1718 /* set QP to receive both tunneled & non-tunneled packets */
8e1a03b6 1719 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
d2fce8a9
OG		 1720 context->srqn = cpu_to_be32(7 << 28);
1721 }
1722 }
3528f696 1723
297e0dad
MS		 1724 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1725 int is_eth = rdma_port_get_link_layer(
1726 &dev->ib_dev, qp->port) ==
1727 IB_LINK_LAYER_ETHERNET;
1728 if (is_eth) {
1729 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1730 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1731 }
1732 }
1733
1734
225c7b1f
RD		 1735 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1736 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1737 sqd_event = 1;
1738 else
1739 sqd_event = 0;
1740
d57f5f72
VS		 1741 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1742 context->rlkey |= (1 << 4);
1743
c0be5fb5
EC		 1744 /*
1745 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1746 * ownership bits of the send queue are set and the SQ
1747 * headroom is stamped so that the hardware doesn't start
1748 * processing stale work requests.
c0be5fb5
EC		 1749 */
1750 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1751 struct mlx4_wqe_ctrl_seg *ctrl;
1752 int i;
1753
0e6e7416 1754 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1755 ctrl = get_send_wqe(qp, i);
1756 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553
EC		 1757 if (qp->sq_max_wqes_per_wr == 1)
1758 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
0e6e7416 1759
ea54b10c 1760 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 1761 }
1762 }
1763
225c7b1f
RD		 1764 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1765 to_mlx4_state(new_state), context, optpar,
1766 sqd_event, &qp->mqp);
1767 if (err)
1768 goto out;
1769
1770 qp->state = new_state;
1771
1772 if (attr_mask & IB_QP_ACCESS_FLAGS)
1773 qp->atomic_rd_en = attr->qp_access_flags;
1774 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1775 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 1776 if (attr_mask & IB_QP_PORT) {
225c7b1f 1777 qp->port = attr->port_num;
fa417f7b
EC		 1778 update_mcg_macs(dev, qp);
1779 }
225c7b1f
RD		 1780 if (attr_mask & IB_QP_ALT_PATH)
1781 qp->alt_port = attr->alt_port_num;
1782
1783 if (is_sqp(dev, qp))
1784 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1785
1786 /*
1787 * If we moved QP0 to RTR, bring the IB link up; if we moved
1788 * QP0 to RESET or ERROR, bring the link back down.
1789 */
1790 if (is_qp0(dev, qp)) {
1791 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 1792 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 1793 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 1794 qp->port);
225c7b1f
RD		 1795
1796 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1797 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1798 mlx4_CLOSE_PORT(dev->dev, qp->port);
1799 }
1800
1801 /*
1802 * If we moved a kernel QP to RESET, clean up all old CQ
1803 * entries and reinitialize the QP.
1804 */
2f5bb473
JM		 1805 if (new_state == IB_QPS_RESET) {
1806 if (!ibqp->uobject) {
1807 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1808 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1809 if (send_cq != recv_cq)
1810 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1811
1812 qp->rq.head = 0;
1813 qp->rq.tail = 0;
1814 qp->sq.head = 0;
1815 qp->sq.tail = 0;
1816 qp->sq_next_wqe = 0;
1817 if (qp->rq.wqe_cnt)
1818 *qp->db.db = 0;
225c7b1f 1819
2f5bb473
JM		 1820 if (qp->flags & MLX4_IB_QP_NETIF)
1821 mlx4_ib_steer_qp_reg(dev, qp, 0);
1822 }
25476b02 1823 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1824 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1825 qp->pri.smac = 0;
25476b02 1826 qp->pri.smac_port = 0;
2f5bb473
JM		 1827 }
1828 if (qp->alt.smac) {
1829 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1830 qp->alt.smac = 0;
1831 }
1832 if (qp->pri.vid < 0x1000) {
1833 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1834 qp->pri.vid = 0xFFFF;
1835 qp->pri.candidate_vid = 0xFFFF;
1836 qp->pri.update_vid = 0;
1837 }
c1c98501 1838
2f5bb473
JM		 1839 if (qp->alt.vid < 0x1000) {
1840 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1841 qp->alt.vid = 0xFFFF;
1842 qp->alt.candidate_vid = 0xFFFF;
1843 qp->alt.update_vid = 0;
1844 }
225c7b1f 1845 }
225c7b1f 1846out:
c1c98501
MB		 1847 if (err && steer_qp)
1848 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 1849 kfree(context);
25476b02
JM		 1850 if (qp->pri.candidate_smac ||
1851 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 1852 if (err) {
1853 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1854 } else {
25476b02 1855 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 1856 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1857 qp->pri.smac = qp->pri.candidate_smac;
1858 qp->pri.smac_index = qp->pri.candidate_smac_index;
1859 qp->pri.smac_port = qp->pri.candidate_smac_port;
1860 }
1861 qp->pri.candidate_smac = 0;
1862 qp->pri.candidate_smac_index = 0;
1863 qp->pri.candidate_smac_port = 0;
1864 }
1865 if (qp->alt.candidate_smac) {
1866 if (err) {
1867 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1868 } else {
1869 if (qp->alt.smac)
1870 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1871 qp->alt.smac = qp->alt.candidate_smac;
1872 qp->alt.smac_index = qp->alt.candidate_smac_index;
1873 qp->alt.smac_port = qp->alt.candidate_smac_port;
1874 }
1875 qp->alt.candidate_smac = 0;
1876 qp->alt.candidate_smac_index = 0;
1877 qp->alt.candidate_smac_port = 0;
1878 }
1879
1880 if (qp->pri.update_vid) {
1881 if (err) {
1882 if (qp->pri.candidate_vid < 0x1000)
1883 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1884 qp->pri.candidate_vid);
1885 } else {
1886 if (qp->pri.vid < 0x1000)
1887 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1888 qp->pri.vid);
1889 qp->pri.vid = qp->pri.candidate_vid;
1890 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1891 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
1892 }
1893 qp->pri.candidate_vid = 0xFFFF;
1894 qp->pri.update_vid = 0;
1895 }
1896
1897 if (qp->alt.update_vid) {
1898 if (err) {
1899 if (qp->alt.candidate_vid < 0x1000)
1900 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
1901 qp->alt.candidate_vid);
1902 } else {
1903 if (qp->alt.vid < 0x1000)
1904 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
1905 qp->alt.vid);
1906 qp->alt.vid = qp->alt.candidate_vid;
1907 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
1908 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
1909 }
1910 qp->alt.candidate_vid = 0xFFFF;
1911 qp->alt.update_vid = 0;
1912 }
1913
225c7b1f
RD		 1914 return err;
1915}
1916
65adfa91
MT		 1917int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1918 int attr_mask, struct ib_udata *udata)
1919{
1920 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1921 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1922 enum ib_qp_state cur_state, new_state;
1923 int err = -EINVAL;
297e0dad 1924 int ll;
65adfa91
MT		 1925 mutex_lock(&qp->mutex);
1926
1927 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1928 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1929
297e0dad
MS		 1930 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1931 ll = IB_LINK_LAYER_UNSPECIFIED;
1932 } else {
1933 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1934 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
1935 }
dd5f03be
MB		 1936
1937 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 1938 attr_mask, ll)) {
b1d8eb5a
JM		 1939 pr_debug("qpn 0x%x: invalid attribute mask specified "
1940 "for transition %d to %d. qp_type %d,"
1941 " attr_mask 0x%x\n",
1942 ibqp->qp_num, cur_state, new_state,
1943 ibqp->qp_type, attr_mask);
65adfa91 1944 goto out;
b1d8eb5a 1945 }
65adfa91 1946
c6215745
MS		 1947 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
1948 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
1949 if ((ibqp->qp_type == IB_QPT_RC) ||
1950 (ibqp->qp_type == IB_QPT_UD) ||
1951 (ibqp->qp_type == IB_QPT_UC) ||
1952 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
1953 (ibqp->qp_type == IB_QPT_XRC_INI)) {
1954 attr->port_num = mlx4_ib_bond_next_port(dev);
1955 }
1956 } else {
1957 /* no sense in changing port_num
1958 * when ports are bonded */
1959 attr_mask &= ~IB_QP_PORT;
1960 }
1961 }
1962
65adfa91 1963 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 1964 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 1965 pr_debug("qpn 0x%x: invalid port number (%d) specified "
1966 "for transition %d to %d. qp_type %d\n",
1967 ibqp->qp_num, attr->port_num, cur_state,
1968 new_state, ibqp->qp_type);
65adfa91
MT		 1969 goto out;
1970 }
1971
3987a2d3
OG		 1972 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1973 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1974 IB_LINK_LAYER_ETHERNET))
1975 goto out;
1976
5ae2a7a8
RD		 1977 if (attr_mask & IB_QP_PKEY_INDEX) {
1978 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 1979 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
1980 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
1981 "for transition %d to %d. qp_type %d\n",
1982 ibqp->qp_num, attr->pkey_index, cur_state,
1983 new_state, ibqp->qp_type);
5ae2a7a8 1984 goto out;
b1d8eb5a 1985 }
5ae2a7a8
RD		 1986 }
1987
65adfa91
MT		 1988 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1989 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 1990 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
1991 "Transition %d to %d. qp_type %d\n",
1992 ibqp->qp_num, attr->max_rd_atomic, cur_state,
1993 new_state, ibqp->qp_type);
65adfa91
MT		 1994 goto out;
1995 }
1996
1997 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1998 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 1999 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2000 "Transition %d to %d. qp_type %d\n",
2001 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2002 new_state, ibqp->qp_type);
65adfa91
MT		 2003 goto out;
2004 }
2005
2006 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2007 err = 0;
2008 goto out;
2009 }
2010
65adfa91
MT		 2011 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2012
c6215745
MS		 2013 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2014 attr->port_num = 1;
2015
65adfa91
MT		 2016out:
2017 mutex_unlock(&qp->mutex);
2018 return err;
2019}
2020
99ec41d0
JM		 2021static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2022{
2023 int i;
2024 for (i = 0; i < dev->caps.num_ports; i++) {
2025 if (qpn == dev->caps.qp0_proxy[i] ||
2026 qpn == dev->caps.qp0_tunnel[i]) {
2027 *qkey = dev->caps.qp0_qkey[i];
2028 return 0;
2029 }
2030 }
2031 return -EINVAL;
2032}
2033
1ffeb2eb
JM		 2034static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2035 struct ib_send_wr *wr,
2036 void *wqe, unsigned *mlx_seg_len)
2037{
2038 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2039 struct ib_device *ib_dev = &mdev->ib_dev;
2040 struct mlx4_wqe_mlx_seg *mlx = wqe;
2041 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2042 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2043 u16 pkey;
2044 u32 qkey;
2045 int send_size;
2046 int header_size;
2047 int spc;
2048 int i;
2049
2050 if (wr->opcode != IB_WR_SEND)
2051 return -EINVAL;
2052
2053 send_size = 0;
2054
2055 for (i = 0; i < wr->num_sge; ++i)
2056 send_size += wr->sg_list[i].length;
2057
2058 /* for proxy-qp0 sends, need to add in size of tunnel header */
2059 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2060 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2061 send_size += sizeof (struct mlx4_ib_tunnel_header);
2062
2063 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
2064
2065 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2066 sqp->ud_header.lrh.service_level =
2067 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2068 sqp->ud_header.lrh.destination_lid =
2069 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2070 sqp->ud_header.lrh.source_lid =
2071 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2072 }
2073
2074 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2075
2076 /* force loopback */
2077 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2078 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2079
2080 sqp->ud_header.lrh.virtual_lane = 0;
2081 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2082 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2083 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2084 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2085 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2086 else
2087 sqp->ud_header.bth.destination_qpn =
47605df9 2088 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 2089
2090 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2091 if (mlx4_is_master(mdev->dev)) {
2092 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2093 return -EINVAL;
2094 } else {
2095 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2096 return -EINVAL;
2097 }
1ffeb2eb
JM		 2098 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2099 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2100
2101 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2102 sqp->ud_header.immediate_present = 0;
2103
2104 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2105
2106 /*
2107 * Inline data segments may not cross a 64 byte boundary. If
2108 * our UD header is bigger than the space available up to the
2109 * next 64 byte boundary in the WQE, use two inline data
2110 * segments to hold the UD header.
2111 */
2112 spc = MLX4_INLINE_ALIGN -
2113 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2114 if (header_size <= spc) {
2115 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2116 memcpy(inl + 1, sqp->header_buf, header_size);
2117 i = 1;
2118 } else {
2119 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2120 memcpy(inl + 1, sqp->header_buf, spc);
2121
2122 inl = (void *) (inl + 1) + spc;
2123 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2124 /*
2125 * Need a barrier here to make sure all the data is
2126 * visible before the byte_count field is set.
2127 * Otherwise the HCA prefetcher could grab the 64-byte
2128 * chunk with this inline segment and get a valid (!=
2129 * 0xffffffff) byte count but stale data, and end up
2130 * generating a packet with bad headers.
2131 *
2132 * The first inline segment's byte_count field doesn't
2133 * need a barrier, because it comes after a
2134 * control/MLX segment and therefore is at an offset
2135 * of 16 mod 64.
2136 */
2137 wmb();
2138 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2139 i = 2;
2140 }
2141
2142 *mlx_seg_len =
2143 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2144 return 0;
2145}
2146
3e0629cb
JM		 2147static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2148{
2149 int i;
2150
2151 for (i = ETH_ALEN; i; i--) {
2152 dst_mac[i - 1] = src_mac & 0xff;
2153 src_mac >>= 8;
2154 }
2155}
2156
225c7b1f 2157static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
f438000f 2158 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2159{
a478868a 2160 struct ib_device *ib_dev = sqp->qp.ibqp.device;
225c7b1f 2161 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2162 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f
RD		 2163 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2164 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
4c3eb3ca 2165 union ib_gid sgid;
225c7b1f
RD		 2166 u16 pkey;
2167 int send_size;
2168 int header_size;
e61ef241 2169 int spc;
225c7b1f 2170 int i;
1ffeb2eb 2171 int err = 0;
57d88cff 2172 u16 vlan = 0xffff;
a29bec12
RD		 2173 bool is_eth;
2174 bool is_vlan = false;
2175 bool is_grh;
225c7b1f
RD		 2176
2177 send_size = 0;
2178 for (i = 0; i < wr->num_sge; ++i)
2179 send_size += wr->sg_list[i].length;
2180
fa417f7b
EC		 2181 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2182 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 2183 if (is_eth) {
1ffeb2eb
JM		 2184 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2185 /* When multi-function is enabled, the ib_core gid
2186 * indexes don't necessarily match the hw ones, so
2187 * we must use our own cache */
6ee51a4e
JM		 2188 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2189 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2190 ah->av.ib.gid_index, &sgid.raw[0]);
2191 if (err)
2192 return err;
1ffeb2eb
JM		 2193 } else {
2194 err = ib_get_cached_gid(ib_dev,
2195 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2196 ah->av.ib.gid_index, &sgid);
2197 if (err)
2198 return err;
2199 }
2200
0e9855db 2201 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 2202 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2203 is_vlan = 1;
2204 }
4c3eb3ca
EC		 2205 }
2206 ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
fa417f7b
EC		 2207
2208 if (!is_eth) {
2209 sqp->ud_header.lrh.service_level =
2210 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2211 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2212 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2213 }
225c7b1f 2214
fa417f7b 2215 if (is_grh) {
225c7b1f 2216 sqp->ud_header.grh.traffic_class =
fa417f7b 2217 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 2218 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 2219 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2220 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
6ee51a4e
JM		 2221 if (is_eth)
2222 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2223 else {
1ffeb2eb
JM		 2224 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2225 /* When multi-function is enabled, the ib_core gid
2226 * indexes don't necessarily match the hw ones, so
2227 * we must use our own cache */
2228 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2229 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2230 subnet_prefix;
2231 sqp->ud_header.grh.source_gid.global.interface_id =
2232 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2233 guid_cache[ah->av.ib.gid_index];
2234 } else
2235 ib_get_cached_gid(ib_dev,
2236 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2237 ah->av.ib.gid_index,
2238 &sqp->ud_header.grh.source_gid);
6ee51a4e 2239 }
225c7b1f 2240 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 2241 ah->av.ib.dgid, 16);
225c7b1f
RD		 2242 }
2243
2244 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 2245
2246 if (!is_eth) {
2247 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2248 (sqp->ud_header.lrh.destination_lid ==
2249 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2250 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 2251 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2252 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 2253 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2254 }
225c7b1f
RD		 2255
2256 switch (wr->opcode) {
2257 case IB_WR_SEND:
2258 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2259 sqp->ud_header.immediate_present = 0;
2260 break;
2261 case IB_WR_SEND_WITH_IMM:
2262 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2263 sqp->ud_header.immediate_present = 1;
0f39cf3d 2264 sqp->ud_header.immediate_data = wr->ex.imm_data;
225c7b1f
RD		 2265 break;
2266 default:
2267 return -EINVAL;
2268 }
2269
fa417f7b 2270 if (is_eth) {
6ee51a4e
JM		 2271 struct in6_addr in6;
2272
c0c1d3d7
OD		 2273 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2274
2275 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b
EC		 2276
2277 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2278 /* FIXME: cache smac value? */
6ee51a4e
JM		 2279 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2280 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2281 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 2282
3e0629cb
JM		 2283 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2284 u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2285 u8 smac[ETH_ALEN];
2286
2287 mlx4_u64_to_smac(smac, mac);
2288 memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2289 } else {
2290 /* use the src mac of the tunnel */
2291 memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2292 }
2293
fa417f7b
EC		 2294 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2295 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca
EC		 2296 if (!is_vlan) {
2297 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2298 } else {
4c3eb3ca 2299 sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
4c3eb3ca
EC		 2300 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2301 }
fa417f7b
EC		 2302 } else {
2303 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
2304 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2305 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2306 }
225c7b1f
RD		 2307 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2308 if (!sqp->qp.ibqp.qp_num)
2309 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2310 else
2311 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
2312 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2313 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2314 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2315 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
2316 sqp->qkey : wr->wr.ud.remote_qkey);
2317 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2318
2319 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2320
2321 if (0) {
987c8f8f 2322 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 2323 for (i = 0; i < header_size / 4; ++i) {
2324 if (i % 8 == 0)
987c8f8f
SP		 2325 pr_err(" [%02x] ", i * 4);
2326 pr_cont(" %08x",
2327 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 2328 if ((i + 1) % 8 == 0)
987c8f8f 2329 pr_cont("\n");
225c7b1f 2330 }
987c8f8f 2331 pr_err("\n");
225c7b1f
RD		 2332 }
2333
e61ef241
RD		 2334 /*
2335 * Inline data segments may not cross a 64 byte boundary. If
2336 * our UD header is bigger than the space available up to the
2337 * next 64 byte boundary in the WQE, use two inline data
2338 * segments to hold the UD header.
2339 */
2340 spc = MLX4_INLINE_ALIGN -
2341 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2342 if (header_size <= spc) {
2343 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2344 memcpy(inl + 1, sqp->header_buf, header_size);
2345 i = 1;
2346 } else {
2347 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2348 memcpy(inl + 1, sqp->header_buf, spc);
2349
2350 inl = (void *) (inl + 1) + spc;
2351 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2352 /*
2353 * Need a barrier here to make sure all the data is
2354 * visible before the byte_count field is set.
2355 * Otherwise the HCA prefetcher could grab the 64-byte
2356 * chunk with this inline segment and get a valid (!=
2357 * 0xffffffff) byte count but stale data, and end up
2358 * generating a packet with bad headers.
2359 *
2360 * The first inline segment's byte_count field doesn't
2361 * need a barrier, because it comes after a
2362 * control/MLX segment and therefore is at an offset
2363 * of 16 mod 64.
2364 */
2365 wmb();
2366 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2367 i = 2;
2368 }
225c7b1f 2369
f438000f
RD		 2370 *mlx_seg_len =
2371 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2372 return 0;
225c7b1f
RD		 2373}
2374
2375static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2376{
2377 unsigned cur;
2378 struct mlx4_ib_cq *cq;
2379
2380 cur = wq->head - wq->tail;
0e6e7416 2381 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 2382 return 0;
2383
2384 cq = to_mcq(ib_cq);
2385 spin_lock(&cq->lock);
2386 cur = wq->head - wq->tail;
2387 spin_unlock(&cq->lock);
2388
0e6e7416 2389 return cur + nreq >= wq->max_post;
225c7b1f
RD		 2390}
2391
95d04f07
RD		 2392static __be32 convert_access(int acc)
2393{
6ff63e19
SM		 2394 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2395 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2396 (acc & IB_ACCESS_REMOTE_WRITE ?
2397 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2398 (acc & IB_ACCESS_REMOTE_READ ?
2399 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 2400 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2401 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2402}
2403
2404static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
2405{
2406 struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
29bdc883
VS		 2407 int i;
2408
2409 for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2b6b7d4b 2410 mfrpl->mapped_page_list[i] =
29bdc883
VS		 2411 cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
2412 MLX4_MTT_FLAG_PRESENT);
95d04f07
RD		 2413
2414 fseg->flags = convert_access(wr->wr.fast_reg.access_flags);
2415 fseg->mem_key = cpu_to_be32(wr->wr.fast_reg.rkey);
2416 fseg->buf_list = cpu_to_be64(mfrpl->map);
2417 fseg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
2418 fseg->reg_len = cpu_to_be64(wr->wr.fast_reg.length);
2419 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2420 fseg->page_size = cpu_to_be32(wr->wr.fast_reg.page_shift);
2421 fseg->reserved[0] = 0;
2422 fseg->reserved[1] = 0;
2423}
2424
6ff63e19
SM		 2425static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr)
2426{
2427 bseg->flags1 =
2428 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) &
2429 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ |
2430 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2431 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2432 bseg->flags2 = 0;
2433 if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2)
2434 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2435 if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED)
2436 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2437 bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey);
2438 bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey);
2439 bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr);
2440 bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length);
2441}
2442
95d04f07
RD		 2443static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2444{
aee38fad
SM		 2445 memset(iseg, 0, sizeof(*iseg));
2446 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 2447}
2448
0fbfa6a9
RD		 2449static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2450 u64 remote_addr, u32 rkey)
2451{
2452 rseg->raddr = cpu_to_be64(remote_addr);
2453 rseg->rkey = cpu_to_be32(rkey);
2454 rseg->reserved = 0;
2455}
2456
2457static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2458{
2459 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2460 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2461 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
6fa8f719
VS		 2462 } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2463 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2464 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add_mask);
0fbfa6a9
RD		 2465 } else {
2466 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2467 aseg->compare = 0;
2468 }
2469
2470}
2471
6fa8f719
VS		 2472static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2473 struct ib_send_wr *wr)
2474{
2475 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2476 aseg->swap_add_mask = cpu_to_be64(wr->wr.atomic.swap_mask);
2477 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
2478 aseg->compare_mask = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2479}
2480
0fbfa6a9 2481static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
80a2dcd8 2482 struct ib_send_wr *wr)
0fbfa6a9
RD		 2483{
2484 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2485 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2486 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
fa417f7b
EC		 2487 dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2488 memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
0fbfa6a9
RD		 2489}
2490
1ffeb2eb
JM		 2491static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2492 struct mlx4_wqe_datagram_seg *dseg,
97982f5a
JM		 2493 struct ib_send_wr *wr,
2494 enum mlx4_ib_qp_type qpt)
1ffeb2eb
JM		 2495{
2496 union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2497 struct mlx4_av sqp_av = {0};
2498 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2499
2500 /* force loopback */
2501 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2502 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2503 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2504 cpu_to_be32(0xf0000000);
2505
2506 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a
JM		 2507 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2508 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2509 else
2510 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
47605df9
JM		 2511 /* Use QKEY from the QP context, which is set by master */
2512 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 2513}
2514
2515static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2516{
2517 struct mlx4_wqe_inline_seg *inl = wqe;
2518 struct mlx4_ib_tunnel_header hdr;
2519 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2520 int spc;
2521 int i;
2522
2523 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2524 hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2525 hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2526 hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
5ea8bbfc
JM		 2527 memcpy(hdr.mac, ah->av.eth.mac, 6);
2528 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 2529
2530 spc = MLX4_INLINE_ALIGN -
2531 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2532 if (sizeof (hdr) <= spc) {
2533 memcpy(inl + 1, &hdr, sizeof (hdr));
2534 wmb();
2535 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2536 i = 1;
2537 } else {
2538 memcpy(inl + 1, &hdr, spc);
2539 wmb();
2540 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2541
2542 inl = (void *) (inl + 1) + spc;
2543 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2544 wmb();
2545 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2546 i = 2;
2547 }
2548
2549 *mlx_seg_len =
2550 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2551}
2552
6e694ea3
JM		 2553static void set_mlx_icrc_seg(void *dseg)
2554{
2555 u32 *t = dseg;
2556 struct mlx4_wqe_inline_seg *iseg = dseg;
2557
2558 t[1] = 0;
2559
2560 /*
2561 * Need a barrier here before writing the byte_count field to
2562 * make sure that all the data is visible before the
2563 * byte_count field is set. Otherwise, if the segment begins
2564 * a new cacheline, the HCA prefetcher could grab the 64-byte
2565 * chunk and get a valid (!= * 0xffffffff) byte count but
2566 * stale data, and end up sending the wrong data.
2567 */
2568 wmb();
2569
2570 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2571}
2572
2573static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 2574{
d420d9e3
RD		 2575 dseg->lkey = cpu_to_be32(sg->lkey);
2576 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 2577
2578 /*
2579 * Need a barrier here before writing the byte_count field to
2580 * make sure that all the data is visible before the
2581 * byte_count field is set. Otherwise, if the segment begins
2582 * a new cacheline, the HCA prefetcher could grab the 64-byte
2583 * chunk and get a valid (!= * 0xffffffff) byte count but
2584 * stale data, and end up sending the wrong data.
2585 */
2586 wmb();
2587
2588 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 2589}
2590
2242fa4f
RD		 2591static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2592{
2593 dseg->byte_count = cpu_to_be32(sg->length);
2594 dseg->lkey = cpu_to_be32(sg->lkey);
2595 dseg->addr = cpu_to_be64(sg->addr);
2596}
2597
47b37475 2598static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
0fd7e1d8 2599 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 2600 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e
EC		 2601{
2602 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2603
417608c2
EC		 2604 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2605 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 2606
2607 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2608 wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2609 return -EINVAL;
2610
2611 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2612
ca9b590c 2613 *lso_hdr_sz = cpu_to_be32(wr->wr.ud.mss << 16 | wr->wr.ud.hlen);
b832be1e
EC		 2614 *lso_seg_len = halign;
2615 return 0;
2616}
2617
95d04f07
RD		 2618static __be32 send_ieth(struct ib_send_wr *wr)
2619{
2620 switch (wr->opcode) {
2621 case IB_WR_SEND_WITH_IMM:
2622 case IB_WR_RDMA_WRITE_WITH_IMM:
2623 return wr->ex.imm_data;
2624
2625 case IB_WR_SEND_WITH_INV:
2626 return cpu_to_be32(wr->ex.invalidate_rkey);
2627
2628 default:
2629 return 0;
2630 }
2631}
2632
1ffeb2eb
JM		 2633static void add_zero_len_inline(void *wqe)
2634{
2635 struct mlx4_wqe_inline_seg *inl = wqe;
2636 memset(wqe, 0, 16);
2637 inl->byte_count = cpu_to_be32(1 << 31);
2638}
2639
225c7b1f
RD		 2640int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2641 struct ib_send_wr **bad_wr)
2642{
2643 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2644 void *wqe;
2645 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 2646 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 2647 unsigned long flags;
2648 int nreq;
2649 int err = 0;
ea54b10c
JM		 2650 unsigned ind;
2651 int uninitialized_var(stamp);
2652 int uninitialized_var(size);
a3d8e159 2653 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 2654 __be32 dummy;
2655 __be32 *lso_wqe;
2656 __be32 uninitialized_var(lso_hdr_sz);
417608c2 2657 __be32 blh;
225c7b1f 2658 int i;
35f05dab 2659 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 2660
96db0e03 2661 spin_lock_irqsave(&qp->sq.lock, flags);
35f05dab
YH		 2662 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2663 err = -EIO;
2664 *bad_wr = wr;
2665 nreq = 0;
2666 goto out;
2667 }
225c7b1f 2668
ea54b10c 2669 ind = qp->sq_next_wqe;
225c7b1f
RD		 2670
2671 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 2672 lso_wqe = &dummy;
417608c2 2673 blh = 0;
0fd7e1d8 2674
225c7b1f
RD		 2675 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2676 err = -ENOMEM;
2677 *bad_wr = wr;
2678 goto out;
2679 }
2680
2681 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2682 err = -EINVAL;
2683 *bad_wr = wr;
2684 goto out;
2685 }
2686
0e6e7416 2687 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 2688 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 2689
2690 ctrl->srcrb_flags =
2691 (wr->send_flags & IB_SEND_SIGNALED ?
2692 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2693 (wr->send_flags & IB_SEND_SOLICITED ?
2694 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 2695 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2696 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2697 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 2698 qp->sq_signal_bits;
2699
95d04f07 2700 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 2701
2702 wqe += sizeof *ctrl;
2703 size = sizeof *ctrl / 16;
2704
1ffeb2eb
JM		 2705 switch (qp->mlx4_ib_qp_type) {
2706 case MLX4_IB_QPT_RC:
2707 case MLX4_IB_QPT_UC:
225c7b1f
RD		 2708 switch (wr->opcode) {
2709 case IB_WR_ATOMIC_CMP_AND_SWP:
2710 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 2711 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
0fbfa6a9
RD		 2712 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2713 wr->wr.atomic.rkey);
225c7b1f
RD		 2714 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2715
0fbfa6a9 2716 set_atomic_seg(wqe, wr);
225c7b1f 2717 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 2718
225c7b1f
RD		 2719 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2720 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 2721
2722 break;
2723
2724 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2725 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2726 wr->wr.atomic.rkey);
2727 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2728
2729 set_masked_atomic_seg(wqe, wr);
2730 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
2731
2732 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2733 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 2734
2735 break;
2736
2737 case IB_WR_RDMA_READ:
2738 case IB_WR_RDMA_WRITE:
2739 case IB_WR_RDMA_WRITE_WITH_IMM:
0fbfa6a9
RD		 2740 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2741 wr->wr.rdma.rkey);
225c7b1f
RD		 2742 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2743 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 2744 break;
95d04f07
RD		 2745
2746 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 2747 ctrl->srcrb_flags |=
2748 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2749 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2750 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
2751 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2752 break;
2753
2754 case IB_WR_FAST_REG_MR:
2ac6bf4d
JM		 2755 ctrl->srcrb_flags |=
2756 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2757 set_fmr_seg(wqe, wr);
2758 wqe += sizeof (struct mlx4_wqe_fmr_seg);
2759 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2760 break;
225c7b1f 2761
6ff63e19
SM		 2762 case IB_WR_BIND_MW:
2763 ctrl->srcrb_flags |=
2764 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2765 set_bind_seg(wqe, wr);
2766 wqe += sizeof(struct mlx4_wqe_bind_seg);
2767 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2768 break;
225c7b1f
RD		 2769 default:
2770 /* No extra segments required for sends */
2771 break;
2772 }
2773 break;
2774
1ffeb2eb
JM		 2775 case MLX4_IB_QPT_TUN_SMI_OWNER:
2776 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2777 if (unlikely(err)) {
2778 *bad_wr = wr;
2779 goto out;
2780 }
2781 wqe += seglen;
2782 size += seglen / 16;
2783 break;
2784 case MLX4_IB_QPT_TUN_SMI:
2785 case MLX4_IB_QPT_TUN_GSI:
2786 /* this is a UD qp used in MAD responses to slaves. */
2787 set_datagram_seg(wqe, wr);
2788 /* set the forced-loopback bit in the data seg av */
2789 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2790 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2791 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2792 break;
2793 case MLX4_IB_QPT_UD:
80a2dcd8 2794 set_datagram_seg(wqe, wr);
225c7b1f
RD		 2795 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2796 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 2797
2798 if (wr->opcode == IB_WR_LSO) {
417608c2 2799 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
b832be1e
EC		 2800 if (unlikely(err)) {
2801 *bad_wr = wr;
2802 goto out;
2803 }
0fd7e1d8 2804 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 2805 wqe += seglen;
2806 size += seglen / 16;
2807 }
225c7b1f
RD		 2808 break;
2809
1ffeb2eb 2810 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1ffeb2eb
JM		 2811 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2812 if (unlikely(err)) {
2813 *bad_wr = wr;
2814 goto out;
2815 }
2816 wqe += seglen;
2817 size += seglen / 16;
2818 /* to start tunnel header on a cache-line boundary */
2819 add_zero_len_inline(wqe);
2820 wqe += 16;
2821 size++;
2822 build_tunnel_header(wr, wqe, &seglen);
2823 wqe += seglen;
2824 size += seglen / 16;
2825 break;
2826 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 2827 case MLX4_IB_QPT_PROXY_GSI:
2828 /* If we are tunneling special qps, this is a UD qp.
2829 * In this case we first add a UD segment targeting
2830 * the tunnel qp, and then add a header with address
2831 * information */
97982f5a
JM		 2832 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr,
2833 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 2834 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2835 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2836 build_tunnel_header(wr, wqe, &seglen);
2837 wqe += seglen;
2838 size += seglen / 16;
2839 break;
2840
2841 case MLX4_IB_QPT_SMI:
2842 case MLX4_IB_QPT_GSI:
f438000f
RD		 2843 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2844 if (unlikely(err)) {
225c7b1f
RD		 2845 *bad_wr = wr;
2846 goto out;
2847 }
f438000f
RD		 2848 wqe += seglen;
2849 size += seglen / 16;
225c7b1f
RD		 2850 break;
2851
2852 default:
2853 break;
2854 }
2855
6e694ea3
JM		 2856 /*
2857 * Write data segments in reverse order, so as to
2858 * overwrite cacheline stamp last within each
2859 * cacheline. This avoids issues with WQE
2860 * prefetching.
2861 */
225c7b1f 2862
6e694ea3
JM		 2863 dseg = wqe;
2864 dseg += wr->num_sge - 1;
2865 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 2866
2867 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 2868 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2869 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2870 qp->mlx4_ib_qp_type &
2871 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 2872 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 2873 size += sizeof (struct mlx4_wqe_data_seg) / 16;
2874 }
2875
6e694ea3
JM		 2876 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2877 set_data_seg(dseg, wr->sg_list + i);
2878
0fd7e1d8
RD		 2879 /*
2880 * Possibly overwrite stamping in cacheline with LSO
2881 * segment only after making sure all data segments
2882 * are written.
2883 */
2884 wmb();
2885 *lso_wqe = lso_hdr_sz;
2886
225c7b1f
RD		 2887 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2888 MLX4_WQE_CTRL_FENCE : 0) | size;
2889
2890 /*
2891 * Make sure descriptor is fully written before
2892 * setting ownership bit (because HW can start
2893 * executing as soon as we do).
2894 */
2895 wmb();
2896
59b0ed12 2897 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 2898 *bad_wr = wr;
225c7b1f
RD		 2899 err = -EINVAL;
2900 goto out;
2901 }
2902
2903 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 2904 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 2905
ea54b10c
JM		 2906 stamp = ind + qp->sq_spare_wqes;
2907 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2908
0e6e7416
RD		 2909 /*
2910 * We can improve latency by not stamping the last
2911 * send queue WQE until after ringing the doorbell, so
2912 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 2913 *
2914 * Same optimization applies to padding with NOP wqe
2915 * in case of WQE shrinking (used to prevent wrap-around
2916 * in the middle of WR).
0e6e7416 2917 */
ea54b10c
JM		 2918 if (wr->next) {
2919 stamp_send_wqe(qp, stamp, size * 16);
2920 ind = pad_wraparound(qp, ind);
2921 }
225c7b1f
RD		 2922 }
2923
2924out:
2925 if (likely(nreq)) {
2926 qp->sq.head += nreq;
2927
2928 /*
2929 * Make sure that descriptors are written before
2930 * doorbell record.
2931 */
2932 wmb();
2933
2934 writel(qp->doorbell_qpn,
2935 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
2936
2937 /*
2938 * Make sure doorbells don't leak out of SQ spinlock
2939 * and reach the HCA out of order.
2940 */
2941 mmiowb();
0e6e7416 2942
ea54b10c
JM		 2943 stamp_send_wqe(qp, stamp, size * 16);
2944
2945 ind = pad_wraparound(qp, ind);
2946 qp->sq_next_wqe = ind;
225c7b1f
RD		 2947 }
2948
96db0e03 2949 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 2950
2951 return err;
2952}
2953
2954int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2955 struct ib_recv_wr **bad_wr)
2956{
2957 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2958 struct mlx4_wqe_data_seg *scat;
2959 unsigned long flags;
2960 int err = 0;
2961 int nreq;
2962 int ind;
1ffeb2eb 2963 int max_gs;
225c7b1f 2964 int i;
35f05dab 2965 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 2966
1ffeb2eb 2967 max_gs = qp->rq.max_gs;
225c7b1f
RD		 2968 spin_lock_irqsave(&qp->rq.lock, flags);
2969
35f05dab
YH		 2970 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2971 err = -EIO;
2972 *bad_wr = wr;
2973 nreq = 0;
2974 goto out;
2975 }
2976
0e6e7416 2977 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 2978
2979 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 2980 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 2981 err = -ENOMEM;
2982 *bad_wr = wr;
2983 goto out;
2984 }
2985
2986 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2987 err = -EINVAL;
2988 *bad_wr = wr;
2989 goto out;
2990 }
2991
2992 scat = get_recv_wqe(qp, ind);
2993
1ffeb2eb
JM		 2994 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
2995 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
2996 ib_dma_sync_single_for_device(ibqp->device,
2997 qp->sqp_proxy_rcv[ind].map,
2998 sizeof (struct mlx4_ib_proxy_sqp_hdr),
2999 DMA_FROM_DEVICE);
3000 scat->byte_count =
3001 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3002 /* use dma lkey from upper layer entry */
3003 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3004 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3005 scat++;
3006 max_gs--;
3007 }
3008
2242fa4f
RD		 3009 for (i = 0; i < wr->num_sge; ++i)
3010 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3011
1ffeb2eb 3012 if (i < max_gs) {
225c7b1f
RD		 3013 scat[i].byte_count = 0;
3014 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3015 scat[i].addr = 0;
3016 }
3017
3018 qp->rq.wrid[ind] = wr->wr_id;
3019
0e6e7416 3020 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3021 }
3022
3023out:
3024 if (likely(nreq)) {
3025 qp->rq.head += nreq;
3026
3027 /*
3028 * Make sure that descriptors are written before
3029 * doorbell record.
3030 */
3031 wmb();
3032
3033 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3034 }
3035
3036 spin_unlock_irqrestore(&qp->rq.lock, flags);
3037
3038 return err;
3039}
6a775e2b
JM		 3040
3041static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3042{
3043 switch (mlx4_state) {
3044 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3045 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3046 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3047 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3048 case MLX4_QP_STATE_SQ_DRAINING:
3049 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3050 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3051 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3052 default: return -1;
3053 }
3054}
3055
3056static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3057{
3058 switch (mlx4_mig_state) {
3059 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3060 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3061 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3062 default: return -1;
3063 }
3064}
3065
3066static int to_ib_qp_access_flags(int mlx4_flags)
3067{
3068 int ib_flags = 0;
3069
3070 if (mlx4_flags & MLX4_QP_BIT_RRE)
3071 ib_flags |= IB_ACCESS_REMOTE_READ;
3072 if (mlx4_flags & MLX4_QP_BIT_RWE)
3073 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3074 if (mlx4_flags & MLX4_QP_BIT_RAE)
3075 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3076
3077 return ib_flags;
3078}
3079
4c3eb3ca 3080static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
6a775e2b
JM		 3081 struct mlx4_qp_path *path)
3082{
4c3eb3ca
EC		 3083 struct mlx4_dev *dev = ibdev->dev;
3084 int is_eth;
3085
8fcea95a 3086 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 3087 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
3088
3089 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3090 return;
3091
4c3eb3ca
EC		 3092 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3093 IB_LINK_LAYER_ETHERNET;
3094 if (is_eth)
3095 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3096 ((path->sched_queue & 4) << 1);
3097 else
3098 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3099
6a775e2b 3100 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
6a775e2b
JM		 3101 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3102 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3103 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3104 if (ib_ah_attr->ah_flags) {
3105 ib_ah_attr->grh.sgid_index = path->mgid_index;
3106 ib_ah_attr->grh.hop_limit = path->hop_limit;
3107 ib_ah_attr->grh.traffic_class =
3108 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3109 ib_ah_attr->grh.flow_label =
586bb586 3110 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 3111 memcpy(ib_ah_attr->grh.dgid.raw,
3112 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3113 }
3114}
3115
3116int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3117 struct ib_qp_init_attr *qp_init_attr)
3118{
3119 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3120 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3121 struct mlx4_qp_context context;
3122 int mlx4_state;
0df67030
DB		 3123 int err = 0;
3124
3125 mutex_lock(&qp->mutex);
6a775e2b
JM		 3126
3127 if (qp->state == IB_QPS_RESET) {
3128 qp_attr->qp_state = IB_QPS_RESET;
3129 goto done;
3130 }
3131
3132 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3133 if (err) {
3134 err = -EINVAL;
3135 goto out;
3136 }
6a775e2b
JM		 3137
3138 mlx4_state = be32_to_cpu(context.flags) >> 28;
3139
0df67030
DB		 3140 qp->state = to_ib_qp_state(mlx4_state);
3141 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3142 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3143 qp_attr->path_mig_state =
3144 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3145 qp_attr->qkey = be32_to_cpu(context.qkey);
3146 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3147 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3148 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3149 qp_attr->qp_access_flags =
3150 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3151
3152 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4c3eb3ca
EC		 3153 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3154 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b
JM		 3155 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3156 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3157 }
3158
3159 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 3160 if (qp_attr->qp_state == IB_QPS_INIT)
3161 qp_attr->port_num = qp->port;
3162 else
3163 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 3164
3165 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3166 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3167
3168 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3169
3170 qp_attr->max_dest_rd_atomic =
3171 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3172 qp_attr->min_rnr_timer =
3173 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3174 qp_attr->timeout = context.pri_path.ackto >> 3;
3175 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3176 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3177 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3178
3179done:
3180 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 3181 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3182 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3183
6a775e2b 3184 if (!ibqp->uobject) {
7f5eb9bb
RD		 3185 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3186 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3187 } else {
3188 qp_attr->cap.max_send_wr = 0;
3189 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 3190 }
3191
7f5eb9bb
RD		 3192 /*
3193 * We don't support inline sends for kernel QPs (yet), and we
3194 * don't know what userspace's value should be.
3195 */
3196 qp_attr->cap.max_inline_data = 0;
3197
3198 qp_init_attr->cap = qp_attr->cap;
3199
521e575b
RL		 3200 qp_init_attr->create_flags = 0;
3201 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3202 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3203
3204 if (qp->flags & MLX4_IB_QP_LSO)
3205 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3206
c1c98501
MB		 3207 if (qp->flags & MLX4_IB_QP_NETIF)
3208 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3209
46db567d
DB		 3210 qp_init_attr->sq_sig_type =
3211 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3212 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3213
0df67030
DB		 3214out:
3215 mutex_unlock(&qp->mutex);
3216 return err;
6a775e2b
JM		 3217}
3218
Linux 6.x block layer and io_uring tree(s)