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IB/mlx5: Advertise atomic capabilities in query device
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
5a0e3ad6 35#include <linux/slab.h>
fa417f7b 36#include <linux/netdevice.h>
0ef2f05c 37#include <linux/vmalloc.h>
ea54b10c 38
225c7b1f
RD		 39#include <rdma/ib_cache.h>
40#include <rdma/ib_pack.h>
4c3eb3ca 41#include <rdma/ib_addr.h>
1ffeb2eb 42#include <rdma/ib_mad.h>
225c7b1f 43
2f48485d 44#include <linux/mlx4/driver.h>
225c7b1f
RD		 45#include <linux/mlx4/qp.h>
46
47#include "mlx4_ib.h"
48#include "user.h"
49
35f05dab
YH		 50static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
51 struct mlx4_ib_cq *recv_cq);
52static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
53 struct mlx4_ib_cq *recv_cq);
54
225c7b1f
RD		 55enum {
56 MLX4_IB_ACK_REQ_FREQ = 8,
57};
58
59enum {
60 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 61 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
62 MLX4_IB_LINK_TYPE_IB = 0,
63 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 64};
65
66enum {
67 /*
fa417f7b 68 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 69 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
70 * tag. (LRH would only use 8 bytes, so Ethernet is the
71 * biggest case)
225c7b1f 72 */
4c3eb3ca 73 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 74 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 75};
76
fa417f7b
EC		 77enum {
78 MLX4_IB_IBOE_ETHERTYPE = 0x8915
79};
80
225c7b1f
RD		 81struct mlx4_ib_sqp {
82 struct mlx4_ib_qp qp;
83 int pkey_index;
84 u32 qkey;
85 u32 send_psn;
86 struct ib_ud_header ud_header;
87 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
88};
89
83904132 90enum {
417608c2
EC		 91 MLX4_IB_MIN_SQ_STRIDE = 6,
92 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 93};
94
3987a2d3
OG		 95enum {
96 MLX4_RAW_QP_MTU = 7,
97 MLX4_RAW_QP_MSGMAX = 31,
98};
99
297e0dad
MS		 100#ifndef ETH_ALEN
101#define ETH_ALEN 6
102#endif
297e0dad 103
225c7b1f 104static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 105 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
106 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
107 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
108 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
109 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
110 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
111 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
112 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
113 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
114 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 115 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 116 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
117 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 118};
119
120static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
121{
122 return container_of(mqp, struct mlx4_ib_sqp, qp);
123}
124
1ffeb2eb
JM		 125static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
126{
127 if (!mlx4_is_master(dev->dev))
128 return 0;
129
47605df9
JM		 130 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
131 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
132 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 133}
134
225c7b1f
RD		 135static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
136{
47605df9
JM		 137 int proxy_sqp = 0;
138 int real_sqp = 0;
139 int i;
140 /* PPF or Native -- real SQP */
141 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
142 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
143 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
144 if (real_sqp)
145 return 1;
146 /* VF or PF -- proxy SQP */
147 if (mlx4_is_mfunc(dev->dev)) {
148 for (i = 0; i < dev->dev->caps.num_ports; i++) {
149 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
150 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
151 proxy_sqp = 1;
152 break;
153 }
154 }
155 }
156 return proxy_sqp;
225c7b1f
RD		 157}
158
1ffeb2eb 159/* used for INIT/CLOSE port logic */
225c7b1f
RD		 160static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
161{
47605df9
JM		 162 int proxy_qp0 = 0;
163 int real_qp0 = 0;
164 int i;
165 /* PPF or Native -- real QP0 */
166 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
167 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
168 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
169 if (real_qp0)
170 return 1;
171 /* VF or PF -- proxy QP0 */
172 if (mlx4_is_mfunc(dev->dev)) {
173 for (i = 0; i < dev->dev->caps.num_ports; i++) {
174 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
175 proxy_qp0 = 1;
176 break;
177 }
178 }
179 }
180 return proxy_qp0;
225c7b1f
RD		 181}
182
183static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
184{
1c69fc2a 185 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 186}
187
188static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
189{
190 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
191}
192
193static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
194{
195 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
196}
197
0e6e7416
RD		 198/*
199 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 200 * first four bytes of every 64 byte chunk with
201 * 0x7FFFFFF | (invalid_ownership_value << 31).
202 *
203 * When the max work request size is less than or equal to the WQE
204 * basic block size, as an optimization, we can stamp all WQEs with
205 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 206 */
ea54b10c 207static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 208{
d2ae16d5 209 __be32 *wqe;
0e6e7416 210 int i;
ea54b10c
JM		 211 int s;
212 int ind;
213 void *buf;
214 __be32 stamp;
9670e553 215 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 216
ea54b10c 217 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 218 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 219 for (i = 0; i < s; i += 64) {
220 ind = (i >> qp->sq.wqe_shift) + n;
221 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
222 cpu_to_be32(0xffffffff);
223 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
224 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
225 *wqe = stamp;
226 }
227 } else {
9670e553
EC		 228 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
229 s = (ctrl->fence_size & 0x3f) << 4;
ea54b10c
JM		 230 for (i = 64; i < s; i += 64) {
231 wqe = buf + i;
d2ae16d5 232 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 233 }
234 }
235}
236
237static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
238{
239 struct mlx4_wqe_ctrl_seg *ctrl;
240 struct mlx4_wqe_inline_seg *inl;
241 void *wqe;
242 int s;
243
244 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
245 s = sizeof(struct mlx4_wqe_ctrl_seg);
246
247 if (qp->ibqp.qp_type == IB_QPT_UD) {
248 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
249 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
250 memset(dgram, 0, sizeof *dgram);
251 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
252 s += sizeof(struct mlx4_wqe_datagram_seg);
253 }
254
255 /* Pad the remainder of the WQE with an inline data segment. */
256 if (size > s) {
257 inl = wqe + s;
258 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
259 }
260 ctrl->srcrb_flags = 0;
261 ctrl->fence_size = size / 16;
262 /*
263 * Make sure descriptor is fully written before setting ownership bit
264 * (because HW can start executing as soon as we do).
265 */
266 wmb();
267
268 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
269 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 270
ea54b10c
JM		 271 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
272}
273
274/* Post NOP WQE to prevent wrap-around in the middle of WR */
275static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
276{
277 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
278 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
279 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
280 ind += s;
281 }
282 return ind;
0e6e7416
RD		 283}
284
225c7b1f
RD		 285static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
286{
287 struct ib_event event;
288 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
289
290 if (type == MLX4_EVENT_TYPE_PATH_MIG)
291 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
292
293 if (ibqp->event_handler) {
294 event.device = ibqp->device;
295 event.element.qp = ibqp;
296 switch (type) {
297 case MLX4_EVENT_TYPE_PATH_MIG:
298 event.event = IB_EVENT_PATH_MIG;
299 break;
300 case MLX4_EVENT_TYPE_COMM_EST:
301 event.event = IB_EVENT_COMM_EST;
302 break;
303 case MLX4_EVENT_TYPE_SQ_DRAINED:
304 event.event = IB_EVENT_SQ_DRAINED;
305 break;
306 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
307 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
308 break;
309 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
310 event.event = IB_EVENT_QP_FATAL;
311 break;
312 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
313 event.event = IB_EVENT_PATH_MIG_ERR;
314 break;
315 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
316 event.event = IB_EVENT_QP_REQ_ERR;
317 break;
318 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
319 event.event = IB_EVENT_QP_ACCESS_ERR;
320 break;
321 default:
987c8f8f 322 pr_warn("Unexpected event type %d "
225c7b1f
RD		 323 "on QP %06x\n", type, qp->qpn);
324 return;
325 }
326
327 ibqp->event_handler(&event, ibqp->qp_context);
328 }
329}
330
1ffeb2eb 331static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 332{
333 /*
334 * UD WQEs must have a datagram segment.
335 * RC and UC WQEs might have a remote address segment.
336 * MLX WQEs need two extra inline data segments (for the UD
337 * header and space for the ICRC).
338 */
339 switch (type) {
1ffeb2eb 340 case MLX4_IB_QPT_UD:
225c7b1f 341 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 342 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 343 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 344 case MLX4_IB_QPT_PROXY_SMI_OWNER:
345 case MLX4_IB_QPT_PROXY_SMI:
346 case MLX4_IB_QPT_PROXY_GSI:
347 return sizeof (struct mlx4_wqe_ctrl_seg) +
348 sizeof (struct mlx4_wqe_datagram_seg) + 64;
349 case MLX4_IB_QPT_TUN_SMI_OWNER:
350 case MLX4_IB_QPT_TUN_GSI:
351 return sizeof (struct mlx4_wqe_ctrl_seg) +
352 sizeof (struct mlx4_wqe_datagram_seg);
353
354 case MLX4_IB_QPT_UC:
225c7b1f
RD		 355 return sizeof (struct mlx4_wqe_ctrl_seg) +
356 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 357 case MLX4_IB_QPT_RC:
225c7b1f
RD		 358 return sizeof (struct mlx4_wqe_ctrl_seg) +
359 sizeof (struct mlx4_wqe_atomic_seg) +
360 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 361 case MLX4_IB_QPT_SMI:
362 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 363 return sizeof (struct mlx4_wqe_ctrl_seg) +
364 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 365 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
366 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 367 sizeof (struct mlx4_wqe_inline_seg),
368 sizeof (struct mlx4_wqe_data_seg)) +
369 ALIGN(4 +
370 sizeof (struct mlx4_wqe_inline_seg),
371 sizeof (struct mlx4_wqe_data_seg));
372 default:
373 return sizeof (struct mlx4_wqe_ctrl_seg);
374 }
375}
376
2446304d 377static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
0a1405da 378 int is_user, int has_rq, struct mlx4_ib_qp *qp)
225c7b1f 379{
2446304d 380 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 381 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
382 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 383 return -EINVAL;
384
0a1405da 385 if (!has_rq) {
a4cd7ed8
RD		 386 if (cap->max_recv_wr)
387 return -EINVAL;
2446304d 388
0e6e7416 389 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 390 } else {
391 /* HW requires >= 1 RQ entry with >= 1 gather entry */
392 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
393 return -EINVAL;
394
0e6e7416 395 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 396 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 397 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
398 }
2446304d 399
fc2d0044
SG		 400 /* leave userspace return values as they were, so as not to break ABI */
401 if (is_user) {
402 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
403 cap->max_recv_sge = qp->rq.max_gs;
404 } else {
405 cap->max_recv_wr = qp->rq.max_post =
406 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
407 cap->max_recv_sge = min(qp->rq.max_gs,
408 min(dev->dev->caps.max_sq_sg,
409 dev->dev->caps.max_rq_sg));
410 }
2446304d
EC		 411
412 return 0;
413}
414
415static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
1ffeb2eb 416 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 417{
ea54b10c
JM		 418 int s;
419
2446304d 420 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 421 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
422 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 423 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 424 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
425 return -EINVAL;
426
427 /*
428 * For MLX transport we need 2 extra S/G entries:
429 * one for the header and one for the checksum at the end
430 */
1ffeb2eb
JM		 431 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
432 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 433 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
434 return -EINVAL;
435
ea54b10c
JM		 436 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
437 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 438 send_wqe_overhead(type, qp->flags);
225c7b1f 439
cd155c1c
RD		 440 if (s > dev->dev->caps.max_sq_desc_sz)
441 return -EINVAL;
442
0e6e7416 443 /*
ea54b10c
JM		 444 * Hermon supports shrinking WQEs, such that a single work
445 * request can include multiple units of 1 << wqe_shift. This
446 * way, work requests can differ in size, and do not have to
447 * be a power of 2 in size, saving memory and speeding up send
448 * WR posting. Unfortunately, if we do this then the
449 * wqe_index field in CQEs can't be used to look up the WR ID
450 * anymore, so we do this only if selective signaling is off.
451 *
452 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 453 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 454 * constant-sized WRs to make sure a WR is always fully within
455 * a single page-sized chunk.
456 *
457 * Finally, we use NOP work requests to pad the end of the
458 * work queue, to avoid wrap-around in the middle of WR. We
459 * set NEC bit to avoid getting completions with error for
460 * these NOP WRs, but since NEC is only supported starting
461 * with firmware 2.2.232, we use constant-sized WRs for older
462 * firmware.
463 *
464 * And, since MLX QPs only support SEND, we use constant-sized
465 * WRs in this case.
466 *
467 * We look for the smallest value of wqe_shift such that the
468 * resulting number of wqes does not exceed device
469 * capabilities.
470 *
471 * We set WQE size to at least 64 bytes, this way stamping
472 * invalidates each WQE.
0e6e7416 473 */
ea54b10c
JM		 474 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
475 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 476 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
477 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
478 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 479 qp->sq.wqe_shift = ilog2(64);
480 else
481 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
482
483 for (;;) {
ea54b10c
JM		 484 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
485
486 /*
487 * We need to leave 2 KB + 1 WR of headroom in the SQ to
488 * allow HW to prefetch.
489 */
490 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
491 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
492 qp->sq_max_wqes_per_wr +
493 qp->sq_spare_wqes);
494
495 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
496 break;
497
498 if (qp->sq_max_wqes_per_wr <= 1)
499 return -EINVAL;
500
501 ++qp->sq.wqe_shift;
502 }
503
cd155c1c
RD		 504 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
505 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 506 send_wqe_overhead(type, qp->flags)) /
507 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 508
509 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
510 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 511 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
512 qp->rq.offset = 0;
0e6e7416 513 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 514 } else {
0e6e7416 515 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 516 qp->sq.offset = 0;
517 }
518
ea54b10c
JM		 519 cap->max_send_wr = qp->sq.max_post =
520 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 521 cap->max_send_sge = min(qp->sq.max_gs,
522 min(dev->dev->caps.max_sq_sg,
523 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 524 /* We don't support inline sends for kernel QPs (yet) */
525 cap->max_inline_data = 0;
225c7b1f
RD		 526
527 return 0;
528}
529
83904132
JM		 530static int set_user_sq_size(struct mlx4_ib_dev *dev,
531 struct mlx4_ib_qp *qp,
2446304d
EC		 532 struct mlx4_ib_create_qp *ucmd)
533{
83904132
JM		 534 /* Sanity check SQ size before proceeding */
535 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
536 ucmd->log_sq_stride >
537 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
538 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
539 return -EINVAL;
540
0e6e7416 541 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 542 qp->sq.wqe_shift = ucmd->log_sq_stride;
543
0e6e7416
RD		 544 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
545 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 546
547 return 0;
548}
549
1ffeb2eb
JM		 550static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
551{
552 int i;
553
554 qp->sqp_proxy_rcv =
555 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
556 GFP_KERNEL);
557 if (!qp->sqp_proxy_rcv)
558 return -ENOMEM;
559 for (i = 0; i < qp->rq.wqe_cnt; i++) {
560 qp->sqp_proxy_rcv[i].addr =
561 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
562 GFP_KERNEL);
563 if (!qp->sqp_proxy_rcv[i].addr)
564 goto err;
565 qp->sqp_proxy_rcv[i].map =
566 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
567 sizeof (struct mlx4_ib_proxy_sqp_hdr),
568 DMA_FROM_DEVICE);
cc47d369
SO		 569 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
570 kfree(qp->sqp_proxy_rcv[i].addr);
571 goto err;
572 }
1ffeb2eb
JM		 573 }
574 return 0;
575
576err:
577 while (i > 0) {
578 --i;
579 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
580 sizeof (struct mlx4_ib_proxy_sqp_hdr),
581 DMA_FROM_DEVICE);
582 kfree(qp->sqp_proxy_rcv[i].addr);
583 }
584 kfree(qp->sqp_proxy_rcv);
585 qp->sqp_proxy_rcv = NULL;
586 return -ENOMEM;
587}
588
589static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
590{
591 int i;
592
593 for (i = 0; i < qp->rq.wqe_cnt; i++) {
594 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
595 sizeof (struct mlx4_ib_proxy_sqp_hdr),
596 DMA_FROM_DEVICE);
597 kfree(qp->sqp_proxy_rcv[i].addr);
598 }
599 kfree(qp->sqp_proxy_rcv);
600}
601
0a1405da
SH		 602static int qp_has_rq(struct ib_qp_init_attr *attr)
603{
604 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
605 return 0;
606
607 return !attr->srq;
608}
609
99ec41d0
JM		 610static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
611{
612 int i;
613 for (i = 0; i < dev->caps.num_ports; i++) {
614 if (qpn == dev->caps.qp0_proxy[i])
615 return !!dev->caps.qp0_qkey[i];
616 }
617 return 0;
618}
619
7b59f0f9
EBE		 620static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
621 struct mlx4_ib_qp *qp)
622{
623 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
624 mlx4_counter_free(dev->dev, qp->counter_index->index);
625 list_del(&qp->counter_index->list);
626 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
627
628 kfree(qp->counter_index);
629 qp->counter_index = NULL;
630}
631
225c7b1f
RD		 632static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
633 struct ib_qp_init_attr *init_attr,
40f2287b
JK		 634 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
635 gfp_t gfp)
225c7b1f 636{
a3cdcbfa 637 int qpn;
225c7b1f 638 int err;
1ffeb2eb
JM		 639 struct mlx4_ib_sqp *sqp;
640 struct mlx4_ib_qp *qp;
641 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 642 struct mlx4_ib_cq *mcq;
643 unsigned long flags;
1ffeb2eb
JM		 644
645 /* When tunneling special qps, we use a plain UD qp */
646 if (sqpn) {
647 if (mlx4_is_mfunc(dev->dev) &&
648 (!mlx4_is_master(dev->dev) ||
649 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
650 if (init_attr->qp_type == IB_QPT_GSI)
651 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 652 else {
653 if (mlx4_is_master(dev->dev) ||
654 qp0_enabled_vf(dev->dev, sqpn))
655 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
656 else
657 qp_type = MLX4_IB_QPT_PROXY_SMI;
658 }
1ffeb2eb
JM		 659 }
660 qpn = sqpn;
661 /* add extra sg entry for tunneling */
662 init_attr->cap.max_recv_sge++;
663 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
664 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
665 container_of(init_attr,
666 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
667 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
668 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
669 !mlx4_is_master(dev->dev))
670 return -EINVAL;
671 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
672 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 673 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
674 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
675 tnl_init->port))
1ffeb2eb
JM		 676 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
677 else
678 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 679 /* we are definitely in the PPF here, since we are creating
680 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
681 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
682 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 683 sqpn = qpn;
684 }
685
686 if (!*caller_qp) {
687 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
688 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
689 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6fcd8d0d 690 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
1ffeb2eb
JM		 691 if (!sqp)
692 return -ENOMEM;
693 qp = &sqp->qp;
2f5bb473
JM		 694 qp->pri.vid = 0xFFFF;
695 qp->alt.vid = 0xFFFF;
1ffeb2eb 696 } else {
6fcd8d0d 697 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
1ffeb2eb
JM		 698 if (!qp)
699 return -ENOMEM;
2f5bb473
JM		 700 qp->pri.vid = 0xFFFF;
701 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 702 }
703 } else
704 qp = *caller_qp;
705
706 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 707
708 mutex_init(&qp->mutex);
709 spin_lock_init(&qp->sq.lock);
710 spin_lock_init(&qp->rq.lock);
fa417f7b 711 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 712 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 713
714 qp->state = IB_QPS_RESET;
ea54b10c
JM		 715 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
716 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 717
0a1405da 718 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
225c7b1f
RD		 719 if (err)
720 goto err;
721
722 if (pd->uobject) {
723 struct mlx4_ib_create_qp ucmd;
724
725 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
726 err = -EFAULT;
727 goto err;
728 }
729
0e6e7416
RD		 730 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
731
83904132 732 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 733 if (err)
734 goto err;
735
225c7b1f 736 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 737 qp->buf_size, 0, 0);
225c7b1f
RD		 738 if (IS_ERR(qp->umem)) {
739 err = PTR_ERR(qp->umem);
740 goto err;
741 }
742
743 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
744 ilog2(qp->umem->page_size), &qp->mtt);
745 if (err)
746 goto err_buf;
747
748 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
749 if (err)
750 goto err_mtt;
751
0a1405da 752 if (qp_has_rq(init_attr)) {
02d89b87
RD		 753 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
754 ucmd.db_addr, &qp->db);
755 if (err)
756 goto err_mtt;
757 }
225c7b1f 758 } else {
0e6e7416
RD		 759 qp->sq_no_prefetch = 0;
760
b832be1e
EC		 761 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
762 qp->flags |= MLX4_IB_QP_LSO;
763
c1c98501
MB		 764 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
765 if (dev->steering_support ==
766 MLX4_STEERING_MODE_DEVICE_MANAGED)
767 qp->flags |= MLX4_IB_QP_NETIF;
768 else
769 goto err;
770 }
771
1ffeb2eb 772 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 773 if (err)
774 goto err;
775
0a1405da 776 if (qp_has_rq(init_attr)) {
40f2287b 777 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
02d89b87
RD		 778 if (err)
779 goto err;
225c7b1f 780
02d89b87
RD		 781 *qp->db.db = 0;
782 }
225c7b1f 783
40f2287b 784 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
225c7b1f
RD		 785 err = -ENOMEM;
786 goto err_db;
787 }
788
789 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
790 &qp->mtt);
791 if (err)
792 goto err_buf;
793
40f2287b 794 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
225c7b1f
RD		 795 if (err)
796 goto err_mtt;
797
0ef2f05c
WW		 798 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(u64), gfp);
799 if (!qp->sq.wrid)
800 qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64),
801 gfp, PAGE_KERNEL);
802 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(u64), gfp);
803 if (!qp->rq.wrid)
804 qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64),
805 gfp, PAGE_KERNEL);
225c7b1f
RD		 806 if (!qp->sq.wrid || !qp->rq.wrid) {
807 err = -ENOMEM;
808 goto err_wrid;
809 }
225c7b1f
RD		 810 }
811
a3cdcbfa 812 if (sqpn) {
1ffeb2eb
JM		 813 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
814 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
815 if (alloc_proxy_bufs(pd->device, qp)) {
816 err = -ENOMEM;
817 goto err_wrid;
818 }
819 }
a3cdcbfa 820 } else {
ddae0349
EE		 821 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
822 * otherwise, the WQE BlueFlame setup flow wrongly causes
823 * VLAN insertion. */
3987a2d3 824 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 825 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 826 (init_attr->cap.max_send_wr ?
827 MLX4_RESERVE_ETH_BF_QP : 0) |
828 (init_attr->cap.max_recv_wr ?
829 MLX4_RESERVE_A0_QP : 0));
3987a2d3 830 else
c1c98501
MB		 831 if (qp->flags & MLX4_IB_QP_NETIF)
832 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
833 else
834 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
ddae0349 835 &qpn, 0);
a3cdcbfa 836 if (err)
1ffeb2eb 837 goto err_proxy;
a3cdcbfa
YP		 838 }
839
fbfb6625
EBE		 840 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
841 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
842
40f2287b 843 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
225c7b1f 844 if (err)
a3cdcbfa 845 goto err_qpn;
225c7b1f 846
0a1405da
SH		 847 if (init_attr->qp_type == IB_QPT_XRC_TGT)
848 qp->mqp.qpn |= (1 << 23);
849
225c7b1f
RD		 850 /*
851 * Hardware wants QPN written in big-endian order (after
852 * shifting) for send doorbell. Precompute this value to save
853 * a little bit when posting sends.
854 */
855 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
856
225c7b1f 857 qp->mqp.event = mlx4_ib_qp_event;
1ffeb2eb
JM		 858 if (!*caller_qp)
859 *caller_qp = qp;
35f05dab
YH		 860
861 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
862 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
863 to_mcq(init_attr->recv_cq));
864 /* Maintain device to QPs access, needed for further handling
865 * via reset flow
866 */
867 list_add_tail(&qp->qps_list, &dev->qp_list);
868 /* Maintain CQ to QPs access, needed for further handling
869 * via reset flow
870 */
871 mcq = to_mcq(init_attr->send_cq);
872 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
873 mcq = to_mcq(init_attr->recv_cq);
874 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
875 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
876 to_mcq(init_attr->recv_cq));
877 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 878 return 0;
879
a3cdcbfa 880err_qpn:
c1c98501
MB		 881 if (!sqpn) {
882 if (qp->flags & MLX4_IB_QP_NETIF)
883 mlx4_ib_steer_qp_free(dev, qpn, 1);
884 else
885 mlx4_qp_release_range(dev->dev, qpn, 1);
886 }
1ffeb2eb
JM		 887err_proxy:
888 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
889 free_proxy_bufs(pd->device, qp);
225c7b1f 890err_wrid:
23f1b384 891 if (pd->uobject) {
0a1405da
SH		 892 if (qp_has_rq(init_attr))
893 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 894 } else {
0ef2f05c
WW		 895 kvfree(qp->sq.wrid);
896 kvfree(qp->rq.wrid);
225c7b1f
RD		 897 }
898
899err_mtt:
900 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
901
902err_buf:
903 if (pd->uobject)
904 ib_umem_release(qp->umem);
905 else
906 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
907
908err_db:
0a1405da 909 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 910 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 911
912err:
1ffeb2eb
JM		 913 if (!*caller_qp)
914 kfree(qp);
225c7b1f
RD		 915 return err;
916}
917
918static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
919{
920 switch (state) {
921 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
922 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
923 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
924 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
925 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
926 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
927 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
928 default: return -1;
929 }
930}
931
932static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 933 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 934{
338a8fad 935 if (send_cq == recv_cq) {
35f05dab 936 spin_lock(&send_cq->lock);
338a8fad
RD		 937 __acquire(&recv_cq->lock);
938 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 939 spin_lock(&send_cq->lock);
225c7b1f
RD		 940 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
941 } else {
35f05dab 942 spin_lock(&recv_cq->lock);
225c7b1f
RD		 943 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
944 }
945}
946
947static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 948 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 949{
338a8fad
RD		 950 if (send_cq == recv_cq) {
951 __release(&recv_cq->lock);
35f05dab 952 spin_unlock(&send_cq->lock);
338a8fad 953 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 954 spin_unlock(&recv_cq->lock);
35f05dab 955 spin_unlock(&send_cq->lock);
225c7b1f
RD		 956 } else {
957 spin_unlock(&send_cq->lock);
35f05dab 958 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 959 }
960}
961
fa417f7b
EC		 962static void del_gid_entries(struct mlx4_ib_qp *qp)
963{
964 struct mlx4_ib_gid_entry *ge, *tmp;
965
966 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
967 list_del(&ge->list);
968 kfree(ge);
969 }
970}
971
0a1405da
SH		 972static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
973{
974 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
975 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
976 else
977 return to_mpd(qp->ibqp.pd);
978}
979
980static void get_cqs(struct mlx4_ib_qp *qp,
981 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
982{
983 switch (qp->ibqp.qp_type) {
984 case IB_QPT_XRC_TGT:
985 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
986 *recv_cq = *send_cq;
987 break;
988 case IB_QPT_XRC_INI:
989 *send_cq = to_mcq(qp->ibqp.send_cq);
990 *recv_cq = *send_cq;
991 break;
992 default:
993 *send_cq = to_mcq(qp->ibqp.send_cq);
994 *recv_cq = to_mcq(qp->ibqp.recv_cq);
995 break;
996 }
997}
998
225c7b1f
RD		 999static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1000 int is_user)
1001{
1002 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1003 unsigned long flags;
225c7b1f 1004
2f5bb473 1005 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1006 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1007 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1008 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1009 qp->mqp.qpn);
25476b02 1010 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1011 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1012 qp->pri.smac = 0;
25476b02 1013 qp->pri.smac_port = 0;
2f5bb473
JM		 1014 }
1015 if (qp->alt.smac) {
1016 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1017 qp->alt.smac = 0;
1018 }
1019 if (qp->pri.vid < 0x1000) {
1020 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1021 qp->pri.vid = 0xFFFF;
1022 qp->pri.candidate_vid = 0xFFFF;
1023 qp->pri.update_vid = 0;
1024 }
1025 if (qp->alt.vid < 0x1000) {
1026 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1027 qp->alt.vid = 0xFFFF;
1028 qp->alt.candidate_vid = 0xFFFF;
1029 qp->alt.update_vid = 0;
1030 }
1031 }
225c7b1f 1032
0a1405da 1033 get_cqs(qp, &send_cq, &recv_cq);
225c7b1f 1034
35f05dab 1035 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1036 mlx4_ib_lock_cqs(send_cq, recv_cq);
1037
35f05dab
YH		 1038 /* del from lists under both locks above to protect reset flow paths */
1039 list_del(&qp->qps_list);
1040 list_del(&qp->cq_send_list);
1041 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1042 if (!is_user) {
1043 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1044 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1045 if (send_cq != recv_cq)
1046 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1047 }
1048
1049 mlx4_qp_remove(dev->dev, &qp->mqp);
1050
1051 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1052 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1053
1054 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1055
c1c98501
MB		 1056 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1057 if (qp->flags & MLX4_IB_QP_NETIF)
1058 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1059 else
1060 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1061 }
a3cdcbfa 1062
225c7b1f
RD		 1063 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1064
1065 if (is_user) {
0a1405da 1066 if (qp->rq.wqe_cnt)
02d89b87
RD		 1067 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1068 &qp->db);
225c7b1f
RD		 1069 ib_umem_release(qp->umem);
1070 } else {
0ef2f05c
WW		 1071 kvfree(qp->sq.wrid);
1072 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1073 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1074 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1075 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1076 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1077 if (qp->rq.wqe_cnt)
6296883c 1078 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1079 }
fa417f7b
EC		 1080
1081 del_gid_entries(qp);
225c7b1f
RD		 1082}
1083
47605df9
JM		 1084static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1085{
1086 /* Native or PPF */
1087 if (!mlx4_is_mfunc(dev->dev) ||
1088 (mlx4_is_master(dev->dev) &&
1089 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1090 return dev->dev->phys_caps.base_sqpn +
1091 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1092 attr->port_num - 1;
1093 }
1094 /* PF or VF -- creating proxies */
1095 if (attr->qp_type == IB_QPT_SMI)
1096 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1097 else
1098 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1099}
1100
225c7b1f
RD		 1101struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1102 struct ib_qp_init_attr *init_attr,
1103 struct ib_udata *udata)
1104{
1ffeb2eb 1105 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1106 int err;
fbfb6625 1107 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1108 u16 xrcdn = 0;
40f2287b 1109 gfp_t gfp;
225c7b1f 1110
40f2287b
JK		 1111 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1112 GFP_NOIO : GFP_KERNEL;
521e575b 1113 /*
1ffeb2eb
JM		 1114 * We only support LSO, vendor flag1, and multicast loopback blocking,
1115 * and only for kernel UD QPs.
521e575b 1116 */
1ffeb2eb
JM		 1117 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1118 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1119 MLX4_IB_SRIOV_TUNNEL_QP |
1120 MLX4_IB_SRIOV_SQP |
40f2287b
JK		 1121 MLX4_IB_QP_NETIF |
1122 MLX4_IB_QP_CREATE_USE_GFP_NOIO))
b832be1e 1123 return ERR_PTR(-EINVAL);
521e575b 1124
c1c98501
MB		 1125 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1126 if (init_attr->qp_type != IB_QPT_UD)
1127 return ERR_PTR(-EINVAL);
1128 }
1129
521e575b 1130 if (init_attr->create_flags &&
fbfb6625
EBE		 1131 ((udata && init_attr->create_flags & ~(sup_u_create_flags)) ||
1132 ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1133 MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1134 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)) &&
1ffeb2eb
JM		 1135 init_attr->qp_type != IB_QPT_UD) ||
1136 ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1137 init_attr->qp_type > IB_QPT_GSI)))
b846f25a
EC		 1138 return ERR_PTR(-EINVAL);
1139
225c7b1f 1140 switch (init_attr->qp_type) {
0a1405da
SH		 1141 case IB_QPT_XRC_TGT:
1142 pd = to_mxrcd(init_attr->xrcd)->pd;
1143 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1144 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1145 /* fall through */
1146 case IB_QPT_XRC_INI:
1147 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1148 return ERR_PTR(-ENOSYS);
1149 init_attr->recv_cq = init_attr->send_cq;
1150 /* fall through */
225c7b1f
RD		 1151 case IB_QPT_RC:
1152 case IB_QPT_UC:
3987a2d3 1153 case IB_QPT_RAW_PACKET:
40f2287b 1154 qp = kzalloc(sizeof *qp, gfp);
225c7b1f
RD		 1155 if (!qp)
1156 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1157 qp->pri.vid = 0xFFFF;
1158 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1159 /* fall through */
1160 case IB_QPT_UD:
1161 {
1162 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
40f2287b 1163 udata, 0, &qp, gfp);
1ffeb2eb 1164 if (err)
225c7b1f 1165 return ERR_PTR(err);
225c7b1f
RD		 1166
1167 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1168 qp->xrcdn = xrcdn;
225c7b1f
RD		 1169
1170 break;
1171 }
1172 case IB_QPT_SMI:
1173 case IB_QPT_GSI:
1174 {
1175 /* Userspace is not allowed to create special QPs: */
0a1405da 1176 if (udata)
225c7b1f
RD		 1177 return ERR_PTR(-EINVAL);
1178
0a1405da 1179 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
47605df9 1180 get_sqp_num(to_mdev(pd->device), init_attr),
40f2287b 1181 &qp, gfp);
1ffeb2eb 1182 if (err)
225c7b1f 1183 return ERR_PTR(err);
225c7b1f
RD		 1184
1185 qp->port = init_attr->port_num;
1186 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1187
1188 break;
1189 }
1190 default:
1191 /* Don't support raw QPs */
1192 return ERR_PTR(-EINVAL);
1193 }
1194
1195 return &qp->ibqp;
1196}
1197
1198int mlx4_ib_destroy_qp(struct ib_qp *qp)
1199{
1200 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1201 struct mlx4_ib_qp *mqp = to_mqp(qp);
0a1405da 1202 struct mlx4_ib_pd *pd;
225c7b1f
RD		 1203
1204 if (is_qp0(dev, mqp))
1205 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1206
9433c188
MB		 1207 if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1208 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1209 dev->qp1_proxy[mqp->port - 1] = NULL;
1210 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1211 }
1212
7b59f0f9
EBE		 1213 if (mqp->counter_index)
1214 mlx4_ib_free_qp_counter(dev, mqp);
1215
0a1405da
SH		 1216 pd = get_pd(mqp);
1217 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
225c7b1f
RD		 1218
1219 if (is_sqp(dev, mqp))
1220 kfree(to_msqp(mqp));
1221 else
1222 kfree(mqp);
1223
1224 return 0;
1225}
1226
1ffeb2eb 1227static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1228{
1229 switch (type) {
1ffeb2eb
JM		 1230 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1231 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1232 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1233 case MLX4_IB_QPT_XRC_INI:
1234 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1235 case MLX4_IB_QPT_SMI:
1236 case MLX4_IB_QPT_GSI:
1237 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1238
1239 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1240 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1241 MLX4_QP_ST_MLX : -1);
1242 case MLX4_IB_QPT_PROXY_SMI:
1243 case MLX4_IB_QPT_TUN_SMI:
1244 case MLX4_IB_QPT_PROXY_GSI:
1245 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1246 MLX4_QP_ST_UD : -1);
1247 default: return -1;
225c7b1f
RD		 1248 }
1249}
1250
65adfa91 1251static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1252 int attr_mask)
1253{
1254 u8 dest_rd_atomic;
1255 u32 access_flags;
1256 u32 hw_access_flags = 0;
1257
1258 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1259 dest_rd_atomic = attr->max_dest_rd_atomic;
1260 else
1261 dest_rd_atomic = qp->resp_depth;
1262
1263 if (attr_mask & IB_QP_ACCESS_FLAGS)
1264 access_flags = attr->qp_access_flags;
1265 else
1266 access_flags = qp->atomic_rd_en;
1267
1268 if (!dest_rd_atomic)
1269 access_flags &= IB_ACCESS_REMOTE_WRITE;
1270
1271 if (access_flags & IB_ACCESS_REMOTE_READ)
1272 hw_access_flags |= MLX4_QP_BIT_RRE;
1273 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1274 hw_access_flags |= MLX4_QP_BIT_RAE;
1275 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1276 hw_access_flags |= MLX4_QP_BIT_RWE;
1277
1278 return cpu_to_be32(hw_access_flags);
1279}
1280
65adfa91 1281static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1282 int attr_mask)
1283{
1284 if (attr_mask & IB_QP_PKEY_INDEX)
1285 sqp->pkey_index = attr->pkey_index;
1286 if (attr_mask & IB_QP_QKEY)
1287 sqp->qkey = attr->qkey;
1288 if (attr_mask & IB_QP_SQ_PSN)
1289 sqp->send_psn = attr->sq_psn;
1290}
1291
1292static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1293{
1294 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1295}
1296
297e0dad
MS		 1297static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1298 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1299 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1300{
fa417f7b
EC		 1301 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1302 IB_LINK_LAYER_ETHERNET;
4c3eb3ca 1303 int vidx;
297e0dad 1304 int smac_index;
2f5bb473 1305 int err;
297e0dad 1306
fa417f7b 1307
225c7b1f
RD		 1308 path->grh_mylmc = ah->src_path_bits & 0x7f;
1309 path->rlid = cpu_to_be16(ah->dlid);
1310 if (ah->static_rate) {
1311 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1312 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1313 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1314 --path->static_rate;
1315 } else
1316 path->static_rate = 0;
225c7b1f
RD		 1317
1318 if (ah->ah_flags & IB_AH_GRH) {
5070cd22
MS		 1319 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1320 port,
1321 ah->grh.sgid_index);
1322
1323 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1324 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1325 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1326 return -1;
1327 }
1328
1329 path->grh_mylmc |= 1 << 7;
5070cd22 1330 path->mgid_index = real_sgid_index;
225c7b1f
RD		 1331 path->hop_limit = ah->grh.hop_limit;
1332 path->tclass_flowlabel =
1333 cpu_to_be32((ah->grh.traffic_class << 20) |
1334 (ah->grh.flow_label));
1335 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1336 }
1337
fa417f7b
EC		 1338 if (is_eth) {
1339 if (!(ah->ah_flags & IB_AH_GRH))
1340 return -1;
1341
2f5bb473
JM		 1342 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1343 ((port - 1) << 6) | ((ah->sl & 7) << 3);
4c3eb3ca 1344
297e0dad 1345 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1346 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1347 if (smac_info->vid < 0x1000) {
1348 /* both valid vlan ids */
1349 if (smac_info->vid != vlan_tag) {
1350 /* different VIDs. unreg old and reg new */
1351 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1352 if (err)
1353 return err;
1354 smac_info->candidate_vid = vlan_tag;
1355 smac_info->candidate_vlan_index = vidx;
1356 smac_info->candidate_vlan_port = port;
1357 smac_info->update_vid = 1;
1358 path->vlan_index = vidx;
1359 } else {
1360 path->vlan_index = smac_info->vlan_index;
1361 }
1362 } else {
1363 /* no current vlan tag in qp */
1364 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1365 if (err)
1366 return err;
1367 smac_info->candidate_vid = vlan_tag;
1368 smac_info->candidate_vlan_index = vidx;
1369 smac_info->candidate_vlan_port = port;
1370 smac_info->update_vid = 1;
1371 path->vlan_index = vidx;
1372 }
297e0dad 1373 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1374 path->fl = 1 << 6;
1375 } else {
1376 /* have current vlan tag. unregister it at modify-qp success */
1377 if (smac_info->vid < 0x1000) {
1378 smac_info->candidate_vid = 0xFFFF;
1379 smac_info->update_vid = 1;
1380 }
4c3eb3ca 1381 }
2f5bb473
JM		 1382
1383 /* get smac_index for RoCE use.
1384 * If no smac was yet assigned, register one.
1385 * If one was already assigned, but the new mac differs,
1386 * unregister the old one and register the new one.
1387 */
25476b02
JM		 1388 if ((!smac_info->smac && !smac_info->smac_port) ||
1389 smac_info->smac != smac) {
2f5bb473
JM		 1390 /* register candidate now, unreg if needed, after success */
1391 smac_index = mlx4_register_mac(dev->dev, port, smac);
1392 if (smac_index >= 0) {
1393 smac_info->candidate_smac_index = smac_index;
1394 smac_info->candidate_smac = smac;
1395 smac_info->candidate_smac_port = port;
1396 } else {
1397 return -EINVAL;
1398 }
1399 } else {
1400 smac_index = smac_info->smac_index;
1401 }
1402
1403 memcpy(path->dmac, ah->dmac, 6);
1404 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1405 /* put MAC table smac index for IBoE */
1406 path->grh_mylmc = (u8) (smac_index) | 0x80;
1407 } else {
4c3eb3ca
EC		 1408 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1409 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
2f5bb473 1410 }
fa417f7b 1411
225c7b1f
RD		 1412 return 0;
1413}
1414
297e0dad
MS		 1415static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1416 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1417 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1418 struct mlx4_qp_path *path, u8 port,
1419 u16 vlan_id, u8 *smac)
297e0dad
MS		 1420{
1421 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1422 mlx4_mac_to_u64(smac),
1423 vlan_id,
2f5bb473 1424 path, &mqp->pri, port);
297e0dad
MS		 1425}
1426
1427static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1428 const struct ib_qp_attr *qp,
1429 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1430 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1431 struct mlx4_qp_path *path, u8 port)
1432{
1433 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1434 0,
1435 0xffff,
2f5bb473 1436 path, &mqp->alt, port);
297e0dad
MS		 1437}
1438
fa417f7b
EC		 1439static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1440{
1441 struct mlx4_ib_gid_entry *ge, *tmp;
1442
1443 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1444 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1445 ge->added = 1;
1446 ge->port = qp->port;
1447 }
1448 }
1449}
1450
dbf727de
MB		 1451static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1452 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1453 struct mlx4_qp_context *context)
1454{
2f5bb473
JM		 1455 u64 u64_mac;
1456 int smac_index;
1457
3e0629cb 1458 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1459
1460 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1461 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1462 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1463 if (smac_index >= 0) {
1464 qp->pri.candidate_smac_index = smac_index;
1465 qp->pri.candidate_smac = u64_mac;
1466 qp->pri.candidate_smac_port = qp->port;
1467 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1468 } else {
1469 return -ENOENT;
1470 }
1471 }
1472 return 0;
1473}
1474
7b59f0f9
EBE		 1475static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1476{
1477 struct counter_index *new_counter_index;
1478 int err;
1479 u32 tmp_idx;
1480
1481 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1482 IB_LINK_LAYER_ETHERNET ||
1483 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1484 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1485 return 0;
1486
1487 err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1488 if (err)
1489 return err;
1490
1491 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1492 if (!new_counter_index) {
1493 mlx4_counter_free(dev->dev, tmp_idx);
1494 return -ENOMEM;
1495 }
1496
1497 new_counter_index->index = tmp_idx;
1498 new_counter_index->allocated = 1;
1499 qp->counter_index = new_counter_index;
1500
1501 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1502 list_add_tail(&new_counter_index->list,
1503 &dev->counters_table[qp->port - 1].counters_list);
1504 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1505
1506 return 0;
1507}
1508
65adfa91
MT		 1509static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1510 const struct ib_qp_attr *attr, int attr_mask,
1511 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 1512{
1513 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1514 struct mlx4_ib_qp *qp = to_mqp(ibqp);
0a1405da
SH		 1515 struct mlx4_ib_pd *pd;
1516 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 1517 struct mlx4_qp_context *context;
1518 enum mlx4_qp_optpar optpar = 0;
225c7b1f 1519 int sqd_event;
c1c98501 1520 int steer_qp = 0;
225c7b1f 1521 int err = -EINVAL;
3ba8e31d 1522 int counter_index;
225c7b1f 1523
3dec4878
JM		 1524 /* APM is not supported under RoCE */
1525 if (attr_mask & IB_QP_ALT_PATH &&
1526 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1527 IB_LINK_LAYER_ETHERNET)
1528 return -ENOTSUPP;
1529
225c7b1f
RD		 1530 context = kzalloc(sizeof *context, GFP_KERNEL);
1531 if (!context)
1532 return -ENOMEM;
1533
225c7b1f 1534 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 1535 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 1536
1537 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1538 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1539 else {
1540 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1541 switch (attr->path_mig_state) {
1542 case IB_MIG_MIGRATED:
1543 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1544 break;
1545 case IB_MIG_REARM:
1546 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1547 break;
1548 case IB_MIG_ARMED:
1549 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1550 break;
1551 }
1552 }
1553
b832be1e 1554 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 1555 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
3987a2d3
OG		 1556 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1557 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
b832be1e
EC		 1558 else if (ibqp->qp_type == IB_QPT_UD) {
1559 if (qp->flags & MLX4_IB_QP_LSO)
1560 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1561 ilog2(dev->dev->caps.max_gso_sz);
1562 else
6e0d733d 1563 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 1564 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 1565 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 1566 pr_err("path MTU (%u) is invalid\n",
225c7b1f 1567 attr->path_mtu);
f5b40431 1568 goto out;
225c7b1f 1569 }
d1f2cd89
EC		 1570 context->mtu_msgmax = (attr->path_mtu << 5) |
1571 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 1572 }
1573
0e6e7416
RD		 1574 if (qp->rq.wqe_cnt)
1575 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 1576 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1577
0e6e7416
RD		 1578 if (qp->sq.wqe_cnt)
1579 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 1580 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1581
7b59f0f9
EBE		 1582 if (new_state == IB_QPS_RESET && qp->counter_index)
1583 mlx4_ib_free_qp_counter(dev, qp);
1584
0a1405da 1585 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 1586 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 1587 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
02d7ef6f
DB		 1588 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1589 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 1590 }
0e6e7416 1591
225c7b1f
RD		 1592 if (qp->ibqp.uobject)
1593 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1594 else
1595 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1596
1597 if (attr_mask & IB_QP_DEST_QPN)
1598 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1599
1600 if (attr_mask & IB_QP_PORT) {
1601 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1602 !(attr_mask & IB_QP_AV)) {
1603 mlx4_set_sched(&context->pri_path, attr->port_num);
1604 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1605 }
1606 }
1607
cfcde11c 1608 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 1609 err = create_qp_lb_counter(dev, qp);
1610 if (err)
1611 goto out;
1612
3ba8e31d
EBE		 1613 counter_index =
1614 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 1615 if (qp->counter_index)
1616 counter_index = qp->counter_index->index;
1617
3ba8e31d
EBE		 1618 if (counter_index != -1) {
1619 context->pri_path.counter_index = counter_index;
cfcde11c 1620 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 1621 if (qp->counter_index) {
1622 context->pri_path.fl |=
1623 MLX4_FL_ETH_SRC_CHECK_MC_LB;
1624 context->pri_path.vlan_control |=
1625 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1626 }
cfcde11c 1627 } else
47d8417f
EBE		 1628 context->pri_path.counter_index =
1629 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 1630
1631 if (qp->flags & MLX4_IB_QP_NETIF) {
1632 mlx4_ib_steer_qp_reg(dev, qp, 1);
1633 steer_qp = 1;
1634 }
cfcde11c
OG		 1635 }
1636
225c7b1f 1637 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 1638 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1639 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 1640 context->pri_path.pkey_index = attr->pkey_index;
1641 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1642 }
1643
225c7b1f 1644 if (attr_mask & IB_QP_AV) {
dbf727de
MB		 1645 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1646 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1647 union ib_gid gid;
1648 struct ib_gid_attr gid_attr;
1649 u16 vlan = 0xffff;
1650 u8 smac[ETH_ALEN];
1651 int status = 0;
1652
1653 if (rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1654 attr->ah_attr.ah_flags & IB_AH_GRH) {
1655 int index = attr->ah_attr.grh.sgid_index;
1656
1657 status = ib_get_cached_gid(ibqp->device, port_num,
1658 index, &gid, &gid_attr);
1659 if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1660 status = -ENOENT;
1661 if (!status && gid_attr.ndev) {
1662 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1663 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1664 dev_put(gid_attr.ndev);
1665 }
1666 }
1667 if (status)
1668 goto out;
1669
2f5bb473 1670 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 1671 port_num, vlan, smac))
225c7b1f 1672 goto out;
225c7b1f
RD		 1673
1674 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1675 MLX4_QP_OPTPAR_SCHED_QUEUE);
1676 }
1677
1678 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 1679 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 1680 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1681 }
1682
1683 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 1684 if (attr->alt_port_num == 0 ||
1685 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 1686 goto out;
225c7b1f 1687
5ae2a7a8
RD		 1688 if (attr->alt_pkey_index >=
1689 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 1690 goto out;
5ae2a7a8 1691
2f5bb473
JM		 1692 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1693 &context->alt_path,
297e0dad 1694 attr->alt_port_num))
f5b40431 1695 goto out;
225c7b1f
RD		 1696
1697 context->alt_path.pkey_index = attr->alt_pkey_index;
1698 context->alt_path.ackto = attr->alt_timeout << 3;
1699 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1700 }
1701
0a1405da
SH		 1702 pd = get_pd(qp);
1703 get_cqs(qp, &send_cq, &recv_cq);
1704 context->pd = cpu_to_be32(pd->pdn);
1705 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1706 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1707 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 1708
95d04f07
RD		 1709 /* Set "fast registration enabled" for all kernel QPs */
1710 if (!qp->ibqp.uobject)
1711 context->params1 |= cpu_to_be32(1 << 11);
1712
57f01b53
JM		 1713 if (attr_mask & IB_QP_RNR_RETRY) {
1714 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1715 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1716 }
1717
225c7b1f
RD		 1718 if (attr_mask & IB_QP_RETRY_CNT) {
1719 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1720 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1721 }
1722
1723 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1724 if (attr->max_rd_atomic)
1725 context->params1 |=
1726 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1727 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1728 }
1729
1730 if (attr_mask & IB_QP_SQ_PSN)
1731 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1732
225c7b1f
RD		 1733 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1734 if (attr->max_dest_rd_atomic)
1735 context->params2 |=
1736 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1737 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1738 }
1739
1740 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1741 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1742 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1743 }
1744
1745 if (ibqp->srq)
1746 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1747
1748 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1749 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1750 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1751 }
1752 if (attr_mask & IB_QP_RQ_PSN)
1753 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1754
1ffeb2eb 1755 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 1756 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 1757 if (qp->mlx4_ib_qp_type &
1758 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1759 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1760 else {
1761 if (mlx4_is_mfunc(dev->dev) &&
1762 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1763 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1764 MLX4_RESERVED_QKEY_BASE) {
1765 pr_err("Cannot use reserved QKEY"
1766 " 0x%x (range 0xffff0000..0xffffffff"
1767 " is reserved)\n", attr->qkey);
1768 err = -EINVAL;
1769 goto out;
1770 }
1771 context->qkey = cpu_to_be32(attr->qkey);
1772 }
225c7b1f
RD		 1773 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1774 }
1775
1776 if (ibqp->srq)
1777 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1778
0a1405da 1779 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1780 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1781
1782 if (cur_state == IB_QPS_INIT &&
1783 new_state == IB_QPS_RTR &&
1784 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
3987a2d3
OG		 1785 ibqp->qp_type == IB_QPT_UD ||
1786 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 1787 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 1788 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1789 qp->mlx4_ib_qp_type &
1790 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 1791 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 1792 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1793 context->pri_path.fl = 0x80;
1794 } else {
1795 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1796 context->pri_path.fl = 0x80;
225c7b1f 1797 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 1798 }
2f5bb473
JM		 1799 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1800 IB_LINK_LAYER_ETHERNET) {
1801 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1802 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1803 context->pri_path.feup = 1 << 7; /* don't fsm */
1804 /* handle smac_index */
1805 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1806 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1807 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 1808 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 1809 if (err) {
1810 err = -EINVAL;
1811 goto out;
1812 }
9433c188
MB		 1813 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1814 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 1815 }
1816 }
225c7b1f
RD		 1817 }
1818
d2fce8a9 1819 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 1820 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1821 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 1822 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1823 /* set QP to receive both tunneled & non-tunneled packets */
8e1a03b6 1824 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
d2fce8a9
OG		 1825 context->srqn = cpu_to_be32(7 << 28);
1826 }
1827 }
3528f696 1828
297e0dad
MS		 1829 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1830 int is_eth = rdma_port_get_link_layer(
1831 &dev->ib_dev, qp->port) ==
1832 IB_LINK_LAYER_ETHERNET;
1833 if (is_eth) {
1834 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1835 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1836 }
1837 }
1838
1839
225c7b1f
RD		 1840 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1841 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1842 sqd_event = 1;
1843 else
1844 sqd_event = 0;
1845
d57f5f72
VS		 1846 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1847 context->rlkey |= (1 << 4);
1848
c0be5fb5
EC		 1849 /*
1850 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1851 * ownership bits of the send queue are set and the SQ
1852 * headroom is stamped so that the hardware doesn't start
1853 * processing stale work requests.
c0be5fb5
EC		 1854 */
1855 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1856 struct mlx4_wqe_ctrl_seg *ctrl;
1857 int i;
1858
0e6e7416 1859 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1860 ctrl = get_send_wqe(qp, i);
1861 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553
EC		 1862 if (qp->sq_max_wqes_per_wr == 1)
1863 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
0e6e7416 1864
ea54b10c 1865 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 1866 }
1867 }
1868
225c7b1f
RD		 1869 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1870 to_mlx4_state(new_state), context, optpar,
1871 sqd_event, &qp->mqp);
1872 if (err)
1873 goto out;
1874
1875 qp->state = new_state;
1876
1877 if (attr_mask & IB_QP_ACCESS_FLAGS)
1878 qp->atomic_rd_en = attr->qp_access_flags;
1879 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1880 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 1881 if (attr_mask & IB_QP_PORT) {
225c7b1f 1882 qp->port = attr->port_num;
fa417f7b
EC		 1883 update_mcg_macs(dev, qp);
1884 }
225c7b1f
RD		 1885 if (attr_mask & IB_QP_ALT_PATH)
1886 qp->alt_port = attr->alt_port_num;
1887
1888 if (is_sqp(dev, qp))
1889 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1890
1891 /*
1892 * If we moved QP0 to RTR, bring the IB link up; if we moved
1893 * QP0 to RESET or ERROR, bring the link back down.
1894 */
1895 if (is_qp0(dev, qp)) {
1896 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 1897 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 1898 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 1899 qp->port);
225c7b1f
RD		 1900
1901 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1902 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1903 mlx4_CLOSE_PORT(dev->dev, qp->port);
1904 }
1905
1906 /*
1907 * If we moved a kernel QP to RESET, clean up all old CQ
1908 * entries and reinitialize the QP.
1909 */
2f5bb473
JM		 1910 if (new_state == IB_QPS_RESET) {
1911 if (!ibqp->uobject) {
1912 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1913 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1914 if (send_cq != recv_cq)
1915 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1916
1917 qp->rq.head = 0;
1918 qp->rq.tail = 0;
1919 qp->sq.head = 0;
1920 qp->sq.tail = 0;
1921 qp->sq_next_wqe = 0;
1922 if (qp->rq.wqe_cnt)
1923 *qp->db.db = 0;
225c7b1f 1924
2f5bb473
JM		 1925 if (qp->flags & MLX4_IB_QP_NETIF)
1926 mlx4_ib_steer_qp_reg(dev, qp, 0);
1927 }
25476b02 1928 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1929 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1930 qp->pri.smac = 0;
25476b02 1931 qp->pri.smac_port = 0;
2f5bb473
JM		 1932 }
1933 if (qp->alt.smac) {
1934 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1935 qp->alt.smac = 0;
1936 }
1937 if (qp->pri.vid < 0x1000) {
1938 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1939 qp->pri.vid = 0xFFFF;
1940 qp->pri.candidate_vid = 0xFFFF;
1941 qp->pri.update_vid = 0;
1942 }
c1c98501 1943
2f5bb473
JM		 1944 if (qp->alt.vid < 0x1000) {
1945 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1946 qp->alt.vid = 0xFFFF;
1947 qp->alt.candidate_vid = 0xFFFF;
1948 qp->alt.update_vid = 0;
1949 }
225c7b1f 1950 }
225c7b1f 1951out:
7b59f0f9
EBE		 1952 if (err && qp->counter_index)
1953 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 1954 if (err && steer_qp)
1955 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 1956 kfree(context);
25476b02
JM		 1957 if (qp->pri.candidate_smac ||
1958 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 1959 if (err) {
1960 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1961 } else {
25476b02 1962 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 1963 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1964 qp->pri.smac = qp->pri.candidate_smac;
1965 qp->pri.smac_index = qp->pri.candidate_smac_index;
1966 qp->pri.smac_port = qp->pri.candidate_smac_port;
1967 }
1968 qp->pri.candidate_smac = 0;
1969 qp->pri.candidate_smac_index = 0;
1970 qp->pri.candidate_smac_port = 0;
1971 }
1972 if (qp->alt.candidate_smac) {
1973 if (err) {
1974 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1975 } else {
1976 if (qp->alt.smac)
1977 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1978 qp->alt.smac = qp->alt.candidate_smac;
1979 qp->alt.smac_index = qp->alt.candidate_smac_index;
1980 qp->alt.smac_port = qp->alt.candidate_smac_port;
1981 }
1982 qp->alt.candidate_smac = 0;
1983 qp->alt.candidate_smac_index = 0;
1984 qp->alt.candidate_smac_port = 0;
1985 }
1986
1987 if (qp->pri.update_vid) {
1988 if (err) {
1989 if (qp->pri.candidate_vid < 0x1000)
1990 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1991 qp->pri.candidate_vid);
1992 } else {
1993 if (qp->pri.vid < 0x1000)
1994 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1995 qp->pri.vid);
1996 qp->pri.vid = qp->pri.candidate_vid;
1997 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1998 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
1999 }
2000 qp->pri.candidate_vid = 0xFFFF;
2001 qp->pri.update_vid = 0;
2002 }
2003
2004 if (qp->alt.update_vid) {
2005 if (err) {
2006 if (qp->alt.candidate_vid < 0x1000)
2007 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2008 qp->alt.candidate_vid);
2009 } else {
2010 if (qp->alt.vid < 0x1000)
2011 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2012 qp->alt.vid);
2013 qp->alt.vid = qp->alt.candidate_vid;
2014 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2015 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2016 }
2017 qp->alt.candidate_vid = 0xFFFF;
2018 qp->alt.update_vid = 0;
2019 }
2020
225c7b1f
RD		 2021 return err;
2022}
2023
65adfa91
MT		 2024int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2025 int attr_mask, struct ib_udata *udata)
2026{
2027 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2028 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2029 enum ib_qp_state cur_state, new_state;
2030 int err = -EINVAL;
297e0dad 2031 int ll;
65adfa91
MT		 2032 mutex_lock(&qp->mutex);
2033
2034 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2035 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2036
297e0dad
MS		 2037 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2038 ll = IB_LINK_LAYER_UNSPECIFIED;
2039 } else {
2040 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2041 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2042 }
dd5f03be
MB		 2043
2044 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 2045 attr_mask, ll)) {
b1d8eb5a
JM		 2046 pr_debug("qpn 0x%x: invalid attribute mask specified "
2047 "for transition %d to %d. qp_type %d,"
2048 " attr_mask 0x%x\n",
2049 ibqp->qp_num, cur_state, new_state,
2050 ibqp->qp_type, attr_mask);
65adfa91 2051 goto out;
b1d8eb5a 2052 }
65adfa91 2053
c6215745
MS		 2054 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2055 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2056 if ((ibqp->qp_type == IB_QPT_RC) ||
2057 (ibqp->qp_type == IB_QPT_UD) ||
2058 (ibqp->qp_type == IB_QPT_UC) ||
2059 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2060 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2061 attr->port_num = mlx4_ib_bond_next_port(dev);
2062 }
2063 } else {
2064 /* no sense in changing port_num
2065 * when ports are bonded */
2066 attr_mask &= ~IB_QP_PORT;
2067 }
2068 }
2069
65adfa91 2070 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2071 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2072 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2073 "for transition %d to %d. qp_type %d\n",
2074 ibqp->qp_num, attr->port_num, cur_state,
2075 new_state, ibqp->qp_type);
65adfa91
MT		 2076 goto out;
2077 }
2078
3987a2d3
OG		 2079 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2080 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2081 IB_LINK_LAYER_ETHERNET))
2082 goto out;
2083
5ae2a7a8
RD		 2084 if (attr_mask & IB_QP_PKEY_INDEX) {
2085 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2086 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2087 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2088 "for transition %d to %d. qp_type %d\n",
2089 ibqp->qp_num, attr->pkey_index, cur_state,
2090 new_state, ibqp->qp_type);
5ae2a7a8 2091 goto out;
b1d8eb5a 2092 }
5ae2a7a8
RD		 2093 }
2094
65adfa91
MT		 2095 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2096 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2097 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2098 "Transition %d to %d. qp_type %d\n",
2099 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2100 new_state, ibqp->qp_type);
65adfa91
MT		 2101 goto out;
2102 }
2103
2104 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2105 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2106 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2107 "Transition %d to %d. qp_type %d\n",
2108 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2109 new_state, ibqp->qp_type);
65adfa91
MT		 2110 goto out;
2111 }
2112
2113 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2114 err = 0;
2115 goto out;
2116 }
2117
65adfa91
MT		 2118 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2119
c6215745
MS		 2120 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2121 attr->port_num = 1;
2122
65adfa91
MT		 2123out:
2124 mutex_unlock(&qp->mutex);
2125 return err;
2126}
2127
99ec41d0
JM		 2128static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2129{
2130 int i;
2131 for (i = 0; i < dev->caps.num_ports; i++) {
2132 if (qpn == dev->caps.qp0_proxy[i] ||
2133 qpn == dev->caps.qp0_tunnel[i]) {
2134 *qkey = dev->caps.qp0_qkey[i];
2135 return 0;
2136 }
2137 }
2138 return -EINVAL;
2139}
2140
1ffeb2eb 2141static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
e622f2f4 2142 struct ib_ud_wr *wr,
1ffeb2eb
JM		 2143 void *wqe, unsigned *mlx_seg_len)
2144{
2145 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2146 struct ib_device *ib_dev = &mdev->ib_dev;
2147 struct mlx4_wqe_mlx_seg *mlx = wqe;
2148 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2149 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2150 u16 pkey;
2151 u32 qkey;
2152 int send_size;
2153 int header_size;
2154 int spc;
2155 int i;
2156
e622f2f4 2157 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2158 return -EINVAL;
2159
2160 send_size = 0;
2161
e622f2f4
CH		 2162 for (i = 0; i < wr->wr.num_sge; ++i)
2163 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2164
2165 /* for proxy-qp0 sends, need to add in size of tunnel header */
2166 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2167 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2168 send_size += sizeof (struct mlx4_ib_tunnel_header);
2169
25f40220 2170 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2171
2172 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2173 sqp->ud_header.lrh.service_level =
2174 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2175 sqp->ud_header.lrh.destination_lid =
2176 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2177 sqp->ud_header.lrh.source_lid =
2178 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2179 }
2180
2181 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2182
2183 /* force loopback */
2184 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2185 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2186
2187 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2188 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1ffeb2eb
JM		 2189 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2190 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2191 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2192 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2193 else
2194 sqp->ud_header.bth.destination_qpn =
47605df9 2195 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 2196
2197 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2198 if (mlx4_is_master(mdev->dev)) {
2199 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2200 return -EINVAL;
2201 } else {
2202 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2203 return -EINVAL;
2204 }
1ffeb2eb
JM		 2205 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2206 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2207
2208 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2209 sqp->ud_header.immediate_present = 0;
2210
2211 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2212
2213 /*
2214 * Inline data segments may not cross a 64 byte boundary. If
2215 * our UD header is bigger than the space available up to the
2216 * next 64 byte boundary in the WQE, use two inline data
2217 * segments to hold the UD header.
2218 */
2219 spc = MLX4_INLINE_ALIGN -
2220 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2221 if (header_size <= spc) {
2222 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2223 memcpy(inl + 1, sqp->header_buf, header_size);
2224 i = 1;
2225 } else {
2226 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2227 memcpy(inl + 1, sqp->header_buf, spc);
2228
2229 inl = (void *) (inl + 1) + spc;
2230 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2231 /*
2232 * Need a barrier here to make sure all the data is
2233 * visible before the byte_count field is set.
2234 * Otherwise the HCA prefetcher could grab the 64-byte
2235 * chunk with this inline segment and get a valid (!=
2236 * 0xffffffff) byte count but stale data, and end up
2237 * generating a packet with bad headers.
2238 *
2239 * The first inline segment's byte_count field doesn't
2240 * need a barrier, because it comes after a
2241 * control/MLX segment and therefore is at an offset
2242 * of 16 mod 64.
2243 */
2244 wmb();
2245 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2246 i = 2;
2247 }
2248
2249 *mlx_seg_len =
2250 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2251 return 0;
2252}
2253
3e0629cb
JM		 2254static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2255{
2256 int i;
2257
2258 for (i = ETH_ALEN; i; i--) {
2259 dst_mac[i - 1] = src_mac & 0xff;
2260 src_mac >>= 8;
2261 }
2262}
2263
e622f2f4 2264static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
f438000f 2265 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2266{
a478868a 2267 struct ib_device *ib_dev = sqp->qp.ibqp.device;
225c7b1f 2268 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2269 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 2270 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2271 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 2272 union ib_gid sgid;
225c7b1f
RD		 2273 u16 pkey;
2274 int send_size;
2275 int header_size;
e61ef241 2276 int spc;
225c7b1f 2277 int i;
1ffeb2eb 2278 int err = 0;
57d88cff 2279 u16 vlan = 0xffff;
a29bec12
RD		 2280 bool is_eth;
2281 bool is_vlan = false;
2282 bool is_grh;
225c7b1f
RD		 2283
2284 send_size = 0;
e622f2f4
CH		 2285 for (i = 0; i < wr->wr.num_sge; ++i)
2286 send_size += wr->wr.sg_list[i].length;
225c7b1f 2287
fa417f7b
EC		 2288 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2289 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 2290 if (is_eth) {
1ffeb2eb
JM		 2291 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2292 /* When multi-function is enabled, the ib_core gid
2293 * indexes don't necessarily match the hw ones, so
2294 * we must use our own cache */
6ee51a4e
JM		 2295 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2296 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2297 ah->av.ib.gid_index, &sgid.raw[0]);
2298 if (err)
2299 return err;
1ffeb2eb
JM		 2300 } else {
2301 err = ib_get_cached_gid(ib_dev,
2302 be32_to_cpu(ah->av.ib.port_pd) >> 24,
55ee3ab2
MB		 2303 ah->av.ib.gid_index, &sgid,
2304 NULL);
dbf727de
MB		 2305 if (!err && !memcmp(&sgid, &zgid, sizeof(sgid)))
2306 err = -ENOENT;
1ffeb2eb
JM		 2307 if (err)
2308 return err;
2309 }
2310
0e9855db 2311 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 2312 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2313 is_vlan = 1;
2314 }
4c3eb3ca 2315 }
25f40220
MS		 2316 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
2317 0, 0, 0, &sqp->ud_header);
2318 if (err)
2319 return err;
fa417f7b
EC		 2320
2321 if (!is_eth) {
2322 sqp->ud_header.lrh.service_level =
2323 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2324 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2325 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2326 }
225c7b1f 2327
fa417f7b 2328 if (is_grh) {
225c7b1f 2329 sqp->ud_header.grh.traffic_class =
fa417f7b 2330 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 2331 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 2332 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2333 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
6ee51a4e
JM		 2334 if (is_eth)
2335 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2336 else {
1ffeb2eb
JM		 2337 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2338 /* When multi-function is enabled, the ib_core gid
2339 * indexes don't necessarily match the hw ones, so
2340 * we must use our own cache */
2341 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2342 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2343 subnet_prefix;
2344 sqp->ud_header.grh.source_gid.global.interface_id =
2345 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2346 guid_cache[ah->av.ib.gid_index];
2347 } else
2348 ib_get_cached_gid(ib_dev,
2349 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2350 ah->av.ib.gid_index,
55ee3ab2 2351 &sqp->ud_header.grh.source_gid, NULL);
6ee51a4e 2352 }
225c7b1f 2353 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 2354 ah->av.ib.dgid, 16);
225c7b1f
RD		 2355 }
2356
2357 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 2358
2359 if (!is_eth) {
2360 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2361 (sqp->ud_header.lrh.destination_lid ==
2362 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2363 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 2364 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2365 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 2366 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2367 }
225c7b1f 2368
e622f2f4 2369 switch (wr->wr.opcode) {
225c7b1f
RD		 2370 case IB_WR_SEND:
2371 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2372 sqp->ud_header.immediate_present = 0;
2373 break;
2374 case IB_WR_SEND_WITH_IMM:
2375 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2376 sqp->ud_header.immediate_present = 1;
e622f2f4 2377 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 2378 break;
2379 default:
2380 return -EINVAL;
2381 }
2382
fa417f7b 2383 if (is_eth) {
6ee51a4e
JM		 2384 struct in6_addr in6;
2385
c0c1d3d7
OD		 2386 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2387
2388 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b
EC		 2389
2390 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2391 /* FIXME: cache smac value? */
6ee51a4e
JM		 2392 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2393 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2394 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 2395
3e0629cb
JM		 2396 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2397 u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2398 u8 smac[ETH_ALEN];
2399
2400 mlx4_u64_to_smac(smac, mac);
2401 memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2402 } else {
2403 /* use the src mac of the tunnel */
2404 memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2405 }
2406
fa417f7b
EC		 2407 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2408 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca
EC		 2409 if (!is_vlan) {
2410 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2411 } else {
4c3eb3ca 2412 sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
4c3eb3ca
EC		 2413 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2414 }
fa417f7b
EC		 2415 } else {
2416 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
2417 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2418 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2419 }
e622f2f4 2420 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f
RD		 2421 if (!sqp->qp.ibqp.qp_num)
2422 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2423 else
e622f2f4 2424 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
225c7b1f 2425 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 2426 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 2427 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 2428 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2429 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 2430 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2431
2432 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2433
2434 if (0) {
987c8f8f 2435 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 2436 for (i = 0; i < header_size / 4; ++i) {
2437 if (i % 8 == 0)
987c8f8f
SP		 2438 pr_err(" [%02x] ", i * 4);
2439 pr_cont(" %08x",
2440 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 2441 if ((i + 1) % 8 == 0)
987c8f8f 2442 pr_cont("\n");
225c7b1f 2443 }
987c8f8f 2444 pr_err("\n");
225c7b1f
RD		 2445 }
2446
e61ef241
RD		 2447 /*
2448 * Inline data segments may not cross a 64 byte boundary. If
2449 * our UD header is bigger than the space available up to the
2450 * next 64 byte boundary in the WQE, use two inline data
2451 * segments to hold the UD header.
2452 */
2453 spc = MLX4_INLINE_ALIGN -
2454 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2455 if (header_size <= spc) {
2456 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2457 memcpy(inl + 1, sqp->header_buf, header_size);
2458 i = 1;
2459 } else {
2460 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2461 memcpy(inl + 1, sqp->header_buf, spc);
2462
2463 inl = (void *) (inl + 1) + spc;
2464 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2465 /*
2466 * Need a barrier here to make sure all the data is
2467 * visible before the byte_count field is set.
2468 * Otherwise the HCA prefetcher could grab the 64-byte
2469 * chunk with this inline segment and get a valid (!=
2470 * 0xffffffff) byte count but stale data, and end up
2471 * generating a packet with bad headers.
2472 *
2473 * The first inline segment's byte_count field doesn't
2474 * need a barrier, because it comes after a
2475 * control/MLX segment and therefore is at an offset
2476 * of 16 mod 64.
2477 */
2478 wmb();
2479 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2480 i = 2;
2481 }
225c7b1f 2482
f438000f
RD		 2483 *mlx_seg_len =
2484 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2485 return 0;
225c7b1f
RD		 2486}
2487
2488static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2489{
2490 unsigned cur;
2491 struct mlx4_ib_cq *cq;
2492
2493 cur = wq->head - wq->tail;
0e6e7416 2494 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 2495 return 0;
2496
2497 cq = to_mcq(ib_cq);
2498 spin_lock(&cq->lock);
2499 cur = wq->head - wq->tail;
2500 spin_unlock(&cq->lock);
2501
0e6e7416 2502 return cur + nreq >= wq->max_post;
225c7b1f
RD		 2503}
2504
95d04f07
RD		 2505static __be32 convert_access(int acc)
2506{
6ff63e19
SM		 2507 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2508 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2509 (acc & IB_ACCESS_REMOTE_WRITE ?
2510 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2511 (acc & IB_ACCESS_REMOTE_READ ?
2512 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 2513 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2514 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2515}
2516
1b2cd0fc
SG		 2517static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2518 struct ib_reg_wr *wr)
2519{
2520 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2521
2522 fseg->flags = convert_access(wr->access);
2523 fseg->mem_key = cpu_to_be32(wr->key);
2524 fseg->buf_list = cpu_to_be64(mr->page_map);
2525 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
2526 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
2527 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2528 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
2529 fseg->reserved[0] = 0;
2530 fseg->reserved[1] = 0;
2531}
2532
95d04f07
RD		 2533static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2534{
aee38fad
SM		 2535 memset(iseg, 0, sizeof(*iseg));
2536 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 2537}
2538
0fbfa6a9
RD		 2539static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2540 u64 remote_addr, u32 rkey)
2541{
2542 rseg->raddr = cpu_to_be64(remote_addr);
2543 rseg->rkey = cpu_to_be32(rkey);
2544 rseg->reserved = 0;
2545}
2546
e622f2f4
CH		 2547static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2548 struct ib_atomic_wr *wr)
0fbfa6a9 2549{
e622f2f4
CH		 2550 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2551 aseg->swap_add = cpu_to_be64(wr->swap);
2552 aseg->compare = cpu_to_be64(wr->compare_add);
2553 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2554 aseg->swap_add = cpu_to_be64(wr->compare_add);
2555 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 2556 } else {
e622f2f4 2557 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 2558 aseg->compare = 0;
2559 }
2560
2561}
2562
6fa8f719 2563static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
e622f2f4 2564 struct ib_atomic_wr *wr)
6fa8f719 2565{
e622f2f4
CH		 2566 aseg->swap_add = cpu_to_be64(wr->swap);
2567 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
2568 aseg->compare = cpu_to_be64(wr->compare_add);
2569 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 2570}
2571
0fbfa6a9 2572static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 2573 struct ib_ud_wr *wr)
0fbfa6a9 2574{
e622f2f4
CH		 2575 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2576 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2577 dseg->qkey = cpu_to_be32(wr->remote_qkey);
2578 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2579 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 2580}
2581
1ffeb2eb
JM		 2582static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2583 struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 2584 struct ib_ud_wr *wr,
97982f5a 2585 enum mlx4_ib_qp_type qpt)
1ffeb2eb 2586{
e622f2f4 2587 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 2588 struct mlx4_av sqp_av = {0};
2589 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2590
2591 /* force loopback */
2592 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2593 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2594 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2595 cpu_to_be32(0xf0000000);
2596
2597 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a
JM		 2598 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2599 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2600 else
2601 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
47605df9
JM		 2602 /* Use QKEY from the QP context, which is set by master */
2603 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 2604}
2605
e622f2f4 2606static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
1ffeb2eb
JM		 2607{
2608 struct mlx4_wqe_inline_seg *inl = wqe;
2609 struct mlx4_ib_tunnel_header hdr;
e622f2f4 2610 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2611 int spc;
2612 int i;
2613
2614 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 2615 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2616 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2617 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 2618 memcpy(hdr.mac, ah->av.eth.mac, 6);
2619 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 2620
2621 spc = MLX4_INLINE_ALIGN -
2622 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2623 if (sizeof (hdr) <= spc) {
2624 memcpy(inl + 1, &hdr, sizeof (hdr));
2625 wmb();
2626 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2627 i = 1;
2628 } else {
2629 memcpy(inl + 1, &hdr, spc);
2630 wmb();
2631 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2632
2633 inl = (void *) (inl + 1) + spc;
2634 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2635 wmb();
2636 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2637 i = 2;
2638 }
2639
2640 *mlx_seg_len =
2641 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2642}
2643
6e694ea3
JM		 2644static void set_mlx_icrc_seg(void *dseg)
2645{
2646 u32 *t = dseg;
2647 struct mlx4_wqe_inline_seg *iseg = dseg;
2648
2649 t[1] = 0;
2650
2651 /*
2652 * Need a barrier here before writing the byte_count field to
2653 * make sure that all the data is visible before the
2654 * byte_count field is set. Otherwise, if the segment begins
2655 * a new cacheline, the HCA prefetcher could grab the 64-byte
2656 * chunk and get a valid (!= * 0xffffffff) byte count but
2657 * stale data, and end up sending the wrong data.
2658 */
2659 wmb();
2660
2661 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2662}
2663
2664static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 2665{
d420d9e3
RD		 2666 dseg->lkey = cpu_to_be32(sg->lkey);
2667 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 2668
2669 /*
2670 * Need a barrier here before writing the byte_count field to
2671 * make sure that all the data is visible before the
2672 * byte_count field is set. Otherwise, if the segment begins
2673 * a new cacheline, the HCA prefetcher could grab the 64-byte
2674 * chunk and get a valid (!= * 0xffffffff) byte count but
2675 * stale data, and end up sending the wrong data.
2676 */
2677 wmb();
2678
2679 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 2680}
2681
2242fa4f
RD		 2682static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2683{
2684 dseg->byte_count = cpu_to_be32(sg->length);
2685 dseg->lkey = cpu_to_be32(sg->lkey);
2686 dseg->addr = cpu_to_be64(sg->addr);
2687}
2688
e622f2f4 2689static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
0fd7e1d8 2690 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 2691 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 2692{
e622f2f4 2693 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 2694
417608c2
EC		 2695 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2696 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 2697
2698 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 2699 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 2700 return -EINVAL;
2701
e622f2f4 2702 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 2703
e622f2f4 2704 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 2705 *lso_seg_len = halign;
2706 return 0;
2707}
2708
95d04f07
RD		 2709static __be32 send_ieth(struct ib_send_wr *wr)
2710{
2711 switch (wr->opcode) {
2712 case IB_WR_SEND_WITH_IMM:
2713 case IB_WR_RDMA_WRITE_WITH_IMM:
2714 return wr->ex.imm_data;
2715
2716 case IB_WR_SEND_WITH_INV:
2717 return cpu_to_be32(wr->ex.invalidate_rkey);
2718
2719 default:
2720 return 0;
2721 }
2722}
2723
1ffeb2eb
JM		 2724static void add_zero_len_inline(void *wqe)
2725{
2726 struct mlx4_wqe_inline_seg *inl = wqe;
2727 memset(wqe, 0, 16);
2728 inl->byte_count = cpu_to_be32(1 << 31);
2729}
2730
225c7b1f
RD		 2731int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2732 struct ib_send_wr **bad_wr)
2733{
2734 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2735 void *wqe;
2736 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 2737 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 2738 unsigned long flags;
2739 int nreq;
2740 int err = 0;
ea54b10c
JM		 2741 unsigned ind;
2742 int uninitialized_var(stamp);
2743 int uninitialized_var(size);
a3d8e159 2744 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 2745 __be32 dummy;
2746 __be32 *lso_wqe;
2747 __be32 uninitialized_var(lso_hdr_sz);
417608c2 2748 __be32 blh;
225c7b1f 2749 int i;
35f05dab 2750 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 2751
96db0e03 2752 spin_lock_irqsave(&qp->sq.lock, flags);
35f05dab
YH		 2753 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2754 err = -EIO;
2755 *bad_wr = wr;
2756 nreq = 0;
2757 goto out;
2758 }
225c7b1f 2759
ea54b10c 2760 ind = qp->sq_next_wqe;
225c7b1f
RD		 2761
2762 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 2763 lso_wqe = &dummy;
417608c2 2764 blh = 0;
0fd7e1d8 2765
225c7b1f
RD		 2766 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2767 err = -ENOMEM;
2768 *bad_wr = wr;
2769 goto out;
2770 }
2771
2772 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2773 err = -EINVAL;
2774 *bad_wr = wr;
2775 goto out;
2776 }
2777
0e6e7416 2778 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 2779 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 2780
2781 ctrl->srcrb_flags =
2782 (wr->send_flags & IB_SEND_SIGNALED ?
2783 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2784 (wr->send_flags & IB_SEND_SOLICITED ?
2785 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 2786 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2787 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2788 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 2789 qp->sq_signal_bits;
2790
95d04f07 2791 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 2792
2793 wqe += sizeof *ctrl;
2794 size = sizeof *ctrl / 16;
2795
1ffeb2eb
JM		 2796 switch (qp->mlx4_ib_qp_type) {
2797 case MLX4_IB_QPT_RC:
2798 case MLX4_IB_QPT_UC:
225c7b1f
RD		 2799 switch (wr->opcode) {
2800 case IB_WR_ATOMIC_CMP_AND_SWP:
2801 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 2802 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 2803 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2804 atomic_wr(wr)->rkey);
225c7b1f
RD		 2805 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2806
e622f2f4 2807 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 2808 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 2809
225c7b1f
RD		 2810 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2811 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 2812
2813 break;
2814
2815 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 2816 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2817 atomic_wr(wr)->rkey);
6fa8f719
VS		 2818 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2819
e622f2f4 2820 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 2821 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
2822
2823 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2824 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 2825
2826 break;
2827
2828 case IB_WR_RDMA_READ:
2829 case IB_WR_RDMA_WRITE:
2830 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 2831 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2832 rdma_wr(wr)->rkey);
225c7b1f
RD		 2833 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2834 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 2835 break;
95d04f07
RD		 2836
2837 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 2838 ctrl->srcrb_flags |=
2839 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2840 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2841 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
2842 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2843 break;
2844
1b2cd0fc
SG		 2845 case IB_WR_REG_MR:
2846 ctrl->srcrb_flags |=
2847 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2848 set_reg_seg(wqe, reg_wr(wr));
2849 wqe += sizeof(struct mlx4_wqe_fmr_seg);
2850 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
2851 break;
2852
225c7b1f
RD		 2853 default:
2854 /* No extra segments required for sends */
2855 break;
2856 }
2857 break;
2858
1ffeb2eb 2859 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 2860 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2861 ctrl, &seglen);
1ffeb2eb
JM		 2862 if (unlikely(err)) {
2863 *bad_wr = wr;
2864 goto out;
2865 }
2866 wqe += seglen;
2867 size += seglen / 16;
2868 break;
2869 case MLX4_IB_QPT_TUN_SMI:
2870 case MLX4_IB_QPT_TUN_GSI:
2871 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 2872 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 2873 /* set the forced-loopback bit in the data seg av */
2874 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2875 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2876 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2877 break;
2878 case MLX4_IB_QPT_UD:
e622f2f4 2879 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 2880 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2881 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 2882
2883 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 2884 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
2885 &lso_hdr_sz, &blh);
b832be1e
EC		 2886 if (unlikely(err)) {
2887 *bad_wr = wr;
2888 goto out;
2889 }
0fd7e1d8 2890 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 2891 wqe += seglen;
2892 size += seglen / 16;
2893 }
225c7b1f
RD		 2894 break;
2895
1ffeb2eb 2896 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 2897 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2898 ctrl, &seglen);
1ffeb2eb
JM		 2899 if (unlikely(err)) {
2900 *bad_wr = wr;
2901 goto out;
2902 }
2903 wqe += seglen;
2904 size += seglen / 16;
2905 /* to start tunnel header on a cache-line boundary */
2906 add_zero_len_inline(wqe);
2907 wqe += 16;
2908 size++;
e622f2f4 2909 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 2910 wqe += seglen;
2911 size += seglen / 16;
2912 break;
2913 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 2914 case MLX4_IB_QPT_PROXY_GSI:
2915 /* If we are tunneling special qps, this is a UD qp.
2916 * In this case we first add a UD segment targeting
2917 * the tunnel qp, and then add a header with address
2918 * information */
e622f2f4
CH		 2919 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
2920 ud_wr(wr),
97982f5a 2921 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 2922 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2923 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 2924 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 2925 wqe += seglen;
2926 size += seglen / 16;
2927 break;
2928
2929 case MLX4_IB_QPT_SMI:
2930 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 2931 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
2932 &seglen);
f438000f 2933 if (unlikely(err)) {
225c7b1f
RD		 2934 *bad_wr = wr;
2935 goto out;
2936 }
f438000f
RD		 2937 wqe += seglen;
2938 size += seglen / 16;
225c7b1f
RD		 2939 break;
2940
2941 default:
2942 break;
2943 }
2944
6e694ea3
JM		 2945 /*
2946 * Write data segments in reverse order, so as to
2947 * overwrite cacheline stamp last within each
2948 * cacheline. This avoids issues with WQE
2949 * prefetching.
2950 */
225c7b1f 2951
6e694ea3
JM		 2952 dseg = wqe;
2953 dseg += wr->num_sge - 1;
2954 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 2955
2956 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 2957 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2958 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2959 qp->mlx4_ib_qp_type &
2960 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 2961 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 2962 size += sizeof (struct mlx4_wqe_data_seg) / 16;
2963 }
2964
6e694ea3
JM		 2965 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2966 set_data_seg(dseg, wr->sg_list + i);
2967
0fd7e1d8
RD		 2968 /*
2969 * Possibly overwrite stamping in cacheline with LSO
2970 * segment only after making sure all data segments
2971 * are written.
2972 */
2973 wmb();
2974 *lso_wqe = lso_hdr_sz;
2975
225c7b1f
RD		 2976 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2977 MLX4_WQE_CTRL_FENCE : 0) | size;
2978
2979 /*
2980 * Make sure descriptor is fully written before
2981 * setting ownership bit (because HW can start
2982 * executing as soon as we do).
2983 */
2984 wmb();
2985
59b0ed12 2986 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 2987 *bad_wr = wr;
225c7b1f
RD		 2988 err = -EINVAL;
2989 goto out;
2990 }
2991
2992 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 2993 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 2994
ea54b10c
JM		 2995 stamp = ind + qp->sq_spare_wqes;
2996 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2997
0e6e7416
RD		 2998 /*
2999 * We can improve latency by not stamping the last
3000 * send queue WQE until after ringing the doorbell, so
3001 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 3002 *
3003 * Same optimization applies to padding with NOP wqe
3004 * in case of WQE shrinking (used to prevent wrap-around
3005 * in the middle of WR).
0e6e7416 3006 */
ea54b10c
JM		 3007 if (wr->next) {
3008 stamp_send_wqe(qp, stamp, size * 16);
3009 ind = pad_wraparound(qp, ind);
3010 }
225c7b1f
RD		 3011 }
3012
3013out:
3014 if (likely(nreq)) {
3015 qp->sq.head += nreq;
3016
3017 /*
3018 * Make sure that descriptors are written before
3019 * doorbell record.
3020 */
3021 wmb();
3022
3023 writel(qp->doorbell_qpn,
3024 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3025
3026 /*
3027 * Make sure doorbells don't leak out of SQ spinlock
3028 * and reach the HCA out of order.
3029 */
3030 mmiowb();
0e6e7416 3031
ea54b10c
JM		 3032 stamp_send_wqe(qp, stamp, size * 16);
3033
3034 ind = pad_wraparound(qp, ind);
3035 qp->sq_next_wqe = ind;
225c7b1f
RD		 3036 }
3037
96db0e03 3038 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3039
3040 return err;
3041}
3042
3043int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3044 struct ib_recv_wr **bad_wr)
3045{
3046 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3047 struct mlx4_wqe_data_seg *scat;
3048 unsigned long flags;
3049 int err = 0;
3050 int nreq;
3051 int ind;
1ffeb2eb 3052 int max_gs;
225c7b1f 3053 int i;
35f05dab 3054 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3055
1ffeb2eb 3056 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3057 spin_lock_irqsave(&qp->rq.lock, flags);
3058
35f05dab
YH		 3059 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3060 err = -EIO;
3061 *bad_wr = wr;
3062 nreq = 0;
3063 goto out;
3064 }
3065
0e6e7416 3066 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3067
3068 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3069 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3070 err = -ENOMEM;
3071 *bad_wr = wr;
3072 goto out;
3073 }
3074
3075 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3076 err = -EINVAL;
3077 *bad_wr = wr;
3078 goto out;
3079 }
3080
3081 scat = get_recv_wqe(qp, ind);
3082
1ffeb2eb
JM		 3083 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3084 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3085 ib_dma_sync_single_for_device(ibqp->device,
3086 qp->sqp_proxy_rcv[ind].map,
3087 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3088 DMA_FROM_DEVICE);
3089 scat->byte_count =
3090 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3091 /* use dma lkey from upper layer entry */
3092 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3093 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3094 scat++;
3095 max_gs--;
3096 }
3097
2242fa4f
RD		 3098 for (i = 0; i < wr->num_sge; ++i)
3099 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3100
1ffeb2eb 3101 if (i < max_gs) {
225c7b1f
RD		 3102 scat[i].byte_count = 0;
3103 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3104 scat[i].addr = 0;
3105 }
3106
3107 qp->rq.wrid[ind] = wr->wr_id;
3108
0e6e7416 3109 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3110 }
3111
3112out:
3113 if (likely(nreq)) {
3114 qp->rq.head += nreq;
3115
3116 /*
3117 * Make sure that descriptors are written before
3118 * doorbell record.
3119 */
3120 wmb();
3121
3122 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3123 }
3124
3125 spin_unlock_irqrestore(&qp->rq.lock, flags);
3126
3127 return err;
3128}
6a775e2b
JM		 3129
3130static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3131{
3132 switch (mlx4_state) {
3133 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3134 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3135 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3136 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3137 case MLX4_QP_STATE_SQ_DRAINING:
3138 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3139 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3140 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3141 default: return -1;
3142 }
3143}
3144
3145static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3146{
3147 switch (mlx4_mig_state) {
3148 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3149 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3150 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3151 default: return -1;
3152 }
3153}
3154
3155static int to_ib_qp_access_flags(int mlx4_flags)
3156{
3157 int ib_flags = 0;
3158
3159 if (mlx4_flags & MLX4_QP_BIT_RRE)
3160 ib_flags |= IB_ACCESS_REMOTE_READ;
3161 if (mlx4_flags & MLX4_QP_BIT_RWE)
3162 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3163 if (mlx4_flags & MLX4_QP_BIT_RAE)
3164 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3165
3166 return ib_flags;
3167}
3168
4c3eb3ca 3169static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
6a775e2b
JM		 3170 struct mlx4_qp_path *path)
3171{
4c3eb3ca
EC		 3172 struct mlx4_dev *dev = ibdev->dev;
3173 int is_eth;
3174
8fcea95a 3175 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 3176 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
3177
3178 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3179 return;
3180
4c3eb3ca
EC		 3181 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3182 IB_LINK_LAYER_ETHERNET;
3183 if (is_eth)
3184 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3185 ((path->sched_queue & 4) << 1);
3186 else
3187 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3188
6a775e2b 3189 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
6a775e2b
JM		 3190 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3191 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3192 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3193 if (ib_ah_attr->ah_flags) {
3194 ib_ah_attr->grh.sgid_index = path->mgid_index;
3195 ib_ah_attr->grh.hop_limit = path->hop_limit;
3196 ib_ah_attr->grh.traffic_class =
3197 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3198 ib_ah_attr->grh.flow_label =
586bb586 3199 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 3200 memcpy(ib_ah_attr->grh.dgid.raw,
3201 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3202 }
3203}
3204
3205int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3206 struct ib_qp_init_attr *qp_init_attr)
3207{
3208 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3209 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3210 struct mlx4_qp_context context;
3211 int mlx4_state;
0df67030
DB		 3212 int err = 0;
3213
3214 mutex_lock(&qp->mutex);
6a775e2b
JM		 3215
3216 if (qp->state == IB_QPS_RESET) {
3217 qp_attr->qp_state = IB_QPS_RESET;
3218 goto done;
3219 }
3220
3221 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3222 if (err) {
3223 err = -EINVAL;
3224 goto out;
3225 }
6a775e2b
JM		 3226
3227 mlx4_state = be32_to_cpu(context.flags) >> 28;
3228
0df67030
DB		 3229 qp->state = to_ib_qp_state(mlx4_state);
3230 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3231 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3232 qp_attr->path_mig_state =
3233 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3234 qp_attr->qkey = be32_to_cpu(context.qkey);
3235 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3236 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3237 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3238 qp_attr->qp_access_flags =
3239 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3240
3241 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4c3eb3ca
EC		 3242 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3243 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b
JM		 3244 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3245 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3246 }
3247
3248 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 3249 if (qp_attr->qp_state == IB_QPS_INIT)
3250 qp_attr->port_num = qp->port;
3251 else
3252 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 3253
3254 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3255 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3256
3257 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3258
3259 qp_attr->max_dest_rd_atomic =
3260 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3261 qp_attr->min_rnr_timer =
3262 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3263 qp_attr->timeout = context.pri_path.ackto >> 3;
3264 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3265 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3266 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3267
3268done:
3269 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 3270 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3271 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3272
6a775e2b 3273 if (!ibqp->uobject) {
7f5eb9bb
RD		 3274 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3275 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3276 } else {
3277 qp_attr->cap.max_send_wr = 0;
3278 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 3279 }
3280
7f5eb9bb
RD		 3281 /*
3282 * We don't support inline sends for kernel QPs (yet), and we
3283 * don't know what userspace's value should be.
3284 */
3285 qp_attr->cap.max_inline_data = 0;
3286
3287 qp_init_attr->cap = qp_attr->cap;
3288
521e575b
RL		 3289 qp_init_attr->create_flags = 0;
3290 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3291 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3292
3293 if (qp->flags & MLX4_IB_QP_LSO)
3294 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3295
c1c98501
MB		 3296 if (qp->flags & MLX4_IB_QP_NETIF)
3297 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3298
46db567d
DB		 3299 qp_init_attr->sq_sig_type =
3300 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3301 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3302
0df67030
DB		 3303out:
3304 mutex_unlock(&qp->mutex);
3305 return err;
6a775e2b
JM		 3306}
3307
Linux 6.x block layer and io_uring tree(s)