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IB/cma: Accept connection without a valid netdev on RoCE
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
5a0e3ad6 35#include <linux/slab.h>
fa417f7b 36#include <linux/netdevice.h>
ea54b10c 37
225c7b1f
RD		 38#include <rdma/ib_cache.h>
39#include <rdma/ib_pack.h>
4c3eb3ca 40#include <rdma/ib_addr.h>
1ffeb2eb 41#include <rdma/ib_mad.h>
225c7b1f 42
2f48485d 43#include <linux/mlx4/driver.h>
225c7b1f
RD		 44#include <linux/mlx4/qp.h>
45
46#include "mlx4_ib.h"
47#include "user.h"
48
35f05dab
YH		 49static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
50 struct mlx4_ib_cq *recv_cq);
51static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
52 struct mlx4_ib_cq *recv_cq);
53
225c7b1f
RD		 54enum {
55 MLX4_IB_ACK_REQ_FREQ = 8,
56};
57
58enum {
59 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 60 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
61 MLX4_IB_LINK_TYPE_IB = 0,
62 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 63};
64
65enum {
66 /*
fa417f7b 67 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 68 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
69 * tag. (LRH would only use 8 bytes, so Ethernet is the
70 * biggest case)
225c7b1f 71 */
4c3eb3ca 72 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 73 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 74};
75
fa417f7b
EC		 76enum {
77 MLX4_IB_IBOE_ETHERTYPE = 0x8915
78};
79
225c7b1f
RD		 80struct mlx4_ib_sqp {
81 struct mlx4_ib_qp qp;
82 int pkey_index;
83 u32 qkey;
84 u32 send_psn;
85 struct ib_ud_header ud_header;
86 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
87};
88
83904132 89enum {
417608c2
EC		 90 MLX4_IB_MIN_SQ_STRIDE = 6,
91 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 92};
93
3987a2d3
OG		 94enum {
95 MLX4_RAW_QP_MTU = 7,
96 MLX4_RAW_QP_MSGMAX = 31,
97};
98
297e0dad
MS		 99#ifndef ETH_ALEN
100#define ETH_ALEN 6
101#endif
297e0dad 102
225c7b1f 103static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
114 [IB_WR_FAST_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
6ff63e19 117 [IB_WR_BIND_MW] = cpu_to_be32(MLX4_OPCODE_BIND_MW),
225c7b1f
RD		 118};
119
120static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
121{
122 return container_of(mqp, struct mlx4_ib_sqp, qp);
123}
124
1ffeb2eb
JM		 125static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
126{
127 if (!mlx4_is_master(dev->dev))
128 return 0;
129
47605df9
JM		 130 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
131 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
132 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 133}
134
225c7b1f
RD		 135static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
136{
47605df9
JM		 137 int proxy_sqp = 0;
138 int real_sqp = 0;
139 int i;
140 /* PPF or Native -- real SQP */
141 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
142 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
143 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
144 if (real_sqp)
145 return 1;
146 /* VF or PF -- proxy SQP */
147 if (mlx4_is_mfunc(dev->dev)) {
148 for (i = 0; i < dev->dev->caps.num_ports; i++) {
149 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
150 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
151 proxy_sqp = 1;
152 break;
153 }
154 }
155 }
156 return proxy_sqp;
225c7b1f
RD		 157}
158
1ffeb2eb 159/* used for INIT/CLOSE port logic */
225c7b1f
RD		 160static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
161{
47605df9
JM		 162 int proxy_qp0 = 0;
163 int real_qp0 = 0;
164 int i;
165 /* PPF or Native -- real QP0 */
166 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
167 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
168 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
169 if (real_qp0)
170 return 1;
171 /* VF or PF -- proxy QP0 */
172 if (mlx4_is_mfunc(dev->dev)) {
173 for (i = 0; i < dev->dev->caps.num_ports; i++) {
174 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
175 proxy_qp0 = 1;
176 break;
177 }
178 }
179 }
180 return proxy_qp0;
225c7b1f
RD		 181}
182
183static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
184{
1c69fc2a 185 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 186}
187
188static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
189{
190 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
191}
192
193static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
194{
195 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
196}
197
0e6e7416
RD		 198/*
199 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 200 * first four bytes of every 64 byte chunk with
201 * 0x7FFFFFF | (invalid_ownership_value << 31).
202 *
203 * When the max work request size is less than or equal to the WQE
204 * basic block size, as an optimization, we can stamp all WQEs with
205 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 206 */
ea54b10c 207static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 208{
d2ae16d5 209 __be32 *wqe;
0e6e7416 210 int i;
ea54b10c
JM		 211 int s;
212 int ind;
213 void *buf;
214 __be32 stamp;
9670e553 215 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 216
ea54b10c 217 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 218 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 219 for (i = 0; i < s; i += 64) {
220 ind = (i >> qp->sq.wqe_shift) + n;
221 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
222 cpu_to_be32(0xffffffff);
223 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
224 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
225 *wqe = stamp;
226 }
227 } else {
9670e553
EC		 228 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
229 s = (ctrl->fence_size & 0x3f) << 4;
ea54b10c
JM		 230 for (i = 64; i < s; i += 64) {
231 wqe = buf + i;
d2ae16d5 232 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 233 }
234 }
235}
236
237static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
238{
239 struct mlx4_wqe_ctrl_seg *ctrl;
240 struct mlx4_wqe_inline_seg *inl;
241 void *wqe;
242 int s;
243
244 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
245 s = sizeof(struct mlx4_wqe_ctrl_seg);
246
247 if (qp->ibqp.qp_type == IB_QPT_UD) {
248 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
249 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
250 memset(dgram, 0, sizeof *dgram);
251 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
252 s += sizeof(struct mlx4_wqe_datagram_seg);
253 }
254
255 /* Pad the remainder of the WQE with an inline data segment. */
256 if (size > s) {
257 inl = wqe + s;
258 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
259 }
260 ctrl->srcrb_flags = 0;
261 ctrl->fence_size = size / 16;
262 /*
263 * Make sure descriptor is fully written before setting ownership bit
264 * (because HW can start executing as soon as we do).
265 */
266 wmb();
267
268 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
269 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 270
ea54b10c
JM		 271 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
272}
273
274/* Post NOP WQE to prevent wrap-around in the middle of WR */
275static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
276{
277 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
278 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
279 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
280 ind += s;
281 }
282 return ind;
0e6e7416
RD		 283}
284
225c7b1f
RD		 285static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
286{
287 struct ib_event event;
288 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
289
290 if (type == MLX4_EVENT_TYPE_PATH_MIG)
291 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
292
293 if (ibqp->event_handler) {
294 event.device = ibqp->device;
295 event.element.qp = ibqp;
296 switch (type) {
297 case MLX4_EVENT_TYPE_PATH_MIG:
298 event.event = IB_EVENT_PATH_MIG;
299 break;
300 case MLX4_EVENT_TYPE_COMM_EST:
301 event.event = IB_EVENT_COMM_EST;
302 break;
303 case MLX4_EVENT_TYPE_SQ_DRAINED:
304 event.event = IB_EVENT_SQ_DRAINED;
305 break;
306 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
307 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
308 break;
309 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
310 event.event = IB_EVENT_QP_FATAL;
311 break;
312 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
313 event.event = IB_EVENT_PATH_MIG_ERR;
314 break;
315 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
316 event.event = IB_EVENT_QP_REQ_ERR;
317 break;
318 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
319 event.event = IB_EVENT_QP_ACCESS_ERR;
320 break;
321 default:
987c8f8f 322 pr_warn("Unexpected event type %d "
225c7b1f
RD		 323 "on QP %06x\n", type, qp->qpn);
324 return;
325 }
326
327 ibqp->event_handler(&event, ibqp->qp_context);
328 }
329}
330
1ffeb2eb 331static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 332{
333 /*
334 * UD WQEs must have a datagram segment.
335 * RC and UC WQEs might have a remote address segment.
336 * MLX WQEs need two extra inline data segments (for the UD
337 * header and space for the ICRC).
338 */
339 switch (type) {
1ffeb2eb 340 case MLX4_IB_QPT_UD:
225c7b1f 341 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 342 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 343 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 344 case MLX4_IB_QPT_PROXY_SMI_OWNER:
345 case MLX4_IB_QPT_PROXY_SMI:
346 case MLX4_IB_QPT_PROXY_GSI:
347 return sizeof (struct mlx4_wqe_ctrl_seg) +
348 sizeof (struct mlx4_wqe_datagram_seg) + 64;
349 case MLX4_IB_QPT_TUN_SMI_OWNER:
350 case MLX4_IB_QPT_TUN_GSI:
351 return sizeof (struct mlx4_wqe_ctrl_seg) +
352 sizeof (struct mlx4_wqe_datagram_seg);
353
354 case MLX4_IB_QPT_UC:
225c7b1f
RD		 355 return sizeof (struct mlx4_wqe_ctrl_seg) +
356 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 357 case MLX4_IB_QPT_RC:
225c7b1f
RD		 358 return sizeof (struct mlx4_wqe_ctrl_seg) +
359 sizeof (struct mlx4_wqe_atomic_seg) +
360 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 361 case MLX4_IB_QPT_SMI:
362 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 363 return sizeof (struct mlx4_wqe_ctrl_seg) +
364 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 365 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
366 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 367 sizeof (struct mlx4_wqe_inline_seg),
368 sizeof (struct mlx4_wqe_data_seg)) +
369 ALIGN(4 +
370 sizeof (struct mlx4_wqe_inline_seg),
371 sizeof (struct mlx4_wqe_data_seg));
372 default:
373 return sizeof (struct mlx4_wqe_ctrl_seg);
374 }
375}
376
2446304d 377static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
0a1405da 378 int is_user, int has_rq, struct mlx4_ib_qp *qp)
225c7b1f 379{
2446304d 380 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 381 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
382 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 383 return -EINVAL;
384
0a1405da 385 if (!has_rq) {
a4cd7ed8
RD		 386 if (cap->max_recv_wr)
387 return -EINVAL;
2446304d 388
0e6e7416 389 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 390 } else {
391 /* HW requires >= 1 RQ entry with >= 1 gather entry */
392 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
393 return -EINVAL;
394
0e6e7416 395 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 396 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 397 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
398 }
2446304d 399
fc2d0044
SG		 400 /* leave userspace return values as they were, so as not to break ABI */
401 if (is_user) {
402 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
403 cap->max_recv_sge = qp->rq.max_gs;
404 } else {
405 cap->max_recv_wr = qp->rq.max_post =
406 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
407 cap->max_recv_sge = min(qp->rq.max_gs,
408 min(dev->dev->caps.max_sq_sg,
409 dev->dev->caps.max_rq_sg));
410 }
2446304d
EC		 411
412 return 0;
413}
414
415static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
1ffeb2eb 416 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 417{
ea54b10c
JM		 418 int s;
419
2446304d 420 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 421 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
422 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 423 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 424 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
425 return -EINVAL;
426
427 /*
428 * For MLX transport we need 2 extra S/G entries:
429 * one for the header and one for the checksum at the end
430 */
1ffeb2eb
JM		 431 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
432 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 433 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
434 return -EINVAL;
435
ea54b10c
JM		 436 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
437 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 438 send_wqe_overhead(type, qp->flags);
225c7b1f 439
cd155c1c
RD		 440 if (s > dev->dev->caps.max_sq_desc_sz)
441 return -EINVAL;
442
0e6e7416 443 /*
ea54b10c
JM		 444 * Hermon supports shrinking WQEs, such that a single work
445 * request can include multiple units of 1 << wqe_shift. This
446 * way, work requests can differ in size, and do not have to
447 * be a power of 2 in size, saving memory and speeding up send
448 * WR posting. Unfortunately, if we do this then the
449 * wqe_index field in CQEs can't be used to look up the WR ID
450 * anymore, so we do this only if selective signaling is off.
451 *
452 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 453 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 454 * constant-sized WRs to make sure a WR is always fully within
455 * a single page-sized chunk.
456 *
457 * Finally, we use NOP work requests to pad the end of the
458 * work queue, to avoid wrap-around in the middle of WR. We
459 * set NEC bit to avoid getting completions with error for
460 * these NOP WRs, but since NEC is only supported starting
461 * with firmware 2.2.232, we use constant-sized WRs for older
462 * firmware.
463 *
464 * And, since MLX QPs only support SEND, we use constant-sized
465 * WRs in this case.
466 *
467 * We look for the smallest value of wqe_shift such that the
468 * resulting number of wqes does not exceed device
469 * capabilities.
470 *
471 * We set WQE size to at least 64 bytes, this way stamping
472 * invalidates each WQE.
0e6e7416 473 */
ea54b10c
JM		 474 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
475 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 476 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
477 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
478 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 479 qp->sq.wqe_shift = ilog2(64);
480 else
481 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
482
483 for (;;) {
ea54b10c
JM		 484 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
485
486 /*
487 * We need to leave 2 KB + 1 WR of headroom in the SQ to
488 * allow HW to prefetch.
489 */
490 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
491 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
492 qp->sq_max_wqes_per_wr +
493 qp->sq_spare_wqes);
494
495 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
496 break;
497
498 if (qp->sq_max_wqes_per_wr <= 1)
499 return -EINVAL;
500
501 ++qp->sq.wqe_shift;
502 }
503
cd155c1c
RD		 504 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
505 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 506 send_wqe_overhead(type, qp->flags)) /
507 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 508
509 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
510 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 511 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
512 qp->rq.offset = 0;
0e6e7416 513 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 514 } else {
0e6e7416 515 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 516 qp->sq.offset = 0;
517 }
518
ea54b10c
JM		 519 cap->max_send_wr = qp->sq.max_post =
520 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 521 cap->max_send_sge = min(qp->sq.max_gs,
522 min(dev->dev->caps.max_sq_sg,
523 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 524 /* We don't support inline sends for kernel QPs (yet) */
525 cap->max_inline_data = 0;
225c7b1f
RD		 526
527 return 0;
528}
529
83904132
JM		 530static int set_user_sq_size(struct mlx4_ib_dev *dev,
531 struct mlx4_ib_qp *qp,
2446304d
EC		 532 struct mlx4_ib_create_qp *ucmd)
533{
83904132
JM		 534 /* Sanity check SQ size before proceeding */
535 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
536 ucmd->log_sq_stride >
537 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
538 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
539 return -EINVAL;
540
0e6e7416 541 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 542 qp->sq.wqe_shift = ucmd->log_sq_stride;
543
0e6e7416
RD		 544 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
545 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 546
547 return 0;
548}
549
1ffeb2eb
JM		 550static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
551{
552 int i;
553
554 qp->sqp_proxy_rcv =
555 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
556 GFP_KERNEL);
557 if (!qp->sqp_proxy_rcv)
558 return -ENOMEM;
559 for (i = 0; i < qp->rq.wqe_cnt; i++) {
560 qp->sqp_proxy_rcv[i].addr =
561 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
562 GFP_KERNEL);
563 if (!qp->sqp_proxy_rcv[i].addr)
564 goto err;
565 qp->sqp_proxy_rcv[i].map =
566 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
567 sizeof (struct mlx4_ib_proxy_sqp_hdr),
568 DMA_FROM_DEVICE);
cc47d369
SO		 569 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
570 kfree(qp->sqp_proxy_rcv[i].addr);
571 goto err;
572 }
1ffeb2eb
JM		 573 }
574 return 0;
575
576err:
577 while (i > 0) {
578 --i;
579 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
580 sizeof (struct mlx4_ib_proxy_sqp_hdr),
581 DMA_FROM_DEVICE);
582 kfree(qp->sqp_proxy_rcv[i].addr);
583 }
584 kfree(qp->sqp_proxy_rcv);
585 qp->sqp_proxy_rcv = NULL;
586 return -ENOMEM;
587}
588
589static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
590{
591 int i;
592
593 for (i = 0; i < qp->rq.wqe_cnt; i++) {
594 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
595 sizeof (struct mlx4_ib_proxy_sqp_hdr),
596 DMA_FROM_DEVICE);
597 kfree(qp->sqp_proxy_rcv[i].addr);
598 }
599 kfree(qp->sqp_proxy_rcv);
600}
601
0a1405da
SH		 602static int qp_has_rq(struct ib_qp_init_attr *attr)
603{
604 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
605 return 0;
606
607 return !attr->srq;
608}
609
99ec41d0
JM		 610static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
611{
612 int i;
613 for (i = 0; i < dev->caps.num_ports; i++) {
614 if (qpn == dev->caps.qp0_proxy[i])
615 return !!dev->caps.qp0_qkey[i];
616 }
617 return 0;
618}
619
225c7b1f
RD		 620static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
621 struct ib_qp_init_attr *init_attr,
40f2287b
JK		 622 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
623 gfp_t gfp)
225c7b1f 624{
a3cdcbfa 625 int qpn;
225c7b1f 626 int err;
1ffeb2eb
JM		 627 struct mlx4_ib_sqp *sqp;
628 struct mlx4_ib_qp *qp;
629 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 630 struct mlx4_ib_cq *mcq;
631 unsigned long flags;
1ffeb2eb
JM		 632
633 /* When tunneling special qps, we use a plain UD qp */
634 if (sqpn) {
635 if (mlx4_is_mfunc(dev->dev) &&
636 (!mlx4_is_master(dev->dev) ||
637 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
638 if (init_attr->qp_type == IB_QPT_GSI)
639 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 640 else {
641 if (mlx4_is_master(dev->dev) ||
642 qp0_enabled_vf(dev->dev, sqpn))
643 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
644 else
645 qp_type = MLX4_IB_QPT_PROXY_SMI;
646 }
1ffeb2eb
JM		 647 }
648 qpn = sqpn;
649 /* add extra sg entry for tunneling */
650 init_attr->cap.max_recv_sge++;
651 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
652 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
653 container_of(init_attr,
654 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
655 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
656 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
657 !mlx4_is_master(dev->dev))
658 return -EINVAL;
659 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
660 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 661 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
662 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
663 tnl_init->port))
1ffeb2eb
JM		 664 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
665 else
666 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 667 /* we are definitely in the PPF here, since we are creating
668 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
669 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
670 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 671 sqpn = qpn;
672 }
673
674 if (!*caller_qp) {
675 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
676 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
677 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6fcd8d0d 678 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
1ffeb2eb
JM		 679 if (!sqp)
680 return -ENOMEM;
681 qp = &sqp->qp;
2f5bb473
JM		 682 qp->pri.vid = 0xFFFF;
683 qp->alt.vid = 0xFFFF;
1ffeb2eb 684 } else {
6fcd8d0d 685 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
1ffeb2eb
JM		 686 if (!qp)
687 return -ENOMEM;
2f5bb473
JM		 688 qp->pri.vid = 0xFFFF;
689 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 690 }
691 } else
692 qp = *caller_qp;
693
694 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 695
696 mutex_init(&qp->mutex);
697 spin_lock_init(&qp->sq.lock);
698 spin_lock_init(&qp->rq.lock);
fa417f7b 699 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 700 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 701
702 qp->state = IB_QPS_RESET;
ea54b10c
JM		 703 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
704 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 705
0a1405da 706 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
225c7b1f
RD		 707 if (err)
708 goto err;
709
710 if (pd->uobject) {
711 struct mlx4_ib_create_qp ucmd;
712
713 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
714 err = -EFAULT;
715 goto err;
716 }
717
0e6e7416
RD		 718 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
719
83904132 720 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 721 if (err)
722 goto err;
723
225c7b1f 724 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 725 qp->buf_size, 0, 0);
225c7b1f
RD		 726 if (IS_ERR(qp->umem)) {
727 err = PTR_ERR(qp->umem);
728 goto err;
729 }
730
731 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
732 ilog2(qp->umem->page_size), &qp->mtt);
733 if (err)
734 goto err_buf;
735
736 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
737 if (err)
738 goto err_mtt;
739
0a1405da 740 if (qp_has_rq(init_attr)) {
02d89b87
RD		 741 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
742 ucmd.db_addr, &qp->db);
743 if (err)
744 goto err_mtt;
745 }
225c7b1f 746 } else {
0e6e7416
RD		 747 qp->sq_no_prefetch = 0;
748
521e575b
RL		 749 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
750 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
751
b832be1e
EC		 752 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
753 qp->flags |= MLX4_IB_QP_LSO;
754
c1c98501
MB		 755 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
756 if (dev->steering_support ==
757 MLX4_STEERING_MODE_DEVICE_MANAGED)
758 qp->flags |= MLX4_IB_QP_NETIF;
759 else
760 goto err;
761 }
762
1ffeb2eb 763 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 764 if (err)
765 goto err;
766
0a1405da 767 if (qp_has_rq(init_attr)) {
40f2287b 768 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
02d89b87
RD		 769 if (err)
770 goto err;
225c7b1f 771
02d89b87
RD		 772 *qp->db.db = 0;
773 }
225c7b1f 774
40f2287b 775 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
225c7b1f
RD		 776 err = -ENOMEM;
777 goto err_db;
778 }
779
780 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
781 &qp->mtt);
782 if (err)
783 goto err_buf;
784
40f2287b 785 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
225c7b1f
RD		 786 if (err)
787 goto err_mtt;
788
40f2287b
JK		 789 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), gfp);
790 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), gfp);
225c7b1f
RD		 791 if (!qp->sq.wrid || !qp->rq.wrid) {
792 err = -ENOMEM;
793 goto err_wrid;
794 }
225c7b1f
RD		 795 }
796
a3cdcbfa 797 if (sqpn) {
1ffeb2eb
JM		 798 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
799 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
800 if (alloc_proxy_bufs(pd->device, qp)) {
801 err = -ENOMEM;
802 goto err_wrid;
803 }
804 }
a3cdcbfa 805 } else {
ddae0349
EE		 806 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
807 * otherwise, the WQE BlueFlame setup flow wrongly causes
808 * VLAN insertion. */
3987a2d3 809 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 810 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 811 (init_attr->cap.max_send_wr ?
812 MLX4_RESERVE_ETH_BF_QP : 0) |
813 (init_attr->cap.max_recv_wr ?
814 MLX4_RESERVE_A0_QP : 0));
3987a2d3 815 else
c1c98501
MB		 816 if (qp->flags & MLX4_IB_QP_NETIF)
817 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
818 else
819 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
ddae0349 820 &qpn, 0);
a3cdcbfa 821 if (err)
1ffeb2eb 822 goto err_proxy;
a3cdcbfa
YP		 823 }
824
40f2287b 825 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
225c7b1f 826 if (err)
a3cdcbfa 827 goto err_qpn;
225c7b1f 828
0a1405da
SH		 829 if (init_attr->qp_type == IB_QPT_XRC_TGT)
830 qp->mqp.qpn |= (1 << 23);
831
225c7b1f
RD		 832 /*
833 * Hardware wants QPN written in big-endian order (after
834 * shifting) for send doorbell. Precompute this value to save
835 * a little bit when posting sends.
836 */
837 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
838
225c7b1f 839 qp->mqp.event = mlx4_ib_qp_event;
1ffeb2eb
JM		 840 if (!*caller_qp)
841 *caller_qp = qp;
35f05dab
YH		 842
843 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
844 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
845 to_mcq(init_attr->recv_cq));
846 /* Maintain device to QPs access, needed for further handling
847 * via reset flow
848 */
849 list_add_tail(&qp->qps_list, &dev->qp_list);
850 /* Maintain CQ to QPs access, needed for further handling
851 * via reset flow
852 */
853 mcq = to_mcq(init_attr->send_cq);
854 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
855 mcq = to_mcq(init_attr->recv_cq);
856 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
857 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
858 to_mcq(init_attr->recv_cq));
859 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 860 return 0;
861
a3cdcbfa 862err_qpn:
c1c98501
MB		 863 if (!sqpn) {
864 if (qp->flags & MLX4_IB_QP_NETIF)
865 mlx4_ib_steer_qp_free(dev, qpn, 1);
866 else
867 mlx4_qp_release_range(dev->dev, qpn, 1);
868 }
1ffeb2eb
JM		 869err_proxy:
870 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
871 free_proxy_bufs(pd->device, qp);
225c7b1f 872err_wrid:
23f1b384 873 if (pd->uobject) {
0a1405da
SH		 874 if (qp_has_rq(init_attr))
875 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 876 } else {
225c7b1f
RD		 877 kfree(qp->sq.wrid);
878 kfree(qp->rq.wrid);
879 }
880
881err_mtt:
882 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
883
884err_buf:
885 if (pd->uobject)
886 ib_umem_release(qp->umem);
887 else
888 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
889
890err_db:
0a1405da 891 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 892 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 893
894err:
1ffeb2eb
JM		 895 if (!*caller_qp)
896 kfree(qp);
225c7b1f
RD		 897 return err;
898}
899
900static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
901{
902 switch (state) {
903 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
904 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
905 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
906 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
907 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
908 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
909 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
910 default: return -1;
911 }
912}
913
914static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 915 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 916{
338a8fad 917 if (send_cq == recv_cq) {
35f05dab 918 spin_lock(&send_cq->lock);
338a8fad
RD		 919 __acquire(&recv_cq->lock);
920 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 921 spin_lock(&send_cq->lock);
225c7b1f
RD		 922 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
923 } else {
35f05dab 924 spin_lock(&recv_cq->lock);
225c7b1f
RD		 925 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
926 }
927}
928
929static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 930 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 931{
338a8fad
RD		 932 if (send_cq == recv_cq) {
933 __release(&recv_cq->lock);
35f05dab 934 spin_unlock(&send_cq->lock);
338a8fad 935 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 936 spin_unlock(&recv_cq->lock);
35f05dab 937 spin_unlock(&send_cq->lock);
225c7b1f
RD		 938 } else {
939 spin_unlock(&send_cq->lock);
35f05dab 940 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 941 }
942}
943
fa417f7b
EC		 944static void del_gid_entries(struct mlx4_ib_qp *qp)
945{
946 struct mlx4_ib_gid_entry *ge, *tmp;
947
948 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
949 list_del(&ge->list);
950 kfree(ge);
951 }
952}
953
0a1405da
SH		 954static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
955{
956 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
957 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
958 else
959 return to_mpd(qp->ibqp.pd);
960}
961
962static void get_cqs(struct mlx4_ib_qp *qp,
963 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
964{
965 switch (qp->ibqp.qp_type) {
966 case IB_QPT_XRC_TGT:
967 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
968 *recv_cq = *send_cq;
969 break;
970 case IB_QPT_XRC_INI:
971 *send_cq = to_mcq(qp->ibqp.send_cq);
972 *recv_cq = *send_cq;
973 break;
974 default:
975 *send_cq = to_mcq(qp->ibqp.send_cq);
976 *recv_cq = to_mcq(qp->ibqp.recv_cq);
977 break;
978 }
979}
980
225c7b1f
RD		 981static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
982 int is_user)
983{
984 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 985 unsigned long flags;
225c7b1f 986
2f5bb473 987 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 988 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
989 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 990 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 991 qp->mqp.qpn);
25476b02 992 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 993 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
994 qp->pri.smac = 0;
25476b02 995 qp->pri.smac_port = 0;
2f5bb473
JM		 996 }
997 if (qp->alt.smac) {
998 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
999 qp->alt.smac = 0;
1000 }
1001 if (qp->pri.vid < 0x1000) {
1002 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1003 qp->pri.vid = 0xFFFF;
1004 qp->pri.candidate_vid = 0xFFFF;
1005 qp->pri.update_vid = 0;
1006 }
1007 if (qp->alt.vid < 0x1000) {
1008 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1009 qp->alt.vid = 0xFFFF;
1010 qp->alt.candidate_vid = 0xFFFF;
1011 qp->alt.update_vid = 0;
1012 }
1013 }
225c7b1f 1014
0a1405da 1015 get_cqs(qp, &send_cq, &recv_cq);
225c7b1f 1016
35f05dab 1017 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1018 mlx4_ib_lock_cqs(send_cq, recv_cq);
1019
35f05dab
YH		 1020 /* del from lists under both locks above to protect reset flow paths */
1021 list_del(&qp->qps_list);
1022 list_del(&qp->cq_send_list);
1023 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1024 if (!is_user) {
1025 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1026 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1027 if (send_cq != recv_cq)
1028 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1029 }
1030
1031 mlx4_qp_remove(dev->dev, &qp->mqp);
1032
1033 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1034 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1035
1036 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1037
c1c98501
MB		 1038 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1039 if (qp->flags & MLX4_IB_QP_NETIF)
1040 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1041 else
1042 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1043 }
a3cdcbfa 1044
225c7b1f
RD		 1045 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1046
1047 if (is_user) {
0a1405da 1048 if (qp->rq.wqe_cnt)
02d89b87
RD		 1049 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1050 &qp->db);
225c7b1f
RD		 1051 ib_umem_release(qp->umem);
1052 } else {
1053 kfree(qp->sq.wrid);
1054 kfree(qp->rq.wrid);
1ffeb2eb
JM		 1055 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1056 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1057 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1058 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1059 if (qp->rq.wqe_cnt)
6296883c 1060 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1061 }
fa417f7b
EC		 1062
1063 del_gid_entries(qp);
225c7b1f
RD		 1064}
1065
47605df9
JM		 1066static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1067{
1068 /* Native or PPF */
1069 if (!mlx4_is_mfunc(dev->dev) ||
1070 (mlx4_is_master(dev->dev) &&
1071 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1072 return dev->dev->phys_caps.base_sqpn +
1073 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1074 attr->port_num - 1;
1075 }
1076 /* PF or VF -- creating proxies */
1077 if (attr->qp_type == IB_QPT_SMI)
1078 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1079 else
1080 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1081}
1082
225c7b1f
RD		 1083struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1084 struct ib_qp_init_attr *init_attr,
1085 struct ib_udata *udata)
1086{
1ffeb2eb 1087 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1088 int err;
0a1405da 1089 u16 xrcdn = 0;
40f2287b 1090 gfp_t gfp;
225c7b1f 1091
40f2287b
JK		 1092 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1093 GFP_NOIO : GFP_KERNEL;
521e575b 1094 /*
1ffeb2eb
JM		 1095 * We only support LSO, vendor flag1, and multicast loopback blocking,
1096 * and only for kernel UD QPs.
521e575b 1097 */
1ffeb2eb
JM		 1098 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1099 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1100 MLX4_IB_SRIOV_TUNNEL_QP |
1101 MLX4_IB_SRIOV_SQP |
40f2287b
JK		 1102 MLX4_IB_QP_NETIF |
1103 MLX4_IB_QP_CREATE_USE_GFP_NOIO))
b832be1e 1104 return ERR_PTR(-EINVAL);
521e575b 1105
c1c98501
MB		 1106 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1107 if (init_attr->qp_type != IB_QPT_UD)
1108 return ERR_PTR(-EINVAL);
1109 }
1110
521e575b 1111 if (init_attr->create_flags &&
1ffeb2eb 1112 (udata ||
40f2287b 1113 ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | MLX4_IB_QP_CREATE_USE_GFP_NOIO)) &&
1ffeb2eb
JM		 1114 init_attr->qp_type != IB_QPT_UD) ||
1115 ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1116 init_attr->qp_type > IB_QPT_GSI)))
b846f25a
EC		 1117 return ERR_PTR(-EINVAL);
1118
225c7b1f 1119 switch (init_attr->qp_type) {
0a1405da
SH		 1120 case IB_QPT_XRC_TGT:
1121 pd = to_mxrcd(init_attr->xrcd)->pd;
1122 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1123 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1124 /* fall through */
1125 case IB_QPT_XRC_INI:
1126 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1127 return ERR_PTR(-ENOSYS);
1128 init_attr->recv_cq = init_attr->send_cq;
1129 /* fall through */
225c7b1f
RD		 1130 case IB_QPT_RC:
1131 case IB_QPT_UC:
3987a2d3 1132 case IB_QPT_RAW_PACKET:
40f2287b 1133 qp = kzalloc(sizeof *qp, gfp);
225c7b1f
RD		 1134 if (!qp)
1135 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1136 qp->pri.vid = 0xFFFF;
1137 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1138 /* fall through */
1139 case IB_QPT_UD:
1140 {
1141 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
40f2287b 1142 udata, 0, &qp, gfp);
1ffeb2eb 1143 if (err)
225c7b1f 1144 return ERR_PTR(err);
225c7b1f
RD		 1145
1146 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1147 qp->xrcdn = xrcdn;
225c7b1f
RD		 1148
1149 break;
1150 }
1151 case IB_QPT_SMI:
1152 case IB_QPT_GSI:
1153 {
1154 /* Userspace is not allowed to create special QPs: */
0a1405da 1155 if (udata)
225c7b1f
RD		 1156 return ERR_PTR(-EINVAL);
1157
0a1405da 1158 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
47605df9 1159 get_sqp_num(to_mdev(pd->device), init_attr),
40f2287b 1160 &qp, gfp);
1ffeb2eb 1161 if (err)
225c7b1f 1162 return ERR_PTR(err);
225c7b1f
RD		 1163
1164 qp->port = init_attr->port_num;
1165 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1166
1167 break;
1168 }
1169 default:
1170 /* Don't support raw QPs */
1171 return ERR_PTR(-EINVAL);
1172 }
1173
1174 return &qp->ibqp;
1175}
1176
1177int mlx4_ib_destroy_qp(struct ib_qp *qp)
1178{
1179 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1180 struct mlx4_ib_qp *mqp = to_mqp(qp);
0a1405da 1181 struct mlx4_ib_pd *pd;
225c7b1f
RD		 1182
1183 if (is_qp0(dev, mqp))
1184 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1185
9433c188
MB		 1186 if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1187 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1188 dev->qp1_proxy[mqp->port - 1] = NULL;
1189 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1190 }
1191
0a1405da
SH		 1192 pd = get_pd(mqp);
1193 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
225c7b1f
RD		 1194
1195 if (is_sqp(dev, mqp))
1196 kfree(to_msqp(mqp));
1197 else
1198 kfree(mqp);
1199
1200 return 0;
1201}
1202
1ffeb2eb 1203static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1204{
1205 switch (type) {
1ffeb2eb
JM		 1206 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1207 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1208 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1209 case MLX4_IB_QPT_XRC_INI:
1210 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1211 case MLX4_IB_QPT_SMI:
1212 case MLX4_IB_QPT_GSI:
1213 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1214
1215 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1216 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1217 MLX4_QP_ST_MLX : -1);
1218 case MLX4_IB_QPT_PROXY_SMI:
1219 case MLX4_IB_QPT_TUN_SMI:
1220 case MLX4_IB_QPT_PROXY_GSI:
1221 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1222 MLX4_QP_ST_UD : -1);
1223 default: return -1;
225c7b1f
RD		 1224 }
1225}
1226
65adfa91 1227static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1228 int attr_mask)
1229{
1230 u8 dest_rd_atomic;
1231 u32 access_flags;
1232 u32 hw_access_flags = 0;
1233
1234 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1235 dest_rd_atomic = attr->max_dest_rd_atomic;
1236 else
1237 dest_rd_atomic = qp->resp_depth;
1238
1239 if (attr_mask & IB_QP_ACCESS_FLAGS)
1240 access_flags = attr->qp_access_flags;
1241 else
1242 access_flags = qp->atomic_rd_en;
1243
1244 if (!dest_rd_atomic)
1245 access_flags &= IB_ACCESS_REMOTE_WRITE;
1246
1247 if (access_flags & IB_ACCESS_REMOTE_READ)
1248 hw_access_flags |= MLX4_QP_BIT_RRE;
1249 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1250 hw_access_flags |= MLX4_QP_BIT_RAE;
1251 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1252 hw_access_flags |= MLX4_QP_BIT_RWE;
1253
1254 return cpu_to_be32(hw_access_flags);
1255}
1256
65adfa91 1257static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1258 int attr_mask)
1259{
1260 if (attr_mask & IB_QP_PKEY_INDEX)
1261 sqp->pkey_index = attr->pkey_index;
1262 if (attr_mask & IB_QP_QKEY)
1263 sqp->qkey = attr->qkey;
1264 if (attr_mask & IB_QP_SQ_PSN)
1265 sqp->send_psn = attr->sq_psn;
1266}
1267
1268static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1269{
1270 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1271}
1272
297e0dad
MS		 1273static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1274 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1275 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1276{
fa417f7b
EC		 1277 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1278 IB_LINK_LAYER_ETHERNET;
4c3eb3ca 1279 int vidx;
297e0dad 1280 int smac_index;
2f5bb473 1281 int err;
297e0dad 1282
fa417f7b 1283
225c7b1f
RD		 1284 path->grh_mylmc = ah->src_path_bits & 0x7f;
1285 path->rlid = cpu_to_be16(ah->dlid);
1286 if (ah->static_rate) {
1287 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1288 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1289 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1290 --path->static_rate;
1291 } else
1292 path->static_rate = 0;
225c7b1f
RD		 1293
1294 if (ah->ah_flags & IB_AH_GRH) {
5070cd22
MS		 1295 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1296 port,
1297 ah->grh.sgid_index);
1298
1299 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1300 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1301 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1302 return -1;
1303 }
1304
1305 path->grh_mylmc |= 1 << 7;
5070cd22 1306 path->mgid_index = real_sgid_index;
225c7b1f
RD		 1307 path->hop_limit = ah->grh.hop_limit;
1308 path->tclass_flowlabel =
1309 cpu_to_be32((ah->grh.traffic_class << 20) |
1310 (ah->grh.flow_label));
1311 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1312 }
1313
fa417f7b
EC		 1314 if (is_eth) {
1315 if (!(ah->ah_flags & IB_AH_GRH))
1316 return -1;
1317
2f5bb473
JM		 1318 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1319 ((port - 1) << 6) | ((ah->sl & 7) << 3);
4c3eb3ca 1320
297e0dad 1321 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1322 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1323 if (smac_info->vid < 0x1000) {
1324 /* both valid vlan ids */
1325 if (smac_info->vid != vlan_tag) {
1326 /* different VIDs. unreg old and reg new */
1327 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1328 if (err)
1329 return err;
1330 smac_info->candidate_vid = vlan_tag;
1331 smac_info->candidate_vlan_index = vidx;
1332 smac_info->candidate_vlan_port = port;
1333 smac_info->update_vid = 1;
1334 path->vlan_index = vidx;
1335 } else {
1336 path->vlan_index = smac_info->vlan_index;
1337 }
1338 } else {
1339 /* no current vlan tag in qp */
1340 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1341 if (err)
1342 return err;
1343 smac_info->candidate_vid = vlan_tag;
1344 smac_info->candidate_vlan_index = vidx;
1345 smac_info->candidate_vlan_port = port;
1346 smac_info->update_vid = 1;
1347 path->vlan_index = vidx;
1348 }
297e0dad 1349 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1350 path->fl = 1 << 6;
1351 } else {
1352 /* have current vlan tag. unregister it at modify-qp success */
1353 if (smac_info->vid < 0x1000) {
1354 smac_info->candidate_vid = 0xFFFF;
1355 smac_info->update_vid = 1;
1356 }
4c3eb3ca 1357 }
2f5bb473
JM		 1358
1359 /* get smac_index for RoCE use.
1360 * If no smac was yet assigned, register one.
1361 * If one was already assigned, but the new mac differs,
1362 * unregister the old one and register the new one.
1363 */
25476b02
JM		 1364 if ((!smac_info->smac && !smac_info->smac_port) ||
1365 smac_info->smac != smac) {
2f5bb473
JM		 1366 /* register candidate now, unreg if needed, after success */
1367 smac_index = mlx4_register_mac(dev->dev, port, smac);
1368 if (smac_index >= 0) {
1369 smac_info->candidate_smac_index = smac_index;
1370 smac_info->candidate_smac = smac;
1371 smac_info->candidate_smac_port = port;
1372 } else {
1373 return -EINVAL;
1374 }
1375 } else {
1376 smac_index = smac_info->smac_index;
1377 }
1378
1379 memcpy(path->dmac, ah->dmac, 6);
1380 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1381 /* put MAC table smac index for IBoE */
1382 path->grh_mylmc = (u8) (smac_index) | 0x80;
1383 } else {
4c3eb3ca
EC		 1384 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1385 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
2f5bb473 1386 }
fa417f7b 1387
225c7b1f
RD		 1388 return 0;
1389}
1390
297e0dad
MS		 1391static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1392 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1393 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1394 struct mlx4_qp_path *path, u8 port)
1395{
1396 return _mlx4_set_path(dev, &qp->ah_attr,
1397 mlx4_mac_to_u64((u8 *)qp->smac),
1398 (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff,
2f5bb473 1399 path, &mqp->pri, port);
297e0dad
MS		 1400}
1401
1402static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1403 const struct ib_qp_attr *qp,
1404 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1405 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1406 struct mlx4_qp_path *path, u8 port)
1407{
1408 return _mlx4_set_path(dev, &qp->alt_ah_attr,
1409 mlx4_mac_to_u64((u8 *)qp->alt_smac),
1410 (qp_attr_mask & IB_QP_ALT_VID) ?
1411 qp->alt_vlan_id : 0xffff,
2f5bb473 1412 path, &mqp->alt, port);
297e0dad
MS		 1413}
1414
fa417f7b
EC		 1415static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1416{
1417 struct mlx4_ib_gid_entry *ge, *tmp;
1418
1419 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1420 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1421 ge->added = 1;
1422 ge->port = qp->port;
1423 }
1424 }
1425}
1426
2f5bb473
JM		 1427static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, u8 *smac,
1428 struct mlx4_qp_context *context)
1429{
2f5bb473
JM		 1430 u64 u64_mac;
1431 int smac_index;
1432
3e0629cb 1433 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1434
1435 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1436 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1437 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1438 if (smac_index >= 0) {
1439 qp->pri.candidate_smac_index = smac_index;
1440 qp->pri.candidate_smac = u64_mac;
1441 qp->pri.candidate_smac_port = qp->port;
1442 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1443 } else {
1444 return -ENOENT;
1445 }
1446 }
1447 return 0;
1448}
1449
65adfa91
MT		 1450static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1451 const struct ib_qp_attr *attr, int attr_mask,
1452 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 1453{
1454 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1455 struct mlx4_ib_qp *qp = to_mqp(ibqp);
0a1405da
SH		 1456 struct mlx4_ib_pd *pd;
1457 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 1458 struct mlx4_qp_context *context;
1459 enum mlx4_qp_optpar optpar = 0;
225c7b1f 1460 int sqd_event;
c1c98501 1461 int steer_qp = 0;
225c7b1f
RD		 1462 int err = -EINVAL;
1463
3dec4878
JM		 1464 /* APM is not supported under RoCE */
1465 if (attr_mask & IB_QP_ALT_PATH &&
1466 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1467 IB_LINK_LAYER_ETHERNET)
1468 return -ENOTSUPP;
1469
225c7b1f
RD		 1470 context = kzalloc(sizeof *context, GFP_KERNEL);
1471 if (!context)
1472 return -ENOMEM;
1473
225c7b1f 1474 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 1475 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 1476
1477 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1478 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1479 else {
1480 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1481 switch (attr->path_mig_state) {
1482 case IB_MIG_MIGRATED:
1483 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1484 break;
1485 case IB_MIG_REARM:
1486 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1487 break;
1488 case IB_MIG_ARMED:
1489 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1490 break;
1491 }
1492 }
1493
b832be1e 1494 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 1495 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
3987a2d3
OG		 1496 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1497 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
b832be1e
EC		 1498 else if (ibqp->qp_type == IB_QPT_UD) {
1499 if (qp->flags & MLX4_IB_QP_LSO)
1500 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1501 ilog2(dev->dev->caps.max_gso_sz);
1502 else
6e0d733d 1503 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 1504 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 1505 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 1506 pr_err("path MTU (%u) is invalid\n",
225c7b1f 1507 attr->path_mtu);
f5b40431 1508 goto out;
225c7b1f 1509 }
d1f2cd89
EC		 1510 context->mtu_msgmax = (attr->path_mtu << 5) |
1511 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 1512 }
1513
0e6e7416
RD		 1514 if (qp->rq.wqe_cnt)
1515 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 1516 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1517
0e6e7416
RD		 1518 if (qp->sq.wqe_cnt)
1519 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 1520 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1521
0a1405da 1522 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 1523 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 1524 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
02d7ef6f
DB		 1525 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1526 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 1527 }
0e6e7416 1528
225c7b1f
RD		 1529 if (qp->ibqp.uobject)
1530 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1531 else
1532 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1533
1534 if (attr_mask & IB_QP_DEST_QPN)
1535 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1536
1537 if (attr_mask & IB_QP_PORT) {
1538 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1539 !(attr_mask & IB_QP_AV)) {
1540 mlx4_set_sched(&context->pri_path, attr->port_num);
1541 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1542 }
1543 }
1544
cfcde11c 1545 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
c3abb51b 1546 if (dev->counters[qp->port - 1].index != -1) {
cfcde11c 1547 context->pri_path.counter_index =
c3abb51b 1548 dev->counters[qp->port - 1].index;
cfcde11c
OG		 1549 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1550 } else
47d8417f
EBE		 1551 context->pri_path.counter_index =
1552 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 1553
1554 if (qp->flags & MLX4_IB_QP_NETIF) {
1555 mlx4_ib_steer_qp_reg(dev, qp, 1);
1556 steer_qp = 1;
1557 }
cfcde11c
OG		 1558 }
1559
225c7b1f 1560 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 1561 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1562 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 1563 context->pri_path.pkey_index = attr->pkey_index;
1564 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1565 }
1566
225c7b1f 1567 if (attr_mask & IB_QP_AV) {
2f5bb473 1568 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1ffeb2eb
JM		 1569 attr_mask & IB_QP_PORT ?
1570 attr->port_num : qp->port))
225c7b1f 1571 goto out;
225c7b1f
RD		 1572
1573 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1574 MLX4_QP_OPTPAR_SCHED_QUEUE);
1575 }
1576
1577 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 1578 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 1579 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1580 }
1581
1582 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 1583 if (attr->alt_port_num == 0 ||
1584 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 1585 goto out;
225c7b1f 1586
5ae2a7a8
RD		 1587 if (attr->alt_pkey_index >=
1588 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 1589 goto out;
5ae2a7a8 1590
2f5bb473
JM		 1591 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1592 &context->alt_path,
297e0dad 1593 attr->alt_port_num))
f5b40431 1594 goto out;
225c7b1f
RD		 1595
1596 context->alt_path.pkey_index = attr->alt_pkey_index;
1597 context->alt_path.ackto = attr->alt_timeout << 3;
1598 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1599 }
1600
0a1405da
SH		 1601 pd = get_pd(qp);
1602 get_cqs(qp, &send_cq, &recv_cq);
1603 context->pd = cpu_to_be32(pd->pdn);
1604 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1605 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1606 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 1607
95d04f07
RD		 1608 /* Set "fast registration enabled" for all kernel QPs */
1609 if (!qp->ibqp.uobject)
1610 context->params1 |= cpu_to_be32(1 << 11);
1611
57f01b53
JM		 1612 if (attr_mask & IB_QP_RNR_RETRY) {
1613 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1614 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1615 }
1616
225c7b1f
RD		 1617 if (attr_mask & IB_QP_RETRY_CNT) {
1618 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1619 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1620 }
1621
1622 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1623 if (attr->max_rd_atomic)
1624 context->params1 |=
1625 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1626 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1627 }
1628
1629 if (attr_mask & IB_QP_SQ_PSN)
1630 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1631
225c7b1f
RD		 1632 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1633 if (attr->max_dest_rd_atomic)
1634 context->params2 |=
1635 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1636 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1637 }
1638
1639 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1640 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1641 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1642 }
1643
1644 if (ibqp->srq)
1645 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1646
1647 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1648 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1649 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1650 }
1651 if (attr_mask & IB_QP_RQ_PSN)
1652 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1653
1ffeb2eb 1654 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 1655 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 1656 if (qp->mlx4_ib_qp_type &
1657 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1658 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1659 else {
1660 if (mlx4_is_mfunc(dev->dev) &&
1661 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1662 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1663 MLX4_RESERVED_QKEY_BASE) {
1664 pr_err("Cannot use reserved QKEY"
1665 " 0x%x (range 0xffff0000..0xffffffff"
1666 " is reserved)\n", attr->qkey);
1667 err = -EINVAL;
1668 goto out;
1669 }
1670 context->qkey = cpu_to_be32(attr->qkey);
1671 }
225c7b1f
RD		 1672 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1673 }
1674
1675 if (ibqp->srq)
1676 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1677
0a1405da 1678 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1679 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1680
1681 if (cur_state == IB_QPS_INIT &&
1682 new_state == IB_QPS_RTR &&
1683 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
3987a2d3
OG		 1684 ibqp->qp_type == IB_QPT_UD ||
1685 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 1686 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 1687 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1688 qp->mlx4_ib_qp_type &
1689 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 1690 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 1691 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1692 context->pri_path.fl = 0x80;
1693 } else {
1694 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1695 context->pri_path.fl = 0x80;
225c7b1f 1696 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 1697 }
2f5bb473
JM		 1698 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1699 IB_LINK_LAYER_ETHERNET) {
1700 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1701 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1702 context->pri_path.feup = 1 << 7; /* don't fsm */
1703 /* handle smac_index */
1704 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1705 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1706 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1707 err = handle_eth_ud_smac_index(dev, qp, (u8 *)attr->smac, context);
bede98e7
MD		 1708 if (err) {
1709 err = -EINVAL;
1710 goto out;
1711 }
9433c188
MB		 1712 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1713 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 1714 }
1715 }
225c7b1f
RD		 1716 }
1717
d2fce8a9 1718 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 1719 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1720 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 1721 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1722 /* set QP to receive both tunneled & non-tunneled packets */
8e1a03b6 1723 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
d2fce8a9
OG		 1724 context->srqn = cpu_to_be32(7 << 28);
1725 }
1726 }
3528f696 1727
297e0dad
MS		 1728 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1729 int is_eth = rdma_port_get_link_layer(
1730 &dev->ib_dev, qp->port) ==
1731 IB_LINK_LAYER_ETHERNET;
1732 if (is_eth) {
1733 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1734 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1735 }
1736 }
1737
1738
225c7b1f
RD		 1739 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1740 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1741 sqd_event = 1;
1742 else
1743 sqd_event = 0;
1744
d57f5f72
VS		 1745 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1746 context->rlkey |= (1 << 4);
1747
c0be5fb5
EC		 1748 /*
1749 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1750 * ownership bits of the send queue are set and the SQ
1751 * headroom is stamped so that the hardware doesn't start
1752 * processing stale work requests.
c0be5fb5
EC		 1753 */
1754 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1755 struct mlx4_wqe_ctrl_seg *ctrl;
1756 int i;
1757
0e6e7416 1758 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1759 ctrl = get_send_wqe(qp, i);
1760 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553
EC		 1761 if (qp->sq_max_wqes_per_wr == 1)
1762 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
0e6e7416 1763
ea54b10c 1764 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 1765 }
1766 }
1767
225c7b1f
RD		 1768 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1769 to_mlx4_state(new_state), context, optpar,
1770 sqd_event, &qp->mqp);
1771 if (err)
1772 goto out;
1773
1774 qp->state = new_state;
1775
1776 if (attr_mask & IB_QP_ACCESS_FLAGS)
1777 qp->atomic_rd_en = attr->qp_access_flags;
1778 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1779 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 1780 if (attr_mask & IB_QP_PORT) {
225c7b1f 1781 qp->port = attr->port_num;
fa417f7b
EC		 1782 update_mcg_macs(dev, qp);
1783 }
225c7b1f
RD		 1784 if (attr_mask & IB_QP_ALT_PATH)
1785 qp->alt_port = attr->alt_port_num;
1786
1787 if (is_sqp(dev, qp))
1788 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1789
1790 /*
1791 * If we moved QP0 to RTR, bring the IB link up; if we moved
1792 * QP0 to RESET or ERROR, bring the link back down.
1793 */
1794 if (is_qp0(dev, qp)) {
1795 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 1796 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 1797 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 1798 qp->port);
225c7b1f
RD		 1799
1800 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1801 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1802 mlx4_CLOSE_PORT(dev->dev, qp->port);
1803 }
1804
1805 /*
1806 * If we moved a kernel QP to RESET, clean up all old CQ
1807 * entries and reinitialize the QP.
1808 */
2f5bb473
JM		 1809 if (new_state == IB_QPS_RESET) {
1810 if (!ibqp->uobject) {
1811 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1812 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1813 if (send_cq != recv_cq)
1814 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1815
1816 qp->rq.head = 0;
1817 qp->rq.tail = 0;
1818 qp->sq.head = 0;
1819 qp->sq.tail = 0;
1820 qp->sq_next_wqe = 0;
1821 if (qp->rq.wqe_cnt)
1822 *qp->db.db = 0;
225c7b1f 1823
2f5bb473
JM		 1824 if (qp->flags & MLX4_IB_QP_NETIF)
1825 mlx4_ib_steer_qp_reg(dev, qp, 0);
1826 }
25476b02 1827 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1828 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1829 qp->pri.smac = 0;
25476b02 1830 qp->pri.smac_port = 0;
2f5bb473
JM		 1831 }
1832 if (qp->alt.smac) {
1833 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1834 qp->alt.smac = 0;
1835 }
1836 if (qp->pri.vid < 0x1000) {
1837 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1838 qp->pri.vid = 0xFFFF;
1839 qp->pri.candidate_vid = 0xFFFF;
1840 qp->pri.update_vid = 0;
1841 }
c1c98501 1842
2f5bb473
JM		 1843 if (qp->alt.vid < 0x1000) {
1844 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1845 qp->alt.vid = 0xFFFF;
1846 qp->alt.candidate_vid = 0xFFFF;
1847 qp->alt.update_vid = 0;
1848 }
225c7b1f 1849 }
225c7b1f 1850out:
c1c98501
MB		 1851 if (err && steer_qp)
1852 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 1853 kfree(context);
25476b02
JM		 1854 if (qp->pri.candidate_smac ||
1855 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 1856 if (err) {
1857 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1858 } else {
25476b02 1859 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 1860 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1861 qp->pri.smac = qp->pri.candidate_smac;
1862 qp->pri.smac_index = qp->pri.candidate_smac_index;
1863 qp->pri.smac_port = qp->pri.candidate_smac_port;
1864 }
1865 qp->pri.candidate_smac = 0;
1866 qp->pri.candidate_smac_index = 0;
1867 qp->pri.candidate_smac_port = 0;
1868 }
1869 if (qp->alt.candidate_smac) {
1870 if (err) {
1871 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1872 } else {
1873 if (qp->alt.smac)
1874 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1875 qp->alt.smac = qp->alt.candidate_smac;
1876 qp->alt.smac_index = qp->alt.candidate_smac_index;
1877 qp->alt.smac_port = qp->alt.candidate_smac_port;
1878 }
1879 qp->alt.candidate_smac = 0;
1880 qp->alt.candidate_smac_index = 0;
1881 qp->alt.candidate_smac_port = 0;
1882 }
1883
1884 if (qp->pri.update_vid) {
1885 if (err) {
1886 if (qp->pri.candidate_vid < 0x1000)
1887 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1888 qp->pri.candidate_vid);
1889 } else {
1890 if (qp->pri.vid < 0x1000)
1891 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1892 qp->pri.vid);
1893 qp->pri.vid = qp->pri.candidate_vid;
1894 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1895 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
1896 }
1897 qp->pri.candidate_vid = 0xFFFF;
1898 qp->pri.update_vid = 0;
1899 }
1900
1901 if (qp->alt.update_vid) {
1902 if (err) {
1903 if (qp->alt.candidate_vid < 0x1000)
1904 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
1905 qp->alt.candidate_vid);
1906 } else {
1907 if (qp->alt.vid < 0x1000)
1908 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
1909 qp->alt.vid);
1910 qp->alt.vid = qp->alt.candidate_vid;
1911 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
1912 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
1913 }
1914 qp->alt.candidate_vid = 0xFFFF;
1915 qp->alt.update_vid = 0;
1916 }
1917
225c7b1f
RD		 1918 return err;
1919}
1920
65adfa91
MT		 1921int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1922 int attr_mask, struct ib_udata *udata)
1923{
1924 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1925 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1926 enum ib_qp_state cur_state, new_state;
1927 int err = -EINVAL;
297e0dad 1928 int ll;
65adfa91
MT		 1929 mutex_lock(&qp->mutex);
1930
1931 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1932 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1933
297e0dad
MS		 1934 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1935 ll = IB_LINK_LAYER_UNSPECIFIED;
1936 } else {
1937 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1938 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
1939 }
dd5f03be
MB		 1940
1941 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 1942 attr_mask, ll)) {
b1d8eb5a
JM		 1943 pr_debug("qpn 0x%x: invalid attribute mask specified "
1944 "for transition %d to %d. qp_type %d,"
1945 " attr_mask 0x%x\n",
1946 ibqp->qp_num, cur_state, new_state,
1947 ibqp->qp_type, attr_mask);
65adfa91 1948 goto out;
b1d8eb5a 1949 }
65adfa91 1950
c6215745
MS		 1951 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
1952 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
1953 if ((ibqp->qp_type == IB_QPT_RC) ||
1954 (ibqp->qp_type == IB_QPT_UD) ||
1955 (ibqp->qp_type == IB_QPT_UC) ||
1956 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
1957 (ibqp->qp_type == IB_QPT_XRC_INI)) {
1958 attr->port_num = mlx4_ib_bond_next_port(dev);
1959 }
1960 } else {
1961 /* no sense in changing port_num
1962 * when ports are bonded */
1963 attr_mask &= ~IB_QP_PORT;
1964 }
1965 }
1966
65adfa91 1967 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 1968 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 1969 pr_debug("qpn 0x%x: invalid port number (%d) specified "
1970 "for transition %d to %d. qp_type %d\n",
1971 ibqp->qp_num, attr->port_num, cur_state,
1972 new_state, ibqp->qp_type);
65adfa91
MT		 1973 goto out;
1974 }
1975
3987a2d3
OG		 1976 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1977 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1978 IB_LINK_LAYER_ETHERNET))
1979 goto out;
1980
5ae2a7a8
RD		 1981 if (attr_mask & IB_QP_PKEY_INDEX) {
1982 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 1983 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
1984 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
1985 "for transition %d to %d. qp_type %d\n",
1986 ibqp->qp_num, attr->pkey_index, cur_state,
1987 new_state, ibqp->qp_type);
5ae2a7a8 1988 goto out;
b1d8eb5a 1989 }
5ae2a7a8
RD		 1990 }
1991
65adfa91
MT		 1992 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1993 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 1994 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
1995 "Transition %d to %d. qp_type %d\n",
1996 ibqp->qp_num, attr->max_rd_atomic, cur_state,
1997 new_state, ibqp->qp_type);
65adfa91
MT		 1998 goto out;
1999 }
2000
2001 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2002 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2003 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2004 "Transition %d to %d. qp_type %d\n",
2005 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2006 new_state, ibqp->qp_type);
65adfa91
MT		 2007 goto out;
2008 }
2009
2010 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2011 err = 0;
2012 goto out;
2013 }
2014
65adfa91
MT		 2015 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2016
c6215745
MS		 2017 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2018 attr->port_num = 1;
2019
65adfa91
MT		 2020out:
2021 mutex_unlock(&qp->mutex);
2022 return err;
2023}
2024
99ec41d0
JM		 2025static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2026{
2027 int i;
2028 for (i = 0; i < dev->caps.num_ports; i++) {
2029 if (qpn == dev->caps.qp0_proxy[i] ||
2030 qpn == dev->caps.qp0_tunnel[i]) {
2031 *qkey = dev->caps.qp0_qkey[i];
2032 return 0;
2033 }
2034 }
2035 return -EINVAL;
2036}
2037
1ffeb2eb
JM		 2038static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2039 struct ib_send_wr *wr,
2040 void *wqe, unsigned *mlx_seg_len)
2041{
2042 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2043 struct ib_device *ib_dev = &mdev->ib_dev;
2044 struct mlx4_wqe_mlx_seg *mlx = wqe;
2045 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2046 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2047 u16 pkey;
2048 u32 qkey;
2049 int send_size;
2050 int header_size;
2051 int spc;
2052 int i;
2053
2054 if (wr->opcode != IB_WR_SEND)
2055 return -EINVAL;
2056
2057 send_size = 0;
2058
2059 for (i = 0; i < wr->num_sge; ++i)
2060 send_size += wr->sg_list[i].length;
2061
2062 /* for proxy-qp0 sends, need to add in size of tunnel header */
2063 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2064 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2065 send_size += sizeof (struct mlx4_ib_tunnel_header);
2066
2067 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
2068
2069 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2070 sqp->ud_header.lrh.service_level =
2071 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2072 sqp->ud_header.lrh.destination_lid =
2073 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2074 sqp->ud_header.lrh.source_lid =
2075 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2076 }
2077
2078 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2079
2080 /* force loopback */
2081 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2082 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2083
2084 sqp->ud_header.lrh.virtual_lane = 0;
2085 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2086 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2087 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2088 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2089 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2090 else
2091 sqp->ud_header.bth.destination_qpn =
47605df9 2092 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 2093
2094 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2095 if (mlx4_is_master(mdev->dev)) {
2096 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2097 return -EINVAL;
2098 } else {
2099 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2100 return -EINVAL;
2101 }
1ffeb2eb
JM		 2102 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2103 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2104
2105 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2106 sqp->ud_header.immediate_present = 0;
2107
2108 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2109
2110 /*
2111 * Inline data segments may not cross a 64 byte boundary. If
2112 * our UD header is bigger than the space available up to the
2113 * next 64 byte boundary in the WQE, use two inline data
2114 * segments to hold the UD header.
2115 */
2116 spc = MLX4_INLINE_ALIGN -
2117 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2118 if (header_size <= spc) {
2119 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2120 memcpy(inl + 1, sqp->header_buf, header_size);
2121 i = 1;
2122 } else {
2123 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2124 memcpy(inl + 1, sqp->header_buf, spc);
2125
2126 inl = (void *) (inl + 1) + spc;
2127 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2128 /*
2129 * Need a barrier here to make sure all the data is
2130 * visible before the byte_count field is set.
2131 * Otherwise the HCA prefetcher could grab the 64-byte
2132 * chunk with this inline segment and get a valid (!=
2133 * 0xffffffff) byte count but stale data, and end up
2134 * generating a packet with bad headers.
2135 *
2136 * The first inline segment's byte_count field doesn't
2137 * need a barrier, because it comes after a
2138 * control/MLX segment and therefore is at an offset
2139 * of 16 mod 64.
2140 */
2141 wmb();
2142 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2143 i = 2;
2144 }
2145
2146 *mlx_seg_len =
2147 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2148 return 0;
2149}
2150
3e0629cb
JM		 2151static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2152{
2153 int i;
2154
2155 for (i = ETH_ALEN; i; i--) {
2156 dst_mac[i - 1] = src_mac & 0xff;
2157 src_mac >>= 8;
2158 }
2159}
2160
225c7b1f 2161static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
f438000f 2162 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2163{
a478868a 2164 struct ib_device *ib_dev = sqp->qp.ibqp.device;
225c7b1f 2165 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2166 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f
RD		 2167 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2168 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
4c3eb3ca 2169 union ib_gid sgid;
225c7b1f
RD		 2170 u16 pkey;
2171 int send_size;
2172 int header_size;
e61ef241 2173 int spc;
225c7b1f 2174 int i;
1ffeb2eb 2175 int err = 0;
57d88cff 2176 u16 vlan = 0xffff;
a29bec12
RD		 2177 bool is_eth;
2178 bool is_vlan = false;
2179 bool is_grh;
225c7b1f
RD		 2180
2181 send_size = 0;
2182 for (i = 0; i < wr->num_sge; ++i)
2183 send_size += wr->sg_list[i].length;
2184
fa417f7b
EC		 2185 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2186 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 2187 if (is_eth) {
1ffeb2eb
JM		 2188 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2189 /* When multi-function is enabled, the ib_core gid
2190 * indexes don't necessarily match the hw ones, so
2191 * we must use our own cache */
6ee51a4e
JM		 2192 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2193 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2194 ah->av.ib.gid_index, &sgid.raw[0]);
2195 if (err)
2196 return err;
1ffeb2eb
JM		 2197 } else {
2198 err = ib_get_cached_gid(ib_dev,
2199 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2200 ah->av.ib.gid_index, &sgid);
2201 if (err)
2202 return err;
2203 }
2204
0e9855db 2205 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 2206 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2207 is_vlan = 1;
2208 }
4c3eb3ca
EC		 2209 }
2210 ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
fa417f7b
EC		 2211
2212 if (!is_eth) {
2213 sqp->ud_header.lrh.service_level =
2214 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2215 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2216 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2217 }
225c7b1f 2218
fa417f7b 2219 if (is_grh) {
225c7b1f 2220 sqp->ud_header.grh.traffic_class =
fa417f7b 2221 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 2222 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 2223 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2224 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
6ee51a4e
JM		 2225 if (is_eth)
2226 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2227 else {
1ffeb2eb
JM		 2228 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2229 /* When multi-function is enabled, the ib_core gid
2230 * indexes don't necessarily match the hw ones, so
2231 * we must use our own cache */
2232 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2233 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2234 subnet_prefix;
2235 sqp->ud_header.grh.source_gid.global.interface_id =
2236 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2237 guid_cache[ah->av.ib.gid_index];
2238 } else
2239 ib_get_cached_gid(ib_dev,
2240 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2241 ah->av.ib.gid_index,
2242 &sqp->ud_header.grh.source_gid);
6ee51a4e 2243 }
225c7b1f 2244 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 2245 ah->av.ib.dgid, 16);
225c7b1f
RD		 2246 }
2247
2248 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 2249
2250 if (!is_eth) {
2251 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2252 (sqp->ud_header.lrh.destination_lid ==
2253 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2254 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 2255 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2256 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 2257 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2258 }
225c7b1f
RD		 2259
2260 switch (wr->opcode) {
2261 case IB_WR_SEND:
2262 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2263 sqp->ud_header.immediate_present = 0;
2264 break;
2265 case IB_WR_SEND_WITH_IMM:
2266 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2267 sqp->ud_header.immediate_present = 1;
0f39cf3d 2268 sqp->ud_header.immediate_data = wr->ex.imm_data;
225c7b1f
RD		 2269 break;
2270 default:
2271 return -EINVAL;
2272 }
2273
fa417f7b 2274 if (is_eth) {
6ee51a4e
JM		 2275 struct in6_addr in6;
2276
c0c1d3d7
OD		 2277 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2278
2279 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b
EC		 2280
2281 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2282 /* FIXME: cache smac value? */
6ee51a4e
JM		 2283 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2284 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2285 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 2286
3e0629cb
JM		 2287 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2288 u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2289 u8 smac[ETH_ALEN];
2290
2291 mlx4_u64_to_smac(smac, mac);
2292 memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2293 } else {
2294 /* use the src mac of the tunnel */
2295 memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2296 }
2297
fa417f7b
EC		 2298 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2299 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca
EC		 2300 if (!is_vlan) {
2301 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2302 } else {
4c3eb3ca 2303 sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
4c3eb3ca
EC		 2304 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2305 }
fa417f7b
EC		 2306 } else {
2307 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
2308 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2309 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2310 }
225c7b1f
RD		 2311 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2312 if (!sqp->qp.ibqp.qp_num)
2313 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2314 else
2315 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
2316 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2317 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2318 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2319 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
2320 sqp->qkey : wr->wr.ud.remote_qkey);
2321 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2322
2323 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2324
2325 if (0) {
987c8f8f 2326 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 2327 for (i = 0; i < header_size / 4; ++i) {
2328 if (i % 8 == 0)
987c8f8f
SP		 2329 pr_err(" [%02x] ", i * 4);
2330 pr_cont(" %08x",
2331 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 2332 if ((i + 1) % 8 == 0)
987c8f8f 2333 pr_cont("\n");
225c7b1f 2334 }
987c8f8f 2335 pr_err("\n");
225c7b1f
RD		 2336 }
2337
e61ef241
RD		 2338 /*
2339 * Inline data segments may not cross a 64 byte boundary. If
2340 * our UD header is bigger than the space available up to the
2341 * next 64 byte boundary in the WQE, use two inline data
2342 * segments to hold the UD header.
2343 */
2344 spc = MLX4_INLINE_ALIGN -
2345 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2346 if (header_size <= spc) {
2347 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2348 memcpy(inl + 1, sqp->header_buf, header_size);
2349 i = 1;
2350 } else {
2351 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2352 memcpy(inl + 1, sqp->header_buf, spc);
2353
2354 inl = (void *) (inl + 1) + spc;
2355 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2356 /*
2357 * Need a barrier here to make sure all the data is
2358 * visible before the byte_count field is set.
2359 * Otherwise the HCA prefetcher could grab the 64-byte
2360 * chunk with this inline segment and get a valid (!=
2361 * 0xffffffff) byte count but stale data, and end up
2362 * generating a packet with bad headers.
2363 *
2364 * The first inline segment's byte_count field doesn't
2365 * need a barrier, because it comes after a
2366 * control/MLX segment and therefore is at an offset
2367 * of 16 mod 64.
2368 */
2369 wmb();
2370 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2371 i = 2;
2372 }
225c7b1f 2373
f438000f
RD		 2374 *mlx_seg_len =
2375 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2376 return 0;
225c7b1f
RD		 2377}
2378
2379static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2380{
2381 unsigned cur;
2382 struct mlx4_ib_cq *cq;
2383
2384 cur = wq->head - wq->tail;
0e6e7416 2385 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 2386 return 0;
2387
2388 cq = to_mcq(ib_cq);
2389 spin_lock(&cq->lock);
2390 cur = wq->head - wq->tail;
2391 spin_unlock(&cq->lock);
2392
0e6e7416 2393 return cur + nreq >= wq->max_post;
225c7b1f
RD		 2394}
2395
95d04f07
RD		 2396static __be32 convert_access(int acc)
2397{
6ff63e19
SM		 2398 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2399 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2400 (acc & IB_ACCESS_REMOTE_WRITE ?
2401 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2402 (acc & IB_ACCESS_REMOTE_READ ?
2403 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 2404 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2405 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2406}
2407
2408static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
2409{
2410 struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
29bdc883
VS		 2411 int i;
2412
2413 for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2b6b7d4b 2414 mfrpl->mapped_page_list[i] =
29bdc883
VS		 2415 cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
2416 MLX4_MTT_FLAG_PRESENT);
95d04f07
RD		 2417
2418 fseg->flags = convert_access(wr->wr.fast_reg.access_flags);
2419 fseg->mem_key = cpu_to_be32(wr->wr.fast_reg.rkey);
2420 fseg->buf_list = cpu_to_be64(mfrpl->map);
2421 fseg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
2422 fseg->reg_len = cpu_to_be64(wr->wr.fast_reg.length);
2423 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2424 fseg->page_size = cpu_to_be32(wr->wr.fast_reg.page_shift);
2425 fseg->reserved[0] = 0;
2426 fseg->reserved[1] = 0;
2427}
2428
6ff63e19
SM		 2429static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr)
2430{
2431 bseg->flags1 =
2432 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) &
2433 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ |
2434 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2435 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2436 bseg->flags2 = 0;
2437 if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2)
2438 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2439 if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED)
2440 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2441 bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey);
2442 bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey);
2443 bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr);
2444 bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length);
2445}
2446
95d04f07
RD		 2447static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2448{
aee38fad
SM		 2449 memset(iseg, 0, sizeof(*iseg));
2450 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 2451}
2452
0fbfa6a9
RD		 2453static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2454 u64 remote_addr, u32 rkey)
2455{
2456 rseg->raddr = cpu_to_be64(remote_addr);
2457 rseg->rkey = cpu_to_be32(rkey);
2458 rseg->reserved = 0;
2459}
2460
2461static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2462{
2463 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2464 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2465 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
6fa8f719
VS		 2466 } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2467 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2468 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add_mask);
0fbfa6a9
RD		 2469 } else {
2470 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2471 aseg->compare = 0;
2472 }
2473
2474}
2475
6fa8f719
VS		 2476static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2477 struct ib_send_wr *wr)
2478{
2479 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2480 aseg->swap_add_mask = cpu_to_be64(wr->wr.atomic.swap_mask);
2481 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
2482 aseg->compare_mask = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2483}
2484
0fbfa6a9 2485static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
80a2dcd8 2486 struct ib_send_wr *wr)
0fbfa6a9
RD		 2487{
2488 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2489 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2490 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
fa417f7b
EC		 2491 dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2492 memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
0fbfa6a9
RD		 2493}
2494
1ffeb2eb
JM		 2495static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2496 struct mlx4_wqe_datagram_seg *dseg,
97982f5a
JM		 2497 struct ib_send_wr *wr,
2498 enum mlx4_ib_qp_type qpt)
1ffeb2eb
JM		 2499{
2500 union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2501 struct mlx4_av sqp_av = {0};
2502 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2503
2504 /* force loopback */
2505 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2506 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2507 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2508 cpu_to_be32(0xf0000000);
2509
2510 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a
JM		 2511 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2512 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2513 else
2514 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
47605df9
JM		 2515 /* Use QKEY from the QP context, which is set by master */
2516 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 2517}
2518
2519static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2520{
2521 struct mlx4_wqe_inline_seg *inl = wqe;
2522 struct mlx4_ib_tunnel_header hdr;
2523 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2524 int spc;
2525 int i;
2526
2527 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2528 hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2529 hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2530 hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
5ea8bbfc
JM		 2531 memcpy(hdr.mac, ah->av.eth.mac, 6);
2532 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 2533
2534 spc = MLX4_INLINE_ALIGN -
2535 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2536 if (sizeof (hdr) <= spc) {
2537 memcpy(inl + 1, &hdr, sizeof (hdr));
2538 wmb();
2539 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2540 i = 1;
2541 } else {
2542 memcpy(inl + 1, &hdr, spc);
2543 wmb();
2544 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2545
2546 inl = (void *) (inl + 1) + spc;
2547 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2548 wmb();
2549 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2550 i = 2;
2551 }
2552
2553 *mlx_seg_len =
2554 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2555}
2556
6e694ea3
JM		 2557static void set_mlx_icrc_seg(void *dseg)
2558{
2559 u32 *t = dseg;
2560 struct mlx4_wqe_inline_seg *iseg = dseg;
2561
2562 t[1] = 0;
2563
2564 /*
2565 * Need a barrier here before writing the byte_count field to
2566 * make sure that all the data is visible before the
2567 * byte_count field is set. Otherwise, if the segment begins
2568 * a new cacheline, the HCA prefetcher could grab the 64-byte
2569 * chunk and get a valid (!= * 0xffffffff) byte count but
2570 * stale data, and end up sending the wrong data.
2571 */
2572 wmb();
2573
2574 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2575}
2576
2577static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 2578{
d420d9e3
RD		 2579 dseg->lkey = cpu_to_be32(sg->lkey);
2580 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 2581
2582 /*
2583 * Need a barrier here before writing the byte_count field to
2584 * make sure that all the data is visible before the
2585 * byte_count field is set. Otherwise, if the segment begins
2586 * a new cacheline, the HCA prefetcher could grab the 64-byte
2587 * chunk and get a valid (!= * 0xffffffff) byte count but
2588 * stale data, and end up sending the wrong data.
2589 */
2590 wmb();
2591
2592 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 2593}
2594
2242fa4f
RD		 2595static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2596{
2597 dseg->byte_count = cpu_to_be32(sg->length);
2598 dseg->lkey = cpu_to_be32(sg->lkey);
2599 dseg->addr = cpu_to_be64(sg->addr);
2600}
2601
47b37475 2602static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
0fd7e1d8 2603 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 2604 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e
EC		 2605{
2606 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2607
417608c2
EC		 2608 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2609 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 2610
2611 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2612 wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2613 return -EINVAL;
2614
2615 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2616
ca9b590c 2617 *lso_hdr_sz = cpu_to_be32(wr->wr.ud.mss << 16 | wr->wr.ud.hlen);
b832be1e
EC		 2618 *lso_seg_len = halign;
2619 return 0;
2620}
2621
95d04f07
RD		 2622static __be32 send_ieth(struct ib_send_wr *wr)
2623{
2624 switch (wr->opcode) {
2625 case IB_WR_SEND_WITH_IMM:
2626 case IB_WR_RDMA_WRITE_WITH_IMM:
2627 return wr->ex.imm_data;
2628
2629 case IB_WR_SEND_WITH_INV:
2630 return cpu_to_be32(wr->ex.invalidate_rkey);
2631
2632 default:
2633 return 0;
2634 }
2635}
2636
1ffeb2eb
JM		 2637static void add_zero_len_inline(void *wqe)
2638{
2639 struct mlx4_wqe_inline_seg *inl = wqe;
2640 memset(wqe, 0, 16);
2641 inl->byte_count = cpu_to_be32(1 << 31);
2642}
2643
225c7b1f
RD		 2644int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2645 struct ib_send_wr **bad_wr)
2646{
2647 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2648 void *wqe;
2649 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 2650 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 2651 unsigned long flags;
2652 int nreq;
2653 int err = 0;
ea54b10c
JM		 2654 unsigned ind;
2655 int uninitialized_var(stamp);
2656 int uninitialized_var(size);
a3d8e159 2657 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 2658 __be32 dummy;
2659 __be32 *lso_wqe;
2660 __be32 uninitialized_var(lso_hdr_sz);
417608c2 2661 __be32 blh;
225c7b1f 2662 int i;
35f05dab 2663 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 2664
96db0e03 2665 spin_lock_irqsave(&qp->sq.lock, flags);
35f05dab
YH		 2666 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2667 err = -EIO;
2668 *bad_wr = wr;
2669 nreq = 0;
2670 goto out;
2671 }
225c7b1f 2672
ea54b10c 2673 ind = qp->sq_next_wqe;
225c7b1f
RD		 2674
2675 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 2676 lso_wqe = &dummy;
417608c2 2677 blh = 0;
0fd7e1d8 2678
225c7b1f
RD		 2679 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2680 err = -ENOMEM;
2681 *bad_wr = wr;
2682 goto out;
2683 }
2684
2685 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2686 err = -EINVAL;
2687 *bad_wr = wr;
2688 goto out;
2689 }
2690
0e6e7416 2691 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 2692 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 2693
2694 ctrl->srcrb_flags =
2695 (wr->send_flags & IB_SEND_SIGNALED ?
2696 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2697 (wr->send_flags & IB_SEND_SOLICITED ?
2698 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 2699 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2700 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2701 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 2702 qp->sq_signal_bits;
2703
95d04f07 2704 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 2705
2706 wqe += sizeof *ctrl;
2707 size = sizeof *ctrl / 16;
2708
1ffeb2eb
JM		 2709 switch (qp->mlx4_ib_qp_type) {
2710 case MLX4_IB_QPT_RC:
2711 case MLX4_IB_QPT_UC:
225c7b1f
RD		 2712 switch (wr->opcode) {
2713 case IB_WR_ATOMIC_CMP_AND_SWP:
2714 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 2715 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
0fbfa6a9
RD		 2716 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2717 wr->wr.atomic.rkey);
225c7b1f
RD		 2718 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2719
0fbfa6a9 2720 set_atomic_seg(wqe, wr);
225c7b1f 2721 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 2722
225c7b1f
RD		 2723 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2724 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 2725
2726 break;
2727
2728 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2729 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2730 wr->wr.atomic.rkey);
2731 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2732
2733 set_masked_atomic_seg(wqe, wr);
2734 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
2735
2736 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2737 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 2738
2739 break;
2740
2741 case IB_WR_RDMA_READ:
2742 case IB_WR_RDMA_WRITE:
2743 case IB_WR_RDMA_WRITE_WITH_IMM:
0fbfa6a9
RD		 2744 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2745 wr->wr.rdma.rkey);
225c7b1f
RD		 2746 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2747 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 2748 break;
95d04f07
RD		 2749
2750 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 2751 ctrl->srcrb_flags |=
2752 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2753 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2754 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
2755 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2756 break;
2757
2758 case IB_WR_FAST_REG_MR:
2ac6bf4d
JM		 2759 ctrl->srcrb_flags |=
2760 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2761 set_fmr_seg(wqe, wr);
2762 wqe += sizeof (struct mlx4_wqe_fmr_seg);
2763 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2764 break;
225c7b1f 2765
6ff63e19
SM		 2766 case IB_WR_BIND_MW:
2767 ctrl->srcrb_flags |=
2768 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2769 set_bind_seg(wqe, wr);
2770 wqe += sizeof(struct mlx4_wqe_bind_seg);
2771 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2772 break;
225c7b1f
RD		 2773 default:
2774 /* No extra segments required for sends */
2775 break;
2776 }
2777 break;
2778
1ffeb2eb
JM		 2779 case MLX4_IB_QPT_TUN_SMI_OWNER:
2780 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2781 if (unlikely(err)) {
2782 *bad_wr = wr;
2783 goto out;
2784 }
2785 wqe += seglen;
2786 size += seglen / 16;
2787 break;
2788 case MLX4_IB_QPT_TUN_SMI:
2789 case MLX4_IB_QPT_TUN_GSI:
2790 /* this is a UD qp used in MAD responses to slaves. */
2791 set_datagram_seg(wqe, wr);
2792 /* set the forced-loopback bit in the data seg av */
2793 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2794 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2795 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2796 break;
2797 case MLX4_IB_QPT_UD:
80a2dcd8 2798 set_datagram_seg(wqe, wr);
225c7b1f
RD		 2799 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2800 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 2801
2802 if (wr->opcode == IB_WR_LSO) {
417608c2 2803 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
b832be1e
EC		 2804 if (unlikely(err)) {
2805 *bad_wr = wr;
2806 goto out;
2807 }
0fd7e1d8 2808 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 2809 wqe += seglen;
2810 size += seglen / 16;
2811 }
225c7b1f
RD		 2812 break;
2813
1ffeb2eb 2814 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1ffeb2eb
JM		 2815 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2816 if (unlikely(err)) {
2817 *bad_wr = wr;
2818 goto out;
2819 }
2820 wqe += seglen;
2821 size += seglen / 16;
2822 /* to start tunnel header on a cache-line boundary */
2823 add_zero_len_inline(wqe);
2824 wqe += 16;
2825 size++;
2826 build_tunnel_header(wr, wqe, &seglen);
2827 wqe += seglen;
2828 size += seglen / 16;
2829 break;
2830 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 2831 case MLX4_IB_QPT_PROXY_GSI:
2832 /* If we are tunneling special qps, this is a UD qp.
2833 * In this case we first add a UD segment targeting
2834 * the tunnel qp, and then add a header with address
2835 * information */
97982f5a
JM		 2836 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr,
2837 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 2838 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2839 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2840 build_tunnel_header(wr, wqe, &seglen);
2841 wqe += seglen;
2842 size += seglen / 16;
2843 break;
2844
2845 case MLX4_IB_QPT_SMI:
2846 case MLX4_IB_QPT_GSI:
f438000f
RD		 2847 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2848 if (unlikely(err)) {
225c7b1f
RD		 2849 *bad_wr = wr;
2850 goto out;
2851 }
f438000f
RD		 2852 wqe += seglen;
2853 size += seglen / 16;
225c7b1f
RD		 2854 break;
2855
2856 default:
2857 break;
2858 }
2859
6e694ea3
JM		 2860 /*
2861 * Write data segments in reverse order, so as to
2862 * overwrite cacheline stamp last within each
2863 * cacheline. This avoids issues with WQE
2864 * prefetching.
2865 */
225c7b1f 2866
6e694ea3
JM		 2867 dseg = wqe;
2868 dseg += wr->num_sge - 1;
2869 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 2870
2871 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 2872 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2873 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2874 qp->mlx4_ib_qp_type &
2875 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 2876 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 2877 size += sizeof (struct mlx4_wqe_data_seg) / 16;
2878 }
2879
6e694ea3
JM		 2880 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2881 set_data_seg(dseg, wr->sg_list + i);
2882
0fd7e1d8
RD		 2883 /*
2884 * Possibly overwrite stamping in cacheline with LSO
2885 * segment only after making sure all data segments
2886 * are written.
2887 */
2888 wmb();
2889 *lso_wqe = lso_hdr_sz;
2890
225c7b1f
RD		 2891 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2892 MLX4_WQE_CTRL_FENCE : 0) | size;
2893
2894 /*
2895 * Make sure descriptor is fully written before
2896 * setting ownership bit (because HW can start
2897 * executing as soon as we do).
2898 */
2899 wmb();
2900
59b0ed12 2901 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 2902 *bad_wr = wr;
225c7b1f
RD		 2903 err = -EINVAL;
2904 goto out;
2905 }
2906
2907 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 2908 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 2909
ea54b10c
JM		 2910 stamp = ind + qp->sq_spare_wqes;
2911 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2912
0e6e7416
RD		 2913 /*
2914 * We can improve latency by not stamping the last
2915 * send queue WQE until after ringing the doorbell, so
2916 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 2917 *
2918 * Same optimization applies to padding with NOP wqe
2919 * in case of WQE shrinking (used to prevent wrap-around
2920 * in the middle of WR).
0e6e7416 2921 */
ea54b10c
JM		 2922 if (wr->next) {
2923 stamp_send_wqe(qp, stamp, size * 16);
2924 ind = pad_wraparound(qp, ind);
2925 }
225c7b1f
RD		 2926 }
2927
2928out:
2929 if (likely(nreq)) {
2930 qp->sq.head += nreq;
2931
2932 /*
2933 * Make sure that descriptors are written before
2934 * doorbell record.
2935 */
2936 wmb();
2937
2938 writel(qp->doorbell_qpn,
2939 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
2940
2941 /*
2942 * Make sure doorbells don't leak out of SQ spinlock
2943 * and reach the HCA out of order.
2944 */
2945 mmiowb();
0e6e7416 2946
ea54b10c
JM		 2947 stamp_send_wqe(qp, stamp, size * 16);
2948
2949 ind = pad_wraparound(qp, ind);
2950 qp->sq_next_wqe = ind;
225c7b1f
RD		 2951 }
2952
96db0e03 2953 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 2954
2955 return err;
2956}
2957
2958int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2959 struct ib_recv_wr **bad_wr)
2960{
2961 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2962 struct mlx4_wqe_data_seg *scat;
2963 unsigned long flags;
2964 int err = 0;
2965 int nreq;
2966 int ind;
1ffeb2eb 2967 int max_gs;
225c7b1f 2968 int i;
35f05dab 2969 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 2970
1ffeb2eb 2971 max_gs = qp->rq.max_gs;
225c7b1f
RD		 2972 spin_lock_irqsave(&qp->rq.lock, flags);
2973
35f05dab
YH		 2974 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2975 err = -EIO;
2976 *bad_wr = wr;
2977 nreq = 0;
2978 goto out;
2979 }
2980
0e6e7416 2981 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 2982
2983 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 2984 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 2985 err = -ENOMEM;
2986 *bad_wr = wr;
2987 goto out;
2988 }
2989
2990 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2991 err = -EINVAL;
2992 *bad_wr = wr;
2993 goto out;
2994 }
2995
2996 scat = get_recv_wqe(qp, ind);
2997
1ffeb2eb
JM		 2998 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
2999 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3000 ib_dma_sync_single_for_device(ibqp->device,
3001 qp->sqp_proxy_rcv[ind].map,
3002 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3003 DMA_FROM_DEVICE);
3004 scat->byte_count =
3005 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3006 /* use dma lkey from upper layer entry */
3007 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3008 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3009 scat++;
3010 max_gs--;
3011 }
3012
2242fa4f
RD		 3013 for (i = 0; i < wr->num_sge; ++i)
3014 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3015
1ffeb2eb 3016 if (i < max_gs) {
225c7b1f
RD		 3017 scat[i].byte_count = 0;
3018 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3019 scat[i].addr = 0;
3020 }
3021
3022 qp->rq.wrid[ind] = wr->wr_id;
3023
0e6e7416 3024 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3025 }
3026
3027out:
3028 if (likely(nreq)) {
3029 qp->rq.head += nreq;
3030
3031 /*
3032 * Make sure that descriptors are written before
3033 * doorbell record.
3034 */
3035 wmb();
3036
3037 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3038 }
3039
3040 spin_unlock_irqrestore(&qp->rq.lock, flags);
3041
3042 return err;
3043}
6a775e2b
JM		 3044
3045static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3046{
3047 switch (mlx4_state) {
3048 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3049 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3050 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3051 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3052 case MLX4_QP_STATE_SQ_DRAINING:
3053 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3054 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3055 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3056 default: return -1;
3057 }
3058}
3059
3060static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3061{
3062 switch (mlx4_mig_state) {
3063 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3064 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3065 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3066 default: return -1;
3067 }
3068}
3069
3070static int to_ib_qp_access_flags(int mlx4_flags)
3071{
3072 int ib_flags = 0;
3073
3074 if (mlx4_flags & MLX4_QP_BIT_RRE)
3075 ib_flags |= IB_ACCESS_REMOTE_READ;
3076 if (mlx4_flags & MLX4_QP_BIT_RWE)
3077 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3078 if (mlx4_flags & MLX4_QP_BIT_RAE)
3079 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3080
3081 return ib_flags;
3082}
3083
4c3eb3ca 3084static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
6a775e2b
JM		 3085 struct mlx4_qp_path *path)
3086{
4c3eb3ca
EC		 3087 struct mlx4_dev *dev = ibdev->dev;
3088 int is_eth;
3089
8fcea95a 3090 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 3091 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
3092
3093 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3094 return;
3095
4c3eb3ca
EC		 3096 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3097 IB_LINK_LAYER_ETHERNET;
3098 if (is_eth)
3099 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3100 ((path->sched_queue & 4) << 1);
3101 else
3102 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3103
6a775e2b 3104 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
6a775e2b
JM		 3105 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3106 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3107 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3108 if (ib_ah_attr->ah_flags) {
3109 ib_ah_attr->grh.sgid_index = path->mgid_index;
3110 ib_ah_attr->grh.hop_limit = path->hop_limit;
3111 ib_ah_attr->grh.traffic_class =
3112 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3113 ib_ah_attr->grh.flow_label =
586bb586 3114 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 3115 memcpy(ib_ah_attr->grh.dgid.raw,
3116 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3117 }
3118}
3119
3120int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3121 struct ib_qp_init_attr *qp_init_attr)
3122{
3123 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3124 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3125 struct mlx4_qp_context context;
3126 int mlx4_state;
0df67030
DB		 3127 int err = 0;
3128
3129 mutex_lock(&qp->mutex);
6a775e2b
JM		 3130
3131 if (qp->state == IB_QPS_RESET) {
3132 qp_attr->qp_state = IB_QPS_RESET;
3133 goto done;
3134 }
3135
3136 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3137 if (err) {
3138 err = -EINVAL;
3139 goto out;
3140 }
6a775e2b
JM		 3141
3142 mlx4_state = be32_to_cpu(context.flags) >> 28;
3143
0df67030
DB		 3144 qp->state = to_ib_qp_state(mlx4_state);
3145 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3146 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3147 qp_attr->path_mig_state =
3148 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3149 qp_attr->qkey = be32_to_cpu(context.qkey);
3150 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3151 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3152 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3153 qp_attr->qp_access_flags =
3154 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3155
3156 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4c3eb3ca
EC		 3157 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3158 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b
JM		 3159 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3160 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3161 }
3162
3163 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 3164 if (qp_attr->qp_state == IB_QPS_INIT)
3165 qp_attr->port_num = qp->port;
3166 else
3167 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 3168
3169 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3170 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3171
3172 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3173
3174 qp_attr->max_dest_rd_atomic =
3175 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3176 qp_attr->min_rnr_timer =
3177 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3178 qp_attr->timeout = context.pri_path.ackto >> 3;
3179 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3180 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3181 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3182
3183done:
3184 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 3185 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3186 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3187
6a775e2b 3188 if (!ibqp->uobject) {
7f5eb9bb
RD		 3189 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3190 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3191 } else {
3192 qp_attr->cap.max_send_wr = 0;
3193 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 3194 }
3195
7f5eb9bb
RD		 3196 /*
3197 * We don't support inline sends for kernel QPs (yet), and we
3198 * don't know what userspace's value should be.
3199 */
3200 qp_attr->cap.max_inline_data = 0;
3201
3202 qp_init_attr->cap = qp_attr->cap;
3203
521e575b
RL		 3204 qp_init_attr->create_flags = 0;
3205 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3206 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3207
3208 if (qp->flags & MLX4_IB_QP_LSO)
3209 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3210
c1c98501
MB		 3211 if (qp->flags & MLX4_IB_QP_NETIF)
3212 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3213
46db567d
DB		 3214 qp_init_attr->sq_sig_type =
3215 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3216 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3217
0df67030
DB		 3218out:
3219 mutex_unlock(&qp->mutex);
3220 return err;
6a775e2b
JM		 3221}
3222
Linux 6.x block layer and io_uring tree(s)