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IB/mlx4: Add counter based implementation for QP multicast loopback block
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
5a0e3ad6 35#include <linux/slab.h>
fa417f7b 36#include <linux/netdevice.h>
ea54b10c 37
225c7b1f
RD		 38#include <rdma/ib_cache.h>
39#include <rdma/ib_pack.h>
4c3eb3ca 40#include <rdma/ib_addr.h>
1ffeb2eb 41#include <rdma/ib_mad.h>
225c7b1f 42
2f48485d 43#include <linux/mlx4/driver.h>
225c7b1f
RD		 44#include <linux/mlx4/qp.h>
45
46#include "mlx4_ib.h"
47#include "user.h"
48
35f05dab
YH		 49static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
50 struct mlx4_ib_cq *recv_cq);
51static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
52 struct mlx4_ib_cq *recv_cq);
53
225c7b1f
RD		 54enum {
55 MLX4_IB_ACK_REQ_FREQ = 8,
56};
57
58enum {
59 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 60 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
61 MLX4_IB_LINK_TYPE_IB = 0,
62 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 63};
64
65enum {
66 /*
fa417f7b 67 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 68 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
69 * tag. (LRH would only use 8 bytes, so Ethernet is the
70 * biggest case)
225c7b1f 71 */
4c3eb3ca 72 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 73 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 74};
75
fa417f7b
EC		 76enum {
77 MLX4_IB_IBOE_ETHERTYPE = 0x8915
78};
79
225c7b1f
RD		 80struct mlx4_ib_sqp {
81 struct mlx4_ib_qp qp;
82 int pkey_index;
83 u32 qkey;
84 u32 send_psn;
85 struct ib_ud_header ud_header;
86 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
87};
88
83904132 89enum {
417608c2
EC		 90 MLX4_IB_MIN_SQ_STRIDE = 6,
91 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 92};
93
3987a2d3
OG		 94enum {
95 MLX4_RAW_QP_MTU = 7,
96 MLX4_RAW_QP_MSGMAX = 31,
97};
98
297e0dad
MS		 99#ifndef ETH_ALEN
100#define ETH_ALEN 6
101#endif
297e0dad 102
225c7b1f 103static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
114 [IB_WR_FAST_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
6ff63e19 117 [IB_WR_BIND_MW] = cpu_to_be32(MLX4_OPCODE_BIND_MW),
225c7b1f
RD		 118};
119
120static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
121{
122 return container_of(mqp, struct mlx4_ib_sqp, qp);
123}
124
1ffeb2eb
JM		 125static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
126{
127 if (!mlx4_is_master(dev->dev))
128 return 0;
129
47605df9
JM		 130 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
131 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
132 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 133}
134
225c7b1f
RD		 135static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
136{
47605df9
JM		 137 int proxy_sqp = 0;
138 int real_sqp = 0;
139 int i;
140 /* PPF or Native -- real SQP */
141 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
142 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
143 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
144 if (real_sqp)
145 return 1;
146 /* VF or PF -- proxy SQP */
147 if (mlx4_is_mfunc(dev->dev)) {
148 for (i = 0; i < dev->dev->caps.num_ports; i++) {
149 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
150 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
151 proxy_sqp = 1;
152 break;
153 }
154 }
155 }
156 return proxy_sqp;
225c7b1f
RD		 157}
158
1ffeb2eb 159/* used for INIT/CLOSE port logic */
225c7b1f
RD		 160static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
161{
47605df9
JM		 162 int proxy_qp0 = 0;
163 int real_qp0 = 0;
164 int i;
165 /* PPF or Native -- real QP0 */
166 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
167 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
168 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
169 if (real_qp0)
170 return 1;
171 /* VF or PF -- proxy QP0 */
172 if (mlx4_is_mfunc(dev->dev)) {
173 for (i = 0; i < dev->dev->caps.num_ports; i++) {
174 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
175 proxy_qp0 = 1;
176 break;
177 }
178 }
179 }
180 return proxy_qp0;
225c7b1f
RD		 181}
182
183static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
184{
1c69fc2a 185 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 186}
187
188static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
189{
190 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
191}
192
193static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
194{
195 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
196}
197
0e6e7416
RD		 198/*
199 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 200 * first four bytes of every 64 byte chunk with
201 * 0x7FFFFFF | (invalid_ownership_value << 31).
202 *
203 * When the max work request size is less than or equal to the WQE
204 * basic block size, as an optimization, we can stamp all WQEs with
205 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 206 */
ea54b10c 207static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 208{
d2ae16d5 209 __be32 *wqe;
0e6e7416 210 int i;
ea54b10c
JM		 211 int s;
212 int ind;
213 void *buf;
214 __be32 stamp;
9670e553 215 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 216
ea54b10c 217 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 218 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 219 for (i = 0; i < s; i += 64) {
220 ind = (i >> qp->sq.wqe_shift) + n;
221 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
222 cpu_to_be32(0xffffffff);
223 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
224 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
225 *wqe = stamp;
226 }
227 } else {
9670e553
EC		 228 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
229 s = (ctrl->fence_size & 0x3f) << 4;
ea54b10c
JM		 230 for (i = 64; i < s; i += 64) {
231 wqe = buf + i;
d2ae16d5 232 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 233 }
234 }
235}
236
237static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
238{
239 struct mlx4_wqe_ctrl_seg *ctrl;
240 struct mlx4_wqe_inline_seg *inl;
241 void *wqe;
242 int s;
243
244 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
245 s = sizeof(struct mlx4_wqe_ctrl_seg);
246
247 if (qp->ibqp.qp_type == IB_QPT_UD) {
248 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
249 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
250 memset(dgram, 0, sizeof *dgram);
251 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
252 s += sizeof(struct mlx4_wqe_datagram_seg);
253 }
254
255 /* Pad the remainder of the WQE with an inline data segment. */
256 if (size > s) {
257 inl = wqe + s;
258 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
259 }
260 ctrl->srcrb_flags = 0;
261 ctrl->fence_size = size / 16;
262 /*
263 * Make sure descriptor is fully written before setting ownership bit
264 * (because HW can start executing as soon as we do).
265 */
266 wmb();
267
268 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
269 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 270
ea54b10c
JM		 271 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
272}
273
274/* Post NOP WQE to prevent wrap-around in the middle of WR */
275static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
276{
277 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
278 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
279 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
280 ind += s;
281 }
282 return ind;
0e6e7416
RD		 283}
284
225c7b1f
RD		 285static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
286{
287 struct ib_event event;
288 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
289
290 if (type == MLX4_EVENT_TYPE_PATH_MIG)
291 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
292
293 if (ibqp->event_handler) {
294 event.device = ibqp->device;
295 event.element.qp = ibqp;
296 switch (type) {
297 case MLX4_EVENT_TYPE_PATH_MIG:
298 event.event = IB_EVENT_PATH_MIG;
299 break;
300 case MLX4_EVENT_TYPE_COMM_EST:
301 event.event = IB_EVENT_COMM_EST;
302 break;
303 case MLX4_EVENT_TYPE_SQ_DRAINED:
304 event.event = IB_EVENT_SQ_DRAINED;
305 break;
306 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
307 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
308 break;
309 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
310 event.event = IB_EVENT_QP_FATAL;
311 break;
312 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
313 event.event = IB_EVENT_PATH_MIG_ERR;
314 break;
315 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
316 event.event = IB_EVENT_QP_REQ_ERR;
317 break;
318 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
319 event.event = IB_EVENT_QP_ACCESS_ERR;
320 break;
321 default:
987c8f8f 322 pr_warn("Unexpected event type %d "
225c7b1f
RD		 323 "on QP %06x\n", type, qp->qpn);
324 return;
325 }
326
327 ibqp->event_handler(&event, ibqp->qp_context);
328 }
329}
330
1ffeb2eb 331static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 332{
333 /*
334 * UD WQEs must have a datagram segment.
335 * RC and UC WQEs might have a remote address segment.
336 * MLX WQEs need two extra inline data segments (for the UD
337 * header and space for the ICRC).
338 */
339 switch (type) {
1ffeb2eb 340 case MLX4_IB_QPT_UD:
225c7b1f 341 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 342 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 343 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 344 case MLX4_IB_QPT_PROXY_SMI_OWNER:
345 case MLX4_IB_QPT_PROXY_SMI:
346 case MLX4_IB_QPT_PROXY_GSI:
347 return sizeof (struct mlx4_wqe_ctrl_seg) +
348 sizeof (struct mlx4_wqe_datagram_seg) + 64;
349 case MLX4_IB_QPT_TUN_SMI_OWNER:
350 case MLX4_IB_QPT_TUN_GSI:
351 return sizeof (struct mlx4_wqe_ctrl_seg) +
352 sizeof (struct mlx4_wqe_datagram_seg);
353
354 case MLX4_IB_QPT_UC:
225c7b1f
RD		 355 return sizeof (struct mlx4_wqe_ctrl_seg) +
356 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 357 case MLX4_IB_QPT_RC:
225c7b1f
RD		 358 return sizeof (struct mlx4_wqe_ctrl_seg) +
359 sizeof (struct mlx4_wqe_atomic_seg) +
360 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 361 case MLX4_IB_QPT_SMI:
362 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 363 return sizeof (struct mlx4_wqe_ctrl_seg) +
364 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 365 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
366 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 367 sizeof (struct mlx4_wqe_inline_seg),
368 sizeof (struct mlx4_wqe_data_seg)) +
369 ALIGN(4 +
370 sizeof (struct mlx4_wqe_inline_seg),
371 sizeof (struct mlx4_wqe_data_seg));
372 default:
373 return sizeof (struct mlx4_wqe_ctrl_seg);
374 }
375}
376
2446304d 377static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
0a1405da 378 int is_user, int has_rq, struct mlx4_ib_qp *qp)
225c7b1f 379{
2446304d 380 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 381 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
382 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 383 return -EINVAL;
384
0a1405da 385 if (!has_rq) {
a4cd7ed8
RD		 386 if (cap->max_recv_wr)
387 return -EINVAL;
2446304d 388
0e6e7416 389 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 390 } else {
391 /* HW requires >= 1 RQ entry with >= 1 gather entry */
392 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
393 return -EINVAL;
394
0e6e7416 395 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 396 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 397 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
398 }
2446304d 399
fc2d0044
SG		 400 /* leave userspace return values as they were, so as not to break ABI */
401 if (is_user) {
402 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
403 cap->max_recv_sge = qp->rq.max_gs;
404 } else {
405 cap->max_recv_wr = qp->rq.max_post =
406 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
407 cap->max_recv_sge = min(qp->rq.max_gs,
408 min(dev->dev->caps.max_sq_sg,
409 dev->dev->caps.max_rq_sg));
410 }
2446304d
EC		 411
412 return 0;
413}
414
415static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
1ffeb2eb 416 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 417{
ea54b10c
JM		 418 int s;
419
2446304d 420 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 421 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
422 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 423 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 424 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
425 return -EINVAL;
426
427 /*
428 * For MLX transport we need 2 extra S/G entries:
429 * one for the header and one for the checksum at the end
430 */
1ffeb2eb
JM		 431 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
432 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 433 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
434 return -EINVAL;
435
ea54b10c
JM		 436 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
437 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 438 send_wqe_overhead(type, qp->flags);
225c7b1f 439
cd155c1c
RD		 440 if (s > dev->dev->caps.max_sq_desc_sz)
441 return -EINVAL;
442
0e6e7416 443 /*
ea54b10c
JM		 444 * Hermon supports shrinking WQEs, such that a single work
445 * request can include multiple units of 1 << wqe_shift. This
446 * way, work requests can differ in size, and do not have to
447 * be a power of 2 in size, saving memory and speeding up send
448 * WR posting. Unfortunately, if we do this then the
449 * wqe_index field in CQEs can't be used to look up the WR ID
450 * anymore, so we do this only if selective signaling is off.
451 *
452 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 453 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 454 * constant-sized WRs to make sure a WR is always fully within
455 * a single page-sized chunk.
456 *
457 * Finally, we use NOP work requests to pad the end of the
458 * work queue, to avoid wrap-around in the middle of WR. We
459 * set NEC bit to avoid getting completions with error for
460 * these NOP WRs, but since NEC is only supported starting
461 * with firmware 2.2.232, we use constant-sized WRs for older
462 * firmware.
463 *
464 * And, since MLX QPs only support SEND, we use constant-sized
465 * WRs in this case.
466 *
467 * We look for the smallest value of wqe_shift such that the
468 * resulting number of wqes does not exceed device
469 * capabilities.
470 *
471 * We set WQE size to at least 64 bytes, this way stamping
472 * invalidates each WQE.
0e6e7416 473 */
ea54b10c
JM		 474 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
475 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 476 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
477 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
478 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 479 qp->sq.wqe_shift = ilog2(64);
480 else
481 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
482
483 for (;;) {
ea54b10c
JM		 484 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
485
486 /*
487 * We need to leave 2 KB + 1 WR of headroom in the SQ to
488 * allow HW to prefetch.
489 */
490 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
491 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
492 qp->sq_max_wqes_per_wr +
493 qp->sq_spare_wqes);
494
495 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
496 break;
497
498 if (qp->sq_max_wqes_per_wr <= 1)
499 return -EINVAL;
500
501 ++qp->sq.wqe_shift;
502 }
503
cd155c1c
RD		 504 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
505 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 506 send_wqe_overhead(type, qp->flags)) /
507 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 508
509 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
510 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 511 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
512 qp->rq.offset = 0;
0e6e7416 513 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 514 } else {
0e6e7416 515 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 516 qp->sq.offset = 0;
517 }
518
ea54b10c
JM		 519 cap->max_send_wr = qp->sq.max_post =
520 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 521 cap->max_send_sge = min(qp->sq.max_gs,
522 min(dev->dev->caps.max_sq_sg,
523 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 524 /* We don't support inline sends for kernel QPs (yet) */
525 cap->max_inline_data = 0;
225c7b1f
RD		 526
527 return 0;
528}
529
83904132
JM		 530static int set_user_sq_size(struct mlx4_ib_dev *dev,
531 struct mlx4_ib_qp *qp,
2446304d
EC		 532 struct mlx4_ib_create_qp *ucmd)
533{
83904132
JM		 534 /* Sanity check SQ size before proceeding */
535 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
536 ucmd->log_sq_stride >
537 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
538 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
539 return -EINVAL;
540
0e6e7416 541 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 542 qp->sq.wqe_shift = ucmd->log_sq_stride;
543
0e6e7416
RD		 544 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
545 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 546
547 return 0;
548}
549
1ffeb2eb
JM		 550static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
551{
552 int i;
553
554 qp->sqp_proxy_rcv =
555 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
556 GFP_KERNEL);
557 if (!qp->sqp_proxy_rcv)
558 return -ENOMEM;
559 for (i = 0; i < qp->rq.wqe_cnt; i++) {
560 qp->sqp_proxy_rcv[i].addr =
561 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
562 GFP_KERNEL);
563 if (!qp->sqp_proxy_rcv[i].addr)
564 goto err;
565 qp->sqp_proxy_rcv[i].map =
566 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
567 sizeof (struct mlx4_ib_proxy_sqp_hdr),
568 DMA_FROM_DEVICE);
cc47d369
SO		 569 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
570 kfree(qp->sqp_proxy_rcv[i].addr);
571 goto err;
572 }
1ffeb2eb
JM		 573 }
574 return 0;
575
576err:
577 while (i > 0) {
578 --i;
579 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
580 sizeof (struct mlx4_ib_proxy_sqp_hdr),
581 DMA_FROM_DEVICE);
582 kfree(qp->sqp_proxy_rcv[i].addr);
583 }
584 kfree(qp->sqp_proxy_rcv);
585 qp->sqp_proxy_rcv = NULL;
586 return -ENOMEM;
587}
588
589static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
590{
591 int i;
592
593 for (i = 0; i < qp->rq.wqe_cnt; i++) {
594 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
595 sizeof (struct mlx4_ib_proxy_sqp_hdr),
596 DMA_FROM_DEVICE);
597 kfree(qp->sqp_proxy_rcv[i].addr);
598 }
599 kfree(qp->sqp_proxy_rcv);
600}
601
0a1405da
SH		 602static int qp_has_rq(struct ib_qp_init_attr *attr)
603{
604 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
605 return 0;
606
607 return !attr->srq;
608}
609
99ec41d0
JM		 610static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
611{
612 int i;
613 for (i = 0; i < dev->caps.num_ports; i++) {
614 if (qpn == dev->caps.qp0_proxy[i])
615 return !!dev->caps.qp0_qkey[i];
616 }
617 return 0;
618}
619
7b59f0f9
EBE		 620static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
621 struct mlx4_ib_qp *qp)
622{
623 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
624 mlx4_counter_free(dev->dev, qp->counter_index->index);
625 list_del(&qp->counter_index->list);
626 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
627
628 kfree(qp->counter_index);
629 qp->counter_index = NULL;
630}
631
225c7b1f
RD		 632static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
633 struct ib_qp_init_attr *init_attr,
40f2287b
JK		 634 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
635 gfp_t gfp)
225c7b1f 636{
a3cdcbfa 637 int qpn;
225c7b1f 638 int err;
1ffeb2eb
JM		 639 struct mlx4_ib_sqp *sqp;
640 struct mlx4_ib_qp *qp;
641 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 642 struct mlx4_ib_cq *mcq;
643 unsigned long flags;
1ffeb2eb
JM		 644
645 /* When tunneling special qps, we use a plain UD qp */
646 if (sqpn) {
647 if (mlx4_is_mfunc(dev->dev) &&
648 (!mlx4_is_master(dev->dev) ||
649 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
650 if (init_attr->qp_type == IB_QPT_GSI)
651 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 652 else {
653 if (mlx4_is_master(dev->dev) ||
654 qp0_enabled_vf(dev->dev, sqpn))
655 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
656 else
657 qp_type = MLX4_IB_QPT_PROXY_SMI;
658 }
1ffeb2eb
JM		 659 }
660 qpn = sqpn;
661 /* add extra sg entry for tunneling */
662 init_attr->cap.max_recv_sge++;
663 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
664 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
665 container_of(init_attr,
666 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
667 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
668 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
669 !mlx4_is_master(dev->dev))
670 return -EINVAL;
671 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
672 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 673 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
674 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
675 tnl_init->port))
1ffeb2eb
JM		 676 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
677 else
678 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 679 /* we are definitely in the PPF here, since we are creating
680 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
681 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
682 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 683 sqpn = qpn;
684 }
685
686 if (!*caller_qp) {
687 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
688 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
689 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6fcd8d0d 690 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
1ffeb2eb
JM		 691 if (!sqp)
692 return -ENOMEM;
693 qp = &sqp->qp;
2f5bb473
JM		 694 qp->pri.vid = 0xFFFF;
695 qp->alt.vid = 0xFFFF;
1ffeb2eb 696 } else {
6fcd8d0d 697 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
1ffeb2eb
JM		 698 if (!qp)
699 return -ENOMEM;
2f5bb473
JM		 700 qp->pri.vid = 0xFFFF;
701 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 702 }
703 } else
704 qp = *caller_qp;
705
706 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 707
708 mutex_init(&qp->mutex);
709 spin_lock_init(&qp->sq.lock);
710 spin_lock_init(&qp->rq.lock);
fa417f7b 711 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 712 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 713
714 qp->state = IB_QPS_RESET;
ea54b10c
JM		 715 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
716 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 717
0a1405da 718 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
225c7b1f
RD		 719 if (err)
720 goto err;
721
722 if (pd->uobject) {
723 struct mlx4_ib_create_qp ucmd;
724
725 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
726 err = -EFAULT;
727 goto err;
728 }
729
0e6e7416
RD		 730 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
731
83904132 732 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 733 if (err)
734 goto err;
735
225c7b1f 736 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 737 qp->buf_size, 0, 0);
225c7b1f
RD		 738 if (IS_ERR(qp->umem)) {
739 err = PTR_ERR(qp->umem);
740 goto err;
741 }
742
743 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
744 ilog2(qp->umem->page_size), &qp->mtt);
745 if (err)
746 goto err_buf;
747
748 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
749 if (err)
750 goto err_mtt;
751
0a1405da 752 if (qp_has_rq(init_attr)) {
02d89b87
RD		 753 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
754 ucmd.db_addr, &qp->db);
755 if (err)
756 goto err_mtt;
757 }
225c7b1f 758 } else {
0e6e7416
RD		 759 qp->sq_no_prefetch = 0;
760
521e575b
RL		 761 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
762 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
763
b832be1e
EC		 764 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
765 qp->flags |= MLX4_IB_QP_LSO;
766
c1c98501
MB		 767 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
768 if (dev->steering_support ==
769 MLX4_STEERING_MODE_DEVICE_MANAGED)
770 qp->flags |= MLX4_IB_QP_NETIF;
771 else
772 goto err;
773 }
774
1ffeb2eb 775 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 776 if (err)
777 goto err;
778
0a1405da 779 if (qp_has_rq(init_attr)) {
40f2287b 780 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
02d89b87
RD		 781 if (err)
782 goto err;
225c7b1f 783
02d89b87
RD		 784 *qp->db.db = 0;
785 }
225c7b1f 786
40f2287b 787 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
225c7b1f
RD		 788 err = -ENOMEM;
789 goto err_db;
790 }
791
792 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
793 &qp->mtt);
794 if (err)
795 goto err_buf;
796
40f2287b 797 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
225c7b1f
RD		 798 if (err)
799 goto err_mtt;
800
40f2287b
JK		 801 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), gfp);
802 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), gfp);
225c7b1f
RD		 803 if (!qp->sq.wrid || !qp->rq.wrid) {
804 err = -ENOMEM;
805 goto err_wrid;
806 }
225c7b1f
RD		 807 }
808
a3cdcbfa 809 if (sqpn) {
1ffeb2eb
JM		 810 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
811 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
812 if (alloc_proxy_bufs(pd->device, qp)) {
813 err = -ENOMEM;
814 goto err_wrid;
815 }
816 }
a3cdcbfa 817 } else {
ddae0349
EE		 818 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
819 * otherwise, the WQE BlueFlame setup flow wrongly causes
820 * VLAN insertion. */
3987a2d3 821 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 822 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 823 (init_attr->cap.max_send_wr ?
824 MLX4_RESERVE_ETH_BF_QP : 0) |
825 (init_attr->cap.max_recv_wr ?
826 MLX4_RESERVE_A0_QP : 0));
3987a2d3 827 else
c1c98501
MB		 828 if (qp->flags & MLX4_IB_QP_NETIF)
829 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
830 else
831 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
ddae0349 832 &qpn, 0);
a3cdcbfa 833 if (err)
1ffeb2eb 834 goto err_proxy;
a3cdcbfa
YP		 835 }
836
40f2287b 837 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
225c7b1f 838 if (err)
a3cdcbfa 839 goto err_qpn;
225c7b1f 840
0a1405da
SH		 841 if (init_attr->qp_type == IB_QPT_XRC_TGT)
842 qp->mqp.qpn |= (1 << 23);
843
225c7b1f
RD		 844 /*
845 * Hardware wants QPN written in big-endian order (after
846 * shifting) for send doorbell. Precompute this value to save
847 * a little bit when posting sends.
848 */
849 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
850
225c7b1f 851 qp->mqp.event = mlx4_ib_qp_event;
1ffeb2eb
JM		 852 if (!*caller_qp)
853 *caller_qp = qp;
35f05dab
YH		 854
855 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
856 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
857 to_mcq(init_attr->recv_cq));
858 /* Maintain device to QPs access, needed for further handling
859 * via reset flow
860 */
861 list_add_tail(&qp->qps_list, &dev->qp_list);
862 /* Maintain CQ to QPs access, needed for further handling
863 * via reset flow
864 */
865 mcq = to_mcq(init_attr->send_cq);
866 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
867 mcq = to_mcq(init_attr->recv_cq);
868 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
869 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
870 to_mcq(init_attr->recv_cq));
871 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 872 return 0;
873
a3cdcbfa 874err_qpn:
c1c98501
MB		 875 if (!sqpn) {
876 if (qp->flags & MLX4_IB_QP_NETIF)
877 mlx4_ib_steer_qp_free(dev, qpn, 1);
878 else
879 mlx4_qp_release_range(dev->dev, qpn, 1);
880 }
1ffeb2eb
JM		 881err_proxy:
882 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
883 free_proxy_bufs(pd->device, qp);
225c7b1f 884err_wrid:
23f1b384 885 if (pd->uobject) {
0a1405da
SH		 886 if (qp_has_rq(init_attr))
887 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 888 } else {
225c7b1f
RD		 889 kfree(qp->sq.wrid);
890 kfree(qp->rq.wrid);
891 }
892
893err_mtt:
894 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
895
896err_buf:
897 if (pd->uobject)
898 ib_umem_release(qp->umem);
899 else
900 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
901
902err_db:
0a1405da 903 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 904 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 905
906err:
1ffeb2eb
JM		 907 if (!*caller_qp)
908 kfree(qp);
225c7b1f
RD		 909 return err;
910}
911
912static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
913{
914 switch (state) {
915 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
916 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
917 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
918 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
919 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
920 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
921 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
922 default: return -1;
923 }
924}
925
926static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 927 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 928{
338a8fad 929 if (send_cq == recv_cq) {
35f05dab 930 spin_lock(&send_cq->lock);
338a8fad
RD		 931 __acquire(&recv_cq->lock);
932 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 933 spin_lock(&send_cq->lock);
225c7b1f
RD		 934 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
935 } else {
35f05dab 936 spin_lock(&recv_cq->lock);
225c7b1f
RD		 937 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
938 }
939}
940
941static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 942 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 943{
338a8fad
RD		 944 if (send_cq == recv_cq) {
945 __release(&recv_cq->lock);
35f05dab 946 spin_unlock(&send_cq->lock);
338a8fad 947 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 948 spin_unlock(&recv_cq->lock);
35f05dab 949 spin_unlock(&send_cq->lock);
225c7b1f
RD		 950 } else {
951 spin_unlock(&send_cq->lock);
35f05dab 952 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 953 }
954}
955
fa417f7b
EC		 956static void del_gid_entries(struct mlx4_ib_qp *qp)
957{
958 struct mlx4_ib_gid_entry *ge, *tmp;
959
960 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
961 list_del(&ge->list);
962 kfree(ge);
963 }
964}
965
0a1405da
SH		 966static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
967{
968 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
969 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
970 else
971 return to_mpd(qp->ibqp.pd);
972}
973
974static void get_cqs(struct mlx4_ib_qp *qp,
975 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
976{
977 switch (qp->ibqp.qp_type) {
978 case IB_QPT_XRC_TGT:
979 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
980 *recv_cq = *send_cq;
981 break;
982 case IB_QPT_XRC_INI:
983 *send_cq = to_mcq(qp->ibqp.send_cq);
984 *recv_cq = *send_cq;
985 break;
986 default:
987 *send_cq = to_mcq(qp->ibqp.send_cq);
988 *recv_cq = to_mcq(qp->ibqp.recv_cq);
989 break;
990 }
991}
992
225c7b1f
RD		 993static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
994 int is_user)
995{
996 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 997 unsigned long flags;
225c7b1f 998
2f5bb473 999 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1000 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1001 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1002 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1003 qp->mqp.qpn);
25476b02 1004 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1005 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1006 qp->pri.smac = 0;
25476b02 1007 qp->pri.smac_port = 0;
2f5bb473
JM		 1008 }
1009 if (qp->alt.smac) {
1010 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1011 qp->alt.smac = 0;
1012 }
1013 if (qp->pri.vid < 0x1000) {
1014 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1015 qp->pri.vid = 0xFFFF;
1016 qp->pri.candidate_vid = 0xFFFF;
1017 qp->pri.update_vid = 0;
1018 }
1019 if (qp->alt.vid < 0x1000) {
1020 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1021 qp->alt.vid = 0xFFFF;
1022 qp->alt.candidate_vid = 0xFFFF;
1023 qp->alt.update_vid = 0;
1024 }
1025 }
225c7b1f 1026
0a1405da 1027 get_cqs(qp, &send_cq, &recv_cq);
225c7b1f 1028
35f05dab 1029 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1030 mlx4_ib_lock_cqs(send_cq, recv_cq);
1031
35f05dab
YH		 1032 /* del from lists under both locks above to protect reset flow paths */
1033 list_del(&qp->qps_list);
1034 list_del(&qp->cq_send_list);
1035 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1036 if (!is_user) {
1037 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1038 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1039 if (send_cq != recv_cq)
1040 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1041 }
1042
1043 mlx4_qp_remove(dev->dev, &qp->mqp);
1044
1045 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1046 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1047
1048 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1049
c1c98501
MB		 1050 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1051 if (qp->flags & MLX4_IB_QP_NETIF)
1052 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1053 else
1054 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1055 }
a3cdcbfa 1056
225c7b1f
RD		 1057 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1058
1059 if (is_user) {
0a1405da 1060 if (qp->rq.wqe_cnt)
02d89b87
RD		 1061 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1062 &qp->db);
225c7b1f
RD		 1063 ib_umem_release(qp->umem);
1064 } else {
1065 kfree(qp->sq.wrid);
1066 kfree(qp->rq.wrid);
1ffeb2eb
JM		 1067 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1068 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1069 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1070 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1071 if (qp->rq.wqe_cnt)
6296883c 1072 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1073 }
fa417f7b
EC		 1074
1075 del_gid_entries(qp);
225c7b1f
RD		 1076}
1077
47605df9
JM		 1078static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1079{
1080 /* Native or PPF */
1081 if (!mlx4_is_mfunc(dev->dev) ||
1082 (mlx4_is_master(dev->dev) &&
1083 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1084 return dev->dev->phys_caps.base_sqpn +
1085 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1086 attr->port_num - 1;
1087 }
1088 /* PF or VF -- creating proxies */
1089 if (attr->qp_type == IB_QPT_SMI)
1090 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1091 else
1092 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1093}
1094
225c7b1f
RD		 1095struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1096 struct ib_qp_init_attr *init_attr,
1097 struct ib_udata *udata)
1098{
1ffeb2eb 1099 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1100 int err;
0a1405da 1101 u16 xrcdn = 0;
40f2287b 1102 gfp_t gfp;
225c7b1f 1103
40f2287b
JK		 1104 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1105 GFP_NOIO : GFP_KERNEL;
521e575b 1106 /*
1ffeb2eb
JM		 1107 * We only support LSO, vendor flag1, and multicast loopback blocking,
1108 * and only for kernel UD QPs.
521e575b 1109 */
1ffeb2eb
JM		 1110 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1111 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1112 MLX4_IB_SRIOV_TUNNEL_QP |
1113 MLX4_IB_SRIOV_SQP |
40f2287b
JK		 1114 MLX4_IB_QP_NETIF |
1115 MLX4_IB_QP_CREATE_USE_GFP_NOIO))
b832be1e 1116 return ERR_PTR(-EINVAL);
521e575b 1117
c1c98501
MB		 1118 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1119 if (init_attr->qp_type != IB_QPT_UD)
1120 return ERR_PTR(-EINVAL);
1121 }
1122
521e575b 1123 if (init_attr->create_flags &&
1ffeb2eb 1124 (udata ||
40f2287b 1125 ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | MLX4_IB_QP_CREATE_USE_GFP_NOIO)) &&
1ffeb2eb
JM		 1126 init_attr->qp_type != IB_QPT_UD) ||
1127 ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1128 init_attr->qp_type > IB_QPT_GSI)))
b846f25a
EC		 1129 return ERR_PTR(-EINVAL);
1130
225c7b1f 1131 switch (init_attr->qp_type) {
0a1405da
SH		 1132 case IB_QPT_XRC_TGT:
1133 pd = to_mxrcd(init_attr->xrcd)->pd;
1134 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1135 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1136 /* fall through */
1137 case IB_QPT_XRC_INI:
1138 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1139 return ERR_PTR(-ENOSYS);
1140 init_attr->recv_cq = init_attr->send_cq;
1141 /* fall through */
225c7b1f
RD		 1142 case IB_QPT_RC:
1143 case IB_QPT_UC:
3987a2d3 1144 case IB_QPT_RAW_PACKET:
40f2287b 1145 qp = kzalloc(sizeof *qp, gfp);
225c7b1f
RD		 1146 if (!qp)
1147 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1148 qp->pri.vid = 0xFFFF;
1149 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1150 /* fall through */
1151 case IB_QPT_UD:
1152 {
1153 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
40f2287b 1154 udata, 0, &qp, gfp);
1ffeb2eb 1155 if (err)
225c7b1f 1156 return ERR_PTR(err);
225c7b1f
RD		 1157
1158 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1159 qp->xrcdn = xrcdn;
225c7b1f
RD		 1160
1161 break;
1162 }
1163 case IB_QPT_SMI:
1164 case IB_QPT_GSI:
1165 {
1166 /* Userspace is not allowed to create special QPs: */
0a1405da 1167 if (udata)
225c7b1f
RD		 1168 return ERR_PTR(-EINVAL);
1169
0a1405da 1170 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
47605df9 1171 get_sqp_num(to_mdev(pd->device), init_attr),
40f2287b 1172 &qp, gfp);
1ffeb2eb 1173 if (err)
225c7b1f 1174 return ERR_PTR(err);
225c7b1f
RD		 1175
1176 qp->port = init_attr->port_num;
1177 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1178
1179 break;
1180 }
1181 default:
1182 /* Don't support raw QPs */
1183 return ERR_PTR(-EINVAL);
1184 }
1185
1186 return &qp->ibqp;
1187}
1188
1189int mlx4_ib_destroy_qp(struct ib_qp *qp)
1190{
1191 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1192 struct mlx4_ib_qp *mqp = to_mqp(qp);
0a1405da 1193 struct mlx4_ib_pd *pd;
225c7b1f
RD		 1194
1195 if (is_qp0(dev, mqp))
1196 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1197
9433c188
MB		 1198 if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1199 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1200 dev->qp1_proxy[mqp->port - 1] = NULL;
1201 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1202 }
1203
7b59f0f9
EBE		 1204 if (mqp->counter_index)
1205 mlx4_ib_free_qp_counter(dev, mqp);
1206
0a1405da
SH		 1207 pd = get_pd(mqp);
1208 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
225c7b1f
RD		 1209
1210 if (is_sqp(dev, mqp))
1211 kfree(to_msqp(mqp));
1212 else
1213 kfree(mqp);
1214
1215 return 0;
1216}
1217
1ffeb2eb 1218static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1219{
1220 switch (type) {
1ffeb2eb
JM		 1221 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1222 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1223 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1224 case MLX4_IB_QPT_XRC_INI:
1225 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1226 case MLX4_IB_QPT_SMI:
1227 case MLX4_IB_QPT_GSI:
1228 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1229
1230 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1231 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1232 MLX4_QP_ST_MLX : -1);
1233 case MLX4_IB_QPT_PROXY_SMI:
1234 case MLX4_IB_QPT_TUN_SMI:
1235 case MLX4_IB_QPT_PROXY_GSI:
1236 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1237 MLX4_QP_ST_UD : -1);
1238 default: return -1;
225c7b1f
RD		 1239 }
1240}
1241
65adfa91 1242static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1243 int attr_mask)
1244{
1245 u8 dest_rd_atomic;
1246 u32 access_flags;
1247 u32 hw_access_flags = 0;
1248
1249 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1250 dest_rd_atomic = attr->max_dest_rd_atomic;
1251 else
1252 dest_rd_atomic = qp->resp_depth;
1253
1254 if (attr_mask & IB_QP_ACCESS_FLAGS)
1255 access_flags = attr->qp_access_flags;
1256 else
1257 access_flags = qp->atomic_rd_en;
1258
1259 if (!dest_rd_atomic)
1260 access_flags &= IB_ACCESS_REMOTE_WRITE;
1261
1262 if (access_flags & IB_ACCESS_REMOTE_READ)
1263 hw_access_flags |= MLX4_QP_BIT_RRE;
1264 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1265 hw_access_flags |= MLX4_QP_BIT_RAE;
1266 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1267 hw_access_flags |= MLX4_QP_BIT_RWE;
1268
1269 return cpu_to_be32(hw_access_flags);
1270}
1271
65adfa91 1272static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1273 int attr_mask)
1274{
1275 if (attr_mask & IB_QP_PKEY_INDEX)
1276 sqp->pkey_index = attr->pkey_index;
1277 if (attr_mask & IB_QP_QKEY)
1278 sqp->qkey = attr->qkey;
1279 if (attr_mask & IB_QP_SQ_PSN)
1280 sqp->send_psn = attr->sq_psn;
1281}
1282
1283static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1284{
1285 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1286}
1287
297e0dad
MS		 1288static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1289 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1290 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1291{
fa417f7b
EC		 1292 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1293 IB_LINK_LAYER_ETHERNET;
4c3eb3ca 1294 int vidx;
297e0dad 1295 int smac_index;
2f5bb473 1296 int err;
297e0dad 1297
fa417f7b 1298
225c7b1f
RD		 1299 path->grh_mylmc = ah->src_path_bits & 0x7f;
1300 path->rlid = cpu_to_be16(ah->dlid);
1301 if (ah->static_rate) {
1302 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1303 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1304 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1305 --path->static_rate;
1306 } else
1307 path->static_rate = 0;
225c7b1f
RD		 1308
1309 if (ah->ah_flags & IB_AH_GRH) {
5070cd22
MS		 1310 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1311 port,
1312 ah->grh.sgid_index);
1313
1314 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1315 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1316 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1317 return -1;
1318 }
1319
1320 path->grh_mylmc |= 1 << 7;
5070cd22 1321 path->mgid_index = real_sgid_index;
225c7b1f
RD		 1322 path->hop_limit = ah->grh.hop_limit;
1323 path->tclass_flowlabel =
1324 cpu_to_be32((ah->grh.traffic_class << 20) |
1325 (ah->grh.flow_label));
1326 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1327 }
1328
fa417f7b
EC		 1329 if (is_eth) {
1330 if (!(ah->ah_flags & IB_AH_GRH))
1331 return -1;
1332
2f5bb473
JM		 1333 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1334 ((port - 1) << 6) | ((ah->sl & 7) << 3);
4c3eb3ca 1335
297e0dad 1336 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1337 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1338 if (smac_info->vid < 0x1000) {
1339 /* both valid vlan ids */
1340 if (smac_info->vid != vlan_tag) {
1341 /* different VIDs. unreg old and reg new */
1342 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1343 if (err)
1344 return err;
1345 smac_info->candidate_vid = vlan_tag;
1346 smac_info->candidate_vlan_index = vidx;
1347 smac_info->candidate_vlan_port = port;
1348 smac_info->update_vid = 1;
1349 path->vlan_index = vidx;
1350 } else {
1351 path->vlan_index = smac_info->vlan_index;
1352 }
1353 } else {
1354 /* no current vlan tag in qp */
1355 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1356 if (err)
1357 return err;
1358 smac_info->candidate_vid = vlan_tag;
1359 smac_info->candidate_vlan_index = vidx;
1360 smac_info->candidate_vlan_port = port;
1361 smac_info->update_vid = 1;
1362 path->vlan_index = vidx;
1363 }
297e0dad 1364 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1365 path->fl = 1 << 6;
1366 } else {
1367 /* have current vlan tag. unregister it at modify-qp success */
1368 if (smac_info->vid < 0x1000) {
1369 smac_info->candidate_vid = 0xFFFF;
1370 smac_info->update_vid = 1;
1371 }
4c3eb3ca 1372 }
2f5bb473
JM		 1373
1374 /* get smac_index for RoCE use.
1375 * If no smac was yet assigned, register one.
1376 * If one was already assigned, but the new mac differs,
1377 * unregister the old one and register the new one.
1378 */
25476b02
JM		 1379 if ((!smac_info->smac && !smac_info->smac_port) ||
1380 smac_info->smac != smac) {
2f5bb473
JM		 1381 /* register candidate now, unreg if needed, after success */
1382 smac_index = mlx4_register_mac(dev->dev, port, smac);
1383 if (smac_index >= 0) {
1384 smac_info->candidate_smac_index = smac_index;
1385 smac_info->candidate_smac = smac;
1386 smac_info->candidate_smac_port = port;
1387 } else {
1388 return -EINVAL;
1389 }
1390 } else {
1391 smac_index = smac_info->smac_index;
1392 }
1393
1394 memcpy(path->dmac, ah->dmac, 6);
1395 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1396 /* put MAC table smac index for IBoE */
1397 path->grh_mylmc = (u8) (smac_index) | 0x80;
1398 } else {
4c3eb3ca
EC		 1399 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1400 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
2f5bb473 1401 }
fa417f7b 1402
225c7b1f
RD		 1403 return 0;
1404}
1405
297e0dad
MS		 1406static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1407 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1408 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1409 struct mlx4_qp_path *path, u8 port)
1410{
1411 return _mlx4_set_path(dev, &qp->ah_attr,
1412 mlx4_mac_to_u64((u8 *)qp->smac),
1413 (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff,
2f5bb473 1414 path, &mqp->pri, port);
297e0dad
MS		 1415}
1416
1417static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1418 const struct ib_qp_attr *qp,
1419 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1420 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1421 struct mlx4_qp_path *path, u8 port)
1422{
1423 return _mlx4_set_path(dev, &qp->alt_ah_attr,
1424 mlx4_mac_to_u64((u8 *)qp->alt_smac),
1425 (qp_attr_mask & IB_QP_ALT_VID) ?
1426 qp->alt_vlan_id : 0xffff,
2f5bb473 1427 path, &mqp->alt, port);
297e0dad
MS		 1428}
1429
fa417f7b
EC		 1430static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1431{
1432 struct mlx4_ib_gid_entry *ge, *tmp;
1433
1434 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1435 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1436 ge->added = 1;
1437 ge->port = qp->port;
1438 }
1439 }
1440}
1441
2f5bb473
JM		 1442static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, u8 *smac,
1443 struct mlx4_qp_context *context)
1444{
2f5bb473
JM		 1445 u64 u64_mac;
1446 int smac_index;
1447
3e0629cb 1448 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1449
1450 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1451 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1452 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1453 if (smac_index >= 0) {
1454 qp->pri.candidate_smac_index = smac_index;
1455 qp->pri.candidate_smac = u64_mac;
1456 qp->pri.candidate_smac_port = qp->port;
1457 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1458 } else {
1459 return -ENOENT;
1460 }
1461 }
1462 return 0;
1463}
1464
7b59f0f9
EBE		 1465static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1466{
1467 struct counter_index *new_counter_index;
1468 int err;
1469 u32 tmp_idx;
1470
1471 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1472 IB_LINK_LAYER_ETHERNET ||
1473 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1474 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1475 return 0;
1476
1477 err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1478 if (err)
1479 return err;
1480
1481 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1482 if (!new_counter_index) {
1483 mlx4_counter_free(dev->dev, tmp_idx);
1484 return -ENOMEM;
1485 }
1486
1487 new_counter_index->index = tmp_idx;
1488 new_counter_index->allocated = 1;
1489 qp->counter_index = new_counter_index;
1490
1491 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1492 list_add_tail(&new_counter_index->list,
1493 &dev->counters_table[qp->port - 1].counters_list);
1494 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1495
1496 return 0;
1497}
1498
65adfa91
MT		 1499static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1500 const struct ib_qp_attr *attr, int attr_mask,
1501 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 1502{
1503 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1504 struct mlx4_ib_qp *qp = to_mqp(ibqp);
0a1405da
SH		 1505 struct mlx4_ib_pd *pd;
1506 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 1507 struct mlx4_qp_context *context;
1508 enum mlx4_qp_optpar optpar = 0;
225c7b1f 1509 int sqd_event;
c1c98501 1510 int steer_qp = 0;
225c7b1f 1511 int err = -EINVAL;
3ba8e31d 1512 int counter_index;
225c7b1f 1513
3dec4878
JM		 1514 /* APM is not supported under RoCE */
1515 if (attr_mask & IB_QP_ALT_PATH &&
1516 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1517 IB_LINK_LAYER_ETHERNET)
1518 return -ENOTSUPP;
1519
225c7b1f
RD		 1520 context = kzalloc(sizeof *context, GFP_KERNEL);
1521 if (!context)
1522 return -ENOMEM;
1523
225c7b1f 1524 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 1525 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 1526
1527 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1528 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1529 else {
1530 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1531 switch (attr->path_mig_state) {
1532 case IB_MIG_MIGRATED:
1533 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1534 break;
1535 case IB_MIG_REARM:
1536 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1537 break;
1538 case IB_MIG_ARMED:
1539 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1540 break;
1541 }
1542 }
1543
b832be1e 1544 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 1545 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
3987a2d3
OG		 1546 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1547 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
b832be1e
EC		 1548 else if (ibqp->qp_type == IB_QPT_UD) {
1549 if (qp->flags & MLX4_IB_QP_LSO)
1550 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1551 ilog2(dev->dev->caps.max_gso_sz);
1552 else
6e0d733d 1553 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 1554 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 1555 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 1556 pr_err("path MTU (%u) is invalid\n",
225c7b1f 1557 attr->path_mtu);
f5b40431 1558 goto out;
225c7b1f 1559 }
d1f2cd89
EC		 1560 context->mtu_msgmax = (attr->path_mtu << 5) |
1561 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 1562 }
1563
0e6e7416
RD		 1564 if (qp->rq.wqe_cnt)
1565 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 1566 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1567
0e6e7416
RD		 1568 if (qp->sq.wqe_cnt)
1569 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 1570 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1571
7b59f0f9
EBE		 1572 if (new_state == IB_QPS_RESET && qp->counter_index)
1573 mlx4_ib_free_qp_counter(dev, qp);
1574
0a1405da 1575 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 1576 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 1577 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
02d7ef6f
DB		 1578 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1579 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 1580 }
0e6e7416 1581
225c7b1f
RD		 1582 if (qp->ibqp.uobject)
1583 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1584 else
1585 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1586
1587 if (attr_mask & IB_QP_DEST_QPN)
1588 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1589
1590 if (attr_mask & IB_QP_PORT) {
1591 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1592 !(attr_mask & IB_QP_AV)) {
1593 mlx4_set_sched(&context->pri_path, attr->port_num);
1594 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1595 }
1596 }
1597
cfcde11c 1598 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 1599 err = create_qp_lb_counter(dev, qp);
1600 if (err)
1601 goto out;
1602
3ba8e31d
EBE		 1603 counter_index =
1604 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 1605 if (qp->counter_index)
1606 counter_index = qp->counter_index->index;
1607
3ba8e31d
EBE		 1608 if (counter_index != -1) {
1609 context->pri_path.counter_index = counter_index;
cfcde11c 1610 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 1611 if (qp->counter_index) {
1612 context->pri_path.fl |=
1613 MLX4_FL_ETH_SRC_CHECK_MC_LB;
1614 context->pri_path.vlan_control |=
1615 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1616 }
cfcde11c 1617 } else
47d8417f
EBE		 1618 context->pri_path.counter_index =
1619 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 1620
1621 if (qp->flags & MLX4_IB_QP_NETIF) {
1622 mlx4_ib_steer_qp_reg(dev, qp, 1);
1623 steer_qp = 1;
1624 }
cfcde11c
OG		 1625 }
1626
225c7b1f 1627 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 1628 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1629 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 1630 context->pri_path.pkey_index = attr->pkey_index;
1631 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1632 }
1633
225c7b1f 1634 if (attr_mask & IB_QP_AV) {
2f5bb473 1635 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1ffeb2eb
JM		 1636 attr_mask & IB_QP_PORT ?
1637 attr->port_num : qp->port))
225c7b1f 1638 goto out;
225c7b1f
RD		 1639
1640 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1641 MLX4_QP_OPTPAR_SCHED_QUEUE);
1642 }
1643
1644 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 1645 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 1646 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1647 }
1648
1649 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 1650 if (attr->alt_port_num == 0 ||
1651 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 1652 goto out;
225c7b1f 1653
5ae2a7a8
RD		 1654 if (attr->alt_pkey_index >=
1655 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 1656 goto out;
5ae2a7a8 1657
2f5bb473
JM		 1658 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1659 &context->alt_path,
297e0dad 1660 attr->alt_port_num))
f5b40431 1661 goto out;
225c7b1f
RD		 1662
1663 context->alt_path.pkey_index = attr->alt_pkey_index;
1664 context->alt_path.ackto = attr->alt_timeout << 3;
1665 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1666 }
1667
0a1405da
SH		 1668 pd = get_pd(qp);
1669 get_cqs(qp, &send_cq, &recv_cq);
1670 context->pd = cpu_to_be32(pd->pdn);
1671 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1672 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1673 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 1674
95d04f07
RD		 1675 /* Set "fast registration enabled" for all kernel QPs */
1676 if (!qp->ibqp.uobject)
1677 context->params1 |= cpu_to_be32(1 << 11);
1678
57f01b53
JM		 1679 if (attr_mask & IB_QP_RNR_RETRY) {
1680 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1681 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1682 }
1683
225c7b1f
RD		 1684 if (attr_mask & IB_QP_RETRY_CNT) {
1685 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1686 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1687 }
1688
1689 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1690 if (attr->max_rd_atomic)
1691 context->params1 |=
1692 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1693 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1694 }
1695
1696 if (attr_mask & IB_QP_SQ_PSN)
1697 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1698
225c7b1f
RD		 1699 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1700 if (attr->max_dest_rd_atomic)
1701 context->params2 |=
1702 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1703 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1704 }
1705
1706 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1707 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1708 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1709 }
1710
1711 if (ibqp->srq)
1712 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1713
1714 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1715 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1716 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1717 }
1718 if (attr_mask & IB_QP_RQ_PSN)
1719 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1720
1ffeb2eb 1721 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 1722 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 1723 if (qp->mlx4_ib_qp_type &
1724 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1725 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1726 else {
1727 if (mlx4_is_mfunc(dev->dev) &&
1728 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1729 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1730 MLX4_RESERVED_QKEY_BASE) {
1731 pr_err("Cannot use reserved QKEY"
1732 " 0x%x (range 0xffff0000..0xffffffff"
1733 " is reserved)\n", attr->qkey);
1734 err = -EINVAL;
1735 goto out;
1736 }
1737 context->qkey = cpu_to_be32(attr->qkey);
1738 }
225c7b1f
RD		 1739 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1740 }
1741
1742 if (ibqp->srq)
1743 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1744
0a1405da 1745 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1746 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1747
1748 if (cur_state == IB_QPS_INIT &&
1749 new_state == IB_QPS_RTR &&
1750 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
3987a2d3
OG		 1751 ibqp->qp_type == IB_QPT_UD ||
1752 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 1753 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 1754 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1755 qp->mlx4_ib_qp_type &
1756 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 1757 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 1758 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1759 context->pri_path.fl = 0x80;
1760 } else {
1761 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1762 context->pri_path.fl = 0x80;
225c7b1f 1763 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 1764 }
2f5bb473
JM		 1765 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1766 IB_LINK_LAYER_ETHERNET) {
1767 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1768 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1769 context->pri_path.feup = 1 << 7; /* don't fsm */
1770 /* handle smac_index */
1771 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1772 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1773 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1774 err = handle_eth_ud_smac_index(dev, qp, (u8 *)attr->smac, context);
bede98e7
MD		 1775 if (err) {
1776 err = -EINVAL;
1777 goto out;
1778 }
9433c188
MB		 1779 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1780 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 1781 }
1782 }
225c7b1f
RD		 1783 }
1784
d2fce8a9 1785 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 1786 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1787 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 1788 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1789 /* set QP to receive both tunneled & non-tunneled packets */
8e1a03b6 1790 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
d2fce8a9
OG		 1791 context->srqn = cpu_to_be32(7 << 28);
1792 }
1793 }
3528f696 1794
297e0dad
MS		 1795 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1796 int is_eth = rdma_port_get_link_layer(
1797 &dev->ib_dev, qp->port) ==
1798 IB_LINK_LAYER_ETHERNET;
1799 if (is_eth) {
1800 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1801 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1802 }
1803 }
1804
1805
225c7b1f
RD		 1806 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1807 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1808 sqd_event = 1;
1809 else
1810 sqd_event = 0;
1811
d57f5f72
VS		 1812 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1813 context->rlkey |= (1 << 4);
1814
c0be5fb5
EC		 1815 /*
1816 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1817 * ownership bits of the send queue are set and the SQ
1818 * headroom is stamped so that the hardware doesn't start
1819 * processing stale work requests.
c0be5fb5
EC		 1820 */
1821 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1822 struct mlx4_wqe_ctrl_seg *ctrl;
1823 int i;
1824
0e6e7416 1825 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1826 ctrl = get_send_wqe(qp, i);
1827 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553
EC		 1828 if (qp->sq_max_wqes_per_wr == 1)
1829 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
0e6e7416 1830
ea54b10c 1831 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 1832 }
1833 }
1834
225c7b1f
RD		 1835 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1836 to_mlx4_state(new_state), context, optpar,
1837 sqd_event, &qp->mqp);
1838 if (err)
1839 goto out;
1840
1841 qp->state = new_state;
1842
1843 if (attr_mask & IB_QP_ACCESS_FLAGS)
1844 qp->atomic_rd_en = attr->qp_access_flags;
1845 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1846 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 1847 if (attr_mask & IB_QP_PORT) {
225c7b1f 1848 qp->port = attr->port_num;
fa417f7b
EC		 1849 update_mcg_macs(dev, qp);
1850 }
225c7b1f
RD		 1851 if (attr_mask & IB_QP_ALT_PATH)
1852 qp->alt_port = attr->alt_port_num;
1853
1854 if (is_sqp(dev, qp))
1855 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1856
1857 /*
1858 * If we moved QP0 to RTR, bring the IB link up; if we moved
1859 * QP0 to RESET or ERROR, bring the link back down.
1860 */
1861 if (is_qp0(dev, qp)) {
1862 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 1863 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 1864 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 1865 qp->port);
225c7b1f
RD		 1866
1867 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1868 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1869 mlx4_CLOSE_PORT(dev->dev, qp->port);
1870 }
1871
1872 /*
1873 * If we moved a kernel QP to RESET, clean up all old CQ
1874 * entries and reinitialize the QP.
1875 */
2f5bb473
JM		 1876 if (new_state == IB_QPS_RESET) {
1877 if (!ibqp->uobject) {
1878 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1879 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1880 if (send_cq != recv_cq)
1881 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1882
1883 qp->rq.head = 0;
1884 qp->rq.tail = 0;
1885 qp->sq.head = 0;
1886 qp->sq.tail = 0;
1887 qp->sq_next_wqe = 0;
1888 if (qp->rq.wqe_cnt)
1889 *qp->db.db = 0;
225c7b1f 1890
2f5bb473
JM		 1891 if (qp->flags & MLX4_IB_QP_NETIF)
1892 mlx4_ib_steer_qp_reg(dev, qp, 0);
1893 }
25476b02 1894 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1895 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1896 qp->pri.smac = 0;
25476b02 1897 qp->pri.smac_port = 0;
2f5bb473
JM		 1898 }
1899 if (qp->alt.smac) {
1900 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1901 qp->alt.smac = 0;
1902 }
1903 if (qp->pri.vid < 0x1000) {
1904 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1905 qp->pri.vid = 0xFFFF;
1906 qp->pri.candidate_vid = 0xFFFF;
1907 qp->pri.update_vid = 0;
1908 }
c1c98501 1909
2f5bb473
JM		 1910 if (qp->alt.vid < 0x1000) {
1911 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1912 qp->alt.vid = 0xFFFF;
1913 qp->alt.candidate_vid = 0xFFFF;
1914 qp->alt.update_vid = 0;
1915 }
225c7b1f 1916 }
225c7b1f 1917out:
7b59f0f9
EBE		 1918 if (err && qp->counter_index)
1919 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 1920 if (err && steer_qp)
1921 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 1922 kfree(context);
25476b02
JM		 1923 if (qp->pri.candidate_smac ||
1924 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 1925 if (err) {
1926 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1927 } else {
25476b02 1928 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 1929 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1930 qp->pri.smac = qp->pri.candidate_smac;
1931 qp->pri.smac_index = qp->pri.candidate_smac_index;
1932 qp->pri.smac_port = qp->pri.candidate_smac_port;
1933 }
1934 qp->pri.candidate_smac = 0;
1935 qp->pri.candidate_smac_index = 0;
1936 qp->pri.candidate_smac_port = 0;
1937 }
1938 if (qp->alt.candidate_smac) {
1939 if (err) {
1940 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1941 } else {
1942 if (qp->alt.smac)
1943 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1944 qp->alt.smac = qp->alt.candidate_smac;
1945 qp->alt.smac_index = qp->alt.candidate_smac_index;
1946 qp->alt.smac_port = qp->alt.candidate_smac_port;
1947 }
1948 qp->alt.candidate_smac = 0;
1949 qp->alt.candidate_smac_index = 0;
1950 qp->alt.candidate_smac_port = 0;
1951 }
1952
1953 if (qp->pri.update_vid) {
1954 if (err) {
1955 if (qp->pri.candidate_vid < 0x1000)
1956 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1957 qp->pri.candidate_vid);
1958 } else {
1959 if (qp->pri.vid < 0x1000)
1960 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1961 qp->pri.vid);
1962 qp->pri.vid = qp->pri.candidate_vid;
1963 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1964 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
1965 }
1966 qp->pri.candidate_vid = 0xFFFF;
1967 qp->pri.update_vid = 0;
1968 }
1969
1970 if (qp->alt.update_vid) {
1971 if (err) {
1972 if (qp->alt.candidate_vid < 0x1000)
1973 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
1974 qp->alt.candidate_vid);
1975 } else {
1976 if (qp->alt.vid < 0x1000)
1977 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
1978 qp->alt.vid);
1979 qp->alt.vid = qp->alt.candidate_vid;
1980 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
1981 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
1982 }
1983 qp->alt.candidate_vid = 0xFFFF;
1984 qp->alt.update_vid = 0;
1985 }
1986
225c7b1f
RD		 1987 return err;
1988}
1989
65adfa91
MT		 1990int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1991 int attr_mask, struct ib_udata *udata)
1992{
1993 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1994 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1995 enum ib_qp_state cur_state, new_state;
1996 int err = -EINVAL;
297e0dad 1997 int ll;
65adfa91
MT		 1998 mutex_lock(&qp->mutex);
1999
2000 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2001 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2002
297e0dad
MS		 2003 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2004 ll = IB_LINK_LAYER_UNSPECIFIED;
2005 } else {
2006 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2007 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2008 }
dd5f03be
MB		 2009
2010 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 2011 attr_mask, ll)) {
b1d8eb5a
JM		 2012 pr_debug("qpn 0x%x: invalid attribute mask specified "
2013 "for transition %d to %d. qp_type %d,"
2014 " attr_mask 0x%x\n",
2015 ibqp->qp_num, cur_state, new_state,
2016 ibqp->qp_type, attr_mask);
65adfa91 2017 goto out;
b1d8eb5a 2018 }
65adfa91 2019
c6215745
MS		 2020 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2021 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2022 if ((ibqp->qp_type == IB_QPT_RC) ||
2023 (ibqp->qp_type == IB_QPT_UD) ||
2024 (ibqp->qp_type == IB_QPT_UC) ||
2025 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2026 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2027 attr->port_num = mlx4_ib_bond_next_port(dev);
2028 }
2029 } else {
2030 /* no sense in changing port_num
2031 * when ports are bonded */
2032 attr_mask &= ~IB_QP_PORT;
2033 }
2034 }
2035
65adfa91 2036 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2037 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2038 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2039 "for transition %d to %d. qp_type %d\n",
2040 ibqp->qp_num, attr->port_num, cur_state,
2041 new_state, ibqp->qp_type);
65adfa91
MT		 2042 goto out;
2043 }
2044
3987a2d3
OG		 2045 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2046 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2047 IB_LINK_LAYER_ETHERNET))
2048 goto out;
2049
5ae2a7a8
RD		 2050 if (attr_mask & IB_QP_PKEY_INDEX) {
2051 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2052 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2053 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2054 "for transition %d to %d. qp_type %d\n",
2055 ibqp->qp_num, attr->pkey_index, cur_state,
2056 new_state, ibqp->qp_type);
5ae2a7a8 2057 goto out;
b1d8eb5a 2058 }
5ae2a7a8
RD		 2059 }
2060
65adfa91
MT		 2061 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2062 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2063 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2064 "Transition %d to %d. qp_type %d\n",
2065 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2066 new_state, ibqp->qp_type);
65adfa91
MT		 2067 goto out;
2068 }
2069
2070 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2071 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2072 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2073 "Transition %d to %d. qp_type %d\n",
2074 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2075 new_state, ibqp->qp_type);
65adfa91
MT		 2076 goto out;
2077 }
2078
2079 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2080 err = 0;
2081 goto out;
2082 }
2083
65adfa91
MT		 2084 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2085
c6215745
MS		 2086 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2087 attr->port_num = 1;
2088
65adfa91
MT		 2089out:
2090 mutex_unlock(&qp->mutex);
2091 return err;
2092}
2093
99ec41d0
JM		 2094static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2095{
2096 int i;
2097 for (i = 0; i < dev->caps.num_ports; i++) {
2098 if (qpn == dev->caps.qp0_proxy[i] ||
2099 qpn == dev->caps.qp0_tunnel[i]) {
2100 *qkey = dev->caps.qp0_qkey[i];
2101 return 0;
2102 }
2103 }
2104 return -EINVAL;
2105}
2106
1ffeb2eb
JM		 2107static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2108 struct ib_send_wr *wr,
2109 void *wqe, unsigned *mlx_seg_len)
2110{
2111 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2112 struct ib_device *ib_dev = &mdev->ib_dev;
2113 struct mlx4_wqe_mlx_seg *mlx = wqe;
2114 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2115 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2116 u16 pkey;
2117 u32 qkey;
2118 int send_size;
2119 int header_size;
2120 int spc;
2121 int i;
2122
2123 if (wr->opcode != IB_WR_SEND)
2124 return -EINVAL;
2125
2126 send_size = 0;
2127
2128 for (i = 0; i < wr->num_sge; ++i)
2129 send_size += wr->sg_list[i].length;
2130
2131 /* for proxy-qp0 sends, need to add in size of tunnel header */
2132 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2133 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2134 send_size += sizeof (struct mlx4_ib_tunnel_header);
2135
2136 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
2137
2138 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2139 sqp->ud_header.lrh.service_level =
2140 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2141 sqp->ud_header.lrh.destination_lid =
2142 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2143 sqp->ud_header.lrh.source_lid =
2144 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2145 }
2146
2147 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2148
2149 /* force loopback */
2150 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2151 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2152
2153 sqp->ud_header.lrh.virtual_lane = 0;
2154 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2155 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2156 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2157 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2158 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2159 else
2160 sqp->ud_header.bth.destination_qpn =
47605df9 2161 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 2162
2163 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2164 if (mlx4_is_master(mdev->dev)) {
2165 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2166 return -EINVAL;
2167 } else {
2168 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2169 return -EINVAL;
2170 }
1ffeb2eb
JM		 2171 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2172 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2173
2174 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2175 sqp->ud_header.immediate_present = 0;
2176
2177 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2178
2179 /*
2180 * Inline data segments may not cross a 64 byte boundary. If
2181 * our UD header is bigger than the space available up to the
2182 * next 64 byte boundary in the WQE, use two inline data
2183 * segments to hold the UD header.
2184 */
2185 spc = MLX4_INLINE_ALIGN -
2186 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2187 if (header_size <= spc) {
2188 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2189 memcpy(inl + 1, sqp->header_buf, header_size);
2190 i = 1;
2191 } else {
2192 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2193 memcpy(inl + 1, sqp->header_buf, spc);
2194
2195 inl = (void *) (inl + 1) + spc;
2196 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2197 /*
2198 * Need a barrier here to make sure all the data is
2199 * visible before the byte_count field is set.
2200 * Otherwise the HCA prefetcher could grab the 64-byte
2201 * chunk with this inline segment and get a valid (!=
2202 * 0xffffffff) byte count but stale data, and end up
2203 * generating a packet with bad headers.
2204 *
2205 * The first inline segment's byte_count field doesn't
2206 * need a barrier, because it comes after a
2207 * control/MLX segment and therefore is at an offset
2208 * of 16 mod 64.
2209 */
2210 wmb();
2211 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2212 i = 2;
2213 }
2214
2215 *mlx_seg_len =
2216 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2217 return 0;
2218}
2219
3e0629cb
JM		 2220static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2221{
2222 int i;
2223
2224 for (i = ETH_ALEN; i; i--) {
2225 dst_mac[i - 1] = src_mac & 0xff;
2226 src_mac >>= 8;
2227 }
2228}
2229
225c7b1f 2230static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
f438000f 2231 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2232{
a478868a 2233 struct ib_device *ib_dev = sqp->qp.ibqp.device;
225c7b1f 2234 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2235 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f
RD		 2236 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2237 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
4c3eb3ca 2238 union ib_gid sgid;
225c7b1f
RD		 2239 u16 pkey;
2240 int send_size;
2241 int header_size;
e61ef241 2242 int spc;
225c7b1f 2243 int i;
1ffeb2eb 2244 int err = 0;
57d88cff 2245 u16 vlan = 0xffff;
a29bec12
RD		 2246 bool is_eth;
2247 bool is_vlan = false;
2248 bool is_grh;
225c7b1f
RD		 2249
2250 send_size = 0;
2251 for (i = 0; i < wr->num_sge; ++i)
2252 send_size += wr->sg_list[i].length;
2253
fa417f7b
EC		 2254 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2255 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 2256 if (is_eth) {
1ffeb2eb
JM		 2257 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2258 /* When multi-function is enabled, the ib_core gid
2259 * indexes don't necessarily match the hw ones, so
2260 * we must use our own cache */
6ee51a4e
JM		 2261 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2262 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2263 ah->av.ib.gid_index, &sgid.raw[0]);
2264 if (err)
2265 return err;
1ffeb2eb
JM		 2266 } else {
2267 err = ib_get_cached_gid(ib_dev,
2268 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2269 ah->av.ib.gid_index, &sgid);
2270 if (err)
2271 return err;
2272 }
2273
0e9855db 2274 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 2275 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2276 is_vlan = 1;
2277 }
4c3eb3ca
EC		 2278 }
2279 ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
fa417f7b
EC		 2280
2281 if (!is_eth) {
2282 sqp->ud_header.lrh.service_level =
2283 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2284 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2285 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2286 }
225c7b1f 2287
fa417f7b 2288 if (is_grh) {
225c7b1f 2289 sqp->ud_header.grh.traffic_class =
fa417f7b 2290 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 2291 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 2292 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2293 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
6ee51a4e
JM		 2294 if (is_eth)
2295 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2296 else {
1ffeb2eb
JM		 2297 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2298 /* When multi-function is enabled, the ib_core gid
2299 * indexes don't necessarily match the hw ones, so
2300 * we must use our own cache */
2301 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2302 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2303 subnet_prefix;
2304 sqp->ud_header.grh.source_gid.global.interface_id =
2305 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2306 guid_cache[ah->av.ib.gid_index];
2307 } else
2308 ib_get_cached_gid(ib_dev,
2309 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2310 ah->av.ib.gid_index,
2311 &sqp->ud_header.grh.source_gid);
6ee51a4e 2312 }
225c7b1f 2313 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 2314 ah->av.ib.dgid, 16);
225c7b1f
RD		 2315 }
2316
2317 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 2318
2319 if (!is_eth) {
2320 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2321 (sqp->ud_header.lrh.destination_lid ==
2322 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2323 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 2324 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2325 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 2326 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2327 }
225c7b1f
RD		 2328
2329 switch (wr->opcode) {
2330 case IB_WR_SEND:
2331 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2332 sqp->ud_header.immediate_present = 0;
2333 break;
2334 case IB_WR_SEND_WITH_IMM:
2335 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2336 sqp->ud_header.immediate_present = 1;
0f39cf3d 2337 sqp->ud_header.immediate_data = wr->ex.imm_data;
225c7b1f
RD		 2338 break;
2339 default:
2340 return -EINVAL;
2341 }
2342
fa417f7b 2343 if (is_eth) {
6ee51a4e
JM		 2344 struct in6_addr in6;
2345
c0c1d3d7
OD		 2346 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2347
2348 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b
EC		 2349
2350 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2351 /* FIXME: cache smac value? */
6ee51a4e
JM		 2352 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2353 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2354 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 2355
3e0629cb
JM		 2356 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2357 u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2358 u8 smac[ETH_ALEN];
2359
2360 mlx4_u64_to_smac(smac, mac);
2361 memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2362 } else {
2363 /* use the src mac of the tunnel */
2364 memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2365 }
2366
fa417f7b
EC		 2367 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2368 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca
EC		 2369 if (!is_vlan) {
2370 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2371 } else {
4c3eb3ca 2372 sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
4c3eb3ca
EC		 2373 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2374 }
fa417f7b
EC		 2375 } else {
2376 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
2377 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2378 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2379 }
225c7b1f
RD		 2380 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2381 if (!sqp->qp.ibqp.qp_num)
2382 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2383 else
2384 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
2385 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2386 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2387 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2388 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
2389 sqp->qkey : wr->wr.ud.remote_qkey);
2390 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2391
2392 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2393
2394 if (0) {
987c8f8f 2395 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 2396 for (i = 0; i < header_size / 4; ++i) {
2397 if (i % 8 == 0)
987c8f8f
SP		 2398 pr_err(" [%02x] ", i * 4);
2399 pr_cont(" %08x",
2400 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 2401 if ((i + 1) % 8 == 0)
987c8f8f 2402 pr_cont("\n");
225c7b1f 2403 }
987c8f8f 2404 pr_err("\n");
225c7b1f
RD		 2405 }
2406
e61ef241
RD		 2407 /*
2408 * Inline data segments may not cross a 64 byte boundary. If
2409 * our UD header is bigger than the space available up to the
2410 * next 64 byte boundary in the WQE, use two inline data
2411 * segments to hold the UD header.
2412 */
2413 spc = MLX4_INLINE_ALIGN -
2414 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2415 if (header_size <= spc) {
2416 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2417 memcpy(inl + 1, sqp->header_buf, header_size);
2418 i = 1;
2419 } else {
2420 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2421 memcpy(inl + 1, sqp->header_buf, spc);
2422
2423 inl = (void *) (inl + 1) + spc;
2424 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2425 /*
2426 * Need a barrier here to make sure all the data is
2427 * visible before the byte_count field is set.
2428 * Otherwise the HCA prefetcher could grab the 64-byte
2429 * chunk with this inline segment and get a valid (!=
2430 * 0xffffffff) byte count but stale data, and end up
2431 * generating a packet with bad headers.
2432 *
2433 * The first inline segment's byte_count field doesn't
2434 * need a barrier, because it comes after a
2435 * control/MLX segment and therefore is at an offset
2436 * of 16 mod 64.
2437 */
2438 wmb();
2439 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2440 i = 2;
2441 }
225c7b1f 2442
f438000f
RD		 2443 *mlx_seg_len =
2444 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2445 return 0;
225c7b1f
RD		 2446}
2447
2448static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2449{
2450 unsigned cur;
2451 struct mlx4_ib_cq *cq;
2452
2453 cur = wq->head - wq->tail;
0e6e7416 2454 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 2455 return 0;
2456
2457 cq = to_mcq(ib_cq);
2458 spin_lock(&cq->lock);
2459 cur = wq->head - wq->tail;
2460 spin_unlock(&cq->lock);
2461
0e6e7416 2462 return cur + nreq >= wq->max_post;
225c7b1f
RD		 2463}
2464
95d04f07
RD		 2465static __be32 convert_access(int acc)
2466{
6ff63e19
SM		 2467 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2468 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2469 (acc & IB_ACCESS_REMOTE_WRITE ?
2470 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2471 (acc & IB_ACCESS_REMOTE_READ ?
2472 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 2473 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2474 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2475}
2476
2477static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
2478{
2479 struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
29bdc883
VS		 2480 int i;
2481
2482 for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2b6b7d4b 2483 mfrpl->mapped_page_list[i] =
29bdc883
VS		 2484 cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
2485 MLX4_MTT_FLAG_PRESENT);
95d04f07
RD		 2486
2487 fseg->flags = convert_access(wr->wr.fast_reg.access_flags);
2488 fseg->mem_key = cpu_to_be32(wr->wr.fast_reg.rkey);
2489 fseg->buf_list = cpu_to_be64(mfrpl->map);
2490 fseg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
2491 fseg->reg_len = cpu_to_be64(wr->wr.fast_reg.length);
2492 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2493 fseg->page_size = cpu_to_be32(wr->wr.fast_reg.page_shift);
2494 fseg->reserved[0] = 0;
2495 fseg->reserved[1] = 0;
2496}
2497
6ff63e19
SM		 2498static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr)
2499{
2500 bseg->flags1 =
2501 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) &
2502 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ |
2503 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2504 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2505 bseg->flags2 = 0;
2506 if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2)
2507 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2508 if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED)
2509 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2510 bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey);
2511 bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey);
2512 bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr);
2513 bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length);
2514}
2515
95d04f07
RD		 2516static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2517{
aee38fad
SM		 2518 memset(iseg, 0, sizeof(*iseg));
2519 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 2520}
2521
0fbfa6a9
RD		 2522static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2523 u64 remote_addr, u32 rkey)
2524{
2525 rseg->raddr = cpu_to_be64(remote_addr);
2526 rseg->rkey = cpu_to_be32(rkey);
2527 rseg->reserved = 0;
2528}
2529
2530static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2531{
2532 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2533 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2534 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
6fa8f719
VS		 2535 } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2536 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2537 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add_mask);
0fbfa6a9
RD		 2538 } else {
2539 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2540 aseg->compare = 0;
2541 }
2542
2543}
2544
6fa8f719
VS		 2545static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2546 struct ib_send_wr *wr)
2547{
2548 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2549 aseg->swap_add_mask = cpu_to_be64(wr->wr.atomic.swap_mask);
2550 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
2551 aseg->compare_mask = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2552}
2553
0fbfa6a9 2554static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
80a2dcd8 2555 struct ib_send_wr *wr)
0fbfa6a9
RD		 2556{
2557 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2558 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2559 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
fa417f7b
EC		 2560 dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2561 memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
0fbfa6a9
RD		 2562}
2563
1ffeb2eb
JM		 2564static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2565 struct mlx4_wqe_datagram_seg *dseg,
97982f5a
JM		 2566 struct ib_send_wr *wr,
2567 enum mlx4_ib_qp_type qpt)
1ffeb2eb
JM		 2568{
2569 union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2570 struct mlx4_av sqp_av = {0};
2571 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2572
2573 /* force loopback */
2574 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2575 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2576 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2577 cpu_to_be32(0xf0000000);
2578
2579 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a
JM		 2580 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2581 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2582 else
2583 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
47605df9
JM		 2584 /* Use QKEY from the QP context, which is set by master */
2585 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 2586}
2587
2588static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2589{
2590 struct mlx4_wqe_inline_seg *inl = wqe;
2591 struct mlx4_ib_tunnel_header hdr;
2592 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2593 int spc;
2594 int i;
2595
2596 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2597 hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2598 hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2599 hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
5ea8bbfc
JM		 2600 memcpy(hdr.mac, ah->av.eth.mac, 6);
2601 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 2602
2603 spc = MLX4_INLINE_ALIGN -
2604 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2605 if (sizeof (hdr) <= spc) {
2606 memcpy(inl + 1, &hdr, sizeof (hdr));
2607 wmb();
2608 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2609 i = 1;
2610 } else {
2611 memcpy(inl + 1, &hdr, spc);
2612 wmb();
2613 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2614
2615 inl = (void *) (inl + 1) + spc;
2616 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2617 wmb();
2618 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2619 i = 2;
2620 }
2621
2622 *mlx_seg_len =
2623 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2624}
2625
6e694ea3
JM		 2626static void set_mlx_icrc_seg(void *dseg)
2627{
2628 u32 *t = dseg;
2629 struct mlx4_wqe_inline_seg *iseg = dseg;
2630
2631 t[1] = 0;
2632
2633 /*
2634 * Need a barrier here before writing the byte_count field to
2635 * make sure that all the data is visible before the
2636 * byte_count field is set. Otherwise, if the segment begins
2637 * a new cacheline, the HCA prefetcher could grab the 64-byte
2638 * chunk and get a valid (!= * 0xffffffff) byte count but
2639 * stale data, and end up sending the wrong data.
2640 */
2641 wmb();
2642
2643 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2644}
2645
2646static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 2647{
d420d9e3
RD		 2648 dseg->lkey = cpu_to_be32(sg->lkey);
2649 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 2650
2651 /*
2652 * Need a barrier here before writing the byte_count field to
2653 * make sure that all the data is visible before the
2654 * byte_count field is set. Otherwise, if the segment begins
2655 * a new cacheline, the HCA prefetcher could grab the 64-byte
2656 * chunk and get a valid (!= * 0xffffffff) byte count but
2657 * stale data, and end up sending the wrong data.
2658 */
2659 wmb();
2660
2661 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 2662}
2663
2242fa4f
RD		 2664static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2665{
2666 dseg->byte_count = cpu_to_be32(sg->length);
2667 dseg->lkey = cpu_to_be32(sg->lkey);
2668 dseg->addr = cpu_to_be64(sg->addr);
2669}
2670
47b37475 2671static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
0fd7e1d8 2672 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 2673 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e
EC		 2674{
2675 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2676
417608c2
EC		 2677 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2678 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 2679
2680 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2681 wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2682 return -EINVAL;
2683
2684 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2685
ca9b590c 2686 *lso_hdr_sz = cpu_to_be32(wr->wr.ud.mss << 16 | wr->wr.ud.hlen);
b832be1e
EC		 2687 *lso_seg_len = halign;
2688 return 0;
2689}
2690
95d04f07
RD		 2691static __be32 send_ieth(struct ib_send_wr *wr)
2692{
2693 switch (wr->opcode) {
2694 case IB_WR_SEND_WITH_IMM:
2695 case IB_WR_RDMA_WRITE_WITH_IMM:
2696 return wr->ex.imm_data;
2697
2698 case IB_WR_SEND_WITH_INV:
2699 return cpu_to_be32(wr->ex.invalidate_rkey);
2700
2701 default:
2702 return 0;
2703 }
2704}
2705
1ffeb2eb
JM		 2706static void add_zero_len_inline(void *wqe)
2707{
2708 struct mlx4_wqe_inline_seg *inl = wqe;
2709 memset(wqe, 0, 16);
2710 inl->byte_count = cpu_to_be32(1 << 31);
2711}
2712
225c7b1f
RD		 2713int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2714 struct ib_send_wr **bad_wr)
2715{
2716 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2717 void *wqe;
2718 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 2719 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 2720 unsigned long flags;
2721 int nreq;
2722 int err = 0;
ea54b10c
JM		 2723 unsigned ind;
2724 int uninitialized_var(stamp);
2725 int uninitialized_var(size);
a3d8e159 2726 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 2727 __be32 dummy;
2728 __be32 *lso_wqe;
2729 __be32 uninitialized_var(lso_hdr_sz);
417608c2 2730 __be32 blh;
225c7b1f 2731 int i;
35f05dab 2732 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 2733
96db0e03 2734 spin_lock_irqsave(&qp->sq.lock, flags);
35f05dab
YH		 2735 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2736 err = -EIO;
2737 *bad_wr = wr;
2738 nreq = 0;
2739 goto out;
2740 }
225c7b1f 2741
ea54b10c 2742 ind = qp->sq_next_wqe;
225c7b1f
RD		 2743
2744 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 2745 lso_wqe = &dummy;
417608c2 2746 blh = 0;
0fd7e1d8 2747
225c7b1f
RD		 2748 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2749 err = -ENOMEM;
2750 *bad_wr = wr;
2751 goto out;
2752 }
2753
2754 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2755 err = -EINVAL;
2756 *bad_wr = wr;
2757 goto out;
2758 }
2759
0e6e7416 2760 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 2761 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 2762
2763 ctrl->srcrb_flags =
2764 (wr->send_flags & IB_SEND_SIGNALED ?
2765 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2766 (wr->send_flags & IB_SEND_SOLICITED ?
2767 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 2768 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2769 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2770 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 2771 qp->sq_signal_bits;
2772
95d04f07 2773 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 2774
2775 wqe += sizeof *ctrl;
2776 size = sizeof *ctrl / 16;
2777
1ffeb2eb
JM		 2778 switch (qp->mlx4_ib_qp_type) {
2779 case MLX4_IB_QPT_RC:
2780 case MLX4_IB_QPT_UC:
225c7b1f
RD		 2781 switch (wr->opcode) {
2782 case IB_WR_ATOMIC_CMP_AND_SWP:
2783 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 2784 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
0fbfa6a9
RD		 2785 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2786 wr->wr.atomic.rkey);
225c7b1f
RD		 2787 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2788
0fbfa6a9 2789 set_atomic_seg(wqe, wr);
225c7b1f 2790 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 2791
225c7b1f
RD		 2792 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2793 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 2794
2795 break;
2796
2797 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2798 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2799 wr->wr.atomic.rkey);
2800 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2801
2802 set_masked_atomic_seg(wqe, wr);
2803 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
2804
2805 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2806 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 2807
2808 break;
2809
2810 case IB_WR_RDMA_READ:
2811 case IB_WR_RDMA_WRITE:
2812 case IB_WR_RDMA_WRITE_WITH_IMM:
0fbfa6a9
RD		 2813 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2814 wr->wr.rdma.rkey);
225c7b1f
RD		 2815 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2816 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 2817 break;
95d04f07
RD		 2818
2819 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 2820 ctrl->srcrb_flags |=
2821 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2822 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2823 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
2824 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2825 break;
2826
2827 case IB_WR_FAST_REG_MR:
2ac6bf4d
JM		 2828 ctrl->srcrb_flags |=
2829 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2830 set_fmr_seg(wqe, wr);
2831 wqe += sizeof (struct mlx4_wqe_fmr_seg);
2832 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2833 break;
225c7b1f 2834
6ff63e19
SM		 2835 case IB_WR_BIND_MW:
2836 ctrl->srcrb_flags |=
2837 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2838 set_bind_seg(wqe, wr);
2839 wqe += sizeof(struct mlx4_wqe_bind_seg);
2840 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2841 break;
225c7b1f
RD		 2842 default:
2843 /* No extra segments required for sends */
2844 break;
2845 }
2846 break;
2847
1ffeb2eb
JM		 2848 case MLX4_IB_QPT_TUN_SMI_OWNER:
2849 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2850 if (unlikely(err)) {
2851 *bad_wr = wr;
2852 goto out;
2853 }
2854 wqe += seglen;
2855 size += seglen / 16;
2856 break;
2857 case MLX4_IB_QPT_TUN_SMI:
2858 case MLX4_IB_QPT_TUN_GSI:
2859 /* this is a UD qp used in MAD responses to slaves. */
2860 set_datagram_seg(wqe, wr);
2861 /* set the forced-loopback bit in the data seg av */
2862 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2863 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2864 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2865 break;
2866 case MLX4_IB_QPT_UD:
80a2dcd8 2867 set_datagram_seg(wqe, wr);
225c7b1f
RD		 2868 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2869 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 2870
2871 if (wr->opcode == IB_WR_LSO) {
417608c2 2872 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
b832be1e
EC		 2873 if (unlikely(err)) {
2874 *bad_wr = wr;
2875 goto out;
2876 }
0fd7e1d8 2877 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 2878 wqe += seglen;
2879 size += seglen / 16;
2880 }
225c7b1f
RD		 2881 break;
2882
1ffeb2eb 2883 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1ffeb2eb
JM		 2884 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2885 if (unlikely(err)) {
2886 *bad_wr = wr;
2887 goto out;
2888 }
2889 wqe += seglen;
2890 size += seglen / 16;
2891 /* to start tunnel header on a cache-line boundary */
2892 add_zero_len_inline(wqe);
2893 wqe += 16;
2894 size++;
2895 build_tunnel_header(wr, wqe, &seglen);
2896 wqe += seglen;
2897 size += seglen / 16;
2898 break;
2899 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 2900 case MLX4_IB_QPT_PROXY_GSI:
2901 /* If we are tunneling special qps, this is a UD qp.
2902 * In this case we first add a UD segment targeting
2903 * the tunnel qp, and then add a header with address
2904 * information */
97982f5a
JM		 2905 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr,
2906 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 2907 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2908 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2909 build_tunnel_header(wr, wqe, &seglen);
2910 wqe += seglen;
2911 size += seglen / 16;
2912 break;
2913
2914 case MLX4_IB_QPT_SMI:
2915 case MLX4_IB_QPT_GSI:
f438000f
RD		 2916 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2917 if (unlikely(err)) {
225c7b1f
RD		 2918 *bad_wr = wr;
2919 goto out;
2920 }
f438000f
RD		 2921 wqe += seglen;
2922 size += seglen / 16;
225c7b1f
RD		 2923 break;
2924
2925 default:
2926 break;
2927 }
2928
6e694ea3
JM		 2929 /*
2930 * Write data segments in reverse order, so as to
2931 * overwrite cacheline stamp last within each
2932 * cacheline. This avoids issues with WQE
2933 * prefetching.
2934 */
225c7b1f 2935
6e694ea3
JM		 2936 dseg = wqe;
2937 dseg += wr->num_sge - 1;
2938 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 2939
2940 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 2941 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2942 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2943 qp->mlx4_ib_qp_type &
2944 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 2945 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 2946 size += sizeof (struct mlx4_wqe_data_seg) / 16;
2947 }
2948
6e694ea3
JM		 2949 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2950 set_data_seg(dseg, wr->sg_list + i);
2951
0fd7e1d8
RD		 2952 /*
2953 * Possibly overwrite stamping in cacheline with LSO
2954 * segment only after making sure all data segments
2955 * are written.
2956 */
2957 wmb();
2958 *lso_wqe = lso_hdr_sz;
2959
225c7b1f
RD		 2960 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2961 MLX4_WQE_CTRL_FENCE : 0) | size;
2962
2963 /*
2964 * Make sure descriptor is fully written before
2965 * setting ownership bit (because HW can start
2966 * executing as soon as we do).
2967 */
2968 wmb();
2969
59b0ed12 2970 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 2971 *bad_wr = wr;
225c7b1f
RD		 2972 err = -EINVAL;
2973 goto out;
2974 }
2975
2976 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 2977 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 2978
ea54b10c
JM		 2979 stamp = ind + qp->sq_spare_wqes;
2980 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2981
0e6e7416
RD		 2982 /*
2983 * We can improve latency by not stamping the last
2984 * send queue WQE until after ringing the doorbell, so
2985 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 2986 *
2987 * Same optimization applies to padding with NOP wqe
2988 * in case of WQE shrinking (used to prevent wrap-around
2989 * in the middle of WR).
0e6e7416 2990 */
ea54b10c
JM		 2991 if (wr->next) {
2992 stamp_send_wqe(qp, stamp, size * 16);
2993 ind = pad_wraparound(qp, ind);
2994 }
225c7b1f
RD		 2995 }
2996
2997out:
2998 if (likely(nreq)) {
2999 qp->sq.head += nreq;
3000
3001 /*
3002 * Make sure that descriptors are written before
3003 * doorbell record.
3004 */
3005 wmb();
3006
3007 writel(qp->doorbell_qpn,
3008 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3009
3010 /*
3011 * Make sure doorbells don't leak out of SQ spinlock
3012 * and reach the HCA out of order.
3013 */
3014 mmiowb();
0e6e7416 3015
ea54b10c
JM		 3016 stamp_send_wqe(qp, stamp, size * 16);
3017
3018 ind = pad_wraparound(qp, ind);
3019 qp->sq_next_wqe = ind;
225c7b1f
RD		 3020 }
3021
96db0e03 3022 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3023
3024 return err;
3025}
3026
3027int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3028 struct ib_recv_wr **bad_wr)
3029{
3030 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3031 struct mlx4_wqe_data_seg *scat;
3032 unsigned long flags;
3033 int err = 0;
3034 int nreq;
3035 int ind;
1ffeb2eb 3036 int max_gs;
225c7b1f 3037 int i;
35f05dab 3038 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3039
1ffeb2eb 3040 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3041 spin_lock_irqsave(&qp->rq.lock, flags);
3042
35f05dab
YH		 3043 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3044 err = -EIO;
3045 *bad_wr = wr;
3046 nreq = 0;
3047 goto out;
3048 }
3049
0e6e7416 3050 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3051
3052 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3053 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3054 err = -ENOMEM;
3055 *bad_wr = wr;
3056 goto out;
3057 }
3058
3059 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3060 err = -EINVAL;
3061 *bad_wr = wr;
3062 goto out;
3063 }
3064
3065 scat = get_recv_wqe(qp, ind);
3066
1ffeb2eb
JM		 3067 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3068 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3069 ib_dma_sync_single_for_device(ibqp->device,
3070 qp->sqp_proxy_rcv[ind].map,
3071 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3072 DMA_FROM_DEVICE);
3073 scat->byte_count =
3074 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3075 /* use dma lkey from upper layer entry */
3076 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3077 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3078 scat++;
3079 max_gs--;
3080 }
3081
2242fa4f
RD		 3082 for (i = 0; i < wr->num_sge; ++i)
3083 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3084
1ffeb2eb 3085 if (i < max_gs) {
225c7b1f
RD		 3086 scat[i].byte_count = 0;
3087 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3088 scat[i].addr = 0;
3089 }
3090
3091 qp->rq.wrid[ind] = wr->wr_id;
3092
0e6e7416 3093 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3094 }
3095
3096out:
3097 if (likely(nreq)) {
3098 qp->rq.head += nreq;
3099
3100 /*
3101 * Make sure that descriptors are written before
3102 * doorbell record.
3103 */
3104 wmb();
3105
3106 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3107 }
3108
3109 spin_unlock_irqrestore(&qp->rq.lock, flags);
3110
3111 return err;
3112}
6a775e2b
JM		 3113
3114static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3115{
3116 switch (mlx4_state) {
3117 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3118 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3119 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3120 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3121 case MLX4_QP_STATE_SQ_DRAINING:
3122 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3123 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3124 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3125 default: return -1;
3126 }
3127}
3128
3129static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3130{
3131 switch (mlx4_mig_state) {
3132 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3133 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3134 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3135 default: return -1;
3136 }
3137}
3138
3139static int to_ib_qp_access_flags(int mlx4_flags)
3140{
3141 int ib_flags = 0;
3142
3143 if (mlx4_flags & MLX4_QP_BIT_RRE)
3144 ib_flags |= IB_ACCESS_REMOTE_READ;
3145 if (mlx4_flags & MLX4_QP_BIT_RWE)
3146 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3147 if (mlx4_flags & MLX4_QP_BIT_RAE)
3148 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3149
3150 return ib_flags;
3151}
3152
4c3eb3ca 3153static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
6a775e2b
JM		 3154 struct mlx4_qp_path *path)
3155{
4c3eb3ca
EC		 3156 struct mlx4_dev *dev = ibdev->dev;
3157 int is_eth;
3158
8fcea95a 3159 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 3160 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
3161
3162 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3163 return;
3164
4c3eb3ca
EC		 3165 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3166 IB_LINK_LAYER_ETHERNET;
3167 if (is_eth)
3168 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3169 ((path->sched_queue & 4) << 1);
3170 else
3171 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3172
6a775e2b 3173 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
6a775e2b
JM		 3174 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3175 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3176 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3177 if (ib_ah_attr->ah_flags) {
3178 ib_ah_attr->grh.sgid_index = path->mgid_index;
3179 ib_ah_attr->grh.hop_limit = path->hop_limit;
3180 ib_ah_attr->grh.traffic_class =
3181 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3182 ib_ah_attr->grh.flow_label =
586bb586 3183 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 3184 memcpy(ib_ah_attr->grh.dgid.raw,
3185 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3186 }
3187}
3188
3189int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3190 struct ib_qp_init_attr *qp_init_attr)
3191{
3192 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3193 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3194 struct mlx4_qp_context context;
3195 int mlx4_state;
0df67030
DB		 3196 int err = 0;
3197
3198 mutex_lock(&qp->mutex);
6a775e2b
JM		 3199
3200 if (qp->state == IB_QPS_RESET) {
3201 qp_attr->qp_state = IB_QPS_RESET;
3202 goto done;
3203 }
3204
3205 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3206 if (err) {
3207 err = -EINVAL;
3208 goto out;
3209 }
6a775e2b
JM		 3210
3211 mlx4_state = be32_to_cpu(context.flags) >> 28;
3212
0df67030
DB		 3213 qp->state = to_ib_qp_state(mlx4_state);
3214 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3215 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3216 qp_attr->path_mig_state =
3217 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3218 qp_attr->qkey = be32_to_cpu(context.qkey);
3219 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3220 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3221 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3222 qp_attr->qp_access_flags =
3223 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3224
3225 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4c3eb3ca
EC		 3226 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3227 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b
JM		 3228 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3229 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3230 }
3231
3232 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 3233 if (qp_attr->qp_state == IB_QPS_INIT)
3234 qp_attr->port_num = qp->port;
3235 else
3236 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 3237
3238 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3239 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3240
3241 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3242
3243 qp_attr->max_dest_rd_atomic =
3244 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3245 qp_attr->min_rnr_timer =
3246 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3247 qp_attr->timeout = context.pri_path.ackto >> 3;
3248 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3249 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3250 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3251
3252done:
3253 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 3254 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3255 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3256
6a775e2b 3257 if (!ibqp->uobject) {
7f5eb9bb
RD		 3258 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3259 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3260 } else {
3261 qp_attr->cap.max_send_wr = 0;
3262 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 3263 }
3264
7f5eb9bb
RD		 3265 /*
3266 * We don't support inline sends for kernel QPs (yet), and we
3267 * don't know what userspace's value should be.
3268 */
3269 qp_attr->cap.max_inline_data = 0;
3270
3271 qp_init_attr->cap = qp_attr->cap;
3272
521e575b
RL		 3273 qp_init_attr->create_flags = 0;
3274 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3275 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3276
3277 if (qp->flags & MLX4_IB_QP_LSO)
3278 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3279
c1c98501
MB		 3280 if (qp->flags & MLX4_IB_QP_NETIF)
3281 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3282
46db567d
DB		 3283 qp_init_attr->sq_sig_type =
3284 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3285 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3286
0df67030
DB		 3287out:
3288 mutex_unlock(&qp->mutex);
3289 return err;
6a775e2b
JM		 3290}
3291
Linux 6.x block layer and io_uring tree(s)