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net/mlx4: Add mlx4_bitmap zone allocator
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
5a0e3ad6 35#include <linux/slab.h>
fa417f7b 36#include <linux/netdevice.h>
ea54b10c 37
225c7b1f
RD		 38#include <rdma/ib_cache.h>
39#include <rdma/ib_pack.h>
4c3eb3ca 40#include <rdma/ib_addr.h>
1ffeb2eb 41#include <rdma/ib_mad.h>
225c7b1f
RD		 42
43#include <linux/mlx4/qp.h>
44
45#include "mlx4_ib.h"
46#include "user.h"
47
48enum {
49 MLX4_IB_ACK_REQ_FREQ = 8,
50};
51
52enum {
53 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 54 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
55 MLX4_IB_LINK_TYPE_IB = 0,
56 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 57};
58
59enum {
60 /*
fa417f7b 61 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 62 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
63 * tag. (LRH would only use 8 bytes, so Ethernet is the
64 * biggest case)
225c7b1f 65 */
4c3eb3ca 66 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 67 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 68};
69
fa417f7b
EC		 70enum {
71 MLX4_IB_IBOE_ETHERTYPE = 0x8915
72};
73
225c7b1f
RD		 74struct mlx4_ib_sqp {
75 struct mlx4_ib_qp qp;
76 int pkey_index;
77 u32 qkey;
78 u32 send_psn;
79 struct ib_ud_header ud_header;
80 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
81};
82
83904132 83enum {
417608c2
EC		 84 MLX4_IB_MIN_SQ_STRIDE = 6,
85 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 86};
87
3987a2d3
OG		 88enum {
89 MLX4_RAW_QP_MTU = 7,
90 MLX4_RAW_QP_MSGMAX = 31,
91};
92
297e0dad
MS		 93#ifndef ETH_ALEN
94#define ETH_ALEN 6
95#endif
96static inline u64 mlx4_mac_to_u64(u8 *addr)
97{
98 u64 mac = 0;
99 int i;
100
101 for (i = 0; i < ETH_ALEN; i++) {
102 mac <<= 8;
103 mac |= addr[i];
104 }
105 return mac;
106}
107
225c7b1f 108static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 109 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
110 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
111 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
112 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
113 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
114 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
115 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
116 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
117 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
118 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
119 [IB_WR_FAST_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
120 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
121 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
6ff63e19 122 [IB_WR_BIND_MW] = cpu_to_be32(MLX4_OPCODE_BIND_MW),
225c7b1f
RD		 123};
124
125static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
126{
127 return container_of(mqp, struct mlx4_ib_sqp, qp);
128}
129
1ffeb2eb
JM		 130static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
131{
132 if (!mlx4_is_master(dev->dev))
133 return 0;
134
47605df9
JM		 135 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
136 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
137 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 138}
139
225c7b1f
RD		 140static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
141{
47605df9
JM		 142 int proxy_sqp = 0;
143 int real_sqp = 0;
144 int i;
145 /* PPF or Native -- real SQP */
146 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
147 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
148 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
149 if (real_sqp)
150 return 1;
151 /* VF or PF -- proxy SQP */
152 if (mlx4_is_mfunc(dev->dev)) {
153 for (i = 0; i < dev->dev->caps.num_ports; i++) {
154 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
155 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
156 proxy_sqp = 1;
157 break;
158 }
159 }
160 }
161 return proxy_sqp;
225c7b1f
RD		 162}
163
1ffeb2eb 164/* used for INIT/CLOSE port logic */
225c7b1f
RD		 165static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
166{
47605df9
JM		 167 int proxy_qp0 = 0;
168 int real_qp0 = 0;
169 int i;
170 /* PPF or Native -- real QP0 */
171 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
172 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
173 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
174 if (real_qp0)
175 return 1;
176 /* VF or PF -- proxy QP0 */
177 if (mlx4_is_mfunc(dev->dev)) {
178 for (i = 0; i < dev->dev->caps.num_ports; i++) {
179 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
180 proxy_qp0 = 1;
181 break;
182 }
183 }
184 }
185 return proxy_qp0;
225c7b1f
RD		 186}
187
188static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
189{
1c69fc2a 190 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 191}
192
193static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
194{
195 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
196}
197
198static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
199{
200 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
201}
202
0e6e7416
RD		 203/*
204 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 205 * first four bytes of every 64 byte chunk with
206 * 0x7FFFFFF | (invalid_ownership_value << 31).
207 *
208 * When the max work request size is less than or equal to the WQE
209 * basic block size, as an optimization, we can stamp all WQEs with
210 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 211 */
ea54b10c 212static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 213{
d2ae16d5 214 __be32 *wqe;
0e6e7416 215 int i;
ea54b10c
JM		 216 int s;
217 int ind;
218 void *buf;
219 __be32 stamp;
9670e553 220 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 221
ea54b10c 222 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 223 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 224 for (i = 0; i < s; i += 64) {
225 ind = (i >> qp->sq.wqe_shift) + n;
226 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
227 cpu_to_be32(0xffffffff);
228 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
229 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
230 *wqe = stamp;
231 }
232 } else {
9670e553
EC		 233 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
234 s = (ctrl->fence_size & 0x3f) << 4;
ea54b10c
JM		 235 for (i = 64; i < s; i += 64) {
236 wqe = buf + i;
d2ae16d5 237 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 238 }
239 }
240}
241
242static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
243{
244 struct mlx4_wqe_ctrl_seg *ctrl;
245 struct mlx4_wqe_inline_seg *inl;
246 void *wqe;
247 int s;
248
249 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
250 s = sizeof(struct mlx4_wqe_ctrl_seg);
251
252 if (qp->ibqp.qp_type == IB_QPT_UD) {
253 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
254 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
255 memset(dgram, 0, sizeof *dgram);
256 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
257 s += sizeof(struct mlx4_wqe_datagram_seg);
258 }
259
260 /* Pad the remainder of the WQE with an inline data segment. */
261 if (size > s) {
262 inl = wqe + s;
263 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
264 }
265 ctrl->srcrb_flags = 0;
266 ctrl->fence_size = size / 16;
267 /*
268 * Make sure descriptor is fully written before setting ownership bit
269 * (because HW can start executing as soon as we do).
270 */
271 wmb();
272
273 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
274 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 275
ea54b10c
JM		 276 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
277}
278
279/* Post NOP WQE to prevent wrap-around in the middle of WR */
280static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
281{
282 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
283 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
284 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
285 ind += s;
286 }
287 return ind;
0e6e7416
RD		 288}
289
225c7b1f
RD		 290static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
291{
292 struct ib_event event;
293 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
294
295 if (type == MLX4_EVENT_TYPE_PATH_MIG)
296 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
297
298 if (ibqp->event_handler) {
299 event.device = ibqp->device;
300 event.element.qp = ibqp;
301 switch (type) {
302 case MLX4_EVENT_TYPE_PATH_MIG:
303 event.event = IB_EVENT_PATH_MIG;
304 break;
305 case MLX4_EVENT_TYPE_COMM_EST:
306 event.event = IB_EVENT_COMM_EST;
307 break;
308 case MLX4_EVENT_TYPE_SQ_DRAINED:
309 event.event = IB_EVENT_SQ_DRAINED;
310 break;
311 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
312 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
313 break;
314 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
315 event.event = IB_EVENT_QP_FATAL;
316 break;
317 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
318 event.event = IB_EVENT_PATH_MIG_ERR;
319 break;
320 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
321 event.event = IB_EVENT_QP_REQ_ERR;
322 break;
323 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
324 event.event = IB_EVENT_QP_ACCESS_ERR;
325 break;
326 default:
987c8f8f 327 pr_warn("Unexpected event type %d "
225c7b1f
RD		 328 "on QP %06x\n", type, qp->qpn);
329 return;
330 }
331
332 ibqp->event_handler(&event, ibqp->qp_context);
333 }
334}
335
1ffeb2eb 336static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 337{
338 /*
339 * UD WQEs must have a datagram segment.
340 * RC and UC WQEs might have a remote address segment.
341 * MLX WQEs need two extra inline data segments (for the UD
342 * header and space for the ICRC).
343 */
344 switch (type) {
1ffeb2eb 345 case MLX4_IB_QPT_UD:
225c7b1f 346 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 347 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 348 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 349 case MLX4_IB_QPT_PROXY_SMI_OWNER:
350 case MLX4_IB_QPT_PROXY_SMI:
351 case MLX4_IB_QPT_PROXY_GSI:
352 return sizeof (struct mlx4_wqe_ctrl_seg) +
353 sizeof (struct mlx4_wqe_datagram_seg) + 64;
354 case MLX4_IB_QPT_TUN_SMI_OWNER:
355 case MLX4_IB_QPT_TUN_GSI:
356 return sizeof (struct mlx4_wqe_ctrl_seg) +
357 sizeof (struct mlx4_wqe_datagram_seg);
358
359 case MLX4_IB_QPT_UC:
225c7b1f
RD		 360 return sizeof (struct mlx4_wqe_ctrl_seg) +
361 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 362 case MLX4_IB_QPT_RC:
225c7b1f
RD		 363 return sizeof (struct mlx4_wqe_ctrl_seg) +
364 sizeof (struct mlx4_wqe_atomic_seg) +
365 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 366 case MLX4_IB_QPT_SMI:
367 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 368 return sizeof (struct mlx4_wqe_ctrl_seg) +
369 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 370 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
371 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 372 sizeof (struct mlx4_wqe_inline_seg),
373 sizeof (struct mlx4_wqe_data_seg)) +
374 ALIGN(4 +
375 sizeof (struct mlx4_wqe_inline_seg),
376 sizeof (struct mlx4_wqe_data_seg));
377 default:
378 return sizeof (struct mlx4_wqe_ctrl_seg);
379 }
380}
381
2446304d 382static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
0a1405da 383 int is_user, int has_rq, struct mlx4_ib_qp *qp)
225c7b1f 384{
2446304d 385 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 386 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
387 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 388 return -EINVAL;
389
0a1405da 390 if (!has_rq) {
a4cd7ed8
RD		 391 if (cap->max_recv_wr)
392 return -EINVAL;
2446304d 393
0e6e7416 394 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 395 } else {
396 /* HW requires >= 1 RQ entry with >= 1 gather entry */
397 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
398 return -EINVAL;
399
0e6e7416 400 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 401 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 402 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
403 }
2446304d 404
fc2d0044
SG		 405 /* leave userspace return values as they were, so as not to break ABI */
406 if (is_user) {
407 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
408 cap->max_recv_sge = qp->rq.max_gs;
409 } else {
410 cap->max_recv_wr = qp->rq.max_post =
411 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
412 cap->max_recv_sge = min(qp->rq.max_gs,
413 min(dev->dev->caps.max_sq_sg,
414 dev->dev->caps.max_rq_sg));
415 }
2446304d
EC		 416
417 return 0;
418}
419
420static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
1ffeb2eb 421 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 422{
ea54b10c
JM		 423 int s;
424
2446304d 425 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 426 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
427 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 428 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 429 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
430 return -EINVAL;
431
432 /*
433 * For MLX transport we need 2 extra S/G entries:
434 * one for the header and one for the checksum at the end
435 */
1ffeb2eb
JM		 436 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
437 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 438 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
439 return -EINVAL;
440
ea54b10c
JM		 441 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
442 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 443 send_wqe_overhead(type, qp->flags);
225c7b1f 444
cd155c1c
RD		 445 if (s > dev->dev->caps.max_sq_desc_sz)
446 return -EINVAL;
447
0e6e7416 448 /*
ea54b10c
JM		 449 * Hermon supports shrinking WQEs, such that a single work
450 * request can include multiple units of 1 << wqe_shift. This
451 * way, work requests can differ in size, and do not have to
452 * be a power of 2 in size, saving memory and speeding up send
453 * WR posting. Unfortunately, if we do this then the
454 * wqe_index field in CQEs can't be used to look up the WR ID
455 * anymore, so we do this only if selective signaling is off.
456 *
457 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 458 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 459 * constant-sized WRs to make sure a WR is always fully within
460 * a single page-sized chunk.
461 *
462 * Finally, we use NOP work requests to pad the end of the
463 * work queue, to avoid wrap-around in the middle of WR. We
464 * set NEC bit to avoid getting completions with error for
465 * these NOP WRs, but since NEC is only supported starting
466 * with firmware 2.2.232, we use constant-sized WRs for older
467 * firmware.
468 *
469 * And, since MLX QPs only support SEND, we use constant-sized
470 * WRs in this case.
471 *
472 * We look for the smallest value of wqe_shift such that the
473 * resulting number of wqes does not exceed device
474 * capabilities.
475 *
476 * We set WQE size to at least 64 bytes, this way stamping
477 * invalidates each WQE.
0e6e7416 478 */
ea54b10c
JM		 479 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
480 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 481 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
482 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
483 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 484 qp->sq.wqe_shift = ilog2(64);
485 else
486 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
487
488 for (;;) {
ea54b10c
JM		 489 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
490
491 /*
492 * We need to leave 2 KB + 1 WR of headroom in the SQ to
493 * allow HW to prefetch.
494 */
495 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
496 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
497 qp->sq_max_wqes_per_wr +
498 qp->sq_spare_wqes);
499
500 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
501 break;
502
503 if (qp->sq_max_wqes_per_wr <= 1)
504 return -EINVAL;
505
506 ++qp->sq.wqe_shift;
507 }
508
cd155c1c
RD		 509 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
510 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 511 send_wqe_overhead(type, qp->flags)) /
512 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 513
514 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
515 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 516 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
517 qp->rq.offset = 0;
0e6e7416 518 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 519 } else {
0e6e7416 520 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 521 qp->sq.offset = 0;
522 }
523
ea54b10c
JM		 524 cap->max_send_wr = qp->sq.max_post =
525 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 526 cap->max_send_sge = min(qp->sq.max_gs,
527 min(dev->dev->caps.max_sq_sg,
528 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 529 /* We don't support inline sends for kernel QPs (yet) */
530 cap->max_inline_data = 0;
225c7b1f
RD		 531
532 return 0;
533}
534
83904132
JM		 535static int set_user_sq_size(struct mlx4_ib_dev *dev,
536 struct mlx4_ib_qp *qp,
2446304d
EC		 537 struct mlx4_ib_create_qp *ucmd)
538{
83904132
JM		 539 /* Sanity check SQ size before proceeding */
540 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
541 ucmd->log_sq_stride >
542 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
543 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
544 return -EINVAL;
545
0e6e7416 546 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 547 qp->sq.wqe_shift = ucmd->log_sq_stride;
548
0e6e7416
RD		 549 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
550 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 551
552 return 0;
553}
554
1ffeb2eb
JM		 555static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
556{
557 int i;
558
559 qp->sqp_proxy_rcv =
560 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
561 GFP_KERNEL);
562 if (!qp->sqp_proxy_rcv)
563 return -ENOMEM;
564 for (i = 0; i < qp->rq.wqe_cnt; i++) {
565 qp->sqp_proxy_rcv[i].addr =
566 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
567 GFP_KERNEL);
568 if (!qp->sqp_proxy_rcv[i].addr)
569 goto err;
570 qp->sqp_proxy_rcv[i].map =
571 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
572 sizeof (struct mlx4_ib_proxy_sqp_hdr),
573 DMA_FROM_DEVICE);
574 }
575 return 0;
576
577err:
578 while (i > 0) {
579 --i;
580 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
581 sizeof (struct mlx4_ib_proxy_sqp_hdr),
582 DMA_FROM_DEVICE);
583 kfree(qp->sqp_proxy_rcv[i].addr);
584 }
585 kfree(qp->sqp_proxy_rcv);
586 qp->sqp_proxy_rcv = NULL;
587 return -ENOMEM;
588}
589
590static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
591{
592 int i;
593
594 for (i = 0; i < qp->rq.wqe_cnt; i++) {
595 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
596 sizeof (struct mlx4_ib_proxy_sqp_hdr),
597 DMA_FROM_DEVICE);
598 kfree(qp->sqp_proxy_rcv[i].addr);
599 }
600 kfree(qp->sqp_proxy_rcv);
601}
602
0a1405da
SH		 603static int qp_has_rq(struct ib_qp_init_attr *attr)
604{
605 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
606 return 0;
607
608 return !attr->srq;
609}
610
99ec41d0
JM		 611static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
612{
613 int i;
614 for (i = 0; i < dev->caps.num_ports; i++) {
615 if (qpn == dev->caps.qp0_proxy[i])
616 return !!dev->caps.qp0_qkey[i];
617 }
618 return 0;
619}
620
225c7b1f
RD		 621static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
622 struct ib_qp_init_attr *init_attr,
40f2287b
JK		 623 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
624 gfp_t gfp)
225c7b1f 625{
a3cdcbfa 626 int qpn;
225c7b1f 627 int err;
1ffeb2eb
JM		 628 struct mlx4_ib_sqp *sqp;
629 struct mlx4_ib_qp *qp;
630 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
631
632 /* When tunneling special qps, we use a plain UD qp */
633 if (sqpn) {
634 if (mlx4_is_mfunc(dev->dev) &&
635 (!mlx4_is_master(dev->dev) ||
636 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
637 if (init_attr->qp_type == IB_QPT_GSI)
638 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 639 else {
640 if (mlx4_is_master(dev->dev) ||
641 qp0_enabled_vf(dev->dev, sqpn))
642 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
643 else
644 qp_type = MLX4_IB_QPT_PROXY_SMI;
645 }
1ffeb2eb
JM		 646 }
647 qpn = sqpn;
648 /* add extra sg entry for tunneling */
649 init_attr->cap.max_recv_sge++;
650 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
651 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
652 container_of(init_attr,
653 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
654 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
655 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
656 !mlx4_is_master(dev->dev))
657 return -EINVAL;
658 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
659 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 660 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
661 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
662 tnl_init->port))
1ffeb2eb
JM		 663 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
664 else
665 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 666 /* we are definitely in the PPF here, since we are creating
667 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
668 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
669 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 670 sqpn = qpn;
671 }
672
673 if (!*caller_qp) {
674 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
675 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
676 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6fcd8d0d 677 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
1ffeb2eb
JM		 678 if (!sqp)
679 return -ENOMEM;
680 qp = &sqp->qp;
2f5bb473
JM		 681 qp->pri.vid = 0xFFFF;
682 qp->alt.vid = 0xFFFF;
1ffeb2eb 683 } else {
6fcd8d0d 684 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
1ffeb2eb
JM		 685 if (!qp)
686 return -ENOMEM;
2f5bb473
JM		 687 qp->pri.vid = 0xFFFF;
688 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 689 }
690 } else
691 qp = *caller_qp;
692
693 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 694
695 mutex_init(&qp->mutex);
696 spin_lock_init(&qp->sq.lock);
697 spin_lock_init(&qp->rq.lock);
fa417f7b 698 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 699 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 700
701 qp->state = IB_QPS_RESET;
ea54b10c
JM		 702 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
703 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 704
0a1405da 705 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
225c7b1f
RD		 706 if (err)
707 goto err;
708
709 if (pd->uobject) {
710 struct mlx4_ib_create_qp ucmd;
711
712 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
713 err = -EFAULT;
714 goto err;
715 }
716
0e6e7416
RD		 717 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
718
83904132 719 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 720 if (err)
721 goto err;
722
225c7b1f 723 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 724 qp->buf_size, 0, 0);
225c7b1f
RD		 725 if (IS_ERR(qp->umem)) {
726 err = PTR_ERR(qp->umem);
727 goto err;
728 }
729
730 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
731 ilog2(qp->umem->page_size), &qp->mtt);
732 if (err)
733 goto err_buf;
734
735 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
736 if (err)
737 goto err_mtt;
738
0a1405da 739 if (qp_has_rq(init_attr)) {
02d89b87
RD		 740 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
741 ucmd.db_addr, &qp->db);
742 if (err)
743 goto err_mtt;
744 }
225c7b1f 745 } else {
0e6e7416
RD		 746 qp->sq_no_prefetch = 0;
747
521e575b
RL		 748 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
749 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
750
b832be1e
EC		 751 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
752 qp->flags |= MLX4_IB_QP_LSO;
753
c1c98501
MB		 754 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
755 if (dev->steering_support ==
756 MLX4_STEERING_MODE_DEVICE_MANAGED)
757 qp->flags |= MLX4_IB_QP_NETIF;
758 else
759 goto err;
760 }
761
1ffeb2eb 762 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 763 if (err)
764 goto err;
765
0a1405da 766 if (qp_has_rq(init_attr)) {
40f2287b 767 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
02d89b87
RD		 768 if (err)
769 goto err;
225c7b1f 770
02d89b87
RD		 771 *qp->db.db = 0;
772 }
225c7b1f 773
40f2287b 774 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
225c7b1f
RD		 775 err = -ENOMEM;
776 goto err_db;
777 }
778
779 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
780 &qp->mtt);
781 if (err)
782 goto err_buf;
783
40f2287b 784 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
225c7b1f
RD		 785 if (err)
786 goto err_mtt;
787
40f2287b
JK		 788 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), gfp);
789 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), gfp);
225c7b1f
RD		 790 if (!qp->sq.wrid || !qp->rq.wrid) {
791 err = -ENOMEM;
792 goto err_wrid;
793 }
225c7b1f
RD		 794 }
795
a3cdcbfa 796 if (sqpn) {
1ffeb2eb
JM		 797 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
798 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
799 if (alloc_proxy_bufs(pd->device, qp)) {
800 err = -ENOMEM;
801 goto err_wrid;
802 }
803 }
a3cdcbfa 804 } else {
ddae0349
EE		 805 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
806 * otherwise, the WQE BlueFlame setup flow wrongly causes
807 * VLAN insertion. */
3987a2d3 808 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349
EE		 809 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
810 init_attr->cap.max_send_wr ?
811 MLX4_RESERVE_ETH_BF_QP : 0);
3987a2d3 812 else
c1c98501
MB		 813 if (qp->flags & MLX4_IB_QP_NETIF)
814 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
815 else
816 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
ddae0349 817 &qpn, 0);
a3cdcbfa 818 if (err)
1ffeb2eb 819 goto err_proxy;
a3cdcbfa
YP		 820 }
821
40f2287b 822 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
225c7b1f 823 if (err)
a3cdcbfa 824 goto err_qpn;
225c7b1f 825
0a1405da
SH		 826 if (init_attr->qp_type == IB_QPT_XRC_TGT)
827 qp->mqp.qpn |= (1 << 23);
828
225c7b1f
RD		 829 /*
830 * Hardware wants QPN written in big-endian order (after
831 * shifting) for send doorbell. Precompute this value to save
832 * a little bit when posting sends.
833 */
834 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
835
225c7b1f 836 qp->mqp.event = mlx4_ib_qp_event;
1ffeb2eb
JM		 837 if (!*caller_qp)
838 *caller_qp = qp;
225c7b1f
RD		 839 return 0;
840
a3cdcbfa 841err_qpn:
c1c98501
MB		 842 if (!sqpn) {
843 if (qp->flags & MLX4_IB_QP_NETIF)
844 mlx4_ib_steer_qp_free(dev, qpn, 1);
845 else
846 mlx4_qp_release_range(dev->dev, qpn, 1);
847 }
1ffeb2eb
JM		 848err_proxy:
849 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
850 free_proxy_bufs(pd->device, qp);
225c7b1f 851err_wrid:
23f1b384 852 if (pd->uobject) {
0a1405da
SH		 853 if (qp_has_rq(init_attr))
854 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 855 } else {
225c7b1f
RD		 856 kfree(qp->sq.wrid);
857 kfree(qp->rq.wrid);
858 }
859
860err_mtt:
861 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
862
863err_buf:
864 if (pd->uobject)
865 ib_umem_release(qp->umem);
866 else
867 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
868
869err_db:
0a1405da 870 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 871 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 872
873err:
1ffeb2eb
JM		 874 if (!*caller_qp)
875 kfree(qp);
225c7b1f
RD		 876 return err;
877}
878
879static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
880{
881 switch (state) {
882 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
883 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
884 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
885 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
886 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
887 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
888 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
889 default: return -1;
890 }
891}
892
893static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 894 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 895{
338a8fad 896 if (send_cq == recv_cq) {
225c7b1f 897 spin_lock_irq(&send_cq->lock);
338a8fad
RD		 898 __acquire(&recv_cq->lock);
899 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f
RD		 900 spin_lock_irq(&send_cq->lock);
901 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
902 } else {
903 spin_lock_irq(&recv_cq->lock);
904 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
905 }
906}
907
908static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 909 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 910{
338a8fad
RD		 911 if (send_cq == recv_cq) {
912 __release(&recv_cq->lock);
225c7b1f 913 spin_unlock_irq(&send_cq->lock);
338a8fad 914 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f
RD		 915 spin_unlock(&recv_cq->lock);
916 spin_unlock_irq(&send_cq->lock);
917 } else {
918 spin_unlock(&send_cq->lock);
919 spin_unlock_irq(&recv_cq->lock);
920 }
921}
922
fa417f7b
EC		 923static void del_gid_entries(struct mlx4_ib_qp *qp)
924{
925 struct mlx4_ib_gid_entry *ge, *tmp;
926
927 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
928 list_del(&ge->list);
929 kfree(ge);
930 }
931}
932
0a1405da
SH		 933static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
934{
935 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
936 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
937 else
938 return to_mpd(qp->ibqp.pd);
939}
940
941static void get_cqs(struct mlx4_ib_qp *qp,
942 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
943{
944 switch (qp->ibqp.qp_type) {
945 case IB_QPT_XRC_TGT:
946 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
947 *recv_cq = *send_cq;
948 break;
949 case IB_QPT_XRC_INI:
950 *send_cq = to_mcq(qp->ibqp.send_cq);
951 *recv_cq = *send_cq;
952 break;
953 default:
954 *send_cq = to_mcq(qp->ibqp.send_cq);
955 *recv_cq = to_mcq(qp->ibqp.recv_cq);
956 break;
957 }
958}
959
225c7b1f
RD		 960static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
961 int is_user)
962{
963 struct mlx4_ib_cq *send_cq, *recv_cq;
964
2f5bb473 965 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 966 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
967 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 968 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 969 qp->mqp.qpn);
25476b02 970 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 971 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
972 qp->pri.smac = 0;
25476b02 973 qp->pri.smac_port = 0;
2f5bb473
JM		 974 }
975 if (qp->alt.smac) {
976 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
977 qp->alt.smac = 0;
978 }
979 if (qp->pri.vid < 0x1000) {
980 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
981 qp->pri.vid = 0xFFFF;
982 qp->pri.candidate_vid = 0xFFFF;
983 qp->pri.update_vid = 0;
984 }
985 if (qp->alt.vid < 0x1000) {
986 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
987 qp->alt.vid = 0xFFFF;
988 qp->alt.candidate_vid = 0xFFFF;
989 qp->alt.update_vid = 0;
990 }
991 }
225c7b1f 992
0a1405da 993 get_cqs(qp, &send_cq, &recv_cq);
225c7b1f
RD		 994
995 mlx4_ib_lock_cqs(send_cq, recv_cq);
996
997 if (!is_user) {
998 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
999 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1000 if (send_cq != recv_cq)
1001 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1002 }
1003
1004 mlx4_qp_remove(dev->dev, &qp->mqp);
1005
1006 mlx4_ib_unlock_cqs(send_cq, recv_cq);
1007
1008 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1009
c1c98501
MB		 1010 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1011 if (qp->flags & MLX4_IB_QP_NETIF)
1012 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1013 else
1014 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1015 }
a3cdcbfa 1016
225c7b1f
RD		 1017 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1018
1019 if (is_user) {
0a1405da 1020 if (qp->rq.wqe_cnt)
02d89b87
RD		 1021 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1022 &qp->db);
225c7b1f
RD		 1023 ib_umem_release(qp->umem);
1024 } else {
1025 kfree(qp->sq.wrid);
1026 kfree(qp->rq.wrid);
1ffeb2eb
JM		 1027 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1028 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1029 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1030 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1031 if (qp->rq.wqe_cnt)
6296883c 1032 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1033 }
fa417f7b
EC		 1034
1035 del_gid_entries(qp);
225c7b1f
RD		 1036}
1037
47605df9
JM		 1038static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1039{
1040 /* Native or PPF */
1041 if (!mlx4_is_mfunc(dev->dev) ||
1042 (mlx4_is_master(dev->dev) &&
1043 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1044 return dev->dev->phys_caps.base_sqpn +
1045 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1046 attr->port_num - 1;
1047 }
1048 /* PF or VF -- creating proxies */
1049 if (attr->qp_type == IB_QPT_SMI)
1050 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1051 else
1052 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1053}
1054
225c7b1f
RD		 1055struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1056 struct ib_qp_init_attr *init_attr,
1057 struct ib_udata *udata)
1058{
1ffeb2eb 1059 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1060 int err;
0a1405da 1061 u16 xrcdn = 0;
40f2287b 1062 gfp_t gfp;
225c7b1f 1063
40f2287b
JK		 1064 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1065 GFP_NOIO : GFP_KERNEL;
521e575b 1066 /*
1ffeb2eb
JM		 1067 * We only support LSO, vendor flag1, and multicast loopback blocking,
1068 * and only for kernel UD QPs.
521e575b 1069 */
1ffeb2eb
JM		 1070 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1071 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1072 MLX4_IB_SRIOV_TUNNEL_QP |
1073 MLX4_IB_SRIOV_SQP |
40f2287b
JK		 1074 MLX4_IB_QP_NETIF |
1075 MLX4_IB_QP_CREATE_USE_GFP_NOIO))
b832be1e 1076 return ERR_PTR(-EINVAL);
521e575b 1077
c1c98501
MB		 1078 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1079 if (init_attr->qp_type != IB_QPT_UD)
1080 return ERR_PTR(-EINVAL);
1081 }
1082
521e575b 1083 if (init_attr->create_flags &&
1ffeb2eb 1084 (udata ||
40f2287b 1085 ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | MLX4_IB_QP_CREATE_USE_GFP_NOIO)) &&
1ffeb2eb
JM		 1086 init_attr->qp_type != IB_QPT_UD) ||
1087 ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1088 init_attr->qp_type > IB_QPT_GSI)))
b846f25a
EC		 1089 return ERR_PTR(-EINVAL);
1090
225c7b1f 1091 switch (init_attr->qp_type) {
0a1405da
SH		 1092 case IB_QPT_XRC_TGT:
1093 pd = to_mxrcd(init_attr->xrcd)->pd;
1094 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1095 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1096 /* fall through */
1097 case IB_QPT_XRC_INI:
1098 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1099 return ERR_PTR(-ENOSYS);
1100 init_attr->recv_cq = init_attr->send_cq;
1101 /* fall through */
225c7b1f
RD		 1102 case IB_QPT_RC:
1103 case IB_QPT_UC:
3987a2d3 1104 case IB_QPT_RAW_PACKET:
40f2287b 1105 qp = kzalloc(sizeof *qp, gfp);
225c7b1f
RD		 1106 if (!qp)
1107 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1108 qp->pri.vid = 0xFFFF;
1109 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1110 /* fall through */
1111 case IB_QPT_UD:
1112 {
1113 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
40f2287b 1114 udata, 0, &qp, gfp);
1ffeb2eb 1115 if (err)
225c7b1f 1116 return ERR_PTR(err);
225c7b1f
RD		 1117
1118 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1119 qp->xrcdn = xrcdn;
225c7b1f
RD		 1120
1121 break;
1122 }
1123 case IB_QPT_SMI:
1124 case IB_QPT_GSI:
1125 {
1126 /* Userspace is not allowed to create special QPs: */
0a1405da 1127 if (udata)
225c7b1f
RD		 1128 return ERR_PTR(-EINVAL);
1129
0a1405da 1130 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
47605df9 1131 get_sqp_num(to_mdev(pd->device), init_attr),
40f2287b 1132 &qp, gfp);
1ffeb2eb 1133 if (err)
225c7b1f 1134 return ERR_PTR(err);
225c7b1f
RD		 1135
1136 qp->port = init_attr->port_num;
1137 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1138
1139 break;
1140 }
1141 default:
1142 /* Don't support raw QPs */
1143 return ERR_PTR(-EINVAL);
1144 }
1145
1146 return &qp->ibqp;
1147}
1148
1149int mlx4_ib_destroy_qp(struct ib_qp *qp)
1150{
1151 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1152 struct mlx4_ib_qp *mqp = to_mqp(qp);
0a1405da 1153 struct mlx4_ib_pd *pd;
225c7b1f
RD		 1154
1155 if (is_qp0(dev, mqp))
1156 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1157
9433c188
MB		 1158 if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1159 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1160 dev->qp1_proxy[mqp->port - 1] = NULL;
1161 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1162 }
1163
0a1405da
SH		 1164 pd = get_pd(mqp);
1165 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
225c7b1f
RD		 1166
1167 if (is_sqp(dev, mqp))
1168 kfree(to_msqp(mqp));
1169 else
1170 kfree(mqp);
1171
1172 return 0;
1173}
1174
1ffeb2eb 1175static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1176{
1177 switch (type) {
1ffeb2eb
JM		 1178 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1179 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1180 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1181 case MLX4_IB_QPT_XRC_INI:
1182 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1183 case MLX4_IB_QPT_SMI:
1184 case MLX4_IB_QPT_GSI:
1185 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1186
1187 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1188 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1189 MLX4_QP_ST_MLX : -1);
1190 case MLX4_IB_QPT_PROXY_SMI:
1191 case MLX4_IB_QPT_TUN_SMI:
1192 case MLX4_IB_QPT_PROXY_GSI:
1193 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1194 MLX4_QP_ST_UD : -1);
1195 default: return -1;
225c7b1f
RD		 1196 }
1197}
1198
65adfa91 1199static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1200 int attr_mask)
1201{
1202 u8 dest_rd_atomic;
1203 u32 access_flags;
1204 u32 hw_access_flags = 0;
1205
1206 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1207 dest_rd_atomic = attr->max_dest_rd_atomic;
1208 else
1209 dest_rd_atomic = qp->resp_depth;
1210
1211 if (attr_mask & IB_QP_ACCESS_FLAGS)
1212 access_flags = attr->qp_access_flags;
1213 else
1214 access_flags = qp->atomic_rd_en;
1215
1216 if (!dest_rd_atomic)
1217 access_flags &= IB_ACCESS_REMOTE_WRITE;
1218
1219 if (access_flags & IB_ACCESS_REMOTE_READ)
1220 hw_access_flags |= MLX4_QP_BIT_RRE;
1221 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1222 hw_access_flags |= MLX4_QP_BIT_RAE;
1223 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1224 hw_access_flags |= MLX4_QP_BIT_RWE;
1225
1226 return cpu_to_be32(hw_access_flags);
1227}
1228
65adfa91 1229static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1230 int attr_mask)
1231{
1232 if (attr_mask & IB_QP_PKEY_INDEX)
1233 sqp->pkey_index = attr->pkey_index;
1234 if (attr_mask & IB_QP_QKEY)
1235 sqp->qkey = attr->qkey;
1236 if (attr_mask & IB_QP_SQ_PSN)
1237 sqp->send_psn = attr->sq_psn;
1238}
1239
1240static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1241{
1242 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1243}
1244
297e0dad
MS		 1245static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1246 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1247 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1248{
fa417f7b
EC		 1249 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1250 IB_LINK_LAYER_ETHERNET;
4c3eb3ca 1251 int vidx;
297e0dad 1252 int smac_index;
2f5bb473 1253 int err;
297e0dad 1254
fa417f7b 1255
225c7b1f
RD		 1256 path->grh_mylmc = ah->src_path_bits & 0x7f;
1257 path->rlid = cpu_to_be16(ah->dlid);
1258 if (ah->static_rate) {
1259 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1260 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1261 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1262 --path->static_rate;
1263 } else
1264 path->static_rate = 0;
225c7b1f
RD		 1265
1266 if (ah->ah_flags & IB_AH_GRH) {
5ae2a7a8 1267 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1268 pr_err("sgid_index (%u) too large. max is %d\n",
5ae2a7a8 1269 ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1270 return -1;
1271 }
1272
1273 path->grh_mylmc |= 1 << 7;
1274 path->mgid_index = ah->grh.sgid_index;
1275 path->hop_limit = ah->grh.hop_limit;
1276 path->tclass_flowlabel =
1277 cpu_to_be32((ah->grh.traffic_class << 20) |
1278 (ah->grh.flow_label));
1279 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1280 }
1281
fa417f7b
EC		 1282 if (is_eth) {
1283 if (!(ah->ah_flags & IB_AH_GRH))
1284 return -1;
1285
2f5bb473
JM		 1286 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1287 ((port - 1) << 6) | ((ah->sl & 7) << 3);
4c3eb3ca 1288
297e0dad 1289 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1290 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1291 if (smac_info->vid < 0x1000) {
1292 /* both valid vlan ids */
1293 if (smac_info->vid != vlan_tag) {
1294 /* different VIDs. unreg old and reg new */
1295 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1296 if (err)
1297 return err;
1298 smac_info->candidate_vid = vlan_tag;
1299 smac_info->candidate_vlan_index = vidx;
1300 smac_info->candidate_vlan_port = port;
1301 smac_info->update_vid = 1;
1302 path->vlan_index = vidx;
1303 } else {
1304 path->vlan_index = smac_info->vlan_index;
1305 }
1306 } else {
1307 /* no current vlan tag in qp */
1308 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1309 if (err)
1310 return err;
1311 smac_info->candidate_vid = vlan_tag;
1312 smac_info->candidate_vlan_index = vidx;
1313 smac_info->candidate_vlan_port = port;
1314 smac_info->update_vid = 1;
1315 path->vlan_index = vidx;
1316 }
297e0dad 1317 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1318 path->fl = 1 << 6;
1319 } else {
1320 /* have current vlan tag. unregister it at modify-qp success */
1321 if (smac_info->vid < 0x1000) {
1322 smac_info->candidate_vid = 0xFFFF;
1323 smac_info->update_vid = 1;
1324 }
4c3eb3ca 1325 }
2f5bb473
JM		 1326
1327 /* get smac_index for RoCE use.
1328 * If no smac was yet assigned, register one.
1329 * If one was already assigned, but the new mac differs,
1330 * unregister the old one and register the new one.
1331 */
25476b02
JM		 1332 if ((!smac_info->smac && !smac_info->smac_port) ||
1333 smac_info->smac != smac) {
2f5bb473
JM		 1334 /* register candidate now, unreg if needed, after success */
1335 smac_index = mlx4_register_mac(dev->dev, port, smac);
1336 if (smac_index >= 0) {
1337 smac_info->candidate_smac_index = smac_index;
1338 smac_info->candidate_smac = smac;
1339 smac_info->candidate_smac_port = port;
1340 } else {
1341 return -EINVAL;
1342 }
1343 } else {
1344 smac_index = smac_info->smac_index;
1345 }
1346
1347 memcpy(path->dmac, ah->dmac, 6);
1348 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1349 /* put MAC table smac index for IBoE */
1350 path->grh_mylmc = (u8) (smac_index) | 0x80;
1351 } else {
4c3eb3ca
EC		 1352 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1353 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
2f5bb473 1354 }
fa417f7b 1355
225c7b1f
RD		 1356 return 0;
1357}
1358
297e0dad
MS		 1359static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1360 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1361 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1362 struct mlx4_qp_path *path, u8 port)
1363{
1364 return _mlx4_set_path(dev, &qp->ah_attr,
1365 mlx4_mac_to_u64((u8 *)qp->smac),
1366 (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff,
2f5bb473 1367 path, &mqp->pri, port);
297e0dad
MS		 1368}
1369
1370static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1371 const struct ib_qp_attr *qp,
1372 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1373 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1374 struct mlx4_qp_path *path, u8 port)
1375{
1376 return _mlx4_set_path(dev, &qp->alt_ah_attr,
1377 mlx4_mac_to_u64((u8 *)qp->alt_smac),
1378 (qp_attr_mask & IB_QP_ALT_VID) ?
1379 qp->alt_vlan_id : 0xffff,
2f5bb473 1380 path, &mqp->alt, port);
297e0dad
MS		 1381}
1382
fa417f7b
EC		 1383static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1384{
1385 struct mlx4_ib_gid_entry *ge, *tmp;
1386
1387 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1388 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1389 ge->added = 1;
1390 ge->port = qp->port;
1391 }
1392 }
1393}
1394
2f5bb473
JM		 1395static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, u8 *smac,
1396 struct mlx4_qp_context *context)
1397{
2f5bb473
JM		 1398 u64 u64_mac;
1399 int smac_index;
1400
3e0629cb 1401 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1402
1403 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1404 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1405 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1406 if (smac_index >= 0) {
1407 qp->pri.candidate_smac_index = smac_index;
1408 qp->pri.candidate_smac = u64_mac;
1409 qp->pri.candidate_smac_port = qp->port;
1410 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1411 } else {
1412 return -ENOENT;
1413 }
1414 }
1415 return 0;
1416}
1417
65adfa91
MT		 1418static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1419 const struct ib_qp_attr *attr, int attr_mask,
1420 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 1421{
1422 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1423 struct mlx4_ib_qp *qp = to_mqp(ibqp);
0a1405da
SH		 1424 struct mlx4_ib_pd *pd;
1425 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 1426 struct mlx4_qp_context *context;
1427 enum mlx4_qp_optpar optpar = 0;
225c7b1f 1428 int sqd_event;
c1c98501 1429 int steer_qp = 0;
225c7b1f
RD		 1430 int err = -EINVAL;
1431
3dec4878
JM		 1432 /* APM is not supported under RoCE */
1433 if (attr_mask & IB_QP_ALT_PATH &&
1434 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1435 IB_LINK_LAYER_ETHERNET)
1436 return -ENOTSUPP;
1437
225c7b1f
RD		 1438 context = kzalloc(sizeof *context, GFP_KERNEL);
1439 if (!context)
1440 return -ENOMEM;
1441
225c7b1f 1442 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 1443 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 1444
1445 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1446 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1447 else {
1448 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1449 switch (attr->path_mig_state) {
1450 case IB_MIG_MIGRATED:
1451 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1452 break;
1453 case IB_MIG_REARM:
1454 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1455 break;
1456 case IB_MIG_ARMED:
1457 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1458 break;
1459 }
1460 }
1461
b832be1e 1462 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 1463 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
3987a2d3
OG		 1464 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1465 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
b832be1e
EC		 1466 else if (ibqp->qp_type == IB_QPT_UD) {
1467 if (qp->flags & MLX4_IB_QP_LSO)
1468 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1469 ilog2(dev->dev->caps.max_gso_sz);
1470 else
6e0d733d 1471 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 1472 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 1473 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 1474 pr_err("path MTU (%u) is invalid\n",
225c7b1f 1475 attr->path_mtu);
f5b40431 1476 goto out;
225c7b1f 1477 }
d1f2cd89
EC		 1478 context->mtu_msgmax = (attr->path_mtu << 5) |
1479 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 1480 }
1481
0e6e7416
RD		 1482 if (qp->rq.wqe_cnt)
1483 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 1484 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1485
0e6e7416
RD		 1486 if (qp->sq.wqe_cnt)
1487 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 1488 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1489
0a1405da 1490 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 1491 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 1492 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
02d7ef6f
DB		 1493 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1494 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 1495 }
0e6e7416 1496
225c7b1f
RD		 1497 if (qp->ibqp.uobject)
1498 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1499 else
1500 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1501
1502 if (attr_mask & IB_QP_DEST_QPN)
1503 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1504
1505 if (attr_mask & IB_QP_PORT) {
1506 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1507 !(attr_mask & IB_QP_AV)) {
1508 mlx4_set_sched(&context->pri_path, attr->port_num);
1509 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1510 }
1511 }
1512
cfcde11c
OG		 1513 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1514 if (dev->counters[qp->port - 1] != -1) {
1515 context->pri_path.counter_index =
1516 dev->counters[qp->port - 1];
1517 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1518 } else
1519 context->pri_path.counter_index = 0xff;
c1c98501
MB		 1520
1521 if (qp->flags & MLX4_IB_QP_NETIF) {
1522 mlx4_ib_steer_qp_reg(dev, qp, 1);
1523 steer_qp = 1;
1524 }
cfcde11c
OG		 1525 }
1526
225c7b1f 1527 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 1528 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1529 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 1530 context->pri_path.pkey_index = attr->pkey_index;
1531 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1532 }
1533
225c7b1f 1534 if (attr_mask & IB_QP_AV) {
2f5bb473 1535 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1ffeb2eb
JM		 1536 attr_mask & IB_QP_PORT ?
1537 attr->port_num : qp->port))
225c7b1f 1538 goto out;
225c7b1f
RD		 1539
1540 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1541 MLX4_QP_OPTPAR_SCHED_QUEUE);
1542 }
1543
1544 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 1545 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 1546 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1547 }
1548
1549 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 1550 if (attr->alt_port_num == 0 ||
1551 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 1552 goto out;
225c7b1f 1553
5ae2a7a8
RD		 1554 if (attr->alt_pkey_index >=
1555 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 1556 goto out;
5ae2a7a8 1557
2f5bb473
JM		 1558 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1559 &context->alt_path,
297e0dad 1560 attr->alt_port_num))
f5b40431 1561 goto out;
225c7b1f
RD		 1562
1563 context->alt_path.pkey_index = attr->alt_pkey_index;
1564 context->alt_path.ackto = attr->alt_timeout << 3;
1565 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1566 }
1567
0a1405da
SH		 1568 pd = get_pd(qp);
1569 get_cqs(qp, &send_cq, &recv_cq);
1570 context->pd = cpu_to_be32(pd->pdn);
1571 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1572 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1573 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 1574
95d04f07
RD		 1575 /* Set "fast registration enabled" for all kernel QPs */
1576 if (!qp->ibqp.uobject)
1577 context->params1 |= cpu_to_be32(1 << 11);
1578
57f01b53
JM		 1579 if (attr_mask & IB_QP_RNR_RETRY) {
1580 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1581 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1582 }
1583
225c7b1f
RD		 1584 if (attr_mask & IB_QP_RETRY_CNT) {
1585 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1586 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1587 }
1588
1589 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1590 if (attr->max_rd_atomic)
1591 context->params1 |=
1592 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1593 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1594 }
1595
1596 if (attr_mask & IB_QP_SQ_PSN)
1597 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1598
225c7b1f
RD		 1599 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1600 if (attr->max_dest_rd_atomic)
1601 context->params2 |=
1602 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1603 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1604 }
1605
1606 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1607 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1608 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1609 }
1610
1611 if (ibqp->srq)
1612 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1613
1614 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1615 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1616 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1617 }
1618 if (attr_mask & IB_QP_RQ_PSN)
1619 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1620
1ffeb2eb 1621 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 1622 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 1623 if (qp->mlx4_ib_qp_type &
1624 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1625 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1626 else {
1627 if (mlx4_is_mfunc(dev->dev) &&
1628 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1629 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1630 MLX4_RESERVED_QKEY_BASE) {
1631 pr_err("Cannot use reserved QKEY"
1632 " 0x%x (range 0xffff0000..0xffffffff"
1633 " is reserved)\n", attr->qkey);
1634 err = -EINVAL;
1635 goto out;
1636 }
1637 context->qkey = cpu_to_be32(attr->qkey);
1638 }
225c7b1f
RD		 1639 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1640 }
1641
1642 if (ibqp->srq)
1643 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1644
0a1405da 1645 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1646 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1647
1648 if (cur_state == IB_QPS_INIT &&
1649 new_state == IB_QPS_RTR &&
1650 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
3987a2d3
OG		 1651 ibqp->qp_type == IB_QPT_UD ||
1652 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 1653 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 1654 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1655 qp->mlx4_ib_qp_type &
1656 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 1657 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 1658 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1659 context->pri_path.fl = 0x80;
1660 } else {
1661 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1662 context->pri_path.fl = 0x80;
225c7b1f 1663 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 1664 }
2f5bb473
JM		 1665 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1666 IB_LINK_LAYER_ETHERNET) {
1667 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1668 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1669 context->pri_path.feup = 1 << 7; /* don't fsm */
1670 /* handle smac_index */
1671 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1672 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1673 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1674 err = handle_eth_ud_smac_index(dev, qp, (u8 *)attr->smac, context);
1675 if (err)
1676 return -EINVAL;
9433c188
MB		 1677 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1678 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 1679 }
1680 }
225c7b1f
RD		 1681 }
1682
d2fce8a9 1683 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 1684 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1685 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 1686 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1687 /* set QP to receive both tunneled & non-tunneled packets */
8e1a03b6 1688 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
d2fce8a9
OG		 1689 context->srqn = cpu_to_be32(7 << 28);
1690 }
1691 }
3528f696 1692
297e0dad
MS		 1693 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1694 int is_eth = rdma_port_get_link_layer(
1695 &dev->ib_dev, qp->port) ==
1696 IB_LINK_LAYER_ETHERNET;
1697 if (is_eth) {
1698 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1699 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1700 }
1701 }
1702
1703
225c7b1f
RD		 1704 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1705 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1706 sqd_event = 1;
1707 else
1708 sqd_event = 0;
1709
d57f5f72
VS		 1710 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1711 context->rlkey |= (1 << 4);
1712
c0be5fb5
EC		 1713 /*
1714 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1715 * ownership bits of the send queue are set and the SQ
1716 * headroom is stamped so that the hardware doesn't start
1717 * processing stale work requests.
c0be5fb5
EC		 1718 */
1719 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1720 struct mlx4_wqe_ctrl_seg *ctrl;
1721 int i;
1722
0e6e7416 1723 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1724 ctrl = get_send_wqe(qp, i);
1725 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553
EC		 1726 if (qp->sq_max_wqes_per_wr == 1)
1727 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
0e6e7416 1728
ea54b10c 1729 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 1730 }
1731 }
1732
225c7b1f
RD		 1733 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1734 to_mlx4_state(new_state), context, optpar,
1735 sqd_event, &qp->mqp);
1736 if (err)
1737 goto out;
1738
1739 qp->state = new_state;
1740
1741 if (attr_mask & IB_QP_ACCESS_FLAGS)
1742 qp->atomic_rd_en = attr->qp_access_flags;
1743 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1744 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 1745 if (attr_mask & IB_QP_PORT) {
225c7b1f 1746 qp->port = attr->port_num;
fa417f7b
EC		 1747 update_mcg_macs(dev, qp);
1748 }
225c7b1f
RD		 1749 if (attr_mask & IB_QP_ALT_PATH)
1750 qp->alt_port = attr->alt_port_num;
1751
1752 if (is_sqp(dev, qp))
1753 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1754
1755 /*
1756 * If we moved QP0 to RTR, bring the IB link up; if we moved
1757 * QP0 to RESET or ERROR, bring the link back down.
1758 */
1759 if (is_qp0(dev, qp)) {
1760 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 1761 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 1762 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 1763 qp->port);
225c7b1f
RD		 1764
1765 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1766 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1767 mlx4_CLOSE_PORT(dev->dev, qp->port);
1768 }
1769
1770 /*
1771 * If we moved a kernel QP to RESET, clean up all old CQ
1772 * entries and reinitialize the QP.
1773 */
2f5bb473
JM		 1774 if (new_state == IB_QPS_RESET) {
1775 if (!ibqp->uobject) {
1776 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1777 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1778 if (send_cq != recv_cq)
1779 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1780
1781 qp->rq.head = 0;
1782 qp->rq.tail = 0;
1783 qp->sq.head = 0;
1784 qp->sq.tail = 0;
1785 qp->sq_next_wqe = 0;
1786 if (qp->rq.wqe_cnt)
1787 *qp->db.db = 0;
225c7b1f 1788
2f5bb473
JM		 1789 if (qp->flags & MLX4_IB_QP_NETIF)
1790 mlx4_ib_steer_qp_reg(dev, qp, 0);
1791 }
25476b02 1792 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1793 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1794 qp->pri.smac = 0;
25476b02 1795 qp->pri.smac_port = 0;
2f5bb473
JM		 1796 }
1797 if (qp->alt.smac) {
1798 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1799 qp->alt.smac = 0;
1800 }
1801 if (qp->pri.vid < 0x1000) {
1802 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1803 qp->pri.vid = 0xFFFF;
1804 qp->pri.candidate_vid = 0xFFFF;
1805 qp->pri.update_vid = 0;
1806 }
c1c98501 1807
2f5bb473
JM		 1808 if (qp->alt.vid < 0x1000) {
1809 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1810 qp->alt.vid = 0xFFFF;
1811 qp->alt.candidate_vid = 0xFFFF;
1812 qp->alt.update_vid = 0;
1813 }
225c7b1f 1814 }
225c7b1f 1815out:
c1c98501
MB		 1816 if (err && steer_qp)
1817 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 1818 kfree(context);
25476b02
JM		 1819 if (qp->pri.candidate_smac ||
1820 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 1821 if (err) {
1822 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1823 } else {
25476b02 1824 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 1825 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1826 qp->pri.smac = qp->pri.candidate_smac;
1827 qp->pri.smac_index = qp->pri.candidate_smac_index;
1828 qp->pri.smac_port = qp->pri.candidate_smac_port;
1829 }
1830 qp->pri.candidate_smac = 0;
1831 qp->pri.candidate_smac_index = 0;
1832 qp->pri.candidate_smac_port = 0;
1833 }
1834 if (qp->alt.candidate_smac) {
1835 if (err) {
1836 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1837 } else {
1838 if (qp->alt.smac)
1839 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1840 qp->alt.smac = qp->alt.candidate_smac;
1841 qp->alt.smac_index = qp->alt.candidate_smac_index;
1842 qp->alt.smac_port = qp->alt.candidate_smac_port;
1843 }
1844 qp->alt.candidate_smac = 0;
1845 qp->alt.candidate_smac_index = 0;
1846 qp->alt.candidate_smac_port = 0;
1847 }
1848
1849 if (qp->pri.update_vid) {
1850 if (err) {
1851 if (qp->pri.candidate_vid < 0x1000)
1852 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1853 qp->pri.candidate_vid);
1854 } else {
1855 if (qp->pri.vid < 0x1000)
1856 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1857 qp->pri.vid);
1858 qp->pri.vid = qp->pri.candidate_vid;
1859 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1860 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
1861 }
1862 qp->pri.candidate_vid = 0xFFFF;
1863 qp->pri.update_vid = 0;
1864 }
1865
1866 if (qp->alt.update_vid) {
1867 if (err) {
1868 if (qp->alt.candidate_vid < 0x1000)
1869 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
1870 qp->alt.candidate_vid);
1871 } else {
1872 if (qp->alt.vid < 0x1000)
1873 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
1874 qp->alt.vid);
1875 qp->alt.vid = qp->alt.candidate_vid;
1876 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
1877 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
1878 }
1879 qp->alt.candidate_vid = 0xFFFF;
1880 qp->alt.update_vid = 0;
1881 }
1882
225c7b1f
RD		 1883 return err;
1884}
1885
65adfa91
MT		 1886int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1887 int attr_mask, struct ib_udata *udata)
1888{
1889 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1890 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1891 enum ib_qp_state cur_state, new_state;
1892 int err = -EINVAL;
297e0dad 1893 int ll;
65adfa91
MT		 1894 mutex_lock(&qp->mutex);
1895
1896 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1897 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1898
297e0dad
MS		 1899 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1900 ll = IB_LINK_LAYER_UNSPECIFIED;
1901 } else {
1902 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1903 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
1904 }
dd5f03be
MB		 1905
1906 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 1907 attr_mask, ll)) {
b1d8eb5a
JM		 1908 pr_debug("qpn 0x%x: invalid attribute mask specified "
1909 "for transition %d to %d. qp_type %d,"
1910 " attr_mask 0x%x\n",
1911 ibqp->qp_num, cur_state, new_state,
1912 ibqp->qp_type, attr_mask);
65adfa91 1913 goto out;
b1d8eb5a 1914 }
65adfa91 1915
65adfa91 1916 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 1917 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 1918 pr_debug("qpn 0x%x: invalid port number (%d) specified "
1919 "for transition %d to %d. qp_type %d\n",
1920 ibqp->qp_num, attr->port_num, cur_state,
1921 new_state, ibqp->qp_type);
65adfa91
MT		 1922 goto out;
1923 }
1924
3987a2d3
OG		 1925 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1926 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1927 IB_LINK_LAYER_ETHERNET))
1928 goto out;
1929
5ae2a7a8
RD		 1930 if (attr_mask & IB_QP_PKEY_INDEX) {
1931 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 1932 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
1933 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
1934 "for transition %d to %d. qp_type %d\n",
1935 ibqp->qp_num, attr->pkey_index, cur_state,
1936 new_state, ibqp->qp_type);
5ae2a7a8 1937 goto out;
b1d8eb5a 1938 }
5ae2a7a8
RD		 1939 }
1940
65adfa91
MT		 1941 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1942 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 1943 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
1944 "Transition %d to %d. qp_type %d\n",
1945 ibqp->qp_num, attr->max_rd_atomic, cur_state,
1946 new_state, ibqp->qp_type);
65adfa91
MT		 1947 goto out;
1948 }
1949
1950 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1951 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 1952 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
1953 "Transition %d to %d. qp_type %d\n",
1954 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
1955 new_state, ibqp->qp_type);
65adfa91
MT		 1956 goto out;
1957 }
1958
1959 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1960 err = 0;
1961 goto out;
1962 }
1963
65adfa91
MT		 1964 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1965
1966out:
1967 mutex_unlock(&qp->mutex);
1968 return err;
1969}
1970
99ec41d0
JM		 1971static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
1972{
1973 int i;
1974 for (i = 0; i < dev->caps.num_ports; i++) {
1975 if (qpn == dev->caps.qp0_proxy[i] ||
1976 qpn == dev->caps.qp0_tunnel[i]) {
1977 *qkey = dev->caps.qp0_qkey[i];
1978 return 0;
1979 }
1980 }
1981 return -EINVAL;
1982}
1983
1ffeb2eb
JM		 1984static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
1985 struct ib_send_wr *wr,
1986 void *wqe, unsigned *mlx_seg_len)
1987{
1988 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
1989 struct ib_device *ib_dev = &mdev->ib_dev;
1990 struct mlx4_wqe_mlx_seg *mlx = wqe;
1991 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1992 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1993 u16 pkey;
1994 u32 qkey;
1995 int send_size;
1996 int header_size;
1997 int spc;
1998 int i;
1999
2000 if (wr->opcode != IB_WR_SEND)
2001 return -EINVAL;
2002
2003 send_size = 0;
2004
2005 for (i = 0; i < wr->num_sge; ++i)
2006 send_size += wr->sg_list[i].length;
2007
2008 /* for proxy-qp0 sends, need to add in size of tunnel header */
2009 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2010 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2011 send_size += sizeof (struct mlx4_ib_tunnel_header);
2012
2013 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
2014
2015 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2016 sqp->ud_header.lrh.service_level =
2017 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2018 sqp->ud_header.lrh.destination_lid =
2019 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2020 sqp->ud_header.lrh.source_lid =
2021 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2022 }
2023
2024 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2025
2026 /* force loopback */
2027 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2028 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2029
2030 sqp->ud_header.lrh.virtual_lane = 0;
2031 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2032 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2033 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2034 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2035 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2036 else
2037 sqp->ud_header.bth.destination_qpn =
47605df9 2038 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 2039
2040 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2041 if (mlx4_is_master(mdev->dev)) {
2042 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2043 return -EINVAL;
2044 } else {
2045 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2046 return -EINVAL;
2047 }
1ffeb2eb
JM		 2048 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2049 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2050
2051 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2052 sqp->ud_header.immediate_present = 0;
2053
2054 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2055
2056 /*
2057 * Inline data segments may not cross a 64 byte boundary. If
2058 * our UD header is bigger than the space available up to the
2059 * next 64 byte boundary in the WQE, use two inline data
2060 * segments to hold the UD header.
2061 */
2062 spc = MLX4_INLINE_ALIGN -
2063 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2064 if (header_size <= spc) {
2065 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2066 memcpy(inl + 1, sqp->header_buf, header_size);
2067 i = 1;
2068 } else {
2069 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2070 memcpy(inl + 1, sqp->header_buf, spc);
2071
2072 inl = (void *) (inl + 1) + spc;
2073 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2074 /*
2075 * Need a barrier here to make sure all the data is
2076 * visible before the byte_count field is set.
2077 * Otherwise the HCA prefetcher could grab the 64-byte
2078 * chunk with this inline segment and get a valid (!=
2079 * 0xffffffff) byte count but stale data, and end up
2080 * generating a packet with bad headers.
2081 *
2082 * The first inline segment's byte_count field doesn't
2083 * need a barrier, because it comes after a
2084 * control/MLX segment and therefore is at an offset
2085 * of 16 mod 64.
2086 */
2087 wmb();
2088 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2089 i = 2;
2090 }
2091
2092 *mlx_seg_len =
2093 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2094 return 0;
2095}
2096
3e0629cb
JM		 2097static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2098{
2099 int i;
2100
2101 for (i = ETH_ALEN; i; i--) {
2102 dst_mac[i - 1] = src_mac & 0xff;
2103 src_mac >>= 8;
2104 }
2105}
2106
225c7b1f 2107static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
f438000f 2108 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2109{
a478868a 2110 struct ib_device *ib_dev = sqp->qp.ibqp.device;
225c7b1f 2111 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2112 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f
RD		 2113 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2114 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
4c3eb3ca 2115 union ib_gid sgid;
225c7b1f
RD		 2116 u16 pkey;
2117 int send_size;
2118 int header_size;
e61ef241 2119 int spc;
225c7b1f 2120 int i;
1ffeb2eb 2121 int err = 0;
57d88cff 2122 u16 vlan = 0xffff;
a29bec12
RD		 2123 bool is_eth;
2124 bool is_vlan = false;
2125 bool is_grh;
225c7b1f
RD		 2126
2127 send_size = 0;
2128 for (i = 0; i < wr->num_sge; ++i)
2129 send_size += wr->sg_list[i].length;
2130
fa417f7b
EC		 2131 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2132 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 2133 if (is_eth) {
1ffeb2eb
JM		 2134 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2135 /* When multi-function is enabled, the ib_core gid
2136 * indexes don't necessarily match the hw ones, so
2137 * we must use our own cache */
6ee51a4e
JM		 2138 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2139 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2140 ah->av.ib.gid_index, &sgid.raw[0]);
2141 if (err)
2142 return err;
1ffeb2eb
JM		 2143 } else {
2144 err = ib_get_cached_gid(ib_dev,
2145 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2146 ah->av.ib.gid_index, &sgid);
2147 if (err)
2148 return err;
2149 }
2150
0e9855db 2151 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 2152 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2153 is_vlan = 1;
2154 }
4c3eb3ca
EC		 2155 }
2156 ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
fa417f7b
EC		 2157
2158 if (!is_eth) {
2159 sqp->ud_header.lrh.service_level =
2160 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2161 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2162 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2163 }
225c7b1f 2164
fa417f7b 2165 if (is_grh) {
225c7b1f 2166 sqp->ud_header.grh.traffic_class =
fa417f7b 2167 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 2168 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 2169 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2170 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
6ee51a4e
JM		 2171 if (is_eth)
2172 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2173 else {
1ffeb2eb
JM		 2174 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2175 /* When multi-function is enabled, the ib_core gid
2176 * indexes don't necessarily match the hw ones, so
2177 * we must use our own cache */
2178 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2179 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2180 subnet_prefix;
2181 sqp->ud_header.grh.source_gid.global.interface_id =
2182 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2183 guid_cache[ah->av.ib.gid_index];
2184 } else
2185 ib_get_cached_gid(ib_dev,
2186 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2187 ah->av.ib.gid_index,
2188 &sqp->ud_header.grh.source_gid);
6ee51a4e 2189 }
225c7b1f 2190 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 2191 ah->av.ib.dgid, 16);
225c7b1f
RD		 2192 }
2193
2194 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 2195
2196 if (!is_eth) {
2197 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2198 (sqp->ud_header.lrh.destination_lid ==
2199 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2200 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 2201 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2202 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 2203 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2204 }
225c7b1f
RD		 2205
2206 switch (wr->opcode) {
2207 case IB_WR_SEND:
2208 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2209 sqp->ud_header.immediate_present = 0;
2210 break;
2211 case IB_WR_SEND_WITH_IMM:
2212 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2213 sqp->ud_header.immediate_present = 1;
0f39cf3d 2214 sqp->ud_header.immediate_data = wr->ex.imm_data;
225c7b1f
RD		 2215 break;
2216 default:
2217 return -EINVAL;
2218 }
2219
fa417f7b 2220 if (is_eth) {
6ee51a4e
JM		 2221 struct in6_addr in6;
2222
c0c1d3d7
OD		 2223 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2224
2225 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b
EC		 2226
2227 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2228 /* FIXME: cache smac value? */
6ee51a4e
JM		 2229 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2230 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2231 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 2232
3e0629cb
JM		 2233 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2234 u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2235 u8 smac[ETH_ALEN];
2236
2237 mlx4_u64_to_smac(smac, mac);
2238 memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2239 } else {
2240 /* use the src mac of the tunnel */
2241 memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2242 }
2243
fa417f7b
EC		 2244 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2245 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca
EC		 2246 if (!is_vlan) {
2247 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2248 } else {
4c3eb3ca 2249 sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
4c3eb3ca
EC		 2250 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2251 }
fa417f7b
EC		 2252 } else {
2253 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
2254 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2255 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2256 }
225c7b1f
RD		 2257 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2258 if (!sqp->qp.ibqp.qp_num)
2259 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2260 else
2261 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
2262 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2263 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2264 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2265 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
2266 sqp->qkey : wr->wr.ud.remote_qkey);
2267 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2268
2269 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2270
2271 if (0) {
987c8f8f 2272 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 2273 for (i = 0; i < header_size / 4; ++i) {
2274 if (i % 8 == 0)
987c8f8f
SP		 2275 pr_err(" [%02x] ", i * 4);
2276 pr_cont(" %08x",
2277 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 2278 if ((i + 1) % 8 == 0)
987c8f8f 2279 pr_cont("\n");
225c7b1f 2280 }
987c8f8f 2281 pr_err("\n");
225c7b1f
RD		 2282 }
2283
e61ef241
RD		 2284 /*
2285 * Inline data segments may not cross a 64 byte boundary. If
2286 * our UD header is bigger than the space available up to the
2287 * next 64 byte boundary in the WQE, use two inline data
2288 * segments to hold the UD header.
2289 */
2290 spc = MLX4_INLINE_ALIGN -
2291 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2292 if (header_size <= spc) {
2293 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2294 memcpy(inl + 1, sqp->header_buf, header_size);
2295 i = 1;
2296 } else {
2297 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2298 memcpy(inl + 1, sqp->header_buf, spc);
2299
2300 inl = (void *) (inl + 1) + spc;
2301 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2302 /*
2303 * Need a barrier here to make sure all the data is
2304 * visible before the byte_count field is set.
2305 * Otherwise the HCA prefetcher could grab the 64-byte
2306 * chunk with this inline segment and get a valid (!=
2307 * 0xffffffff) byte count but stale data, and end up
2308 * generating a packet with bad headers.
2309 *
2310 * The first inline segment's byte_count field doesn't
2311 * need a barrier, because it comes after a
2312 * control/MLX segment and therefore is at an offset
2313 * of 16 mod 64.
2314 */
2315 wmb();
2316 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2317 i = 2;
2318 }
225c7b1f 2319
f438000f
RD		 2320 *mlx_seg_len =
2321 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2322 return 0;
225c7b1f
RD		 2323}
2324
2325static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2326{
2327 unsigned cur;
2328 struct mlx4_ib_cq *cq;
2329
2330 cur = wq->head - wq->tail;
0e6e7416 2331 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 2332 return 0;
2333
2334 cq = to_mcq(ib_cq);
2335 spin_lock(&cq->lock);
2336 cur = wq->head - wq->tail;
2337 spin_unlock(&cq->lock);
2338
0e6e7416 2339 return cur + nreq >= wq->max_post;
225c7b1f
RD		 2340}
2341
95d04f07
RD		 2342static __be32 convert_access(int acc)
2343{
6ff63e19
SM		 2344 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2345 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2346 (acc & IB_ACCESS_REMOTE_WRITE ?
2347 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2348 (acc & IB_ACCESS_REMOTE_READ ?
2349 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 2350 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2351 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2352}
2353
2354static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
2355{
2356 struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
29bdc883
VS		 2357 int i;
2358
2359 for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2b6b7d4b 2360 mfrpl->mapped_page_list[i] =
29bdc883
VS		 2361 cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
2362 MLX4_MTT_FLAG_PRESENT);
95d04f07
RD		 2363
2364 fseg->flags = convert_access(wr->wr.fast_reg.access_flags);
2365 fseg->mem_key = cpu_to_be32(wr->wr.fast_reg.rkey);
2366 fseg->buf_list = cpu_to_be64(mfrpl->map);
2367 fseg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
2368 fseg->reg_len = cpu_to_be64(wr->wr.fast_reg.length);
2369 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2370 fseg->page_size = cpu_to_be32(wr->wr.fast_reg.page_shift);
2371 fseg->reserved[0] = 0;
2372 fseg->reserved[1] = 0;
2373}
2374
6ff63e19
SM		 2375static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr)
2376{
2377 bseg->flags1 =
2378 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) &
2379 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ |
2380 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2381 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2382 bseg->flags2 = 0;
2383 if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2)
2384 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2385 if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED)
2386 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2387 bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey);
2388 bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey);
2389 bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr);
2390 bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length);
2391}
2392
95d04f07
RD		 2393static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2394{
aee38fad
SM		 2395 memset(iseg, 0, sizeof(*iseg));
2396 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 2397}
2398
0fbfa6a9
RD		 2399static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2400 u64 remote_addr, u32 rkey)
2401{
2402 rseg->raddr = cpu_to_be64(remote_addr);
2403 rseg->rkey = cpu_to_be32(rkey);
2404 rseg->reserved = 0;
2405}
2406
2407static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2408{
2409 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2410 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2411 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
6fa8f719
VS		 2412 } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2413 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2414 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add_mask);
0fbfa6a9
RD		 2415 } else {
2416 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2417 aseg->compare = 0;
2418 }
2419
2420}
2421
6fa8f719
VS		 2422static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2423 struct ib_send_wr *wr)
2424{
2425 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2426 aseg->swap_add_mask = cpu_to_be64(wr->wr.atomic.swap_mask);
2427 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
2428 aseg->compare_mask = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2429}
2430
0fbfa6a9 2431static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
80a2dcd8 2432 struct ib_send_wr *wr)
0fbfa6a9
RD		 2433{
2434 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2435 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2436 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
fa417f7b
EC		 2437 dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2438 memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
0fbfa6a9
RD		 2439}
2440
1ffeb2eb
JM		 2441static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2442 struct mlx4_wqe_datagram_seg *dseg,
97982f5a
JM		 2443 struct ib_send_wr *wr,
2444 enum mlx4_ib_qp_type qpt)
1ffeb2eb
JM		 2445{
2446 union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2447 struct mlx4_av sqp_av = {0};
2448 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2449
2450 /* force loopback */
2451 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2452 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2453 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2454 cpu_to_be32(0xf0000000);
2455
2456 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a
JM		 2457 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2458 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2459 else
2460 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
47605df9
JM		 2461 /* Use QKEY from the QP context, which is set by master */
2462 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 2463}
2464
2465static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2466{
2467 struct mlx4_wqe_inline_seg *inl = wqe;
2468 struct mlx4_ib_tunnel_header hdr;
2469 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2470 int spc;
2471 int i;
2472
2473 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2474 hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2475 hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2476 hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
5ea8bbfc
JM		 2477 memcpy(hdr.mac, ah->av.eth.mac, 6);
2478 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 2479
2480 spc = MLX4_INLINE_ALIGN -
2481 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2482 if (sizeof (hdr) <= spc) {
2483 memcpy(inl + 1, &hdr, sizeof (hdr));
2484 wmb();
2485 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2486 i = 1;
2487 } else {
2488 memcpy(inl + 1, &hdr, spc);
2489 wmb();
2490 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2491
2492 inl = (void *) (inl + 1) + spc;
2493 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2494 wmb();
2495 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2496 i = 2;
2497 }
2498
2499 *mlx_seg_len =
2500 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2501}
2502
6e694ea3
JM		 2503static void set_mlx_icrc_seg(void *dseg)
2504{
2505 u32 *t = dseg;
2506 struct mlx4_wqe_inline_seg *iseg = dseg;
2507
2508 t[1] = 0;
2509
2510 /*
2511 * Need a barrier here before writing the byte_count field to
2512 * make sure that all the data is visible before the
2513 * byte_count field is set. Otherwise, if the segment begins
2514 * a new cacheline, the HCA prefetcher could grab the 64-byte
2515 * chunk and get a valid (!= * 0xffffffff) byte count but
2516 * stale data, and end up sending the wrong data.
2517 */
2518 wmb();
2519
2520 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2521}
2522
2523static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 2524{
d420d9e3
RD		 2525 dseg->lkey = cpu_to_be32(sg->lkey);
2526 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 2527
2528 /*
2529 * Need a barrier here before writing the byte_count field to
2530 * make sure that all the data is visible before the
2531 * byte_count field is set. Otherwise, if the segment begins
2532 * a new cacheline, the HCA prefetcher could grab the 64-byte
2533 * chunk and get a valid (!= * 0xffffffff) byte count but
2534 * stale data, and end up sending the wrong data.
2535 */
2536 wmb();
2537
2538 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 2539}
2540
2242fa4f
RD		 2541static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2542{
2543 dseg->byte_count = cpu_to_be32(sg->length);
2544 dseg->lkey = cpu_to_be32(sg->lkey);
2545 dseg->addr = cpu_to_be64(sg->addr);
2546}
2547
47b37475 2548static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
0fd7e1d8 2549 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 2550 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e
EC		 2551{
2552 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2553
417608c2
EC		 2554 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2555 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 2556
2557 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2558 wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2559 return -EINVAL;
2560
2561 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2562
0fd7e1d8
RD		 2563 *lso_hdr_sz = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
2564 wr->wr.ud.hlen);
b832be1e
EC		 2565 *lso_seg_len = halign;
2566 return 0;
2567}
2568
95d04f07
RD		 2569static __be32 send_ieth(struct ib_send_wr *wr)
2570{
2571 switch (wr->opcode) {
2572 case IB_WR_SEND_WITH_IMM:
2573 case IB_WR_RDMA_WRITE_WITH_IMM:
2574 return wr->ex.imm_data;
2575
2576 case IB_WR_SEND_WITH_INV:
2577 return cpu_to_be32(wr->ex.invalidate_rkey);
2578
2579 default:
2580 return 0;
2581 }
2582}
2583
1ffeb2eb
JM		 2584static void add_zero_len_inline(void *wqe)
2585{
2586 struct mlx4_wqe_inline_seg *inl = wqe;
2587 memset(wqe, 0, 16);
2588 inl->byte_count = cpu_to_be32(1 << 31);
2589}
2590
225c7b1f
RD		 2591int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2592 struct ib_send_wr **bad_wr)
2593{
2594 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2595 void *wqe;
2596 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 2597 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 2598 unsigned long flags;
2599 int nreq;
2600 int err = 0;
ea54b10c
JM		 2601 unsigned ind;
2602 int uninitialized_var(stamp);
2603 int uninitialized_var(size);
a3d8e159 2604 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 2605 __be32 dummy;
2606 __be32 *lso_wqe;
2607 __be32 uninitialized_var(lso_hdr_sz);
417608c2 2608 __be32 blh;
225c7b1f
RD		 2609 int i;
2610
96db0e03 2611 spin_lock_irqsave(&qp->sq.lock, flags);
225c7b1f 2612
ea54b10c 2613 ind = qp->sq_next_wqe;
225c7b1f
RD		 2614
2615 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 2616 lso_wqe = &dummy;
417608c2 2617 blh = 0;
0fd7e1d8 2618
225c7b1f
RD		 2619 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2620 err = -ENOMEM;
2621 *bad_wr = wr;
2622 goto out;
2623 }
2624
2625 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2626 err = -EINVAL;
2627 *bad_wr = wr;
2628 goto out;
2629 }
2630
0e6e7416 2631 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 2632 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 2633
2634 ctrl->srcrb_flags =
2635 (wr->send_flags & IB_SEND_SIGNALED ?
2636 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2637 (wr->send_flags & IB_SEND_SOLICITED ?
2638 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 2639 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2640 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2641 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 2642 qp->sq_signal_bits;
2643
95d04f07 2644 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 2645
2646 wqe += sizeof *ctrl;
2647 size = sizeof *ctrl / 16;
2648
1ffeb2eb
JM		 2649 switch (qp->mlx4_ib_qp_type) {
2650 case MLX4_IB_QPT_RC:
2651 case MLX4_IB_QPT_UC:
225c7b1f
RD		 2652 switch (wr->opcode) {
2653 case IB_WR_ATOMIC_CMP_AND_SWP:
2654 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 2655 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
0fbfa6a9
RD		 2656 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2657 wr->wr.atomic.rkey);
225c7b1f
RD		 2658 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2659
0fbfa6a9 2660 set_atomic_seg(wqe, wr);
225c7b1f 2661 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 2662
225c7b1f
RD		 2663 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2664 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 2665
2666 break;
2667
2668 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2669 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2670 wr->wr.atomic.rkey);
2671 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2672
2673 set_masked_atomic_seg(wqe, wr);
2674 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
2675
2676 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2677 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 2678
2679 break;
2680
2681 case IB_WR_RDMA_READ:
2682 case IB_WR_RDMA_WRITE:
2683 case IB_WR_RDMA_WRITE_WITH_IMM:
0fbfa6a9
RD		 2684 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2685 wr->wr.rdma.rkey);
225c7b1f
RD		 2686 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2687 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 2688 break;
95d04f07
RD		 2689
2690 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 2691 ctrl->srcrb_flags |=
2692 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2693 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2694 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
2695 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2696 break;
2697
2698 case IB_WR_FAST_REG_MR:
2ac6bf4d
JM		 2699 ctrl->srcrb_flags |=
2700 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2701 set_fmr_seg(wqe, wr);
2702 wqe += sizeof (struct mlx4_wqe_fmr_seg);
2703 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2704 break;
225c7b1f 2705
6ff63e19
SM		 2706 case IB_WR_BIND_MW:
2707 ctrl->srcrb_flags |=
2708 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2709 set_bind_seg(wqe, wr);
2710 wqe += sizeof(struct mlx4_wqe_bind_seg);
2711 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2712 break;
225c7b1f
RD		 2713 default:
2714 /* No extra segments required for sends */
2715 break;
2716 }
2717 break;
2718
1ffeb2eb
JM		 2719 case MLX4_IB_QPT_TUN_SMI_OWNER:
2720 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2721 if (unlikely(err)) {
2722 *bad_wr = wr;
2723 goto out;
2724 }
2725 wqe += seglen;
2726 size += seglen / 16;
2727 break;
2728 case MLX4_IB_QPT_TUN_SMI:
2729 case MLX4_IB_QPT_TUN_GSI:
2730 /* this is a UD qp used in MAD responses to slaves. */
2731 set_datagram_seg(wqe, wr);
2732 /* set the forced-loopback bit in the data seg av */
2733 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2734 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2735 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2736 break;
2737 case MLX4_IB_QPT_UD:
80a2dcd8 2738 set_datagram_seg(wqe, wr);
225c7b1f
RD		 2739 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2740 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 2741
2742 if (wr->opcode == IB_WR_LSO) {
417608c2 2743 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
b832be1e
EC		 2744 if (unlikely(err)) {
2745 *bad_wr = wr;
2746 goto out;
2747 }
0fd7e1d8 2748 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 2749 wqe += seglen;
2750 size += seglen / 16;
2751 }
225c7b1f
RD		 2752 break;
2753
1ffeb2eb 2754 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1ffeb2eb
JM		 2755 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2756 if (unlikely(err)) {
2757 *bad_wr = wr;
2758 goto out;
2759 }
2760 wqe += seglen;
2761 size += seglen / 16;
2762 /* to start tunnel header on a cache-line boundary */
2763 add_zero_len_inline(wqe);
2764 wqe += 16;
2765 size++;
2766 build_tunnel_header(wr, wqe, &seglen);
2767 wqe += seglen;
2768 size += seglen / 16;
2769 break;
2770 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 2771 case MLX4_IB_QPT_PROXY_GSI:
2772 /* If we are tunneling special qps, this is a UD qp.
2773 * In this case we first add a UD segment targeting
2774 * the tunnel qp, and then add a header with address
2775 * information */
97982f5a
JM		 2776 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr,
2777 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 2778 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2779 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2780 build_tunnel_header(wr, wqe, &seglen);
2781 wqe += seglen;
2782 size += seglen / 16;
2783 break;
2784
2785 case MLX4_IB_QPT_SMI:
2786 case MLX4_IB_QPT_GSI:
f438000f
RD		 2787 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2788 if (unlikely(err)) {
225c7b1f
RD		 2789 *bad_wr = wr;
2790 goto out;
2791 }
f438000f
RD		 2792 wqe += seglen;
2793 size += seglen / 16;
225c7b1f
RD		 2794 break;
2795
2796 default:
2797 break;
2798 }
2799
6e694ea3
JM		 2800 /*
2801 * Write data segments in reverse order, so as to
2802 * overwrite cacheline stamp last within each
2803 * cacheline. This avoids issues with WQE
2804 * prefetching.
2805 */
225c7b1f 2806
6e694ea3
JM		 2807 dseg = wqe;
2808 dseg += wr->num_sge - 1;
2809 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 2810
2811 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 2812 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2813 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2814 qp->mlx4_ib_qp_type &
2815 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 2816 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 2817 size += sizeof (struct mlx4_wqe_data_seg) / 16;
2818 }
2819
6e694ea3
JM		 2820 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2821 set_data_seg(dseg, wr->sg_list + i);
2822
0fd7e1d8
RD		 2823 /*
2824 * Possibly overwrite stamping in cacheline with LSO
2825 * segment only after making sure all data segments
2826 * are written.
2827 */
2828 wmb();
2829 *lso_wqe = lso_hdr_sz;
2830
225c7b1f
RD		 2831 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2832 MLX4_WQE_CTRL_FENCE : 0) | size;
2833
2834 /*
2835 * Make sure descriptor is fully written before
2836 * setting ownership bit (because HW can start
2837 * executing as soon as we do).
2838 */
2839 wmb();
2840
59b0ed12 2841 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 2842 *bad_wr = wr;
225c7b1f
RD		 2843 err = -EINVAL;
2844 goto out;
2845 }
2846
2847 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 2848 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 2849
ea54b10c
JM		 2850 stamp = ind + qp->sq_spare_wqes;
2851 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2852
0e6e7416
RD		 2853 /*
2854 * We can improve latency by not stamping the last
2855 * send queue WQE until after ringing the doorbell, so
2856 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 2857 *
2858 * Same optimization applies to padding with NOP wqe
2859 * in case of WQE shrinking (used to prevent wrap-around
2860 * in the middle of WR).
0e6e7416 2861 */
ea54b10c
JM		 2862 if (wr->next) {
2863 stamp_send_wqe(qp, stamp, size * 16);
2864 ind = pad_wraparound(qp, ind);
2865 }
225c7b1f
RD		 2866 }
2867
2868out:
2869 if (likely(nreq)) {
2870 qp->sq.head += nreq;
2871
2872 /*
2873 * Make sure that descriptors are written before
2874 * doorbell record.
2875 */
2876 wmb();
2877
2878 writel(qp->doorbell_qpn,
2879 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
2880
2881 /*
2882 * Make sure doorbells don't leak out of SQ spinlock
2883 * and reach the HCA out of order.
2884 */
2885 mmiowb();
0e6e7416 2886
ea54b10c
JM		 2887 stamp_send_wqe(qp, stamp, size * 16);
2888
2889 ind = pad_wraparound(qp, ind);
2890 qp->sq_next_wqe = ind;
225c7b1f
RD		 2891 }
2892
96db0e03 2893 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 2894
2895 return err;
2896}
2897
2898int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2899 struct ib_recv_wr **bad_wr)
2900{
2901 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2902 struct mlx4_wqe_data_seg *scat;
2903 unsigned long flags;
2904 int err = 0;
2905 int nreq;
2906 int ind;
1ffeb2eb 2907 int max_gs;
225c7b1f
RD		 2908 int i;
2909
1ffeb2eb 2910 max_gs = qp->rq.max_gs;
225c7b1f
RD		 2911 spin_lock_irqsave(&qp->rq.lock, flags);
2912
0e6e7416 2913 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 2914
2915 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 2916 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 2917 err = -ENOMEM;
2918 *bad_wr = wr;
2919 goto out;
2920 }
2921
2922 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2923 err = -EINVAL;
2924 *bad_wr = wr;
2925 goto out;
2926 }
2927
2928 scat = get_recv_wqe(qp, ind);
2929
1ffeb2eb
JM		 2930 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
2931 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
2932 ib_dma_sync_single_for_device(ibqp->device,
2933 qp->sqp_proxy_rcv[ind].map,
2934 sizeof (struct mlx4_ib_proxy_sqp_hdr),
2935 DMA_FROM_DEVICE);
2936 scat->byte_count =
2937 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
2938 /* use dma lkey from upper layer entry */
2939 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
2940 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
2941 scat++;
2942 max_gs--;
2943 }
2944
2242fa4f
RD		 2945 for (i = 0; i < wr->num_sge; ++i)
2946 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 2947
1ffeb2eb 2948 if (i < max_gs) {
225c7b1f
RD		 2949 scat[i].byte_count = 0;
2950 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
2951 scat[i].addr = 0;
2952 }
2953
2954 qp->rq.wrid[ind] = wr->wr_id;
2955
0e6e7416 2956 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 2957 }
2958
2959out:
2960 if (likely(nreq)) {
2961 qp->rq.head += nreq;
2962
2963 /*
2964 * Make sure that descriptors are written before
2965 * doorbell record.
2966 */
2967 wmb();
2968
2969 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2970 }
2971
2972 spin_unlock_irqrestore(&qp->rq.lock, flags);
2973
2974 return err;
2975}
6a775e2b
JM		 2976
2977static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
2978{
2979 switch (mlx4_state) {
2980 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
2981 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
2982 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
2983 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
2984 case MLX4_QP_STATE_SQ_DRAINING:
2985 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
2986 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
2987 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
2988 default: return -1;
2989 }
2990}
2991
2992static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
2993{
2994 switch (mlx4_mig_state) {
2995 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
2996 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
2997 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
2998 default: return -1;
2999 }
3000}
3001
3002static int to_ib_qp_access_flags(int mlx4_flags)
3003{
3004 int ib_flags = 0;
3005
3006 if (mlx4_flags & MLX4_QP_BIT_RRE)
3007 ib_flags |= IB_ACCESS_REMOTE_READ;
3008 if (mlx4_flags & MLX4_QP_BIT_RWE)
3009 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3010 if (mlx4_flags & MLX4_QP_BIT_RAE)
3011 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3012
3013 return ib_flags;
3014}
3015
4c3eb3ca 3016static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
6a775e2b
JM		 3017 struct mlx4_qp_path *path)
3018{
4c3eb3ca
EC		 3019 struct mlx4_dev *dev = ibdev->dev;
3020 int is_eth;
3021
8fcea95a 3022 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 3023 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
3024
3025 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3026 return;
3027
4c3eb3ca
EC		 3028 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3029 IB_LINK_LAYER_ETHERNET;
3030 if (is_eth)
3031 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3032 ((path->sched_queue & 4) << 1);
3033 else
3034 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3035
6a775e2b 3036 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
6a775e2b
JM		 3037 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3038 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3039 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3040 if (ib_ah_attr->ah_flags) {
3041 ib_ah_attr->grh.sgid_index = path->mgid_index;
3042 ib_ah_attr->grh.hop_limit = path->hop_limit;
3043 ib_ah_attr->grh.traffic_class =
3044 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3045 ib_ah_attr->grh.flow_label =
586bb586 3046 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 3047 memcpy(ib_ah_attr->grh.dgid.raw,
3048 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3049 }
3050}
3051
3052int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3053 struct ib_qp_init_attr *qp_init_attr)
3054{
3055 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3056 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3057 struct mlx4_qp_context context;
3058 int mlx4_state;
0df67030
DB		 3059 int err = 0;
3060
3061 mutex_lock(&qp->mutex);
6a775e2b
JM		 3062
3063 if (qp->state == IB_QPS_RESET) {
3064 qp_attr->qp_state = IB_QPS_RESET;
3065 goto done;
3066 }
3067
3068 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3069 if (err) {
3070 err = -EINVAL;
3071 goto out;
3072 }
6a775e2b
JM		 3073
3074 mlx4_state = be32_to_cpu(context.flags) >> 28;
3075
0df67030
DB		 3076 qp->state = to_ib_qp_state(mlx4_state);
3077 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3078 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3079 qp_attr->path_mig_state =
3080 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3081 qp_attr->qkey = be32_to_cpu(context.qkey);
3082 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3083 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3084 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3085 qp_attr->qp_access_flags =
3086 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3087
3088 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4c3eb3ca
EC		 3089 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3090 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b
JM		 3091 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3092 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3093 }
3094
3095 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 3096 if (qp_attr->qp_state == IB_QPS_INIT)
3097 qp_attr->port_num = qp->port;
3098 else
3099 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 3100
3101 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3102 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3103
3104 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3105
3106 qp_attr->max_dest_rd_atomic =
3107 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3108 qp_attr->min_rnr_timer =
3109 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3110 qp_attr->timeout = context.pri_path.ackto >> 3;
3111 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3112 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3113 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3114
3115done:
3116 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 3117 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3118 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3119
6a775e2b 3120 if (!ibqp->uobject) {
7f5eb9bb
RD		 3121 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3122 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3123 } else {
3124 qp_attr->cap.max_send_wr = 0;
3125 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 3126 }
3127
7f5eb9bb
RD		 3128 /*
3129 * We don't support inline sends for kernel QPs (yet), and we
3130 * don't know what userspace's value should be.
3131 */
3132 qp_attr->cap.max_inline_data = 0;
3133
3134 qp_init_attr->cap = qp_attr->cap;
3135
521e575b
RL		 3136 qp_init_attr->create_flags = 0;
3137 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3138 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3139
3140 if (qp->flags & MLX4_IB_QP_LSO)
3141 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3142
c1c98501
MB		 3143 if (qp->flags & MLX4_IB_QP_NETIF)
3144 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3145
46db567d
DB		 3146 qp_init_attr->sq_sig_type =
3147 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3148 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3149
0df67030
DB		 3150out:
3151 mutex_unlock(&qp->mutex);
3152 return err;
6a775e2b
JM		 3153}
3154
Linux 6.x block layer and io_uring tree(s)