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IB/mlx4: Adjust duplicate test
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
5a0e3ad6 35#include <linux/slab.h>
fa417f7b 36#include <linux/netdevice.h>
ea54b10c 37
225c7b1f
RD		 38#include <rdma/ib_cache.h>
39#include <rdma/ib_pack.h>
4c3eb3ca 40#include <rdma/ib_addr.h>
1ffeb2eb 41#include <rdma/ib_mad.h>
225c7b1f
RD		 42
43#include <linux/mlx4/qp.h>
44
45#include "mlx4_ib.h"
46#include "user.h"
47
48enum {
49 MLX4_IB_ACK_REQ_FREQ = 8,
50};
51
52enum {
53 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 54 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
55 MLX4_IB_LINK_TYPE_IB = 0,
56 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 57};
58
59enum {
60 /*
fa417f7b 61 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 62 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
63 * tag. (LRH would only use 8 bytes, so Ethernet is the
64 * biggest case)
225c7b1f 65 */
4c3eb3ca 66 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 67 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 68};
69
fa417f7b
EC		 70enum {
71 MLX4_IB_IBOE_ETHERTYPE = 0x8915
72};
73
225c7b1f
RD		 74struct mlx4_ib_sqp {
75 struct mlx4_ib_qp qp;
76 int pkey_index;
77 u32 qkey;
78 u32 send_psn;
79 struct ib_ud_header ud_header;
80 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
81};
82
83904132 83enum {
417608c2
EC		 84 MLX4_IB_MIN_SQ_STRIDE = 6,
85 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 86};
87
3987a2d3
OG		 88enum {
89 MLX4_RAW_QP_MTU = 7,
90 MLX4_RAW_QP_MSGMAX = 31,
91};
92
225c7b1f 93static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 94 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
95 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
96 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
97 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
98 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
99 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
100 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
101 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
102 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
103 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
104 [IB_WR_FAST_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
105 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
106 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 107};
108
109static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
110{
111 return container_of(mqp, struct mlx4_ib_sqp, qp);
112}
113
1ffeb2eb
JM		 114static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
115{
116 if (!mlx4_is_master(dev->dev))
117 return 0;
118
47605df9
JM		 119 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
120 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
121 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 122}
123
225c7b1f
RD		 124static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
125{
47605df9
JM		 126 int proxy_sqp = 0;
127 int real_sqp = 0;
128 int i;
129 /* PPF or Native -- real SQP */
130 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
131 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
132 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
133 if (real_sqp)
134 return 1;
135 /* VF or PF -- proxy SQP */
136 if (mlx4_is_mfunc(dev->dev)) {
137 for (i = 0; i < dev->dev->caps.num_ports; i++) {
138 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
139 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
140 proxy_sqp = 1;
141 break;
142 }
143 }
144 }
145 return proxy_sqp;
225c7b1f
RD		 146}
147
1ffeb2eb 148/* used for INIT/CLOSE port logic */
225c7b1f
RD		 149static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
150{
47605df9
JM		 151 int proxy_qp0 = 0;
152 int real_qp0 = 0;
153 int i;
154 /* PPF or Native -- real QP0 */
155 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
156 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
157 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
158 if (real_qp0)
159 return 1;
160 /* VF or PF -- proxy QP0 */
161 if (mlx4_is_mfunc(dev->dev)) {
162 for (i = 0; i < dev->dev->caps.num_ports; i++) {
163 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
164 proxy_qp0 = 1;
165 break;
166 }
167 }
168 }
169 return proxy_qp0;
225c7b1f
RD		 170}
171
172static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
173{
1c69fc2a 174 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 175}
176
177static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
178{
179 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
180}
181
182static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
183{
184 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
185}
186
0e6e7416
RD		 187/*
188 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 189 * first four bytes of every 64 byte chunk with
190 * 0x7FFFFFF | (invalid_ownership_value << 31).
191 *
192 * When the max work request size is less than or equal to the WQE
193 * basic block size, as an optimization, we can stamp all WQEs with
194 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 195 */
ea54b10c 196static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 197{
d2ae16d5 198 __be32 *wqe;
0e6e7416 199 int i;
ea54b10c
JM		 200 int s;
201 int ind;
202 void *buf;
203 __be32 stamp;
9670e553 204 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 205
ea54b10c 206 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 207 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 208 for (i = 0; i < s; i += 64) {
209 ind = (i >> qp->sq.wqe_shift) + n;
210 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
211 cpu_to_be32(0xffffffff);
212 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
213 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
214 *wqe = stamp;
215 }
216 } else {
9670e553
EC		 217 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
218 s = (ctrl->fence_size & 0x3f) << 4;
ea54b10c
JM		 219 for (i = 64; i < s; i += 64) {
220 wqe = buf + i;
d2ae16d5 221 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 222 }
223 }
224}
225
226static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
227{
228 struct mlx4_wqe_ctrl_seg *ctrl;
229 struct mlx4_wqe_inline_seg *inl;
230 void *wqe;
231 int s;
232
233 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
234 s = sizeof(struct mlx4_wqe_ctrl_seg);
235
236 if (qp->ibqp.qp_type == IB_QPT_UD) {
237 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
238 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
239 memset(dgram, 0, sizeof *dgram);
240 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
241 s += sizeof(struct mlx4_wqe_datagram_seg);
242 }
243
244 /* Pad the remainder of the WQE with an inline data segment. */
245 if (size > s) {
246 inl = wqe + s;
247 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
248 }
249 ctrl->srcrb_flags = 0;
250 ctrl->fence_size = size / 16;
251 /*
252 * Make sure descriptor is fully written before setting ownership bit
253 * (because HW can start executing as soon as we do).
254 */
255 wmb();
256
257 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
258 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 259
ea54b10c
JM		 260 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
261}
262
263/* Post NOP WQE to prevent wrap-around in the middle of WR */
264static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
265{
266 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
267 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
268 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
269 ind += s;
270 }
271 return ind;
0e6e7416
RD		 272}
273
225c7b1f
RD		 274static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
275{
276 struct ib_event event;
277 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
278
279 if (type == MLX4_EVENT_TYPE_PATH_MIG)
280 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
281
282 if (ibqp->event_handler) {
283 event.device = ibqp->device;
284 event.element.qp = ibqp;
285 switch (type) {
286 case MLX4_EVENT_TYPE_PATH_MIG:
287 event.event = IB_EVENT_PATH_MIG;
288 break;
289 case MLX4_EVENT_TYPE_COMM_EST:
290 event.event = IB_EVENT_COMM_EST;
291 break;
292 case MLX4_EVENT_TYPE_SQ_DRAINED:
293 event.event = IB_EVENT_SQ_DRAINED;
294 break;
295 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
296 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
297 break;
298 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
299 event.event = IB_EVENT_QP_FATAL;
300 break;
301 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
302 event.event = IB_EVENT_PATH_MIG_ERR;
303 break;
304 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
305 event.event = IB_EVENT_QP_REQ_ERR;
306 break;
307 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
308 event.event = IB_EVENT_QP_ACCESS_ERR;
309 break;
310 default:
987c8f8f 311 pr_warn("Unexpected event type %d "
225c7b1f
RD		 312 "on QP %06x\n", type, qp->qpn);
313 return;
314 }
315
316 ibqp->event_handler(&event, ibqp->qp_context);
317 }
318}
319
1ffeb2eb 320static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 321{
322 /*
323 * UD WQEs must have a datagram segment.
324 * RC and UC WQEs might have a remote address segment.
325 * MLX WQEs need two extra inline data segments (for the UD
326 * header and space for the ICRC).
327 */
328 switch (type) {
1ffeb2eb 329 case MLX4_IB_QPT_UD:
225c7b1f 330 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 331 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 332 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 333 case MLX4_IB_QPT_PROXY_SMI_OWNER:
334 case MLX4_IB_QPT_PROXY_SMI:
335 case MLX4_IB_QPT_PROXY_GSI:
336 return sizeof (struct mlx4_wqe_ctrl_seg) +
337 sizeof (struct mlx4_wqe_datagram_seg) + 64;
338 case MLX4_IB_QPT_TUN_SMI_OWNER:
339 case MLX4_IB_QPT_TUN_GSI:
340 return sizeof (struct mlx4_wqe_ctrl_seg) +
341 sizeof (struct mlx4_wqe_datagram_seg);
342
343 case MLX4_IB_QPT_UC:
225c7b1f
RD		 344 return sizeof (struct mlx4_wqe_ctrl_seg) +
345 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 346 case MLX4_IB_QPT_RC:
225c7b1f
RD		 347 return sizeof (struct mlx4_wqe_ctrl_seg) +
348 sizeof (struct mlx4_wqe_atomic_seg) +
349 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 350 case MLX4_IB_QPT_SMI:
351 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 352 return sizeof (struct mlx4_wqe_ctrl_seg) +
353 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 354 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
355 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 356 sizeof (struct mlx4_wqe_inline_seg),
357 sizeof (struct mlx4_wqe_data_seg)) +
358 ALIGN(4 +
359 sizeof (struct mlx4_wqe_inline_seg),
360 sizeof (struct mlx4_wqe_data_seg));
361 default:
362 return sizeof (struct mlx4_wqe_ctrl_seg);
363 }
364}
365
2446304d 366static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
0a1405da 367 int is_user, int has_rq, struct mlx4_ib_qp *qp)
225c7b1f 368{
2446304d 369 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 370 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
371 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 372 return -EINVAL;
373
0a1405da 374 if (!has_rq) {
a4cd7ed8
RD		 375 if (cap->max_recv_wr)
376 return -EINVAL;
2446304d 377
0e6e7416 378 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 379 } else {
380 /* HW requires >= 1 RQ entry with >= 1 gather entry */
381 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
382 return -EINVAL;
383
0e6e7416 384 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 385 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 386 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
387 }
2446304d 388
fc2d0044
SG		 389 /* leave userspace return values as they were, so as not to break ABI */
390 if (is_user) {
391 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
392 cap->max_recv_sge = qp->rq.max_gs;
393 } else {
394 cap->max_recv_wr = qp->rq.max_post =
395 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
396 cap->max_recv_sge = min(qp->rq.max_gs,
397 min(dev->dev->caps.max_sq_sg,
398 dev->dev->caps.max_rq_sg));
399 }
2446304d
EC		 400
401 return 0;
402}
403
404static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
1ffeb2eb 405 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 406{
ea54b10c
JM		 407 int s;
408
2446304d 409 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 410 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
411 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 412 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 413 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
414 return -EINVAL;
415
416 /*
417 * For MLX transport we need 2 extra S/G entries:
418 * one for the header and one for the checksum at the end
419 */
1ffeb2eb
JM		 420 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
421 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 422 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
423 return -EINVAL;
424
ea54b10c
JM		 425 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
426 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 427 send_wqe_overhead(type, qp->flags);
225c7b1f 428
cd155c1c
RD		 429 if (s > dev->dev->caps.max_sq_desc_sz)
430 return -EINVAL;
431
0e6e7416 432 /*
ea54b10c
JM		 433 * Hermon supports shrinking WQEs, such that a single work
434 * request can include multiple units of 1 << wqe_shift. This
435 * way, work requests can differ in size, and do not have to
436 * be a power of 2 in size, saving memory and speeding up send
437 * WR posting. Unfortunately, if we do this then the
438 * wqe_index field in CQEs can't be used to look up the WR ID
439 * anymore, so we do this only if selective signaling is off.
440 *
441 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 442 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 443 * constant-sized WRs to make sure a WR is always fully within
444 * a single page-sized chunk.
445 *
446 * Finally, we use NOP work requests to pad the end of the
447 * work queue, to avoid wrap-around in the middle of WR. We
448 * set NEC bit to avoid getting completions with error for
449 * these NOP WRs, but since NEC is only supported starting
450 * with firmware 2.2.232, we use constant-sized WRs for older
451 * firmware.
452 *
453 * And, since MLX QPs only support SEND, we use constant-sized
454 * WRs in this case.
455 *
456 * We look for the smallest value of wqe_shift such that the
457 * resulting number of wqes does not exceed device
458 * capabilities.
459 *
460 * We set WQE size to at least 64 bytes, this way stamping
461 * invalidates each WQE.
0e6e7416 462 */
ea54b10c
JM		 463 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
464 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 465 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
466 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
467 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 468 qp->sq.wqe_shift = ilog2(64);
469 else
470 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
471
472 for (;;) {
ea54b10c
JM		 473 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
474
475 /*
476 * We need to leave 2 KB + 1 WR of headroom in the SQ to
477 * allow HW to prefetch.
478 */
479 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
480 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
481 qp->sq_max_wqes_per_wr +
482 qp->sq_spare_wqes);
483
484 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
485 break;
486
487 if (qp->sq_max_wqes_per_wr <= 1)
488 return -EINVAL;
489
490 ++qp->sq.wqe_shift;
491 }
492
cd155c1c
RD		 493 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
494 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 495 send_wqe_overhead(type, qp->flags)) /
496 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 497
498 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
499 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 500 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
501 qp->rq.offset = 0;
0e6e7416 502 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 503 } else {
0e6e7416 504 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 505 qp->sq.offset = 0;
506 }
507
ea54b10c
JM		 508 cap->max_send_wr = qp->sq.max_post =
509 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 510 cap->max_send_sge = min(qp->sq.max_gs,
511 min(dev->dev->caps.max_sq_sg,
512 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 513 /* We don't support inline sends for kernel QPs (yet) */
514 cap->max_inline_data = 0;
225c7b1f
RD		 515
516 return 0;
517}
518
83904132
JM		 519static int set_user_sq_size(struct mlx4_ib_dev *dev,
520 struct mlx4_ib_qp *qp,
2446304d
EC		 521 struct mlx4_ib_create_qp *ucmd)
522{
83904132
JM		 523 /* Sanity check SQ size before proceeding */
524 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
525 ucmd->log_sq_stride >
526 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
527 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
528 return -EINVAL;
529
0e6e7416 530 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 531 qp->sq.wqe_shift = ucmd->log_sq_stride;
532
0e6e7416
RD		 533 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
534 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 535
536 return 0;
537}
538
1ffeb2eb
JM		 539static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
540{
541 int i;
542
543 qp->sqp_proxy_rcv =
544 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
545 GFP_KERNEL);
546 if (!qp->sqp_proxy_rcv)
547 return -ENOMEM;
548 for (i = 0; i < qp->rq.wqe_cnt; i++) {
549 qp->sqp_proxy_rcv[i].addr =
550 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
551 GFP_KERNEL);
552 if (!qp->sqp_proxy_rcv[i].addr)
553 goto err;
554 qp->sqp_proxy_rcv[i].map =
555 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
556 sizeof (struct mlx4_ib_proxy_sqp_hdr),
557 DMA_FROM_DEVICE);
558 }
559 return 0;
560
561err:
562 while (i > 0) {
563 --i;
564 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
565 sizeof (struct mlx4_ib_proxy_sqp_hdr),
566 DMA_FROM_DEVICE);
567 kfree(qp->sqp_proxy_rcv[i].addr);
568 }
569 kfree(qp->sqp_proxy_rcv);
570 qp->sqp_proxy_rcv = NULL;
571 return -ENOMEM;
572}
573
574static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
575{
576 int i;
577
578 for (i = 0; i < qp->rq.wqe_cnt; i++) {
579 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
580 sizeof (struct mlx4_ib_proxy_sqp_hdr),
581 DMA_FROM_DEVICE);
582 kfree(qp->sqp_proxy_rcv[i].addr);
583 }
584 kfree(qp->sqp_proxy_rcv);
585}
586
0a1405da
SH		 587static int qp_has_rq(struct ib_qp_init_attr *attr)
588{
589 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
590 return 0;
591
592 return !attr->srq;
593}
594
225c7b1f
RD		 595static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
596 struct ib_qp_init_attr *init_attr,
1ffeb2eb 597 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp)
225c7b1f 598{
a3cdcbfa 599 int qpn;
225c7b1f 600 int err;
1ffeb2eb
JM		 601 struct mlx4_ib_sqp *sqp;
602 struct mlx4_ib_qp *qp;
603 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
604
605 /* When tunneling special qps, we use a plain UD qp */
606 if (sqpn) {
607 if (mlx4_is_mfunc(dev->dev) &&
608 (!mlx4_is_master(dev->dev) ||
609 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
610 if (init_attr->qp_type == IB_QPT_GSI)
611 qp_type = MLX4_IB_QPT_PROXY_GSI;
612 else if (mlx4_is_master(dev->dev))
613 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
614 else
615 qp_type = MLX4_IB_QPT_PROXY_SMI;
616 }
617 qpn = sqpn;
618 /* add extra sg entry for tunneling */
619 init_attr->cap.max_recv_sge++;
620 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
621 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
622 container_of(init_attr,
623 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
624 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
625 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
626 !mlx4_is_master(dev->dev))
627 return -EINVAL;
628 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
629 qp_type = MLX4_IB_QPT_TUN_GSI;
630 else if (tnl_init->slave == mlx4_master_func_num(dev->dev))
631 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
632 else
633 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 634 /* we are definitely in the PPF here, since we are creating
635 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
636 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
637 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 638 sqpn = qpn;
639 }
640
641 if (!*caller_qp) {
642 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
643 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
644 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
645 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), GFP_KERNEL);
646 if (!sqp)
647 return -ENOMEM;
648 qp = &sqp->qp;
649 } else {
650 qp = kzalloc(sizeof (struct mlx4_ib_qp), GFP_KERNEL);
651 if (!qp)
652 return -ENOMEM;
653 }
654 } else
655 qp = *caller_qp;
656
657 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 658
659 mutex_init(&qp->mutex);
660 spin_lock_init(&qp->sq.lock);
661 spin_lock_init(&qp->rq.lock);
fa417f7b 662 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 663 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 664
665 qp->state = IB_QPS_RESET;
ea54b10c
JM		 666 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
667 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 668
0a1405da 669 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
225c7b1f
RD		 670 if (err)
671 goto err;
672
673 if (pd->uobject) {
674 struct mlx4_ib_create_qp ucmd;
675
676 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
677 err = -EFAULT;
678 goto err;
679 }
680
0e6e7416
RD		 681 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
682
83904132 683 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 684 if (err)
685 goto err;
686
225c7b1f 687 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 688 qp->buf_size, 0, 0);
225c7b1f
RD		 689 if (IS_ERR(qp->umem)) {
690 err = PTR_ERR(qp->umem);
691 goto err;
692 }
693
694 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
695 ilog2(qp->umem->page_size), &qp->mtt);
696 if (err)
697 goto err_buf;
698
699 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
700 if (err)
701 goto err_mtt;
702
0a1405da 703 if (qp_has_rq(init_attr)) {
02d89b87
RD		 704 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
705 ucmd.db_addr, &qp->db);
706 if (err)
707 goto err_mtt;
708 }
225c7b1f 709 } else {
0e6e7416
RD		 710 qp->sq_no_prefetch = 0;
711
521e575b
RL		 712 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
713 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
714
b832be1e
EC		 715 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
716 qp->flags |= MLX4_IB_QP_LSO;
717
1ffeb2eb 718 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 719 if (err)
720 goto err;
721
0a1405da 722 if (qp_has_rq(init_attr)) {
6296883c 723 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 724 if (err)
725 goto err;
225c7b1f 726
02d89b87
RD		 727 *qp->db.db = 0;
728 }
225c7b1f
RD		 729
730 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
731 err = -ENOMEM;
732 goto err_db;
733 }
734
735 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
736 &qp->mtt);
737 if (err)
738 goto err_buf;
739
740 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
741 if (err)
742 goto err_mtt;
743
0e6e7416
RD		 744 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
745 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
225c7b1f
RD		 746
747 if (!qp->sq.wrid || !qp->rq.wrid) {
748 err = -ENOMEM;
749 goto err_wrid;
750 }
225c7b1f
RD		 751 }
752
a3cdcbfa 753 if (sqpn) {
1ffeb2eb
JM		 754 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
755 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
756 if (alloc_proxy_bufs(pd->device, qp)) {
757 err = -ENOMEM;
758 goto err_wrid;
759 }
760 }
a3cdcbfa 761 } else {
3987a2d3
OG		 762 /* Raw packet QPNs must be aligned to 8 bits. If not, the WQE
763 * BlueFlame setup flow wrongly causes VLAN insertion. */
764 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
765 err = mlx4_qp_reserve_range(dev->dev, 1, 1 << 8, &qpn);
766 else
767 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn);
a3cdcbfa 768 if (err)
1ffeb2eb 769 goto err_proxy;
a3cdcbfa
YP		 770 }
771
772 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
225c7b1f 773 if (err)
a3cdcbfa 774 goto err_qpn;
225c7b1f 775
0a1405da
SH		 776 if (init_attr->qp_type == IB_QPT_XRC_TGT)
777 qp->mqp.qpn |= (1 << 23);
778
225c7b1f
RD		 779 /*
780 * Hardware wants QPN written in big-endian order (after
781 * shifting) for send doorbell. Precompute this value to save
782 * a little bit when posting sends.
783 */
784 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
785
225c7b1f 786 qp->mqp.event = mlx4_ib_qp_event;
1ffeb2eb
JM		 787 if (!*caller_qp)
788 *caller_qp = qp;
225c7b1f
RD		 789 return 0;
790
a3cdcbfa
YP		 791err_qpn:
792 if (!sqpn)
793 mlx4_qp_release_range(dev->dev, qpn, 1);
1ffeb2eb
JM		 794err_proxy:
795 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
796 free_proxy_bufs(pd->device, qp);
225c7b1f 797err_wrid:
23f1b384 798 if (pd->uobject) {
0a1405da
SH		 799 if (qp_has_rq(init_attr))
800 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 801 } else {
225c7b1f
RD		 802 kfree(qp->sq.wrid);
803 kfree(qp->rq.wrid);
804 }
805
806err_mtt:
807 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
808
809err_buf:
810 if (pd->uobject)
811 ib_umem_release(qp->umem);
812 else
813 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
814
815err_db:
0a1405da 816 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 817 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 818
819err:
1ffeb2eb
JM		 820 if (!*caller_qp)
821 kfree(qp);
225c7b1f
RD		 822 return err;
823}
824
825static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
826{
827 switch (state) {
828 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
829 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
830 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
831 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
832 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
833 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
834 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
835 default: return -1;
836 }
837}
838
839static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 840 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 841{
338a8fad 842 if (send_cq == recv_cq) {
225c7b1f 843 spin_lock_irq(&send_cq->lock);
338a8fad
RD		 844 __acquire(&recv_cq->lock);
845 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f
RD		 846 spin_lock_irq(&send_cq->lock);
847 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
848 } else {
849 spin_lock_irq(&recv_cq->lock);
850 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
851 }
852}
853
854static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 855 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 856{
338a8fad
RD		 857 if (send_cq == recv_cq) {
858 __release(&recv_cq->lock);
225c7b1f 859 spin_unlock_irq(&send_cq->lock);
338a8fad 860 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f
RD		 861 spin_unlock(&recv_cq->lock);
862 spin_unlock_irq(&send_cq->lock);
863 } else {
864 spin_unlock(&send_cq->lock);
865 spin_unlock_irq(&recv_cq->lock);
866 }
867}
868
fa417f7b
EC		 869static void del_gid_entries(struct mlx4_ib_qp *qp)
870{
871 struct mlx4_ib_gid_entry *ge, *tmp;
872
873 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
874 list_del(&ge->list);
875 kfree(ge);
876 }
877}
878
0a1405da
SH		 879static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
880{
881 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
882 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
883 else
884 return to_mpd(qp->ibqp.pd);
885}
886
887static void get_cqs(struct mlx4_ib_qp *qp,
888 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
889{
890 switch (qp->ibqp.qp_type) {
891 case IB_QPT_XRC_TGT:
892 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
893 *recv_cq = *send_cq;
894 break;
895 case IB_QPT_XRC_INI:
896 *send_cq = to_mcq(qp->ibqp.send_cq);
897 *recv_cq = *send_cq;
898 break;
899 default:
900 *send_cq = to_mcq(qp->ibqp.send_cq);
901 *recv_cq = to_mcq(qp->ibqp.recv_cq);
902 break;
903 }
904}
905
225c7b1f
RD		 906static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
907 int is_user)
908{
909 struct mlx4_ib_cq *send_cq, *recv_cq;
910
911 if (qp->state != IB_QPS_RESET)
912 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
913 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 914 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f
RD		 915 qp->mqp.qpn);
916
0a1405da 917 get_cqs(qp, &send_cq, &recv_cq);
225c7b1f
RD		 918
919 mlx4_ib_lock_cqs(send_cq, recv_cq);
920
921 if (!is_user) {
922 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
923 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
924 if (send_cq != recv_cq)
925 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
926 }
927
928 mlx4_qp_remove(dev->dev, &qp->mqp);
929
930 mlx4_ib_unlock_cqs(send_cq, recv_cq);
931
932 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 933
1ffeb2eb 934 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp))
a3cdcbfa
YP		 935 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
936
225c7b1f
RD		 937 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
938
939 if (is_user) {
0a1405da 940 if (qp->rq.wqe_cnt)
02d89b87
RD		 941 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
942 &qp->db);
225c7b1f
RD		 943 ib_umem_release(qp->umem);
944 } else {
945 kfree(qp->sq.wrid);
946 kfree(qp->rq.wrid);
1ffeb2eb
JM		 947 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
948 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
949 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 950 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 951 if (qp->rq.wqe_cnt)
6296883c 952 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 953 }
fa417f7b
EC		 954
955 del_gid_entries(qp);
225c7b1f
RD		 956}
957
47605df9
JM		 958static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
959{
960 /* Native or PPF */
961 if (!mlx4_is_mfunc(dev->dev) ||
962 (mlx4_is_master(dev->dev) &&
963 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
964 return dev->dev->phys_caps.base_sqpn +
965 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
966 attr->port_num - 1;
967 }
968 /* PF or VF -- creating proxies */
969 if (attr->qp_type == IB_QPT_SMI)
970 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
971 else
972 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
973}
974
225c7b1f
RD		 975struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
976 struct ib_qp_init_attr *init_attr,
977 struct ib_udata *udata)
978{
1ffeb2eb 979 struct mlx4_ib_qp *qp = NULL;
225c7b1f 980 int err;
0a1405da 981 u16 xrcdn = 0;
225c7b1f 982
521e575b 983 /*
1ffeb2eb
JM		 984 * We only support LSO, vendor flag1, and multicast loopback blocking,
985 * and only for kernel UD QPs.
521e575b 986 */
1ffeb2eb
JM		 987 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
988 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
989 MLX4_IB_SRIOV_TUNNEL_QP | MLX4_IB_SRIOV_SQP))
b832be1e 990 return ERR_PTR(-EINVAL);
521e575b
RL		 991
992 if (init_attr->create_flags &&
1ffeb2eb
JM		 993 (udata ||
994 ((init_attr->create_flags & ~MLX4_IB_SRIOV_SQP) &&
995 init_attr->qp_type != IB_QPT_UD) ||
996 ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
997 init_attr->qp_type > IB_QPT_GSI)))
b846f25a
EC		 998 return ERR_PTR(-EINVAL);
999
225c7b1f 1000 switch (init_attr->qp_type) {
0a1405da
SH		 1001 case IB_QPT_XRC_TGT:
1002 pd = to_mxrcd(init_attr->xrcd)->pd;
1003 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1004 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1005 /* fall through */
1006 case IB_QPT_XRC_INI:
1007 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1008 return ERR_PTR(-ENOSYS);
1009 init_attr->recv_cq = init_attr->send_cq;
1010 /* fall through */
225c7b1f
RD		 1011 case IB_QPT_RC:
1012 case IB_QPT_UC:
3987a2d3 1013 case IB_QPT_RAW_PACKET:
f507d28b 1014 qp = kzalloc(sizeof *qp, GFP_KERNEL);
225c7b1f
RD		 1015 if (!qp)
1016 return ERR_PTR(-ENOMEM);
1ffeb2eb
JM		 1017 /* fall through */
1018 case IB_QPT_UD:
1019 {
1020 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1021 udata, 0, &qp);
1022 if (err)
225c7b1f 1023 return ERR_PTR(err);
225c7b1f
RD		 1024
1025 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1026 qp->xrcdn = xrcdn;
225c7b1f
RD		 1027
1028 break;
1029 }
1030 case IB_QPT_SMI:
1031 case IB_QPT_GSI:
1032 {
1033 /* Userspace is not allowed to create special QPs: */
0a1405da 1034 if (udata)
225c7b1f
RD		 1035 return ERR_PTR(-EINVAL);
1036
0a1405da 1037 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
47605df9 1038 get_sqp_num(to_mdev(pd->device), init_attr),
1ffeb2eb
JM		 1039 &qp);
1040 if (err)
225c7b1f 1041 return ERR_PTR(err);
225c7b1f
RD		 1042
1043 qp->port = init_attr->port_num;
1044 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1045
1046 break;
1047 }
1048 default:
1049 /* Don't support raw QPs */
1050 return ERR_PTR(-EINVAL);
1051 }
1052
1053 return &qp->ibqp;
1054}
1055
1056int mlx4_ib_destroy_qp(struct ib_qp *qp)
1057{
1058 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1059 struct mlx4_ib_qp *mqp = to_mqp(qp);
0a1405da 1060 struct mlx4_ib_pd *pd;
225c7b1f
RD		 1061
1062 if (is_qp0(dev, mqp))
1063 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1064
0a1405da
SH		 1065 pd = get_pd(mqp);
1066 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
225c7b1f
RD		 1067
1068 if (is_sqp(dev, mqp))
1069 kfree(to_msqp(mqp));
1070 else
1071 kfree(mqp);
1072
1073 return 0;
1074}
1075
1ffeb2eb 1076static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1077{
1078 switch (type) {
1ffeb2eb
JM		 1079 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1080 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1081 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1082 case MLX4_IB_QPT_XRC_INI:
1083 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1084 case MLX4_IB_QPT_SMI:
1085 case MLX4_IB_QPT_GSI:
1086 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1087
1088 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1089 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1090 MLX4_QP_ST_MLX : -1);
1091 case MLX4_IB_QPT_PROXY_SMI:
1092 case MLX4_IB_QPT_TUN_SMI:
1093 case MLX4_IB_QPT_PROXY_GSI:
1094 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1095 MLX4_QP_ST_UD : -1);
1096 default: return -1;
225c7b1f
RD		 1097 }
1098}
1099
65adfa91 1100static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1101 int attr_mask)
1102{
1103 u8 dest_rd_atomic;
1104 u32 access_flags;
1105 u32 hw_access_flags = 0;
1106
1107 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1108 dest_rd_atomic = attr->max_dest_rd_atomic;
1109 else
1110 dest_rd_atomic = qp->resp_depth;
1111
1112 if (attr_mask & IB_QP_ACCESS_FLAGS)
1113 access_flags = attr->qp_access_flags;
1114 else
1115 access_flags = qp->atomic_rd_en;
1116
1117 if (!dest_rd_atomic)
1118 access_flags &= IB_ACCESS_REMOTE_WRITE;
1119
1120 if (access_flags & IB_ACCESS_REMOTE_READ)
1121 hw_access_flags |= MLX4_QP_BIT_RRE;
1122 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1123 hw_access_flags |= MLX4_QP_BIT_RAE;
1124 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1125 hw_access_flags |= MLX4_QP_BIT_RWE;
1126
1127 return cpu_to_be32(hw_access_flags);
1128}
1129
65adfa91 1130static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1131 int attr_mask)
1132{
1133 if (attr_mask & IB_QP_PKEY_INDEX)
1134 sqp->pkey_index = attr->pkey_index;
1135 if (attr_mask & IB_QP_QKEY)
1136 sqp->qkey = attr->qkey;
1137 if (attr_mask & IB_QP_SQ_PSN)
1138 sqp->send_psn = attr->sq_psn;
1139}
1140
1141static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1142{
1143 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1144}
1145
65adfa91 1146static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
225c7b1f
RD		 1147 struct mlx4_qp_path *path, u8 port)
1148{
fa417f7b
EC		 1149 int err;
1150 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1151 IB_LINK_LAYER_ETHERNET;
1152 u8 mac[6];
1153 int is_mcast;
4c3eb3ca
EC		 1154 u16 vlan_tag;
1155 int vidx;
fa417f7b 1156
225c7b1f
RD		 1157 path->grh_mylmc = ah->src_path_bits & 0x7f;
1158 path->rlid = cpu_to_be16(ah->dlid);
1159 if (ah->static_rate) {
1160 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1161 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1162 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1163 --path->static_rate;
1164 } else
1165 path->static_rate = 0;
225c7b1f
RD		 1166
1167 if (ah->ah_flags & IB_AH_GRH) {
5ae2a7a8 1168 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1169 pr_err("sgid_index (%u) too large. max is %d\n",
5ae2a7a8 1170 ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1171 return -1;
1172 }
1173
1174 path->grh_mylmc |= 1 << 7;
1175 path->mgid_index = ah->grh.sgid_index;
1176 path->hop_limit = ah->grh.hop_limit;
1177 path->tclass_flowlabel =
1178 cpu_to_be32((ah->grh.traffic_class << 20) |
1179 (ah->grh.flow_label));
1180 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1181 }
1182
fa417f7b 1183 if (is_eth) {
4c3eb3ca 1184 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
9106c410 1185 ((port - 1) << 6) | ((ah->sl & 7) << 3);
4c3eb3ca 1186
fa417f7b
EC		 1187 if (!(ah->ah_flags & IB_AH_GRH))
1188 return -1;
1189
1190 err = mlx4_ib_resolve_grh(dev, ah, mac, &is_mcast, port);
1191 if (err)
1192 return err;
1193
1194 memcpy(path->dmac, mac, 6);
1195 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1196 /* use index 0 into MAC table for IBoE */
1197 path->grh_mylmc &= 0x80;
4c3eb3ca
EC		 1198
1199 vlan_tag = rdma_get_vlan_id(&dev->iboe.gid_table[port - 1][ah->grh.sgid_index]);
1200 if (vlan_tag < 0x1000) {
1201 if (mlx4_find_cached_vlan(dev->dev, port, vlan_tag, &vidx))
1202 return -ENOENT;
1203
1204 path->vlan_index = vidx;
1205 path->fl = 1 << 6;
1206 }
1207 } else
1208 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1209 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
fa417f7b 1210
225c7b1f
RD		 1211 return 0;
1212}
1213
fa417f7b
EC		 1214static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1215{
1216 struct mlx4_ib_gid_entry *ge, *tmp;
1217
1218 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1219 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1220 ge->added = 1;
1221 ge->port = qp->port;
1222 }
1223 }
1224}
1225
65adfa91
MT		 1226static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1227 const struct ib_qp_attr *attr, int attr_mask,
1228 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 1229{
1230 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1231 struct mlx4_ib_qp *qp = to_mqp(ibqp);
0a1405da
SH		 1232 struct mlx4_ib_pd *pd;
1233 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 1234 struct mlx4_qp_context *context;
1235 enum mlx4_qp_optpar optpar = 0;
225c7b1f
RD		 1236 int sqd_event;
1237 int err = -EINVAL;
1238
1239 context = kzalloc(sizeof *context, GFP_KERNEL);
1240 if (!context)
1241 return -ENOMEM;
1242
225c7b1f 1243 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 1244 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 1245
1246 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1247 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1248 else {
1249 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1250 switch (attr->path_mig_state) {
1251 case IB_MIG_MIGRATED:
1252 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1253 break;
1254 case IB_MIG_REARM:
1255 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1256 break;
1257 case IB_MIG_ARMED:
1258 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1259 break;
1260 }
1261 }
1262
b832be1e 1263 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 1264 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
3987a2d3
OG		 1265 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1266 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
b832be1e
EC		 1267 else if (ibqp->qp_type == IB_QPT_UD) {
1268 if (qp->flags & MLX4_IB_QP_LSO)
1269 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1270 ilog2(dev->dev->caps.max_gso_sz);
1271 else
6e0d733d 1272 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 1273 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 1274 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 1275 pr_err("path MTU (%u) is invalid\n",
225c7b1f 1276 attr->path_mtu);
f5b40431 1277 goto out;
225c7b1f 1278 }
d1f2cd89
EC		 1279 context->mtu_msgmax = (attr->path_mtu << 5) |
1280 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 1281 }
1282
0e6e7416
RD		 1283 if (qp->rq.wqe_cnt)
1284 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 1285 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1286
0e6e7416
RD		 1287 if (qp->sq.wqe_cnt)
1288 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 1289 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1290
0a1405da 1291 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 1292 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da
SH		 1293 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1294 }
0e6e7416 1295
225c7b1f
RD		 1296 if (qp->ibqp.uobject)
1297 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1298 else
1299 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1300
1301 if (attr_mask & IB_QP_DEST_QPN)
1302 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1303
1304 if (attr_mask & IB_QP_PORT) {
1305 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1306 !(attr_mask & IB_QP_AV)) {
1307 mlx4_set_sched(&context->pri_path, attr->port_num);
1308 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1309 }
1310 }
1311
cfcde11c
OG		 1312 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1313 if (dev->counters[qp->port - 1] != -1) {
1314 context->pri_path.counter_index =
1315 dev->counters[qp->port - 1];
1316 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1317 } else
1318 context->pri_path.counter_index = 0xff;
1319 }
1320
225c7b1f 1321 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 1322 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1323 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 1324 context->pri_path.pkey_index = attr->pkey_index;
1325 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1326 }
1327
225c7b1f
RD		 1328 if (attr_mask & IB_QP_AV) {
1329 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
1ffeb2eb
JM		 1330 attr_mask & IB_QP_PORT ?
1331 attr->port_num : qp->port))
225c7b1f 1332 goto out;
225c7b1f
RD		 1333
1334 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1335 MLX4_QP_OPTPAR_SCHED_QUEUE);
1336 }
1337
1338 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 1339 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 1340 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1341 }
1342
1343 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 1344 if (attr->alt_port_num == 0 ||
1345 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 1346 goto out;
225c7b1f 1347
5ae2a7a8
RD		 1348 if (attr->alt_pkey_index >=
1349 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 1350 goto out;
5ae2a7a8 1351
225c7b1f
RD		 1352 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1353 attr->alt_port_num))
f5b40431 1354 goto out;
225c7b1f
RD		 1355
1356 context->alt_path.pkey_index = attr->alt_pkey_index;
1357 context->alt_path.ackto = attr->alt_timeout << 3;
1358 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1359 }
1360
0a1405da
SH		 1361 pd = get_pd(qp);
1362 get_cqs(qp, &send_cq, &recv_cq);
1363 context->pd = cpu_to_be32(pd->pdn);
1364 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1365 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1366 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 1367
95d04f07
RD		 1368 /* Set "fast registration enabled" for all kernel QPs */
1369 if (!qp->ibqp.uobject)
1370 context->params1 |= cpu_to_be32(1 << 11);
1371
57f01b53
JM		 1372 if (attr_mask & IB_QP_RNR_RETRY) {
1373 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1374 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1375 }
1376
225c7b1f
RD		 1377 if (attr_mask & IB_QP_RETRY_CNT) {
1378 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1379 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1380 }
1381
1382 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1383 if (attr->max_rd_atomic)
1384 context->params1 |=
1385 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1386 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1387 }
1388
1389 if (attr_mask & IB_QP_SQ_PSN)
1390 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1391
225c7b1f
RD		 1392 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1393 if (attr->max_dest_rd_atomic)
1394 context->params2 |=
1395 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1396 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1397 }
1398
1399 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1400 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1401 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1402 }
1403
1404 if (ibqp->srq)
1405 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1406
1407 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1408 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1409 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1410 }
1411 if (attr_mask & IB_QP_RQ_PSN)
1412 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1413
1ffeb2eb 1414 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 1415 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 1416 if (qp->mlx4_ib_qp_type &
1417 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1418 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1419 else {
1420 if (mlx4_is_mfunc(dev->dev) &&
1421 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1422 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1423 MLX4_RESERVED_QKEY_BASE) {
1424 pr_err("Cannot use reserved QKEY"
1425 " 0x%x (range 0xffff0000..0xffffffff"
1426 " is reserved)\n", attr->qkey);
1427 err = -EINVAL;
1428 goto out;
1429 }
1430 context->qkey = cpu_to_be32(attr->qkey);
1431 }
225c7b1f
RD		 1432 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1433 }
1434
1435 if (ibqp->srq)
1436 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1437
0a1405da 1438 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1439 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1440
1441 if (cur_state == IB_QPS_INIT &&
1442 new_state == IB_QPS_RTR &&
1443 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
3987a2d3
OG		 1444 ibqp->qp_type == IB_QPT_UD ||
1445 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 1446 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 1447 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1448 qp->mlx4_ib_qp_type &
1449 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 1450 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 1451 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1452 context->pri_path.fl = 0x80;
1453 } else {
1454 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1455 context->pri_path.fl = 0x80;
225c7b1f 1456 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 1457 }
225c7b1f
RD		 1458 }
1459
1460 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1461 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1462 sqd_event = 1;
1463 else
1464 sqd_event = 0;
1465
d57f5f72
VS		 1466 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1467 context->rlkey |= (1 << 4);
1468
c0be5fb5
EC		 1469 /*
1470 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1471 * ownership bits of the send queue are set and the SQ
1472 * headroom is stamped so that the hardware doesn't start
1473 * processing stale work requests.
c0be5fb5
EC		 1474 */
1475 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1476 struct mlx4_wqe_ctrl_seg *ctrl;
1477 int i;
1478
0e6e7416 1479 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1480 ctrl = get_send_wqe(qp, i);
1481 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553
EC		 1482 if (qp->sq_max_wqes_per_wr == 1)
1483 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
0e6e7416 1484
ea54b10c 1485 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 1486 }
1487 }
1488
225c7b1f
RD		 1489 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1490 to_mlx4_state(new_state), context, optpar,
1491 sqd_event, &qp->mqp);
1492 if (err)
1493 goto out;
1494
1495 qp->state = new_state;
1496
1497 if (attr_mask & IB_QP_ACCESS_FLAGS)
1498 qp->atomic_rd_en = attr->qp_access_flags;
1499 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1500 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 1501 if (attr_mask & IB_QP_PORT) {
225c7b1f 1502 qp->port = attr->port_num;
fa417f7b
EC		 1503 update_mcg_macs(dev, qp);
1504 }
225c7b1f
RD		 1505 if (attr_mask & IB_QP_ALT_PATH)
1506 qp->alt_port = attr->alt_port_num;
1507
1508 if (is_sqp(dev, qp))
1509 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1510
1511 /*
1512 * If we moved QP0 to RTR, bring the IB link up; if we moved
1513 * QP0 to RESET or ERROR, bring the link back down.
1514 */
1515 if (is_qp0(dev, qp)) {
1516 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 1517 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 1518 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 1519 qp->port);
225c7b1f
RD		 1520
1521 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1522 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1523 mlx4_CLOSE_PORT(dev->dev, qp->port);
1524 }
1525
1526 /*
1527 * If we moved a kernel QP to RESET, clean up all old CQ
1528 * entries and reinitialize the QP.
1529 */
1530 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
0a1405da 1531 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
225c7b1f 1532 ibqp->srq ? to_msrq(ibqp->srq): NULL);
0a1405da
SH		 1533 if (send_cq != recv_cq)
1534 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
225c7b1f
RD		 1535
1536 qp->rq.head = 0;
1537 qp->rq.tail = 0;
1538 qp->sq.head = 0;
1539 qp->sq.tail = 0;
ea54b10c 1540 qp->sq_next_wqe = 0;
0a1405da 1541 if (qp->rq.wqe_cnt)
02d89b87 1542 *qp->db.db = 0;
225c7b1f
RD		 1543 }
1544
1545out:
225c7b1f
RD		 1546 kfree(context);
1547 return err;
1548}
1549
65adfa91
MT		 1550int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1551 int attr_mask, struct ib_udata *udata)
1552{
1553 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1554 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1555 enum ib_qp_state cur_state, new_state;
1556 int err = -EINVAL;
1557
1558 mutex_lock(&qp->mutex);
1559
1560 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1561 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1562
b1d8eb5a
JM		 1563 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
1564 pr_debug("qpn 0x%x: invalid attribute mask specified "
1565 "for transition %d to %d. qp_type %d,"
1566 " attr_mask 0x%x\n",
1567 ibqp->qp_num, cur_state, new_state,
1568 ibqp->qp_type, attr_mask);
65adfa91 1569 goto out;
b1d8eb5a 1570 }
65adfa91 1571
65adfa91 1572 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 1573 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 1574 pr_debug("qpn 0x%x: invalid port number (%d) specified "
1575 "for transition %d to %d. qp_type %d\n",
1576 ibqp->qp_num, attr->port_num, cur_state,
1577 new_state, ibqp->qp_type);
65adfa91
MT		 1578 goto out;
1579 }
1580
3987a2d3
OG		 1581 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1582 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1583 IB_LINK_LAYER_ETHERNET))
1584 goto out;
1585
5ae2a7a8
RD		 1586 if (attr_mask & IB_QP_PKEY_INDEX) {
1587 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 1588 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
1589 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
1590 "for transition %d to %d. qp_type %d\n",
1591 ibqp->qp_num, attr->pkey_index, cur_state,
1592 new_state, ibqp->qp_type);
5ae2a7a8 1593 goto out;
b1d8eb5a 1594 }
5ae2a7a8
RD		 1595 }
1596
65adfa91
MT		 1597 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1598 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 1599 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
1600 "Transition %d to %d. qp_type %d\n",
1601 ibqp->qp_num, attr->max_rd_atomic, cur_state,
1602 new_state, ibqp->qp_type);
65adfa91
MT		 1603 goto out;
1604 }
1605
1606 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1607 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 1608 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
1609 "Transition %d to %d. qp_type %d\n",
1610 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
1611 new_state, ibqp->qp_type);
65adfa91
MT		 1612 goto out;
1613 }
1614
1615 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1616 err = 0;
1617 goto out;
1618 }
1619
65adfa91
MT		 1620 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1621
1622out:
1623 mutex_unlock(&qp->mutex);
1624 return err;
1625}
1626
1ffeb2eb
JM		 1627static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
1628 struct ib_send_wr *wr,
1629 void *wqe, unsigned *mlx_seg_len)
1630{
1631 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
1632 struct ib_device *ib_dev = &mdev->ib_dev;
1633 struct mlx4_wqe_mlx_seg *mlx = wqe;
1634 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1635 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1636 u16 pkey;
1637 u32 qkey;
1638 int send_size;
1639 int header_size;
1640 int spc;
1641 int i;
1642
1643 if (wr->opcode != IB_WR_SEND)
1644 return -EINVAL;
1645
1646 send_size = 0;
1647
1648 for (i = 0; i < wr->num_sge; ++i)
1649 send_size += wr->sg_list[i].length;
1650
1651 /* for proxy-qp0 sends, need to add in size of tunnel header */
1652 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
1653 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
1654 send_size += sizeof (struct mlx4_ib_tunnel_header);
1655
1656 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
1657
1658 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
1659 sqp->ud_header.lrh.service_level =
1660 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
1661 sqp->ud_header.lrh.destination_lid =
1662 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1663 sqp->ud_header.lrh.source_lid =
1664 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1665 }
1666
1667 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1668
1669 /* force loopback */
1670 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
1671 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1672
1673 sqp->ud_header.lrh.virtual_lane = 0;
1674 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1675 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
1676 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1677 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
1678 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1679 else
1680 sqp->ud_header.bth.destination_qpn =
47605df9 1681 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 1682
1683 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1684 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
1685 return -EINVAL;
1686 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
1687 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
1688
1689 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1690 sqp->ud_header.immediate_present = 0;
1691
1692 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1693
1694 /*
1695 * Inline data segments may not cross a 64 byte boundary. If
1696 * our UD header is bigger than the space available up to the
1697 * next 64 byte boundary in the WQE, use two inline data
1698 * segments to hold the UD header.
1699 */
1700 spc = MLX4_INLINE_ALIGN -
1701 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1702 if (header_size <= spc) {
1703 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1704 memcpy(inl + 1, sqp->header_buf, header_size);
1705 i = 1;
1706 } else {
1707 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1708 memcpy(inl + 1, sqp->header_buf, spc);
1709
1710 inl = (void *) (inl + 1) + spc;
1711 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1712 /*
1713 * Need a barrier here to make sure all the data is
1714 * visible before the byte_count field is set.
1715 * Otherwise the HCA prefetcher could grab the 64-byte
1716 * chunk with this inline segment and get a valid (!=
1717 * 0xffffffff) byte count but stale data, and end up
1718 * generating a packet with bad headers.
1719 *
1720 * The first inline segment's byte_count field doesn't
1721 * need a barrier, because it comes after a
1722 * control/MLX segment and therefore is at an offset
1723 * of 16 mod 64.
1724 */
1725 wmb();
1726 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1727 i = 2;
1728 }
1729
1730 *mlx_seg_len =
1731 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1732 return 0;
1733}
1734
225c7b1f 1735static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
f438000f 1736 void *wqe, unsigned *mlx_seg_len)
225c7b1f 1737{
a478868a 1738 struct ib_device *ib_dev = sqp->qp.ibqp.device;
225c7b1f
RD		 1739 struct mlx4_wqe_mlx_seg *mlx = wqe;
1740 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1741 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
a0675a38 1742 struct net_device *ndev;
4c3eb3ca 1743 union ib_gid sgid;
225c7b1f
RD		 1744 u16 pkey;
1745 int send_size;
1746 int header_size;
e61ef241 1747 int spc;
225c7b1f 1748 int i;
fa417f7b 1749 int is_eth;
4c3eb3ca 1750 int is_vlan = 0;
fa417f7b 1751 int is_grh;
4c3eb3ca 1752 u16 vlan;
1ffeb2eb 1753 int err = 0;
225c7b1f
RD		 1754
1755 send_size = 0;
1756 for (i = 0; i < wr->num_sge; ++i)
1757 send_size += wr->sg_list[i].length;
1758
fa417f7b
EC		 1759 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
1760 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 1761 if (is_eth) {
1ffeb2eb
JM		 1762 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
1763 /* When multi-function is enabled, the ib_core gid
1764 * indexes don't necessarily match the hw ones, so
1765 * we must use our own cache */
1766 sgid.global.subnet_prefix =
1767 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
1768 subnet_prefix;
1769 sgid.global.interface_id =
1770 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
1771 guid_cache[ah->av.ib.gid_index];
1772 } else {
1773 err = ib_get_cached_gid(ib_dev,
1774 be32_to_cpu(ah->av.ib.port_pd) >> 24,
1775 ah->av.ib.gid_index, &sgid);
1776 if (err)
1777 return err;
1778 }
1779
4c3eb3ca
EC		 1780 vlan = rdma_get_vlan_id(&sgid);
1781 is_vlan = vlan < 0x1000;
1782 }
1783 ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
fa417f7b
EC		 1784
1785 if (!is_eth) {
1786 sqp->ud_header.lrh.service_level =
1787 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
1788 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
1789 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1790 }
225c7b1f 1791
fa417f7b 1792 if (is_grh) {
225c7b1f 1793 sqp->ud_header.grh.traffic_class =
fa417f7b 1794 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 1795 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 1796 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1797 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
1ffeb2eb
JM		 1798 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
1799 /* When multi-function is enabled, the ib_core gid
1800 * indexes don't necessarily match the hw ones, so
1801 * we must use our own cache */
1802 sqp->ud_header.grh.source_gid.global.subnet_prefix =
1803 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
1804 subnet_prefix;
1805 sqp->ud_header.grh.source_gid.global.interface_id =
1806 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
1807 guid_cache[ah->av.ib.gid_index];
1808 } else
1809 ib_get_cached_gid(ib_dev,
1810 be32_to_cpu(ah->av.ib.port_pd) >> 24,
1811 ah->av.ib.gid_index,
1812 &sqp->ud_header.grh.source_gid);
225c7b1f 1813 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 1814 ah->av.ib.dgid, 16);
225c7b1f
RD		 1815 }
1816
1817 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 1818
1819 if (!is_eth) {
1820 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1821 (sqp->ud_header.lrh.destination_lid ==
1822 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1823 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 1824 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
1825 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 1826 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1827 }
225c7b1f
RD		 1828
1829 switch (wr->opcode) {
1830 case IB_WR_SEND:
1831 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1832 sqp->ud_header.immediate_present = 0;
1833 break;
1834 case IB_WR_SEND_WITH_IMM:
1835 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1836 sqp->ud_header.immediate_present = 1;
0f39cf3d 1837 sqp->ud_header.immediate_data = wr->ex.imm_data;
225c7b1f
RD		 1838 break;
1839 default:
1840 return -EINVAL;
1841 }
1842
fa417f7b
EC		 1843 if (is_eth) {
1844 u8 *smac;
c0c1d3d7
OD		 1845 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
1846
1847 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b
EC		 1848
1849 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
1850 /* FIXME: cache smac value? */
a0675a38
KSS		 1851 ndev = to_mdev(sqp->qp.ibqp.device)->iboe.netdevs[sqp->qp.port - 1];
1852 if (!ndev)
1853 return -ENODEV;
1854 smac = ndev->dev_addr;
fa417f7b
EC		 1855 memcpy(sqp->ud_header.eth.smac_h, smac, 6);
1856 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
1857 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca
EC		 1858 if (!is_vlan) {
1859 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
1860 } else {
4c3eb3ca 1861 sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
4c3eb3ca
EC		 1862 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
1863 }
fa417f7b
EC		 1864 } else {
1865 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1866 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1867 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1868 }
225c7b1f
RD		 1869 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1870 if (!sqp->qp.ibqp.qp_num)
1871 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1872 else
1873 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1874 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1875 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1876 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1877 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1878 sqp->qkey : wr->wr.ud.remote_qkey);
1879 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1880
1881 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1882
1883 if (0) {
987c8f8f 1884 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 1885 for (i = 0; i < header_size / 4; ++i) {
1886 if (i % 8 == 0)
987c8f8f
SP		 1887 pr_err(" [%02x] ", i * 4);
1888 pr_cont(" %08x",
1889 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 1890 if ((i + 1) % 8 == 0)
987c8f8f 1891 pr_cont("\n");
225c7b1f 1892 }
987c8f8f 1893 pr_err("\n");
225c7b1f
RD		 1894 }
1895
e61ef241
RD		 1896 /*
1897 * Inline data segments may not cross a 64 byte boundary. If
1898 * our UD header is bigger than the space available up to the
1899 * next 64 byte boundary in the WQE, use two inline data
1900 * segments to hold the UD header.
1901 */
1902 spc = MLX4_INLINE_ALIGN -
1903 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1904 if (header_size <= spc) {
1905 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1906 memcpy(inl + 1, sqp->header_buf, header_size);
1907 i = 1;
1908 } else {
1909 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1910 memcpy(inl + 1, sqp->header_buf, spc);
1911
1912 inl = (void *) (inl + 1) + spc;
1913 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1914 /*
1915 * Need a barrier here to make sure all the data is
1916 * visible before the byte_count field is set.
1917 * Otherwise the HCA prefetcher could grab the 64-byte
1918 * chunk with this inline segment and get a valid (!=
1919 * 0xffffffff) byte count but stale data, and end up
1920 * generating a packet with bad headers.
1921 *
1922 * The first inline segment's byte_count field doesn't
1923 * need a barrier, because it comes after a
1924 * control/MLX segment and therefore is at an offset
1925 * of 16 mod 64.
1926 */
1927 wmb();
1928 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1929 i = 2;
1930 }
225c7b1f 1931
f438000f
RD		 1932 *mlx_seg_len =
1933 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1934 return 0;
225c7b1f
RD		 1935}
1936
1937static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1938{
1939 unsigned cur;
1940 struct mlx4_ib_cq *cq;
1941
1942 cur = wq->head - wq->tail;
0e6e7416 1943 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 1944 return 0;
1945
1946 cq = to_mcq(ib_cq);
1947 spin_lock(&cq->lock);
1948 cur = wq->head - wq->tail;
1949 spin_unlock(&cq->lock);
1950
0e6e7416 1951 return cur + nreq >= wq->max_post;
225c7b1f
RD		 1952}
1953
95d04f07
RD		 1954static __be32 convert_access(int acc)
1955{
1956 return (acc & IB_ACCESS_REMOTE_ATOMIC ? cpu_to_be32(MLX4_WQE_FMR_PERM_ATOMIC) : 0) |
1957 (acc & IB_ACCESS_REMOTE_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_WRITE) : 0) |
1958 (acc & IB_ACCESS_REMOTE_READ ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_READ) : 0) |
1959 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
1960 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
1961}
1962
1963static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
1964{
1965 struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
29bdc883
VS		 1966 int i;
1967
1968 for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2b6b7d4b 1969 mfrpl->mapped_page_list[i] =
29bdc883
VS		 1970 cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
1971 MLX4_MTT_FLAG_PRESENT);
95d04f07
RD		 1972
1973 fseg->flags = convert_access(wr->wr.fast_reg.access_flags);
1974 fseg->mem_key = cpu_to_be32(wr->wr.fast_reg.rkey);
1975 fseg->buf_list = cpu_to_be64(mfrpl->map);
1976 fseg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1977 fseg->reg_len = cpu_to_be64(wr->wr.fast_reg.length);
1978 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
1979 fseg->page_size = cpu_to_be32(wr->wr.fast_reg.page_shift);
1980 fseg->reserved[0] = 0;
1981 fseg->reserved[1] = 0;
1982}
1983
1984static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
1985{
1986 iseg->flags = 0;
1987 iseg->mem_key = cpu_to_be32(rkey);
1988 iseg->guest_id = 0;
1989 iseg->pa = 0;
1990}
1991
0fbfa6a9
RD		 1992static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1993 u64 remote_addr, u32 rkey)
1994{
1995 rseg->raddr = cpu_to_be64(remote_addr);
1996 rseg->rkey = cpu_to_be32(rkey);
1997 rseg->reserved = 0;
1998}
1999
2000static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2001{
2002 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2003 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2004 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
6fa8f719
VS		 2005 } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2006 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2007 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add_mask);
0fbfa6a9
RD		 2008 } else {
2009 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2010 aseg->compare = 0;
2011 }
2012
2013}
2014
6fa8f719
VS		 2015static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2016 struct ib_send_wr *wr)
2017{
2018 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2019 aseg->swap_add_mask = cpu_to_be64(wr->wr.atomic.swap_mask);
2020 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
2021 aseg->compare_mask = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2022}
2023
0fbfa6a9 2024static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
80a2dcd8 2025 struct ib_send_wr *wr)
0fbfa6a9
RD		 2026{
2027 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2028 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2029 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
fa417f7b
EC		 2030 dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2031 memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
0fbfa6a9
RD		 2032}
2033
1ffeb2eb
JM		 2034static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2035 struct mlx4_wqe_datagram_seg *dseg,
2036 struct ib_send_wr *wr, enum ib_qp_type qpt)
2037{
2038 union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2039 struct mlx4_av sqp_av = {0};
2040 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2041
2042 /* force loopback */
2043 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2044 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2045 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2046 cpu_to_be32(0xf0000000);
2047
2048 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
47605df9
JM		 2049 /* This function used only for sending on QP1 proxies */
2050 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2051 /* Use QKEY from the QP context, which is set by master */
2052 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 2053}
2054
2055static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2056{
2057 struct mlx4_wqe_inline_seg *inl = wqe;
2058 struct mlx4_ib_tunnel_header hdr;
2059 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2060 int spc;
2061 int i;
2062
2063 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2064 hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2065 hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2066 hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2067
2068 spc = MLX4_INLINE_ALIGN -
2069 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2070 if (sizeof (hdr) <= spc) {
2071 memcpy(inl + 1, &hdr, sizeof (hdr));
2072 wmb();
2073 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2074 i = 1;
2075 } else {
2076 memcpy(inl + 1, &hdr, spc);
2077 wmb();
2078 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2079
2080 inl = (void *) (inl + 1) + spc;
2081 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2082 wmb();
2083 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2084 i = 2;
2085 }
2086
2087 *mlx_seg_len =
2088 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2089}
2090
6e694ea3
JM		 2091static void set_mlx_icrc_seg(void *dseg)
2092{
2093 u32 *t = dseg;
2094 struct mlx4_wqe_inline_seg *iseg = dseg;
2095
2096 t[1] = 0;
2097
2098 /*
2099 * Need a barrier here before writing the byte_count field to
2100 * make sure that all the data is visible before the
2101 * byte_count field is set. Otherwise, if the segment begins
2102 * a new cacheline, the HCA prefetcher could grab the 64-byte
2103 * chunk and get a valid (!= * 0xffffffff) byte count but
2104 * stale data, and end up sending the wrong data.
2105 */
2106 wmb();
2107
2108 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2109}
2110
2111static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 2112{
d420d9e3
RD		 2113 dseg->lkey = cpu_to_be32(sg->lkey);
2114 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 2115
2116 /*
2117 * Need a barrier here before writing the byte_count field to
2118 * make sure that all the data is visible before the
2119 * byte_count field is set. Otherwise, if the segment begins
2120 * a new cacheline, the HCA prefetcher could grab the 64-byte
2121 * chunk and get a valid (!= * 0xffffffff) byte count but
2122 * stale data, and end up sending the wrong data.
2123 */
2124 wmb();
2125
2126 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 2127}
2128
2242fa4f
RD		 2129static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2130{
2131 dseg->byte_count = cpu_to_be32(sg->length);
2132 dseg->lkey = cpu_to_be32(sg->lkey);
2133 dseg->addr = cpu_to_be64(sg->addr);
2134}
2135
47b37475 2136static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
0fd7e1d8 2137 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 2138 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e
EC		 2139{
2140 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2141
417608c2
EC		 2142 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2143 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 2144
2145 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2146 wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2147 return -EINVAL;
2148
2149 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2150
0fd7e1d8
RD		 2151 *lso_hdr_sz = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
2152 wr->wr.ud.hlen);
b832be1e
EC		 2153 *lso_seg_len = halign;
2154 return 0;
2155}
2156
95d04f07
RD		 2157static __be32 send_ieth(struct ib_send_wr *wr)
2158{
2159 switch (wr->opcode) {
2160 case IB_WR_SEND_WITH_IMM:
2161 case IB_WR_RDMA_WRITE_WITH_IMM:
2162 return wr->ex.imm_data;
2163
2164 case IB_WR_SEND_WITH_INV:
2165 return cpu_to_be32(wr->ex.invalidate_rkey);
2166
2167 default:
2168 return 0;
2169 }
2170}
2171
1ffeb2eb
JM		 2172static void add_zero_len_inline(void *wqe)
2173{
2174 struct mlx4_wqe_inline_seg *inl = wqe;
2175 memset(wqe, 0, 16);
2176 inl->byte_count = cpu_to_be32(1 << 31);
2177}
2178
225c7b1f
RD		 2179int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2180 struct ib_send_wr **bad_wr)
2181{
2182 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2183 void *wqe;
2184 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 2185 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 2186 unsigned long flags;
2187 int nreq;
2188 int err = 0;
ea54b10c
JM		 2189 unsigned ind;
2190 int uninitialized_var(stamp);
2191 int uninitialized_var(size);
a3d8e159 2192 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 2193 __be32 dummy;
2194 __be32 *lso_wqe;
2195 __be32 uninitialized_var(lso_hdr_sz);
417608c2 2196 __be32 blh;
225c7b1f
RD		 2197 int i;
2198
96db0e03 2199 spin_lock_irqsave(&qp->sq.lock, flags);
225c7b1f 2200
ea54b10c 2201 ind = qp->sq_next_wqe;
225c7b1f
RD		 2202
2203 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 2204 lso_wqe = &dummy;
417608c2 2205 blh = 0;
0fd7e1d8 2206
225c7b1f
RD		 2207 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2208 err = -ENOMEM;
2209 *bad_wr = wr;
2210 goto out;
2211 }
2212
2213 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2214 err = -EINVAL;
2215 *bad_wr = wr;
2216 goto out;
2217 }
2218
0e6e7416 2219 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 2220 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 2221
2222 ctrl->srcrb_flags =
2223 (wr->send_flags & IB_SEND_SIGNALED ?
2224 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2225 (wr->send_flags & IB_SEND_SOLICITED ?
2226 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 2227 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2228 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2229 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 2230 qp->sq_signal_bits;
2231
95d04f07 2232 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 2233
2234 wqe += sizeof *ctrl;
2235 size = sizeof *ctrl / 16;
2236
1ffeb2eb
JM		 2237 switch (qp->mlx4_ib_qp_type) {
2238 case MLX4_IB_QPT_RC:
2239 case MLX4_IB_QPT_UC:
225c7b1f
RD		 2240 switch (wr->opcode) {
2241 case IB_WR_ATOMIC_CMP_AND_SWP:
2242 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 2243 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
0fbfa6a9
RD		 2244 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2245 wr->wr.atomic.rkey);
225c7b1f
RD		 2246 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2247
0fbfa6a9 2248 set_atomic_seg(wqe, wr);
225c7b1f 2249 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 2250
225c7b1f
RD		 2251 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2252 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 2253
2254 break;
2255
2256 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2257 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2258 wr->wr.atomic.rkey);
2259 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2260
2261 set_masked_atomic_seg(wqe, wr);
2262 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
2263
2264 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2265 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 2266
2267 break;
2268
2269 case IB_WR_RDMA_READ:
2270 case IB_WR_RDMA_WRITE:
2271 case IB_WR_RDMA_WRITE_WITH_IMM:
0fbfa6a9
RD		 2272 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2273 wr->wr.rdma.rkey);
225c7b1f
RD		 2274 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2275 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 2276 break;
95d04f07
RD		 2277
2278 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 2279 ctrl->srcrb_flags |=
2280 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2281 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2282 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
2283 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2284 break;
2285
2286 case IB_WR_FAST_REG_MR:
2ac6bf4d
JM		 2287 ctrl->srcrb_flags |=
2288 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2289 set_fmr_seg(wqe, wr);
2290 wqe += sizeof (struct mlx4_wqe_fmr_seg);
2291 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2292 break;
225c7b1f
RD		 2293
2294 default:
2295 /* No extra segments required for sends */
2296 break;
2297 }
2298 break;
2299
1ffeb2eb
JM		 2300 case MLX4_IB_QPT_TUN_SMI_OWNER:
2301 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2302 if (unlikely(err)) {
2303 *bad_wr = wr;
2304 goto out;
2305 }
2306 wqe += seglen;
2307 size += seglen / 16;
2308 break;
2309 case MLX4_IB_QPT_TUN_SMI:
2310 case MLX4_IB_QPT_TUN_GSI:
2311 /* this is a UD qp used in MAD responses to slaves. */
2312 set_datagram_seg(wqe, wr);
2313 /* set the forced-loopback bit in the data seg av */
2314 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2315 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2316 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2317 break;
2318 case MLX4_IB_QPT_UD:
80a2dcd8 2319 set_datagram_seg(wqe, wr);
225c7b1f
RD		 2320 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2321 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 2322
2323 if (wr->opcode == IB_WR_LSO) {
417608c2 2324 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
b832be1e
EC		 2325 if (unlikely(err)) {
2326 *bad_wr = wr;
2327 goto out;
2328 }
0fd7e1d8 2329 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 2330 wqe += seglen;
2331 size += seglen / 16;
2332 }
225c7b1f
RD		 2333 break;
2334
1ffeb2eb
JM		 2335 case MLX4_IB_QPT_PROXY_SMI_OWNER:
2336 if (unlikely(!mlx4_is_master(to_mdev(ibqp->device)->dev))) {
2337 err = -ENOSYS;
2338 *bad_wr = wr;
2339 goto out;
2340 }
2341 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2342 if (unlikely(err)) {
2343 *bad_wr = wr;
2344 goto out;
2345 }
2346 wqe += seglen;
2347 size += seglen / 16;
2348 /* to start tunnel header on a cache-line boundary */
2349 add_zero_len_inline(wqe);
2350 wqe += 16;
2351 size++;
2352 build_tunnel_header(wr, wqe, &seglen);
2353 wqe += seglen;
2354 size += seglen / 16;
2355 break;
2356 case MLX4_IB_QPT_PROXY_SMI:
2357 /* don't allow QP0 sends on guests */
2358 err = -ENOSYS;
2359 *bad_wr = wr;
2360 goto out;
2361 case MLX4_IB_QPT_PROXY_GSI:
2362 /* If we are tunneling special qps, this is a UD qp.
2363 * In this case we first add a UD segment targeting
2364 * the tunnel qp, and then add a header with address
2365 * information */
2366 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr, ibqp->qp_type);
2367 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2368 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2369 build_tunnel_header(wr, wqe, &seglen);
2370 wqe += seglen;
2371 size += seglen / 16;
2372 break;
2373
2374 case MLX4_IB_QPT_SMI:
2375 case MLX4_IB_QPT_GSI:
f438000f
RD		 2376 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2377 if (unlikely(err)) {
225c7b1f
RD		 2378 *bad_wr = wr;
2379 goto out;
2380 }
f438000f
RD		 2381 wqe += seglen;
2382 size += seglen / 16;
225c7b1f
RD		 2383 break;
2384
2385 default:
2386 break;
2387 }
2388
6e694ea3
JM		 2389 /*
2390 * Write data segments in reverse order, so as to
2391 * overwrite cacheline stamp last within each
2392 * cacheline. This avoids issues with WQE
2393 * prefetching.
2394 */
225c7b1f 2395
6e694ea3
JM		 2396 dseg = wqe;
2397 dseg += wr->num_sge - 1;
2398 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 2399
2400 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 2401 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2402 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2403 qp->mlx4_ib_qp_type &
2404 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 2405 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 2406 size += sizeof (struct mlx4_wqe_data_seg) / 16;
2407 }
2408
6e694ea3
JM		 2409 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2410 set_data_seg(dseg, wr->sg_list + i);
2411
0fd7e1d8
RD		 2412 /*
2413 * Possibly overwrite stamping in cacheline with LSO
2414 * segment only after making sure all data segments
2415 * are written.
2416 */
2417 wmb();
2418 *lso_wqe = lso_hdr_sz;
2419
225c7b1f
RD		 2420 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2421 MLX4_WQE_CTRL_FENCE : 0) | size;
2422
2423 /*
2424 * Make sure descriptor is fully written before
2425 * setting ownership bit (because HW can start
2426 * executing as soon as we do).
2427 */
2428 wmb();
2429
59b0ed12 2430 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 2431 *bad_wr = wr;
225c7b1f
RD		 2432 err = -EINVAL;
2433 goto out;
2434 }
2435
2436 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 2437 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 2438
ea54b10c
JM		 2439 stamp = ind + qp->sq_spare_wqes;
2440 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2441
0e6e7416
RD		 2442 /*
2443 * We can improve latency by not stamping the last
2444 * send queue WQE until after ringing the doorbell, so
2445 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 2446 *
2447 * Same optimization applies to padding with NOP wqe
2448 * in case of WQE shrinking (used to prevent wrap-around
2449 * in the middle of WR).
0e6e7416 2450 */
ea54b10c
JM		 2451 if (wr->next) {
2452 stamp_send_wqe(qp, stamp, size * 16);
2453 ind = pad_wraparound(qp, ind);
2454 }
225c7b1f
RD		 2455 }
2456
2457out:
2458 if (likely(nreq)) {
2459 qp->sq.head += nreq;
2460
2461 /*
2462 * Make sure that descriptors are written before
2463 * doorbell record.
2464 */
2465 wmb();
2466
2467 writel(qp->doorbell_qpn,
2468 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
2469
2470 /*
2471 * Make sure doorbells don't leak out of SQ spinlock
2472 * and reach the HCA out of order.
2473 */
2474 mmiowb();
0e6e7416 2475
ea54b10c
JM		 2476 stamp_send_wqe(qp, stamp, size * 16);
2477
2478 ind = pad_wraparound(qp, ind);
2479 qp->sq_next_wqe = ind;
225c7b1f
RD		 2480 }
2481
96db0e03 2482 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 2483
2484 return err;
2485}
2486
2487int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2488 struct ib_recv_wr **bad_wr)
2489{
2490 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2491 struct mlx4_wqe_data_seg *scat;
2492 unsigned long flags;
2493 int err = 0;
2494 int nreq;
2495 int ind;
1ffeb2eb 2496 int max_gs;
225c7b1f
RD		 2497 int i;
2498
1ffeb2eb 2499 max_gs = qp->rq.max_gs;
225c7b1f
RD		 2500 spin_lock_irqsave(&qp->rq.lock, flags);
2501
0e6e7416 2502 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 2503
2504 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 2505 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 2506 err = -ENOMEM;
2507 *bad_wr = wr;
2508 goto out;
2509 }
2510
2511 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2512 err = -EINVAL;
2513 *bad_wr = wr;
2514 goto out;
2515 }
2516
2517 scat = get_recv_wqe(qp, ind);
2518
1ffeb2eb
JM		 2519 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
2520 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
2521 ib_dma_sync_single_for_device(ibqp->device,
2522 qp->sqp_proxy_rcv[ind].map,
2523 sizeof (struct mlx4_ib_proxy_sqp_hdr),
2524 DMA_FROM_DEVICE);
2525 scat->byte_count =
2526 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
2527 /* use dma lkey from upper layer entry */
2528 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
2529 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
2530 scat++;
2531 max_gs--;
2532 }
2533
2242fa4f
RD		 2534 for (i = 0; i < wr->num_sge; ++i)
2535 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 2536
1ffeb2eb 2537 if (i < max_gs) {
225c7b1f
RD		 2538 scat[i].byte_count = 0;
2539 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
2540 scat[i].addr = 0;
2541 }
2542
2543 qp->rq.wrid[ind] = wr->wr_id;
2544
0e6e7416 2545 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 2546 }
2547
2548out:
2549 if (likely(nreq)) {
2550 qp->rq.head += nreq;
2551
2552 /*
2553 * Make sure that descriptors are written before
2554 * doorbell record.
2555 */
2556 wmb();
2557
2558 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2559 }
2560
2561 spin_unlock_irqrestore(&qp->rq.lock, flags);
2562
2563 return err;
2564}
6a775e2b
JM		 2565
2566static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
2567{
2568 switch (mlx4_state) {
2569 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
2570 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
2571 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
2572 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
2573 case MLX4_QP_STATE_SQ_DRAINING:
2574 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
2575 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
2576 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
2577 default: return -1;
2578 }
2579}
2580
2581static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
2582{
2583 switch (mlx4_mig_state) {
2584 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
2585 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
2586 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
2587 default: return -1;
2588 }
2589}
2590
2591static int to_ib_qp_access_flags(int mlx4_flags)
2592{
2593 int ib_flags = 0;
2594
2595 if (mlx4_flags & MLX4_QP_BIT_RRE)
2596 ib_flags |= IB_ACCESS_REMOTE_READ;
2597 if (mlx4_flags & MLX4_QP_BIT_RWE)
2598 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2599 if (mlx4_flags & MLX4_QP_BIT_RAE)
2600 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2601
2602 return ib_flags;
2603}
2604
4c3eb3ca 2605static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
6a775e2b
JM		 2606 struct mlx4_qp_path *path)
2607{
4c3eb3ca
EC		 2608 struct mlx4_dev *dev = ibdev->dev;
2609 int is_eth;
2610
8fcea95a 2611 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 2612 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
2613
2614 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
2615 return;
2616
4c3eb3ca
EC		 2617 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
2618 IB_LINK_LAYER_ETHERNET;
2619 if (is_eth)
2620 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
2621 ((path->sched_queue & 4) << 1);
2622 else
2623 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
2624
6a775e2b 2625 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
6a775e2b
JM		 2626 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
2627 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
2628 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
2629 if (ib_ah_attr->ah_flags) {
2630 ib_ah_attr->grh.sgid_index = path->mgid_index;
2631 ib_ah_attr->grh.hop_limit = path->hop_limit;
2632 ib_ah_attr->grh.traffic_class =
2633 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2634 ib_ah_attr->grh.flow_label =
586bb586 2635 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 2636 memcpy(ib_ah_attr->grh.dgid.raw,
2637 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
2638 }
2639}
2640
2641int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2642 struct ib_qp_init_attr *qp_init_attr)
2643{
2644 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2645 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2646 struct mlx4_qp_context context;
2647 int mlx4_state;
0df67030
DB		 2648 int err = 0;
2649
2650 mutex_lock(&qp->mutex);
6a775e2b
JM		 2651
2652 if (qp->state == IB_QPS_RESET) {
2653 qp_attr->qp_state = IB_QPS_RESET;
2654 goto done;
2655 }
2656
2657 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 2658 if (err) {
2659 err = -EINVAL;
2660 goto out;
2661 }
6a775e2b
JM		 2662
2663 mlx4_state = be32_to_cpu(context.flags) >> 28;
2664
0df67030
DB		 2665 qp->state = to_ib_qp_state(mlx4_state);
2666 qp_attr->qp_state = qp->state;
6a775e2b
JM		 2667 qp_attr->path_mtu = context.mtu_msgmax >> 5;
2668 qp_attr->path_mig_state =
2669 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
2670 qp_attr->qkey = be32_to_cpu(context.qkey);
2671 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
2672 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
2673 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
2674 qp_attr->qp_access_flags =
2675 to_ib_qp_access_flags(be32_to_cpu(context.params2));
2676
2677 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4c3eb3ca
EC		 2678 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
2679 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b
JM		 2680 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
2681 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
2682 }
2683
2684 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 2685 if (qp_attr->qp_state == IB_QPS_INIT)
2686 qp_attr->port_num = qp->port;
2687 else
2688 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 2689
2690 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2691 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
2692
2693 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
2694
2695 qp_attr->max_dest_rd_atomic =
2696 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
2697 qp_attr->min_rnr_timer =
2698 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
2699 qp_attr->timeout = context.pri_path.ackto >> 3;
2700 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
2701 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
2702 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
2703
2704done:
2705 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 2706 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
2707 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
2708
6a775e2b 2709 if (!ibqp->uobject) {
7f5eb9bb
RD		 2710 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
2711 qp_attr->cap.max_send_sge = qp->sq.max_gs;
2712 } else {
2713 qp_attr->cap.max_send_wr = 0;
2714 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 2715 }
2716
7f5eb9bb
RD		 2717 /*
2718 * We don't support inline sends for kernel QPs (yet), and we
2719 * don't know what userspace's value should be.
2720 */
2721 qp_attr->cap.max_inline_data = 0;
2722
2723 qp_init_attr->cap = qp_attr->cap;
2724
521e575b
RL		 2725 qp_init_attr->create_flags = 0;
2726 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2727 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
2728
2729 if (qp->flags & MLX4_IB_QP_LSO)
2730 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
2731
46db567d
DB		 2732 qp_init_attr->sq_sig_type =
2733 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
2734 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
2735
0df67030
DB		 2736out:
2737 mutex_unlock(&qp->mutex);
2738 return err;
6a775e2b
JM		 2739}
2740
Linux 6.x block layer and io_uring tree(s)