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IB/mlx4: Fix warning in rounding up queue sizes
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <rdma/ib_cache.h>
34#include <rdma/ib_pack.h>
35
36#include <linux/mlx4/qp.h>
37
38#include "mlx4_ib.h"
39#include "user.h"
40
41enum {
42 MLX4_IB_ACK_REQ_FREQ = 8,
43};
44
45enum {
46 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
47 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
48};
49
50enum {
51 /*
52 * Largest possible UD header: send with GRH and immediate data.
53 */
54 MLX4_IB_UD_HEADER_SIZE = 72
55};
56
57struct mlx4_ib_sqp {
58 struct mlx4_ib_qp qp;
59 int pkey_index;
60 u32 qkey;
61 u32 send_psn;
62 struct ib_ud_header ud_header;
63 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
64};
65
66static const __be32 mlx4_ib_opcode[] = {
67 [IB_WR_SEND] = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
68 [IB_WR_SEND_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
69 [IB_WR_RDMA_WRITE] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
70 [IB_WR_RDMA_WRITE_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
71 [IB_WR_RDMA_READ] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
72 [IB_WR_ATOMIC_CMP_AND_SWP] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
73 [IB_WR_ATOMIC_FETCH_AND_ADD] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
74};
75
76static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
77{
78 return container_of(mqp, struct mlx4_ib_sqp, qp);
79}
80
81static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
82{
83 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
84 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
85}
86
87static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
88{
89 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
90 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
91}
92
93static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
94{
95 if (qp->buf.nbufs == 1)
96 return qp->buf.u.direct.buf + offset;
97 else
98 return qp->buf.u.page_list[offset >> PAGE_SHIFT].buf +
99 (offset & (PAGE_SIZE - 1));
100}
101
102static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
103{
104 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
105}
106
107static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
108{
109 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
110}
111
112static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
113{
114 struct ib_event event;
115 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
116
117 if (type == MLX4_EVENT_TYPE_PATH_MIG)
118 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
119
120 if (ibqp->event_handler) {
121 event.device = ibqp->device;
122 event.element.qp = ibqp;
123 switch (type) {
124 case MLX4_EVENT_TYPE_PATH_MIG:
125 event.event = IB_EVENT_PATH_MIG;
126 break;
127 case MLX4_EVENT_TYPE_COMM_EST:
128 event.event = IB_EVENT_COMM_EST;
129 break;
130 case MLX4_EVENT_TYPE_SQ_DRAINED:
131 event.event = IB_EVENT_SQ_DRAINED;
132 break;
133 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
134 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
135 break;
136 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
137 event.event = IB_EVENT_QP_FATAL;
138 break;
139 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
140 event.event = IB_EVENT_PATH_MIG_ERR;
141 break;
142 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
143 event.event = IB_EVENT_QP_REQ_ERR;
144 break;
145 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
146 event.event = IB_EVENT_QP_ACCESS_ERR;
147 break;
148 default:
149 printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
150 "on QP %06x\n", type, qp->qpn);
151 return;
152 }
153
154 ibqp->event_handler(&event, ibqp->qp_context);
155 }
156}
157
158static int send_wqe_overhead(enum ib_qp_type type)
159{
160 /*
161 * UD WQEs must have a datagram segment.
162 * RC and UC WQEs might have a remote address segment.
163 * MLX WQEs need two extra inline data segments (for the UD
164 * header and space for the ICRC).
165 */
166 switch (type) {
167 case IB_QPT_UD:
168 return sizeof (struct mlx4_wqe_ctrl_seg) +
169 sizeof (struct mlx4_wqe_datagram_seg);
170 case IB_QPT_UC:
171 return sizeof (struct mlx4_wqe_ctrl_seg) +
172 sizeof (struct mlx4_wqe_raddr_seg);
173 case IB_QPT_RC:
174 return sizeof (struct mlx4_wqe_ctrl_seg) +
175 sizeof (struct mlx4_wqe_atomic_seg) +
176 sizeof (struct mlx4_wqe_raddr_seg);
177 case IB_QPT_SMI:
178 case IB_QPT_GSI:
179 return sizeof (struct mlx4_wqe_ctrl_seg) +
180 ALIGN(MLX4_IB_UD_HEADER_SIZE +
181 sizeof (struct mlx4_wqe_inline_seg),
182 sizeof (struct mlx4_wqe_data_seg)) +
183 ALIGN(4 +
184 sizeof (struct mlx4_wqe_inline_seg),
185 sizeof (struct mlx4_wqe_data_seg));
186 default:
187 return sizeof (struct mlx4_wqe_ctrl_seg);
188 }
189}
190
2446304d 191static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
a4cd7ed8 192 int is_user, int has_srq, struct mlx4_ib_qp *qp)
225c7b1f 193{
2446304d
EC		 194 /* Sanity check RQ size before proceeding */
195 if (cap->max_recv_wr > dev->dev->caps.max_wqes ||
196 cap->max_recv_sge > dev->dev->caps.max_rq_sg)
197 return -EINVAL;
198
a4cd7ed8
RD		 199 if (has_srq) {
200 /* QPs attached to an SRQ should have no RQ */
201 if (cap->max_recv_wr)
202 return -EINVAL;
2446304d 203
a4cd7ed8
RD		 204 qp->rq.max = qp->rq.max_gs = 0;
205 } else {
206 /* HW requires >= 1 RQ entry with >= 1 gather entry */
207 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
208 return -EINVAL;
209
42c059ea
RD		 210 qp->rq.max = roundup_pow_of_two(max(1U, cap->max_recv_wr));
211 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 212 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
213 }
2446304d
EC		 214
215 cap->max_recv_wr = qp->rq.max;
216 cap->max_recv_sge = qp->rq.max_gs;
217
218 return 0;
219}
220
221static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
222 enum ib_qp_type type, struct mlx4_ib_qp *qp)
223{
224 /* Sanity check SQ size before proceeding */
225c7b1f 225 if (cap->max_send_wr > dev->dev->caps.max_wqes ||
225c7b1f 226 cap->max_send_sge > dev->dev->caps.max_sq_sg ||
225c7b1f
RD		 227 cap->max_inline_data + send_wqe_overhead(type) +
228 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
229 return -EINVAL;
230
231 /*
232 * For MLX transport we need 2 extra S/G entries:
233 * one for the header and one for the checksum at the end
234 */
235 if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
236 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
237 return -EINVAL;
238
2446304d 239 qp->sq.max = cap->max_send_wr ? roundup_pow_of_two(cap->max_send_wr) : 1;
225c7b1f
RD		 240
241 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(max(cap->max_send_sge *
242 sizeof (struct mlx4_wqe_data_seg),
243 cap->max_inline_data +
244 sizeof (struct mlx4_wqe_inline_seg)) +
245 send_wqe_overhead(type)));
246 qp->sq.max_gs = ((1 << qp->sq.wqe_shift) - send_wqe_overhead(type)) /
247 sizeof (struct mlx4_wqe_data_seg);
248
249 qp->buf_size = (qp->rq.max << qp->rq.wqe_shift) +
250 (qp->sq.max << qp->sq.wqe_shift);
251 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
252 qp->rq.offset = 0;
253 qp->sq.offset = qp->rq.max << qp->rq.wqe_shift;
254 } else {
255 qp->rq.offset = qp->sq.max << qp->sq.wqe_shift;
256 qp->sq.offset = 0;
257 }
258
2446304d
EC		 259 cap->max_send_wr = qp->sq.max;
260 cap->max_send_sge = qp->sq.max_gs;
225c7b1f
RD		 261 cap->max_inline_data = (1 << qp->sq.wqe_shift) - send_wqe_overhead(type) -
262 sizeof (struct mlx4_wqe_inline_seg);
263
264 return 0;
265}
266
2446304d
EC		 267static int set_user_sq_size(struct mlx4_ib_qp *qp,
268 struct mlx4_ib_create_qp *ucmd)
269{
270 qp->sq.max = 1 << ucmd->log_sq_bb_count;
271 qp->sq.wqe_shift = ucmd->log_sq_stride;
272
273 qp->buf_size = (qp->rq.max << qp->rq.wqe_shift) +
274 (qp->sq.max << qp->sq.wqe_shift);
275
276 return 0;
277}
278
225c7b1f
RD		 279static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
280 struct ib_qp_init_attr *init_attr,
281 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
282{
225c7b1f 283 int err;
225c7b1f
RD		 284
285 mutex_init(&qp->mutex);
286 spin_lock_init(&qp->sq.lock);
287 spin_lock_init(&qp->rq.lock);
288
289 qp->state = IB_QPS_RESET;
290 qp->atomic_rd_en = 0;
291 qp->resp_depth = 0;
292
293 qp->rq.head = 0;
294 qp->rq.tail = 0;
295 qp->sq.head = 0;
296 qp->sq.tail = 0;
297
a4cd7ed8 298 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
225c7b1f
RD		 299 if (err)
300 goto err;
301
302 if (pd->uobject) {
303 struct mlx4_ib_create_qp ucmd;
304
305 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
306 err = -EFAULT;
307 goto err;
308 }
309
2446304d
EC		 310 err = set_user_sq_size(qp, &ucmd);
311 if (err)
312 goto err;
313
225c7b1f
RD		 314 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
315 qp->buf_size, 0);
316 if (IS_ERR(qp->umem)) {
317 err = PTR_ERR(qp->umem);
318 goto err;
319 }
320
321 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
322 ilog2(qp->umem->page_size), &qp->mtt);
323 if (err)
324 goto err_buf;
325
326 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
327 if (err)
328 goto err_mtt;
329
02d89b87
RD		 330 if (!init_attr->srq) {
331 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
332 ucmd.db_addr, &qp->db);
333 if (err)
334 goto err_mtt;
335 }
225c7b1f 336 } else {
2446304d
EC		 337 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
338 if (err)
339 goto err;
340
02d89b87
RD		 341 if (!init_attr->srq) {
342 err = mlx4_ib_db_alloc(dev, &qp->db, 0);
343 if (err)
344 goto err;
225c7b1f 345
02d89b87
RD		 346 *qp->db.db = 0;
347 }
225c7b1f
RD		 348
349 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
350 err = -ENOMEM;
351 goto err_db;
352 }
353
354 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
355 &qp->mtt);
356 if (err)
357 goto err_buf;
358
359 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
360 if (err)
361 goto err_mtt;
362
225c7b1f
RD		 363 qp->sq.wrid = kmalloc(qp->sq.max * sizeof (u64), GFP_KERNEL);
364 qp->rq.wrid = kmalloc(qp->rq.max * sizeof (u64), GFP_KERNEL);
365
366 if (!qp->sq.wrid || !qp->rq.wrid) {
367 err = -ENOMEM;
368 goto err_wrid;
369 }
370
371 /* We don't support inline sends for kernel QPs (yet) */
372 init_attr->cap.max_inline_data = 0;
373 }
374
375 err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
376 if (err)
377 goto err_wrid;
378
379 /*
380 * Hardware wants QPN written in big-endian order (after
381 * shifting) for send doorbell. Precompute this value to save
382 * a little bit when posting sends.
383 */
384 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
385
386 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
387 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
388 else
389 qp->sq_signal_bits = 0;
390
391 qp->mqp.event = mlx4_ib_qp_event;
392
393 return 0;
394
395err_wrid:
02d89b87 396 if (pd->uobject && !init_attr->srq)
225c7b1f
RD		 397 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
398 else {
399 kfree(qp->sq.wrid);
400 kfree(qp->rq.wrid);
401 }
402
403err_mtt:
404 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
405
406err_buf:
407 if (pd->uobject)
408 ib_umem_release(qp->umem);
409 else
410 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
411
412err_db:
02d89b87 413 if (!pd->uobject && !init_attr->srq)
225c7b1f
RD		 414 mlx4_ib_db_free(dev, &qp->db);
415
416err:
417 return err;
418}
419
420static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
421{
422 switch (state) {
423 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
424 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
425 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
426 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
427 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
428 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
429 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
430 default: return -1;
431 }
432}
433
434static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
435{
436 if (send_cq == recv_cq)
437 spin_lock_irq(&send_cq->lock);
438 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
439 spin_lock_irq(&send_cq->lock);
440 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
441 } else {
442 spin_lock_irq(&recv_cq->lock);
443 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
444 }
445}
446
447static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
448{
449 if (send_cq == recv_cq)
450 spin_unlock_irq(&send_cq->lock);
451 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
452 spin_unlock(&recv_cq->lock);
453 spin_unlock_irq(&send_cq->lock);
454 } else {
455 spin_unlock(&send_cq->lock);
456 spin_unlock_irq(&recv_cq->lock);
457 }
458}
459
460static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
461 int is_user)
462{
463 struct mlx4_ib_cq *send_cq, *recv_cq;
464
465 if (qp->state != IB_QPS_RESET)
466 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
467 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
468 printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
469 qp->mqp.qpn);
470
471 send_cq = to_mcq(qp->ibqp.send_cq);
472 recv_cq = to_mcq(qp->ibqp.recv_cq);
473
474 mlx4_ib_lock_cqs(send_cq, recv_cq);
475
476 if (!is_user) {
477 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
478 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
479 if (send_cq != recv_cq)
480 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
481 }
482
483 mlx4_qp_remove(dev->dev, &qp->mqp);
484
485 mlx4_ib_unlock_cqs(send_cq, recv_cq);
486
487 mlx4_qp_free(dev->dev, &qp->mqp);
488 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
489
490 if (is_user) {
02d89b87
RD		 491 if (!qp->ibqp.srq)
492 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
493 &qp->db);
225c7b1f
RD		 494 ib_umem_release(qp->umem);
495 } else {
496 kfree(qp->sq.wrid);
497 kfree(qp->rq.wrid);
498 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
02d89b87
RD		 499 if (!qp->ibqp.srq)
500 mlx4_ib_db_free(dev, &qp->db);
225c7b1f
RD		 501 }
502}
503
504struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
505 struct ib_qp_init_attr *init_attr,
506 struct ib_udata *udata)
507{
508 struct mlx4_ib_dev *dev = to_mdev(pd->device);
509 struct mlx4_ib_sqp *sqp;
510 struct mlx4_ib_qp *qp;
511 int err;
512
513 switch (init_attr->qp_type) {
514 case IB_QPT_RC:
515 case IB_QPT_UC:
516 case IB_QPT_UD:
517 {
518 qp = kmalloc(sizeof *qp, GFP_KERNEL);
519 if (!qp)
520 return ERR_PTR(-ENOMEM);
521
522 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
523 if (err) {
524 kfree(qp);
525 return ERR_PTR(err);
526 }
527
528 qp->ibqp.qp_num = qp->mqp.qpn;
529
530 break;
531 }
532 case IB_QPT_SMI:
533 case IB_QPT_GSI:
534 {
535 /* Userspace is not allowed to create special QPs: */
536 if (pd->uobject)
537 return ERR_PTR(-EINVAL);
538
539 sqp = kmalloc(sizeof *sqp, GFP_KERNEL);
540 if (!sqp)
541 return ERR_PTR(-ENOMEM);
542
543 qp = &sqp->qp;
544
545 err = create_qp_common(dev, pd, init_attr, udata,
546 dev->dev->caps.sqp_start +
547 (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
548 init_attr->port_num - 1,
549 qp);
550 if (err) {
551 kfree(sqp);
552 return ERR_PTR(err);
553 }
554
555 qp->port = init_attr->port_num;
556 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
557
558 break;
559 }
560 default:
561 /* Don't support raw QPs */
562 return ERR_PTR(-EINVAL);
563 }
564
565 return &qp->ibqp;
566}
567
568int mlx4_ib_destroy_qp(struct ib_qp *qp)
569{
570 struct mlx4_ib_dev *dev = to_mdev(qp->device);
571 struct mlx4_ib_qp *mqp = to_mqp(qp);
572
573 if (is_qp0(dev, mqp))
574 mlx4_CLOSE_PORT(dev->dev, mqp->port);
575
576 destroy_qp_common(dev, mqp, !!qp->pd->uobject);
577
578 if (is_sqp(dev, mqp))
579 kfree(to_msqp(mqp));
580 else
581 kfree(mqp);
582
583 return 0;
584}
585
586static void init_port(struct mlx4_ib_dev *dev, int port)
587{
588 struct mlx4_init_port_param param;
589 int err;
590
591 memset(&param, 0, sizeof param);
592
593 param.port_width_cap = dev->dev->caps.port_width_cap;
594 param.vl_cap = dev->dev->caps.vl_cap;
595 param.mtu = ib_mtu_enum_to_int(dev->dev->caps.mtu_cap);
596 param.max_gid = dev->dev->caps.gid_table_len;
597 param.max_pkey = dev->dev->caps.pkey_table_len;
598
599 err = mlx4_INIT_PORT(dev->dev, &param, port);
600 if (err)
601 printk(KERN_WARNING "INIT_PORT failed, return code %d.\n", err);
602}
603
604static int to_mlx4_st(enum ib_qp_type type)
605{
606 switch (type) {
607 case IB_QPT_RC: return MLX4_QP_ST_RC;
608 case IB_QPT_UC: return MLX4_QP_ST_UC;
609 case IB_QPT_UD: return MLX4_QP_ST_UD;
610 case IB_QPT_SMI:
611 case IB_QPT_GSI: return MLX4_QP_ST_MLX;
612 default: return -1;
613 }
614}
615
65adfa91 616static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 617 int attr_mask)
618{
619 u8 dest_rd_atomic;
620 u32 access_flags;
621 u32 hw_access_flags = 0;
622
623 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
624 dest_rd_atomic = attr->max_dest_rd_atomic;
625 else
626 dest_rd_atomic = qp->resp_depth;
627
628 if (attr_mask & IB_QP_ACCESS_FLAGS)
629 access_flags = attr->qp_access_flags;
630 else
631 access_flags = qp->atomic_rd_en;
632
633 if (!dest_rd_atomic)
634 access_flags &= IB_ACCESS_REMOTE_WRITE;
635
636 if (access_flags & IB_ACCESS_REMOTE_READ)
637 hw_access_flags |= MLX4_QP_BIT_RRE;
638 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
639 hw_access_flags |= MLX4_QP_BIT_RAE;
640 if (access_flags & IB_ACCESS_REMOTE_WRITE)
641 hw_access_flags |= MLX4_QP_BIT_RWE;
642
643 return cpu_to_be32(hw_access_flags);
644}
645
65adfa91 646static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 647 int attr_mask)
648{
649 if (attr_mask & IB_QP_PKEY_INDEX)
650 sqp->pkey_index = attr->pkey_index;
651 if (attr_mask & IB_QP_QKEY)
652 sqp->qkey = attr->qkey;
653 if (attr_mask & IB_QP_SQ_PSN)
654 sqp->send_psn = attr->sq_psn;
655}
656
657static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
658{
659 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
660}
661
65adfa91 662static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
225c7b1f
RD		 663 struct mlx4_qp_path *path, u8 port)
664{
665 path->grh_mylmc = ah->src_path_bits & 0x7f;
666 path->rlid = cpu_to_be16(ah->dlid);
667 if (ah->static_rate) {
668 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
669 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
670 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
671 --path->static_rate;
672 } else
673 path->static_rate = 0;
674 path->counter_index = 0xff;
675
676 if (ah->ah_flags & IB_AH_GRH) {
677 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len) {
678 printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
679 ah->grh.sgid_index, dev->dev->caps.gid_table_len - 1);
680 return -1;
681 }
682
683 path->grh_mylmc |= 1 << 7;
684 path->mgid_index = ah->grh.sgid_index;
685 path->hop_limit = ah->grh.hop_limit;
686 path->tclass_flowlabel =
687 cpu_to_be32((ah->grh.traffic_class << 20) |
688 (ah->grh.flow_label));
689 memcpy(path->rgid, ah->grh.dgid.raw, 16);
690 }
691
692 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
693 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
694
695 return 0;
696}
697
65adfa91
MT		 698static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
699 const struct ib_qp_attr *attr, int attr_mask,
700 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 701{
702 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
703 struct mlx4_ib_qp *qp = to_mqp(ibqp);
704 struct mlx4_qp_context *context;
705 enum mlx4_qp_optpar optpar = 0;
225c7b1f
RD		 706 int sqd_event;
707 int err = -EINVAL;
708
709 context = kzalloc(sizeof *context, GFP_KERNEL);
710 if (!context)
711 return -ENOMEM;
712
225c7b1f
RD		 713 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
714 (to_mlx4_st(ibqp->qp_type) << 16));
715 context->flags |= cpu_to_be32(1 << 8); /* DE? */
716
717 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
718 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
719 else {
720 optpar |= MLX4_QP_OPTPAR_PM_STATE;
721 switch (attr->path_mig_state) {
722 case IB_MIG_MIGRATED:
723 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
724 break;
725 case IB_MIG_REARM:
726 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
727 break;
728 case IB_MIG_ARMED:
729 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
730 break;
731 }
732 }
733
734 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
735 ibqp->qp_type == IB_QPT_UD)
736 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
737 else if (attr_mask & IB_QP_PATH_MTU) {
738 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
739 printk(KERN_ERR "path MTU (%u) is invalid\n",
740 attr->path_mtu);
741 return -EINVAL;
742 }
743 context->mtu_msgmax = (attr->path_mtu << 5) | 31;
744 }
745
746 if (qp->rq.max)
747 context->rq_size_stride = ilog2(qp->rq.max) << 3;
748 context->rq_size_stride |= qp->rq.wqe_shift - 4;
749
750 if (qp->sq.max)
751 context->sq_size_stride = ilog2(qp->sq.max) << 3;
752 context->sq_size_stride |= qp->sq.wqe_shift - 4;
753
754 if (qp->ibqp.uobject)
755 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
756 else
757 context->usr_page = cpu_to_be32(dev->priv_uar.index);
758
759 if (attr_mask & IB_QP_DEST_QPN)
760 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
761
762 if (attr_mask & IB_QP_PORT) {
763 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
764 !(attr_mask & IB_QP_AV)) {
765 mlx4_set_sched(&context->pri_path, attr->port_num);
766 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
767 }
768 }
769
770 if (attr_mask & IB_QP_PKEY_INDEX) {
771 context->pri_path.pkey_index = attr->pkey_index;
772 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
773 }
774
225c7b1f
RD		 775 if (attr_mask & IB_QP_AV) {
776 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
777 attr_mask & IB_QP_PORT ? attr->port_num : qp->port)) {
778 err = -EINVAL;
779 goto out;
780 }
781
782 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
783 MLX4_QP_OPTPAR_SCHED_QUEUE);
784 }
785
786 if (attr_mask & IB_QP_TIMEOUT) {
787 context->pri_path.ackto = attr->timeout << 3;
788 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
789 }
790
791 if (attr_mask & IB_QP_ALT_PATH) {
792 if (attr->alt_pkey_index >= dev->dev->caps.pkey_table_len)
793 return -EINVAL;
794
795 if (attr->alt_port_num == 0 ||
796 attr->alt_port_num > dev->dev->caps.num_ports)
797 return -EINVAL;
798
799 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
800 attr->alt_port_num))
801 return -EINVAL;
802
803 context->alt_path.pkey_index = attr->alt_pkey_index;
804 context->alt_path.ackto = attr->alt_timeout << 3;
805 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
806 }
807
808 context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
809 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53
JM		 810
811 if (attr_mask & IB_QP_RNR_RETRY) {
812 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
813 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
814 }
815
225c7b1f
RD		 816 if (attr_mask & IB_QP_RETRY_CNT) {
817 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
818 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
819 }
820
821 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
822 if (attr->max_rd_atomic)
823 context->params1 |=
824 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
825 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
826 }
827
828 if (attr_mask & IB_QP_SQ_PSN)
829 context->next_send_psn = cpu_to_be32(attr->sq_psn);
830
831 context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
832
833 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
834 if (attr->max_dest_rd_atomic)
835 context->params2 |=
836 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
837 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
838 }
839
840 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
841 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
842 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
843 }
844
845 if (ibqp->srq)
846 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
847
848 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
849 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
850 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
851 }
852 if (attr_mask & IB_QP_RQ_PSN)
853 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
854
855 context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
856
857 if (attr_mask & IB_QP_QKEY) {
858 context->qkey = cpu_to_be32(attr->qkey);
859 optpar |= MLX4_QP_OPTPAR_Q_KEY;
860 }
861
862 if (ibqp->srq)
863 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
864
02d89b87 865 if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 866 context->db_rec_addr = cpu_to_be64(qp->db.dma);
867
868 if (cur_state == IB_QPS_INIT &&
869 new_state == IB_QPS_RTR &&
870 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
871 ibqp->qp_type == IB_QPT_UD)) {
872 context->pri_path.sched_queue = (qp->port - 1) << 6;
873 if (is_qp0(dev, qp))
874 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
875 else
876 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
877 }
878
879 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
880 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
881 sqd_event = 1;
882 else
883 sqd_event = 0;
884
c0be5fb5
EC		 885 /*
886 * Before passing a kernel QP to the HW, make sure that the
887 * ownership bits of the send queue are set so that the
888 * hardware doesn't start processing stale work requests.
889 */
890 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
891 struct mlx4_wqe_ctrl_seg *ctrl;
892 int i;
893
894 for (i = 0; i < qp->sq.max; ++i) {
895 ctrl = get_send_wqe(qp, i);
896 ctrl->owner_opcode = cpu_to_be32(1 << 31);
897 }
898 }
899
225c7b1f
RD		 900 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
901 to_mlx4_state(new_state), context, optpar,
902 sqd_event, &qp->mqp);
903 if (err)
904 goto out;
905
906 qp->state = new_state;
907
908 if (attr_mask & IB_QP_ACCESS_FLAGS)
909 qp->atomic_rd_en = attr->qp_access_flags;
910 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
911 qp->resp_depth = attr->max_dest_rd_atomic;
912 if (attr_mask & IB_QP_PORT)
913 qp->port = attr->port_num;
914 if (attr_mask & IB_QP_ALT_PATH)
915 qp->alt_port = attr->alt_port_num;
916
917 if (is_sqp(dev, qp))
918 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
919
920 /*
921 * If we moved QP0 to RTR, bring the IB link up; if we moved
922 * QP0 to RESET or ERROR, bring the link back down.
923 */
924 if (is_qp0(dev, qp)) {
925 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
926 init_port(dev, qp->port);
927
928 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
929 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
930 mlx4_CLOSE_PORT(dev->dev, qp->port);
931 }
932
933 /*
934 * If we moved a kernel QP to RESET, clean up all old CQ
935 * entries and reinitialize the QP.
936 */
937 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
938 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
939 ibqp->srq ? to_msrq(ibqp->srq): NULL);
940 if (ibqp->send_cq != ibqp->recv_cq)
941 mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
942
943 qp->rq.head = 0;
944 qp->rq.tail = 0;
945 qp->sq.head = 0;
946 qp->sq.tail = 0;
02d89b87
RD		 947 if (!ibqp->srq)
948 *qp->db.db = 0;
225c7b1f
RD		 949 }
950
951out:
225c7b1f
RD		 952 kfree(context);
953 return err;
954}
955
65adfa91
MT		 956static const struct ib_qp_attr mlx4_ib_qp_attr = { .port_num = 1 };
957static const int mlx4_ib_qp_attr_mask_table[IB_QPT_UD + 1] = {
958 [IB_QPT_UD] = (IB_QP_PKEY_INDEX |
959 IB_QP_PORT |
960 IB_QP_QKEY),
961 [IB_QPT_UC] = (IB_QP_PKEY_INDEX |
962 IB_QP_PORT |
963 IB_QP_ACCESS_FLAGS),
964 [IB_QPT_RC] = (IB_QP_PKEY_INDEX |
965 IB_QP_PORT |
966 IB_QP_ACCESS_FLAGS),
967 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX |
968 IB_QP_QKEY),
969 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX |
970 IB_QP_QKEY),
971};
972
973int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
974 int attr_mask, struct ib_udata *udata)
975{
976 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
977 struct mlx4_ib_qp *qp = to_mqp(ibqp);
978 enum ib_qp_state cur_state, new_state;
979 int err = -EINVAL;
980
981 mutex_lock(&qp->mutex);
982
983 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
984 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
985
986 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
987 goto out;
988
989 if ((attr_mask & IB_QP_PKEY_INDEX) &&
990 attr->pkey_index >= dev->dev->caps.pkey_table_len) {
991 goto out;
992 }
993
994 if ((attr_mask & IB_QP_PORT) &&
995 (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
996 goto out;
997 }
998
999 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1000 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1001 goto out;
1002 }
1003
1004 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1005 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1006 goto out;
1007 }
1008
1009 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1010 err = 0;
1011 goto out;
1012 }
1013
1014 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) {
1015 err = __mlx4_ib_modify_qp(ibqp, &mlx4_ib_qp_attr,
1016 mlx4_ib_qp_attr_mask_table[ibqp->qp_type],
1017 IB_QPS_RESET, IB_QPS_INIT);
1018 if (err)
1019 goto out;
1020 cur_state = IB_QPS_INIT;
1021 }
1022
1023 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1024
1025out:
1026 mutex_unlock(&qp->mutex);
1027 return err;
1028}
1029
225c7b1f
RD		 1030static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1031 void *wqe)
1032{
1033 struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1034 struct mlx4_wqe_mlx_seg *mlx = wqe;
1035 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1036 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1037 u16 pkey;
1038 int send_size;
1039 int header_size;
1040 int i;
1041
1042 send_size = 0;
1043 for (i = 0; i < wr->num_sge; ++i)
1044 send_size += wr->sg_list[i].length;
1045
1046 ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1047
1048 sqp->ud_header.lrh.service_level =
1049 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1050 sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1051 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.g_slid & 0x7f);
1052 if (mlx4_ib_ah_grh_present(ah)) {
1053 sqp->ud_header.grh.traffic_class =
1054 (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1055 sqp->ud_header.grh.flow_label =
1056 ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
15261303 1057 sqp->ud_header.grh.hop_limit = ah->av.hop_limit;
225c7b1f
RD		 1058 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1059 ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1060 memcpy(sqp->ud_header.grh.destination_gid.raw,
1061 ah->av.dgid, 16);
1062 }
1063
1064 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1065 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1066 (sqp->ud_header.lrh.destination_lid ==
1067 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1068 (sqp->ud_header.lrh.service_level << 8));
1069 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1070
1071 switch (wr->opcode) {
1072 case IB_WR_SEND:
1073 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1074 sqp->ud_header.immediate_present = 0;
1075 break;
1076 case IB_WR_SEND_WITH_IMM:
1077 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1078 sqp->ud_header.immediate_present = 1;
1079 sqp->ud_header.immediate_data = wr->imm_data;
1080 break;
1081 default:
1082 return -EINVAL;
1083 }
1084
1085 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1086 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1087 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1088 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1089 if (!sqp->qp.ibqp.qp_num)
1090 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1091 else
1092 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1093 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1094 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1095 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1096 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1097 sqp->qkey : wr->wr.ud.remote_qkey);
1098 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1099
1100 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1101
1102 if (0) {
1103 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1104 for (i = 0; i < header_size / 4; ++i) {
1105 if (i % 8 == 0)
1106 printk(" [%02x] ", i * 4);
1107 printk(" %08x",
1108 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1109 if ((i + 1) % 8 == 0)
1110 printk("\n");
1111 }
1112 printk("\n");
1113 }
1114
1115 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1116 memcpy(inl + 1, sqp->header_buf, header_size);
1117
1118 return ALIGN(sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1119}
1120
1121static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1122{
1123 unsigned cur;
1124 struct mlx4_ib_cq *cq;
1125
1126 cur = wq->head - wq->tail;
1127 if (likely(cur + nreq < wq->max))
1128 return 0;
1129
1130 cq = to_mcq(ib_cq);
1131 spin_lock(&cq->lock);
1132 cur = wq->head - wq->tail;
1133 spin_unlock(&cq->lock);
1134
1135 return cur + nreq >= wq->max;
1136}
1137
1138int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1139 struct ib_send_wr **bad_wr)
1140{
1141 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1142 void *wqe;
1143 struct mlx4_wqe_ctrl_seg *ctrl;
1144 unsigned long flags;
1145 int nreq;
1146 int err = 0;
1147 int ind;
1148 int size;
1149 int i;
1150
1151 spin_lock_irqsave(&qp->rq.lock, flags);
1152
1153 ind = qp->sq.head;
1154
1155 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1156 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1157 err = -ENOMEM;
1158 *bad_wr = wr;
1159 goto out;
1160 }
1161
1162 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1163 err = -EINVAL;
1164 *bad_wr = wr;
1165 goto out;
1166 }
1167
1168 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.max - 1));
1169 qp->sq.wrid[ind & (qp->sq.max - 1)] = wr->wr_id;
1170
1171 ctrl->srcrb_flags =
1172 (wr->send_flags & IB_SEND_SIGNALED ?
1173 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1174 (wr->send_flags & IB_SEND_SOLICITED ?
1175 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1176 qp->sq_signal_bits;
1177
1178 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1179 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1180 ctrl->imm = wr->imm_data;
1181 else
1182 ctrl->imm = 0;
1183
1184 wqe += sizeof *ctrl;
1185 size = sizeof *ctrl / 16;
1186
1187 switch (ibqp->qp_type) {
1188 case IB_QPT_RC:
1189 case IB_QPT_UC:
1190 switch (wr->opcode) {
1191 case IB_WR_ATOMIC_CMP_AND_SWP:
1192 case IB_WR_ATOMIC_FETCH_AND_ADD:
1193 ((struct mlx4_wqe_raddr_seg *) wqe)->raddr =
1194 cpu_to_be64(wr->wr.atomic.remote_addr);
1195 ((struct mlx4_wqe_raddr_seg *) wqe)->rkey =
1196 cpu_to_be32(wr->wr.atomic.rkey);
1197 ((struct mlx4_wqe_raddr_seg *) wqe)->reserved = 0;
1198
1199 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1200
1201 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1202 ((struct mlx4_wqe_atomic_seg *) wqe)->swap_add =
1203 cpu_to_be64(wr->wr.atomic.swap);
1204 ((struct mlx4_wqe_atomic_seg *) wqe)->compare =
1205 cpu_to_be64(wr->wr.atomic.compare_add);
1206 } else {
1207 ((struct mlx4_wqe_atomic_seg *) wqe)->swap_add =
1208 cpu_to_be64(wr->wr.atomic.compare_add);
1209 ((struct mlx4_wqe_atomic_seg *) wqe)->compare = 0;
1210 }
1211
1212 wqe += sizeof (struct mlx4_wqe_atomic_seg);
1213 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1214 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1215
1216 break;
1217
1218 case IB_WR_RDMA_READ:
1219 case IB_WR_RDMA_WRITE:
1220 case IB_WR_RDMA_WRITE_WITH_IMM:
1221 ((struct mlx4_wqe_raddr_seg *) wqe)->raddr =
1222 cpu_to_be64(wr->wr.rdma.remote_addr);
1223 ((struct mlx4_wqe_raddr_seg *) wqe)->rkey =
1224 cpu_to_be32(wr->wr.rdma.rkey);
1225 ((struct mlx4_wqe_raddr_seg *) wqe)->reserved = 0;
1226
1227 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1228 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1229
1230 break;
1231
1232 default:
1233 /* No extra segments required for sends */
1234 break;
1235 }
1236 break;
1237
1238 case IB_QPT_UD:
1239 memcpy(((struct mlx4_wqe_datagram_seg *) wqe)->av,
1240 &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1241 ((struct mlx4_wqe_datagram_seg *) wqe)->dqpn =
1242 cpu_to_be32(wr->wr.ud.remote_qpn);
1243 ((struct mlx4_wqe_datagram_seg *) wqe)->qkey =
1244 cpu_to_be32(wr->wr.ud.remote_qkey);
1245
1246 wqe += sizeof (struct mlx4_wqe_datagram_seg);
1247 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1248 break;
1249
1250 case IB_QPT_SMI:
1251 case IB_QPT_GSI:
1252 err = build_mlx_header(to_msqp(qp), wr, ctrl);
1253 if (err < 0) {
1254 *bad_wr = wr;
1255 goto out;
1256 }
1257 wqe += err;
1258 size += err / 16;
1259
1260 err = 0;
1261 break;
1262
1263 default:
1264 break;
1265 }
1266
1267 for (i = 0; i < wr->num_sge; ++i) {
1268 ((struct mlx4_wqe_data_seg *) wqe)->byte_count =
1269 cpu_to_be32(wr->sg_list[i].length);
1270 ((struct mlx4_wqe_data_seg *) wqe)->lkey =
1271 cpu_to_be32(wr->sg_list[i].lkey);
1272 ((struct mlx4_wqe_data_seg *) wqe)->addr =
1273 cpu_to_be64(wr->sg_list[i].addr);
1274
1275 wqe += sizeof (struct mlx4_wqe_data_seg);
1276 size += sizeof (struct mlx4_wqe_data_seg) / 16;
1277 }
1278
1279 /* Add one more inline data segment for ICRC for MLX sends */
1280 if (qp->ibqp.qp_type == IB_QPT_SMI || qp->ibqp.qp_type == IB_QPT_GSI) {
1281 ((struct mlx4_wqe_inline_seg *) wqe)->byte_count =
1282 cpu_to_be32((1 << 31) | 4);
1283 ((u32 *) wqe)[1] = 0;
1284 wqe += sizeof (struct mlx4_wqe_data_seg);
1285 size += sizeof (struct mlx4_wqe_data_seg) / 16;
1286 }
1287
1288 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1289 MLX4_WQE_CTRL_FENCE : 0) | size;
1290
1291 /*
1292 * Make sure descriptor is fully written before
1293 * setting ownership bit (because HW can start
1294 * executing as soon as we do).
1295 */
1296 wmb();
1297
59b0ed12 1298 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
225c7b1f
RD		 1299 err = -EINVAL;
1300 goto out;
1301 }
1302
1303 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1304 (ind & qp->sq.max ? cpu_to_be32(1 << 31) : 0);
1305
1306 ++ind;
1307 }
1308
1309out:
1310 if (likely(nreq)) {
1311 qp->sq.head += nreq;
1312
1313 /*
1314 * Make sure that descriptors are written before
1315 * doorbell record.
1316 */
1317 wmb();
1318
1319 writel(qp->doorbell_qpn,
1320 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1321
1322 /*
1323 * Make sure doorbells don't leak out of SQ spinlock
1324 * and reach the HCA out of order.
1325 */
1326 mmiowb();
1327 }
1328
1329 spin_unlock_irqrestore(&qp->rq.lock, flags);
1330
1331 return err;
1332}
1333
1334int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1335 struct ib_recv_wr **bad_wr)
1336{
1337 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1338 struct mlx4_wqe_data_seg *scat;
1339 unsigned long flags;
1340 int err = 0;
1341 int nreq;
1342 int ind;
1343 int i;
1344
1345 spin_lock_irqsave(&qp->rq.lock, flags);
1346
1347 ind = qp->rq.head & (qp->rq.max - 1);
1348
1349 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1350 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1351 err = -ENOMEM;
1352 *bad_wr = wr;
1353 goto out;
1354 }
1355
1356 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1357 err = -EINVAL;
1358 *bad_wr = wr;
1359 goto out;
1360 }
1361
1362 scat = get_recv_wqe(qp, ind);
1363
1364 for (i = 0; i < wr->num_sge; ++i) {
1365 scat[i].byte_count = cpu_to_be32(wr->sg_list[i].length);
1366 scat[i].lkey = cpu_to_be32(wr->sg_list[i].lkey);
1367 scat[i].addr = cpu_to_be64(wr->sg_list[i].addr);
1368 }
1369
1370 if (i < qp->rq.max_gs) {
1371 scat[i].byte_count = 0;
1372 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
1373 scat[i].addr = 0;
1374 }
1375
1376 qp->rq.wrid[ind] = wr->wr_id;
1377
1378 ind = (ind + 1) & (qp->rq.max - 1);
1379 }
1380
1381out:
1382 if (likely(nreq)) {
1383 qp->rq.head += nreq;
1384
1385 /*
1386 * Make sure that descriptors are written before
1387 * doorbell record.
1388 */
1389 wmb();
1390
1391 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1392 }
1393
1394 spin_unlock_irqrestore(&qp->rq.lock, flags);
1395
1396 return err;
1397}
Linux 6.x block layer and io_uring tree(s)