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IB/mlx4: Add IB counters table
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
5a0e3ad6 35#include <linux/slab.h>
fa417f7b 36#include <linux/netdevice.h>
ea54b10c 37
225c7b1f
RD		 38#include <rdma/ib_cache.h>
39#include <rdma/ib_pack.h>
4c3eb3ca 40#include <rdma/ib_addr.h>
1ffeb2eb 41#include <rdma/ib_mad.h>
225c7b1f 42
2f48485d 43#include <linux/mlx4/driver.h>
225c7b1f
RD		 44#include <linux/mlx4/qp.h>
45
46#include "mlx4_ib.h"
47#include "user.h"
48
35f05dab
YH		 49static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
50 struct mlx4_ib_cq *recv_cq);
51static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
52 struct mlx4_ib_cq *recv_cq);
53
225c7b1f
RD		 54enum {
55 MLX4_IB_ACK_REQ_FREQ = 8,
56};
57
58enum {
59 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 60 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
61 MLX4_IB_LINK_TYPE_IB = 0,
62 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 63};
64
65enum {
66 /*
fa417f7b 67 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 68 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
69 * tag. (LRH would only use 8 bytes, so Ethernet is the
70 * biggest case)
225c7b1f 71 */
4c3eb3ca 72 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 73 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 74};
75
fa417f7b
EC		 76enum {
77 MLX4_IB_IBOE_ETHERTYPE = 0x8915
78};
79
225c7b1f
RD		 80struct mlx4_ib_sqp {
81 struct mlx4_ib_qp qp;
82 int pkey_index;
83 u32 qkey;
84 u32 send_psn;
85 struct ib_ud_header ud_header;
86 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
87};
88
83904132 89enum {
417608c2
EC		 90 MLX4_IB_MIN_SQ_STRIDE = 6,
91 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 92};
93
3987a2d3
OG		 94enum {
95 MLX4_RAW_QP_MTU = 7,
96 MLX4_RAW_QP_MSGMAX = 31,
97};
98
297e0dad
MS		 99#ifndef ETH_ALEN
100#define ETH_ALEN 6
101#endif
297e0dad 102
225c7b1f 103static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
114 [IB_WR_FAST_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
6ff63e19 117 [IB_WR_BIND_MW] = cpu_to_be32(MLX4_OPCODE_BIND_MW),
225c7b1f
RD		 118};
119
120static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
121{
122 return container_of(mqp, struct mlx4_ib_sqp, qp);
123}
124
1ffeb2eb
JM		 125static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
126{
127 if (!mlx4_is_master(dev->dev))
128 return 0;
129
47605df9
JM		 130 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
131 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
132 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 133}
134
225c7b1f
RD		 135static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
136{
47605df9
JM		 137 int proxy_sqp = 0;
138 int real_sqp = 0;
139 int i;
140 /* PPF or Native -- real SQP */
141 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
142 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
143 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
144 if (real_sqp)
145 return 1;
146 /* VF or PF -- proxy SQP */
147 if (mlx4_is_mfunc(dev->dev)) {
148 for (i = 0; i < dev->dev->caps.num_ports; i++) {
149 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
150 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
151 proxy_sqp = 1;
152 break;
153 }
154 }
155 }
156 return proxy_sqp;
225c7b1f
RD		 157}
158
1ffeb2eb 159/* used for INIT/CLOSE port logic */
225c7b1f
RD		 160static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
161{
47605df9
JM		 162 int proxy_qp0 = 0;
163 int real_qp0 = 0;
164 int i;
165 /* PPF or Native -- real QP0 */
166 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
167 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
168 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
169 if (real_qp0)
170 return 1;
171 /* VF or PF -- proxy QP0 */
172 if (mlx4_is_mfunc(dev->dev)) {
173 for (i = 0; i < dev->dev->caps.num_ports; i++) {
174 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
175 proxy_qp0 = 1;
176 break;
177 }
178 }
179 }
180 return proxy_qp0;
225c7b1f
RD		 181}
182
183static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
184{
1c69fc2a 185 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 186}
187
188static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
189{
190 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
191}
192
193static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
194{
195 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
196}
197
0e6e7416
RD		 198/*
199 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 200 * first four bytes of every 64 byte chunk with
201 * 0x7FFFFFF | (invalid_ownership_value << 31).
202 *
203 * When the max work request size is less than or equal to the WQE
204 * basic block size, as an optimization, we can stamp all WQEs with
205 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 206 */
ea54b10c 207static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 208{
d2ae16d5 209 __be32 *wqe;
0e6e7416 210 int i;
ea54b10c
JM		 211 int s;
212 int ind;
213 void *buf;
214 __be32 stamp;
9670e553 215 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 216
ea54b10c 217 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 218 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 219 for (i = 0; i < s; i += 64) {
220 ind = (i >> qp->sq.wqe_shift) + n;
221 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
222 cpu_to_be32(0xffffffff);
223 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
224 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
225 *wqe = stamp;
226 }
227 } else {
9670e553
EC		 228 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
229 s = (ctrl->fence_size & 0x3f) << 4;
ea54b10c
JM		 230 for (i = 64; i < s; i += 64) {
231 wqe = buf + i;
d2ae16d5 232 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 233 }
234 }
235}
236
237static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
238{
239 struct mlx4_wqe_ctrl_seg *ctrl;
240 struct mlx4_wqe_inline_seg *inl;
241 void *wqe;
242 int s;
243
244 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
245 s = sizeof(struct mlx4_wqe_ctrl_seg);
246
247 if (qp->ibqp.qp_type == IB_QPT_UD) {
248 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
249 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
250 memset(dgram, 0, sizeof *dgram);
251 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
252 s += sizeof(struct mlx4_wqe_datagram_seg);
253 }
254
255 /* Pad the remainder of the WQE with an inline data segment. */
256 if (size > s) {
257 inl = wqe + s;
258 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
259 }
260 ctrl->srcrb_flags = 0;
261 ctrl->fence_size = size / 16;
262 /*
263 * Make sure descriptor is fully written before setting ownership bit
264 * (because HW can start executing as soon as we do).
265 */
266 wmb();
267
268 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
269 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 270
ea54b10c
JM		 271 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
272}
273
274/* Post NOP WQE to prevent wrap-around in the middle of WR */
275static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
276{
277 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
278 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
279 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
280 ind += s;
281 }
282 return ind;
0e6e7416
RD		 283}
284
225c7b1f
RD		 285static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
286{
287 struct ib_event event;
288 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
289
290 if (type == MLX4_EVENT_TYPE_PATH_MIG)
291 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
292
293 if (ibqp->event_handler) {
294 event.device = ibqp->device;
295 event.element.qp = ibqp;
296 switch (type) {
297 case MLX4_EVENT_TYPE_PATH_MIG:
298 event.event = IB_EVENT_PATH_MIG;
299 break;
300 case MLX4_EVENT_TYPE_COMM_EST:
301 event.event = IB_EVENT_COMM_EST;
302 break;
303 case MLX4_EVENT_TYPE_SQ_DRAINED:
304 event.event = IB_EVENT_SQ_DRAINED;
305 break;
306 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
307 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
308 break;
309 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
310 event.event = IB_EVENT_QP_FATAL;
311 break;
312 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
313 event.event = IB_EVENT_PATH_MIG_ERR;
314 break;
315 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
316 event.event = IB_EVENT_QP_REQ_ERR;
317 break;
318 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
319 event.event = IB_EVENT_QP_ACCESS_ERR;
320 break;
321 default:
987c8f8f 322 pr_warn("Unexpected event type %d "
225c7b1f
RD		 323 "on QP %06x\n", type, qp->qpn);
324 return;
325 }
326
327 ibqp->event_handler(&event, ibqp->qp_context);
328 }
329}
330
1ffeb2eb 331static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 332{
333 /*
334 * UD WQEs must have a datagram segment.
335 * RC and UC WQEs might have a remote address segment.
336 * MLX WQEs need two extra inline data segments (for the UD
337 * header and space for the ICRC).
338 */
339 switch (type) {
1ffeb2eb 340 case MLX4_IB_QPT_UD:
225c7b1f 341 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 342 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 343 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 344 case MLX4_IB_QPT_PROXY_SMI_OWNER:
345 case MLX4_IB_QPT_PROXY_SMI:
346 case MLX4_IB_QPT_PROXY_GSI:
347 return sizeof (struct mlx4_wqe_ctrl_seg) +
348 sizeof (struct mlx4_wqe_datagram_seg) + 64;
349 case MLX4_IB_QPT_TUN_SMI_OWNER:
350 case MLX4_IB_QPT_TUN_GSI:
351 return sizeof (struct mlx4_wqe_ctrl_seg) +
352 sizeof (struct mlx4_wqe_datagram_seg);
353
354 case MLX4_IB_QPT_UC:
225c7b1f
RD		 355 return sizeof (struct mlx4_wqe_ctrl_seg) +
356 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 357 case MLX4_IB_QPT_RC:
225c7b1f
RD		 358 return sizeof (struct mlx4_wqe_ctrl_seg) +
359 sizeof (struct mlx4_wqe_atomic_seg) +
360 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 361 case MLX4_IB_QPT_SMI:
362 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 363 return sizeof (struct mlx4_wqe_ctrl_seg) +
364 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 365 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
366 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 367 sizeof (struct mlx4_wqe_inline_seg),
368 sizeof (struct mlx4_wqe_data_seg)) +
369 ALIGN(4 +
370 sizeof (struct mlx4_wqe_inline_seg),
371 sizeof (struct mlx4_wqe_data_seg));
372 default:
373 return sizeof (struct mlx4_wqe_ctrl_seg);
374 }
375}
376
2446304d 377static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
0a1405da 378 int is_user, int has_rq, struct mlx4_ib_qp *qp)
225c7b1f 379{
2446304d 380 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 381 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
382 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 383 return -EINVAL;
384
0a1405da 385 if (!has_rq) {
a4cd7ed8
RD		 386 if (cap->max_recv_wr)
387 return -EINVAL;
2446304d 388
0e6e7416 389 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 390 } else {
391 /* HW requires >= 1 RQ entry with >= 1 gather entry */
392 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
393 return -EINVAL;
394
0e6e7416 395 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 396 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 397 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
398 }
2446304d 399
fc2d0044
SG		 400 /* leave userspace return values as they were, so as not to break ABI */
401 if (is_user) {
402 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
403 cap->max_recv_sge = qp->rq.max_gs;
404 } else {
405 cap->max_recv_wr = qp->rq.max_post =
406 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
407 cap->max_recv_sge = min(qp->rq.max_gs,
408 min(dev->dev->caps.max_sq_sg,
409 dev->dev->caps.max_rq_sg));
410 }
2446304d
EC		 411
412 return 0;
413}
414
415static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
1ffeb2eb 416 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 417{
ea54b10c
JM		 418 int s;
419
2446304d 420 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 421 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
422 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 423 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 424 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
425 return -EINVAL;
426
427 /*
428 * For MLX transport we need 2 extra S/G entries:
429 * one for the header and one for the checksum at the end
430 */
1ffeb2eb
JM		 431 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
432 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 433 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
434 return -EINVAL;
435
ea54b10c
JM		 436 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
437 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 438 send_wqe_overhead(type, qp->flags);
225c7b1f 439
cd155c1c
RD		 440 if (s > dev->dev->caps.max_sq_desc_sz)
441 return -EINVAL;
442
0e6e7416 443 /*
ea54b10c
JM		 444 * Hermon supports shrinking WQEs, such that a single work
445 * request can include multiple units of 1 << wqe_shift. This
446 * way, work requests can differ in size, and do not have to
447 * be a power of 2 in size, saving memory and speeding up send
448 * WR posting. Unfortunately, if we do this then the
449 * wqe_index field in CQEs can't be used to look up the WR ID
450 * anymore, so we do this only if selective signaling is off.
451 *
452 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 453 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 454 * constant-sized WRs to make sure a WR is always fully within
455 * a single page-sized chunk.
456 *
457 * Finally, we use NOP work requests to pad the end of the
458 * work queue, to avoid wrap-around in the middle of WR. We
459 * set NEC bit to avoid getting completions with error for
460 * these NOP WRs, but since NEC is only supported starting
461 * with firmware 2.2.232, we use constant-sized WRs for older
462 * firmware.
463 *
464 * And, since MLX QPs only support SEND, we use constant-sized
465 * WRs in this case.
466 *
467 * We look for the smallest value of wqe_shift such that the
468 * resulting number of wqes does not exceed device
469 * capabilities.
470 *
471 * We set WQE size to at least 64 bytes, this way stamping
472 * invalidates each WQE.
0e6e7416 473 */
ea54b10c
JM		 474 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
475 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 476 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
477 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
478 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 479 qp->sq.wqe_shift = ilog2(64);
480 else
481 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
482
483 for (;;) {
ea54b10c
JM		 484 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
485
486 /*
487 * We need to leave 2 KB + 1 WR of headroom in the SQ to
488 * allow HW to prefetch.
489 */
490 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
491 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
492 qp->sq_max_wqes_per_wr +
493 qp->sq_spare_wqes);
494
495 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
496 break;
497
498 if (qp->sq_max_wqes_per_wr <= 1)
499 return -EINVAL;
500
501 ++qp->sq.wqe_shift;
502 }
503
cd155c1c
RD		 504 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
505 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 506 send_wqe_overhead(type, qp->flags)) /
507 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 508
509 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
510 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 511 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
512 qp->rq.offset = 0;
0e6e7416 513 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 514 } else {
0e6e7416 515 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 516 qp->sq.offset = 0;
517 }
518
ea54b10c
JM		 519 cap->max_send_wr = qp->sq.max_post =
520 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 521 cap->max_send_sge = min(qp->sq.max_gs,
522 min(dev->dev->caps.max_sq_sg,
523 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 524 /* We don't support inline sends for kernel QPs (yet) */
525 cap->max_inline_data = 0;
225c7b1f
RD		 526
527 return 0;
528}
529
83904132
JM		 530static int set_user_sq_size(struct mlx4_ib_dev *dev,
531 struct mlx4_ib_qp *qp,
2446304d
EC		 532 struct mlx4_ib_create_qp *ucmd)
533{
83904132
JM		 534 /* Sanity check SQ size before proceeding */
535 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
536 ucmd->log_sq_stride >
537 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
538 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
539 return -EINVAL;
540
0e6e7416 541 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 542 qp->sq.wqe_shift = ucmd->log_sq_stride;
543
0e6e7416
RD		 544 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
545 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 546
547 return 0;
548}
549
1ffeb2eb
JM		 550static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
551{
552 int i;
553
554 qp->sqp_proxy_rcv =
555 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
556 GFP_KERNEL);
557 if (!qp->sqp_proxy_rcv)
558 return -ENOMEM;
559 for (i = 0; i < qp->rq.wqe_cnt; i++) {
560 qp->sqp_proxy_rcv[i].addr =
561 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
562 GFP_KERNEL);
563 if (!qp->sqp_proxy_rcv[i].addr)
564 goto err;
565 qp->sqp_proxy_rcv[i].map =
566 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
567 sizeof (struct mlx4_ib_proxy_sqp_hdr),
568 DMA_FROM_DEVICE);
cc47d369
SO		 569 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
570 kfree(qp->sqp_proxy_rcv[i].addr);
571 goto err;
572 }
1ffeb2eb
JM		 573 }
574 return 0;
575
576err:
577 while (i > 0) {
578 --i;
579 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
580 sizeof (struct mlx4_ib_proxy_sqp_hdr),
581 DMA_FROM_DEVICE);
582 kfree(qp->sqp_proxy_rcv[i].addr);
583 }
584 kfree(qp->sqp_proxy_rcv);
585 qp->sqp_proxy_rcv = NULL;
586 return -ENOMEM;
587}
588
589static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
590{
591 int i;
592
593 for (i = 0; i < qp->rq.wqe_cnt; i++) {
594 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
595 sizeof (struct mlx4_ib_proxy_sqp_hdr),
596 DMA_FROM_DEVICE);
597 kfree(qp->sqp_proxy_rcv[i].addr);
598 }
599 kfree(qp->sqp_proxy_rcv);
600}
601
0a1405da
SH		 602static int qp_has_rq(struct ib_qp_init_attr *attr)
603{
604 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
605 return 0;
606
607 return !attr->srq;
608}
609
99ec41d0
JM		 610static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
611{
612 int i;
613 for (i = 0; i < dev->caps.num_ports; i++) {
614 if (qpn == dev->caps.qp0_proxy[i])
615 return !!dev->caps.qp0_qkey[i];
616 }
617 return 0;
618}
619
225c7b1f
RD		 620static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
621 struct ib_qp_init_attr *init_attr,
40f2287b
JK		 622 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
623 gfp_t gfp)
225c7b1f 624{
a3cdcbfa 625 int qpn;
225c7b1f 626 int err;
1ffeb2eb
JM		 627 struct mlx4_ib_sqp *sqp;
628 struct mlx4_ib_qp *qp;
629 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 630 struct mlx4_ib_cq *mcq;
631 unsigned long flags;
1ffeb2eb
JM		 632
633 /* When tunneling special qps, we use a plain UD qp */
634 if (sqpn) {
635 if (mlx4_is_mfunc(dev->dev) &&
636 (!mlx4_is_master(dev->dev) ||
637 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
638 if (init_attr->qp_type == IB_QPT_GSI)
639 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 640 else {
641 if (mlx4_is_master(dev->dev) ||
642 qp0_enabled_vf(dev->dev, sqpn))
643 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
644 else
645 qp_type = MLX4_IB_QPT_PROXY_SMI;
646 }
1ffeb2eb
JM		 647 }
648 qpn = sqpn;
649 /* add extra sg entry for tunneling */
650 init_attr->cap.max_recv_sge++;
651 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
652 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
653 container_of(init_attr,
654 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
655 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
656 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
657 !mlx4_is_master(dev->dev))
658 return -EINVAL;
659 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
660 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 661 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
662 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
663 tnl_init->port))
1ffeb2eb
JM		 664 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
665 else
666 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 667 /* we are definitely in the PPF here, since we are creating
668 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
669 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
670 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 671 sqpn = qpn;
672 }
673
674 if (!*caller_qp) {
675 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
676 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
677 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6fcd8d0d 678 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
1ffeb2eb
JM		 679 if (!sqp)
680 return -ENOMEM;
681 qp = &sqp->qp;
2f5bb473
JM		 682 qp->pri.vid = 0xFFFF;
683 qp->alt.vid = 0xFFFF;
1ffeb2eb 684 } else {
6fcd8d0d 685 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
1ffeb2eb
JM		 686 if (!qp)
687 return -ENOMEM;
2f5bb473
JM		 688 qp->pri.vid = 0xFFFF;
689 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 690 }
691 } else
692 qp = *caller_qp;
693
694 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 695
696 mutex_init(&qp->mutex);
697 spin_lock_init(&qp->sq.lock);
698 spin_lock_init(&qp->rq.lock);
fa417f7b 699 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 700 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 701
702 qp->state = IB_QPS_RESET;
ea54b10c
JM		 703 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
704 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 705
0a1405da 706 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
225c7b1f
RD		 707 if (err)
708 goto err;
709
710 if (pd->uobject) {
711 struct mlx4_ib_create_qp ucmd;
712
713 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
714 err = -EFAULT;
715 goto err;
716 }
717
0e6e7416
RD		 718 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
719
83904132 720 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 721 if (err)
722 goto err;
723
225c7b1f 724 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 725 qp->buf_size, 0, 0);
225c7b1f
RD		 726 if (IS_ERR(qp->umem)) {
727 err = PTR_ERR(qp->umem);
728 goto err;
729 }
730
731 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
732 ilog2(qp->umem->page_size), &qp->mtt);
733 if (err)
734 goto err_buf;
735
736 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
737 if (err)
738 goto err_mtt;
739
0a1405da 740 if (qp_has_rq(init_attr)) {
02d89b87
RD		 741 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
742 ucmd.db_addr, &qp->db);
743 if (err)
744 goto err_mtt;
745 }
225c7b1f 746 } else {
0e6e7416
RD		 747 qp->sq_no_prefetch = 0;
748
521e575b
RL		 749 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
750 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
751
b832be1e
EC		 752 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
753 qp->flags |= MLX4_IB_QP_LSO;
754
c1c98501
MB		 755 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
756 if (dev->steering_support ==
757 MLX4_STEERING_MODE_DEVICE_MANAGED)
758 qp->flags |= MLX4_IB_QP_NETIF;
759 else
760 goto err;
761 }
762
1ffeb2eb 763 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 764 if (err)
765 goto err;
766
0a1405da 767 if (qp_has_rq(init_attr)) {
40f2287b 768 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
02d89b87
RD		 769 if (err)
770 goto err;
225c7b1f 771
02d89b87
RD		 772 *qp->db.db = 0;
773 }
225c7b1f 774
40f2287b 775 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
225c7b1f
RD		 776 err = -ENOMEM;
777 goto err_db;
778 }
779
780 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
781 &qp->mtt);
782 if (err)
783 goto err_buf;
784
40f2287b 785 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
225c7b1f
RD		 786 if (err)
787 goto err_mtt;
788
40f2287b
JK		 789 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), gfp);
790 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), gfp);
225c7b1f
RD		 791 if (!qp->sq.wrid || !qp->rq.wrid) {
792 err = -ENOMEM;
793 goto err_wrid;
794 }
225c7b1f
RD		 795 }
796
a3cdcbfa 797 if (sqpn) {
1ffeb2eb
JM		 798 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
799 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
800 if (alloc_proxy_bufs(pd->device, qp)) {
801 err = -ENOMEM;
802 goto err_wrid;
803 }
804 }
a3cdcbfa 805 } else {
ddae0349
EE		 806 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
807 * otherwise, the WQE BlueFlame setup flow wrongly causes
808 * VLAN insertion. */
3987a2d3 809 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 810 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 811 (init_attr->cap.max_send_wr ?
812 MLX4_RESERVE_ETH_BF_QP : 0) |
813 (init_attr->cap.max_recv_wr ?
814 MLX4_RESERVE_A0_QP : 0));
3987a2d3 815 else
c1c98501
MB		 816 if (qp->flags & MLX4_IB_QP_NETIF)
817 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
818 else
819 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
ddae0349 820 &qpn, 0);
a3cdcbfa 821 if (err)
1ffeb2eb 822 goto err_proxy;
a3cdcbfa
YP		 823 }
824
40f2287b 825 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
225c7b1f 826 if (err)
a3cdcbfa 827 goto err_qpn;
225c7b1f 828
0a1405da
SH		 829 if (init_attr->qp_type == IB_QPT_XRC_TGT)
830 qp->mqp.qpn |= (1 << 23);
831
225c7b1f
RD		 832 /*
833 * Hardware wants QPN written in big-endian order (after
834 * shifting) for send doorbell. Precompute this value to save
835 * a little bit when posting sends.
836 */
837 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
838
225c7b1f 839 qp->mqp.event = mlx4_ib_qp_event;
1ffeb2eb
JM		 840 if (!*caller_qp)
841 *caller_qp = qp;
35f05dab
YH		 842
843 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
844 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
845 to_mcq(init_attr->recv_cq));
846 /* Maintain device to QPs access, needed for further handling
847 * via reset flow
848 */
849 list_add_tail(&qp->qps_list, &dev->qp_list);
850 /* Maintain CQ to QPs access, needed for further handling
851 * via reset flow
852 */
853 mcq = to_mcq(init_attr->send_cq);
854 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
855 mcq = to_mcq(init_attr->recv_cq);
856 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
857 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
858 to_mcq(init_attr->recv_cq));
859 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 860 return 0;
861
a3cdcbfa 862err_qpn:
c1c98501
MB		 863 if (!sqpn) {
864 if (qp->flags & MLX4_IB_QP_NETIF)
865 mlx4_ib_steer_qp_free(dev, qpn, 1);
866 else
867 mlx4_qp_release_range(dev->dev, qpn, 1);
868 }
1ffeb2eb
JM		 869err_proxy:
870 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
871 free_proxy_bufs(pd->device, qp);
225c7b1f 872err_wrid:
23f1b384 873 if (pd->uobject) {
0a1405da
SH		 874 if (qp_has_rq(init_attr))
875 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 876 } else {
225c7b1f
RD		 877 kfree(qp->sq.wrid);
878 kfree(qp->rq.wrid);
879 }
880
881err_mtt:
882 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
883
884err_buf:
885 if (pd->uobject)
886 ib_umem_release(qp->umem);
887 else
888 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
889
890err_db:
0a1405da 891 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 892 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 893
894err:
1ffeb2eb
JM		 895 if (!*caller_qp)
896 kfree(qp);
225c7b1f
RD		 897 return err;
898}
899
900static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
901{
902 switch (state) {
903 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
904 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
905 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
906 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
907 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
908 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
909 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
910 default: return -1;
911 }
912}
913
914static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 915 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 916{
338a8fad 917 if (send_cq == recv_cq) {
35f05dab 918 spin_lock(&send_cq->lock);
338a8fad
RD		 919 __acquire(&recv_cq->lock);
920 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 921 spin_lock(&send_cq->lock);
225c7b1f
RD		 922 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
923 } else {
35f05dab 924 spin_lock(&recv_cq->lock);
225c7b1f
RD		 925 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
926 }
927}
928
929static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 930 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 931{
338a8fad
RD		 932 if (send_cq == recv_cq) {
933 __release(&recv_cq->lock);
35f05dab 934 spin_unlock(&send_cq->lock);
338a8fad 935 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 936 spin_unlock(&recv_cq->lock);
35f05dab 937 spin_unlock(&send_cq->lock);
225c7b1f
RD		 938 } else {
939 spin_unlock(&send_cq->lock);
35f05dab 940 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 941 }
942}
943
fa417f7b
EC		 944static void del_gid_entries(struct mlx4_ib_qp *qp)
945{
946 struct mlx4_ib_gid_entry *ge, *tmp;
947
948 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
949 list_del(&ge->list);
950 kfree(ge);
951 }
952}
953
0a1405da
SH		 954static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
955{
956 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
957 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
958 else
959 return to_mpd(qp->ibqp.pd);
960}
961
962static void get_cqs(struct mlx4_ib_qp *qp,
963 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
964{
965 switch (qp->ibqp.qp_type) {
966 case IB_QPT_XRC_TGT:
967 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
968 *recv_cq = *send_cq;
969 break;
970 case IB_QPT_XRC_INI:
971 *send_cq = to_mcq(qp->ibqp.send_cq);
972 *recv_cq = *send_cq;
973 break;
974 default:
975 *send_cq = to_mcq(qp->ibqp.send_cq);
976 *recv_cq = to_mcq(qp->ibqp.recv_cq);
977 break;
978 }
979}
980
225c7b1f
RD		 981static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
982 int is_user)
983{
984 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 985 unsigned long flags;
225c7b1f 986
2f5bb473 987 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 988 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
989 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 990 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 991 qp->mqp.qpn);
25476b02 992 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 993 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
994 qp->pri.smac = 0;
25476b02 995 qp->pri.smac_port = 0;
2f5bb473
JM		 996 }
997 if (qp->alt.smac) {
998 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
999 qp->alt.smac = 0;
1000 }
1001 if (qp->pri.vid < 0x1000) {
1002 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1003 qp->pri.vid = 0xFFFF;
1004 qp->pri.candidate_vid = 0xFFFF;
1005 qp->pri.update_vid = 0;
1006 }
1007 if (qp->alt.vid < 0x1000) {
1008 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1009 qp->alt.vid = 0xFFFF;
1010 qp->alt.candidate_vid = 0xFFFF;
1011 qp->alt.update_vid = 0;
1012 }
1013 }
225c7b1f 1014
0a1405da 1015 get_cqs(qp, &send_cq, &recv_cq);
225c7b1f 1016
35f05dab 1017 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1018 mlx4_ib_lock_cqs(send_cq, recv_cq);
1019
35f05dab
YH		 1020 /* del from lists under both locks above to protect reset flow paths */
1021 list_del(&qp->qps_list);
1022 list_del(&qp->cq_send_list);
1023 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1024 if (!is_user) {
1025 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1026 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1027 if (send_cq != recv_cq)
1028 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1029 }
1030
1031 mlx4_qp_remove(dev->dev, &qp->mqp);
1032
1033 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1034 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1035
1036 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1037
c1c98501
MB		 1038 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1039 if (qp->flags & MLX4_IB_QP_NETIF)
1040 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1041 else
1042 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1043 }
a3cdcbfa 1044
225c7b1f
RD		 1045 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1046
1047 if (is_user) {
0a1405da 1048 if (qp->rq.wqe_cnt)
02d89b87
RD		 1049 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1050 &qp->db);
225c7b1f
RD		 1051 ib_umem_release(qp->umem);
1052 } else {
1053 kfree(qp->sq.wrid);
1054 kfree(qp->rq.wrid);
1ffeb2eb
JM		 1055 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1056 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1057 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1058 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1059 if (qp->rq.wqe_cnt)
6296883c 1060 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1061 }
fa417f7b
EC		 1062
1063 del_gid_entries(qp);
225c7b1f
RD		 1064}
1065
47605df9
JM		 1066static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1067{
1068 /* Native or PPF */
1069 if (!mlx4_is_mfunc(dev->dev) ||
1070 (mlx4_is_master(dev->dev) &&
1071 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1072 return dev->dev->phys_caps.base_sqpn +
1073 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1074 attr->port_num - 1;
1075 }
1076 /* PF or VF -- creating proxies */
1077 if (attr->qp_type == IB_QPT_SMI)
1078 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1079 else
1080 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1081}
1082
225c7b1f
RD		 1083struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1084 struct ib_qp_init_attr *init_attr,
1085 struct ib_udata *udata)
1086{
1ffeb2eb 1087 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1088 int err;
0a1405da 1089 u16 xrcdn = 0;
40f2287b 1090 gfp_t gfp;
225c7b1f 1091
40f2287b
JK		 1092 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1093 GFP_NOIO : GFP_KERNEL;
521e575b 1094 /*
1ffeb2eb
JM		 1095 * We only support LSO, vendor flag1, and multicast loopback blocking,
1096 * and only for kernel UD QPs.
521e575b 1097 */
1ffeb2eb
JM		 1098 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1099 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1100 MLX4_IB_SRIOV_TUNNEL_QP |
1101 MLX4_IB_SRIOV_SQP |
40f2287b
JK		 1102 MLX4_IB_QP_NETIF |
1103 MLX4_IB_QP_CREATE_USE_GFP_NOIO))
b832be1e 1104 return ERR_PTR(-EINVAL);
521e575b 1105
c1c98501
MB		 1106 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1107 if (init_attr->qp_type != IB_QPT_UD)
1108 return ERR_PTR(-EINVAL);
1109 }
1110
521e575b 1111 if (init_attr->create_flags &&
1ffeb2eb 1112 (udata ||
40f2287b 1113 ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | MLX4_IB_QP_CREATE_USE_GFP_NOIO)) &&
1ffeb2eb
JM		 1114 init_attr->qp_type != IB_QPT_UD) ||
1115 ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1116 init_attr->qp_type > IB_QPT_GSI)))
b846f25a
EC		 1117 return ERR_PTR(-EINVAL);
1118
225c7b1f 1119 switch (init_attr->qp_type) {
0a1405da
SH		 1120 case IB_QPT_XRC_TGT:
1121 pd = to_mxrcd(init_attr->xrcd)->pd;
1122 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1123 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1124 /* fall through */
1125 case IB_QPT_XRC_INI:
1126 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1127 return ERR_PTR(-ENOSYS);
1128 init_attr->recv_cq = init_attr->send_cq;
1129 /* fall through */
225c7b1f
RD		 1130 case IB_QPT_RC:
1131 case IB_QPT_UC:
3987a2d3 1132 case IB_QPT_RAW_PACKET:
40f2287b 1133 qp = kzalloc(sizeof *qp, gfp);
225c7b1f
RD		 1134 if (!qp)
1135 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1136 qp->pri.vid = 0xFFFF;
1137 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1138 /* fall through */
1139 case IB_QPT_UD:
1140 {
1141 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
40f2287b 1142 udata, 0, &qp, gfp);
1ffeb2eb 1143 if (err)
225c7b1f 1144 return ERR_PTR(err);
225c7b1f
RD		 1145
1146 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1147 qp->xrcdn = xrcdn;
225c7b1f
RD		 1148
1149 break;
1150 }
1151 case IB_QPT_SMI:
1152 case IB_QPT_GSI:
1153 {
1154 /* Userspace is not allowed to create special QPs: */
0a1405da 1155 if (udata)
225c7b1f
RD		 1156 return ERR_PTR(-EINVAL);
1157
0a1405da 1158 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
47605df9 1159 get_sqp_num(to_mdev(pd->device), init_attr),
40f2287b 1160 &qp, gfp);
1ffeb2eb 1161 if (err)
225c7b1f 1162 return ERR_PTR(err);
225c7b1f
RD		 1163
1164 qp->port = init_attr->port_num;
1165 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1166
1167 break;
1168 }
1169 default:
1170 /* Don't support raw QPs */
1171 return ERR_PTR(-EINVAL);
1172 }
1173
1174 return &qp->ibqp;
1175}
1176
1177int mlx4_ib_destroy_qp(struct ib_qp *qp)
1178{
1179 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1180 struct mlx4_ib_qp *mqp = to_mqp(qp);
0a1405da 1181 struct mlx4_ib_pd *pd;
225c7b1f
RD		 1182
1183 if (is_qp0(dev, mqp))
1184 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1185
9433c188
MB		 1186 if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1187 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1188 dev->qp1_proxy[mqp->port - 1] = NULL;
1189 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1190 }
1191
0a1405da
SH		 1192 pd = get_pd(mqp);
1193 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
225c7b1f
RD		 1194
1195 if (is_sqp(dev, mqp))
1196 kfree(to_msqp(mqp));
1197 else
1198 kfree(mqp);
1199
1200 return 0;
1201}
1202
1ffeb2eb 1203static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1204{
1205 switch (type) {
1ffeb2eb
JM		 1206 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1207 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1208 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1209 case MLX4_IB_QPT_XRC_INI:
1210 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1211 case MLX4_IB_QPT_SMI:
1212 case MLX4_IB_QPT_GSI:
1213 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1214
1215 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1216 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1217 MLX4_QP_ST_MLX : -1);
1218 case MLX4_IB_QPT_PROXY_SMI:
1219 case MLX4_IB_QPT_TUN_SMI:
1220 case MLX4_IB_QPT_PROXY_GSI:
1221 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1222 MLX4_QP_ST_UD : -1);
1223 default: return -1;
225c7b1f
RD		 1224 }
1225}
1226
65adfa91 1227static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1228 int attr_mask)
1229{
1230 u8 dest_rd_atomic;
1231 u32 access_flags;
1232 u32 hw_access_flags = 0;
1233
1234 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1235 dest_rd_atomic = attr->max_dest_rd_atomic;
1236 else
1237 dest_rd_atomic = qp->resp_depth;
1238
1239 if (attr_mask & IB_QP_ACCESS_FLAGS)
1240 access_flags = attr->qp_access_flags;
1241 else
1242 access_flags = qp->atomic_rd_en;
1243
1244 if (!dest_rd_atomic)
1245 access_flags &= IB_ACCESS_REMOTE_WRITE;
1246
1247 if (access_flags & IB_ACCESS_REMOTE_READ)
1248 hw_access_flags |= MLX4_QP_BIT_RRE;
1249 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1250 hw_access_flags |= MLX4_QP_BIT_RAE;
1251 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1252 hw_access_flags |= MLX4_QP_BIT_RWE;
1253
1254 return cpu_to_be32(hw_access_flags);
1255}
1256
65adfa91 1257static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1258 int attr_mask)
1259{
1260 if (attr_mask & IB_QP_PKEY_INDEX)
1261 sqp->pkey_index = attr->pkey_index;
1262 if (attr_mask & IB_QP_QKEY)
1263 sqp->qkey = attr->qkey;
1264 if (attr_mask & IB_QP_SQ_PSN)
1265 sqp->send_psn = attr->sq_psn;
1266}
1267
1268static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1269{
1270 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1271}
1272
297e0dad
MS		 1273static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1274 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1275 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1276{
fa417f7b
EC		 1277 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1278 IB_LINK_LAYER_ETHERNET;
4c3eb3ca 1279 int vidx;
297e0dad 1280 int smac_index;
2f5bb473 1281 int err;
297e0dad 1282
fa417f7b 1283
225c7b1f
RD		 1284 path->grh_mylmc = ah->src_path_bits & 0x7f;
1285 path->rlid = cpu_to_be16(ah->dlid);
1286 if (ah->static_rate) {
1287 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1288 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1289 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1290 --path->static_rate;
1291 } else
1292 path->static_rate = 0;
225c7b1f
RD		 1293
1294 if (ah->ah_flags & IB_AH_GRH) {
5070cd22
MS		 1295 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1296 port,
1297 ah->grh.sgid_index);
1298
1299 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1300 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1301 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1302 return -1;
1303 }
1304
1305 path->grh_mylmc |= 1 << 7;
5070cd22 1306 path->mgid_index = real_sgid_index;
225c7b1f
RD		 1307 path->hop_limit = ah->grh.hop_limit;
1308 path->tclass_flowlabel =
1309 cpu_to_be32((ah->grh.traffic_class << 20) |
1310 (ah->grh.flow_label));
1311 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1312 }
1313
fa417f7b
EC		 1314 if (is_eth) {
1315 if (!(ah->ah_flags & IB_AH_GRH))
1316 return -1;
1317
2f5bb473
JM		 1318 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1319 ((port - 1) << 6) | ((ah->sl & 7) << 3);
4c3eb3ca 1320
297e0dad 1321 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1322 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1323 if (smac_info->vid < 0x1000) {
1324 /* both valid vlan ids */
1325 if (smac_info->vid != vlan_tag) {
1326 /* different VIDs. unreg old and reg new */
1327 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1328 if (err)
1329 return err;
1330 smac_info->candidate_vid = vlan_tag;
1331 smac_info->candidate_vlan_index = vidx;
1332 smac_info->candidate_vlan_port = port;
1333 smac_info->update_vid = 1;
1334 path->vlan_index = vidx;
1335 } else {
1336 path->vlan_index = smac_info->vlan_index;
1337 }
1338 } else {
1339 /* no current vlan tag in qp */
1340 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1341 if (err)
1342 return err;
1343 smac_info->candidate_vid = vlan_tag;
1344 smac_info->candidate_vlan_index = vidx;
1345 smac_info->candidate_vlan_port = port;
1346 smac_info->update_vid = 1;
1347 path->vlan_index = vidx;
1348 }
297e0dad 1349 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1350 path->fl = 1 << 6;
1351 } else {
1352 /* have current vlan tag. unregister it at modify-qp success */
1353 if (smac_info->vid < 0x1000) {
1354 smac_info->candidate_vid = 0xFFFF;
1355 smac_info->update_vid = 1;
1356 }
4c3eb3ca 1357 }
2f5bb473
JM		 1358
1359 /* get smac_index for RoCE use.
1360 * If no smac was yet assigned, register one.
1361 * If one was already assigned, but the new mac differs,
1362 * unregister the old one and register the new one.
1363 */
25476b02
JM		 1364 if ((!smac_info->smac && !smac_info->smac_port) ||
1365 smac_info->smac != smac) {
2f5bb473
JM		 1366 /* register candidate now, unreg if needed, after success */
1367 smac_index = mlx4_register_mac(dev->dev, port, smac);
1368 if (smac_index >= 0) {
1369 smac_info->candidate_smac_index = smac_index;
1370 smac_info->candidate_smac = smac;
1371 smac_info->candidate_smac_port = port;
1372 } else {
1373 return -EINVAL;
1374 }
1375 } else {
1376 smac_index = smac_info->smac_index;
1377 }
1378
1379 memcpy(path->dmac, ah->dmac, 6);
1380 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1381 /* put MAC table smac index for IBoE */
1382 path->grh_mylmc = (u8) (smac_index) | 0x80;
1383 } else {
4c3eb3ca
EC		 1384 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1385 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
2f5bb473 1386 }
fa417f7b 1387
225c7b1f
RD		 1388 return 0;
1389}
1390
297e0dad
MS		 1391static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1392 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1393 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1394 struct mlx4_qp_path *path, u8 port)
1395{
1396 return _mlx4_set_path(dev, &qp->ah_attr,
1397 mlx4_mac_to_u64((u8 *)qp->smac),
1398 (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff,
2f5bb473 1399 path, &mqp->pri, port);
297e0dad
MS		 1400}
1401
1402static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1403 const struct ib_qp_attr *qp,
1404 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1405 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1406 struct mlx4_qp_path *path, u8 port)
1407{
1408 return _mlx4_set_path(dev, &qp->alt_ah_attr,
1409 mlx4_mac_to_u64((u8 *)qp->alt_smac),
1410 (qp_attr_mask & IB_QP_ALT_VID) ?
1411 qp->alt_vlan_id : 0xffff,
2f5bb473 1412 path, &mqp->alt, port);
297e0dad
MS		 1413}
1414
fa417f7b
EC		 1415static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1416{
1417 struct mlx4_ib_gid_entry *ge, *tmp;
1418
1419 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1420 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1421 ge->added = 1;
1422 ge->port = qp->port;
1423 }
1424 }
1425}
1426
2f5bb473
JM		 1427static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, u8 *smac,
1428 struct mlx4_qp_context *context)
1429{
2f5bb473
JM		 1430 u64 u64_mac;
1431 int smac_index;
1432
3e0629cb 1433 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1434
1435 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1436 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1437 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1438 if (smac_index >= 0) {
1439 qp->pri.candidate_smac_index = smac_index;
1440 qp->pri.candidate_smac = u64_mac;
1441 qp->pri.candidate_smac_port = qp->port;
1442 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1443 } else {
1444 return -ENOENT;
1445 }
1446 }
1447 return 0;
1448}
1449
65adfa91
MT		 1450static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1451 const struct ib_qp_attr *attr, int attr_mask,
1452 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 1453{
1454 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1455 struct mlx4_ib_qp *qp = to_mqp(ibqp);
0a1405da
SH		 1456 struct mlx4_ib_pd *pd;
1457 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 1458 struct mlx4_qp_context *context;
1459 enum mlx4_qp_optpar optpar = 0;
225c7b1f 1460 int sqd_event;
c1c98501 1461 int steer_qp = 0;
225c7b1f 1462 int err = -EINVAL;
3ba8e31d 1463 int counter_index;
225c7b1f 1464
3dec4878
JM		 1465 /* APM is not supported under RoCE */
1466 if (attr_mask & IB_QP_ALT_PATH &&
1467 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1468 IB_LINK_LAYER_ETHERNET)
1469 return -ENOTSUPP;
1470
225c7b1f
RD		 1471 context = kzalloc(sizeof *context, GFP_KERNEL);
1472 if (!context)
1473 return -ENOMEM;
1474
225c7b1f 1475 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 1476 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 1477
1478 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1479 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1480 else {
1481 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1482 switch (attr->path_mig_state) {
1483 case IB_MIG_MIGRATED:
1484 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1485 break;
1486 case IB_MIG_REARM:
1487 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1488 break;
1489 case IB_MIG_ARMED:
1490 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1491 break;
1492 }
1493 }
1494
b832be1e 1495 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 1496 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
3987a2d3
OG		 1497 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1498 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
b832be1e
EC		 1499 else if (ibqp->qp_type == IB_QPT_UD) {
1500 if (qp->flags & MLX4_IB_QP_LSO)
1501 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1502 ilog2(dev->dev->caps.max_gso_sz);
1503 else
6e0d733d 1504 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 1505 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 1506 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 1507 pr_err("path MTU (%u) is invalid\n",
225c7b1f 1508 attr->path_mtu);
f5b40431 1509 goto out;
225c7b1f 1510 }
d1f2cd89
EC		 1511 context->mtu_msgmax = (attr->path_mtu << 5) |
1512 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 1513 }
1514
0e6e7416
RD		 1515 if (qp->rq.wqe_cnt)
1516 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 1517 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1518
0e6e7416
RD		 1519 if (qp->sq.wqe_cnt)
1520 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 1521 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1522
0a1405da 1523 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 1524 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 1525 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
02d7ef6f
DB		 1526 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1527 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 1528 }
0e6e7416 1529
225c7b1f
RD		 1530 if (qp->ibqp.uobject)
1531 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1532 else
1533 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1534
1535 if (attr_mask & IB_QP_DEST_QPN)
1536 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1537
1538 if (attr_mask & IB_QP_PORT) {
1539 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1540 !(attr_mask & IB_QP_AV)) {
1541 mlx4_set_sched(&context->pri_path, attr->port_num);
1542 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1543 }
1544 }
1545
cfcde11c 1546 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3ba8e31d
EBE		 1547 counter_index =
1548 dev->counters_table[qp->port - 1].default_counter;
1549 if (counter_index != -1) {
1550 context->pri_path.counter_index = counter_index;
cfcde11c
OG		 1551 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1552 } else
47d8417f
EBE		 1553 context->pri_path.counter_index =
1554 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 1555
1556 if (qp->flags & MLX4_IB_QP_NETIF) {
1557 mlx4_ib_steer_qp_reg(dev, qp, 1);
1558 steer_qp = 1;
1559 }
cfcde11c
OG		 1560 }
1561
225c7b1f 1562 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 1563 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1564 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 1565 context->pri_path.pkey_index = attr->pkey_index;
1566 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1567 }
1568
225c7b1f 1569 if (attr_mask & IB_QP_AV) {
2f5bb473 1570 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1ffeb2eb
JM		 1571 attr_mask & IB_QP_PORT ?
1572 attr->port_num : qp->port))
225c7b1f 1573 goto out;
225c7b1f
RD		 1574
1575 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1576 MLX4_QP_OPTPAR_SCHED_QUEUE);
1577 }
1578
1579 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 1580 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 1581 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1582 }
1583
1584 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 1585 if (attr->alt_port_num == 0 ||
1586 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 1587 goto out;
225c7b1f 1588
5ae2a7a8
RD		 1589 if (attr->alt_pkey_index >=
1590 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 1591 goto out;
5ae2a7a8 1592
2f5bb473
JM		 1593 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1594 &context->alt_path,
297e0dad 1595 attr->alt_port_num))
f5b40431 1596 goto out;
225c7b1f
RD		 1597
1598 context->alt_path.pkey_index = attr->alt_pkey_index;
1599 context->alt_path.ackto = attr->alt_timeout << 3;
1600 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1601 }
1602
0a1405da
SH		 1603 pd = get_pd(qp);
1604 get_cqs(qp, &send_cq, &recv_cq);
1605 context->pd = cpu_to_be32(pd->pdn);
1606 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1607 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1608 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 1609
95d04f07
RD		 1610 /* Set "fast registration enabled" for all kernel QPs */
1611 if (!qp->ibqp.uobject)
1612 context->params1 |= cpu_to_be32(1 << 11);
1613
57f01b53
JM		 1614 if (attr_mask & IB_QP_RNR_RETRY) {
1615 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1616 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1617 }
1618
225c7b1f
RD		 1619 if (attr_mask & IB_QP_RETRY_CNT) {
1620 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1621 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1622 }
1623
1624 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1625 if (attr->max_rd_atomic)
1626 context->params1 |=
1627 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1628 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1629 }
1630
1631 if (attr_mask & IB_QP_SQ_PSN)
1632 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1633
225c7b1f
RD		 1634 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1635 if (attr->max_dest_rd_atomic)
1636 context->params2 |=
1637 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1638 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1639 }
1640
1641 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1642 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1643 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1644 }
1645
1646 if (ibqp->srq)
1647 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1648
1649 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1650 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1651 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1652 }
1653 if (attr_mask & IB_QP_RQ_PSN)
1654 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1655
1ffeb2eb 1656 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 1657 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 1658 if (qp->mlx4_ib_qp_type &
1659 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1660 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1661 else {
1662 if (mlx4_is_mfunc(dev->dev) &&
1663 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1664 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1665 MLX4_RESERVED_QKEY_BASE) {
1666 pr_err("Cannot use reserved QKEY"
1667 " 0x%x (range 0xffff0000..0xffffffff"
1668 " is reserved)\n", attr->qkey);
1669 err = -EINVAL;
1670 goto out;
1671 }
1672 context->qkey = cpu_to_be32(attr->qkey);
1673 }
225c7b1f
RD		 1674 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1675 }
1676
1677 if (ibqp->srq)
1678 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1679
0a1405da 1680 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1681 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1682
1683 if (cur_state == IB_QPS_INIT &&
1684 new_state == IB_QPS_RTR &&
1685 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
3987a2d3
OG		 1686 ibqp->qp_type == IB_QPT_UD ||
1687 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 1688 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 1689 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1690 qp->mlx4_ib_qp_type &
1691 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 1692 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 1693 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1694 context->pri_path.fl = 0x80;
1695 } else {
1696 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1697 context->pri_path.fl = 0x80;
225c7b1f 1698 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 1699 }
2f5bb473
JM		 1700 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1701 IB_LINK_LAYER_ETHERNET) {
1702 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1703 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1704 context->pri_path.feup = 1 << 7; /* don't fsm */
1705 /* handle smac_index */
1706 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1707 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1708 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1709 err = handle_eth_ud_smac_index(dev, qp, (u8 *)attr->smac, context);
bede98e7
MD		 1710 if (err) {
1711 err = -EINVAL;
1712 goto out;
1713 }
9433c188
MB		 1714 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1715 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 1716 }
1717 }
225c7b1f
RD		 1718 }
1719
d2fce8a9 1720 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 1721 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1722 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 1723 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1724 /* set QP to receive both tunneled & non-tunneled packets */
8e1a03b6 1725 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
d2fce8a9
OG		 1726 context->srqn = cpu_to_be32(7 << 28);
1727 }
1728 }
3528f696 1729
297e0dad
MS		 1730 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1731 int is_eth = rdma_port_get_link_layer(
1732 &dev->ib_dev, qp->port) ==
1733 IB_LINK_LAYER_ETHERNET;
1734 if (is_eth) {
1735 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1736 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1737 }
1738 }
1739
1740
225c7b1f
RD		 1741 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1742 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1743 sqd_event = 1;
1744 else
1745 sqd_event = 0;
1746
d57f5f72
VS		 1747 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1748 context->rlkey |= (1 << 4);
1749
c0be5fb5
EC		 1750 /*
1751 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1752 * ownership bits of the send queue are set and the SQ
1753 * headroom is stamped so that the hardware doesn't start
1754 * processing stale work requests.
c0be5fb5
EC		 1755 */
1756 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1757 struct mlx4_wqe_ctrl_seg *ctrl;
1758 int i;
1759
0e6e7416 1760 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1761 ctrl = get_send_wqe(qp, i);
1762 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553
EC		 1763 if (qp->sq_max_wqes_per_wr == 1)
1764 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
0e6e7416 1765
ea54b10c 1766 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 1767 }
1768 }
1769
225c7b1f
RD		 1770 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1771 to_mlx4_state(new_state), context, optpar,
1772 sqd_event, &qp->mqp);
1773 if (err)
1774 goto out;
1775
1776 qp->state = new_state;
1777
1778 if (attr_mask & IB_QP_ACCESS_FLAGS)
1779 qp->atomic_rd_en = attr->qp_access_flags;
1780 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1781 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 1782 if (attr_mask & IB_QP_PORT) {
225c7b1f 1783 qp->port = attr->port_num;
fa417f7b
EC		 1784 update_mcg_macs(dev, qp);
1785 }
225c7b1f
RD		 1786 if (attr_mask & IB_QP_ALT_PATH)
1787 qp->alt_port = attr->alt_port_num;
1788
1789 if (is_sqp(dev, qp))
1790 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1791
1792 /*
1793 * If we moved QP0 to RTR, bring the IB link up; if we moved
1794 * QP0 to RESET or ERROR, bring the link back down.
1795 */
1796 if (is_qp0(dev, qp)) {
1797 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 1798 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 1799 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 1800 qp->port);
225c7b1f
RD		 1801
1802 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1803 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1804 mlx4_CLOSE_PORT(dev->dev, qp->port);
1805 }
1806
1807 /*
1808 * If we moved a kernel QP to RESET, clean up all old CQ
1809 * entries and reinitialize the QP.
1810 */
2f5bb473
JM		 1811 if (new_state == IB_QPS_RESET) {
1812 if (!ibqp->uobject) {
1813 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1814 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1815 if (send_cq != recv_cq)
1816 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1817
1818 qp->rq.head = 0;
1819 qp->rq.tail = 0;
1820 qp->sq.head = 0;
1821 qp->sq.tail = 0;
1822 qp->sq_next_wqe = 0;
1823 if (qp->rq.wqe_cnt)
1824 *qp->db.db = 0;
225c7b1f 1825
2f5bb473
JM		 1826 if (qp->flags & MLX4_IB_QP_NETIF)
1827 mlx4_ib_steer_qp_reg(dev, qp, 0);
1828 }
25476b02 1829 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1830 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1831 qp->pri.smac = 0;
25476b02 1832 qp->pri.smac_port = 0;
2f5bb473
JM		 1833 }
1834 if (qp->alt.smac) {
1835 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1836 qp->alt.smac = 0;
1837 }
1838 if (qp->pri.vid < 0x1000) {
1839 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1840 qp->pri.vid = 0xFFFF;
1841 qp->pri.candidate_vid = 0xFFFF;
1842 qp->pri.update_vid = 0;
1843 }
c1c98501 1844
2f5bb473
JM		 1845 if (qp->alt.vid < 0x1000) {
1846 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1847 qp->alt.vid = 0xFFFF;
1848 qp->alt.candidate_vid = 0xFFFF;
1849 qp->alt.update_vid = 0;
1850 }
225c7b1f 1851 }
225c7b1f 1852out:
c1c98501
MB		 1853 if (err && steer_qp)
1854 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 1855 kfree(context);
25476b02
JM		 1856 if (qp->pri.candidate_smac ||
1857 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 1858 if (err) {
1859 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1860 } else {
25476b02 1861 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 1862 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1863 qp->pri.smac = qp->pri.candidate_smac;
1864 qp->pri.smac_index = qp->pri.candidate_smac_index;
1865 qp->pri.smac_port = qp->pri.candidate_smac_port;
1866 }
1867 qp->pri.candidate_smac = 0;
1868 qp->pri.candidate_smac_index = 0;
1869 qp->pri.candidate_smac_port = 0;
1870 }
1871 if (qp->alt.candidate_smac) {
1872 if (err) {
1873 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1874 } else {
1875 if (qp->alt.smac)
1876 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1877 qp->alt.smac = qp->alt.candidate_smac;
1878 qp->alt.smac_index = qp->alt.candidate_smac_index;
1879 qp->alt.smac_port = qp->alt.candidate_smac_port;
1880 }
1881 qp->alt.candidate_smac = 0;
1882 qp->alt.candidate_smac_index = 0;
1883 qp->alt.candidate_smac_port = 0;
1884 }
1885
1886 if (qp->pri.update_vid) {
1887 if (err) {
1888 if (qp->pri.candidate_vid < 0x1000)
1889 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1890 qp->pri.candidate_vid);
1891 } else {
1892 if (qp->pri.vid < 0x1000)
1893 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1894 qp->pri.vid);
1895 qp->pri.vid = qp->pri.candidate_vid;
1896 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1897 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
1898 }
1899 qp->pri.candidate_vid = 0xFFFF;
1900 qp->pri.update_vid = 0;
1901 }
1902
1903 if (qp->alt.update_vid) {
1904 if (err) {
1905 if (qp->alt.candidate_vid < 0x1000)
1906 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
1907 qp->alt.candidate_vid);
1908 } else {
1909 if (qp->alt.vid < 0x1000)
1910 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
1911 qp->alt.vid);
1912 qp->alt.vid = qp->alt.candidate_vid;
1913 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
1914 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
1915 }
1916 qp->alt.candidate_vid = 0xFFFF;
1917 qp->alt.update_vid = 0;
1918 }
1919
225c7b1f
RD		 1920 return err;
1921}
1922
65adfa91
MT		 1923int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1924 int attr_mask, struct ib_udata *udata)
1925{
1926 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1927 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1928 enum ib_qp_state cur_state, new_state;
1929 int err = -EINVAL;
297e0dad 1930 int ll;
65adfa91
MT		 1931 mutex_lock(&qp->mutex);
1932
1933 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1934 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1935
297e0dad
MS		 1936 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1937 ll = IB_LINK_LAYER_UNSPECIFIED;
1938 } else {
1939 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1940 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
1941 }
dd5f03be
MB		 1942
1943 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 1944 attr_mask, ll)) {
b1d8eb5a
JM		 1945 pr_debug("qpn 0x%x: invalid attribute mask specified "
1946 "for transition %d to %d. qp_type %d,"
1947 " attr_mask 0x%x\n",
1948 ibqp->qp_num, cur_state, new_state,
1949 ibqp->qp_type, attr_mask);
65adfa91 1950 goto out;
b1d8eb5a 1951 }
65adfa91 1952
c6215745
MS		 1953 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
1954 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
1955 if ((ibqp->qp_type == IB_QPT_RC) ||
1956 (ibqp->qp_type == IB_QPT_UD) ||
1957 (ibqp->qp_type == IB_QPT_UC) ||
1958 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
1959 (ibqp->qp_type == IB_QPT_XRC_INI)) {
1960 attr->port_num = mlx4_ib_bond_next_port(dev);
1961 }
1962 } else {
1963 /* no sense in changing port_num
1964 * when ports are bonded */
1965 attr_mask &= ~IB_QP_PORT;
1966 }
1967 }
1968
65adfa91 1969 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 1970 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 1971 pr_debug("qpn 0x%x: invalid port number (%d) specified "
1972 "for transition %d to %d. qp_type %d\n",
1973 ibqp->qp_num, attr->port_num, cur_state,
1974 new_state, ibqp->qp_type);
65adfa91
MT		 1975 goto out;
1976 }
1977
3987a2d3
OG		 1978 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1979 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1980 IB_LINK_LAYER_ETHERNET))
1981 goto out;
1982
5ae2a7a8
RD		 1983 if (attr_mask & IB_QP_PKEY_INDEX) {
1984 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 1985 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
1986 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
1987 "for transition %d to %d. qp_type %d\n",
1988 ibqp->qp_num, attr->pkey_index, cur_state,
1989 new_state, ibqp->qp_type);
5ae2a7a8 1990 goto out;
b1d8eb5a 1991 }
5ae2a7a8
RD		 1992 }
1993
65adfa91
MT		 1994 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1995 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 1996 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
1997 "Transition %d to %d. qp_type %d\n",
1998 ibqp->qp_num, attr->max_rd_atomic, cur_state,
1999 new_state, ibqp->qp_type);
65adfa91
MT		 2000 goto out;
2001 }
2002
2003 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2004 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2005 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2006 "Transition %d to %d. qp_type %d\n",
2007 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2008 new_state, ibqp->qp_type);
65adfa91
MT		 2009 goto out;
2010 }
2011
2012 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2013 err = 0;
2014 goto out;
2015 }
2016
65adfa91
MT		 2017 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2018
c6215745
MS		 2019 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2020 attr->port_num = 1;
2021
65adfa91
MT		 2022out:
2023 mutex_unlock(&qp->mutex);
2024 return err;
2025}
2026
99ec41d0
JM		 2027static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2028{
2029 int i;
2030 for (i = 0; i < dev->caps.num_ports; i++) {
2031 if (qpn == dev->caps.qp0_proxy[i] ||
2032 qpn == dev->caps.qp0_tunnel[i]) {
2033 *qkey = dev->caps.qp0_qkey[i];
2034 return 0;
2035 }
2036 }
2037 return -EINVAL;
2038}
2039
1ffeb2eb
JM		 2040static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2041 struct ib_send_wr *wr,
2042 void *wqe, unsigned *mlx_seg_len)
2043{
2044 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2045 struct ib_device *ib_dev = &mdev->ib_dev;
2046 struct mlx4_wqe_mlx_seg *mlx = wqe;
2047 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2048 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2049 u16 pkey;
2050 u32 qkey;
2051 int send_size;
2052 int header_size;
2053 int spc;
2054 int i;
2055
2056 if (wr->opcode != IB_WR_SEND)
2057 return -EINVAL;
2058
2059 send_size = 0;
2060
2061 for (i = 0; i < wr->num_sge; ++i)
2062 send_size += wr->sg_list[i].length;
2063
2064 /* for proxy-qp0 sends, need to add in size of tunnel header */
2065 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2066 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2067 send_size += sizeof (struct mlx4_ib_tunnel_header);
2068
2069 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
2070
2071 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2072 sqp->ud_header.lrh.service_level =
2073 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2074 sqp->ud_header.lrh.destination_lid =
2075 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2076 sqp->ud_header.lrh.source_lid =
2077 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2078 }
2079
2080 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2081
2082 /* force loopback */
2083 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2084 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2085
2086 sqp->ud_header.lrh.virtual_lane = 0;
2087 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2088 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2089 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2090 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2091 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2092 else
2093 sqp->ud_header.bth.destination_qpn =
47605df9 2094 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 2095
2096 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2097 if (mlx4_is_master(mdev->dev)) {
2098 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2099 return -EINVAL;
2100 } else {
2101 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2102 return -EINVAL;
2103 }
1ffeb2eb
JM		 2104 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2105 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2106
2107 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2108 sqp->ud_header.immediate_present = 0;
2109
2110 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2111
2112 /*
2113 * Inline data segments may not cross a 64 byte boundary. If
2114 * our UD header is bigger than the space available up to the
2115 * next 64 byte boundary in the WQE, use two inline data
2116 * segments to hold the UD header.
2117 */
2118 spc = MLX4_INLINE_ALIGN -
2119 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2120 if (header_size <= spc) {
2121 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2122 memcpy(inl + 1, sqp->header_buf, header_size);
2123 i = 1;
2124 } else {
2125 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2126 memcpy(inl + 1, sqp->header_buf, spc);
2127
2128 inl = (void *) (inl + 1) + spc;
2129 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2130 /*
2131 * Need a barrier here to make sure all the data is
2132 * visible before the byte_count field is set.
2133 * Otherwise the HCA prefetcher could grab the 64-byte
2134 * chunk with this inline segment and get a valid (!=
2135 * 0xffffffff) byte count but stale data, and end up
2136 * generating a packet with bad headers.
2137 *
2138 * The first inline segment's byte_count field doesn't
2139 * need a barrier, because it comes after a
2140 * control/MLX segment and therefore is at an offset
2141 * of 16 mod 64.
2142 */
2143 wmb();
2144 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2145 i = 2;
2146 }
2147
2148 *mlx_seg_len =
2149 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2150 return 0;
2151}
2152
3e0629cb
JM		 2153static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2154{
2155 int i;
2156
2157 for (i = ETH_ALEN; i; i--) {
2158 dst_mac[i - 1] = src_mac & 0xff;
2159 src_mac >>= 8;
2160 }
2161}
2162
225c7b1f 2163static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
f438000f 2164 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2165{
a478868a 2166 struct ib_device *ib_dev = sqp->qp.ibqp.device;
225c7b1f 2167 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2168 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f
RD		 2169 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2170 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
4c3eb3ca 2171 union ib_gid sgid;
225c7b1f
RD		 2172 u16 pkey;
2173 int send_size;
2174 int header_size;
e61ef241 2175 int spc;
225c7b1f 2176 int i;
1ffeb2eb 2177 int err = 0;
57d88cff 2178 u16 vlan = 0xffff;
a29bec12
RD		 2179 bool is_eth;
2180 bool is_vlan = false;
2181 bool is_grh;
225c7b1f
RD		 2182
2183 send_size = 0;
2184 for (i = 0; i < wr->num_sge; ++i)
2185 send_size += wr->sg_list[i].length;
2186
fa417f7b
EC		 2187 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2188 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 2189 if (is_eth) {
1ffeb2eb
JM		 2190 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2191 /* When multi-function is enabled, the ib_core gid
2192 * indexes don't necessarily match the hw ones, so
2193 * we must use our own cache */
6ee51a4e
JM		 2194 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2195 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2196 ah->av.ib.gid_index, &sgid.raw[0]);
2197 if (err)
2198 return err;
1ffeb2eb
JM		 2199 } else {
2200 err = ib_get_cached_gid(ib_dev,
2201 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2202 ah->av.ib.gid_index, &sgid);
2203 if (err)
2204 return err;
2205 }
2206
0e9855db 2207 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 2208 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2209 is_vlan = 1;
2210 }
4c3eb3ca
EC		 2211 }
2212 ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
fa417f7b
EC		 2213
2214 if (!is_eth) {
2215 sqp->ud_header.lrh.service_level =
2216 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2217 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2218 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2219 }
225c7b1f 2220
fa417f7b 2221 if (is_grh) {
225c7b1f 2222 sqp->ud_header.grh.traffic_class =
fa417f7b 2223 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 2224 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 2225 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2226 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
6ee51a4e
JM		 2227 if (is_eth)
2228 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2229 else {
1ffeb2eb
JM		 2230 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2231 /* When multi-function is enabled, the ib_core gid
2232 * indexes don't necessarily match the hw ones, so
2233 * we must use our own cache */
2234 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2235 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2236 subnet_prefix;
2237 sqp->ud_header.grh.source_gid.global.interface_id =
2238 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2239 guid_cache[ah->av.ib.gid_index];
2240 } else
2241 ib_get_cached_gid(ib_dev,
2242 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2243 ah->av.ib.gid_index,
2244 &sqp->ud_header.grh.source_gid);
6ee51a4e 2245 }
225c7b1f 2246 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 2247 ah->av.ib.dgid, 16);
225c7b1f
RD		 2248 }
2249
2250 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 2251
2252 if (!is_eth) {
2253 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2254 (sqp->ud_header.lrh.destination_lid ==
2255 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2256 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 2257 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2258 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 2259 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2260 }
225c7b1f
RD		 2261
2262 switch (wr->opcode) {
2263 case IB_WR_SEND:
2264 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2265 sqp->ud_header.immediate_present = 0;
2266 break;
2267 case IB_WR_SEND_WITH_IMM:
2268 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2269 sqp->ud_header.immediate_present = 1;
0f39cf3d 2270 sqp->ud_header.immediate_data = wr->ex.imm_data;
225c7b1f
RD		 2271 break;
2272 default:
2273 return -EINVAL;
2274 }
2275
fa417f7b 2276 if (is_eth) {
6ee51a4e
JM		 2277 struct in6_addr in6;
2278
c0c1d3d7
OD		 2279 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2280
2281 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b
EC		 2282
2283 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2284 /* FIXME: cache smac value? */
6ee51a4e
JM		 2285 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2286 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2287 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 2288
3e0629cb
JM		 2289 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2290 u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2291 u8 smac[ETH_ALEN];
2292
2293 mlx4_u64_to_smac(smac, mac);
2294 memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2295 } else {
2296 /* use the src mac of the tunnel */
2297 memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2298 }
2299
fa417f7b
EC		 2300 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2301 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca
EC		 2302 if (!is_vlan) {
2303 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2304 } else {
4c3eb3ca 2305 sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
4c3eb3ca
EC		 2306 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2307 }
fa417f7b
EC		 2308 } else {
2309 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
2310 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2311 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2312 }
225c7b1f
RD		 2313 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2314 if (!sqp->qp.ibqp.qp_num)
2315 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2316 else
2317 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
2318 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2319 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2320 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2321 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
2322 sqp->qkey : wr->wr.ud.remote_qkey);
2323 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2324
2325 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2326
2327 if (0) {
987c8f8f 2328 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 2329 for (i = 0; i < header_size / 4; ++i) {
2330 if (i % 8 == 0)
987c8f8f
SP		 2331 pr_err(" [%02x] ", i * 4);
2332 pr_cont(" %08x",
2333 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 2334 if ((i + 1) % 8 == 0)
987c8f8f 2335 pr_cont("\n");
225c7b1f 2336 }
987c8f8f 2337 pr_err("\n");
225c7b1f
RD		 2338 }
2339
e61ef241
RD		 2340 /*
2341 * Inline data segments may not cross a 64 byte boundary. If
2342 * our UD header is bigger than the space available up to the
2343 * next 64 byte boundary in the WQE, use two inline data
2344 * segments to hold the UD header.
2345 */
2346 spc = MLX4_INLINE_ALIGN -
2347 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2348 if (header_size <= spc) {
2349 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2350 memcpy(inl + 1, sqp->header_buf, header_size);
2351 i = 1;
2352 } else {
2353 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2354 memcpy(inl + 1, sqp->header_buf, spc);
2355
2356 inl = (void *) (inl + 1) + spc;
2357 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2358 /*
2359 * Need a barrier here to make sure all the data is
2360 * visible before the byte_count field is set.
2361 * Otherwise the HCA prefetcher could grab the 64-byte
2362 * chunk with this inline segment and get a valid (!=
2363 * 0xffffffff) byte count but stale data, and end up
2364 * generating a packet with bad headers.
2365 *
2366 * The first inline segment's byte_count field doesn't
2367 * need a barrier, because it comes after a
2368 * control/MLX segment and therefore is at an offset
2369 * of 16 mod 64.
2370 */
2371 wmb();
2372 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2373 i = 2;
2374 }
225c7b1f 2375
f438000f
RD		 2376 *mlx_seg_len =
2377 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2378 return 0;
225c7b1f
RD		 2379}
2380
2381static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2382{
2383 unsigned cur;
2384 struct mlx4_ib_cq *cq;
2385
2386 cur = wq->head - wq->tail;
0e6e7416 2387 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 2388 return 0;
2389
2390 cq = to_mcq(ib_cq);
2391 spin_lock(&cq->lock);
2392 cur = wq->head - wq->tail;
2393 spin_unlock(&cq->lock);
2394
0e6e7416 2395 return cur + nreq >= wq->max_post;
225c7b1f
RD		 2396}
2397
95d04f07
RD		 2398static __be32 convert_access(int acc)
2399{
6ff63e19
SM		 2400 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2401 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2402 (acc & IB_ACCESS_REMOTE_WRITE ?
2403 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2404 (acc & IB_ACCESS_REMOTE_READ ?
2405 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 2406 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2407 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2408}
2409
2410static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
2411{
2412 struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
29bdc883
VS		 2413 int i;
2414
2415 for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2b6b7d4b 2416 mfrpl->mapped_page_list[i] =
29bdc883
VS		 2417 cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
2418 MLX4_MTT_FLAG_PRESENT);
95d04f07
RD		 2419
2420 fseg->flags = convert_access(wr->wr.fast_reg.access_flags);
2421 fseg->mem_key = cpu_to_be32(wr->wr.fast_reg.rkey);
2422 fseg->buf_list = cpu_to_be64(mfrpl->map);
2423 fseg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
2424 fseg->reg_len = cpu_to_be64(wr->wr.fast_reg.length);
2425 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2426 fseg->page_size = cpu_to_be32(wr->wr.fast_reg.page_shift);
2427 fseg->reserved[0] = 0;
2428 fseg->reserved[1] = 0;
2429}
2430
6ff63e19
SM		 2431static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr)
2432{
2433 bseg->flags1 =
2434 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) &
2435 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ |
2436 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2437 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2438 bseg->flags2 = 0;
2439 if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2)
2440 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2441 if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED)
2442 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2443 bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey);
2444 bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey);
2445 bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr);
2446 bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length);
2447}
2448
95d04f07
RD		 2449static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2450{
aee38fad
SM		 2451 memset(iseg, 0, sizeof(*iseg));
2452 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 2453}
2454
0fbfa6a9
RD		 2455static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2456 u64 remote_addr, u32 rkey)
2457{
2458 rseg->raddr = cpu_to_be64(remote_addr);
2459 rseg->rkey = cpu_to_be32(rkey);
2460 rseg->reserved = 0;
2461}
2462
2463static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2464{
2465 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2466 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2467 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
6fa8f719
VS		 2468 } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2469 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2470 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add_mask);
0fbfa6a9
RD		 2471 } else {
2472 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2473 aseg->compare = 0;
2474 }
2475
2476}
2477
6fa8f719
VS		 2478static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2479 struct ib_send_wr *wr)
2480{
2481 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2482 aseg->swap_add_mask = cpu_to_be64(wr->wr.atomic.swap_mask);
2483 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
2484 aseg->compare_mask = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2485}
2486
0fbfa6a9 2487static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
80a2dcd8 2488 struct ib_send_wr *wr)
0fbfa6a9
RD		 2489{
2490 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2491 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2492 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
fa417f7b
EC		 2493 dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2494 memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
0fbfa6a9
RD		 2495}
2496
1ffeb2eb
JM		 2497static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2498 struct mlx4_wqe_datagram_seg *dseg,
97982f5a
JM		 2499 struct ib_send_wr *wr,
2500 enum mlx4_ib_qp_type qpt)
1ffeb2eb
JM		 2501{
2502 union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2503 struct mlx4_av sqp_av = {0};
2504 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2505
2506 /* force loopback */
2507 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2508 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2509 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2510 cpu_to_be32(0xf0000000);
2511
2512 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a
JM		 2513 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2514 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2515 else
2516 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
47605df9
JM		 2517 /* Use QKEY from the QP context, which is set by master */
2518 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 2519}
2520
2521static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2522{
2523 struct mlx4_wqe_inline_seg *inl = wqe;
2524 struct mlx4_ib_tunnel_header hdr;
2525 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2526 int spc;
2527 int i;
2528
2529 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2530 hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2531 hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2532 hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
5ea8bbfc
JM		 2533 memcpy(hdr.mac, ah->av.eth.mac, 6);
2534 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 2535
2536 spc = MLX4_INLINE_ALIGN -
2537 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2538 if (sizeof (hdr) <= spc) {
2539 memcpy(inl + 1, &hdr, sizeof (hdr));
2540 wmb();
2541 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2542 i = 1;
2543 } else {
2544 memcpy(inl + 1, &hdr, spc);
2545 wmb();
2546 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2547
2548 inl = (void *) (inl + 1) + spc;
2549 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2550 wmb();
2551 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2552 i = 2;
2553 }
2554
2555 *mlx_seg_len =
2556 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2557}
2558
6e694ea3
JM		 2559static void set_mlx_icrc_seg(void *dseg)
2560{
2561 u32 *t = dseg;
2562 struct mlx4_wqe_inline_seg *iseg = dseg;
2563
2564 t[1] = 0;
2565
2566 /*
2567 * Need a barrier here before writing the byte_count field to
2568 * make sure that all the data is visible before the
2569 * byte_count field is set. Otherwise, if the segment begins
2570 * a new cacheline, the HCA prefetcher could grab the 64-byte
2571 * chunk and get a valid (!= * 0xffffffff) byte count but
2572 * stale data, and end up sending the wrong data.
2573 */
2574 wmb();
2575
2576 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2577}
2578
2579static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 2580{
d420d9e3
RD		 2581 dseg->lkey = cpu_to_be32(sg->lkey);
2582 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 2583
2584 /*
2585 * Need a barrier here before writing the byte_count field to
2586 * make sure that all the data is visible before the
2587 * byte_count field is set. Otherwise, if the segment begins
2588 * a new cacheline, the HCA prefetcher could grab the 64-byte
2589 * chunk and get a valid (!= * 0xffffffff) byte count but
2590 * stale data, and end up sending the wrong data.
2591 */
2592 wmb();
2593
2594 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 2595}
2596
2242fa4f
RD		 2597static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2598{
2599 dseg->byte_count = cpu_to_be32(sg->length);
2600 dseg->lkey = cpu_to_be32(sg->lkey);
2601 dseg->addr = cpu_to_be64(sg->addr);
2602}
2603
47b37475 2604static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
0fd7e1d8 2605 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 2606 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e
EC		 2607{
2608 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2609
417608c2
EC		 2610 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2611 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 2612
2613 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2614 wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2615 return -EINVAL;
2616
2617 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2618
ca9b590c 2619 *lso_hdr_sz = cpu_to_be32(wr->wr.ud.mss << 16 | wr->wr.ud.hlen);
b832be1e
EC		 2620 *lso_seg_len = halign;
2621 return 0;
2622}
2623
95d04f07
RD		 2624static __be32 send_ieth(struct ib_send_wr *wr)
2625{
2626 switch (wr->opcode) {
2627 case IB_WR_SEND_WITH_IMM:
2628 case IB_WR_RDMA_WRITE_WITH_IMM:
2629 return wr->ex.imm_data;
2630
2631 case IB_WR_SEND_WITH_INV:
2632 return cpu_to_be32(wr->ex.invalidate_rkey);
2633
2634 default:
2635 return 0;
2636 }
2637}
2638
1ffeb2eb
JM		 2639static void add_zero_len_inline(void *wqe)
2640{
2641 struct mlx4_wqe_inline_seg *inl = wqe;
2642 memset(wqe, 0, 16);
2643 inl->byte_count = cpu_to_be32(1 << 31);
2644}
2645
225c7b1f
RD		 2646int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2647 struct ib_send_wr **bad_wr)
2648{
2649 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2650 void *wqe;
2651 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 2652 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 2653 unsigned long flags;
2654 int nreq;
2655 int err = 0;
ea54b10c
JM		 2656 unsigned ind;
2657 int uninitialized_var(stamp);
2658 int uninitialized_var(size);
a3d8e159 2659 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 2660 __be32 dummy;
2661 __be32 *lso_wqe;
2662 __be32 uninitialized_var(lso_hdr_sz);
417608c2 2663 __be32 blh;
225c7b1f 2664 int i;
35f05dab 2665 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 2666
96db0e03 2667 spin_lock_irqsave(&qp->sq.lock, flags);
35f05dab
YH		 2668 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2669 err = -EIO;
2670 *bad_wr = wr;
2671 nreq = 0;
2672 goto out;
2673 }
225c7b1f 2674
ea54b10c 2675 ind = qp->sq_next_wqe;
225c7b1f
RD		 2676
2677 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 2678 lso_wqe = &dummy;
417608c2 2679 blh = 0;
0fd7e1d8 2680
225c7b1f
RD		 2681 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2682 err = -ENOMEM;
2683 *bad_wr = wr;
2684 goto out;
2685 }
2686
2687 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2688 err = -EINVAL;
2689 *bad_wr = wr;
2690 goto out;
2691 }
2692
0e6e7416 2693 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 2694 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 2695
2696 ctrl->srcrb_flags =
2697 (wr->send_flags & IB_SEND_SIGNALED ?
2698 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2699 (wr->send_flags & IB_SEND_SOLICITED ?
2700 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 2701 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2702 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2703 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 2704 qp->sq_signal_bits;
2705
95d04f07 2706 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 2707
2708 wqe += sizeof *ctrl;
2709 size = sizeof *ctrl / 16;
2710
1ffeb2eb
JM		 2711 switch (qp->mlx4_ib_qp_type) {
2712 case MLX4_IB_QPT_RC:
2713 case MLX4_IB_QPT_UC:
225c7b1f
RD		 2714 switch (wr->opcode) {
2715 case IB_WR_ATOMIC_CMP_AND_SWP:
2716 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 2717 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
0fbfa6a9
RD		 2718 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2719 wr->wr.atomic.rkey);
225c7b1f
RD		 2720 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2721
0fbfa6a9 2722 set_atomic_seg(wqe, wr);
225c7b1f 2723 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 2724
225c7b1f
RD		 2725 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2726 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 2727
2728 break;
2729
2730 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2731 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2732 wr->wr.atomic.rkey);
2733 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2734
2735 set_masked_atomic_seg(wqe, wr);
2736 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
2737
2738 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2739 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 2740
2741 break;
2742
2743 case IB_WR_RDMA_READ:
2744 case IB_WR_RDMA_WRITE:
2745 case IB_WR_RDMA_WRITE_WITH_IMM:
0fbfa6a9
RD		 2746 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2747 wr->wr.rdma.rkey);
225c7b1f
RD		 2748 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2749 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 2750 break;
95d04f07
RD		 2751
2752 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 2753 ctrl->srcrb_flags |=
2754 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2755 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2756 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
2757 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2758 break;
2759
2760 case IB_WR_FAST_REG_MR:
2ac6bf4d
JM		 2761 ctrl->srcrb_flags |=
2762 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2763 set_fmr_seg(wqe, wr);
2764 wqe += sizeof (struct mlx4_wqe_fmr_seg);
2765 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2766 break;
225c7b1f 2767
6ff63e19
SM		 2768 case IB_WR_BIND_MW:
2769 ctrl->srcrb_flags |=
2770 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2771 set_bind_seg(wqe, wr);
2772 wqe += sizeof(struct mlx4_wqe_bind_seg);
2773 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2774 break;
225c7b1f
RD		 2775 default:
2776 /* No extra segments required for sends */
2777 break;
2778 }
2779 break;
2780
1ffeb2eb
JM		 2781 case MLX4_IB_QPT_TUN_SMI_OWNER:
2782 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2783 if (unlikely(err)) {
2784 *bad_wr = wr;
2785 goto out;
2786 }
2787 wqe += seglen;
2788 size += seglen / 16;
2789 break;
2790 case MLX4_IB_QPT_TUN_SMI:
2791 case MLX4_IB_QPT_TUN_GSI:
2792 /* this is a UD qp used in MAD responses to slaves. */
2793 set_datagram_seg(wqe, wr);
2794 /* set the forced-loopback bit in the data seg av */
2795 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2796 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2797 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2798 break;
2799 case MLX4_IB_QPT_UD:
80a2dcd8 2800 set_datagram_seg(wqe, wr);
225c7b1f
RD		 2801 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2802 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 2803
2804 if (wr->opcode == IB_WR_LSO) {
417608c2 2805 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
b832be1e
EC		 2806 if (unlikely(err)) {
2807 *bad_wr = wr;
2808 goto out;
2809 }
0fd7e1d8 2810 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 2811 wqe += seglen;
2812 size += seglen / 16;
2813 }
225c7b1f
RD		 2814 break;
2815
1ffeb2eb 2816 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1ffeb2eb
JM		 2817 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2818 if (unlikely(err)) {
2819 *bad_wr = wr;
2820 goto out;
2821 }
2822 wqe += seglen;
2823 size += seglen / 16;
2824 /* to start tunnel header on a cache-line boundary */
2825 add_zero_len_inline(wqe);
2826 wqe += 16;
2827 size++;
2828 build_tunnel_header(wr, wqe, &seglen);
2829 wqe += seglen;
2830 size += seglen / 16;
2831 break;
2832 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 2833 case MLX4_IB_QPT_PROXY_GSI:
2834 /* If we are tunneling special qps, this is a UD qp.
2835 * In this case we first add a UD segment targeting
2836 * the tunnel qp, and then add a header with address
2837 * information */
97982f5a
JM		 2838 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr,
2839 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 2840 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2841 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2842 build_tunnel_header(wr, wqe, &seglen);
2843 wqe += seglen;
2844 size += seglen / 16;
2845 break;
2846
2847 case MLX4_IB_QPT_SMI:
2848 case MLX4_IB_QPT_GSI:
f438000f
RD		 2849 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2850 if (unlikely(err)) {
225c7b1f
RD		 2851 *bad_wr = wr;
2852 goto out;
2853 }
f438000f
RD		 2854 wqe += seglen;
2855 size += seglen / 16;
225c7b1f
RD		 2856 break;
2857
2858 default:
2859 break;
2860 }
2861
6e694ea3
JM		 2862 /*
2863 * Write data segments in reverse order, so as to
2864 * overwrite cacheline stamp last within each
2865 * cacheline. This avoids issues with WQE
2866 * prefetching.
2867 */
225c7b1f 2868
6e694ea3
JM		 2869 dseg = wqe;
2870 dseg += wr->num_sge - 1;
2871 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 2872
2873 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 2874 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2875 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2876 qp->mlx4_ib_qp_type &
2877 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 2878 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 2879 size += sizeof (struct mlx4_wqe_data_seg) / 16;
2880 }
2881
6e694ea3
JM		 2882 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2883 set_data_seg(dseg, wr->sg_list + i);
2884
0fd7e1d8
RD		 2885 /*
2886 * Possibly overwrite stamping in cacheline with LSO
2887 * segment only after making sure all data segments
2888 * are written.
2889 */
2890 wmb();
2891 *lso_wqe = lso_hdr_sz;
2892
225c7b1f
RD		 2893 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2894 MLX4_WQE_CTRL_FENCE : 0) | size;
2895
2896 /*
2897 * Make sure descriptor is fully written before
2898 * setting ownership bit (because HW can start
2899 * executing as soon as we do).
2900 */
2901 wmb();
2902
59b0ed12 2903 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 2904 *bad_wr = wr;
225c7b1f
RD		 2905 err = -EINVAL;
2906 goto out;
2907 }
2908
2909 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 2910 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 2911
ea54b10c
JM		 2912 stamp = ind + qp->sq_spare_wqes;
2913 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2914
0e6e7416
RD		 2915 /*
2916 * We can improve latency by not stamping the last
2917 * send queue WQE until after ringing the doorbell, so
2918 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 2919 *
2920 * Same optimization applies to padding with NOP wqe
2921 * in case of WQE shrinking (used to prevent wrap-around
2922 * in the middle of WR).
0e6e7416 2923 */
ea54b10c
JM		 2924 if (wr->next) {
2925 stamp_send_wqe(qp, stamp, size * 16);
2926 ind = pad_wraparound(qp, ind);
2927 }
225c7b1f
RD		 2928 }
2929
2930out:
2931 if (likely(nreq)) {
2932 qp->sq.head += nreq;
2933
2934 /*
2935 * Make sure that descriptors are written before
2936 * doorbell record.
2937 */
2938 wmb();
2939
2940 writel(qp->doorbell_qpn,
2941 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
2942
2943 /*
2944 * Make sure doorbells don't leak out of SQ spinlock
2945 * and reach the HCA out of order.
2946 */
2947 mmiowb();
0e6e7416 2948
ea54b10c
JM		 2949 stamp_send_wqe(qp, stamp, size * 16);
2950
2951 ind = pad_wraparound(qp, ind);
2952 qp->sq_next_wqe = ind;
225c7b1f
RD		 2953 }
2954
96db0e03 2955 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 2956
2957 return err;
2958}
2959
2960int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2961 struct ib_recv_wr **bad_wr)
2962{
2963 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2964 struct mlx4_wqe_data_seg *scat;
2965 unsigned long flags;
2966 int err = 0;
2967 int nreq;
2968 int ind;
1ffeb2eb 2969 int max_gs;
225c7b1f 2970 int i;
35f05dab 2971 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 2972
1ffeb2eb 2973 max_gs = qp->rq.max_gs;
225c7b1f
RD		 2974 spin_lock_irqsave(&qp->rq.lock, flags);
2975
35f05dab
YH		 2976 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2977 err = -EIO;
2978 *bad_wr = wr;
2979 nreq = 0;
2980 goto out;
2981 }
2982
0e6e7416 2983 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 2984
2985 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 2986 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 2987 err = -ENOMEM;
2988 *bad_wr = wr;
2989 goto out;
2990 }
2991
2992 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2993 err = -EINVAL;
2994 *bad_wr = wr;
2995 goto out;
2996 }
2997
2998 scat = get_recv_wqe(qp, ind);
2999
1ffeb2eb
JM		 3000 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3001 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3002 ib_dma_sync_single_for_device(ibqp->device,
3003 qp->sqp_proxy_rcv[ind].map,
3004 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3005 DMA_FROM_DEVICE);
3006 scat->byte_count =
3007 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3008 /* use dma lkey from upper layer entry */
3009 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3010 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3011 scat++;
3012 max_gs--;
3013 }
3014
2242fa4f
RD		 3015 for (i = 0; i < wr->num_sge; ++i)
3016 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3017
1ffeb2eb 3018 if (i < max_gs) {
225c7b1f
RD		 3019 scat[i].byte_count = 0;
3020 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3021 scat[i].addr = 0;
3022 }
3023
3024 qp->rq.wrid[ind] = wr->wr_id;
3025
0e6e7416 3026 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3027 }
3028
3029out:
3030 if (likely(nreq)) {
3031 qp->rq.head += nreq;
3032
3033 /*
3034 * Make sure that descriptors are written before
3035 * doorbell record.
3036 */
3037 wmb();
3038
3039 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3040 }
3041
3042 spin_unlock_irqrestore(&qp->rq.lock, flags);
3043
3044 return err;
3045}
6a775e2b
JM		 3046
3047static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3048{
3049 switch (mlx4_state) {
3050 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3051 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3052 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3053 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3054 case MLX4_QP_STATE_SQ_DRAINING:
3055 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3056 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3057 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3058 default: return -1;
3059 }
3060}
3061
3062static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3063{
3064 switch (mlx4_mig_state) {
3065 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3066 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3067 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3068 default: return -1;
3069 }
3070}
3071
3072static int to_ib_qp_access_flags(int mlx4_flags)
3073{
3074 int ib_flags = 0;
3075
3076 if (mlx4_flags & MLX4_QP_BIT_RRE)
3077 ib_flags |= IB_ACCESS_REMOTE_READ;
3078 if (mlx4_flags & MLX4_QP_BIT_RWE)
3079 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3080 if (mlx4_flags & MLX4_QP_BIT_RAE)
3081 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3082
3083 return ib_flags;
3084}
3085
4c3eb3ca 3086static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
6a775e2b
JM		 3087 struct mlx4_qp_path *path)
3088{
4c3eb3ca
EC		 3089 struct mlx4_dev *dev = ibdev->dev;
3090 int is_eth;
3091
8fcea95a 3092 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 3093 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
3094
3095 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3096 return;
3097
4c3eb3ca
EC		 3098 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3099 IB_LINK_LAYER_ETHERNET;
3100 if (is_eth)
3101 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3102 ((path->sched_queue & 4) << 1);
3103 else
3104 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3105
6a775e2b 3106 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
6a775e2b
JM		 3107 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3108 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3109 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3110 if (ib_ah_attr->ah_flags) {
3111 ib_ah_attr->grh.sgid_index = path->mgid_index;
3112 ib_ah_attr->grh.hop_limit = path->hop_limit;
3113 ib_ah_attr->grh.traffic_class =
3114 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3115 ib_ah_attr->grh.flow_label =
586bb586 3116 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 3117 memcpy(ib_ah_attr->grh.dgid.raw,
3118 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3119 }
3120}
3121
3122int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3123 struct ib_qp_init_attr *qp_init_attr)
3124{
3125 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3126 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3127 struct mlx4_qp_context context;
3128 int mlx4_state;
0df67030
DB		 3129 int err = 0;
3130
3131 mutex_lock(&qp->mutex);
6a775e2b
JM		 3132
3133 if (qp->state == IB_QPS_RESET) {
3134 qp_attr->qp_state = IB_QPS_RESET;
3135 goto done;
3136 }
3137
3138 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3139 if (err) {
3140 err = -EINVAL;
3141 goto out;
3142 }
6a775e2b
JM		 3143
3144 mlx4_state = be32_to_cpu(context.flags) >> 28;
3145
0df67030
DB		 3146 qp->state = to_ib_qp_state(mlx4_state);
3147 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3148 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3149 qp_attr->path_mig_state =
3150 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3151 qp_attr->qkey = be32_to_cpu(context.qkey);
3152 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3153 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3154 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3155 qp_attr->qp_access_flags =
3156 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3157
3158 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4c3eb3ca
EC		 3159 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3160 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b
JM		 3161 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3162 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3163 }
3164
3165 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 3166 if (qp_attr->qp_state == IB_QPS_INIT)
3167 qp_attr->port_num = qp->port;
3168 else
3169 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 3170
3171 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3172 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3173
3174 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3175
3176 qp_attr->max_dest_rd_atomic =
3177 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3178 qp_attr->min_rnr_timer =
3179 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3180 qp_attr->timeout = context.pri_path.ackto >> 3;
3181 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3182 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3183 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3184
3185done:
3186 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 3187 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3188 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3189
6a775e2b 3190 if (!ibqp->uobject) {
7f5eb9bb
RD		 3191 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3192 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3193 } else {
3194 qp_attr->cap.max_send_wr = 0;
3195 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 3196 }
3197
7f5eb9bb
RD		 3198 /*
3199 * We don't support inline sends for kernel QPs (yet), and we
3200 * don't know what userspace's value should be.
3201 */
3202 qp_attr->cap.max_inline_data = 0;
3203
3204 qp_init_attr->cap = qp_attr->cap;
3205
521e575b
RL		 3206 qp_init_attr->create_flags = 0;
3207 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3208 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3209
3210 if (qp->flags & MLX4_IB_QP_LSO)
3211 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3212
c1c98501
MB		 3213 if (qp->flags & MLX4_IB_QP_NETIF)
3214 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3215
46db567d
DB		 3216 qp_init_attr->sq_sig_type =
3217 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3218 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3219
0df67030
DB		 3220out:
3221 mutex_unlock(&qp->mutex);
3222 return err;
6a775e2b
JM		 3223}
3224
Linux 6.x block layer and io_uring tree(s)