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IB/mthca: Fix max_sge value returned by query_device
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
ea54b10c
JM		 33#include <linux/log2.h>
34
225c7b1f
RD		 35#include <rdma/ib_cache.h>
36#include <rdma/ib_pack.h>
37
38#include <linux/mlx4/qp.h>
39
40#include "mlx4_ib.h"
41#include "user.h"
42
43enum {
44 MLX4_IB_ACK_REQ_FREQ = 8,
45};
46
47enum {
48 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
50};
51
52enum {
53 /*
54 * Largest possible UD header: send with GRH and immediate data.
55 */
56 MLX4_IB_UD_HEADER_SIZE = 72
57};
58
59struct mlx4_ib_sqp {
60 struct mlx4_ib_qp qp;
61 int pkey_index;
62 u32 qkey;
63 u32 send_psn;
64 struct ib_ud_header ud_header;
65 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
66};
67
83904132
JM		 68enum {
69 MLX4_IB_MIN_SQ_STRIDE = 6
70};
71
225c7b1f
RD		 72static const __be32 mlx4_ib_opcode[] = {
73 [IB_WR_SEND] = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
b832be1e 74 [IB_WR_LSO] = __constant_cpu_to_be32(MLX4_OPCODE_LSO),
225c7b1f
RD		 75 [IB_WR_SEND_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
76 [IB_WR_RDMA_WRITE] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
77 [IB_WR_RDMA_WRITE_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
78 [IB_WR_RDMA_READ] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
79 [IB_WR_ATOMIC_CMP_AND_SWP] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
80 [IB_WR_ATOMIC_FETCH_AND_ADD] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
81};
82
83static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
84{
85 return container_of(mqp, struct mlx4_ib_sqp, qp);
86}
87
88static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
89{
90 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
91 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
92}
93
94static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
95{
96 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
97 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
98}
99
100static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
101{
1c69fc2a 102 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 103}
104
105static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
106{
107 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
108}
109
110static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
111{
112 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
113}
114
0e6e7416
RD		 115/*
116 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 117 * first four bytes of every 64 byte chunk with
118 * 0x7FFFFFF | (invalid_ownership_value << 31).
119 *
120 * When the max work request size is less than or equal to the WQE
121 * basic block size, as an optimization, we can stamp all WQEs with
122 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 123 */
ea54b10c 124static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 125{
d2ae16d5 126 __be32 *wqe;
0e6e7416 127 int i;
ea54b10c
JM		 128 int s;
129 int ind;
130 void *buf;
131 __be32 stamp;
132
133 s = roundup(size, 1U << qp->sq.wqe_shift);
134 if (qp->sq_max_wqes_per_wr > 1) {
135 for (i = 0; i < s; i += 64) {
136 ind = (i >> qp->sq.wqe_shift) + n;
137 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
138 cpu_to_be32(0xffffffff);
139 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
140 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
141 *wqe = stamp;
142 }
143 } else {
144 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
145 for (i = 64; i < s; i += 64) {
146 wqe = buf + i;
d2ae16d5 147 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 148 }
149 }
150}
151
152static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
153{
154 struct mlx4_wqe_ctrl_seg *ctrl;
155 struct mlx4_wqe_inline_seg *inl;
156 void *wqe;
157 int s;
158
159 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
160 s = sizeof(struct mlx4_wqe_ctrl_seg);
161
162 if (qp->ibqp.qp_type == IB_QPT_UD) {
163 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
164 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
165 memset(dgram, 0, sizeof *dgram);
166 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
167 s += sizeof(struct mlx4_wqe_datagram_seg);
168 }
169
170 /* Pad the remainder of the WQE with an inline data segment. */
171 if (size > s) {
172 inl = wqe + s;
173 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
174 }
175 ctrl->srcrb_flags = 0;
176 ctrl->fence_size = size / 16;
177 /*
178 * Make sure descriptor is fully written before setting ownership bit
179 * (because HW can start executing as soon as we do).
180 */
181 wmb();
182
183 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
184 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 185
ea54b10c
JM		 186 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
187}
188
189/* Post NOP WQE to prevent wrap-around in the middle of WR */
190static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
191{
192 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
193 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
194 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
195 ind += s;
196 }
197 return ind;
0e6e7416
RD		 198}
199
225c7b1f
RD		 200static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
201{
202 struct ib_event event;
203 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
204
205 if (type == MLX4_EVENT_TYPE_PATH_MIG)
206 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
207
208 if (ibqp->event_handler) {
209 event.device = ibqp->device;
210 event.element.qp = ibqp;
211 switch (type) {
212 case MLX4_EVENT_TYPE_PATH_MIG:
213 event.event = IB_EVENT_PATH_MIG;
214 break;
215 case MLX4_EVENT_TYPE_COMM_EST:
216 event.event = IB_EVENT_COMM_EST;
217 break;
218 case MLX4_EVENT_TYPE_SQ_DRAINED:
219 event.event = IB_EVENT_SQ_DRAINED;
220 break;
221 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
222 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
223 break;
224 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
225 event.event = IB_EVENT_QP_FATAL;
226 break;
227 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
228 event.event = IB_EVENT_PATH_MIG_ERR;
229 break;
230 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
231 event.event = IB_EVENT_QP_REQ_ERR;
232 break;
233 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
234 event.event = IB_EVENT_QP_ACCESS_ERR;
235 break;
236 default:
237 printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
238 "on QP %06x\n", type, qp->qpn);
239 return;
240 }
241
242 ibqp->event_handler(&event, ibqp->qp_context);
243 }
244}
245
b832be1e 246static int send_wqe_overhead(enum ib_qp_type type, u32 flags)
225c7b1f
RD		 247{
248 /*
249 * UD WQEs must have a datagram segment.
250 * RC and UC WQEs might have a remote address segment.
251 * MLX WQEs need two extra inline data segments (for the UD
252 * header and space for the ICRC).
253 */
254 switch (type) {
255 case IB_QPT_UD:
256 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e
EC		 257 sizeof (struct mlx4_wqe_datagram_seg) +
258 ((flags & MLX4_IB_QP_LSO) ? 64 : 0);
225c7b1f
RD		 259 case IB_QPT_UC:
260 return sizeof (struct mlx4_wqe_ctrl_seg) +
261 sizeof (struct mlx4_wqe_raddr_seg);
262 case IB_QPT_RC:
263 return sizeof (struct mlx4_wqe_ctrl_seg) +
264 sizeof (struct mlx4_wqe_atomic_seg) +
265 sizeof (struct mlx4_wqe_raddr_seg);
266 case IB_QPT_SMI:
267 case IB_QPT_GSI:
268 return sizeof (struct mlx4_wqe_ctrl_seg) +
269 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 270 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
271 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 272 sizeof (struct mlx4_wqe_inline_seg),
273 sizeof (struct mlx4_wqe_data_seg)) +
274 ALIGN(4 +
275 sizeof (struct mlx4_wqe_inline_seg),
276 sizeof (struct mlx4_wqe_data_seg));
277 default:
278 return sizeof (struct mlx4_wqe_ctrl_seg);
279 }
280}
281
2446304d 282static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
a4cd7ed8 283 int is_user, int has_srq, struct mlx4_ib_qp *qp)
225c7b1f 284{
2446304d
EC		 285 /* Sanity check RQ size before proceeding */
286 if (cap->max_recv_wr > dev->dev->caps.max_wqes ||
287 cap->max_recv_sge > dev->dev->caps.max_rq_sg)
288 return -EINVAL;
289
a4cd7ed8
RD		 290 if (has_srq) {
291 /* QPs attached to an SRQ should have no RQ */
292 if (cap->max_recv_wr)
293 return -EINVAL;
2446304d 294
0e6e7416 295 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 296 } else {
297 /* HW requires >= 1 RQ entry with >= 1 gather entry */
298 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
299 return -EINVAL;
300
0e6e7416 301 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 302 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 303 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
304 }
2446304d 305
0e6e7416 306 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
2446304d
EC		 307 cap->max_recv_sge = qp->rq.max_gs;
308
309 return 0;
310}
311
312static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
313 enum ib_qp_type type, struct mlx4_ib_qp *qp)
314{
ea54b10c
JM		 315 int s;
316
2446304d 317 /* Sanity check SQ size before proceeding */
225c7b1f 318 if (cap->max_send_wr > dev->dev->caps.max_wqes ||
225c7b1f 319 cap->max_send_sge > dev->dev->caps.max_sq_sg ||
b832be1e 320 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 321 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
322 return -EINVAL;
323
324 /*
325 * For MLX transport we need 2 extra S/G entries:
326 * one for the header and one for the checksum at the end
327 */
328 if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
329 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
330 return -EINVAL;
331
ea54b10c
JM		 332 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
333 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 334 send_wqe_overhead(type, qp->flags);
225c7b1f 335
0e6e7416 336 /*
ea54b10c
JM		 337 * Hermon supports shrinking WQEs, such that a single work
338 * request can include multiple units of 1 << wqe_shift. This
339 * way, work requests can differ in size, and do not have to
340 * be a power of 2 in size, saving memory and speeding up send
341 * WR posting. Unfortunately, if we do this then the
342 * wqe_index field in CQEs can't be used to look up the WR ID
343 * anymore, so we do this only if selective signaling is off.
344 *
345 * Further, on 32-bit platforms, we can't use vmap() to make
346 * the QP buffer virtually contigious. Thus we have to use
347 * constant-sized WRs to make sure a WR is always fully within
348 * a single page-sized chunk.
349 *
350 * Finally, we use NOP work requests to pad the end of the
351 * work queue, to avoid wrap-around in the middle of WR. We
352 * set NEC bit to avoid getting completions with error for
353 * these NOP WRs, but since NEC is only supported starting
354 * with firmware 2.2.232, we use constant-sized WRs for older
355 * firmware.
356 *
357 * And, since MLX QPs only support SEND, we use constant-sized
358 * WRs in this case.
359 *
360 * We look for the smallest value of wqe_shift such that the
361 * resulting number of wqes does not exceed device
362 * capabilities.
363 *
364 * We set WQE size to at least 64 bytes, this way stamping
365 * invalidates each WQE.
0e6e7416 366 */
ea54b10c
JM		 367 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
368 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
369 type != IB_QPT_SMI && type != IB_QPT_GSI)
370 qp->sq.wqe_shift = ilog2(64);
371 else
372 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
373
374 for (;;) {
375 if (1 << qp->sq.wqe_shift > dev->dev->caps.max_sq_desc_sz)
376 return -EINVAL;
377
378 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
379
380 /*
381 * We need to leave 2 KB + 1 WR of headroom in the SQ to
382 * allow HW to prefetch.
383 */
384 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
385 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
386 qp->sq_max_wqes_per_wr +
387 qp->sq_spare_wqes);
388
389 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
390 break;
391
392 if (qp->sq_max_wqes_per_wr <= 1)
393 return -EINVAL;
394
395 ++qp->sq.wqe_shift;
396 }
397
398 qp->sq.max_gs = ((qp->sq_max_wqes_per_wr << qp->sq.wqe_shift) -
b832be1e
EC		 399 send_wqe_overhead(type, qp->flags)) /
400 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 401
402 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
403 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 404 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
405 qp->rq.offset = 0;
0e6e7416 406 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 407 } else {
0e6e7416 408 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 409 qp->sq.offset = 0;
410 }
411
ea54b10c
JM		 412 cap->max_send_wr = qp->sq.max_post =
413 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
0e6e7416 414 cap->max_send_sge = qp->sq.max_gs;
54e95f8d
RD		 415 /* We don't support inline sends for kernel QPs (yet) */
416 cap->max_inline_data = 0;
225c7b1f
RD		 417
418 return 0;
419}
420
83904132
JM		 421static int set_user_sq_size(struct mlx4_ib_dev *dev,
422 struct mlx4_ib_qp *qp,
2446304d
EC		 423 struct mlx4_ib_create_qp *ucmd)
424{
83904132
JM		 425 /* Sanity check SQ size before proceeding */
426 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
427 ucmd->log_sq_stride >
428 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
429 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
430 return -EINVAL;
431
0e6e7416 432 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 433 qp->sq.wqe_shift = ucmd->log_sq_stride;
434
0e6e7416
RD		 435 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
436 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 437
438 return 0;
439}
440
225c7b1f
RD		 441static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
442 struct ib_qp_init_attr *init_attr,
443 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
444{
225c7b1f 445 int err;
225c7b1f
RD		 446
447 mutex_init(&qp->mutex);
448 spin_lock_init(&qp->sq.lock);
449 spin_lock_init(&qp->rq.lock);
450
451 qp->state = IB_QPS_RESET;
452 qp->atomic_rd_en = 0;
453 qp->resp_depth = 0;
454
455 qp->rq.head = 0;
456 qp->rq.tail = 0;
457 qp->sq.head = 0;
458 qp->sq.tail = 0;
ea54b10c
JM		 459 qp->sq_next_wqe = 0;
460
461 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
462 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
463 else
464 qp->sq_signal_bits = 0;
225c7b1f 465
a4cd7ed8 466 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
225c7b1f
RD		 467 if (err)
468 goto err;
469
470 if (pd->uobject) {
471 struct mlx4_ib_create_qp ucmd;
472
473 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
474 err = -EFAULT;
475 goto err;
476 }
477
0e6e7416
RD		 478 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
479
83904132 480 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 481 if (err)
482 goto err;
483
225c7b1f 484 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 485 qp->buf_size, 0, 0);
225c7b1f
RD		 486 if (IS_ERR(qp->umem)) {
487 err = PTR_ERR(qp->umem);
488 goto err;
489 }
490
491 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
492 ilog2(qp->umem->page_size), &qp->mtt);
493 if (err)
494 goto err_buf;
495
496 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
497 if (err)
498 goto err_mtt;
499
02d89b87
RD		 500 if (!init_attr->srq) {
501 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
502 ucmd.db_addr, &qp->db);
503 if (err)
504 goto err_mtt;
505 }
225c7b1f 506 } else {
0e6e7416
RD		 507 qp->sq_no_prefetch = 0;
508
b832be1e
EC		 509 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
510 qp->flags |= MLX4_IB_QP_LSO;
511
2446304d
EC		 512 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
513 if (err)
514 goto err;
515
02d89b87 516 if (!init_attr->srq) {
6296883c 517 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 518 if (err)
519 goto err;
225c7b1f 520
02d89b87
RD		 521 *qp->db.db = 0;
522 }
225c7b1f
RD		 523
524 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
525 err = -ENOMEM;
526 goto err_db;
527 }
528
529 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
530 &qp->mtt);
531 if (err)
532 goto err_buf;
533
534 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
535 if (err)
536 goto err_mtt;
537
0e6e7416
RD		 538 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
539 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
225c7b1f
RD		 540
541 if (!qp->sq.wrid || !qp->rq.wrid) {
542 err = -ENOMEM;
543 goto err_wrid;
544 }
225c7b1f
RD		 545 }
546
547 err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
548 if (err)
549 goto err_wrid;
550
551 /*
552 * Hardware wants QPN written in big-endian order (after
553 * shifting) for send doorbell. Precompute this value to save
554 * a little bit when posting sends.
555 */
556 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
557
225c7b1f
RD		 558 qp->mqp.event = mlx4_ib_qp_event;
559
560 return 0;
561
562err_wrid:
23f1b384
RD		 563 if (pd->uobject) {
564 if (!init_attr->srq)
565 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context),
566 &qp->db);
567 } else {
225c7b1f
RD		 568 kfree(qp->sq.wrid);
569 kfree(qp->rq.wrid);
570 }
571
572err_mtt:
573 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
574
575err_buf:
576 if (pd->uobject)
577 ib_umem_release(qp->umem);
578 else
579 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
580
581err_db:
02d89b87 582 if (!pd->uobject && !init_attr->srq)
6296883c 583 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 584
585err:
586 return err;
587}
588
589static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
590{
591 switch (state) {
592 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
593 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
594 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
595 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
596 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
597 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
598 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
599 default: return -1;
600 }
601}
602
603static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
604{
605 if (send_cq == recv_cq)
606 spin_lock_irq(&send_cq->lock);
607 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
608 spin_lock_irq(&send_cq->lock);
609 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
610 } else {
611 spin_lock_irq(&recv_cq->lock);
612 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
613 }
614}
615
616static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
617{
618 if (send_cq == recv_cq)
619 spin_unlock_irq(&send_cq->lock);
620 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
621 spin_unlock(&recv_cq->lock);
622 spin_unlock_irq(&send_cq->lock);
623 } else {
624 spin_unlock(&send_cq->lock);
625 spin_unlock_irq(&recv_cq->lock);
626 }
627}
628
629static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
630 int is_user)
631{
632 struct mlx4_ib_cq *send_cq, *recv_cq;
633
634 if (qp->state != IB_QPS_RESET)
635 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
636 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
637 printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
638 qp->mqp.qpn);
639
640 send_cq = to_mcq(qp->ibqp.send_cq);
641 recv_cq = to_mcq(qp->ibqp.recv_cq);
642
643 mlx4_ib_lock_cqs(send_cq, recv_cq);
644
645 if (!is_user) {
646 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
647 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
648 if (send_cq != recv_cq)
649 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
650 }
651
652 mlx4_qp_remove(dev->dev, &qp->mqp);
653
654 mlx4_ib_unlock_cqs(send_cq, recv_cq);
655
656 mlx4_qp_free(dev->dev, &qp->mqp);
657 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
658
659 if (is_user) {
02d89b87
RD		 660 if (!qp->ibqp.srq)
661 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
662 &qp->db);
225c7b1f
RD		 663 ib_umem_release(qp->umem);
664 } else {
665 kfree(qp->sq.wrid);
666 kfree(qp->rq.wrid);
667 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
02d89b87 668 if (!qp->ibqp.srq)
6296883c 669 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 670 }
671}
672
673struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
674 struct ib_qp_init_attr *init_attr,
675 struct ib_udata *udata)
676{
677 struct mlx4_ib_dev *dev = to_mdev(pd->device);
678 struct mlx4_ib_sqp *sqp;
679 struct mlx4_ib_qp *qp;
680 int err;
681
b832be1e
EC		 682 /* We only support LSO, and only for kernel UD QPs. */
683 if (init_attr->create_flags & ~IB_QP_CREATE_IPOIB_UD_LSO)
684 return ERR_PTR(-EINVAL);
685 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO &&
686 (pd->uobject || init_attr->qp_type != IB_QPT_UD))
b846f25a
EC		 687 return ERR_PTR(-EINVAL);
688
225c7b1f
RD		 689 switch (init_attr->qp_type) {
690 case IB_QPT_RC:
691 case IB_QPT_UC:
692 case IB_QPT_UD:
693 {
694 qp = kmalloc(sizeof *qp, GFP_KERNEL);
695 if (!qp)
696 return ERR_PTR(-ENOMEM);
697
698 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
699 if (err) {
700 kfree(qp);
701 return ERR_PTR(err);
702 }
703
704 qp->ibqp.qp_num = qp->mqp.qpn;
705
706 break;
707 }
708 case IB_QPT_SMI:
709 case IB_QPT_GSI:
710 {
711 /* Userspace is not allowed to create special QPs: */
712 if (pd->uobject)
713 return ERR_PTR(-EINVAL);
714
715 sqp = kmalloc(sizeof *sqp, GFP_KERNEL);
716 if (!sqp)
717 return ERR_PTR(-ENOMEM);
718
719 qp = &sqp->qp;
720
721 err = create_qp_common(dev, pd, init_attr, udata,
722 dev->dev->caps.sqp_start +
723 (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
724 init_attr->port_num - 1,
725 qp);
726 if (err) {
727 kfree(sqp);
728 return ERR_PTR(err);
729 }
730
731 qp->port = init_attr->port_num;
732 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
733
734 break;
735 }
736 default:
737 /* Don't support raw QPs */
738 return ERR_PTR(-EINVAL);
739 }
740
741 return &qp->ibqp;
742}
743
744int mlx4_ib_destroy_qp(struct ib_qp *qp)
745{
746 struct mlx4_ib_dev *dev = to_mdev(qp->device);
747 struct mlx4_ib_qp *mqp = to_mqp(qp);
748
749 if (is_qp0(dev, mqp))
750 mlx4_CLOSE_PORT(dev->dev, mqp->port);
751
752 destroy_qp_common(dev, mqp, !!qp->pd->uobject);
753
754 if (is_sqp(dev, mqp))
755 kfree(to_msqp(mqp));
756 else
757 kfree(mqp);
758
759 return 0;
760}
761
225c7b1f
RD		 762static int to_mlx4_st(enum ib_qp_type type)
763{
764 switch (type) {
765 case IB_QPT_RC: return MLX4_QP_ST_RC;
766 case IB_QPT_UC: return MLX4_QP_ST_UC;
767 case IB_QPT_UD: return MLX4_QP_ST_UD;
768 case IB_QPT_SMI:
769 case IB_QPT_GSI: return MLX4_QP_ST_MLX;
770 default: return -1;
771 }
772}
773
65adfa91 774static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 775 int attr_mask)
776{
777 u8 dest_rd_atomic;
778 u32 access_flags;
779 u32 hw_access_flags = 0;
780
781 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
782 dest_rd_atomic = attr->max_dest_rd_atomic;
783 else
784 dest_rd_atomic = qp->resp_depth;
785
786 if (attr_mask & IB_QP_ACCESS_FLAGS)
787 access_flags = attr->qp_access_flags;
788 else
789 access_flags = qp->atomic_rd_en;
790
791 if (!dest_rd_atomic)
792 access_flags &= IB_ACCESS_REMOTE_WRITE;
793
794 if (access_flags & IB_ACCESS_REMOTE_READ)
795 hw_access_flags |= MLX4_QP_BIT_RRE;
796 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
797 hw_access_flags |= MLX4_QP_BIT_RAE;
798 if (access_flags & IB_ACCESS_REMOTE_WRITE)
799 hw_access_flags |= MLX4_QP_BIT_RWE;
800
801 return cpu_to_be32(hw_access_flags);
802}
803
65adfa91 804static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 805 int attr_mask)
806{
807 if (attr_mask & IB_QP_PKEY_INDEX)
808 sqp->pkey_index = attr->pkey_index;
809 if (attr_mask & IB_QP_QKEY)
810 sqp->qkey = attr->qkey;
811 if (attr_mask & IB_QP_SQ_PSN)
812 sqp->send_psn = attr->sq_psn;
813}
814
815static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
816{
817 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
818}
819
65adfa91 820static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
225c7b1f
RD		 821 struct mlx4_qp_path *path, u8 port)
822{
823 path->grh_mylmc = ah->src_path_bits & 0x7f;
824 path->rlid = cpu_to_be16(ah->dlid);
825 if (ah->static_rate) {
826 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
827 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
828 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
829 --path->static_rate;
830 } else
831 path->static_rate = 0;
832 path->counter_index = 0xff;
833
834 if (ah->ah_flags & IB_AH_GRH) {
5ae2a7a8 835 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
225c7b1f 836 printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
5ae2a7a8 837 ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 838 return -1;
839 }
840
841 path->grh_mylmc |= 1 << 7;
842 path->mgid_index = ah->grh.sgid_index;
843 path->hop_limit = ah->grh.hop_limit;
844 path->tclass_flowlabel =
845 cpu_to_be32((ah->grh.traffic_class << 20) |
846 (ah->grh.flow_label));
847 memcpy(path->rgid, ah->grh.dgid.raw, 16);
848 }
849
850 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
851 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
852
853 return 0;
854}
855
65adfa91
MT		 856static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
857 const struct ib_qp_attr *attr, int attr_mask,
858 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 859{
860 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
861 struct mlx4_ib_qp *qp = to_mqp(ibqp);
862 struct mlx4_qp_context *context;
863 enum mlx4_qp_optpar optpar = 0;
225c7b1f
RD		 864 int sqd_event;
865 int err = -EINVAL;
866
867 context = kzalloc(sizeof *context, GFP_KERNEL);
868 if (!context)
869 return -ENOMEM;
870
225c7b1f
RD		 871 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
872 (to_mlx4_st(ibqp->qp_type) << 16));
873 context->flags |= cpu_to_be32(1 << 8); /* DE? */
874
875 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
876 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
877 else {
878 optpar |= MLX4_QP_OPTPAR_PM_STATE;
879 switch (attr->path_mig_state) {
880 case IB_MIG_MIGRATED:
881 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
882 break;
883 case IB_MIG_REARM:
884 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
885 break;
886 case IB_MIG_ARMED:
887 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
888 break;
889 }
890 }
891
b832be1e 892 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 893 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
b832be1e
EC		 894 else if (ibqp->qp_type == IB_QPT_UD) {
895 if (qp->flags & MLX4_IB_QP_LSO)
896 context->mtu_msgmax = (IB_MTU_4096 << 5) |
897 ilog2(dev->dev->caps.max_gso_sz);
898 else
899 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
900 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f
RD		 901 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
902 printk(KERN_ERR "path MTU (%u) is invalid\n",
903 attr->path_mtu);
f5b40431 904 goto out;
225c7b1f
RD		 905 }
906 context->mtu_msgmax = (attr->path_mtu << 5) | 31;
907 }
908
0e6e7416
RD		 909 if (qp->rq.wqe_cnt)
910 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 911 context->rq_size_stride |= qp->rq.wqe_shift - 4;
912
0e6e7416
RD		 913 if (qp->sq.wqe_cnt)
914 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 915 context->sq_size_stride |= qp->sq.wqe_shift - 4;
916
0e6e7416
RD		 917 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
918 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
919
225c7b1f
RD		 920 if (qp->ibqp.uobject)
921 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
922 else
923 context->usr_page = cpu_to_be32(dev->priv_uar.index);
924
925 if (attr_mask & IB_QP_DEST_QPN)
926 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
927
928 if (attr_mask & IB_QP_PORT) {
929 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
930 !(attr_mask & IB_QP_AV)) {
931 mlx4_set_sched(&context->pri_path, attr->port_num);
932 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
933 }
934 }
935
936 if (attr_mask & IB_QP_PKEY_INDEX) {
937 context->pri_path.pkey_index = attr->pkey_index;
938 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
939 }
940
225c7b1f
RD		 941 if (attr_mask & IB_QP_AV) {
942 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
f5b40431 943 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
225c7b1f 944 goto out;
225c7b1f
RD		 945
946 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
947 MLX4_QP_OPTPAR_SCHED_QUEUE);
948 }
949
950 if (attr_mask & IB_QP_TIMEOUT) {
951 context->pri_path.ackto = attr->timeout << 3;
952 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
953 }
954
955 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 956 if (attr->alt_port_num == 0 ||
957 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 958 goto out;
225c7b1f 959
5ae2a7a8
RD		 960 if (attr->alt_pkey_index >=
961 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 962 goto out;
5ae2a7a8 963
225c7b1f
RD		 964 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
965 attr->alt_port_num))
f5b40431 966 goto out;
225c7b1f
RD		 967
968 context->alt_path.pkey_index = attr->alt_pkey_index;
969 context->alt_path.ackto = attr->alt_timeout << 3;
970 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
971 }
972
973 context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
974 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53
JM		 975
976 if (attr_mask & IB_QP_RNR_RETRY) {
977 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
978 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
979 }
980
225c7b1f
RD		 981 if (attr_mask & IB_QP_RETRY_CNT) {
982 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
983 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
984 }
985
986 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
987 if (attr->max_rd_atomic)
988 context->params1 |=
989 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
990 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
991 }
992
993 if (attr_mask & IB_QP_SQ_PSN)
994 context->next_send_psn = cpu_to_be32(attr->sq_psn);
995
996 context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
997
998 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
999 if (attr->max_dest_rd_atomic)
1000 context->params2 |=
1001 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1002 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1003 }
1004
1005 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1006 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1007 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1008 }
1009
1010 if (ibqp->srq)
1011 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1012
1013 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1014 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1015 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1016 }
1017 if (attr_mask & IB_QP_RQ_PSN)
1018 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1019
1020 context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
1021
1022 if (attr_mask & IB_QP_QKEY) {
1023 context->qkey = cpu_to_be32(attr->qkey);
1024 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1025 }
1026
1027 if (ibqp->srq)
1028 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1029
02d89b87 1030 if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1031 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1032
1033 if (cur_state == IB_QPS_INIT &&
1034 new_state == IB_QPS_RTR &&
1035 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1036 ibqp->qp_type == IB_QPT_UD)) {
1037 context->pri_path.sched_queue = (qp->port - 1) << 6;
1038 if (is_qp0(dev, qp))
1039 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1040 else
1041 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1042 }
1043
1044 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1045 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1046 sqd_event = 1;
1047 else
1048 sqd_event = 0;
1049
c0be5fb5
EC		 1050 /*
1051 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1052 * ownership bits of the send queue are set and the SQ
1053 * headroom is stamped so that the hardware doesn't start
1054 * processing stale work requests.
c0be5fb5
EC		 1055 */
1056 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1057 struct mlx4_wqe_ctrl_seg *ctrl;
1058 int i;
1059
0e6e7416 1060 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1061 ctrl = get_send_wqe(qp, i);
1062 ctrl->owner_opcode = cpu_to_be32(1 << 31);
0e6e7416 1063
ea54b10c 1064 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 1065 }
1066 }
1067
225c7b1f
RD		 1068 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1069 to_mlx4_state(new_state), context, optpar,
1070 sqd_event, &qp->mqp);
1071 if (err)
1072 goto out;
1073
1074 qp->state = new_state;
1075
1076 if (attr_mask & IB_QP_ACCESS_FLAGS)
1077 qp->atomic_rd_en = attr->qp_access_flags;
1078 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1079 qp->resp_depth = attr->max_dest_rd_atomic;
1080 if (attr_mask & IB_QP_PORT)
1081 qp->port = attr->port_num;
1082 if (attr_mask & IB_QP_ALT_PATH)
1083 qp->alt_port = attr->alt_port_num;
1084
1085 if (is_sqp(dev, qp))
1086 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1087
1088 /*
1089 * If we moved QP0 to RTR, bring the IB link up; if we moved
1090 * QP0 to RESET or ERROR, bring the link back down.
1091 */
1092 if (is_qp0(dev, qp)) {
1093 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8
RD		 1094 if (mlx4_INIT_PORT(dev->dev, qp->port))
1095 printk(KERN_WARNING "INIT_PORT failed for port %d\n",
1096 qp->port);
225c7b1f
RD		 1097
1098 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1099 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1100 mlx4_CLOSE_PORT(dev->dev, qp->port);
1101 }
1102
1103 /*
1104 * If we moved a kernel QP to RESET, clean up all old CQ
1105 * entries and reinitialize the QP.
1106 */
1107 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1108 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
1109 ibqp->srq ? to_msrq(ibqp->srq): NULL);
1110 if (ibqp->send_cq != ibqp->recv_cq)
1111 mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
1112
1113 qp->rq.head = 0;
1114 qp->rq.tail = 0;
1115 qp->sq.head = 0;
1116 qp->sq.tail = 0;
ea54b10c 1117 qp->sq_next_wqe = 0;
02d89b87
RD		 1118 if (!ibqp->srq)
1119 *qp->db.db = 0;
225c7b1f
RD		 1120 }
1121
1122out:
225c7b1f
RD		 1123 kfree(context);
1124 return err;
1125}
1126
65adfa91
MT		 1127static const struct ib_qp_attr mlx4_ib_qp_attr = { .port_num = 1 };
1128static const int mlx4_ib_qp_attr_mask_table[IB_QPT_UD + 1] = {
1129 [IB_QPT_UD] = (IB_QP_PKEY_INDEX |
1130 IB_QP_PORT |
1131 IB_QP_QKEY),
1132 [IB_QPT_UC] = (IB_QP_PKEY_INDEX |
1133 IB_QP_PORT |
1134 IB_QP_ACCESS_FLAGS),
1135 [IB_QPT_RC] = (IB_QP_PKEY_INDEX |
1136 IB_QP_PORT |
1137 IB_QP_ACCESS_FLAGS),
1138 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX |
1139 IB_QP_QKEY),
1140 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX |
1141 IB_QP_QKEY),
1142};
1143
1144int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1145 int attr_mask, struct ib_udata *udata)
1146{
1147 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1148 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1149 enum ib_qp_state cur_state, new_state;
1150 int err = -EINVAL;
1151
1152 mutex_lock(&qp->mutex);
1153
1154 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1155 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1156
1157 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1158 goto out;
1159
65adfa91
MT		 1160 if ((attr_mask & IB_QP_PORT) &&
1161 (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1162 goto out;
1163 }
1164
5ae2a7a8
RD		 1165 if (attr_mask & IB_QP_PKEY_INDEX) {
1166 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1167 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1168 goto out;
1169 }
1170
65adfa91
MT		 1171 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1172 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1173 goto out;
1174 }
1175
1176 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1177 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1178 goto out;
1179 }
1180
1181 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1182 err = 0;
1183 goto out;
1184 }
1185
1186 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) {
1187 err = __mlx4_ib_modify_qp(ibqp, &mlx4_ib_qp_attr,
1188 mlx4_ib_qp_attr_mask_table[ibqp->qp_type],
1189 IB_QPS_RESET, IB_QPS_INIT);
1190 if (err)
1191 goto out;
1192 cur_state = IB_QPS_INIT;
1193 }
1194
1195 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1196
1197out:
1198 mutex_unlock(&qp->mutex);
1199 return err;
1200}
1201
225c7b1f 1202static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
f438000f 1203 void *wqe, unsigned *mlx_seg_len)
225c7b1f
RD		 1204{
1205 struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1206 struct mlx4_wqe_mlx_seg *mlx = wqe;
1207 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1208 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1209 u16 pkey;
1210 int send_size;
1211 int header_size;
e61ef241 1212 int spc;
225c7b1f
RD		 1213 int i;
1214
1215 send_size = 0;
1216 for (i = 0; i < wr->num_sge; ++i)
1217 send_size += wr->sg_list[i].length;
1218
1219 ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1220
1221 sqp->ud_header.lrh.service_level =
1222 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1223 sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1224 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.g_slid & 0x7f);
1225 if (mlx4_ib_ah_grh_present(ah)) {
1226 sqp->ud_header.grh.traffic_class =
1227 (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1228 sqp->ud_header.grh.flow_label =
1229 ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
15261303 1230 sqp->ud_header.grh.hop_limit = ah->av.hop_limit;
225c7b1f
RD		 1231 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1232 ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1233 memcpy(sqp->ud_header.grh.destination_gid.raw,
1234 ah->av.dgid, 16);
1235 }
1236
1237 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1238 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1239 (sqp->ud_header.lrh.destination_lid ==
1240 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1241 (sqp->ud_header.lrh.service_level << 8));
1242 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1243
1244 switch (wr->opcode) {
1245 case IB_WR_SEND:
1246 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1247 sqp->ud_header.immediate_present = 0;
1248 break;
1249 case IB_WR_SEND_WITH_IMM:
1250 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1251 sqp->ud_header.immediate_present = 1;
0f39cf3d 1252 sqp->ud_header.immediate_data = wr->ex.imm_data;
225c7b1f
RD		 1253 break;
1254 default:
1255 return -EINVAL;
1256 }
1257
1258 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1259 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1260 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1261 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1262 if (!sqp->qp.ibqp.qp_num)
1263 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1264 else
1265 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1266 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1267 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1268 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1269 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1270 sqp->qkey : wr->wr.ud.remote_qkey);
1271 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1272
1273 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1274
1275 if (0) {
1276 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1277 for (i = 0; i < header_size / 4; ++i) {
1278 if (i % 8 == 0)
1279 printk(" [%02x] ", i * 4);
1280 printk(" %08x",
1281 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1282 if ((i + 1) % 8 == 0)
1283 printk("\n");
1284 }
1285 printk("\n");
1286 }
1287
e61ef241
RD		 1288 /*
1289 * Inline data segments may not cross a 64 byte boundary. If
1290 * our UD header is bigger than the space available up to the
1291 * next 64 byte boundary in the WQE, use two inline data
1292 * segments to hold the UD header.
1293 */
1294 spc = MLX4_INLINE_ALIGN -
1295 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1296 if (header_size <= spc) {
1297 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1298 memcpy(inl + 1, sqp->header_buf, header_size);
1299 i = 1;
1300 } else {
1301 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1302 memcpy(inl + 1, sqp->header_buf, spc);
1303
1304 inl = (void *) (inl + 1) + spc;
1305 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1306 /*
1307 * Need a barrier here to make sure all the data is
1308 * visible before the byte_count field is set.
1309 * Otherwise the HCA prefetcher could grab the 64-byte
1310 * chunk with this inline segment and get a valid (!=
1311 * 0xffffffff) byte count but stale data, and end up
1312 * generating a packet with bad headers.
1313 *
1314 * The first inline segment's byte_count field doesn't
1315 * need a barrier, because it comes after a
1316 * control/MLX segment and therefore is at an offset
1317 * of 16 mod 64.
1318 */
1319 wmb();
1320 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1321 i = 2;
1322 }
225c7b1f 1323
f438000f
RD		 1324 *mlx_seg_len =
1325 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1326 return 0;
225c7b1f
RD		 1327}
1328
1329static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1330{
1331 unsigned cur;
1332 struct mlx4_ib_cq *cq;
1333
1334 cur = wq->head - wq->tail;
0e6e7416 1335 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 1336 return 0;
1337
1338 cq = to_mcq(ib_cq);
1339 spin_lock(&cq->lock);
1340 cur = wq->head - wq->tail;
1341 spin_unlock(&cq->lock);
1342
0e6e7416 1343 return cur + nreq >= wq->max_post;
225c7b1f
RD		 1344}
1345
0fbfa6a9
RD		 1346static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1347 u64 remote_addr, u32 rkey)
1348{
1349 rseg->raddr = cpu_to_be64(remote_addr);
1350 rseg->rkey = cpu_to_be32(rkey);
1351 rseg->reserved = 0;
1352}
1353
1354static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1355{
1356 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1357 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1358 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
1359 } else {
1360 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1361 aseg->compare = 0;
1362 }
1363
1364}
1365
1366static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1367 struct ib_send_wr *wr)
1368{
1369 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1370 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1371 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
0fbfa6a9
RD		 1372}
1373
6e694ea3
JM		 1374static void set_mlx_icrc_seg(void *dseg)
1375{
1376 u32 *t = dseg;
1377 struct mlx4_wqe_inline_seg *iseg = dseg;
1378
1379 t[1] = 0;
1380
1381 /*
1382 * Need a barrier here before writing the byte_count field to
1383 * make sure that all the data is visible before the
1384 * byte_count field is set. Otherwise, if the segment begins
1385 * a new cacheline, the HCA prefetcher could grab the 64-byte
1386 * chunk and get a valid (!= * 0xffffffff) byte count but
1387 * stale data, and end up sending the wrong data.
1388 */
1389 wmb();
1390
1391 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1392}
1393
1394static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 1395{
d420d9e3
RD		 1396 dseg->lkey = cpu_to_be32(sg->lkey);
1397 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 1398
1399 /*
1400 * Need a barrier here before writing the byte_count field to
1401 * make sure that all the data is visible before the
1402 * byte_count field is set. Otherwise, if the segment begins
1403 * a new cacheline, the HCA prefetcher could grab the 64-byte
1404 * chunk and get a valid (!= * 0xffffffff) byte count but
1405 * stale data, and end up sending the wrong data.
1406 */
1407 wmb();
1408
1409 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 1410}
1411
2242fa4f
RD		 1412static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1413{
1414 dseg->byte_count = cpu_to_be32(sg->length);
1415 dseg->lkey = cpu_to_be32(sg->lkey);
1416 dseg->addr = cpu_to_be64(sg->addr);
1417}
1418
b832be1e
EC		 1419static int build_lso_seg(struct mlx4_lso_seg *wqe, struct ib_send_wr *wr,
1420 struct mlx4_ib_qp *qp, unsigned *lso_seg_len)
1421{
1422 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
1423
1424 /*
1425 * This is a temporary limitation and will be removed in
1426 * a forthcoming FW release:
1427 */
1428 if (unlikely(halign > 64))
1429 return -EINVAL;
1430
1431 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
1432 wr->num_sge > qp->sq.max_gs - (halign >> 4)))
1433 return -EINVAL;
1434
1435 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
1436
1437 /* make sure LSO header is written before overwriting stamping */
1438 wmb();
1439
1440 wqe->mss_hdr_size = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
1441 wr->wr.ud.hlen);
1442
1443 *lso_seg_len = halign;
1444 return 0;
1445}
1446
225c7b1f
RD		 1447int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1448 struct ib_send_wr **bad_wr)
1449{
1450 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1451 void *wqe;
1452 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 1453 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 1454 unsigned long flags;
1455 int nreq;
1456 int err = 0;
ea54b10c
JM		 1457 unsigned ind;
1458 int uninitialized_var(stamp);
1459 int uninitialized_var(size);
a3d8e159 1460 unsigned uninitialized_var(seglen);
225c7b1f
RD		 1461 int i;
1462
96db0e03 1463 spin_lock_irqsave(&qp->sq.lock, flags);
225c7b1f 1464
ea54b10c 1465 ind = qp->sq_next_wqe;
225c7b1f
RD		 1466
1467 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1468 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1469 err = -ENOMEM;
1470 *bad_wr = wr;
1471 goto out;
1472 }
1473
1474 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1475 err = -EINVAL;
1476 *bad_wr = wr;
1477 goto out;
1478 }
1479
0e6e7416 1480 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 1481 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 1482
1483 ctrl->srcrb_flags =
1484 (wr->send_flags & IB_SEND_SIGNALED ?
1485 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1486 (wr->send_flags & IB_SEND_SOLICITED ?
1487 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 1488 ((wr->send_flags & IB_SEND_IP_CSUM) ?
1489 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
1490 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 1491 qp->sq_signal_bits;
1492
1493 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1494 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
0f39cf3d 1495 ctrl->imm = wr->ex.imm_data;
225c7b1f
RD		 1496 else
1497 ctrl->imm = 0;
1498
1499 wqe += sizeof *ctrl;
1500 size = sizeof *ctrl / 16;
1501
1502 switch (ibqp->qp_type) {
1503 case IB_QPT_RC:
1504 case IB_QPT_UC:
1505 switch (wr->opcode) {
1506 case IB_WR_ATOMIC_CMP_AND_SWP:
1507 case IB_WR_ATOMIC_FETCH_AND_ADD:
0fbfa6a9
RD		 1508 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1509 wr->wr.atomic.rkey);
225c7b1f
RD		 1510 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1511
0fbfa6a9 1512 set_atomic_seg(wqe, wr);
225c7b1f 1513 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 1514
225c7b1f
RD		 1515 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1516 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1517
1518 break;
1519
1520 case IB_WR_RDMA_READ:
1521 case IB_WR_RDMA_WRITE:
1522 case IB_WR_RDMA_WRITE_WITH_IMM:
0fbfa6a9
RD		 1523 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1524 wr->wr.rdma.rkey);
225c7b1f
RD		 1525 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1526 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f
RD		 1527 break;
1528
1529 default:
1530 /* No extra segments required for sends */
1531 break;
1532 }
1533 break;
1534
1535 case IB_QPT_UD:
0fbfa6a9 1536 set_datagram_seg(wqe, wr);
225c7b1f
RD		 1537 wqe += sizeof (struct mlx4_wqe_datagram_seg);
1538 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 1539
1540 if (wr->opcode == IB_WR_LSO) {
1541 err = build_lso_seg(wqe, wr, qp, &seglen);
1542 if (unlikely(err)) {
1543 *bad_wr = wr;
1544 goto out;
1545 }
1546 wqe += seglen;
1547 size += seglen / 16;
1548 }
225c7b1f
RD		 1549 break;
1550
1551 case IB_QPT_SMI:
1552 case IB_QPT_GSI:
f438000f
RD		 1553 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
1554 if (unlikely(err)) {
225c7b1f
RD		 1555 *bad_wr = wr;
1556 goto out;
1557 }
f438000f
RD		 1558 wqe += seglen;
1559 size += seglen / 16;
225c7b1f
RD		 1560 break;
1561
1562 default:
1563 break;
1564 }
1565
6e694ea3
JM		 1566 /*
1567 * Write data segments in reverse order, so as to
1568 * overwrite cacheline stamp last within each
1569 * cacheline. This avoids issues with WQE
1570 * prefetching.
1571 */
225c7b1f 1572
6e694ea3
JM		 1573 dseg = wqe;
1574 dseg += wr->num_sge - 1;
1575 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 1576
1577 /* Add one more inline data segment for ICRC for MLX sends */
6e694ea3
JM		 1578 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1579 qp->ibqp.qp_type == IB_QPT_GSI)) {
1580 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 1581 size += sizeof (struct mlx4_wqe_data_seg) / 16;
1582 }
1583
6e694ea3
JM		 1584 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
1585 set_data_seg(dseg, wr->sg_list + i);
1586
225c7b1f
RD		 1587 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1588 MLX4_WQE_CTRL_FENCE : 0) | size;
1589
1590 /*
1591 * Make sure descriptor is fully written before
1592 * setting ownership bit (because HW can start
1593 * executing as soon as we do).
1594 */
1595 wmb();
1596
59b0ed12 1597 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
225c7b1f
RD		 1598 err = -EINVAL;
1599 goto out;
1600 }
1601
1602 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
0e6e7416
RD		 1603 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
1604
ea54b10c
JM		 1605 stamp = ind + qp->sq_spare_wqes;
1606 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
1607
0e6e7416
RD		 1608 /*
1609 * We can improve latency by not stamping the last
1610 * send queue WQE until after ringing the doorbell, so
1611 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 1612 *
1613 * Same optimization applies to padding with NOP wqe
1614 * in case of WQE shrinking (used to prevent wrap-around
1615 * in the middle of WR).
0e6e7416 1616 */
ea54b10c
JM		 1617 if (wr->next) {
1618 stamp_send_wqe(qp, stamp, size * 16);
1619 ind = pad_wraparound(qp, ind);
1620 }
225c7b1f 1621
225c7b1f
RD		 1622 }
1623
1624out:
1625 if (likely(nreq)) {
1626 qp->sq.head += nreq;
1627
1628 /*
1629 * Make sure that descriptors are written before
1630 * doorbell record.
1631 */
1632 wmb();
1633
1634 writel(qp->doorbell_qpn,
1635 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1636
1637 /*
1638 * Make sure doorbells don't leak out of SQ spinlock
1639 * and reach the HCA out of order.
1640 */
1641 mmiowb();
0e6e7416 1642
ea54b10c
JM		 1643 stamp_send_wqe(qp, stamp, size * 16);
1644
1645 ind = pad_wraparound(qp, ind);
1646 qp->sq_next_wqe = ind;
225c7b1f
RD		 1647 }
1648
96db0e03 1649 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 1650
1651 return err;
1652}
1653
1654int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1655 struct ib_recv_wr **bad_wr)
1656{
1657 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1658 struct mlx4_wqe_data_seg *scat;
1659 unsigned long flags;
1660 int err = 0;
1661 int nreq;
1662 int ind;
1663 int i;
1664
1665 spin_lock_irqsave(&qp->rq.lock, flags);
1666
0e6e7416 1667 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 1668
1669 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1670 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1671 err = -ENOMEM;
1672 *bad_wr = wr;
1673 goto out;
1674 }
1675
1676 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1677 err = -EINVAL;
1678 *bad_wr = wr;
1679 goto out;
1680 }
1681
1682 scat = get_recv_wqe(qp, ind);
1683
2242fa4f
RD		 1684 for (i = 0; i < wr->num_sge; ++i)
1685 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f
RD		 1686
1687 if (i < qp->rq.max_gs) {
1688 scat[i].byte_count = 0;
1689 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
1690 scat[i].addr = 0;
1691 }
1692
1693 qp->rq.wrid[ind] = wr->wr_id;
1694
0e6e7416 1695 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 1696 }
1697
1698out:
1699 if (likely(nreq)) {
1700 qp->rq.head += nreq;
1701
1702 /*
1703 * Make sure that descriptors are written before
1704 * doorbell record.
1705 */
1706 wmb();
1707
1708 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1709 }
1710
1711 spin_unlock_irqrestore(&qp->rq.lock, flags);
1712
1713 return err;
1714}
6a775e2b
JM		 1715
1716static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
1717{
1718 switch (mlx4_state) {
1719 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
1720 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
1721 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
1722 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
1723 case MLX4_QP_STATE_SQ_DRAINING:
1724 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
1725 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
1726 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
1727 default: return -1;
1728 }
1729}
1730
1731static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
1732{
1733 switch (mlx4_mig_state) {
1734 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
1735 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
1736 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
1737 default: return -1;
1738 }
1739}
1740
1741static int to_ib_qp_access_flags(int mlx4_flags)
1742{
1743 int ib_flags = 0;
1744
1745 if (mlx4_flags & MLX4_QP_BIT_RRE)
1746 ib_flags |= IB_ACCESS_REMOTE_READ;
1747 if (mlx4_flags & MLX4_QP_BIT_RWE)
1748 ib_flags |= IB_ACCESS_REMOTE_WRITE;
1749 if (mlx4_flags & MLX4_QP_BIT_RAE)
1750 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
1751
1752 return ib_flags;
1753}
1754
1755static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr,
1756 struct mlx4_qp_path *path)
1757{
8fcea95a 1758 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 1759 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
1760
1761 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
1762 return;
1763
1764 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
1765 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
1766 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
1767 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
1768 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
1769 if (ib_ah_attr->ah_flags) {
1770 ib_ah_attr->grh.sgid_index = path->mgid_index;
1771 ib_ah_attr->grh.hop_limit = path->hop_limit;
1772 ib_ah_attr->grh.traffic_class =
1773 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
1774 ib_ah_attr->grh.flow_label =
586bb586 1775 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 1776 memcpy(ib_ah_attr->grh.dgid.raw,
1777 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
1778 }
1779}
1780
1781int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1782 struct ib_qp_init_attr *qp_init_attr)
1783{
1784 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1785 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1786 struct mlx4_qp_context context;
1787 int mlx4_state;
0df67030
DB		 1788 int err = 0;
1789
1790 mutex_lock(&qp->mutex);
6a775e2b
JM		 1791
1792 if (qp->state == IB_QPS_RESET) {
1793 qp_attr->qp_state = IB_QPS_RESET;
1794 goto done;
1795 }
1796
1797 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 1798 if (err) {
1799 err = -EINVAL;
1800 goto out;
1801 }
6a775e2b
JM		 1802
1803 mlx4_state = be32_to_cpu(context.flags) >> 28;
1804
0df67030
DB		 1805 qp->state = to_ib_qp_state(mlx4_state);
1806 qp_attr->qp_state = qp->state;
6a775e2b
JM		 1807 qp_attr->path_mtu = context.mtu_msgmax >> 5;
1808 qp_attr->path_mig_state =
1809 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
1810 qp_attr->qkey = be32_to_cpu(context.qkey);
1811 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
1812 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
1813 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
1814 qp_attr->qp_access_flags =
1815 to_ib_qp_access_flags(be32_to_cpu(context.params2));
1816
1817 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
1818 to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path);
1819 to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path);
1820 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
1821 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
1822 }
1823
1824 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 1825 if (qp_attr->qp_state == IB_QPS_INIT)
1826 qp_attr->port_num = qp->port;
1827 else
1828 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 1829
1830 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
1831 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
1832
1833 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
1834
1835 qp_attr->max_dest_rd_atomic =
1836 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
1837 qp_attr->min_rnr_timer =
1838 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
1839 qp_attr->timeout = context.pri_path.ackto >> 3;
1840 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
1841 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
1842 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
1843
1844done:
1845 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 1846 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
1847 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
1848
6a775e2b 1849 if (!ibqp->uobject) {
7f5eb9bb
RD		 1850 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
1851 qp_attr->cap.max_send_sge = qp->sq.max_gs;
1852 } else {
1853 qp_attr->cap.max_send_wr = 0;
1854 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 1855 }
1856
7f5eb9bb
RD		 1857 /*
1858 * We don't support inline sends for kernel QPs (yet), and we
1859 * don't know what userspace's value should be.
1860 */
1861 qp_attr->cap.max_inline_data = 0;
1862
1863 qp_init_attr->cap = qp_attr->cap;
1864
0df67030
DB		 1865out:
1866 mutex_unlock(&qp->mutex);
1867 return err;
6a775e2b
JM		 1868}
1869
Linux 6.x block layer and io_uring tree(s)