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IB/mlx4: Handle new FW requirement for send request prefetching
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <rdma/ib_cache.h>
34#include <rdma/ib_pack.h>
35
36#include <linux/mlx4/qp.h>
37
38#include "mlx4_ib.h"
39#include "user.h"
40
41enum {
42 MLX4_IB_ACK_REQ_FREQ = 8,
43};
44
45enum {
46 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
47 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
48};
49
50enum {
51 /*
52 * Largest possible UD header: send with GRH and immediate data.
53 */
54 MLX4_IB_UD_HEADER_SIZE = 72
55};
56
57struct mlx4_ib_sqp {
58 struct mlx4_ib_qp qp;
59 int pkey_index;
60 u32 qkey;
61 u32 send_psn;
62 struct ib_ud_header ud_header;
63 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
64};
65
66static const __be32 mlx4_ib_opcode[] = {
67 [IB_WR_SEND] = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
68 [IB_WR_SEND_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
69 [IB_WR_RDMA_WRITE] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
70 [IB_WR_RDMA_WRITE_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
71 [IB_WR_RDMA_READ] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
72 [IB_WR_ATOMIC_CMP_AND_SWP] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
73 [IB_WR_ATOMIC_FETCH_AND_ADD] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
74};
75
76static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
77{
78 return container_of(mqp, struct mlx4_ib_sqp, qp);
79}
80
81static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
82{
83 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
84 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
85}
86
87static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
88{
89 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
90 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
91}
92
93static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
94{
95 if (qp->buf.nbufs == 1)
96 return qp->buf.u.direct.buf + offset;
97 else
98 return qp->buf.u.page_list[offset >> PAGE_SHIFT].buf +
99 (offset & (PAGE_SIZE - 1));
100}
101
102static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
103{
104 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
105}
106
107static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
108{
109 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
110}
111
0e6e7416
RD		 112/*
113 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
114 * first four bytes of every 64 byte chunk with 0xffffffff, except for
115 * the very first chunk of the WQE.
116 */
117static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
118{
119 u32 *wqe = get_send_wqe(qp, n);
120 int i;
121
122 for (i = 16; i < 1 << (qp->sq.wqe_shift - 2); i += 16)
123 wqe[i] = 0xffffffff;
124}
125
225c7b1f
RD		 126static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
127{
128 struct ib_event event;
129 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
130
131 if (type == MLX4_EVENT_TYPE_PATH_MIG)
132 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
133
134 if (ibqp->event_handler) {
135 event.device = ibqp->device;
136 event.element.qp = ibqp;
137 switch (type) {
138 case MLX4_EVENT_TYPE_PATH_MIG:
139 event.event = IB_EVENT_PATH_MIG;
140 break;
141 case MLX4_EVENT_TYPE_COMM_EST:
142 event.event = IB_EVENT_COMM_EST;
143 break;
144 case MLX4_EVENT_TYPE_SQ_DRAINED:
145 event.event = IB_EVENT_SQ_DRAINED;
146 break;
147 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
148 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
149 break;
150 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
151 event.event = IB_EVENT_QP_FATAL;
152 break;
153 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
154 event.event = IB_EVENT_PATH_MIG_ERR;
155 break;
156 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
157 event.event = IB_EVENT_QP_REQ_ERR;
158 break;
159 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
160 event.event = IB_EVENT_QP_ACCESS_ERR;
161 break;
162 default:
163 printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
164 "on QP %06x\n", type, qp->qpn);
165 return;
166 }
167
168 ibqp->event_handler(&event, ibqp->qp_context);
169 }
170}
171
172static int send_wqe_overhead(enum ib_qp_type type)
173{
174 /*
175 * UD WQEs must have a datagram segment.
176 * RC and UC WQEs might have a remote address segment.
177 * MLX WQEs need two extra inline data segments (for the UD
178 * header and space for the ICRC).
179 */
180 switch (type) {
181 case IB_QPT_UD:
182 return sizeof (struct mlx4_wqe_ctrl_seg) +
183 sizeof (struct mlx4_wqe_datagram_seg);
184 case IB_QPT_UC:
185 return sizeof (struct mlx4_wqe_ctrl_seg) +
186 sizeof (struct mlx4_wqe_raddr_seg);
187 case IB_QPT_RC:
188 return sizeof (struct mlx4_wqe_ctrl_seg) +
189 sizeof (struct mlx4_wqe_atomic_seg) +
190 sizeof (struct mlx4_wqe_raddr_seg);
191 case IB_QPT_SMI:
192 case IB_QPT_GSI:
193 return sizeof (struct mlx4_wqe_ctrl_seg) +
194 ALIGN(MLX4_IB_UD_HEADER_SIZE +
195 sizeof (struct mlx4_wqe_inline_seg),
196 sizeof (struct mlx4_wqe_data_seg)) +
197 ALIGN(4 +
198 sizeof (struct mlx4_wqe_inline_seg),
199 sizeof (struct mlx4_wqe_data_seg));
200 default:
201 return sizeof (struct mlx4_wqe_ctrl_seg);
202 }
203}
204
2446304d 205static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
a4cd7ed8 206 int is_user, int has_srq, struct mlx4_ib_qp *qp)
225c7b1f 207{
2446304d
EC		 208 /* Sanity check RQ size before proceeding */
209 if (cap->max_recv_wr > dev->dev->caps.max_wqes ||
210 cap->max_recv_sge > dev->dev->caps.max_rq_sg)
211 return -EINVAL;
212
a4cd7ed8
RD		 213 if (has_srq) {
214 /* QPs attached to an SRQ should have no RQ */
215 if (cap->max_recv_wr)
216 return -EINVAL;
2446304d 217
0e6e7416 218 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 219 } else {
220 /* HW requires >= 1 RQ entry with >= 1 gather entry */
221 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
222 return -EINVAL;
223
0e6e7416 224 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 225 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 226 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
227 }
2446304d 228
0e6e7416 229 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
2446304d
EC		 230 cap->max_recv_sge = qp->rq.max_gs;
231
232 return 0;
233}
234
235static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
236 enum ib_qp_type type, struct mlx4_ib_qp *qp)
237{
238 /* Sanity check SQ size before proceeding */
225c7b1f 239 if (cap->max_send_wr > dev->dev->caps.max_wqes ||
225c7b1f 240 cap->max_send_sge > dev->dev->caps.max_sq_sg ||
225c7b1f
RD		 241 cap->max_inline_data + send_wqe_overhead(type) +
242 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
243 return -EINVAL;
244
245 /*
246 * For MLX transport we need 2 extra S/G entries:
247 * one for the header and one for the checksum at the end
248 */
249 if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
250 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
251 return -EINVAL;
252
225c7b1f
RD		 253 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(max(cap->max_send_sge *
254 sizeof (struct mlx4_wqe_data_seg),
255 cap->max_inline_data +
256 sizeof (struct mlx4_wqe_inline_seg)) +
257 send_wqe_overhead(type)));
258 qp->sq.max_gs = ((1 << qp->sq.wqe_shift) - send_wqe_overhead(type)) /
259 sizeof (struct mlx4_wqe_data_seg);
260
0e6e7416
RD		 261 /*
262 * We need to leave 2 KB + 1 WQE of headroom in the SQ to
263 * allow HW to prefetch.
264 */
265 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + 1;
266 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr + qp->sq_spare_wqes);
267
268 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
269 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 270 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
271 qp->rq.offset = 0;
0e6e7416 272 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 273 } else {
0e6e7416 274 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 275 qp->sq.offset = 0;
276 }
277
0e6e7416
RD		 278 cap->max_send_wr = qp->sq.max_post = qp->sq.wqe_cnt - qp->sq_spare_wqes;
279 cap->max_send_sge = qp->sq.max_gs;
225c7b1f
RD		 280 cap->max_inline_data = (1 << qp->sq.wqe_shift) - send_wqe_overhead(type) -
281 sizeof (struct mlx4_wqe_inline_seg);
282
283 return 0;
284}
285
2446304d
EC		 286static int set_user_sq_size(struct mlx4_ib_qp *qp,
287 struct mlx4_ib_create_qp *ucmd)
288{
0e6e7416 289 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 290 qp->sq.wqe_shift = ucmd->log_sq_stride;
291
0e6e7416
RD		 292 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
293 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 294
295 return 0;
296}
297
225c7b1f
RD		 298static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
299 struct ib_qp_init_attr *init_attr,
300 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
301{
225c7b1f 302 int err;
225c7b1f
RD		 303
304 mutex_init(&qp->mutex);
305 spin_lock_init(&qp->sq.lock);
306 spin_lock_init(&qp->rq.lock);
307
308 qp->state = IB_QPS_RESET;
309 qp->atomic_rd_en = 0;
310 qp->resp_depth = 0;
311
312 qp->rq.head = 0;
313 qp->rq.tail = 0;
314 qp->sq.head = 0;
315 qp->sq.tail = 0;
316
a4cd7ed8 317 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
225c7b1f
RD		 318 if (err)
319 goto err;
320
321 if (pd->uobject) {
322 struct mlx4_ib_create_qp ucmd;
323
324 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
325 err = -EFAULT;
326 goto err;
327 }
328
0e6e7416
RD		 329 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
330
2446304d
EC		 331 err = set_user_sq_size(qp, &ucmd);
332 if (err)
333 goto err;
334
225c7b1f
RD		 335 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
336 qp->buf_size, 0);
337 if (IS_ERR(qp->umem)) {
338 err = PTR_ERR(qp->umem);
339 goto err;
340 }
341
342 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
343 ilog2(qp->umem->page_size), &qp->mtt);
344 if (err)
345 goto err_buf;
346
347 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
348 if (err)
349 goto err_mtt;
350
02d89b87
RD		 351 if (!init_attr->srq) {
352 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
353 ucmd.db_addr, &qp->db);
354 if (err)
355 goto err_mtt;
356 }
225c7b1f 357 } else {
0e6e7416
RD		 358 qp->sq_no_prefetch = 0;
359
2446304d
EC		 360 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
361 if (err)
362 goto err;
363
02d89b87
RD		 364 if (!init_attr->srq) {
365 err = mlx4_ib_db_alloc(dev, &qp->db, 0);
366 if (err)
367 goto err;
225c7b1f 368
02d89b87
RD		 369 *qp->db.db = 0;
370 }
225c7b1f
RD		 371
372 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
373 err = -ENOMEM;
374 goto err_db;
375 }
376
377 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
378 &qp->mtt);
379 if (err)
380 goto err_buf;
381
382 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
383 if (err)
384 goto err_mtt;
385
0e6e7416
RD		 386 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
387 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
225c7b1f
RD		 388
389 if (!qp->sq.wrid || !qp->rq.wrid) {
390 err = -ENOMEM;
391 goto err_wrid;
392 }
393
394 /* We don't support inline sends for kernel QPs (yet) */
395 init_attr->cap.max_inline_data = 0;
396 }
397
398 err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
399 if (err)
400 goto err_wrid;
401
402 /*
403 * Hardware wants QPN written in big-endian order (after
404 * shifting) for send doorbell. Precompute this value to save
405 * a little bit when posting sends.
406 */
407 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
408
409 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
410 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
411 else
412 qp->sq_signal_bits = 0;
413
414 qp->mqp.event = mlx4_ib_qp_event;
415
416 return 0;
417
418err_wrid:
02d89b87 419 if (pd->uobject && !init_attr->srq)
225c7b1f
RD		 420 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
421 else {
422 kfree(qp->sq.wrid);
423 kfree(qp->rq.wrid);
424 }
425
426err_mtt:
427 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
428
429err_buf:
430 if (pd->uobject)
431 ib_umem_release(qp->umem);
432 else
433 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
434
435err_db:
02d89b87 436 if (!pd->uobject && !init_attr->srq)
225c7b1f
RD		 437 mlx4_ib_db_free(dev, &qp->db);
438
439err:
440 return err;
441}
442
443static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
444{
445 switch (state) {
446 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
447 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
448 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
449 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
450 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
451 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
452 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
453 default: return -1;
454 }
455}
456
457static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
458{
459 if (send_cq == recv_cq)
460 spin_lock_irq(&send_cq->lock);
461 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
462 spin_lock_irq(&send_cq->lock);
463 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
464 } else {
465 spin_lock_irq(&recv_cq->lock);
466 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
467 }
468}
469
470static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
471{
472 if (send_cq == recv_cq)
473 spin_unlock_irq(&send_cq->lock);
474 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
475 spin_unlock(&recv_cq->lock);
476 spin_unlock_irq(&send_cq->lock);
477 } else {
478 spin_unlock(&send_cq->lock);
479 spin_unlock_irq(&recv_cq->lock);
480 }
481}
482
483static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
484 int is_user)
485{
486 struct mlx4_ib_cq *send_cq, *recv_cq;
487
488 if (qp->state != IB_QPS_RESET)
489 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
490 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
491 printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
492 qp->mqp.qpn);
493
494 send_cq = to_mcq(qp->ibqp.send_cq);
495 recv_cq = to_mcq(qp->ibqp.recv_cq);
496
497 mlx4_ib_lock_cqs(send_cq, recv_cq);
498
499 if (!is_user) {
500 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
501 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
502 if (send_cq != recv_cq)
503 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
504 }
505
506 mlx4_qp_remove(dev->dev, &qp->mqp);
507
508 mlx4_ib_unlock_cqs(send_cq, recv_cq);
509
510 mlx4_qp_free(dev->dev, &qp->mqp);
511 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
512
513 if (is_user) {
02d89b87
RD		 514 if (!qp->ibqp.srq)
515 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
516 &qp->db);
225c7b1f
RD		 517 ib_umem_release(qp->umem);
518 } else {
519 kfree(qp->sq.wrid);
520 kfree(qp->rq.wrid);
521 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
02d89b87
RD		 522 if (!qp->ibqp.srq)
523 mlx4_ib_db_free(dev, &qp->db);
225c7b1f
RD		 524 }
525}
526
527struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
528 struct ib_qp_init_attr *init_attr,
529 struct ib_udata *udata)
530{
531 struct mlx4_ib_dev *dev = to_mdev(pd->device);
532 struct mlx4_ib_sqp *sqp;
533 struct mlx4_ib_qp *qp;
534 int err;
535
536 switch (init_attr->qp_type) {
537 case IB_QPT_RC:
538 case IB_QPT_UC:
539 case IB_QPT_UD:
540 {
541 qp = kmalloc(sizeof *qp, GFP_KERNEL);
542 if (!qp)
543 return ERR_PTR(-ENOMEM);
544
545 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
546 if (err) {
547 kfree(qp);
548 return ERR_PTR(err);
549 }
550
551 qp->ibqp.qp_num = qp->mqp.qpn;
552
553 break;
554 }
555 case IB_QPT_SMI:
556 case IB_QPT_GSI:
557 {
558 /* Userspace is not allowed to create special QPs: */
559 if (pd->uobject)
560 return ERR_PTR(-EINVAL);
561
562 sqp = kmalloc(sizeof *sqp, GFP_KERNEL);
563 if (!sqp)
564 return ERR_PTR(-ENOMEM);
565
566 qp = &sqp->qp;
567
568 err = create_qp_common(dev, pd, init_attr, udata,
569 dev->dev->caps.sqp_start +
570 (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
571 init_attr->port_num - 1,
572 qp);
573 if (err) {
574 kfree(sqp);
575 return ERR_PTR(err);
576 }
577
578 qp->port = init_attr->port_num;
579 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
580
581 break;
582 }
583 default:
584 /* Don't support raw QPs */
585 return ERR_PTR(-EINVAL);
586 }
587
588 return &qp->ibqp;
589}
590
591int mlx4_ib_destroy_qp(struct ib_qp *qp)
592{
593 struct mlx4_ib_dev *dev = to_mdev(qp->device);
594 struct mlx4_ib_qp *mqp = to_mqp(qp);
595
596 if (is_qp0(dev, mqp))
597 mlx4_CLOSE_PORT(dev->dev, mqp->port);
598
599 destroy_qp_common(dev, mqp, !!qp->pd->uobject);
600
601 if (is_sqp(dev, mqp))
602 kfree(to_msqp(mqp));
603 else
604 kfree(mqp);
605
606 return 0;
607}
608
609static void init_port(struct mlx4_ib_dev *dev, int port)
610{
611 struct mlx4_init_port_param param;
612 int err;
613
614 memset(&param, 0, sizeof param);
615
616 param.port_width_cap = dev->dev->caps.port_width_cap;
617 param.vl_cap = dev->dev->caps.vl_cap;
618 param.mtu = ib_mtu_enum_to_int(dev->dev->caps.mtu_cap);
619 param.max_gid = dev->dev->caps.gid_table_len;
620 param.max_pkey = dev->dev->caps.pkey_table_len;
621
622 err = mlx4_INIT_PORT(dev->dev, &param, port);
623 if (err)
624 printk(KERN_WARNING "INIT_PORT failed, return code %d.\n", err);
625}
626
627static int to_mlx4_st(enum ib_qp_type type)
628{
629 switch (type) {
630 case IB_QPT_RC: return MLX4_QP_ST_RC;
631 case IB_QPT_UC: return MLX4_QP_ST_UC;
632 case IB_QPT_UD: return MLX4_QP_ST_UD;
633 case IB_QPT_SMI:
634 case IB_QPT_GSI: return MLX4_QP_ST_MLX;
635 default: return -1;
636 }
637}
638
65adfa91 639static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 640 int attr_mask)
641{
642 u8 dest_rd_atomic;
643 u32 access_flags;
644 u32 hw_access_flags = 0;
645
646 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
647 dest_rd_atomic = attr->max_dest_rd_atomic;
648 else
649 dest_rd_atomic = qp->resp_depth;
650
651 if (attr_mask & IB_QP_ACCESS_FLAGS)
652 access_flags = attr->qp_access_flags;
653 else
654 access_flags = qp->atomic_rd_en;
655
656 if (!dest_rd_atomic)
657 access_flags &= IB_ACCESS_REMOTE_WRITE;
658
659 if (access_flags & IB_ACCESS_REMOTE_READ)
660 hw_access_flags |= MLX4_QP_BIT_RRE;
661 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
662 hw_access_flags |= MLX4_QP_BIT_RAE;
663 if (access_flags & IB_ACCESS_REMOTE_WRITE)
664 hw_access_flags |= MLX4_QP_BIT_RWE;
665
666 return cpu_to_be32(hw_access_flags);
667}
668
65adfa91 669static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 670 int attr_mask)
671{
672 if (attr_mask & IB_QP_PKEY_INDEX)
673 sqp->pkey_index = attr->pkey_index;
674 if (attr_mask & IB_QP_QKEY)
675 sqp->qkey = attr->qkey;
676 if (attr_mask & IB_QP_SQ_PSN)
677 sqp->send_psn = attr->sq_psn;
678}
679
680static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
681{
682 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
683}
684
65adfa91 685static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
225c7b1f
RD		 686 struct mlx4_qp_path *path, u8 port)
687{
688 path->grh_mylmc = ah->src_path_bits & 0x7f;
689 path->rlid = cpu_to_be16(ah->dlid);
690 if (ah->static_rate) {
691 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
692 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
693 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
694 --path->static_rate;
695 } else
696 path->static_rate = 0;
697 path->counter_index = 0xff;
698
699 if (ah->ah_flags & IB_AH_GRH) {
700 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len) {
701 printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
702 ah->grh.sgid_index, dev->dev->caps.gid_table_len - 1);
703 return -1;
704 }
705
706 path->grh_mylmc |= 1 << 7;
707 path->mgid_index = ah->grh.sgid_index;
708 path->hop_limit = ah->grh.hop_limit;
709 path->tclass_flowlabel =
710 cpu_to_be32((ah->grh.traffic_class << 20) |
711 (ah->grh.flow_label));
712 memcpy(path->rgid, ah->grh.dgid.raw, 16);
713 }
714
715 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
716 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
717
718 return 0;
719}
720
65adfa91
MT		 721static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
722 const struct ib_qp_attr *attr, int attr_mask,
723 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 724{
725 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
726 struct mlx4_ib_qp *qp = to_mqp(ibqp);
727 struct mlx4_qp_context *context;
728 enum mlx4_qp_optpar optpar = 0;
225c7b1f
RD		 729 int sqd_event;
730 int err = -EINVAL;
731
732 context = kzalloc(sizeof *context, GFP_KERNEL);
733 if (!context)
734 return -ENOMEM;
735
225c7b1f
RD		 736 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
737 (to_mlx4_st(ibqp->qp_type) << 16));
738 context->flags |= cpu_to_be32(1 << 8); /* DE? */
739
740 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
741 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
742 else {
743 optpar |= MLX4_QP_OPTPAR_PM_STATE;
744 switch (attr->path_mig_state) {
745 case IB_MIG_MIGRATED:
746 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
747 break;
748 case IB_MIG_REARM:
749 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
750 break;
751 case IB_MIG_ARMED:
752 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
753 break;
754 }
755 }
756
757 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
758 ibqp->qp_type == IB_QPT_UD)
759 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
760 else if (attr_mask & IB_QP_PATH_MTU) {
761 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
762 printk(KERN_ERR "path MTU (%u) is invalid\n",
763 attr->path_mtu);
764 return -EINVAL;
765 }
766 context->mtu_msgmax = (attr->path_mtu << 5) | 31;
767 }
768
0e6e7416
RD		 769 if (qp->rq.wqe_cnt)
770 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 771 context->rq_size_stride |= qp->rq.wqe_shift - 4;
772
0e6e7416
RD		 773 if (qp->sq.wqe_cnt)
774 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 775 context->sq_size_stride |= qp->sq.wqe_shift - 4;
776
0e6e7416
RD		 777 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
778 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
779
225c7b1f
RD		 780 if (qp->ibqp.uobject)
781 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
782 else
783 context->usr_page = cpu_to_be32(dev->priv_uar.index);
784
785 if (attr_mask & IB_QP_DEST_QPN)
786 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
787
788 if (attr_mask & IB_QP_PORT) {
789 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
790 !(attr_mask & IB_QP_AV)) {
791 mlx4_set_sched(&context->pri_path, attr->port_num);
792 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
793 }
794 }
795
796 if (attr_mask & IB_QP_PKEY_INDEX) {
797 context->pri_path.pkey_index = attr->pkey_index;
798 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
799 }
800
225c7b1f
RD		 801 if (attr_mask & IB_QP_AV) {
802 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
803 attr_mask & IB_QP_PORT ? attr->port_num : qp->port)) {
804 err = -EINVAL;
805 goto out;
806 }
807
808 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
809 MLX4_QP_OPTPAR_SCHED_QUEUE);
810 }
811
812 if (attr_mask & IB_QP_TIMEOUT) {
813 context->pri_path.ackto = attr->timeout << 3;
814 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
815 }
816
817 if (attr_mask & IB_QP_ALT_PATH) {
818 if (attr->alt_pkey_index >= dev->dev->caps.pkey_table_len)
819 return -EINVAL;
820
821 if (attr->alt_port_num == 0 ||
822 attr->alt_port_num > dev->dev->caps.num_ports)
823 return -EINVAL;
824
825 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
826 attr->alt_port_num))
827 return -EINVAL;
828
829 context->alt_path.pkey_index = attr->alt_pkey_index;
830 context->alt_path.ackto = attr->alt_timeout << 3;
831 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
832 }
833
834 context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
835 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53
JM		 836
837 if (attr_mask & IB_QP_RNR_RETRY) {
838 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
839 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
840 }
841
225c7b1f
RD		 842 if (attr_mask & IB_QP_RETRY_CNT) {
843 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
844 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
845 }
846
847 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
848 if (attr->max_rd_atomic)
849 context->params1 |=
850 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
851 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
852 }
853
854 if (attr_mask & IB_QP_SQ_PSN)
855 context->next_send_psn = cpu_to_be32(attr->sq_psn);
856
857 context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
858
859 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
860 if (attr->max_dest_rd_atomic)
861 context->params2 |=
862 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
863 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
864 }
865
866 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
867 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
868 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
869 }
870
871 if (ibqp->srq)
872 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
873
874 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
875 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
876 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
877 }
878 if (attr_mask & IB_QP_RQ_PSN)
879 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
880
881 context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
882
883 if (attr_mask & IB_QP_QKEY) {
884 context->qkey = cpu_to_be32(attr->qkey);
885 optpar |= MLX4_QP_OPTPAR_Q_KEY;
886 }
887
888 if (ibqp->srq)
889 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
890
02d89b87 891 if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 892 context->db_rec_addr = cpu_to_be64(qp->db.dma);
893
894 if (cur_state == IB_QPS_INIT &&
895 new_state == IB_QPS_RTR &&
896 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
897 ibqp->qp_type == IB_QPT_UD)) {
898 context->pri_path.sched_queue = (qp->port - 1) << 6;
899 if (is_qp0(dev, qp))
900 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
901 else
902 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
903 }
904
905 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
906 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
907 sqd_event = 1;
908 else
909 sqd_event = 0;
910
c0be5fb5
EC		 911 /*
912 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 913 * ownership bits of the send queue are set and the SQ
914 * headroom is stamped so that the hardware doesn't start
915 * processing stale work requests.
c0be5fb5
EC		 916 */
917 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
918 struct mlx4_wqe_ctrl_seg *ctrl;
919 int i;
920
0e6e7416 921 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 922 ctrl = get_send_wqe(qp, i);
923 ctrl->owner_opcode = cpu_to_be32(1 << 31);
0e6e7416
RD		 924
925 stamp_send_wqe(qp, i);
c0be5fb5
EC		 926 }
927 }
928
225c7b1f
RD		 929 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
930 to_mlx4_state(new_state), context, optpar,
931 sqd_event, &qp->mqp);
932 if (err)
933 goto out;
934
935 qp->state = new_state;
936
937 if (attr_mask & IB_QP_ACCESS_FLAGS)
938 qp->atomic_rd_en = attr->qp_access_flags;
939 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
940 qp->resp_depth = attr->max_dest_rd_atomic;
941 if (attr_mask & IB_QP_PORT)
942 qp->port = attr->port_num;
943 if (attr_mask & IB_QP_ALT_PATH)
944 qp->alt_port = attr->alt_port_num;
945
946 if (is_sqp(dev, qp))
947 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
948
949 /*
950 * If we moved QP0 to RTR, bring the IB link up; if we moved
951 * QP0 to RESET or ERROR, bring the link back down.
952 */
953 if (is_qp0(dev, qp)) {
954 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
955 init_port(dev, qp->port);
956
957 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
958 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
959 mlx4_CLOSE_PORT(dev->dev, qp->port);
960 }
961
962 /*
963 * If we moved a kernel QP to RESET, clean up all old CQ
964 * entries and reinitialize the QP.
965 */
966 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
967 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
968 ibqp->srq ? to_msrq(ibqp->srq): NULL);
969 if (ibqp->send_cq != ibqp->recv_cq)
970 mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
971
972 qp->rq.head = 0;
973 qp->rq.tail = 0;
974 qp->sq.head = 0;
975 qp->sq.tail = 0;
02d89b87
RD		 976 if (!ibqp->srq)
977 *qp->db.db = 0;
225c7b1f
RD		 978 }
979
980out:
225c7b1f
RD		 981 kfree(context);
982 return err;
983}
984
65adfa91
MT		 985static const struct ib_qp_attr mlx4_ib_qp_attr = { .port_num = 1 };
986static const int mlx4_ib_qp_attr_mask_table[IB_QPT_UD + 1] = {
987 [IB_QPT_UD] = (IB_QP_PKEY_INDEX |
988 IB_QP_PORT |
989 IB_QP_QKEY),
990 [IB_QPT_UC] = (IB_QP_PKEY_INDEX |
991 IB_QP_PORT |
992 IB_QP_ACCESS_FLAGS),
993 [IB_QPT_RC] = (IB_QP_PKEY_INDEX |
994 IB_QP_PORT |
995 IB_QP_ACCESS_FLAGS),
996 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX |
997 IB_QP_QKEY),
998 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX |
999 IB_QP_QKEY),
1000};
1001
1002int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1003 int attr_mask, struct ib_udata *udata)
1004{
1005 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1006 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1007 enum ib_qp_state cur_state, new_state;
1008 int err = -EINVAL;
1009
1010 mutex_lock(&qp->mutex);
1011
1012 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1013 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1014
1015 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1016 goto out;
1017
1018 if ((attr_mask & IB_QP_PKEY_INDEX) &&
1019 attr->pkey_index >= dev->dev->caps.pkey_table_len) {
1020 goto out;
1021 }
1022
1023 if ((attr_mask & IB_QP_PORT) &&
1024 (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1025 goto out;
1026 }
1027
1028 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1029 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1030 goto out;
1031 }
1032
1033 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1034 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1035 goto out;
1036 }
1037
1038 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1039 err = 0;
1040 goto out;
1041 }
1042
1043 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) {
1044 err = __mlx4_ib_modify_qp(ibqp, &mlx4_ib_qp_attr,
1045 mlx4_ib_qp_attr_mask_table[ibqp->qp_type],
1046 IB_QPS_RESET, IB_QPS_INIT);
1047 if (err)
1048 goto out;
1049 cur_state = IB_QPS_INIT;
1050 }
1051
1052 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1053
1054out:
1055 mutex_unlock(&qp->mutex);
1056 return err;
1057}
1058
225c7b1f
RD		 1059static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1060 void *wqe)
1061{
1062 struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1063 struct mlx4_wqe_mlx_seg *mlx = wqe;
1064 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1065 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1066 u16 pkey;
1067 int send_size;
1068 int header_size;
1069 int i;
1070
1071 send_size = 0;
1072 for (i = 0; i < wr->num_sge; ++i)
1073 send_size += wr->sg_list[i].length;
1074
1075 ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1076
1077 sqp->ud_header.lrh.service_level =
1078 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1079 sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1080 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.g_slid & 0x7f);
1081 if (mlx4_ib_ah_grh_present(ah)) {
1082 sqp->ud_header.grh.traffic_class =
1083 (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1084 sqp->ud_header.grh.flow_label =
1085 ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
15261303 1086 sqp->ud_header.grh.hop_limit = ah->av.hop_limit;
225c7b1f
RD		 1087 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1088 ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1089 memcpy(sqp->ud_header.grh.destination_gid.raw,
1090 ah->av.dgid, 16);
1091 }
1092
1093 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1094 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1095 (sqp->ud_header.lrh.destination_lid ==
1096 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1097 (sqp->ud_header.lrh.service_level << 8));
1098 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1099
1100 switch (wr->opcode) {
1101 case IB_WR_SEND:
1102 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1103 sqp->ud_header.immediate_present = 0;
1104 break;
1105 case IB_WR_SEND_WITH_IMM:
1106 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1107 sqp->ud_header.immediate_present = 1;
1108 sqp->ud_header.immediate_data = wr->imm_data;
1109 break;
1110 default:
1111 return -EINVAL;
1112 }
1113
1114 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1115 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1116 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1117 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1118 if (!sqp->qp.ibqp.qp_num)
1119 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1120 else
1121 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1122 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1123 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1124 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1125 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1126 sqp->qkey : wr->wr.ud.remote_qkey);
1127 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1128
1129 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1130
1131 if (0) {
1132 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1133 for (i = 0; i < header_size / 4; ++i) {
1134 if (i % 8 == 0)
1135 printk(" [%02x] ", i * 4);
1136 printk(" %08x",
1137 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1138 if ((i + 1) % 8 == 0)
1139 printk("\n");
1140 }
1141 printk("\n");
1142 }
1143
1144 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1145 memcpy(inl + 1, sqp->header_buf, header_size);
1146
1147 return ALIGN(sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1148}
1149
1150static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1151{
1152 unsigned cur;
1153 struct mlx4_ib_cq *cq;
1154
1155 cur = wq->head - wq->tail;
0e6e7416 1156 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 1157 return 0;
1158
1159 cq = to_mcq(ib_cq);
1160 spin_lock(&cq->lock);
1161 cur = wq->head - wq->tail;
1162 spin_unlock(&cq->lock);
1163
0e6e7416 1164 return cur + nreq >= wq->max_post;
225c7b1f
RD		 1165}
1166
1167int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1168 struct ib_send_wr **bad_wr)
1169{
1170 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1171 void *wqe;
1172 struct mlx4_wqe_ctrl_seg *ctrl;
1173 unsigned long flags;
1174 int nreq;
1175 int err = 0;
1176 int ind;
1177 int size;
1178 int i;
1179
1180 spin_lock_irqsave(&qp->rq.lock, flags);
1181
1182 ind = qp->sq.head;
1183
1184 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1185 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1186 err = -ENOMEM;
1187 *bad_wr = wr;
1188 goto out;
1189 }
1190
1191 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1192 err = -EINVAL;
1193 *bad_wr = wr;
1194 goto out;
1195 }
1196
0e6e7416
RD		 1197 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
1198 qp->sq.wrid[ind & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 1199
1200 ctrl->srcrb_flags =
1201 (wr->send_flags & IB_SEND_SIGNALED ?
1202 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1203 (wr->send_flags & IB_SEND_SOLICITED ?
1204 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1205 qp->sq_signal_bits;
1206
1207 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1208 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1209 ctrl->imm = wr->imm_data;
1210 else
1211 ctrl->imm = 0;
1212
1213 wqe += sizeof *ctrl;
1214 size = sizeof *ctrl / 16;
1215
1216 switch (ibqp->qp_type) {
1217 case IB_QPT_RC:
1218 case IB_QPT_UC:
1219 switch (wr->opcode) {
1220 case IB_WR_ATOMIC_CMP_AND_SWP:
1221 case IB_WR_ATOMIC_FETCH_AND_ADD:
1222 ((struct mlx4_wqe_raddr_seg *) wqe)->raddr =
1223 cpu_to_be64(wr->wr.atomic.remote_addr);
1224 ((struct mlx4_wqe_raddr_seg *) wqe)->rkey =
1225 cpu_to_be32(wr->wr.atomic.rkey);
1226 ((struct mlx4_wqe_raddr_seg *) wqe)->reserved = 0;
1227
1228 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1229
1230 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1231 ((struct mlx4_wqe_atomic_seg *) wqe)->swap_add =
1232 cpu_to_be64(wr->wr.atomic.swap);
1233 ((struct mlx4_wqe_atomic_seg *) wqe)->compare =
1234 cpu_to_be64(wr->wr.atomic.compare_add);
1235 } else {
1236 ((struct mlx4_wqe_atomic_seg *) wqe)->swap_add =
1237 cpu_to_be64(wr->wr.atomic.compare_add);
1238 ((struct mlx4_wqe_atomic_seg *) wqe)->compare = 0;
1239 }
1240
1241 wqe += sizeof (struct mlx4_wqe_atomic_seg);
1242 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1243 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1244
1245 break;
1246
1247 case IB_WR_RDMA_READ:
1248 case IB_WR_RDMA_WRITE:
1249 case IB_WR_RDMA_WRITE_WITH_IMM:
1250 ((struct mlx4_wqe_raddr_seg *) wqe)->raddr =
1251 cpu_to_be64(wr->wr.rdma.remote_addr);
1252 ((struct mlx4_wqe_raddr_seg *) wqe)->rkey =
1253 cpu_to_be32(wr->wr.rdma.rkey);
1254 ((struct mlx4_wqe_raddr_seg *) wqe)->reserved = 0;
1255
1256 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1257 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1258
1259 break;
1260
1261 default:
1262 /* No extra segments required for sends */
1263 break;
1264 }
1265 break;
1266
1267 case IB_QPT_UD:
1268 memcpy(((struct mlx4_wqe_datagram_seg *) wqe)->av,
1269 &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1270 ((struct mlx4_wqe_datagram_seg *) wqe)->dqpn =
1271 cpu_to_be32(wr->wr.ud.remote_qpn);
1272 ((struct mlx4_wqe_datagram_seg *) wqe)->qkey =
1273 cpu_to_be32(wr->wr.ud.remote_qkey);
1274
1275 wqe += sizeof (struct mlx4_wqe_datagram_seg);
1276 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1277 break;
1278
1279 case IB_QPT_SMI:
1280 case IB_QPT_GSI:
1281 err = build_mlx_header(to_msqp(qp), wr, ctrl);
1282 if (err < 0) {
1283 *bad_wr = wr;
1284 goto out;
1285 }
1286 wqe += err;
1287 size += err / 16;
1288
1289 err = 0;
1290 break;
1291
1292 default:
1293 break;
1294 }
1295
1296 for (i = 0; i < wr->num_sge; ++i) {
1297 ((struct mlx4_wqe_data_seg *) wqe)->byte_count =
1298 cpu_to_be32(wr->sg_list[i].length);
1299 ((struct mlx4_wqe_data_seg *) wqe)->lkey =
1300 cpu_to_be32(wr->sg_list[i].lkey);
1301 ((struct mlx4_wqe_data_seg *) wqe)->addr =
1302 cpu_to_be64(wr->sg_list[i].addr);
1303
1304 wqe += sizeof (struct mlx4_wqe_data_seg);
1305 size += sizeof (struct mlx4_wqe_data_seg) / 16;
1306 }
1307
1308 /* Add one more inline data segment for ICRC for MLX sends */
1309 if (qp->ibqp.qp_type == IB_QPT_SMI || qp->ibqp.qp_type == IB_QPT_GSI) {
1310 ((struct mlx4_wqe_inline_seg *) wqe)->byte_count =
1311 cpu_to_be32((1 << 31) | 4);
1312 ((u32 *) wqe)[1] = 0;
1313 wqe += sizeof (struct mlx4_wqe_data_seg);
1314 size += sizeof (struct mlx4_wqe_data_seg) / 16;
1315 }
1316
1317 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1318 MLX4_WQE_CTRL_FENCE : 0) | size;
1319
1320 /*
1321 * Make sure descriptor is fully written before
1322 * setting ownership bit (because HW can start
1323 * executing as soon as we do).
1324 */
1325 wmb();
1326
59b0ed12 1327 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
225c7b1f
RD		 1328 err = -EINVAL;
1329 goto out;
1330 }
1331
1332 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
0e6e7416
RD		 1333 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
1334
1335 /*
1336 * We can improve latency by not stamping the last
1337 * send queue WQE until after ringing the doorbell, so
1338 * only stamp here if there are still more WQEs to post.
1339 */
1340 if (wr->next)
1341 stamp_send_wqe(qp, (ind + qp->sq_spare_wqes) &
1342 (qp->sq.wqe_cnt - 1));
225c7b1f
RD		 1343
1344 ++ind;
1345 }
1346
1347out:
1348 if (likely(nreq)) {
1349 qp->sq.head += nreq;
1350
1351 /*
1352 * Make sure that descriptors are written before
1353 * doorbell record.
1354 */
1355 wmb();
1356
1357 writel(qp->doorbell_qpn,
1358 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1359
1360 /*
1361 * Make sure doorbells don't leak out of SQ spinlock
1362 * and reach the HCA out of order.
1363 */
1364 mmiowb();
0e6e7416
RD		 1365
1366 stamp_send_wqe(qp, (ind + qp->sq_spare_wqes - 1) &
1367 (qp->sq.wqe_cnt - 1));
225c7b1f
RD		 1368 }
1369
1370 spin_unlock_irqrestore(&qp->rq.lock, flags);
1371
1372 return err;
1373}
1374
1375int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1376 struct ib_recv_wr **bad_wr)
1377{
1378 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1379 struct mlx4_wqe_data_seg *scat;
1380 unsigned long flags;
1381 int err = 0;
1382 int nreq;
1383 int ind;
1384 int i;
1385
1386 spin_lock_irqsave(&qp->rq.lock, flags);
1387
0e6e7416 1388 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 1389
1390 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1391 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1392 err = -ENOMEM;
1393 *bad_wr = wr;
1394 goto out;
1395 }
1396
1397 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1398 err = -EINVAL;
1399 *bad_wr = wr;
1400 goto out;
1401 }
1402
1403 scat = get_recv_wqe(qp, ind);
1404
1405 for (i = 0; i < wr->num_sge; ++i) {
1406 scat[i].byte_count = cpu_to_be32(wr->sg_list[i].length);
1407 scat[i].lkey = cpu_to_be32(wr->sg_list[i].lkey);
1408 scat[i].addr = cpu_to_be64(wr->sg_list[i].addr);
1409 }
1410
1411 if (i < qp->rq.max_gs) {
1412 scat[i].byte_count = 0;
1413 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
1414 scat[i].addr = 0;
1415 }
1416
1417 qp->rq.wrid[ind] = wr->wr_id;
1418
0e6e7416 1419 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 1420 }
1421
1422out:
1423 if (likely(nreq)) {
1424 qp->rq.head += nreq;
1425
1426 /*
1427 * Make sure that descriptors are written before
1428 * doorbell record.
1429 */
1430 wmb();
1431
1432 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1433 }
1434
1435 spin_unlock_irqrestore(&qp->rq.lock, flags);
1436
1437 return err;
1438}
Linux 6.x block layer and io_uring tree(s)