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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #ifndef MLX4_IB_H | |
35 | #define MLX4_IB_H | |
36 | ||
37 | #include <linux/compiler.h> | |
38 | #include <linux/list.h> | |
63019d93 | 39 | #include <linux/mutex.h> |
b9c5d6a6 | 40 | #include <linux/idr.h> |
73d68002 | 41 | #include <linux/notifier.h> |
225c7b1f RD |
42 | |
43 | #include <rdma/ib_verbs.h> | |
44 | #include <rdma/ib_umem.h> | |
b9c5d6a6 | 45 | #include <rdma/ib_mad.h> |
a0c64a17 | 46 | #include <rdma/ib_sa.h> |
225c7b1f RD |
47 | |
48 | #include <linux/mlx4/device.h> | |
49 | #include <linux/mlx4/doorbell.h> | |
3078f5f1 | 50 | #include <linux/mlx4/qp.h> |
34d9a270 | 51 | #include <linux/mlx4/cq.h> |
225c7b1f | 52 | |
b1d8eb5a JM |
53 | #define MLX4_IB_DRV_NAME "mlx4_ib" |
54 | ||
55 | #ifdef pr_fmt | |
56 | #undef pr_fmt | |
57 | #endif | |
58 | #define pr_fmt(fmt) "<" MLX4_IB_DRV_NAME "> %s: " fmt, __func__ | |
59 | ||
60 | #define mlx4_ib_warn(ibdev, format, arg...) \ | |
d66c88a8 | 61 | dev_warn((ibdev)->dev.parent, MLX4_IB_DRV_NAME ": " format, ## arg) |
b1d8eb5a | 62 | |
fc2d0044 SG |
63 | enum { |
64 | MLX4_IB_SQ_MIN_WQE_SHIFT = 6, | |
65 | MLX4_IB_MAX_HEADROOM = 2048 | |
66 | }; | |
67 | ||
68 | #define MLX4_IB_SQ_HEADROOM(shift) ((MLX4_IB_MAX_HEADROOM >> (shift)) + 1) | |
69 | #define MLX4_IB_SQ_MAX_SPARE (MLX4_IB_SQ_HEADROOM(MLX4_IB_SQ_MIN_WQE_SHIFT)) | |
70 | ||
a0c64a17 JM |
71 | /*module param to indicate if SM assigns the alias_GUID*/ |
72 | extern int mlx4_ib_sm_guid_assign; | |
73 | ||
c1c98501 MB |
74 | #define MLX4_IB_UC_STEER_QPN_ALIGN 1 |
75 | #define MLX4_IB_UC_MAX_NUM_QPS 256 | |
ae184dde YH |
76 | |
77 | enum hw_bar_type { | |
78 | HW_BAR_BF, | |
79 | HW_BAR_DB, | |
80 | HW_BAR_CLOCK, | |
81 | HW_BAR_COUNT | |
82 | }; | |
83 | ||
225c7b1f RD |
84 | struct mlx4_ib_ucontext { |
85 | struct ib_ucontext ibucontext; | |
86 | struct mlx4_uar uar; | |
87 | struct list_head db_page_list; | |
88 | struct mutex db_page_mutex; | |
400b1ebc GL |
89 | struct list_head wqn_ranges_list; |
90 | struct mutex wqn_ranges_mutex; /* protect wqn_ranges_list */ | |
225c7b1f RD |
91 | }; |
92 | ||
93 | struct mlx4_ib_pd { | |
94 | struct ib_pd ibpd; | |
95 | u32 pdn; | |
96 | }; | |
97 | ||
012a8ff5 SH |
98 | struct mlx4_ib_xrcd { |
99 | struct ib_xrcd ibxrcd; | |
100 | u32 xrcdn; | |
101 | struct ib_pd *pd; | |
102 | struct ib_cq *cq; | |
103 | }; | |
104 | ||
225c7b1f RD |
105 | struct mlx4_ib_cq_buf { |
106 | struct mlx4_buf buf; | |
107 | struct mlx4_mtt mtt; | |
08ff3235 | 108 | int entry_size; |
225c7b1f RD |
109 | }; |
110 | ||
bbf8eed1 VS |
111 | struct mlx4_ib_cq_resize { |
112 | struct mlx4_ib_cq_buf buf; | |
113 | int cqe; | |
114 | }; | |
115 | ||
225c7b1f RD |
116 | struct mlx4_ib_cq { |
117 | struct ib_cq ibcq; | |
118 | struct mlx4_cq mcq; | |
119 | struct mlx4_ib_cq_buf buf; | |
bbf8eed1 | 120 | struct mlx4_ib_cq_resize *resize_buf; |
6296883c | 121 | struct mlx4_db db; |
225c7b1f | 122 | spinlock_t lock; |
bbf8eed1 | 123 | struct mutex resize_mutex; |
225c7b1f | 124 | struct ib_umem *umem; |
bbf8eed1 | 125 | struct ib_umem *resize_umem; |
4b664c43 | 126 | int create_flags; |
35f05dab YH |
127 | /* List of qps that it serves.*/ |
128 | struct list_head send_qp_list; | |
129 | struct list_head recv_qp_list; | |
225c7b1f RD |
130 | }; |
131 | ||
1b2cd0fc SG |
132 | #define MLX4_MR_PAGES_ALIGN 0x40 |
133 | ||
225c7b1f RD |
134 | struct mlx4_ib_mr { |
135 | struct ib_mr ibmr; | |
1b2cd0fc SG |
136 | __be64 *pages; |
137 | dma_addr_t page_map; | |
138 | u32 npages; | |
139 | u32 max_pages; | |
225c7b1f RD |
140 | struct mlx4_mr mmr; |
141 | struct ib_umem *umem; | |
cbc9355a | 142 | size_t page_map_size; |
225c7b1f RD |
143 | }; |
144 | ||
804d6a89 SM |
145 | struct mlx4_ib_mw { |
146 | struct ib_mw ibmw; | |
147 | struct mlx4_mw mmw; | |
148 | }; | |
149 | ||
146d6e19 MS |
150 | #define MAX_REGS_PER_FLOW 2 |
151 | ||
152 | struct mlx4_flow_reg_id { | |
153 | u64 id; | |
154 | u64 mirror; | |
155 | }; | |
156 | ||
f77c0162 HHZ |
157 | struct mlx4_ib_flow { |
158 | struct ib_flow ibflow; | |
159 | /* translating DMFS verbs sniffer rule to FW API requires two reg IDs */ | |
146d6e19 | 160 | struct mlx4_flow_reg_id reg_id[MAX_REGS_PER_FLOW]; |
f77c0162 HHZ |
161 | }; |
162 | ||
225c7b1f RD |
163 | struct mlx4_ib_wq { |
164 | u64 *wrid; | |
165 | spinlock_t lock; | |
0e6e7416 RD |
166 | int wqe_cnt; |
167 | int max_post; | |
225c7b1f RD |
168 | int max_gs; |
169 | int offset; | |
170 | int wqe_shift; | |
171 | unsigned head; | |
172 | unsigned tail; | |
173 | }; | |
174 | ||
e1b866c6 MS |
175 | enum { |
176 | MLX4_IB_QP_CREATE_ROCE_V2_GSI = IB_QP_CREATE_RESERVED_START | |
177 | }; | |
178 | ||
b832be1e | 179 | enum mlx4_ib_qp_flags { |
1ffeb2eb JM |
180 | MLX4_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, |
181 | MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, | |
c1c98501 | 182 | MLX4_IB_QP_NETIF = IB_QP_CREATE_NETIF_QP, |
6d06c9aa | 183 | MLX4_IB_QP_SCATTER_FCS = IB_QP_CREATE_SCATTER_FCS, |
e1b866c6 MS |
184 | |
185 | /* Mellanox specific flags start from IB_QP_CREATE_RESERVED_START */ | |
186 | MLX4_IB_ROCE_V2_GSI_QP = MLX4_IB_QP_CREATE_ROCE_V2_GSI, | |
1ffeb2eb JM |
187 | MLX4_IB_SRIOV_TUNNEL_QP = 1 << 30, |
188 | MLX4_IB_SRIOV_SQP = 1 << 31, | |
b832be1e EC |
189 | }; |
190 | ||
fa417f7b EC |
191 | struct mlx4_ib_gid_entry { |
192 | struct list_head list; | |
193 | union ib_gid gid; | |
194 | int added; | |
195 | u8 port; | |
196 | }; | |
197 | ||
1ffeb2eb JM |
198 | enum mlx4_ib_qp_type { |
199 | /* | |
200 | * IB_QPT_SMI and IB_QPT_GSI have to be the first two entries | |
201 | * here (and in that order) since the MAD layer uses them as | |
202 | * indices into a 2-entry table. | |
203 | */ | |
204 | MLX4_IB_QPT_SMI = IB_QPT_SMI, | |
205 | MLX4_IB_QPT_GSI = IB_QPT_GSI, | |
206 | ||
207 | MLX4_IB_QPT_RC = IB_QPT_RC, | |
208 | MLX4_IB_QPT_UC = IB_QPT_UC, | |
209 | MLX4_IB_QPT_UD = IB_QPT_UD, | |
210 | MLX4_IB_QPT_RAW_IPV6 = IB_QPT_RAW_IPV6, | |
211 | MLX4_IB_QPT_RAW_ETHERTYPE = IB_QPT_RAW_ETHERTYPE, | |
212 | MLX4_IB_QPT_RAW_PACKET = IB_QPT_RAW_PACKET, | |
213 | MLX4_IB_QPT_XRC_INI = IB_QPT_XRC_INI, | |
214 | MLX4_IB_QPT_XRC_TGT = IB_QPT_XRC_TGT, | |
215 | ||
216 | MLX4_IB_QPT_PROXY_SMI_OWNER = 1 << 16, | |
217 | MLX4_IB_QPT_PROXY_SMI = 1 << 17, | |
218 | MLX4_IB_QPT_PROXY_GSI = 1 << 18, | |
219 | MLX4_IB_QPT_TUN_SMI_OWNER = 1 << 19, | |
220 | MLX4_IB_QPT_TUN_SMI = 1 << 20, | |
221 | MLX4_IB_QPT_TUN_GSI = 1 << 21, | |
222 | }; | |
223 | ||
224 | #define MLX4_IB_QPT_ANY_SRIOV (MLX4_IB_QPT_PROXY_SMI_OWNER | \ | |
225 | MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER | \ | |
226 | MLX4_IB_QPT_TUN_SMI | MLX4_IB_QPT_TUN_GSI) | |
227 | ||
0a9a0188 JM |
228 | enum mlx4_ib_mad_ifc_flags { |
229 | MLX4_MAD_IFC_IGNORE_MKEY = 1, | |
230 | MLX4_MAD_IFC_IGNORE_BKEY = 2, | |
231 | MLX4_MAD_IFC_IGNORE_KEYS = (MLX4_MAD_IFC_IGNORE_MKEY | | |
232 | MLX4_MAD_IFC_IGNORE_BKEY), | |
233 | MLX4_MAD_IFC_NET_VIEW = 4, | |
234 | }; | |
235 | ||
fc06573d | 236 | enum { |
0ae207fb HB |
237 | MLX4_NUM_TUNNEL_BUFS = 512, |
238 | MLX4_NUM_WIRE_BUFS = 2048, | |
fc06573d JM |
239 | }; |
240 | ||
1ffeb2eb JM |
241 | struct mlx4_ib_tunnel_header { |
242 | struct mlx4_av av; | |
243 | __be32 remote_qpn; | |
244 | __be32 qkey; | |
245 | __be16 vlan; | |
246 | u8 mac[6]; | |
247 | __be16 pkey_index; | |
248 | u8 reserved[6]; | |
249 | }; | |
250 | ||
251 | struct mlx4_ib_buf { | |
252 | void *addr; | |
253 | dma_addr_t map; | |
254 | }; | |
255 | ||
256 | struct mlx4_rcv_tunnel_hdr { | |
257 | __be32 flags_src_qp; /* flags[6:5] is defined for VLANs: | |
258 | * 0x0 - no vlan was in the packet | |
259 | * 0x01 - C-VLAN was in the packet */ | |
260 | u8 g_ml_path; /* gid bit stands for ipv6/4 header in RoCE */ | |
261 | u8 reserved; | |
262 | __be16 pkey_index; | |
263 | __be16 sl_vid; | |
264 | __be16 slid_mac_47_32; | |
265 | __be32 mac_31_0; | |
266 | }; | |
267 | ||
268 | struct mlx4_ib_proxy_sqp_hdr { | |
269 | struct ib_grh grh; | |
270 | struct mlx4_rcv_tunnel_hdr tun; | |
271 | } __packed; | |
272 | ||
2f5bb473 JM |
273 | struct mlx4_roce_smac_vlan_info { |
274 | u64 smac; | |
275 | int smac_index; | |
276 | int smac_port; | |
277 | u64 candidate_smac; | |
278 | int candidate_smac_index; | |
279 | int candidate_smac_port; | |
280 | u16 vid; | |
281 | int vlan_index; | |
282 | int vlan_port; | |
283 | u16 candidate_vid; | |
284 | int candidate_vlan_index; | |
285 | int candidate_vlan_port; | |
286 | int update_vid; | |
287 | }; | |
288 | ||
400b1ebc GL |
289 | struct mlx4_wqn_range { |
290 | int base_wqn; | |
291 | int size; | |
292 | int refcount; | |
293 | bool dirty; | |
294 | struct list_head list; | |
295 | }; | |
296 | ||
3078f5f1 GL |
297 | struct mlx4_ib_rss { |
298 | unsigned int base_qpn_tbl_sz; | |
299 | u8 flags; | |
300 | u8 rss_key[MLX4_EN_RSS_KEY_SIZE]; | |
301 | }; | |
302 | ||
915ec7ed LR |
303 | enum { |
304 | /* | |
305 | * Largest possible UD header: send with GRH and immediate | |
306 | * data plus 18 bytes for an Ethernet header with VLAN/802.1Q | |
307 | * tag. (LRH would only use 8 bytes, so Ethernet is the | |
308 | * biggest case) | |
309 | */ | |
310 | MLX4_IB_UD_HEADER_SIZE = 82, | |
311 | MLX4_IB_LSO_HEADER_SPARE = 128, | |
312 | }; | |
313 | ||
314 | struct mlx4_ib_sqp { | |
315 | int pkey_index; | |
316 | u32 qkey; | |
317 | u32 send_psn; | |
318 | struct ib_ud_header ud_header; | |
319 | u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; | |
320 | struct ib_qp *roce_v2_gsi; | |
321 | }; | |
322 | ||
225c7b1f | 323 | struct mlx4_ib_qp { |
400b1ebc GL |
324 | union { |
325 | struct ib_qp ibqp; | |
326 | struct ib_wq ibwq; | |
327 | }; | |
225c7b1f RD |
328 | struct mlx4_qp mqp; |
329 | struct mlx4_buf buf; | |
330 | ||
6296883c | 331 | struct mlx4_db db; |
225c7b1f RD |
332 | struct mlx4_ib_wq rq; |
333 | ||
334 | u32 doorbell_qpn; | |
335 | __be32 sq_signal_bits; | |
ea54b10c | 336 | unsigned sq_next_wqe; |
0e6e7416 | 337 | int sq_spare_wqes; |
225c7b1f RD |
338 | struct mlx4_ib_wq sq; |
339 | ||
1ffeb2eb | 340 | enum mlx4_ib_qp_type mlx4_ib_qp_type; |
225c7b1f RD |
341 | struct ib_umem *umem; |
342 | struct mlx4_mtt mtt; | |
343 | int buf_size; | |
344 | struct mutex mutex; | |
0a1405da | 345 | u16 xrcdn; |
b832be1e | 346 | u32 flags; |
225c7b1f RD |
347 | u8 port; |
348 | u8 alt_port; | |
349 | u8 atomic_rd_en; | |
350 | u8 resp_depth; | |
0e6e7416 | 351 | u8 sq_no_prefetch; |
225c7b1f | 352 | u8 state; |
fa417f7b | 353 | int mlx_type; |
ea30b966 | 354 | u32 inl_recv_sz; |
fa417f7b | 355 | struct list_head gid_list; |
0ff1fb65 | 356 | struct list_head steering_rules; |
1ffeb2eb | 357 | struct mlx4_ib_buf *sqp_proxy_rcv; |
2f5bb473 JM |
358 | struct mlx4_roce_smac_vlan_info pri; |
359 | struct mlx4_roce_smac_vlan_info alt; | |
c1c98501 | 360 | u64 reg_id; |
35f05dab YH |
361 | struct list_head qps_list; |
362 | struct list_head cq_recv_list; | |
363 | struct list_head cq_send_list; | |
7b59f0f9 | 364 | struct counter_index *counter_index; |
400b1ebc GL |
365 | struct mlx4_wqn_range *wqn_range; |
366 | /* Number of RSS QP parents that uses this WQ */ | |
367 | u32 rss_usecnt; | |
915ec7ed LR |
368 | union { |
369 | struct mlx4_ib_rss *rss_ctx; | |
370 | struct mlx4_ib_sqp *sqp; | |
371 | }; | |
225c7b1f RD |
372 | }; |
373 | ||
374 | struct mlx4_ib_srq { | |
375 | struct ib_srq ibsrq; | |
376 | struct mlx4_srq msrq; | |
377 | struct mlx4_buf buf; | |
6296883c | 378 | struct mlx4_db db; |
225c7b1f RD |
379 | u64 *wrid; |
380 | spinlock_t lock; | |
381 | int head; | |
382 | int tail; | |
383 | u16 wqe_ctr; | |
384 | struct ib_umem *umem; | |
385 | struct mlx4_mtt mtt; | |
386 | struct mutex mutex; | |
387 | }; | |
388 | ||
389 | struct mlx4_ib_ah { | |
390 | struct ib_ah ibah; | |
fa417f7b EC |
391 | union mlx4_ext_av av; |
392 | }; | |
393 | ||
c0a6b5ec LR |
394 | struct mlx4_ib_rwq_ind_table { |
395 | struct ib_rwq_ind_table ib_rwq_ind_tbl; | |
396 | }; | |
397 | ||
a0c64a17 JM |
398 | /****************************************/ |
399 | /* alias guid support */ | |
400 | /****************************************/ | |
401 | #define NUM_PORT_ALIAS_GUID 2 | |
402 | #define NUM_ALIAS_GUID_IN_REC 8 | |
403 | #define NUM_ALIAS_GUID_REC_IN_PORT 16 | |
404 | #define GUID_REC_SIZE 8 | |
405 | #define NUM_ALIAS_GUID_PER_PORT 128 | |
406 | #define MLX4_NOT_SET_GUID (0x00LL) | |
407 | #define MLX4_GUID_FOR_DELETE_VAL (~(0x00LL)) | |
408 | ||
409 | enum mlx4_guid_alias_rec_status { | |
410 | MLX4_GUID_INFO_STATUS_IDLE, | |
411 | MLX4_GUID_INFO_STATUS_SET, | |
a0c64a17 JM |
412 | }; |
413 | ||
f5479601 | 414 | #define GUID_STATE_NEED_PORT_INIT 0x01 |
a0c64a17 JM |
415 | |
416 | enum mlx4_guid_alias_rec_method { | |
417 | MLX4_GUID_INFO_RECORD_SET = IB_MGMT_METHOD_SET, | |
418 | MLX4_GUID_INFO_RECORD_DELETE = IB_SA_METHOD_DELETE, | |
419 | }; | |
420 | ||
421 | struct mlx4_sriov_alias_guid_info_rec_det { | |
422 | u8 all_recs[GUID_REC_SIZE * NUM_ALIAS_GUID_IN_REC]; | |
423 | ib_sa_comp_mask guid_indexes; /*indicates what from the 8 records are valid*/ | |
424 | enum mlx4_guid_alias_rec_status status; /*indicates the administraively status of the record.*/ | |
99ee4df6 YH |
425 | unsigned int guids_retry_schedule[NUM_ALIAS_GUID_IN_REC]; |
426 | u64 time_to_run; | |
a0c64a17 JM |
427 | }; |
428 | ||
429 | struct mlx4_sriov_alias_guid_port_rec_det { | |
430 | struct mlx4_sriov_alias_guid_info_rec_det all_rec_per_port[NUM_ALIAS_GUID_REC_IN_PORT]; | |
431 | struct workqueue_struct *wq; | |
432 | struct delayed_work alias_guid_work; | |
1fb7f897 | 433 | u32 port; |
f5479601 | 434 | u32 state_flags; |
a0c64a17 JM |
435 | struct mlx4_sriov_alias_guid *parent; |
436 | struct list_head cb_list; | |
437 | }; | |
438 | ||
439 | struct mlx4_sriov_alias_guid { | |
440 | struct mlx4_sriov_alias_guid_port_rec_det ports_guid[MLX4_MAX_PORTS]; | |
441 | spinlock_t ag_work_lock; | |
442 | struct ib_sa_client *sa_client; | |
443 | }; | |
444 | ||
fc06573d JM |
445 | struct mlx4_ib_demux_work { |
446 | struct work_struct work; | |
447 | struct mlx4_ib_dev *dev; | |
448 | int slave; | |
449 | int do_init; | |
450 | u8 port; | |
451 | ||
452 | }; | |
453 | ||
1ffeb2eb JM |
454 | struct mlx4_ib_tun_tx_buf { |
455 | struct mlx4_ib_buf buf; | |
456 | struct ib_ah *ah; | |
457 | }; | |
458 | ||
459 | struct mlx4_ib_demux_pv_qp { | |
460 | struct ib_qp *qp; | |
461 | enum ib_qp_type proxy_qpt; | |
462 | struct mlx4_ib_buf *ring; | |
463 | struct mlx4_ib_tun_tx_buf *tx_ring; | |
464 | spinlock_t tx_lock; | |
465 | unsigned tx_ix_head; | |
466 | unsigned tx_ix_tail; | |
467 | }; | |
468 | ||
fc06573d JM |
469 | enum mlx4_ib_demux_pv_state { |
470 | DEMUX_PV_STATE_DOWN, | |
471 | DEMUX_PV_STATE_STARTING, | |
472 | DEMUX_PV_STATE_ACTIVE, | |
473 | DEMUX_PV_STATE_DOWNING, | |
474 | }; | |
475 | ||
1ffeb2eb JM |
476 | struct mlx4_ib_demux_pv_ctx { |
477 | int port; | |
478 | int slave; | |
fc06573d | 479 | enum mlx4_ib_demux_pv_state state; |
1ffeb2eb JM |
480 | int has_smi; |
481 | struct ib_device *ib_dev; | |
482 | struct ib_cq *cq; | |
483 | struct ib_pd *pd; | |
1ffeb2eb JM |
484 | struct work_struct work; |
485 | struct workqueue_struct *wq; | |
7fd1507d | 486 | struct workqueue_struct *wi_wq; |
1ffeb2eb JM |
487 | struct mlx4_ib_demux_pv_qp qp[2]; |
488 | }; | |
489 | ||
490 | struct mlx4_ib_demux_ctx { | |
491 | struct ib_device *ib_dev; | |
492 | int port; | |
493 | struct workqueue_struct *wq; | |
7fd1507d | 494 | struct workqueue_struct *wi_wq; |
1ffeb2eb JM |
495 | struct workqueue_struct *ud_wq; |
496 | spinlock_t ud_lock; | |
8ec07bf8 | 497 | atomic64_t subnet_prefix; |
1ffeb2eb JM |
498 | __be64 guid_cache[128]; |
499 | struct mlx4_ib_dev *dev; | |
b9c5d6a6 OD |
500 | /* the following lock protects both mcg_table and mcg_mgid0_list */ |
501 | struct mutex mcg_table_lock; | |
502 | struct rb_root mcg_table; | |
503 | struct list_head mcg_mgid0_list; | |
504 | struct workqueue_struct *mcg_wq; | |
1ffeb2eb | 505 | struct mlx4_ib_demux_pv_ctx **tun; |
b9c5d6a6 OD |
506 | atomic_t tid; |
507 | int flushing; /* flushing the work queue */ | |
1ffeb2eb JM |
508 | }; |
509 | ||
510 | struct mlx4_ib_sriov { | |
511 | struct mlx4_ib_demux_ctx demux[MLX4_MAX_PORTS]; | |
512 | struct mlx4_ib_demux_pv_ctx *sqps[MLX4_MAX_PORTS]; | |
513 | /* when using this spinlock you should use "irq" because | |
514 | * it may be called from interrupt context.*/ | |
515 | spinlock_t going_down_lock; | |
516 | int is_going_down; | |
3cf69cc8 | 517 | |
a0c64a17 JM |
518 | struct mlx4_sriov_alias_guid alias_guid; |
519 | ||
3cf69cc8 | 520 | /* CM paravirtualization fields */ |
f1430536 MW |
521 | struct xarray pv_id_table; |
522 | u32 pv_id_next; | |
3cf69cc8 AV |
523 | spinlock_t id_map_lock; |
524 | struct rb_root sl_id_map; | |
f1430536 | 525 | struct list_head cm_list; |
bf6a4764 | 526 | struct xarray xa_rej_tmout; |
1ffeb2eb JM |
527 | }; |
528 | ||
e26be1bf MS |
529 | struct gid_cache_context { |
530 | int real_index; | |
531 | int refcount; | |
532 | }; | |
533 | ||
534 | struct gid_entry { | |
535 | union ib_gid gid; | |
b699a859 | 536 | enum ib_gid_type gid_type; |
e26be1bf | 537 | struct gid_cache_context *ctx; |
ff3195b3 | 538 | u16 vlan_id; |
e26be1bf MS |
539 | }; |
540 | ||
541 | struct mlx4_port_gid_table { | |
542 | struct gid_entry gids[MLX4_MAX_PORT_GIDS]; | |
543 | }; | |
544 | ||
fa417f7b EC |
545 | struct mlx4_ib_iboe { |
546 | spinlock_t lock; | |
547 | struct net_device *netdevs[MLX4_MAX_PORTS]; | |
3e0629cb | 548 | atomic64_t mac[MLX4_MAX_PORTS]; |
fa417f7b | 549 | struct notifier_block nb; |
e26be1bf | 550 | struct mlx4_port_gid_table gids[MLX4_MAX_PORTS]; |
fc6526fb | 551 | enum ib_port_state last_port_state[MLX4_MAX_PORTS]; |
225c7b1f RD |
552 | }; |
553 | ||
fc06573d JM |
554 | struct pkey_mgt { |
555 | u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; | |
556 | u16 phys_pkey_cache[MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; | |
557 | struct list_head pkey_port_list[MLX4_MFUNC_MAX]; | |
558 | struct kobject *device_parent[MLX4_MFUNC_MAX]; | |
559 | }; | |
560 | ||
c1e7e466 JM |
561 | struct mlx4_ib_iov_sysfs_attr { |
562 | void *ctx; | |
563 | struct kobject *kobj; | |
564 | unsigned long data; | |
565 | u32 entry_num; | |
566 | char name[15]; | |
567 | struct device_attribute dentry; | |
568 | struct device *dev; | |
569 | }; | |
570 | ||
571 | struct mlx4_ib_iov_sysfs_attr_ar { | |
572 | struct mlx4_ib_iov_sysfs_attr dentries[3 * NUM_ALIAS_GUID_PER_PORT + 1]; | |
573 | }; | |
574 | ||
575 | struct mlx4_ib_iov_port { | |
576 | char name[100]; | |
577 | u8 num; | |
578 | struct mlx4_ib_dev *dev; | |
579 | struct list_head list; | |
580 | struct mlx4_ib_iov_sysfs_attr_ar *dentr_ar; | |
581 | struct ib_port_attr attr; | |
582 | struct kobject *cur_port; | |
583 | struct kobject *admin_alias_parent; | |
584 | struct kobject *gids_parent; | |
585 | struct kobject *pkeys_parent; | |
586 | struct kobject *mcgs_parent; | |
587 | struct mlx4_ib_iov_sysfs_attr mcg_dentry; | |
588 | }; | |
589 | ||
c3abb51b | 590 | struct counter_index { |
3ba8e31d | 591 | struct list_head list; |
c3abb51b EBE |
592 | u32 index; |
593 | u8 allocated; | |
594 | }; | |
595 | ||
3ba8e31d EBE |
596 | struct mlx4_ib_counters { |
597 | struct list_head counters_list; | |
598 | struct mutex mutex; /* mutex for accessing counters list */ | |
599 | u32 default_counter; | |
600 | }; | |
601 | ||
3f85f2aa MB |
602 | #define MLX4_DIAG_COUNTERS_TYPES 2 |
603 | ||
604 | struct mlx4_ib_diag_counters { | |
13f30b0f | 605 | struct rdma_stat_desc *descs; |
3f85f2aa MB |
606 | u32 *offset; |
607 | u32 num_counters; | |
608 | }; | |
609 | ||
225c7b1f RD |
610 | struct mlx4_ib_dev { |
611 | struct ib_device ib_dev; | |
612 | struct mlx4_dev *dev; | |
7ff93f8b | 613 | int num_ports; |
225c7b1f RD |
614 | void __iomem *uar_map; |
615 | ||
225c7b1f RD |
616 | struct mlx4_uar priv_uar; |
617 | u32 priv_pdn; | |
618 | MLX4_DECLARE_DOORBELL_LOCK(uar_lock); | |
619 | ||
620 | struct ib_mad_agent *send_agent[MLX4_MAX_PORTS][2]; | |
621 | struct ib_ah *sm_ah[MLX4_MAX_PORTS]; | |
622 | spinlock_t sm_lock; | |
fd10ed8e | 623 | atomic64_t sl2vl[MLX4_MAX_PORTS]; |
1ffeb2eb | 624 | struct mlx4_ib_sriov sriov; |
225c7b1f RD |
625 | |
626 | struct mutex cap_mask_mutex; | |
3b4a8cd5 | 627 | bool ib_active; |
fa417f7b | 628 | struct mlx4_ib_iboe iboe; |
3ba8e31d | 629 | struct mlx4_ib_counters counters_table[MLX4_MAX_PORTS]; |
e605b743 | 630 | int *eq_table; |
c1e7e466 JM |
631 | struct kobject *iov_parent; |
632 | struct kobject *ports_parent; | |
633 | struct kobject *dev_ports_parent[MLX4_MFUNC_MAX]; | |
634 | struct mlx4_ib_iov_port iov_ports[MLX4_MAX_PORTS]; | |
fc06573d | 635 | struct pkey_mgt pkeys; |
c1c98501 MB |
636 | unsigned long *ib_uc_qpns_bitmap; |
637 | int steer_qpn_count; | |
638 | int steer_qpn_base; | |
0a9b7d59 | 639 | int steering_support; |
9433c188 MB |
640 | struct mlx4_ib_qp *qp1_proxy[MLX4_MAX_PORTS]; |
641 | /* lock when destroying qp1_proxy and getting netdev events */ | |
642 | struct mutex qp1_proxy_lock[MLX4_MAX_PORTS]; | |
c6215745 | 643 | u8 bond_next_port; |
35f05dab YH |
644 | /* protect resources needed as part of reset flow */ |
645 | spinlock_t reset_flow_resource_lock; | |
646 | struct list_head qp_list; | |
3f85f2aa | 647 | struct mlx4_ib_diag_counters diag_counters[MLX4_DIAG_COUNTERS_TYPES]; |
73d68002 | 648 | struct notifier_block mlx_nb; |
225c7b1f RD |
649 | }; |
650 | ||
00f5ce99 JM |
651 | struct ib_event_work { |
652 | struct work_struct work; | |
653 | struct mlx4_ib_dev *ib_dev; | |
654 | struct mlx4_eqe ib_eqe; | |
fd10ed8e | 655 | int port; |
00f5ce99 JM |
656 | }; |
657 | ||
1ffeb2eb JM |
658 | struct mlx4_ib_qp_tunnel_init_attr { |
659 | struct ib_qp_init_attr init_attr; | |
660 | int slave; | |
661 | enum ib_qp_type proxy_qp_type; | |
1fb7f897 | 662 | u32 port; |
1ffeb2eb JM |
663 | }; |
664 | ||
4b664c43 MB |
665 | struct mlx4_uverbs_ex_query_device { |
666 | __u32 comp_mask; | |
667 | __u32 reserved; | |
668 | }; | |
669 | ||
225c7b1f RD |
670 | static inline struct mlx4_ib_dev *to_mdev(struct ib_device *ibdev) |
671 | { | |
672 | return container_of(ibdev, struct mlx4_ib_dev, ib_dev); | |
673 | } | |
674 | ||
675 | static inline struct mlx4_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) | |
676 | { | |
677 | return container_of(ibucontext, struct mlx4_ib_ucontext, ibucontext); | |
678 | } | |
679 | ||
680 | static inline struct mlx4_ib_pd *to_mpd(struct ib_pd *ibpd) | |
681 | { | |
682 | return container_of(ibpd, struct mlx4_ib_pd, ibpd); | |
683 | } | |
684 | ||
012a8ff5 SH |
685 | static inline struct mlx4_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) |
686 | { | |
687 | return container_of(ibxrcd, struct mlx4_ib_xrcd, ibxrcd); | |
688 | } | |
689 | ||
225c7b1f RD |
690 | static inline struct mlx4_ib_cq *to_mcq(struct ib_cq *ibcq) |
691 | { | |
692 | return container_of(ibcq, struct mlx4_ib_cq, ibcq); | |
693 | } | |
694 | ||
695 | static inline struct mlx4_ib_cq *to_mibcq(struct mlx4_cq *mcq) | |
696 | { | |
697 | return container_of(mcq, struct mlx4_ib_cq, mcq); | |
698 | } | |
699 | ||
700 | static inline struct mlx4_ib_mr *to_mmr(struct ib_mr *ibmr) | |
701 | { | |
702 | return container_of(ibmr, struct mlx4_ib_mr, ibmr); | |
703 | } | |
704 | ||
804d6a89 SM |
705 | static inline struct mlx4_ib_mw *to_mmw(struct ib_mw *ibmw) |
706 | { | |
707 | return container_of(ibmw, struct mlx4_ib_mw, ibmw); | |
708 | } | |
709 | ||
f77c0162 HHZ |
710 | static inline struct mlx4_ib_flow *to_mflow(struct ib_flow *ibflow) |
711 | { | |
712 | return container_of(ibflow, struct mlx4_ib_flow, ibflow); | |
713 | } | |
714 | ||
225c7b1f RD |
715 | static inline struct mlx4_ib_qp *to_mqp(struct ib_qp *ibqp) |
716 | { | |
717 | return container_of(ibqp, struct mlx4_ib_qp, ibqp); | |
718 | } | |
719 | ||
720 | static inline struct mlx4_ib_qp *to_mibqp(struct mlx4_qp *mqp) | |
721 | { | |
722 | return container_of(mqp, struct mlx4_ib_qp, mqp); | |
723 | } | |
724 | ||
725 | static inline struct mlx4_ib_srq *to_msrq(struct ib_srq *ibsrq) | |
726 | { | |
727 | return container_of(ibsrq, struct mlx4_ib_srq, ibsrq); | |
728 | } | |
729 | ||
730 | static inline struct mlx4_ib_srq *to_mibsrq(struct mlx4_srq *msrq) | |
731 | { | |
732 | return container_of(msrq, struct mlx4_ib_srq, msrq); | |
733 | } | |
734 | ||
735 | static inline struct mlx4_ib_ah *to_mah(struct ib_ah *ibah) | |
736 | { | |
737 | return container_of(ibah, struct mlx4_ib_ah, ibah); | |
738 | } | |
739 | ||
c6215745 MS |
740 | static inline u8 mlx4_ib_bond_next_port(struct mlx4_ib_dev *dev) |
741 | { | |
742 | dev->bond_next_port = (dev->bond_next_port + 1) % dev->num_ports; | |
743 | ||
744 | return dev->bond_next_port + 1; | |
745 | } | |
746 | ||
fc06573d JM |
747 | int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev); |
748 | void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev); | |
749 | ||
ff23dfa1 | 750 | int mlx4_ib_db_map_user(struct ib_udata *udata, unsigned long virt, |
6296883c YP |
751 | struct mlx4_db *db); |
752 | void mlx4_ib_db_unmap_user(struct mlx4_ib_ucontext *context, struct mlx4_db *db); | |
225c7b1f RD |
753 | |
754 | struct ib_mr *mlx4_ib_get_dma_mr(struct ib_pd *pd, int acc); | |
755 | int mlx4_ib_umem_write_mtt(struct mlx4_ib_dev *dev, struct mlx4_mtt *mtt, | |
756 | struct ib_umem *umem); | |
757 | struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, | |
758 | u64 virt_addr, int access_flags, | |
759 | struct ib_udata *udata); | |
c4367a26 | 760 | int mlx4_ib_dereg_mr(struct ib_mr *mr, struct ib_udata *udata); |
d18bb3e1 | 761 | int mlx4_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); |
804d6a89 | 762 | int mlx4_ib_dealloc_mw(struct ib_mw *mw); |
c4367a26 | 763 | struct ib_mr *mlx4_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, |
42a3b153 | 764 | u32 max_num_sg); |
ff2ba993 | 765 | int mlx4_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
9aa8b321 | 766 | unsigned int *sg_offset); |
3fdcb97f | 767 | int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); |
bbf8eed1 | 768 | int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); |
e39afe3d LR |
769 | int mlx4_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, |
770 | struct ib_udata *udata); | |
43d781b9 | 771 | int mlx4_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); |
225c7b1f RD |
772 | int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); |
773 | int mlx4_ib_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags); | |
774 | void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq); | |
775 | void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq); | |
776 | ||
fa5d010c | 777 | int mlx4_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, |
d3456914 LR |
778 | struct ib_udata *udata); |
779 | int mlx4_ib_create_ah_slave(struct ib_ah *ah, struct rdma_ah_attr *ah_attr, | |
780 | int slave_sgid_index, u8 *s_mac, u16 vlan_tag); | |
90898850 | 781 | int mlx4_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); |
9a9ebf8c LR |
782 | static inline int mlx4_ib_destroy_ah(struct ib_ah *ah, u32 flags) |
783 | { | |
784 | return 0; | |
785 | } | |
225c7b1f | 786 | |
68e326de LR |
787 | int mlx4_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, |
788 | struct ib_udata *udata); | |
225c7b1f RD |
789 | int mlx4_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, |
790 | enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); | |
65541cb7 | 791 | int mlx4_ib_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr); |
119181d1 | 792 | int mlx4_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); |
225c7b1f | 793 | void mlx4_ib_free_srq_wqe(struct mlx4_ib_srq *srq, int wqe_index); |
d34ac5cd BVA |
794 | int mlx4_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, |
795 | const struct ib_recv_wr **bad_wr); | |
225c7b1f | 796 | |
514aee66 LR |
797 | int mlx4_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr, |
798 | struct ib_udata *udata); | |
c4367a26 | 799 | int mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); |
1975acd9 YH |
800 | void mlx4_ib_drain_sq(struct ib_qp *qp); |
801 | void mlx4_ib_drain_rq(struct ib_qp *qp); | |
225c7b1f RD |
802 | int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, |
803 | int attr_mask, struct ib_udata *udata); | |
6a775e2b JM |
804 | int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, |
805 | struct ib_qp_init_attr *qp_init_attr); | |
d34ac5cd BVA |
806 | int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, |
807 | const struct ib_send_wr **bad_wr); | |
808 | int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, | |
809 | const struct ib_recv_wr **bad_wr); | |
225c7b1f | 810 | |
0a9a0188 | 811 | int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags, |
a97e2d86 IW |
812 | int port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
813 | const void *in_mad, void *response_mad); | |
1fb7f897 | 814 | int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num, |
a97e2d86 | 815 | const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
e26e7b88 LR |
816 | const struct ib_mad *in, struct ib_mad *out, |
817 | size_t *out_mad_size, u16 *out_mad_pkey_index); | |
225c7b1f RD |
818 | int mlx4_ib_mad_init(struct mlx4_ib_dev *dev); |
819 | void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev); | |
820 | ||
1fb7f897 | 821 | int __mlx4_ib_query_port(struct ib_device *ibdev, u32 port, |
0a9a0188 | 822 | struct ib_port_attr *props, int netw_view); |
1fb7f897 | 823 | int __mlx4_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, |
0a9a0188 | 824 | u16 *pkey, int netw_view); |
8ad11fb6 | 825 | |
1fb7f897 | 826 | int __mlx4_ib_query_gid(struct ib_device *ibdev, u32 port, int index, |
a0c64a17 JM |
827 | union ib_gid *gid, int netw_view); |
828 | ||
a29bec12 | 829 | static inline bool mlx4_ib_ah_grh_present(struct mlx4_ib_ah *ah) |
225c7b1f | 830 | { |
1fb7f897 | 831 | u32 port = be32_to_cpu(ah->av.ib.port_pd) >> 24 & 3; |
fa417f7b EC |
832 | |
833 | if (rdma_port_get_link_layer(ah->ibah.device, port) == IB_LINK_LAYER_ETHERNET) | |
a29bec12 | 834 | return true; |
fa417f7b EC |
835 | |
836 | return !!(ah->av.ib.g_slid & 0x80); | |
225c7b1f RD |
837 | } |
838 | ||
b9c5d6a6 OD |
839 | int mlx4_ib_mcg_port_init(struct mlx4_ib_demux_ctx *ctx); |
840 | void mlx4_ib_mcg_port_cleanup(struct mlx4_ib_demux_ctx *ctx, int destroy_wq); | |
841 | void clean_vf_mcast(struct mlx4_ib_demux_ctx *ctx, int slave); | |
842 | int mlx4_ib_mcg_init(void); | |
843 | void mlx4_ib_mcg_destroy(void); | |
844 | ||
1fb7f897 | 845 | int mlx4_ib_find_real_gid(struct ib_device *ibdev, u32 port, __be64 guid); |
b9c5d6a6 OD |
846 | |
847 | int mlx4_ib_mcg_multiplex_handler(struct ib_device *ibdev, int port, int slave, | |
848 | struct ib_sa_mad *sa_mad); | |
849 | int mlx4_ib_mcg_demux_handler(struct ib_device *ibdev, int port, int slave, | |
850 | struct ib_sa_mad *mad); | |
851 | ||
fa417f7b EC |
852 | int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, |
853 | union ib_gid *gid); | |
854 | ||
1fb7f897 | 855 | void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u32 port_num, |
00f5ce99 JM |
856 | enum ib_event_type type); |
857 | ||
fc06573d JM |
858 | void mlx4_ib_tunnels_update_work(struct work_struct *work); |
859 | ||
1fb7f897 | 860 | int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u32 port, |
b9c5d6a6 OD |
861 | enum ib_qp_type qpt, struct ib_wc *wc, |
862 | struct ib_grh *grh, struct ib_mad *mad); | |
5ea8bbfc | 863 | |
1fb7f897 | 864 | int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u32 port, |
b9c5d6a6 | 865 | enum ib_qp_type dest_qpt, u16 pkey_index, u32 remote_qpn, |
90898850 | 866 | u32 qkey, struct rdma_ah_attr *attr, u8 *s_mac, |
dbf727de | 867 | u16 vlan_id, struct ib_mad *mad); |
5ea8bbfc | 868 | |
b9c5d6a6 OD |
869 | __be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx); |
870 | ||
3cf69cc8 AV |
871 | int mlx4_ib_demux_cm_handler(struct ib_device *ibdev, int port, int *slave, |
872 | struct ib_mad *mad); | |
873 | ||
874 | int mlx4_ib_multiplex_cm_handler(struct ib_device *ibdev, int port, int slave_id, | |
875 | struct ib_mad *mad); | |
876 | ||
877 | void mlx4_ib_cm_paravirt_init(struct mlx4_ib_dev *dev); | |
878 | void mlx4_ib_cm_paravirt_clean(struct mlx4_ib_dev *dev, int slave_id); | |
879 | ||
a0c64a17 JM |
880 | /* alias guid support */ |
881 | void mlx4_ib_init_alias_guid_work(struct mlx4_ib_dev *dev, int port); | |
882 | int mlx4_ib_init_alias_guid_service(struct mlx4_ib_dev *dev); | |
883 | void mlx4_ib_destroy_alias_guid_service(struct mlx4_ib_dev *dev); | |
884 | void mlx4_ib_invalidate_all_guid_record(struct mlx4_ib_dev *dev, int port); | |
885 | ||
886 | void mlx4_ib_notify_slaves_on_guid_change(struct mlx4_ib_dev *dev, | |
887 | int block_num, | |
1fb7f897 | 888 | u32 port_num, u8 *p_data); |
a0c64a17 JM |
889 | |
890 | void mlx4_ib_update_cache_on_guid_change(struct mlx4_ib_dev *dev, | |
1fb7f897 | 891 | int block_num, u32 port_num, |
a0c64a17 JM |
892 | u8 *p_data); |
893 | ||
c1e7e466 JM |
894 | int add_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num, |
895 | struct attribute *attr); | |
896 | void del_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num, | |
897 | struct attribute *attr); | |
898 | ib_sa_comp_mask mlx4_ib_get_aguid_comp_mask_from_ix(int index); | |
ee59fa0d YH |
899 | void mlx4_ib_slave_alias_guid_event(struct mlx4_ib_dev *dev, int slave, |
900 | int port, int slave_init); | |
c1e7e466 JM |
901 | |
902 | int mlx4_ib_device_register_sysfs(struct mlx4_ib_dev *device) ; | |
903 | ||
904 | void mlx4_ib_device_unregister_sysfs(struct mlx4_ib_dev *device); | |
905 | ||
afa8fd1d JM |
906 | __be64 mlx4_ib_gen_node_guid(void); |
907 | ||
c1c98501 MB |
908 | int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn); |
909 | void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count); | |
910 | int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, | |
911 | int is_attach); | |
6e0954b1 JG |
912 | struct ib_mr *mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, |
913 | u64 length, u64 virt_addr, | |
914 | int mr_access_flags, struct ib_pd *pd, | |
915 | struct ib_udata *udata); | |
e26be1bf | 916 | int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, |
7492052a | 917 | const struct ib_gid_attr *attr); |
afa8fd1d | 918 | |
fd10ed8e JM |
919 | void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev, |
920 | int port); | |
921 | ||
922 | void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port); | |
923 | ||
400b1ebc GL |
924 | struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd, |
925 | struct ib_wq_init_attr *init_attr, | |
926 | struct ib_udata *udata); | |
add53535 | 927 | int mlx4_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); |
400b1ebc GL |
928 | int mlx4_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, |
929 | u32 wq_attr_mask, struct ib_udata *udata); | |
930 | ||
c0a6b5ec LR |
931 | int mlx4_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl, |
932 | struct ib_rwq_ind_table_init_attr *init_attr, | |
933 | struct ib_udata *udata); | |
934 | static inline int | |
935 | mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table) | |
936 | { | |
937 | return 0; | |
938 | } | |
ed8637d3 GL |
939 | int mlx4_ib_umem_calc_optimal_mtt_size(struct ib_umem *umem, u64 start_va, |
940 | int *num_of_mtts); | |
b8d46ca0 | 941 | |
9cf62d91 TH |
942 | int mlx4_ib_cm_init(void); |
943 | void mlx4_ib_cm_destroy(void); | |
944 | ||
312b8f79 MZ |
945 | int mlx4_ib_qp_event_init(void); |
946 | void mlx4_ib_qp_event_cleanup(void); | |
947 | ||
225c7b1f | 948 | #endif /* MLX4_IB_H */ |