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IB/mlx4: Fix corruption of RoCEv2 IPv4 GIDs
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#include <linux/module.h>
35#include <linux/init.h>
5a0e3ad6 36#include <linux/slab.h>
225c7b1f 37#include <linux/errno.h>
fa417f7b
EC		 38#include <linux/netdevice.h>
39#include <linux/inetdevice.h>
40#include <linux/rtnetlink.h>
4c3eb3ca 41#include <linux/if_vlan.h>
6e84f315 42#include <linux/sched/mm.h>
0881e7bd 43#include <linux/sched/task.h>
6e84f315 44
d487ee77
MS		 45#include <net/ipv6.h>
46#include <net/addrconf.h>
09d4d087 47#include <net/devlink.h>
225c7b1f
RD		 48
49#include <rdma/ib_smi.h>
50#include <rdma/ib_user_verbs.h>
fa417f7b 51#include <rdma/ib_addr.h>
e26be1bf
MS		 52#include <rdma/ib_cache.h>
53
54#include <net/bonding.h>
225c7b1f
RD		 55
56#include <linux/mlx4/driver.h>
57#include <linux/mlx4/cmd.h>
9433c188 58#include <linux/mlx4/qp.h>
225c7b1f
RD		 59
60#include "mlx4_ib.h"
9ce28a20 61#include <rdma/mlx4-abi.h>
225c7b1f 62
b1d8eb5a 63#define DRV_NAME MLX4_IB_DRV_NAME
0a528ee9 64#define DRV_VERSION "4.0-0"
225c7b1f 65
f77c0162 66#define MLX4_IB_FLOW_MAX_PRIO 0xFFF
a37a1a42 67#define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
50e2ec91 68#define MLX4_IB_CARD_REV_A0 0xA0
f77c0162 69
225c7b1f
RD		 70MODULE_AUTHOR("Roland Dreier");
71MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
72MODULE_LICENSE("Dual BSD/GPL");
225c7b1f 73
56c1d233 74int mlx4_ib_sm_guid_assign = 0;
a0c64a17 75module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
56c1d233 76MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
a0c64a17 77
68f3948d 78static const char mlx4_ib_version[] =
225c7b1f 79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
0a528ee9 80 DRV_VERSION "\n";
225c7b1f 81
3806d08c 82static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
400b1ebc
GL		 83static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device,
84 u8 port_num);
3806d08c 85
fa417f7b
EC		 86static struct workqueue_struct *wq;
87
225c7b1f
RD		 88static void init_query_mad(struct ib_smp *mad)
89{
90 mad->base_version = 1;
91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
92 mad->class_version = 1;
93 mad->method = IB_MGMT_METHOD_GET;
94}
95
f77c0162
HHZ		 96static int check_flow_steering_support(struct mlx4_dev *dev)
97{
0a9b7d59 98 int eth_num_ports = 0;
f77c0162 99 int ib_num_ports = 0;
f77c0162 100
0a9b7d59
MB		 101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
102
103 if (dmfs) {
104 int i;
105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
106 eth_num_ports++;
107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
108 ib_num_ports++;
109 dmfs &= (!ib_num_ports ||
110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
111 (!eth_num_ports ||
112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
113 if (ib_num_ports && mlx4_is_mfunc(dev)) {
114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
115 dmfs = 0;
f77c0162 116 }
f77c0162 117 }
0a9b7d59 118 return dmfs;
f77c0162
HHZ		 119}
120
3dec4878
JM		 121static int num_ib_ports(struct mlx4_dev *dev)
122{
123 int ib_ports = 0;
124 int i;
125
126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
127 ib_ports++;
128
129 return ib_ports;
130}
131
e26be1bf
MS		 132static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
133{
134 struct mlx4_ib_dev *ibdev = to_mdev(device);
135 struct net_device *dev;
136
137 rcu_read_lock();
138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
139
140 if (dev) {
141 if (mlx4_is_bonded(ibdev->dev)) {
142 struct net_device *upper = NULL;
143
144 upper = netdev_master_upper_dev_get_rcu(dev);
145 if (upper) {
146 struct net_device *active;
147
148 active = bond_option_active_slave_get_rcu(netdev_priv(upper));
149 if (active)
150 dev = active;
151 }
152 }
153 }
154 if (dev)
155 dev_hold(dev);
156
157 rcu_read_unlock();
158 return dev;
159}
160
7e57b85c
MS		 161static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
162 struct mlx4_ib_dev *ibdev,
163 u8 port_num)
e26be1bf
MS		 164{
165 struct mlx4_cmd_mailbox *mailbox;
166 int err;
167 struct mlx4_dev *dev = ibdev->dev;
168 int i;
169 union ib_gid *gid_tbl;
170
171 mailbox = mlx4_alloc_cmd_mailbox(dev);
172 if (IS_ERR(mailbox))
173 return -ENOMEM;
174
175 gid_tbl = mailbox->buf;
176
177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
179
180 err = mlx4_cmd(dev, mailbox->dma,
181 MLX4_SET_PORT_GID_TABLE << 8 | port_num,
182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
183 MLX4_CMD_WRAPPED);
184 if (mlx4_is_bonded(dev))
185 err += mlx4_cmd(dev, mailbox->dma,
186 MLX4_SET_PORT_GID_TABLE << 8 | 2,
187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
188 MLX4_CMD_WRAPPED);
189
190 mlx4_free_cmd_mailbox(dev, mailbox);
191 return err;
192}
193
7e57b85c
MS		 194static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
195 struct mlx4_ib_dev *ibdev,
196 u8 port_num)
197{
198 struct mlx4_cmd_mailbox *mailbox;
199 int err;
200 struct mlx4_dev *dev = ibdev->dev;
201 int i;
202 struct {
203 union ib_gid gid;
204 __be32 rsrvd1[2];
205 __be16 rsrvd2;
206 u8 type;
207 u8 version;
208 __be32 rsrvd3;
209 } *gid_tbl;
210
211 mailbox = mlx4_alloc_cmd_mailbox(dev);
212 if (IS_ERR(mailbox))
213 return -ENOMEM;
214
215 gid_tbl = mailbox->buf;
216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
219 gid_tbl[i].version = 2;
220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
221 gid_tbl[i].type = 1;
7e57b85c
MS		 222 }
223 }
224
225 err = mlx4_cmd(dev, mailbox->dma,
226 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
227 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
228 MLX4_CMD_WRAPPED);
229 if (mlx4_is_bonded(dev))
230 err += mlx4_cmd(dev, mailbox->dma,
231 MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
232 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
233 MLX4_CMD_WRAPPED);
234
235 mlx4_free_cmd_mailbox(dev, mailbox);
236 return err;
237}
238
239static int mlx4_ib_update_gids(struct gid_entry *gids,
240 struct mlx4_ib_dev *ibdev,
241 u8 port_num)
242{
243 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
244 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
245
246 return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
247}
248
e26be1bf
MS		 249static int mlx4_ib_add_gid(struct ib_device *device,
250 u8 port_num,
251 unsigned int index,
252 const union ib_gid *gid,
253 const struct ib_gid_attr *attr,
254 void **context)
255{
256 struct mlx4_ib_dev *ibdev = to_mdev(device);
257 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
258 struct mlx4_port_gid_table *port_gid_table;
259 int free = -1, found = -1;
260 int ret = 0;
261 int hw_update = 0;
262 int i;
263 struct gid_entry *gids = NULL;
264
265 if (!rdma_cap_roce_gid_table(device, port_num))
266 return -EINVAL;
267
268 if (port_num > MLX4_MAX_PORTS)
269 return -EINVAL;
270
271 if (!context)
272 return -EINVAL;
273
274 port_gid_table = &iboe->gids[port_num - 1];
275 spin_lock_bh(&iboe->lock);
276 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
b699a859
MS		 277 if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid)) &&
278 (port_gid_table->gids[i].gid_type == attr->gid_type)) {
e26be1bf
MS		 279 found = i;
280 break;
281 }
282 if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid)))
283 free = i; /* HW has space */
284 }
285
286 if (found < 0) {
287 if (free < 0) {
288 ret = -ENOSPC;
289 } else {
290 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
291 if (!port_gid_table->gids[free].ctx) {
292 ret = -ENOMEM;
293 } else {
294 *context = port_gid_table->gids[free].ctx;
295 memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid));
b699a859 296 port_gid_table->gids[free].gid_type = attr->gid_type;
e26be1bf
MS		 297 port_gid_table->gids[free].ctx->real_index = free;
298 port_gid_table->gids[free].ctx->refcount = 1;
299 hw_update = 1;
300 }
301 }
302 } else {
303 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
304 *context = ctx;
305 ctx->refcount++;
306 }
307 if (!ret && hw_update) {
308 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
309 if (!gids) {
310 ret = -ENOMEM;
311 } else {
b699a859 312 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
e26be1bf 313 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
b699a859
MS		 314 gids[i].gid_type = port_gid_table->gids[i].gid_type;
315 }
e26be1bf
MS		 316 }
317 }
318 spin_unlock_bh(&iboe->lock);
319
320 if (!ret && hw_update) {
321 ret = mlx4_ib_update_gids(gids, ibdev, port_num);
322 kfree(gids);
323 }
324
325 return ret;
326}
327
328static int mlx4_ib_del_gid(struct ib_device *device,
329 u8 port_num,
330 unsigned int index,
331 void **context)
332{
333 struct gid_cache_context *ctx = *context;
334 struct mlx4_ib_dev *ibdev = to_mdev(device);
335 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
336 struct mlx4_port_gid_table *port_gid_table;
337 int ret = 0;
338 int hw_update = 0;
339 struct gid_entry *gids = NULL;
340
341 if (!rdma_cap_roce_gid_table(device, port_num))
342 return -EINVAL;
343
344 if (port_num > MLX4_MAX_PORTS)
345 return -EINVAL;
346
347 port_gid_table = &iboe->gids[port_num - 1];
348 spin_lock_bh(&iboe->lock);
349 if (ctx) {
350 ctx->refcount--;
351 if (!ctx->refcount) {
352 unsigned int real_index = ctx->real_index;
353
354 memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid));
355 kfree(port_gid_table->gids[real_index].ctx);
356 port_gid_table->gids[real_index].ctx = NULL;
357 hw_update = 1;
358 }
359 }
360 if (!ret && hw_update) {
361 int i;
362
363 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
364 if (!gids) {
365 ret = -ENOMEM;
366 } else {
367 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++)
368 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
369 }
370 }
371 spin_unlock_bh(&iboe->lock);
372
373 if (!ret && hw_update) {
374 ret = mlx4_ib_update_gids(gids, ibdev, port_num);
375 kfree(gids);
376 }
377 return ret;
378}
379
380int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
381 u8 port_num, int index)
382{
383 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
384 struct gid_cache_context *ctx = NULL;
385 union ib_gid gid;
386 struct mlx4_port_gid_table *port_gid_table;
387 int real_index = -EINVAL;
388 int i;
389 int ret;
390 unsigned long flags;
b699a859 391 struct ib_gid_attr attr;
e26be1bf
MS		 392
393 if (port_num > MLX4_MAX_PORTS)
394 return -EINVAL;
395
396 if (mlx4_is_bonded(ibdev->dev))
397 port_num = 1;
398
399 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
400 return index;
401
b699a859 402 ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, &attr);
e26be1bf
MS		 403 if (ret)
404 return ret;
405
b699a859
MS		 406 if (attr.ndev)
407 dev_put(attr.ndev);
408
e26be1bf
MS		 409 if (!memcmp(&gid, &zgid, sizeof(gid)))
410 return -EINVAL;
411
412 spin_lock_irqsave(&iboe->lock, flags);
413 port_gid_table = &iboe->gids[port_num - 1];
414
415 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
b699a859
MS		 416 if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid)) &&
417 attr.gid_type == port_gid_table->gids[i].gid_type) {
e26be1bf
MS		 418 ctx = port_gid_table->gids[i].ctx;
419 break;
420 }
421 if (ctx)
422 real_index = ctx->real_index;
423 spin_unlock_irqrestore(&iboe->lock, flags);
424 return real_index;
425}
426
225c7b1f 427static int mlx4_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 428 struct ib_device_attr *props,
429 struct ib_udata *uhw)
225c7b1f
RD		 430{
431 struct mlx4_ib_dev *dev = to_mdev(ibdev);
432 struct ib_smp *in_mad = NULL;
433 struct ib_smp *out_mad = NULL;
46d0703f 434 int err;
3dec4878 435 int have_ib_ports;
4b664c43
MB		 436 struct mlx4_uverbs_ex_query_device cmd;
437 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
438 struct mlx4_clock_params clock_params;
225c7b1f 439
4b664c43
MB		 440 if (uhw->inlen) {
441 if (uhw->inlen < sizeof(cmd))
442 return -EINVAL;
443
444 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
445 if (err)
446 return err;
447
448 if (cmd.comp_mask)
449 return -EINVAL;
450
451 if (cmd.reserved)
452 return -EINVAL;
453 }
2528e33e 454
4b664c43
MB		 455 resp.response_length = offsetof(typeof(resp), response_length) +
456 sizeof(resp.response_length);
225c7b1f
RD		 457 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
458 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
46d0703f 459 err = -ENOMEM;
225c7b1f
RD		 460 if (!in_mad || !out_mad)
461 goto out;
462
463 init_query_mad(in_mad);
464 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
465
0a9a0188
JM		 466 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
467 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 468 if (err)
469 goto out;
470
471 memset(props, 0, sizeof *props);
472
3dec4878
JM		 473 have_ib_ports = num_ib_ports(dev->dev);
474
225c7b1f
RD		 475 props->fw_ver = dev->dev->caps.fw_ver;
476 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
477 IB_DEVICE_PORT_ACTIVE_EVENT |
478 IB_DEVICE_SYS_IMAGE_GUID |
521e575b
RL		 479 IB_DEVICE_RC_RNR_NAK_GEN |
480 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
225c7b1f
RD		 481 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
482 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
483 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
484 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
3dec4878 485 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
225c7b1f
RD		 486 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
487 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
488 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
8ff095ec
EC		 489 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
490 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
50e2ec91
MS		 491 if (dev->dev->caps.max_gso_sz &&
492 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
493 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
b832be1e 494 props->device_cap_flags |= IB_DEVICE_UD_TSO;
95d04f07
RD		 495 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
496 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
497 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
498 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
499 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
500 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
0a1405da
SH		 501 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
502 props->device_cap_flags |= IB_DEVICE_XRC;
b425388d
SM		 503 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
504 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
505 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
506 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
507 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
508 else
509 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
510 }
ca920f5b
BVA		 511 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
512 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
225c7b1f 513
070b3997
BW		 514 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
515
225c7b1f
RD		 516 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
517 0xffffff;
872bf2fb 518 props->vendor_part_id = dev->dev->persist->pdev->device;
225c7b1f
RD		 519 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
520 memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
521
522 props->max_mr_size = ~0ull;
523 props->page_size_cap = dev->dev->caps.page_size_cap;
5a0d0a61 524 props->max_qp = dev->dev->quotas.qp;
fc2d0044 525 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
225c7b1f
RD		 526 props->max_sge = min(dev->dev->caps.max_sq_sg,
527 dev->dev->caps.max_rq_sg);
a5e14ba3 528 props->max_sge_rd = MLX4_MAX_SGE_RD;
5a0d0a61 529 props->max_cq = dev->dev->quotas.cq;
225c7b1f 530 props->max_cqe = dev->dev->caps.max_cqes;
5a0d0a61 531 props->max_mr = dev->dev->quotas.mpt;
225c7b1f
RD		 532 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
533 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
534 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
535 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
5a0d0a61 536 props->max_srq = dev->dev->quotas.srq;
c8681f14 537 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
225c7b1f 538 props->max_srq_sge = dev->dev->caps.max_srq_sge;
5a0fd094 539 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
225c7b1f
RD		 540 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
541 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
542 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
47e956b2 543 props->masked_atomic_cap = props->atomic_cap;
5ae2a7a8 544 props->max_pkeys = dev->dev->caps.pkey_table_len[1];
225c7b1f
RD		 545 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
546 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
547 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
548 props->max_mcast_grp;
a5bbe892 549 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
4b664c43
MB		 550 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
551 props->timestamp_mask = 0xFFFFFFFFFFFFULL;
731e0415 552 props->max_ah = INT_MAX;
225c7b1f 553
400b1ebc
GL		 554 if ((dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) &&
555 (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET ||
6afff1c7
GL		 556 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET)) {
557 props->rss_caps.max_rwq_indirection_tables = props->max_qp;
558 props->rss_caps.max_rwq_indirection_table_size =
559 dev->dev->caps.max_rss_tbl_sz;
560 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
400b1ebc 561 props->max_wq_type_rq = props->max_qp;
6afff1c7 562 }
400b1ebc 563
0fd586de
YC		 564 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT;
565 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD;
566
8a7ff14d
MB		 567 if (!mlx4_is_slave(dev->dev))
568 err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
4b664c43
MB		 569
570 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
4b664c43 571 resp.response_length += sizeof(resp.hca_core_clock_offset);
8a7ff14d
MB		 572 if (!err && !mlx4_is_slave(dev->dev)) {
573 resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP;
574 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
575 }
4b664c43
MB		 576 }
577
ea30b966
MG		 578 if (uhw->outlen >= resp.response_length +
579 sizeof(resp.max_inl_recv_sz)) {
580 resp.response_length += sizeof(resp.max_inl_recv_sz);
581 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg *
582 sizeof(struct mlx4_wqe_data_seg);
583 }
584
09d208b2
GL		 585 if (uhw->outlen >= resp.response_length + sizeof(resp.rss_caps)) {
586 resp.response_length += sizeof(resp.rss_caps);
587 if (props->rss_caps.supported_qpts) {
588 resp.rss_caps.rx_hash_function =
589 MLX4_IB_RX_HASH_FUNC_TOEPLITZ;
07d84f7b 590
09d208b2
GL		 591 resp.rss_caps.rx_hash_fields_mask =
592 MLX4_IB_RX_HASH_SRC_IPV4 |
593 MLX4_IB_RX_HASH_DST_IPV4 |
594 MLX4_IB_RX_HASH_SRC_IPV6 |
595 MLX4_IB_RX_HASH_DST_IPV6 |
596 MLX4_IB_RX_HASH_SRC_PORT_TCP |
597 MLX4_IB_RX_HASH_DST_PORT_TCP |
598 MLX4_IB_RX_HASH_SRC_PORT_UDP |
599 MLX4_IB_RX_HASH_DST_PORT_UDP;
07d84f7b
GL		 600
601 if (dev->dev->caps.tunnel_offload_mode ==
602 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
603 resp.rss_caps.rx_hash_fields_mask |=
604 MLX4_IB_RX_HASH_INNER;
09d208b2
GL		 605 }
606 }
607
4b664c43
MB		 608 if (uhw->outlen) {
609 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
610 if (err)
611 goto out;
612 }
225c7b1f
RD		 613out:
614 kfree(in_mad);
615 kfree(out_mad);
616
617 return err;
618}
619
fa417f7b
EC		 620static enum rdma_link_layer
621mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
225c7b1f 622{
fa417f7b 623 struct mlx4_dev *dev = to_mdev(device)->dev;
225c7b1f 624
65dab25d 625 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
fa417f7b
EC		 626 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
627}
225c7b1f 628
fa417f7b 629static int ib_link_query_port(struct ib_device *ibdev, u8 port,
0a9a0188 630 struct ib_port_attr *props, int netw_view)
fa417f7b 631{
a9c766bb
OG		 632 struct ib_smp *in_mad = NULL;
633 struct ib_smp *out_mad = NULL;
a5e12dff 634 int ext_active_speed;
0a9a0188 635 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
a9c766bb
OG		 636 int err = -ENOMEM;
637
638 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
639 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
640 if (!in_mad || !out_mad)
641 goto out;
642
643 init_query_mad(in_mad);
644 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
645 in_mad->attr_mod = cpu_to_be32(port);
646
0a9a0188
JM		 647 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
648 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
649
650 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
a9c766bb
OG		 651 in_mad, out_mad);
652 if (err)
653 goto out;
654
a5e12dff 655
225c7b1f
RD		 656 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
657 props->lmc = out_mad->data[34] & 0x7;
658 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
659 props->sm_sl = out_mad->data[36] & 0xf;
660 props->state = out_mad->data[32] & 0xf;
661 props->phys_state = out_mad->data[33] >> 4;
662 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
0a9a0188
JM		 663 if (netw_view)
664 props->gid_tbl_len = out_mad->data[50];
665 else
666 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
149983af 667 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
5ae2a7a8 668 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
225c7b1f
RD		 669 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
670 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
671 props->active_width = out_mad->data[31] & 0xf;
672 props->active_speed = out_mad->data[35] >> 4;
673 props->max_mtu = out_mad->data[41] & 0xf;
674 props->active_mtu = out_mad->data[36] >> 4;
675 props->subnet_timeout = out_mad->data[51] & 0x1f;
676 props->max_vl_num = out_mad->data[37] >> 4;
677 props->init_type_reply = out_mad->data[41] >> 4;
678
a5e12dff
MA		 679 /* Check if extended speeds (EDR/FDR/...) are supported */
680 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
681 ext_active_speed = out_mad->data[62] >> 4;
682
683 switch (ext_active_speed) {
684 case 1:
2e96691c 685 props->active_speed = IB_SPEED_FDR;
a5e12dff
MA		 686 break;
687 case 2:
2e96691c 688 props->active_speed = IB_SPEED_EDR;
a5e12dff
MA		 689 break;
690 }
691 }
692
693 /* If reported active speed is QDR, check if is FDR-10 */
2e96691c 694 if (props->active_speed == IB_SPEED_QDR) {
8154c07f
OG		 695 init_query_mad(in_mad);
696 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
697 in_mad->attr_mod = cpu_to_be32(port);
698
0a9a0188 699 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
8154c07f
OG		 700 NULL, NULL, in_mad, out_mad);
701 if (err)
bf6b47de 702 goto out;
8154c07f
OG		 703
704 /* Checking LinkSpeedActive for FDR-10 */
705 if (out_mad->data[15] & 0x1)
706 props->active_speed = IB_SPEED_FDR10;
a5e12dff 707 }
d2ef4068
OG		 708
709 /* Avoid wrong speed value returned by FW if the IB link is down. */
710 if (props->state == IB_PORT_DOWN)
711 props->active_speed = IB_SPEED_SDR;
712
a9c766bb
OG		 713out:
714 kfree(in_mad);
715 kfree(out_mad);
716 return err;
fa417f7b
EC		 717}
718
719static u8 state_to_phys_state(enum ib_port_state state)
720{
721 return state == IB_PORT_ACTIVE ? 5 : 3;
722}
723
724static int eth_link_query_port(struct ib_device *ibdev, u8 port,
850b7415 725 struct ib_port_attr *props)
fa417f7b 726{
a9c766bb
OG		 727
728 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
729 struct mlx4_ib_iboe *iboe = &mdev->iboe;
fa417f7b
EC		 730 struct net_device *ndev;
731 enum ib_mtu tmp;
a9c766bb
OG		 732 struct mlx4_cmd_mailbox *mailbox;
733 int err = 0;
a5750090 734 int is_bonded = mlx4_is_bonded(mdev->dev);
a9c766bb
OG		 735
736 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
737 if (IS_ERR(mailbox))
738 return PTR_ERR(mailbox);
fa417f7b 739
a9c766bb
OG		 740 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
741 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
742 MLX4_CMD_WRAPPED);
743 if (err)
744 goto out;
745
6fa26208
SM		 746 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
747 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
748 IB_WIDTH_4X : IB_WIDTH_1X;
749 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
750 IB_SPEED_FDR : IB_SPEED_QDR;
b4a26a27 751 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
a9c766bb
OG		 752 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
753 props->max_msg_sz = mdev->dev->caps.max_msg_sz;
fa417f7b 754 props->pkey_tbl_len = 1;
bcacb897 755 props->max_mtu = IB_MTU_4096;
a9c766bb 756 props->max_vl_num = 2;
fa417f7b
EC		 757 props->state = IB_PORT_DOWN;
758 props->phys_state = state_to_phys_state(props->state);
759 props->active_mtu = IB_MTU_256;
dba3ad2a 760 spin_lock_bh(&iboe->lock);
fa417f7b 761 ndev = iboe->netdevs[port - 1];
5070cd22
MS		 762 if (ndev && is_bonded) {
763 rcu_read_lock(); /* required to get upper dev */
764 ndev = netdev_master_upper_dev_get_rcu(ndev);
765 rcu_read_unlock();
766 }
fa417f7b 767 if (!ndev)
a9c766bb 768 goto out_unlock;
fa417f7b
EC		 769
770 tmp = iboe_get_mtu(ndev->mtu);
771 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
772
21d60609 773 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
fa417f7b
EC		 774 IB_PORT_ACTIVE : IB_PORT_DOWN;
775 props->phys_state = state_to_phys_state(props->state);
a9c766bb 776out_unlock:
dba3ad2a 777 spin_unlock_bh(&iboe->lock);
a9c766bb
OG		 778out:
779 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
780 return err;
fa417f7b
EC		 781}
782
0a9a0188
JM		 783int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
784 struct ib_port_attr *props, int netw_view)
fa417f7b 785{
a9c766bb 786 int err;
fa417f7b 787
c4550c63 788 /* props being zeroed by the caller, avoid zeroing it here */
fa417f7b 789
fa417f7b 790 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
0a9a0188 791 ib_link_query_port(ibdev, port, props, netw_view) :
850b7415 792 eth_link_query_port(ibdev, port, props);
225c7b1f
RD		 793
794 return err;
795}
796
0a9a0188
JM		 797static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
798 struct ib_port_attr *props)
799{
800 /* returns host view */
801 return __mlx4_ib_query_port(ibdev, port, props, 0);
802}
803
a0c64a17
JM		 804int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
805 union ib_gid *gid, int netw_view)
225c7b1f
RD		 806{
807 struct ib_smp *in_mad = NULL;
808 struct ib_smp *out_mad = NULL;
809 int err = -ENOMEM;
a0c64a17
JM		 810 struct mlx4_ib_dev *dev = to_mdev(ibdev);
811 int clear = 0;
812 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 813
814 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
815 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
816 if (!in_mad || !out_mad)
817 goto out;
818
819 init_query_mad(in_mad);
820 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
821 in_mad->attr_mod = cpu_to_be32(port);
822
a0c64a17
JM		 823 if (mlx4_is_mfunc(dev->dev) && netw_view)
824 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
825
826 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 827 if (err)
828 goto out;
829
830 memcpy(gid->raw, out_mad->data + 8, 8);
831
a0c64a17
JM		 832 if (mlx4_is_mfunc(dev->dev) && !netw_view) {
833 if (index) {
834 /* For any index > 0, return the null guid */
835 err = 0;
836 clear = 1;
837 goto out;
838 }
839 }
840
225c7b1f
RD		 841 init_query_mad(in_mad);
842 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
843 in_mad->attr_mod = cpu_to_be32(index / 8);
844
a0c64a17 845 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
0a9a0188 846 NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 847 if (err)
848 goto out;
849
850 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
851
852out:
a0c64a17
JM		 853 if (clear)
854 memset(gid->raw + 8, 0, 8);
225c7b1f
RD		 855 kfree(in_mad);
856 kfree(out_mad);
857 return err;
858}
859
fa417f7b
EC		 860static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
861 union ib_gid *gid)
862{
5070cd22
MS		 863 int ret;
864
865 if (rdma_protocol_ib(ibdev, port))
a0c64a17 866 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
5070cd22
MS		 867
868 if (!rdma_protocol_roce(ibdev, port))
869 return -ENODEV;
870
871 if (!rdma_cap_roce_gid_table(ibdev, port))
872 return -ENODEV;
873
55ee3ab2 874 ret = ib_get_cached_gid(ibdev, port, index, gid, NULL);
5070cd22
MS		 875 if (ret == -EAGAIN) {
876 memcpy(gid, &zgid, sizeof(*gid));
877 return 0;
878 }
879
880 return ret;
fa417f7b
EC		 881}
882
fd10ed8e
JM		 883static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl)
884{
885 union sl2vl_tbl_to_u64 sl2vl64;
886 struct ib_smp *in_mad = NULL;
887 struct ib_smp *out_mad = NULL;
888 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
889 int err = -ENOMEM;
890 int jj;
891
892 if (mlx4_is_slave(to_mdev(ibdev)->dev)) {
893 *sl2vl_tbl = 0;
894 return 0;
895 }
896
897 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
898 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
899 if (!in_mad || !out_mad)
900 goto out;
901
902 init_query_mad(in_mad);
903 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE;
904 in_mad->attr_mod = 0;
905
906 if (mlx4_is_mfunc(to_mdev(ibdev)->dev))
907 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
908
909 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
910 in_mad, out_mad);
911 if (err)
912 goto out;
913
914 for (jj = 0; jj < 8; jj++)
915 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj];
916 *sl2vl_tbl = sl2vl64.sl64;
917
918out:
919 kfree(in_mad);
920 kfree(out_mad);
921 return err;
922}
923
924static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev)
925{
926 u64 sl2vl;
927 int i;
928 int err;
929
930 for (i = 1; i <= mdev->dev->caps.num_ports; i++) {
931 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
932 continue;
933 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl);
934 if (err) {
935 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n",
936 i, err);
937 sl2vl = 0;
938 }
939 atomic64_set(&mdev->sl2vl[i - 1], sl2vl);
940 }
941}
942
0a9a0188
JM		 943int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
944 u16 *pkey, int netw_view)
225c7b1f
RD		 945{
946 struct ib_smp *in_mad = NULL;
947 struct ib_smp *out_mad = NULL;
0a9a0188 948 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 949 int err = -ENOMEM;
950
951 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
952 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
953 if (!in_mad || !out_mad)
954 goto out;
955
956 init_query_mad(in_mad);
957 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
958 in_mad->attr_mod = cpu_to_be32(index / 32);
959
0a9a0188
JM		 960 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
961 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
962
963 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
964 in_mad, out_mad);
225c7b1f
RD		 965 if (err)
966 goto out;
967
968 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
969
970out:
971 kfree(in_mad);
972 kfree(out_mad);
973 return err;
974}
975
0a9a0188
JM		 976static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
977{
978 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
979}
980
225c7b1f
RD		 981static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
982 struct ib_device_modify *props)
983{
d0d68b86 984 struct mlx4_cmd_mailbox *mailbox;
df7fba66 985 unsigned long flags;
d0d68b86 986
225c7b1f
RD		 987 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
988 return -EOPNOTSUPP;
989
d0d68b86
JM		 990 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
991 return 0;
992
992e8e6e
JM		 993 if (mlx4_is_slave(to_mdev(ibdev)->dev))
994 return -EOPNOTSUPP;
995
df7fba66 996 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
bd99fdea 997 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
df7fba66 998 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
d0d68b86
JM		 999
1000 /*
1001 * If possible, pass node desc to FW, so it can generate
1002 * a 144 trap. If cmd fails, just ignore.
1003 */
1004 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
1005 if (IS_ERR(mailbox))
1006 return 0;
1007
bd99fdea 1008 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
d0d68b86 1009 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
992e8e6e 1010 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
d0d68b86
JM		 1011
1012 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
225c7b1f
RD		 1013
1014 return 0;
1015}
1016
61565013
JM		 1017static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
1018 u32 cap_mask)
225c7b1f
RD		 1019{
1020 struct mlx4_cmd_mailbox *mailbox;
1021 int err;
1022
1023 mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
1024 if (IS_ERR(mailbox))
1025 return PTR_ERR(mailbox);
1026
5ae2a7a8
RD		 1027 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1028 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
1029 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
1030 } else {
1031 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
1032 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
1033 }
225c7b1f 1034
a130b590
IS		 1035 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
1036 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1037 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1038
1039 mlx4_free_cmd_mailbox(dev->dev, mailbox);
1040 return err;
1041}
1042
1043static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1044 struct ib_port_modify *props)
1045{
61565013
JM		 1046 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
1047 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
225c7b1f
RD		 1048 struct ib_port_attr attr;
1049 u32 cap_mask;
1050 int err;
1051
61565013
JM		 1052 /* return OK if this is RoCE. CM calls ib_modify_port() regardless
1053 * of whether port link layer is ETH or IB. For ETH ports, qkey
1054 * violations and port capabilities are not meaningful.
1055 */
1056 if (is_eth)
1057 return 0;
1058
1059 mutex_lock(&mdev->cap_mask_mutex);
225c7b1f 1060
c4550c63 1061 err = ib_query_port(ibdev, port, &attr);
225c7b1f
RD		 1062 if (err)
1063 goto out;
1064
1065 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
1066 ~props->clr_port_cap_mask;
1067
61565013
JM		 1068 err = mlx4_ib_SET_PORT(mdev, port,
1069 !!(mask & IB_PORT_RESET_QKEY_CNTR),
1070 cap_mask);
225c7b1f
RD		 1071
1072out:
1073 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
1074 return err;
1075}
1076
1077static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
1078 struct ib_udata *udata)
1079{
1080 struct mlx4_ib_dev *dev = to_mdev(ibdev);
1081 struct mlx4_ib_ucontext *context;
08ff3235 1082 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
225c7b1f
RD		 1083 struct mlx4_ib_alloc_ucontext_resp resp;
1084 int err;
1085
3b4a8cd5
JM		 1086 if (!dev->ib_active)
1087 return ERR_PTR(-EAGAIN);
1088
08ff3235
OG		 1089 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
1090 resp_v3.qp_tab_size = dev->dev->caps.num_qps;
1091 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
1092 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1093 } else {
1094 resp.dev_caps = dev->dev->caps.userspace_caps;
1095 resp.qp_tab_size = dev->dev->caps.num_qps;
1096 resp.bf_reg_size = dev->dev->caps.bf_reg_size;
1097 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1098 resp.cqe_size = dev->dev->caps.cqe_size;
1099 }
225c7b1f 1100
ae184dde 1101 context = kzalloc(sizeof(*context), GFP_KERNEL);
225c7b1f
RD		 1102 if (!context)
1103 return ERR_PTR(-ENOMEM);
1104
1105 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
1106 if (err) {
1107 kfree(context);
1108 return ERR_PTR(err);
1109 }
1110
1111 INIT_LIST_HEAD(&context->db_page_list);
1112 mutex_init(&context->db_page_mutex);
1113
400b1ebc
GL		 1114 INIT_LIST_HEAD(&context->wqn_ranges_list);
1115 mutex_init(&context->wqn_ranges_mutex);
1116
08ff3235
OG		 1117 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
1118 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
1119 else
1120 err = ib_copy_to_udata(udata, &resp, sizeof(resp));
1121
225c7b1f
RD		 1122 if (err) {
1123 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
1124 kfree(context);
1125 return ERR_PTR(-EFAULT);
1126 }
1127
1128 return &context->ibucontext;
1129}
1130
1131static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1132{
1133 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1134
1135 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
1136 kfree(context);
1137
1138 return 0;
1139}
1140
ae184dde
YH		 1141static void mlx4_ib_vma_open(struct vm_area_struct *area)
1142{
1143 /* vma_open is called when a new VMA is created on top of our VMA.
1144 * This is done through either mremap flow or split_vma (usually due
1145 * to mlock, madvise, munmap, etc.). We do not support a clone of the
1146 * vma, as this VMA is strongly hardware related. Therefore we set the
1147 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1148 * calling us again and trying to do incorrect actions. We assume that
1149 * the original vma size is exactly a single page that there will be no
1150 * "splitting" operations on.
1151 */
1152 area->vm_ops = NULL;
1153}
1154
1155static void mlx4_ib_vma_close(struct vm_area_struct *area)
1156{
1157 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
1158
1159 /* It's guaranteed that all VMAs opened on a FD are closed before the
1160 * file itself is closed, therefore no sync is needed with the regular
1161 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
1162 * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
1163 * The close operation is usually called under mm->mmap_sem except when
1164 * process is exiting. The exiting case is handled explicitly as part
1165 * of mlx4_ib_disassociate_ucontext.
1166 */
1167 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
1168 area->vm_private_data;
1169
1170 /* set the vma context pointer to null in the mlx4_ib driver's private
1171 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
1172 */
1173 mlx4_ib_vma_priv_data->vma = NULL;
1174}
1175
1176static const struct vm_operations_struct mlx4_ib_vm_ops = {
1177 .open = mlx4_ib_vma_open,
1178 .close = mlx4_ib_vma_close
1179};
1180
1181static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1182{
1183 int i;
1184 int ret = 0;
1185 struct vm_area_struct *vma;
1186 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1187 struct task_struct *owning_process = NULL;
1188 struct mm_struct *owning_mm = NULL;
1189
1190 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1191 if (!owning_process)
1192 return;
1193
1194 owning_mm = get_task_mm(owning_process);
1195 if (!owning_mm) {
1196 pr_info("no mm, disassociate ucontext is pending task termination\n");
1197 while (1) {
1198 /* make sure that task is dead before returning, it may
1199 * prevent a rare case of module down in parallel to a
1200 * call to mlx4_ib_vma_close.
1201 */
1202 put_task_struct(owning_process);
98e77d9f 1203 usleep_range(1000, 2000);
ae184dde
YH		 1204 owning_process = get_pid_task(ibcontext->tgid,
1205 PIDTYPE_PID);
1206 if (!owning_process ||
1207 owning_process->state == TASK_DEAD) {
1208 pr_info("disassociate ucontext done, task was terminated\n");
1209 /* in case task was dead need to release the task struct */
1210 if (owning_process)
1211 put_task_struct(owning_process);
1212 return;
1213 }
1214 }
1215 }
1216
1217 /* need to protect from a race on closing the vma as part of
1218 * mlx4_ib_vma_close().
1219 */
22c3653d 1220 down_write(&owning_mm->mmap_sem);
ae184dde
YH		 1221 for (i = 0; i < HW_BAR_COUNT; i++) {
1222 vma = context->hw_bar_info[i].vma;
1223 if (!vma)
1224 continue;
1225
1226 ret = zap_vma_ptes(context->hw_bar_info[i].vma,
1227 context->hw_bar_info[i].vma->vm_start,
1228 PAGE_SIZE);
1229 if (ret) {
1230 pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret);
1231 BUG_ON(1);
1232 }
1233
ca37a664
MG		 1234 context->hw_bar_info[i].vma->vm_flags &=
1235 ~(VM_SHARED | VM_MAYSHARE);
ae184dde
YH		 1236 /* context going to be destroyed, should not access ops any more */
1237 context->hw_bar_info[i].vma->vm_ops = NULL;
1238 }
1239
22c3653d 1240 up_write(&owning_mm->mmap_sem);
ae184dde
YH		 1241 mmput(owning_mm);
1242 put_task_struct(owning_process);
1243}
1244
1245static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
1246 struct mlx4_ib_vma_private_data *vma_private_data)
1247{
1248 vma_private_data->vma = vma;
1249 vma->vm_private_data = vma_private_data;
1250 vma->vm_ops = &mlx4_ib_vm_ops;
1251}
1252
225c7b1f
RD		 1253static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
1254{
1255 struct mlx4_ib_dev *dev = to_mdev(context->device);
ae184dde 1256 struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
225c7b1f
RD		 1257
1258 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1259 return -EINVAL;
1260
1261 if (vma->vm_pgoff == 0) {
ae184dde
YH		 1262 /* We prevent double mmaping on same context */
1263 if (mucontext->hw_bar_info[HW_BAR_DB].vma)
1264 return -EINVAL;
1265
225c7b1f
RD		 1266 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1267
1268 if (io_remap_pfn_range(vma, vma->vm_start,
1269 to_mucontext(context)->uar.pfn,
1270 PAGE_SIZE, vma->vm_page_prot))
1271 return -EAGAIN;
ae184dde
YH		 1272
1273 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
1274
225c7b1f 1275 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
ae184dde
YH		 1276 /* We prevent double mmaping on same context */
1277 if (mucontext->hw_bar_info[HW_BAR_BF].vma)
1278 return -EINVAL;
1279
e1d60ec6 1280 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
225c7b1f
RD		 1281
1282 if (io_remap_pfn_range(vma, vma->vm_start,
1283 to_mucontext(context)->uar.pfn +
1284 dev->dev->caps.num_uars,
1285 PAGE_SIZE, vma->vm_page_prot))
1286 return -EAGAIN;
ae184dde
YH		 1287
1288 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
1289
52033cfb
MB		 1290 } else if (vma->vm_pgoff == 3) {
1291 struct mlx4_clock_params params;
ae184dde
YH		 1292 int ret;
1293
1294 /* We prevent double mmaping on same context */
1295 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
1296 return -EINVAL;
1297
1298 ret = mlx4_get_internal_clock_params(dev->dev, &params);
52033cfb
MB		 1299
1300 if (ret)
1301 return ret;
1302
1303 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1304 if (io_remap_pfn_range(vma, vma->vm_start,
1305 (pci_resource_start(dev->dev->persist->pdev,
1306 params.bar) +
1307 params.offset)
1308 >> PAGE_SHIFT,
1309 PAGE_SIZE, vma->vm_page_prot))
1310 return -EAGAIN;
ae184dde
YH		 1311
1312 mlx4_ib_set_vma_data(vma,
1313 &mucontext->hw_bar_info[HW_BAR_CLOCK]);
52033cfb 1314 } else {
225c7b1f 1315 return -EINVAL;
52033cfb 1316 }
225c7b1f
RD		 1317
1318 return 0;
1319}
1320
1321static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
1322 struct ib_ucontext *context,
1323 struct ib_udata *udata)
1324{
1325 struct mlx4_ib_pd *pd;
1326 int err;
1327
1328 pd = kmalloc(sizeof *pd, GFP_KERNEL);
1329 if (!pd)
1330 return ERR_PTR(-ENOMEM);
1331
1332 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
1333 if (err) {
1334 kfree(pd);
1335 return ERR_PTR(err);
1336 }
1337
1338 if (context)
1339 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
1340 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
1341 kfree(pd);
1342 return ERR_PTR(-EFAULT);
1343 }
1344
1345 return &pd->ibpd;
1346}
1347
1348static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
1349{
1350 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
1351 kfree(pd);
1352
1353 return 0;
1354}
1355
012a8ff5
SH		 1356static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
1357 struct ib_ucontext *context,
1358 struct ib_udata *udata)
1359{
1360 struct mlx4_ib_xrcd *xrcd;
8e37210b 1361 struct ib_cq_init_attr cq_attr = {};
012a8ff5
SH		 1362 int err;
1363
1364 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1365 return ERR_PTR(-ENOSYS);
1366
1367 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
1368 if (!xrcd)
1369 return ERR_PTR(-ENOMEM);
1370
1371 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
1372 if (err)
1373 goto err1;
1374
ed082d36 1375 xrcd->pd = ib_alloc_pd(ibdev, 0);
012a8ff5
SH		 1376 if (IS_ERR(xrcd->pd)) {
1377 err = PTR_ERR(xrcd->pd);
1378 goto err2;
1379 }
1380
8e37210b
MB		 1381 cq_attr.cqe = 1;
1382 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
012a8ff5
SH		 1383 if (IS_ERR(xrcd->cq)) {
1384 err = PTR_ERR(xrcd->cq);
1385 goto err3;
1386 }
1387
1388 return &xrcd->ibxrcd;
1389
1390err3:
1391 ib_dealloc_pd(xrcd->pd);
1392err2:
1393 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
1394err1:
1395 kfree(xrcd);
1396 return ERR_PTR(err);
1397}
1398
1399static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
1400{
1401 ib_destroy_cq(to_mxrcd(xrcd)->cq);
1402 ib_dealloc_pd(to_mxrcd(xrcd)->pd);
1403 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
1404 kfree(xrcd);
1405
1406 return 0;
1407}
1408
fa417f7b
EC		 1409static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
1410{
1411 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1412 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1413 struct mlx4_ib_gid_entry *ge;
1414
1415 ge = kzalloc(sizeof *ge, GFP_KERNEL);
1416 if (!ge)
1417 return -ENOMEM;
1418
1419 ge->gid = *gid;
1420 if (mlx4_ib_add_mc(mdev, mqp, gid)) {
1421 ge->port = mqp->port;
1422 ge->added = 1;
1423 }
1424
1425 mutex_lock(&mqp->mutex);
1426 list_add_tail(&ge->list, &mqp->gid_list);
1427 mutex_unlock(&mqp->mutex);
1428
1429 return 0;
1430}
1431
3ba8e31d
EBE		 1432static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
1433 struct mlx4_ib_counters *ctr_table)
1434{
1435 struct counter_index *counter, *tmp_count;
1436
1437 mutex_lock(&ctr_table->mutex);
1438 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
1439 list) {
1440 if (counter->allocated)
1441 mlx4_counter_free(ibdev->dev, counter->index);
1442 list_del(&counter->list);
1443 kfree(counter);
1444 }
1445 mutex_unlock(&ctr_table->mutex);
1446}
1447
fa417f7b
EC		 1448int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
1449 union ib_gid *gid)
1450{
fa417f7b
EC		 1451 struct net_device *ndev;
1452 int ret = 0;
1453
1454 if (!mqp->port)
1455 return 0;
1456
dba3ad2a 1457 spin_lock_bh(&mdev->iboe.lock);
fa417f7b
EC		 1458 ndev = mdev->iboe.netdevs[mqp->port - 1];
1459 if (ndev)
1460 dev_hold(ndev);
dba3ad2a 1461 spin_unlock_bh(&mdev->iboe.lock);
fa417f7b
EC		 1462
1463 if (ndev) {
fa417f7b 1464 ret = 1;
fa417f7b
EC		 1465 dev_put(ndev);
1466 }
1467
1468 return ret;
1469}
1470
0ff1fb65
HHZ		 1471struct mlx4_ib_steering {
1472 struct list_head list;
146d6e19 1473 struct mlx4_flow_reg_id reg_id;
0ff1fb65
HHZ		 1474 union ib_gid gid;
1475};
1476
1f02a09c
MG		 1477#define LAST_ETH_FIELD vlan_tag
1478#define LAST_IB_FIELD sl
1479#define LAST_IPV4_FIELD dst_ip
1480#define LAST_TCP_UDP_FIELD src_port
1481
1482/* Field is the last supported field */
1483#define FIELDS_NOT_SUPPORTED(filter, field)\
1484 memchr_inv((void *)&filter.field +\
1485 sizeof(filter.field), 0,\
1486 sizeof(filter) -\
1487 offsetof(typeof(filter), field) -\
1488 sizeof(filter.field))
1489
f77c0162 1490static int parse_flow_attr(struct mlx4_dev *dev,
a37a1a42 1491 u32 qp_num,
f77c0162
HHZ		 1492 union ib_flow_spec *ib_spec,
1493 struct _rule_hw *mlx4_spec)
1494{
1495 enum mlx4_net_trans_rule_id type;
1496
1497 switch (ib_spec->type) {
1498 case IB_FLOW_SPEC_ETH:
1f02a09c
MG		 1499 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1500 return -ENOTSUPP;
1501
f77c0162
HHZ		 1502 type = MLX4_NET_TRANS_RULE_ID_ETH;
1503 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
1504 ETH_ALEN);
1505 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
1506 ETH_ALEN);
1507 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
1508 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
1509 break;
a37a1a42 1510 case IB_FLOW_SPEC_IB:
1f02a09c
MG		 1511 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD))
1512 return -ENOTSUPP;
1513
a37a1a42
MB		 1514 type = MLX4_NET_TRANS_RULE_ID_IB;
1515 mlx4_spec->ib.l3_qpn =
1516 cpu_to_be32(qp_num);
1517 mlx4_spec->ib.qpn_mask =
1518 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
1519 break;
1520
f77c0162
HHZ		 1521
1522 case IB_FLOW_SPEC_IPV4:
1f02a09c
MG		 1523 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1524 return -ENOTSUPP;
1525
f77c0162
HHZ		 1526 type = MLX4_NET_TRANS_RULE_ID_IPV4;
1527 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
1528 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
1529 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
1530 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
1531 break;
1532
1533 case IB_FLOW_SPEC_TCP:
1534 case IB_FLOW_SPEC_UDP:
1f02a09c
MG		 1535 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD))
1536 return -ENOTSUPP;
1537
f77c0162
HHZ		 1538 type = ib_spec->type == IB_FLOW_SPEC_TCP ?
1539 MLX4_NET_TRANS_RULE_ID_TCP :
1540 MLX4_NET_TRANS_RULE_ID_UDP;
1541 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
1542 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
1543 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
1544 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
1545 break;
1546
1547 default:
1548 return -EINVAL;
1549 }
1550 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
1551 mlx4_hw_rule_sz(dev, type) < 0)
1552 return -EINVAL;
1553 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
1554 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
1555 return mlx4_hw_rule_sz(dev, type);
1556}
1557
a37a1a42
MB		 1558struct default_rules {
1559 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1560 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1561 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
1562 __u8 link_layer;
1563};
1564static const struct default_rules default_table[] = {
1565 {
1566 .mandatory_fields = {IB_FLOW_SPEC_IPV4},
1567 .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
1568 .rules_create_list = {IB_FLOW_SPEC_IB},
1569 .link_layer = IB_LINK_LAYER_INFINIBAND
1570 }
1571};
1572
1573static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
1574 struct ib_flow_attr *flow_attr)
1575{
1576 int i, j, k;
1577 void *ib_flow;
1578 const struct default_rules *pdefault_rules = default_table;
1579 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
1580
a57f23f6 1581 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
a37a1a42
MB		 1582 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
1583 memset(&field_types, 0, sizeof(field_types));
1584
1585 if (link_layer != pdefault_rules->link_layer)
1586 continue;
1587
1588 ib_flow = flow_attr + 1;
1589 /* we assume the specs are sorted */
1590 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
1591 j < flow_attr->num_of_specs; k++) {
1592 union ib_flow_spec *current_flow =
1593 (union ib_flow_spec *)ib_flow;
1594
1595 /* same layer but different type */
1596 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
1597 (pdefault_rules->mandatory_fields[k] &
1598 IB_FLOW_SPEC_LAYER_MASK)) &&
1599 (current_flow->type !=
1600 pdefault_rules->mandatory_fields[k]))
1601 goto out;
1602
1603 /* same layer, try match next one */
1604 if (current_flow->type ==
1605 pdefault_rules->mandatory_fields[k]) {
1606 j++;
1607 ib_flow +=
1608 ((union ib_flow_spec *)ib_flow)->size;
1609 }
1610 }
1611
1612 ib_flow = flow_attr + 1;
1613 for (j = 0; j < flow_attr->num_of_specs;
1614 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
1615 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
1616 /* same layer and same type */
1617 if (((union ib_flow_spec *)ib_flow)->type ==
1618 pdefault_rules->mandatory_not_fields[k])
1619 goto out;
1620
1621 return i;
1622 }
1623out:
1624 return -1;
1625}
1626
1627static int __mlx4_ib_create_default_rules(
1628 struct mlx4_ib_dev *mdev,
1629 struct ib_qp *qp,
1630 const struct default_rules *pdefault_rules,
1631 struct _rule_hw *mlx4_spec) {
1632 int size = 0;
1633 int i;
1634
a57f23f6 1635 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
a37a1a42
MB		 1636 int ret;
1637 union ib_flow_spec ib_spec;
1638 switch (pdefault_rules->rules_create_list[i]) {
1639 case 0:
1640 /* no rule */
1641 continue;
1642 case IB_FLOW_SPEC_IB:
1643 ib_spec.type = IB_FLOW_SPEC_IB;
1644 ib_spec.size = sizeof(struct ib_flow_spec_ib);
1645
1646 break;
1647 default:
1648 /* invalid rule */
1649 return -EINVAL;
1650 }
1651 /* We must put empty rule, qpn is being ignored */
1652 ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
1653 mlx4_spec);
1654 if (ret < 0) {
1655 pr_info("invalid parsing\n");
1656 return -EINVAL;
1657 }
1658
1659 mlx4_spec = (void *)mlx4_spec + ret;
1660 size += ret;
1661 }
1662 return size;
1663}
1664
f77c0162
HHZ		 1665static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1666 int domain,
1667 enum mlx4_net_trans_promisc_mode flow_type,
1668 u64 *reg_id)
1669{
1670 int ret, i;
1671 int size = 0;
1672 void *ib_flow;
1673 struct mlx4_ib_dev *mdev = to_mdev(qp->device);
1674 struct mlx4_cmd_mailbox *mailbox;
1675 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
a37a1a42 1676 int default_flow;
f77c0162
HHZ		 1677
1678 static const u16 __mlx4_domain[] = {
1679 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
1680 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
1681 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
1682 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
1683 };
1684
1685 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
1686 pr_err("Invalid priority value %d\n", flow_attr->priority);
1687 return -EINVAL;
1688 }
1689
1690 if (domain >= IB_FLOW_DOMAIN_NUM) {
1691 pr_err("Invalid domain value %d\n", domain);
1692 return -EINVAL;
1693 }
1694
1695 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
1696 return -EINVAL;
1697
1698 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
1699 if (IS_ERR(mailbox))
1700 return PTR_ERR(mailbox);
f77c0162
HHZ		 1701 ctrl = mailbox->buf;
1702
1703 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
1704 flow_attr->priority);
1705 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
1706 ctrl->port = flow_attr->port;
1707 ctrl->qpn = cpu_to_be32(qp->qp_num);
1708
1709 ib_flow = flow_attr + 1;
1710 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
a37a1a42
MB		 1711 /* Add default flows */
1712 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
1713 if (default_flow >= 0) {
1714 ret = __mlx4_ib_create_default_rules(
1715 mdev, qp, default_table + default_flow,
1716 mailbox->buf + size);
1717 if (ret < 0) {
1718 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1719 return -EINVAL;
1720 }
1721 size += ret;
1722 }
f77c0162 1723 for (i = 0; i < flow_attr->num_of_specs; i++) {
a37a1a42
MB		 1724 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
1725 mailbox->buf + size);
f77c0162
HHZ		 1726 if (ret < 0) {
1727 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1728 return -EINVAL;
1729 }
1730 ib_flow += ((union ib_flow_spec *) ib_flow)->size;
1731 size += ret;
1732 }
1733
10b1c04e
JM		 1734 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR &&
1735 flow_attr->num_of_specs == 1) {
1736 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1);
1737 enum ib_flow_spec_type header_spec =
1738 ((union ib_flow_spec *)(flow_attr + 1))->type;
1739
1740 if (header_spec == IB_FLOW_SPEC_ETH)
1741 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header);
1742 }
1743
f77c0162
HHZ		 1744 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
1745 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
10b1c04e 1746 MLX4_CMD_NATIVE);
f77c0162
HHZ		 1747 if (ret == -ENOMEM)
1748 pr_err("mcg table is full. Fail to register network rule.\n");
1749 else if (ret == -ENXIO)
1750 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
1751 else if (ret)
35fc7b7d 1752 pr_err("Invalid argument. Fail to register network rule.\n");
f77c0162
HHZ		 1753
1754 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1755 return ret;
1756}
1757
1758static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
1759{
1760 int err;
1761 err = mlx4_cmd(dev, reg_id, 0, 0,
1762 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
10b1c04e 1763 MLX4_CMD_NATIVE);
f77c0162
HHZ		 1764 if (err)
1765 pr_err("Fail to detach network rule. registration id = 0x%llx\n",
1766 reg_id);
1767 return err;
1768}
1769
d2fce8a9
OG		 1770static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1771 u64 *reg_id)
1772{
1773 void *ib_flow;
1774 union ib_flow_spec *ib_spec;
1775 struct mlx4_dev *dev = to_mdev(qp->device)->dev;
1776 int err = 0;
1777
5eff6dad
OG		 1778 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
1779 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
d2fce8a9
OG		 1780 return 0; /* do nothing */
1781
1782 ib_flow = flow_attr + 1;
1783 ib_spec = (union ib_flow_spec *)ib_flow;
1784
1785 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
1786 return 0; /* do nothing */
1787
1788 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
1789 flow_attr->port, qp->qp_num,
1790 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
1791 reg_id);
1792 return err;
1793}
1794
0e451e88
MV		 1795static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
1796 struct ib_flow_attr *flow_attr,
1797 enum mlx4_net_trans_promisc_mode *type)
1798{
1799 int err = 0;
1800
1801 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
1802 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
1803 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
1804 return -EOPNOTSUPP;
1805 }
1806
1807 if (flow_attr->num_of_specs == 0) {
1808 type[0] = MLX4_FS_MC_SNIFFER;
1809 type[1] = MLX4_FS_UC_SNIFFER;
1810 } else {
1811 union ib_flow_spec *ib_spec;
1812
1813 ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1814 if (ib_spec->type != IB_FLOW_SPEC_ETH)
1815 return -EINVAL;
1816
1817 /* if all is zero than MC and UC */
1818 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
1819 type[0] = MLX4_FS_MC_SNIFFER;
1820 type[1] = MLX4_FS_UC_SNIFFER;
1821 } else {
1822 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
1823 ib_spec->eth.mask.dst_mac[1],
1824 ib_spec->eth.mask.dst_mac[2],
1825 ib_spec->eth.mask.dst_mac[3],
1826 ib_spec->eth.mask.dst_mac[4],
1827 ib_spec->eth.mask.dst_mac[5]};
1828
1829 /* Above xor was only on MC bit, non empty mask is valid
1830 * only if this bit is set and rest are zero.
1831 */
1832 if (!is_zero_ether_addr(&mac[0]))
1833 return -EINVAL;
1834
1835 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
1836 type[0] = MLX4_FS_MC_SNIFFER;
1837 else
1838 type[0] = MLX4_FS_UC_SNIFFER;
1839 }
1840 }
1841
1842 return err;
1843}
1844
f77c0162
HHZ		 1845static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
1846 struct ib_flow_attr *flow_attr,
1847 int domain)
1848{
146d6e19 1849 int err = 0, i = 0, j = 0;
f77c0162
HHZ		 1850 struct mlx4_ib_flow *mflow;
1851 enum mlx4_net_trans_promisc_mode type[2];
146d6e19
MS		 1852 struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
1853 int is_bonded = mlx4_is_bonded(dev);
f77c0162 1854
5533c18a
YH		 1855 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
1856 return ERR_PTR(-EINVAL);
1857
0e451e88
MV		 1858 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
1859 (flow_attr->type != IB_FLOW_ATTR_NORMAL))
a3100a78
MV		 1860 return ERR_PTR(-EOPNOTSUPP);
1861
f77c0162
HHZ		 1862 memset(type, 0, sizeof(type));
1863
1864 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
1865 if (!mflow) {
1866 err = -ENOMEM;
1867 goto err_free;
1868 }
1869
1870 switch (flow_attr->type) {
1871 case IB_FLOW_ATTR_NORMAL:
0e451e88
MV		 1872 /* If dont trap flag (continue match) is set, under specific
1873 * condition traffic be replicated to given qp,
1874 * without stealing it
1875 */
1876 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
1877 err = mlx4_ib_add_dont_trap_rule(dev,
1878 flow_attr,
1879 type);
1880 if (err)
1881 goto err_free;
1882 } else {
1883 type[0] = MLX4_FS_REGULAR;
1884 }
f77c0162
HHZ		 1885 break;
1886
1887 case IB_FLOW_ATTR_ALL_DEFAULT:
1888 type[0] = MLX4_FS_ALL_DEFAULT;
1889 break;
1890
1891 case IB_FLOW_ATTR_MC_DEFAULT:
1892 type[0] = MLX4_FS_MC_DEFAULT;
1893 break;
1894
1895 case IB_FLOW_ATTR_SNIFFER:
0e451e88
MV		 1896 type[0] = MLX4_FS_MIRROR_RX_PORT;
1897 type[1] = MLX4_FS_MIRROR_SX_PORT;
f77c0162
HHZ		 1898 break;
1899
1900 default:
1901 err = -EINVAL;
1902 goto err_free;
1903 }
1904
1905 while (i < ARRAY_SIZE(type) && type[i]) {
1906 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
146d6e19 1907 &mflow->reg_id[i].id);
f77c0162 1908 if (err)
571e1b2c 1909 goto err_create_flow;
146d6e19 1910 if (is_bonded) {
824c25c1
MS		 1911 /* Application always sees one port so the mirror rule
1912 * must be on port #2
1913 */
146d6e19
MS		 1914 flow_attr->port = 2;
1915 err = __mlx4_ib_create_flow(qp, flow_attr,
1916 domain, type[j],
1917 &mflow->reg_id[j].mirror);
1918 flow_attr->port = 1;
1919 if (err)
1920 goto err_create_flow;
1921 j++;
1922 }
1923
11562568 1924 i++;
f77c0162
HHZ		 1925 }
1926
d2fce8a9 1927 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
146d6e19
MS		 1928 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1929 &mflow->reg_id[i].id);
d2fce8a9 1930 if (err)
571e1b2c 1931 goto err_create_flow;
11562568 1932
146d6e19
MS		 1933 if (is_bonded) {
1934 flow_attr->port = 2;
1935 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1936 &mflow->reg_id[j].mirror);
1937 flow_attr->port = 1;
1938 if (err)
1939 goto err_create_flow;
1940 j++;
1941 }
1942 /* function to create mirror rule */
11562568 1943 i++;
d2fce8a9
OG		 1944 }
1945
f77c0162
HHZ		 1946 return &mflow->ibflow;
1947
571e1b2c
OG		 1948err_create_flow:
1949 while (i) {
146d6e19
MS		 1950 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1951 mflow->reg_id[i].id);
571e1b2c
OG		 1952 i--;
1953 }
146d6e19
MS		 1954
1955 while (j) {
1956 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1957 mflow->reg_id[j].mirror);
1958 j--;
1959 }
f77c0162
HHZ		 1960err_free:
1961 kfree(mflow);
1962 return ERR_PTR(err);
1963}
1964
1965static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
1966{
1967 int err, ret = 0;
1968 int i = 0;
1969 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
1970 struct mlx4_ib_flow *mflow = to_mflow(flow_id);
1971
146d6e19
MS		 1972 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
1973 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
f77c0162
HHZ		 1974 if (err)
1975 ret = err;
146d6e19
MS		 1976 if (mflow->reg_id[i].mirror) {
1977 err = __mlx4_ib_destroy_flow(mdev->dev,
1978 mflow->reg_id[i].mirror);
1979 if (err)
1980 ret = err;
1981 }
f77c0162
HHZ		 1982 i++;
1983 }
1984
1985 kfree(mflow);
1986 return ret;
1987}
1988
225c7b1f
RD		 1989static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1990{
fa417f7b
EC		 1991 int err;
1992 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
146d6e19 1993 struct mlx4_dev *dev = mdev->dev;
fa417f7b 1994 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
0ff1fb65 1995 struct mlx4_ib_steering *ib_steering = NULL;
e9a7faf1 1996 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
146d6e19 1997 struct mlx4_flow_reg_id reg_id;
0ff1fb65
HHZ		 1998
1999 if (mdev->dev->caps.steering_mode ==
2000 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2001 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
2002 if (!ib_steering)
2003 return -ENOMEM;
2004 }
fa417f7b 2005
0ff1fb65
HHZ		 2006 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
2007 !!(mqp->flags &
2008 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
146d6e19 2009 prot, &reg_id.id);
e9a7faf1
OG		 2010 if (err) {
2011 pr_err("multicast attach op failed, err %d\n", err);
0ff1fb65 2012 goto err_malloc;
e9a7faf1 2013 }
fa417f7b 2014
146d6e19
MS		 2015 reg_id.mirror = 0;
2016 if (mlx4_is_bonded(dev)) {
824c25c1
MS		 2017 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
2018 (mqp->port == 1) ? 2 : 1,
146d6e19
MS		 2019 !!(mqp->flags &
2020 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
2021 prot, &reg_id.mirror);
2022 if (err)
2023 goto err_add;
2024 }
2025
fa417f7b
EC		 2026 err = add_gid_entry(ibqp, gid);
2027 if (err)
2028 goto err_add;
2029
0ff1fb65
HHZ		 2030 if (ib_steering) {
2031 memcpy(ib_steering->gid.raw, gid->raw, 16);
2032 ib_steering->reg_id = reg_id;
2033 mutex_lock(&mqp->mutex);
2034 list_add(&ib_steering->list, &mqp->steering_rules);
2035 mutex_unlock(&mqp->mutex);
2036 }
fa417f7b
EC		 2037 return 0;
2038
2039err_add:
0ff1fb65 2040 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
146d6e19
MS		 2041 prot, reg_id.id);
2042 if (reg_id.mirror)
2043 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2044 prot, reg_id.mirror);
0ff1fb65
HHZ		 2045err_malloc:
2046 kfree(ib_steering);
2047
fa417f7b
EC		 2048 return err;
2049}
2050
2051static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
2052{
2053 struct mlx4_ib_gid_entry *ge;
2054 struct mlx4_ib_gid_entry *tmp;
2055 struct mlx4_ib_gid_entry *ret = NULL;
2056
2057 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
2058 if (!memcmp(raw, ge->gid.raw, 16)) {
2059 ret = ge;
2060 break;
2061 }
2062 }
2063
2064 return ret;
225c7b1f
RD		 2065}
2066
2067static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2068{
fa417f7b
EC		 2069 int err;
2070 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
146d6e19 2071 struct mlx4_dev *dev = mdev->dev;
fa417f7b 2072 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
fa417f7b
EC		 2073 struct net_device *ndev;
2074 struct mlx4_ib_gid_entry *ge;
146d6e19 2075 struct mlx4_flow_reg_id reg_id = {0, 0};
e9a7faf1 2076 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
0ff1fb65
HHZ		 2077
2078 if (mdev->dev->caps.steering_mode ==
2079 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2080 struct mlx4_ib_steering *ib_steering;
2081
2082 mutex_lock(&mqp->mutex);
2083 list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
2084 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
2085 list_del(&ib_steering->list);
2086 break;
2087 }
2088 }
2089 mutex_unlock(&mqp->mutex);
2090 if (&ib_steering->list == &mqp->steering_rules) {
2091 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
2092 return -EINVAL;
2093 }
2094 reg_id = ib_steering->reg_id;
2095 kfree(ib_steering);
2096 }
fa417f7b 2097
0ff1fb65 2098 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
146d6e19 2099 prot, reg_id.id);
fa417f7b
EC		 2100 if (err)
2101 return err;
2102
146d6e19
MS		 2103 if (mlx4_is_bonded(dev)) {
2104 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2105 prot, reg_id.mirror);
2106 if (err)
2107 return err;
2108 }
2109
fa417f7b
EC		 2110 mutex_lock(&mqp->mutex);
2111 ge = find_gid_entry(mqp, gid->raw);
2112 if (ge) {
dba3ad2a 2113 spin_lock_bh(&mdev->iboe.lock);
fa417f7b
EC		 2114 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
2115 if (ndev)
2116 dev_hold(ndev);
dba3ad2a 2117 spin_unlock_bh(&mdev->iboe.lock);
d487ee77 2118 if (ndev)
fa417f7b 2119 dev_put(ndev);
fa417f7b
EC		 2120 list_del(&ge->list);
2121 kfree(ge);
2122 } else
987c8f8f 2123 pr_warn("could not find mgid entry\n");
fa417f7b
EC		 2124
2125 mutex_unlock(&mqp->mutex);
2126
2127 return 0;
225c7b1f
RD		 2128}
2129
2130static int init_node_data(struct mlx4_ib_dev *dev)
2131{
2132 struct ib_smp *in_mad = NULL;
2133 struct ib_smp *out_mad = NULL;
0a9a0188 2134 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
225c7b1f
RD		 2135 int err = -ENOMEM;
2136
2137 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
2138 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
2139 if (!in_mad || !out_mad)
2140 goto out;
2141
2142 init_query_mad(in_mad);
2143 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
0a9a0188
JM		 2144 if (mlx4_is_master(dev->dev))
2145 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
225c7b1f 2146
0a9a0188 2147 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 2148 if (err)
2149 goto out;
2150
bd99fdea 2151 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX);
225c7b1f
RD		 2152
2153 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
2154
0a9a0188 2155 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
225c7b1f
RD		 2156 if (err)
2157 goto out;
2158
992e8e6e 2159 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
225c7b1f
RD		 2160 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
2161
2162out:
2163 kfree(in_mad);
2164 kfree(out_mad);
2165 return err;
2166}
2167
f4e91eb4
TJ		 2168static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2169 char *buf)
cd9281d8 2170{
f4e91eb4
TJ		 2171 struct mlx4_ib_dev *dev =
2172 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
872bf2fb 2173 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
cd9281d8
JM		 2174}
2175
f4e91eb4
TJ		 2176static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2177 char *buf)
cd9281d8 2178{
f4e91eb4
TJ		 2179 struct mlx4_ib_dev *dev =
2180 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
cd9281d8
JM		 2181 return sprintf(buf, "%x\n", dev->dev->rev_id);
2182}
2183
f4e91eb4
TJ		 2184static ssize_t show_board(struct device *device, struct device_attribute *attr,
2185 char *buf)
cd9281d8 2186{
f4e91eb4
TJ		 2187 struct mlx4_ib_dev *dev =
2188 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2189 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
2190 dev->dev->board_id);
cd9281d8
JM		 2191}
2192
f4e91eb4 2193static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
f4e91eb4
TJ		 2194static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2195static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
cd9281d8 2196
f4e91eb4
TJ		 2197static struct device_attribute *mlx4_class_attributes[] = {
2198 &dev_attr_hw_rev,
f4e91eb4
TJ		 2199 &dev_attr_hca_type,
2200 &dev_attr_board_id
cd9281d8
JM		 2201};
2202
3f85f2aa
MB		 2203struct diag_counter {
2204 const char *name;
2205 u32 offset;
2206};
2207
2208#define DIAG_COUNTER(_name, _offset) \
2209 { .name = #_name, .offset = _offset }
2210
2211static const struct diag_counter diag_basic[] = {
2212 DIAG_COUNTER(rq_num_lle, 0x00),
2213 DIAG_COUNTER(sq_num_lle, 0x04),
2214 DIAG_COUNTER(rq_num_lqpoe, 0x08),
2215 DIAG_COUNTER(sq_num_lqpoe, 0x0C),
2216 DIAG_COUNTER(rq_num_lpe, 0x18),
2217 DIAG_COUNTER(sq_num_lpe, 0x1C),
2218 DIAG_COUNTER(rq_num_wrfe, 0x20),
2219 DIAG_COUNTER(sq_num_wrfe, 0x24),
2220 DIAG_COUNTER(sq_num_mwbe, 0x2C),
2221 DIAG_COUNTER(sq_num_bre, 0x34),
2222 DIAG_COUNTER(sq_num_rire, 0x44),
2223 DIAG_COUNTER(rq_num_rire, 0x48),
2224 DIAG_COUNTER(sq_num_rae, 0x4C),
2225 DIAG_COUNTER(rq_num_rae, 0x50),
2226 DIAG_COUNTER(sq_num_roe, 0x54),
2227 DIAG_COUNTER(sq_num_tree, 0x5C),
2228 DIAG_COUNTER(sq_num_rree, 0x64),
2229 DIAG_COUNTER(rq_num_rnr, 0x68),
2230 DIAG_COUNTER(sq_num_rnr, 0x6C),
2231 DIAG_COUNTER(rq_num_oos, 0x100),
2232 DIAG_COUNTER(sq_num_oos, 0x104),
2233};
2234
2235static const struct diag_counter diag_ext[] = {
2236 DIAG_COUNTER(rq_num_dup, 0x130),
2237 DIAG_COUNTER(sq_num_to, 0x134),
2238};
2239
2240static const struct diag_counter diag_device_only[] = {
2241 DIAG_COUNTER(num_cqovf, 0x1A0),
2242 DIAG_COUNTER(rq_num_udsdprd, 0x118),
2243};
2244
2245static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
2246 u8 port_num)
2247{
2248 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2249 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2250
2251 if (!diag[!!port_num].name)
2252 return NULL;
2253
2254 return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
2255 diag[!!port_num].num_counters,
2256 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2257}
2258
2259static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
2260 struct rdma_hw_stats *stats,
2261 u8 port, int index)
2262{
2263 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2264 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2265 u32 hw_value[ARRAY_SIZE(diag_device_only) +
2266 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
2267 int ret;
2268 int i;
2269
2270 ret = mlx4_query_diag_counters(dev->dev,
2271 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
2272 diag[!!port].offset, hw_value,
2273 diag[!!port].num_counters, port);
2274
2275 if (ret)
2276 return ret;
2277
2278 for (i = 0; i < diag[!!port].num_counters; i++)
2279 stats->value[i] = hw_value[i];
2280
2281 return diag[!!port].num_counters;
2282}
2283
2284static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
2285 const char ***name,
2286 u32 **offset,
2287 u32 *num,
2288 bool port)
2289{
2290 u32 num_counters;
2291
2292 num_counters = ARRAY_SIZE(diag_basic);
2293
2294 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
2295 num_counters += ARRAY_SIZE(diag_ext);
2296
2297 if (!port)
2298 num_counters += ARRAY_SIZE(diag_device_only);
2299
2300 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
2301 if (!*name)
2302 return -ENOMEM;
2303
2304 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
2305 if (!*offset)
2306 goto err_name;
2307
2308 *num = num_counters;
2309
2310 return 0;
2311
2312err_name:
2313 kfree(*name);
2314 return -ENOMEM;
2315}
2316
2317static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
2318 const char **name,
2319 u32 *offset,
2320 bool port)
2321{
2322 int i;
2323 int j;
2324
2325 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
2326 name[i] = diag_basic[i].name;
2327 offset[i] = diag_basic[i].offset;
2328 }
2329
2330 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
2331 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
2332 name[j] = diag_ext[i].name;
2333 offset[j] = diag_ext[i].offset;
2334 }
2335 }
2336
2337 if (!port) {
2338 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
2339 name[j] = diag_device_only[i].name;
2340 offset[j] = diag_device_only[i].offset;
2341 }
2342 }
2343}
2344
2345static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
2346{
2347 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
2348 int i;
2349 int ret;
2350 bool per_port = !!(ibdev->dev->caps.flags2 &
2351 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
2352
69d269d3
KH		 2353 if (mlx4_is_slave(ibdev->dev))
2354 return 0;
2355
3f85f2aa
MB		 2356 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2357 /* i == 1 means we are building port counters */
2358 if (i && !per_port)
2359 continue;
2360
2361 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
2362 &diag[i].offset,
2363 &diag[i].num_counters, i);
2364 if (ret)
2365 goto err_alloc;
2366
2367 mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
2368 diag[i].offset, i);
2369 }
2370
2371 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats;
2372 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats;
2373
2374 return 0;
2375
2376err_alloc:
2377 if (i) {
2378 kfree(diag[i - 1].name);
2379 kfree(diag[i - 1].offset);
2380 }
2381
2382 return ret;
2383}
2384
2385static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
2386{
2387 int i;
2388
2389 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2390 kfree(ibdev->diag_counters[i].offset);
2391 kfree(ibdev->diag_counters[i].name);
2392 }
2393}
2394
9433c188
MB		 2395#define MLX4_IB_INVALID_MAC ((u64)-1)
2396static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
2397 struct net_device *dev,
2398 int port)
2399{
2400 u64 new_smac = 0;
2401 u64 release_mac = MLX4_IB_INVALID_MAC;
2402 struct mlx4_ib_qp *qp;
2403
2404 read_lock(&dev_base_lock);
2405 new_smac = mlx4_mac_to_u64(dev->dev_addr);
2406 read_unlock(&dev_base_lock);
2407
3e0629cb
JM		 2408 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
2409
d24d9f43
JM		 2410 /* no need for update QP1 and mac registration in non-SRIOV */
2411 if (!mlx4_is_mfunc(ibdev->dev))
2412 return;
2413
9433c188
MB		 2414 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
2415 qp = ibdev->qp1_proxy[port - 1];
2416 if (qp) {
2417 int new_smac_index;
25476b02 2418 u64 old_smac;
9433c188
MB		 2419 struct mlx4_update_qp_params update_params;
2420
25476b02
JM		 2421 mutex_lock(&qp->mutex);
2422 old_smac = qp->pri.smac;
9433c188
MB		 2423 if (new_smac == old_smac)
2424 goto unlock;
2425
2426 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
2427
2428 if (new_smac_index < 0)
2429 goto unlock;
2430
2431 update_params.smac_index = new_smac_index;
09e05c3f 2432 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
9433c188
MB		 2433 &update_params)) {
2434 release_mac = new_smac;
2435 goto unlock;
2436 }
25476b02
JM		 2437 /* if old port was zero, no mac was yet registered for this QP */
2438 if (qp->pri.smac_port)
2439 release_mac = old_smac;
9433c188 2440 qp->pri.smac = new_smac;
25476b02 2441 qp->pri.smac_port = port;
9433c188 2442 qp->pri.smac_index = new_smac_index;
9433c188
MB		 2443 }
2444
2445unlock:
9433c188
MB		 2446 if (release_mac != MLX4_IB_INVALID_MAC)
2447 mlx4_unregister_mac(ibdev->dev, port, release_mac);
25476b02
JM		 2448 if (qp)
2449 mutex_unlock(&qp->mutex);
2450 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
9433c188
MB		 2451}
2452
9433c188
MB		 2453static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
2454 struct net_device *dev,
2455 unsigned long event)
2456
d487ee77 2457{
fa417f7b 2458 struct mlx4_ib_iboe *iboe;
9433c188 2459 int update_qps_port = -1;
fa417f7b
EC		 2460 int port;
2461
5070cd22
MS		 2462 ASSERT_RTNL();
2463
fa417f7b
EC		 2464 iboe = &ibdev->iboe;
2465
dba3ad2a 2466 spin_lock_bh(&iboe->lock);
fa417f7b 2467 mlx4_foreach_ib_transport_port(port, ibdev->dev) {
ad4885d2 2468
fa417f7b 2469 iboe->netdevs[port - 1] =
0345584e 2470 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
fa417f7b 2471
9433c188
MB		 2472 if (dev == iboe->netdevs[port - 1] &&
2473 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
2474 event == NETDEV_UP || event == NETDEV_CHANGE))
2475 update_qps_port = port;
2476
d487ee77 2477 }
dba3ad2a 2478 spin_unlock_bh(&iboe->lock);
9433c188
MB		 2479
2480 if (update_qps_port > 0)
2481 mlx4_ib_update_qps(ibdev, dev, update_qps_port);
d487ee77
MS		 2482}
2483
2484static int mlx4_ib_netdev_event(struct notifier_block *this,
2485 unsigned long event, void *ptr)
2486{
2487 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
2488 struct mlx4_ib_dev *ibdev;
2489
2490 if (!net_eq(dev_net(dev), &init_net))
2491 return NOTIFY_DONE;
2492
2493 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
9433c188 2494 mlx4_ib_scan_netdevs(ibdev, dev, event);
fa417f7b
EC		 2495
2496 return NOTIFY_DONE;
2497}
2498
54679e14
JM		 2499static void init_pkeys(struct mlx4_ib_dev *ibdev)
2500{
2501 int port;
2502 int slave;
2503 int i;
2504
2505 if (mlx4_is_master(ibdev->dev)) {
872bf2fb
YH		 2506 for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
2507 ++slave) {
54679e14
JM		 2508 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2509 for (i = 0;
2510 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2511 ++i) {
2512 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
2513 /* master has the identity virt2phys pkey mapping */
2514 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
2515 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
2516 mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
2517 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
2518 }
2519 }
2520 }
2521 /* initialize pkey cache */
2522 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2523 for (i = 0;
2524 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2525 ++i)
2526 ibdev->pkeys.phys_pkey_cache[port-1][i] =
2527 (i) ? 0 : 0xFFFF;
2528 }
2529 }
2530}
2531
e605b743
SP		 2532static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2533{
c66fa19c 2534 int i, j, eq = 0, total_eqs = 0;
e605b743 2535
c66fa19c
MB		 2536 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
2537 sizeof(ibdev->eq_table[0]), GFP_KERNEL);
e605b743
SP		 2538 if (!ibdev->eq_table)
2539 return;
2540
c66fa19c
MB		 2541 for (i = 1; i <= dev->caps.num_ports; i++) {
2542 for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
2543 j++, total_eqs++) {
2544 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
2545 continue;
2546 ibdev->eq_table[eq] = total_eqs;
2547 if (!mlx4_assign_eq(dev, i,
2548 &ibdev->eq_table[eq]))
2549 eq++;
2550 else
2551 ibdev->eq_table[eq] = -1;
e605b743
SP		 2552 }
2553 }
2554
c66fa19c
MB		 2555 for (i = eq; i < dev->caps.num_comp_vectors;
2556 ibdev->eq_table[i++] = -1)
2557 ;
e605b743
SP		 2558
2559 /* Advertise the new number of EQs to clients */
c66fa19c 2560 ibdev->ib_dev.num_comp_vectors = eq;
e605b743
SP		 2561}
2562
2563static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2564{
2565 int i;
c66fa19c 2566 int total_eqs = ibdev->ib_dev.num_comp_vectors;
3aac6ff1 2567
c66fa19c 2568 /* no eqs were allocated */
3aac6ff1
SP		 2569 if (!ibdev->eq_table)
2570 return;
e605b743
SP		 2571
2572 /* Reset the advertised EQ number */
c66fa19c 2573 ibdev->ib_dev.num_comp_vectors = 0;
e605b743 2574
c66fa19c 2575 for (i = 0; i < total_eqs; i++)
e605b743 2576 mlx4_release_eq(dev, ibdev->eq_table[i]);
e605b743 2577
e605b743 2578 kfree(ibdev->eq_table);
c66fa19c 2579 ibdev->eq_table = NULL;
e605b743
SP		 2580}
2581
7738613e
IW		 2582static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
2583 struct ib_port_immutable *immutable)
2584{
2585 struct ib_port_attr attr;
4ed088e6 2586 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
7738613e
IW		 2587 int err;
2588
4ed088e6 2589 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
f9b22e35 2590 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
bc63f9d5 2591 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4ed088e6
MB		 2592 } else {
2593 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
2594 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
2595 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
2596 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
2597 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
bc63f9d5
OG		 2598 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET;
2599 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE |
2600 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP))
2601 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4ed088e6 2602 }
f9b22e35 2603
c4550c63
OG		 2604 err = ib_query_port(ibdev, port_num, &attr);
2605 if (err)
2606 return err;
2607
2608 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2609 immutable->gid_tbl_len = attr.gid_tbl_len;
2610
7738613e
IW		 2611 return 0;
2612}
2613
9abb0d1b 2614static void get_fw_ver_str(struct ib_device *device, char *str)
e9db59fc
IW		 2615{
2616 struct mlx4_ib_dev *dev =
2617 container_of(device, struct mlx4_ib_dev, ib_dev);
9abb0d1b 2618 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d",
e9db59fc
IW		 2619 (int) (dev->dev->caps.fw_ver >> 32),
2620 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
2621 (int) dev->dev->caps.fw_ver & 0xffff);
2622}
2623
225c7b1f
RD		 2624static void *mlx4_ib_add(struct mlx4_dev *dev)
2625{
2626 struct mlx4_ib_dev *ibdev;
22e7ef9c 2627 int num_ports = 0;
035b1032 2628 int i, j;
fa417f7b
EC		 2629 int err;
2630 struct mlx4_ib_iboe *iboe;
4196670b 2631 int ib_num_ports = 0;
a5750090 2632 int num_req_counters;
c3abb51b
EBE		 2633 int allocated;
2634 u32 counter_index;
3ba8e31d 2635 struct counter_index *new_counter_index = NULL;
225c7b1f 2636
987c8f8f 2637 pr_info_once("%s", mlx4_ib_version);
68f3948d 2638
026149cb 2639 num_ports = 0;
fa417f7b 2640 mlx4_foreach_ib_transport_port(i, dev)
22e7ef9c
RD		 2641 num_ports++;
2642
2643 /* No point in registering a device with no ports... */
2644 if (num_ports == 0)
2645 return NULL;
2646
225c7b1f
RD		 2647 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
2648 if (!ibdev) {
872bf2fb
YH		 2649 dev_err(&dev->persist->pdev->dev,
2650 "Device struct alloc failed\n");
225c7b1f
RD		 2651 return NULL;
2652 }
2653
fa417f7b
EC		 2654 iboe = &ibdev->iboe;
2655
225c7b1f
RD		 2656 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
2657 goto err_dealloc;
2658
2659 if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
2660 goto err_pd;
2661
4979d18f
RD		 2662 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
2663 PAGE_SIZE);
225c7b1f
RD		 2664 if (!ibdev->uar_map)
2665 goto err_uar;
26c6bc7b 2666 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
225c7b1f 2667
225c7b1f 2668 ibdev->dev = dev;
c6215745 2669 ibdev->bond_next_port = 0;
225c7b1f
RD		 2670
2671 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
2672 ibdev->ib_dev.owner = THIS_MODULE;
2673 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
95d04f07 2674 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
22e7ef9c 2675 ibdev->num_ports = num_ports;
a5750090
MS		 2676 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
2677 1 : ibdev->num_ports;
b8dd786f 2678 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
d66c88a8 2679 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev;
5070cd22
MS		 2680 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
2681 ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
2682 ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
225c7b1f 2683
08ff3235
OG		 2684 if (dev->caps.userspace_caps)
2685 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
2686 else
2687 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
2688
225c7b1f
RD		 2689 ibdev->ib_dev.uverbs_cmd_mask =
2690 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2691 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2692 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2693 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2694 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2695 (1ull << IB_USER_VERBS_CMD_REG_MR) |
9376932d 2696 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
225c7b1f
RD		 2697 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2698 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2699 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
bbf8eed1 2700 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
225c7b1f
RD		 2701 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2702 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2703 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6a775e2b 2704 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
225c7b1f
RD		 2705 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2706 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2707 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2708 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2709 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
65541cb7 2710 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
18abd5ea 2711 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
42849b26
SH		 2712 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2713 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
225c7b1f
RD		 2714
2715 ibdev->ib_dev.query_device = mlx4_ib_query_device;
2716 ibdev->ib_dev.query_port = mlx4_ib_query_port;
fa417f7b 2717 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
225c7b1f
RD		 2718 ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
2719 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
2720 ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
2721 ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
2722 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
2723 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
2724 ibdev->ib_dev.mmap = mlx4_ib_mmap;
2725 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
2726 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
2727 ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
2728 ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
2729 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
2730 ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
2731 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
65541cb7 2732 ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
225c7b1f
RD		 2733 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
2734 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
2735 ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
2736 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
6a775e2b 2737 ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
225c7b1f
RD		 2738 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
2739 ibdev->ib_dev.post_send = mlx4_ib_post_send;
2740 ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
2741 ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
3fdcb97f 2742 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
bbf8eed1 2743 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
225c7b1f
RD		 2744 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
2745 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
2746 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
2747 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
2748 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
9376932d 2749 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
225c7b1f 2750 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
679e34d1 2751 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
1b2cd0fc 2752 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg;
225c7b1f
RD		 2753 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
2754 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
2755 ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
7738613e 2756 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
e9db59fc 2757 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str;
ae184dde 2758 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
225c7b1f 2759
34d9a270
YC		 2760 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2761 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
2762
400b1ebc
GL		 2763 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) &&
2764 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) ==
2765 IB_LINK_LAYER_ETHERNET) ||
2766 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) ==
2767 IB_LINK_LAYER_ETHERNET))) {
2768 ibdev->ib_dev.create_wq = mlx4_ib_create_wq;
2769 ibdev->ib_dev.modify_wq = mlx4_ib_modify_wq;
2770 ibdev->ib_dev.destroy_wq = mlx4_ib_destroy_wq;
b8d46ca0
GL		 2771 ibdev->ib_dev.create_rwq_ind_table =
2772 mlx4_ib_create_rwq_ind_table;
2773 ibdev->ib_dev.destroy_rwq_ind_table =
2774 mlx4_ib_destroy_rwq_ind_table;
400b1ebc 2775 ibdev->ib_dev.uverbs_ex_cmd_mask |=
b8d46ca0
GL		 2776 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
2777 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
2778 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
2779 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
2780 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
400b1ebc
GL		 2781 }
2782
992e8e6e
JM		 2783 if (!mlx4_is_slave(ibdev->dev)) {
2784 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
2785 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
2786 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
2787 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
2788 }
8ad11fb6 2789
b425388d
SM		 2790 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2791 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
2792 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
b425388d
SM		 2793 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
2794
2795 ibdev->ib_dev.uverbs_cmd_mask |=
2796 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2797 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2798 }
2799
012a8ff5
SH		 2800 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
2801 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
2802 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
2803 ibdev->ib_dev.uverbs_cmd_mask |=
2804 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2805 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2806 }
2807
f77c0162 2808 if (check_flow_steering_support(dev)) {
0a9b7d59 2809 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
f77c0162
HHZ		 2810 ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
2811 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
2812
f21519b2
YD		 2813 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2814 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2815 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
f77c0162
HHZ		 2816 }
2817
4b664c43
MB		 2818 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2819 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
fbfb6625
EBE		 2820 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2821 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
4b664c43 2822
e605b743
SP		 2823 mlx4_ib_alloc_eqs(dev, ibdev);
2824
fa417f7b
EC		 2825 spin_lock_init(&iboe->lock);
2826
225c7b1f
RD		 2827 if (init_node_data(ibdev))
2828 goto err_map;
fd10ed8e 2829 mlx4_init_sl2vl_tbl(ibdev);
225c7b1f 2830
3ba8e31d
EBE		 2831 for (i = 0; i < ibdev->num_ports; ++i) {
2832 mutex_init(&ibdev->counters_table[i].mutex);
2833 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
2834 }
2835
a5750090
MS		 2836 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
2837 for (i = 0; i < num_req_counters; ++i) {
9433c188 2838 mutex_init(&ibdev->qp1_proxy_lock[i]);
c3abb51b 2839 allocated = 0;
cfcde11c
OG		 2840 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
2841 IB_LINK_LAYER_ETHERNET) {
f3301870
MS		 2842 err = mlx4_counter_alloc(ibdev->dev, &counter_index,
2843 MLX4_RES_USAGE_DRIVER);
c3abb51b 2844 /* if failed to allocate a new counter, use default */
cfcde11c 2845 if (err)
c3abb51b
EBE		 2846 counter_index =
2847 mlx4_get_default_counter_index(dev,
2848 i + 1);
2849 else
2850 allocated = 1;
2851 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
2852 counter_index = mlx4_get_default_counter_index(dev,
2853 i + 1);
3839d8ac 2854 }
3ba8e31d
EBE		 2855 new_counter_index = kmalloc(sizeof(*new_counter_index),
2856 GFP_KERNEL);
2857 if (!new_counter_index) {
2858 if (allocated)
2859 mlx4_counter_free(ibdev->dev, counter_index);
2860 goto err_counter;
2861 }
2862 new_counter_index->index = counter_index;
2863 new_counter_index->allocated = allocated;
2864 list_add_tail(&new_counter_index->list,
2865 &ibdev->counters_table[i].counters_list);
2866 ibdev->counters_table[i].default_counter = counter_index;
c3abb51b
EBE		 2867 pr_info("counter index %d for port %d allocated %d\n",
2868 counter_index, i + 1, allocated);
cfcde11c 2869 }
a5750090 2870 if (mlx4_is_bonded(dev))
c3abb51b 2871 for (i = 1; i < ibdev->num_ports ; ++i) {
3ba8e31d
EBE		 2872 new_counter_index =
2873 kmalloc(sizeof(struct counter_index),
2874 GFP_KERNEL);
2875 if (!new_counter_index)
2876 goto err_counter;
2877 new_counter_index->index = counter_index;
2878 new_counter_index->allocated = 0;
2879 list_add_tail(&new_counter_index->list,
2880 &ibdev->counters_table[i].counters_list);
2881 ibdev->counters_table[i].default_counter =
2882 counter_index;
c3abb51b 2883 }
cfcde11c 2884
4196670b
MB		 2885 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2886 ib_num_ports++;
2887
225c7b1f
RD		 2888 spin_lock_init(&ibdev->sm_lock);
2889 mutex_init(&ibdev->cap_mask_mutex);
35f05dab
YH		 2890 INIT_LIST_HEAD(&ibdev->qp_list);
2891 spin_lock_init(&ibdev->reset_flow_resource_lock);
225c7b1f 2892
4196670b
MB		 2893 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2894 ib_num_ports) {
c1c98501
MB		 2895 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
2896 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
2897 MLX4_IB_UC_STEER_QPN_ALIGN,
f3301870
MS		 2898 &ibdev->steer_qpn_base, 0,
2899 MLX4_RES_USAGE_DRIVER);
c1c98501
MB		 2900 if (err)
2901 goto err_counter;
2902
2903 ibdev->ib_uc_qpns_bitmap =
2904 kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
2905 sizeof(long),
2906 GFP_KERNEL);
15d4626e 2907 if (!ibdev->ib_uc_qpns_bitmap)
c1c98501 2908 goto err_steer_qp_release;
c1c98501 2909
1f22e454
EBE		 2910 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) {
2911 bitmap_zero(ibdev->ib_uc_qpns_bitmap,
2912 ibdev->steer_qpn_count);
2913 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2914 dev, ibdev->steer_qpn_base,
2915 ibdev->steer_qpn_base +
2916 ibdev->steer_qpn_count - 1);
2917 if (err)
2918 goto err_steer_free_bitmap;
2919 } else {
2920 bitmap_fill(ibdev->ib_uc_qpns_bitmap,
2921 ibdev->steer_qpn_count);
2922 }
c1c98501
MB		 2923 }
2924
3e0629cb
JM		 2925 for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
2926 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
2927
3f85f2aa 2928 if (mlx4_ib_alloc_diag_counters(ibdev))
c1c98501 2929 goto err_steer_free_bitmap;
225c7b1f 2930
3f85f2aa
MB		 2931 if (ib_register_device(&ibdev->ib_dev, NULL))
2932 goto err_diag_counters;
2933
225c7b1f
RD		 2934 if (mlx4_ib_mad_init(ibdev))
2935 goto err_reg;
2936
fc06573d
JM		 2937 if (mlx4_ib_init_sriov(ibdev))
2938 goto err_mad;
2939
dd77abf8
MD		 2940 if (!iboe->nb.notifier_call) {
2941 iboe->nb.notifier_call = mlx4_ib_netdev_event;
2942 err = register_netdevice_notifier(&iboe->nb);
2943 if (err) {
2944 iboe->nb.notifier_call = NULL;
2945 goto err_notif;
71a39bbb 2946 }
fa417f7b 2947 }
dd77abf8
MD		 2948 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2949 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
2950 if (err)
2951 goto err_notif;
2952 }
fa417f7b 2953
035b1032 2954 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
f4e91eb4 2955 if (device_create_file(&ibdev->ib_dev.dev,
035b1032 2956 mlx4_class_attributes[j]))
fa417f7b 2957 goto err_notif;
cd9281d8
JM		 2958 }
2959
3b4a8cd5 2960 ibdev->ib_active = true;
09d4d087
JP		 2961 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2962 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
2963 &ibdev->ib_dev);
3b4a8cd5 2964
54679e14
JM		 2965 if (mlx4_is_mfunc(ibdev->dev))
2966 init_pkeys(ibdev);
2967
3806d08c
JM		 2968 /* create paravirt contexts for any VFs which are active */
2969 if (mlx4_is_master(ibdev->dev)) {
2970 for (j = 0; j < MLX4_MFUNC_MAX; j++) {
2971 if (j == mlx4_master_func_num(ibdev->dev))
2972 continue;
2973 if (mlx4_is_slave_active(ibdev->dev, j))
2974 do_slave_init(ibdev, j, 1);
2975 }
2976 }
225c7b1f
RD		 2977 return ibdev;
2978
fa417f7b 2979err_notif:
d487ee77
MS		 2980 if (ibdev->iboe.nb.notifier_call) {
2981 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2982 pr_warn("failure unregistering notifier\n");
2983 ibdev->iboe.nb.notifier_call = NULL;
2984 }
fa417f7b
EC		 2985 flush_workqueue(wq);
2986
fc06573d
JM		 2987 mlx4_ib_close_sriov(ibdev);
2988
2989err_mad:
2990 mlx4_ib_mad_cleanup(ibdev);
2991
225c7b1f
RD		 2992err_reg:
2993 ib_unregister_device(&ibdev->ib_dev);
2994
3f85f2aa
MB		 2995err_diag_counters:
2996 mlx4_ib_diag_cleanup(ibdev);
2997
c1c98501
MB		 2998err_steer_free_bitmap:
2999 kfree(ibdev->ib_uc_qpns_bitmap);
3000
3001err_steer_qp_release:
852f6927
JM		 3002 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
3003 ibdev->steer_qpn_count);
cfcde11c 3004err_counter:
3ba8e31d
EBE		 3005 for (i = 0; i < ibdev->num_ports; ++i)
3006 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
3007
225c7b1f 3008err_map:
99e68909 3009 mlx4_ib_free_eqs(dev, ibdev);
225c7b1f
RD		 3010 iounmap(ibdev->uar_map);
3011
3012err_uar:
3013 mlx4_uar_free(dev, &ibdev->priv_uar);
3014
3015err_pd:
3016 mlx4_pd_free(dev, ibdev->priv_pdn);
3017
3018err_dealloc:
3019 ib_dealloc_device(&ibdev->ib_dev);
3020
3021 return NULL;
3022}
3023
c1c98501
MB		 3024int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
3025{
3026 int offset;
3027
3028 WARN_ON(!dev->ib_uc_qpns_bitmap);
3029
3030 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
3031 dev->steer_qpn_count,
3032 get_count_order(count));
3033 if (offset < 0)
3034 return offset;
3035
3036 *qpn = dev->steer_qpn_base + offset;
3037 return 0;
3038}
3039
3040void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
3041{
3042 if (!qpn ||
3043 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
3044 return;
3045
3046 BUG_ON(qpn < dev->steer_qpn_base);
3047
3048 bitmap_release_region(dev->ib_uc_qpns_bitmap,
3049 qpn - dev->steer_qpn_base,
3050 get_count_order(count));
3051}
3052
3053int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
3054 int is_attach)
3055{
3056 int err;
3057 size_t flow_size;
3058 struct ib_flow_attr *flow = NULL;
3059 struct ib_flow_spec_ib *ib_spec;
3060
3061 if (is_attach) {
3062 flow_size = sizeof(struct ib_flow_attr) +
3063 sizeof(struct ib_flow_spec_ib);
3064 flow = kzalloc(flow_size, GFP_KERNEL);
3065 if (!flow)
3066 return -ENOMEM;
3067 flow->port = mqp->port;
3068 flow->num_of_specs = 1;
3069 flow->size = flow_size;
3070 ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
3071 ib_spec->type = IB_FLOW_SPEC_IB;
3072 ib_spec->size = sizeof(struct ib_flow_spec_ib);
3073 /* Add an empty rule for IB L2 */
3074 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
3075
3076 err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
3077 IB_FLOW_DOMAIN_NIC,
3078 MLX4_FS_REGULAR,
3079 &mqp->reg_id);
3080 } else {
3081 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
3082 }
3083 kfree(flow);
3084 return err;
3085}
3086
225c7b1f
RD		 3087static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
3088{
3089 struct mlx4_ib_dev *ibdev = ibdev_ptr;
3090 int p;
09d4d087 3091 int i;
225c7b1f 3092
09d4d087
JP		 3093 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
3094 devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
4bf9715f
MS		 3095 ibdev->ib_active = false;
3096 flush_workqueue(wq);
3097
fc06573d 3098 mlx4_ib_close_sriov(ibdev);
a6a47771
YP		 3099 mlx4_ib_mad_cleanup(ibdev);
3100 ib_unregister_device(&ibdev->ib_dev);
3f85f2aa 3101 mlx4_ib_diag_cleanup(ibdev);
fa417f7b
EC		 3102 if (ibdev->iboe.nb.notifier_call) {
3103 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
987c8f8f 3104 pr_warn("failure unregistering notifier\n");
fa417f7b
EC		 3105 ibdev->iboe.nb.notifier_call = NULL;
3106 }
c1c98501 3107
852f6927
JM		 3108 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
3109 ibdev->steer_qpn_count);
3110 kfree(ibdev->ib_uc_qpns_bitmap);
c1c98501 3111
fa417f7b 3112 iounmap(ibdev->uar_map);
cfcde11c 3113 for (p = 0; p < ibdev->num_ports; ++p)
3ba8e31d
EBE		 3114 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
3115
fa417f7b 3116 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
225c7b1f
RD		 3117 mlx4_CLOSE_PORT(dev, p);
3118
e605b743
SP		 3119 mlx4_ib_free_eqs(dev, ibdev);
3120
225c7b1f
RD		 3121 mlx4_uar_free(dev, &ibdev->priv_uar);
3122 mlx4_pd_free(dev, ibdev->priv_pdn);
3123 ib_dealloc_device(&ibdev->ib_dev);
3124}
3125
fc06573d
JM		 3126static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
3127{
3128 struct mlx4_ib_demux_work **dm = NULL;
3129 struct mlx4_dev *dev = ibdev->dev;
3130 int i;
3131 unsigned long flags;
449fc488
MB		 3132 struct mlx4_active_ports actv_ports;
3133 unsigned int ports;
3134 unsigned int first_port;
fc06573d
JM		 3135
3136 if (!mlx4_is_master(dev))
3137 return;
3138
449fc488
MB		 3139 actv_ports = mlx4_get_active_ports(dev, slave);
3140 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
3141 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
3142
3143 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
15d4626e 3144 if (!dm)
a39a98ff 3145 return;
fc06573d 3146
449fc488 3147 for (i = 0; i < ports; i++) {
fc06573d
JM		 3148 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
3149 if (!dm[i]) {
a39a98ff
MS		 3150 while (--i >= 0)
3151 kfree(dm[i]);
fc06573d
JM		 3152 goto out;
3153 }
fc06573d 3154 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
449fc488 3155 dm[i]->port = first_port + i + 1;
fc06573d
JM		 3156 dm[i]->slave = slave;
3157 dm[i]->do_init = do_init;
3158 dm[i]->dev = ibdev;
d9a047ae
DL		 3159 }
3160 /* initialize or tear down tunnel QPs for the slave */
3161 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
3162 if (!ibdev->sriov.is_going_down) {
3163 for (i = 0; i < ports; i++)
fc06573d
JM		 3164 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
3165 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
d9a047ae
DL		 3166 } else {
3167 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3168 for (i = 0; i < ports; i++)
3169 kfree(dm[i]);
fc06573d
JM		 3170 }
3171out:
c89d1271 3172 kfree(dm);
fc06573d
JM		 3173 return;
3174}
3175
35f05dab
YH		 3176static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
3177{
3178 struct mlx4_ib_qp *mqp;
3179 unsigned long flags_qp;
3180 unsigned long flags_cq;
3181 struct mlx4_ib_cq *send_mcq, *recv_mcq;
3182 struct list_head cq_notify_list;
3183 struct mlx4_cq *mcq;
3184 unsigned long flags;
3185
3186 pr_warn("mlx4_ib_handle_catas_error was started\n");
3187 INIT_LIST_HEAD(&cq_notify_list);
3188
3189 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3190 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3191
3192 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3193 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3194 if (mqp->sq.tail != mqp->sq.head) {
3195 send_mcq = to_mcq(mqp->ibqp.send_cq);
3196 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3197 if (send_mcq->mcq.comp &&
3198 mqp->ibqp.send_cq->comp_handler) {
3199 if (!send_mcq->mcq.reset_notify_added) {
3200 send_mcq->mcq.reset_notify_added = 1;
3201 list_add_tail(&send_mcq->mcq.reset_notify,
3202 &cq_notify_list);
3203 }
3204 }
3205 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3206 }
3207 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3208 /* Now, handle the QP's receive queue */
3209 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3210 /* no handling is needed for SRQ */
3211 if (!mqp->ibqp.srq) {
3212 if (mqp->rq.tail != mqp->rq.head) {
3213 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3214 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3215 if (recv_mcq->mcq.comp &&
3216 mqp->ibqp.recv_cq->comp_handler) {
3217 if (!recv_mcq->mcq.reset_notify_added) {
3218 recv_mcq->mcq.reset_notify_added = 1;
3219 list_add_tail(&recv_mcq->mcq.reset_notify,
3220 &cq_notify_list);
3221 }
3222 }
3223 spin_unlock_irqrestore(&recv_mcq->lock,
3224 flags_cq);
3225 }
3226 }
3227 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3228 }
3229
3230 list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
3231 mcq->comp(mcq);
3232 }
3233 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3234 pr_warn("mlx4_ib_handle_catas_error ended\n");
3235}
3236
a5750090
MS		 3237static void handle_bonded_port_state_event(struct work_struct *work)
3238{
3239 struct ib_event_work *ew =
3240 container_of(work, struct ib_event_work, work);
3241 struct mlx4_ib_dev *ibdev = ew->ib_dev;
3242 enum ib_port_state bonded_port_state = IB_PORT_NOP;
3243 int i;
3244 struct ib_event ibev;
3245
3246 kfree(ew);
3247 spin_lock_bh(&ibdev->iboe.lock);
3248 for (i = 0; i < MLX4_MAX_PORTS; ++i) {
3249 struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
217e8b16 3250 enum ib_port_state curr_port_state;
a5750090 3251
217e8b16
MS		 3252 if (!curr_netdev)
3253 continue;
3254
3255 curr_port_state =
a5750090
MS		 3256 (netif_running(curr_netdev) &&
3257 netif_carrier_ok(curr_netdev)) ?
3258 IB_PORT_ACTIVE : IB_PORT_DOWN;
3259
3260 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
3261 curr_port_state : IB_PORT_ACTIVE;
3262 }
3263 spin_unlock_bh(&ibdev->iboe.lock);
3264
3265 ibev.device = &ibdev->ib_dev;
3266 ibev.element.port_num = 1;
3267 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
3268 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3269
3270 ib_dispatch_event(&ibev);
3271}
3272
fd10ed8e
JM		 3273void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port)
3274{
3275 u64 sl2vl;
3276 int err;
3277
3278 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl);
3279 if (err) {
3280 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n",
3281 port, err);
3282 sl2vl = 0;
3283 }
3284 atomic64_set(&mdev->sl2vl[port - 1], sl2vl);
3285}
3286
3287static void ib_sl2vl_update_work(struct work_struct *work)
3288{
3289 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
3290 struct mlx4_ib_dev *mdev = ew->ib_dev;
3291 int port = ew->port;
3292
3293 mlx4_ib_sl2vl_update(mdev, port);
3294
3295 kfree(ew);
3296}
3297
3298void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
3299 int port)
3300{
3301 struct ib_event_work *ew;
3302
3303 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3304 if (ew) {
3305 INIT_WORK(&ew->work, ib_sl2vl_update_work);
3306 ew->port = port;
3307 ew->ib_dev = ibdev;
3308 queue_work(wq, &ew->work);
fd10ed8e
JM		 3309 }
3310}
3311
225c7b1f 3312static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
00f5ce99 3313 enum mlx4_dev_event event, unsigned long param)
225c7b1f
RD		 3314{
3315 struct ib_event ibev;
7ff93f8b 3316 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
00f5ce99
JM		 3317 struct mlx4_eqe *eqe = NULL;
3318 struct ib_event_work *ew;
fc06573d 3319 int p = 0;
00f5ce99 3320
a5750090
MS		 3321 if (mlx4_is_bonded(dev) &&
3322 ((event == MLX4_DEV_EVENT_PORT_UP) ||
3323 (event == MLX4_DEV_EVENT_PORT_DOWN))) {
3324 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3325 if (!ew)
3326 return;
3327 INIT_WORK(&ew->work, handle_bonded_port_state_event);
3328 ew->ib_dev = ibdev;
3329 queue_work(wq, &ew->work);
3330 return;
3331 }
3332
00f5ce99
JM		 3333 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
3334 eqe = (struct mlx4_eqe *)param;
3335 else
fc06573d 3336 p = (int) param;
225c7b1f
RD		 3337
3338 switch (event) {
37608eea 3339 case MLX4_DEV_EVENT_PORT_UP:
fc06573d
JM		 3340 if (p > ibdev->num_ports)
3341 return;
fd10ed8e 3342 if (!mlx4_is_slave(dev) &&
a0c64a17
JM		 3343 rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
3344 IB_LINK_LAYER_INFINIBAND) {
fd10ed8e
JM		 3345 if (mlx4_is_master(dev))
3346 mlx4_ib_invalidate_all_guid_record(ibdev, p);
3347 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST &&
3348 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT))
3349 mlx4_sched_ib_sl2vl_update_work(ibdev, p);
a0c64a17 3350 }
37608eea 3351 ibev.event = IB_EVENT_PORT_ACTIVE;
225c7b1f
RD		 3352 break;
3353
37608eea 3354 case MLX4_DEV_EVENT_PORT_DOWN:
fc06573d
JM		 3355 if (p > ibdev->num_ports)
3356 return;
37608eea
RD		 3357 ibev.event = IB_EVENT_PORT_ERR;
3358 break;
3359
3360 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
3b4a8cd5 3361 ibdev->ib_active = false;
225c7b1f 3362 ibev.event = IB_EVENT_DEVICE_FATAL;
35f05dab 3363 mlx4_ib_handle_catas_error(ibdev);
225c7b1f
RD		 3364 break;
3365
00f5ce99
JM		 3366 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
3367 ew = kmalloc(sizeof *ew, GFP_ATOMIC);
15d4626e 3368 if (!ew)
00f5ce99 3369 break;
00f5ce99
JM		 3370
3371 INIT_WORK(&ew->work, handle_port_mgmt_change_event);
3372 memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
3373 ew->ib_dev = ibdev;
992e8e6e
JM		 3374 /* need to queue only for port owner, which uses GEN_EQE */
3375 if (mlx4_is_master(dev))
3376 queue_work(wq, &ew->work);
3377 else
3378 handle_port_mgmt_change_event(&ew->work);
00f5ce99
JM		 3379 return;
3380
fc06573d
JM		 3381 case MLX4_DEV_EVENT_SLAVE_INIT:
3382 /* here, p is the slave id */
3383 do_slave_init(ibdev, p, 1);
ee59fa0d
YH		 3384 if (mlx4_is_master(dev)) {
3385 int i;
3386
3387 for (i = 1; i <= ibdev->num_ports; i++) {
3388 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3389 == IB_LINK_LAYER_INFINIBAND)
3390 mlx4_ib_slave_alias_guid_event(ibdev,
3391 p, i,
3392 1);
3393 }
3394 }
fc06573d
JM		 3395 return;
3396
3397 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
ee59fa0d
YH		 3398 if (mlx4_is_master(dev)) {
3399 int i;
3400
3401 for (i = 1; i <= ibdev->num_ports; i++) {
3402 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3403 == IB_LINK_LAYER_INFINIBAND)
3404 mlx4_ib_slave_alias_guid_event(ibdev,
3405 p, i,
3406 0);
3407 }
3408 }
fc06573d
JM		 3409 /* here, p is the slave id */
3410 do_slave_init(ibdev, p, 0);
3411 return;
3412
225c7b1f
RD		 3413 default:
3414 return;
3415 }
3416
3417 ibev.device = ibdev_ptr;
a5750090 3418 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
225c7b1f
RD		 3419
3420 ib_dispatch_event(&ibev);
3421}
3422
3423static struct mlx4_interface mlx4_ib_interface = {
fa417f7b
EC		 3424 .add = mlx4_ib_add,
3425 .remove = mlx4_ib_remove,
3426 .event = mlx4_ib_event,
a5750090
MS		 3427 .protocol = MLX4_PROT_IB_IPV6,
3428 .flags = MLX4_INTFF_BONDING
225c7b1f
RD		 3429};
3430
3431static int __init mlx4_ib_init(void)
3432{
fa417f7b
EC		 3433 int err;
3434
41cd3944 3435 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM);
fa417f7b
EC		 3436 if (!wq)
3437 return -ENOMEM;
3438
b9c5d6a6
OD		 3439 err = mlx4_ib_mcg_init();
3440 if (err)
3441 goto clean_wq;
3442
fa417f7b 3443 err = mlx4_register_interface(&mlx4_ib_interface);
b9c5d6a6
OD		 3444 if (err)
3445 goto clean_mcg;
fa417f7b
EC		 3446
3447 return 0;
b9c5d6a6
OD		 3448
3449clean_mcg:
3450 mlx4_ib_mcg_destroy();
3451
3452clean_wq:
3453 destroy_workqueue(wq);
3454 return err;
225c7b1f
RD		 3455}
3456
3457static void __exit mlx4_ib_cleanup(void)
3458{
3459 mlx4_unregister_interface(&mlx4_ib_interface);
b9c5d6a6 3460 mlx4_ib_mcg_destroy();
fa417f7b 3461 destroy_workqueue(wq);
225c7b1f
RD		 3462}
3463
3464module_init(mlx4_ib_init);
3465module_exit(mlx4_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)