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d3749841 FL |
1 | /******************************************************************************* |
2 | * | |
3 | * Copyright (c) 2015-2016 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenFabrics.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | * | |
33 | *******************************************************************************/ | |
34 | ||
35 | #include <linux/module.h> | |
36 | #include <linux/moduleparam.h> | |
37 | #include <linux/random.h> | |
38 | #include <linux/highmem.h> | |
39 | #include <linux/time.h> | |
f26c7c83 | 40 | #include <linux/hugetlb.h> |
baa00fcd | 41 | #include <linux/irq.h> |
d3749841 FL |
42 | #include <asm/byteorder.h> |
43 | #include <net/ip.h> | |
44 | #include <rdma/ib_verbs.h> | |
45 | #include <rdma/iw_cm.h> | |
46 | #include <rdma/ib_user_verbs.h> | |
47 | #include <rdma/ib_umem.h> | |
48 | #include "i40iw.h" | |
49 | ||
50 | /** | |
51 | * i40iw_query_device - get device attributes | |
52 | * @ibdev: device pointer from stack | |
53 | * @props: returning device attributes | |
54 | * @udata: user data | |
55 | */ | |
56 | static int i40iw_query_device(struct ib_device *ibdev, | |
57 | struct ib_device_attr *props, | |
58 | struct ib_udata *udata) | |
59 | { | |
60 | struct i40iw_device *iwdev = to_iwdev(ibdev); | |
61 | ||
62 | if (udata->inlen || udata->outlen) | |
63 | return -EINVAL; | |
64 | memset(props, 0, sizeof(*props)); | |
65 | ether_addr_copy((u8 *)&props->sys_image_guid, iwdev->netdev->dev_addr); | |
66 | props->fw_ver = I40IW_FW_VERSION; | |
67 | props->device_cap_flags = iwdev->device_cap_flags; | |
4920dc31 IM |
68 | props->vendor_id = iwdev->ldev->pcidev->vendor; |
69 | props->vendor_part_id = iwdev->ldev->pcidev->device; | |
d3749841 FL |
70 | props->hw_ver = (u32)iwdev->sc_dev.hw_rev; |
71 | props->max_mr_size = I40IW_MAX_OUTBOUND_MESSAGE_SIZE; | |
85a87c90 | 72 | props->max_qp = iwdev->max_qp - iwdev->used_qps; |
11969238 | 73 | props->max_qp_wr = I40IW_MAX_QP_WRS; |
33023fb8 SW |
74 | props->max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT; |
75 | props->max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT; | |
85a87c90 | 76 | props->max_cq = iwdev->max_cq - iwdev->used_cqs; |
d3749841 | 77 | props->max_cqe = iwdev->max_cqe; |
85a87c90 HO |
78 | props->max_mr = iwdev->max_mr - iwdev->used_mrs; |
79 | props->max_pd = iwdev->max_pd - iwdev->used_pds; | |
6c2f7619 | 80 | props->max_sge_rd = I40IW_MAX_SGE_RD; |
d3749841 FL |
81 | props->max_qp_rd_atom = I40IW_MAX_IRD_SIZE; |
82 | props->max_qp_init_rd_atom = props->max_qp_rd_atom; | |
83 | props->atomic_cap = IB_ATOMIC_NONE; | |
84 | props->max_map_per_fmr = 1; | |
0477e181 | 85 | props->max_fast_reg_page_list_len = I40IW_MAX_PAGES_PER_FMR; |
d3749841 FL |
86 | return 0; |
87 | } | |
88 | ||
89 | /** | |
90 | * i40iw_query_port - get port attrubutes | |
91 | * @ibdev: device pointer from stack | |
92 | * @port: port number for query | |
93 | * @props: returning device attributes | |
94 | */ | |
95 | static int i40iw_query_port(struct ib_device *ibdev, | |
96 | u8 port, | |
97 | struct ib_port_attr *props) | |
98 | { | |
99 | struct i40iw_device *iwdev = to_iwdev(ibdev); | |
100 | struct net_device *netdev = iwdev->netdev; | |
101 | ||
c4550c63 | 102 | /* props being zeroed by the caller, avoid zeroing it here */ |
d3749841 | 103 | props->max_mtu = IB_MTU_4096; |
d3f4aadd | 104 | props->active_mtu = ib_mtu_int_to_enum(netdev->mtu); |
d3749841 FL |
105 | |
106 | props->lid = 1; | |
107 | if (netif_carrier_ok(iwdev->netdev)) | |
108 | props->state = IB_PORT_ACTIVE; | |
109 | else | |
110 | props->state = IB_PORT_DOWN; | |
111 | props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | | |
112 | IB_PORT_VENDOR_CLASS_SUP | IB_PORT_BOOT_MGMT_SUP; | |
113 | props->gid_tbl_len = 1; | |
114 | props->pkey_tbl_len = 1; | |
115 | props->active_width = IB_WIDTH_4X; | |
116 | props->active_speed = 1; | |
bd57aeae | 117 | props->max_msg_sz = I40IW_MAX_OUTBOUND_MESSAGE_SIZE; |
d3749841 FL |
118 | return 0; |
119 | } | |
120 | ||
121 | /** | |
122 | * i40iw_alloc_ucontext - Allocate the user context data structure | |
123 | * @ibdev: device pointer from stack | |
124 | * @udata: user data | |
125 | * | |
126 | * This keeps track of all objects associated with a particular | |
127 | * user-mode client. | |
128 | */ | |
129 | static struct ib_ucontext *i40iw_alloc_ucontext(struct ib_device *ibdev, | |
130 | struct ib_udata *udata) | |
131 | { | |
132 | struct i40iw_device *iwdev = to_iwdev(ibdev); | |
133 | struct i40iw_alloc_ucontext_req req; | |
134 | struct i40iw_alloc_ucontext_resp uresp; | |
135 | struct i40iw_ucontext *ucontext; | |
136 | ||
137 | if (ib_copy_from_udata(&req, udata, sizeof(req))) | |
138 | return ERR_PTR(-EINVAL); | |
139 | ||
61f51b7b CTT |
140 | if (req.userspace_ver < 4 || req.userspace_ver > I40IW_ABI_VER) { |
141 | i40iw_pr_err("Unsupported provider library version %u.\n", req.userspace_ver); | |
d3749841 FL |
142 | return ERR_PTR(-EINVAL); |
143 | } | |
144 | ||
145 | memset(&uresp, 0, sizeof(uresp)); | |
146 | uresp.max_qps = iwdev->max_qp; | |
147 | uresp.max_pds = iwdev->max_pd; | |
148 | uresp.wq_size = iwdev->max_qp_wr * 2; | |
61f51b7b | 149 | uresp.kernel_ver = req.userspace_ver; |
d3749841 FL |
150 | |
151 | ucontext = kzalloc(sizeof(*ucontext), GFP_KERNEL); | |
152 | if (!ucontext) | |
153 | return ERR_PTR(-ENOMEM); | |
154 | ||
155 | ucontext->iwdev = iwdev; | |
61f51b7b | 156 | ucontext->abi_ver = req.userspace_ver; |
d3749841 FL |
157 | |
158 | if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) { | |
159 | kfree(ucontext); | |
160 | return ERR_PTR(-EFAULT); | |
161 | } | |
162 | ||
163 | INIT_LIST_HEAD(&ucontext->cq_reg_mem_list); | |
164 | spin_lock_init(&ucontext->cq_reg_mem_list_lock); | |
165 | INIT_LIST_HEAD(&ucontext->qp_reg_mem_list); | |
166 | spin_lock_init(&ucontext->qp_reg_mem_list_lock); | |
167 | ||
168 | return &ucontext->ibucontext; | |
169 | } | |
170 | ||
171 | /** | |
172 | * i40iw_dealloc_ucontext - deallocate the user context data structure | |
173 | * @context: user context created during alloc | |
174 | */ | |
175 | static int i40iw_dealloc_ucontext(struct ib_ucontext *context) | |
176 | { | |
177 | struct i40iw_ucontext *ucontext = to_ucontext(context); | |
178 | unsigned long flags; | |
179 | ||
180 | spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags); | |
181 | if (!list_empty(&ucontext->cq_reg_mem_list)) { | |
182 | spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags); | |
183 | return -EBUSY; | |
184 | } | |
185 | spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags); | |
186 | spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags); | |
187 | if (!list_empty(&ucontext->qp_reg_mem_list)) { | |
188 | spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags); | |
189 | return -EBUSY; | |
190 | } | |
191 | spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags); | |
192 | ||
193 | kfree(ucontext); | |
194 | return 0; | |
195 | } | |
196 | ||
197 | /** | |
198 | * i40iw_mmap - user memory map | |
199 | * @context: context created during alloc | |
200 | * @vma: kernel info for user memory map | |
201 | */ | |
202 | static int i40iw_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) | |
203 | { | |
204 | struct i40iw_ucontext *ucontext; | |
205 | u64 db_addr_offset; | |
206 | u64 push_offset; | |
207 | ||
208 | ucontext = to_ucontext(context); | |
209 | if (ucontext->iwdev->sc_dev.is_pf) { | |
210 | db_addr_offset = I40IW_DB_ADDR_OFFSET; | |
211 | push_offset = I40IW_PUSH_OFFSET; | |
212 | if (vma->vm_pgoff) | |
213 | vma->vm_pgoff += I40IW_PF_FIRST_PUSH_PAGE_INDEX - 1; | |
214 | } else { | |
215 | db_addr_offset = I40IW_VF_DB_ADDR_OFFSET; | |
216 | push_offset = I40IW_VF_PUSH_OFFSET; | |
217 | if (vma->vm_pgoff) | |
218 | vma->vm_pgoff += I40IW_VF_FIRST_PUSH_PAGE_INDEX - 1; | |
219 | } | |
220 | ||
221 | vma->vm_pgoff += db_addr_offset >> PAGE_SHIFT; | |
222 | ||
223 | if (vma->vm_pgoff == (db_addr_offset >> PAGE_SHIFT)) { | |
224 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
225 | vma->vm_private_data = ucontext; | |
226 | } else { | |
227 | if ((vma->vm_pgoff - (push_offset >> PAGE_SHIFT)) % 2) | |
228 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
229 | else | |
230 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
231 | } | |
232 | ||
233 | if (io_remap_pfn_range(vma, vma->vm_start, | |
234 | vma->vm_pgoff + (pci_resource_start(ucontext->iwdev->ldev->pcidev, 0) >> PAGE_SHIFT), | |
235 | PAGE_SIZE, vma->vm_page_prot)) | |
236 | return -EAGAIN; | |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
241 | /** | |
242 | * i40iw_alloc_push_page - allocate a push page for qp | |
243 | * @iwdev: iwarp device | |
244 | * @qp: hardware control qp | |
245 | */ | |
246 | static void i40iw_alloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp) | |
247 | { | |
248 | struct i40iw_cqp_request *cqp_request; | |
249 | struct cqp_commands_info *cqp_info; | |
d3749841 FL |
250 | enum i40iw_status_code status; |
251 | ||
252 | if (qp->push_idx != I40IW_INVALID_PUSH_PAGE_INDEX) | |
253 | return; | |
254 | ||
255 | cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true); | |
256 | if (!cqp_request) | |
257 | return; | |
258 | ||
259 | atomic_inc(&cqp_request->refcount); | |
260 | ||
261 | cqp_info = &cqp_request->info; | |
262 | cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE; | |
263 | cqp_info->post_sq = 1; | |
264 | ||
0fc2dc58 | 265 | cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle; |
d3749841 FL |
266 | cqp_info->in.u.manage_push_page.info.free_page = 0; |
267 | cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp; | |
268 | cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request; | |
269 | ||
270 | status = i40iw_handle_cqp_op(iwdev, cqp_request); | |
271 | if (!status) | |
272 | qp->push_idx = cqp_request->compl_info.op_ret_val; | |
273 | else | |
274 | i40iw_pr_err("CQP-OP Push page fail"); | |
275 | i40iw_put_cqp_request(&iwdev->cqp, cqp_request); | |
276 | } | |
277 | ||
278 | /** | |
279 | * i40iw_dealloc_push_page - free a push page for qp | |
280 | * @iwdev: iwarp device | |
281 | * @qp: hardware control qp | |
282 | */ | |
283 | static void i40iw_dealloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp) | |
284 | { | |
285 | struct i40iw_cqp_request *cqp_request; | |
286 | struct cqp_commands_info *cqp_info; | |
d3749841 FL |
287 | enum i40iw_status_code status; |
288 | ||
289 | if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX) | |
290 | return; | |
291 | ||
292 | cqp_request = i40iw_get_cqp_request(&iwdev->cqp, false); | |
293 | if (!cqp_request) | |
294 | return; | |
295 | ||
296 | cqp_info = &cqp_request->info; | |
297 | cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE; | |
298 | cqp_info->post_sq = 1; | |
299 | ||
300 | cqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx; | |
0fc2dc58 | 301 | cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle; |
d3749841 FL |
302 | cqp_info->in.u.manage_push_page.info.free_page = 1; |
303 | cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp; | |
304 | cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request; | |
305 | ||
306 | status = i40iw_handle_cqp_op(iwdev, cqp_request); | |
307 | if (!status) | |
308 | qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX; | |
309 | else | |
310 | i40iw_pr_err("CQP-OP Push page fail"); | |
311 | } | |
312 | ||
313 | /** | |
314 | * i40iw_alloc_pd - allocate protection domain | |
315 | * @ibdev: device pointer from stack | |
316 | * @context: user context created during alloc | |
317 | * @udata: user data | |
318 | */ | |
319 | static struct ib_pd *i40iw_alloc_pd(struct ib_device *ibdev, | |
320 | struct ib_ucontext *context, | |
321 | struct ib_udata *udata) | |
322 | { | |
323 | struct i40iw_pd *iwpd; | |
324 | struct i40iw_device *iwdev = to_iwdev(ibdev); | |
325 | struct i40iw_sc_dev *dev = &iwdev->sc_dev; | |
326 | struct i40iw_alloc_pd_resp uresp; | |
327 | struct i40iw_sc_pd *sc_pd; | |
61f51b7b | 328 | struct i40iw_ucontext *ucontext; |
d3749841 FL |
329 | u32 pd_id = 0; |
330 | int err; | |
331 | ||
d5965934 MI |
332 | if (iwdev->closing) |
333 | return ERR_PTR(-ENODEV); | |
334 | ||
d3749841 FL |
335 | err = i40iw_alloc_resource(iwdev, iwdev->allocated_pds, |
336 | iwdev->max_pd, &pd_id, &iwdev->next_pd); | |
337 | if (err) { | |
338 | i40iw_pr_err("alloc resource failed\n"); | |
339 | return ERR_PTR(err); | |
340 | } | |
341 | ||
342 | iwpd = kzalloc(sizeof(*iwpd), GFP_KERNEL); | |
343 | if (!iwpd) { | |
344 | err = -ENOMEM; | |
345 | goto free_res; | |
346 | } | |
347 | ||
348 | sc_pd = &iwpd->sc_pd; | |
d3749841 FL |
349 | |
350 | if (context) { | |
61f51b7b CTT |
351 | ucontext = to_ucontext(context); |
352 | dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id, ucontext->abi_ver); | |
d3749841 FL |
353 | memset(&uresp, 0, sizeof(uresp)); |
354 | uresp.pd_id = pd_id; | |
355 | if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) { | |
356 | err = -EFAULT; | |
357 | goto error; | |
358 | } | |
61f51b7b CTT |
359 | } else { |
360 | dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id, -1); | |
d3749841 FL |
361 | } |
362 | ||
363 | i40iw_add_pdusecount(iwpd); | |
364 | return &iwpd->ibpd; | |
365 | error: | |
366 | kfree(iwpd); | |
367 | free_res: | |
368 | i40iw_free_resource(iwdev, iwdev->allocated_pds, pd_id); | |
369 | return ERR_PTR(err); | |
370 | } | |
371 | ||
372 | /** | |
373 | * i40iw_dealloc_pd - deallocate pd | |
374 | * @ibpd: ptr of pd to be deallocated | |
375 | */ | |
376 | static int i40iw_dealloc_pd(struct ib_pd *ibpd) | |
377 | { | |
378 | struct i40iw_pd *iwpd = to_iwpd(ibpd); | |
379 | struct i40iw_device *iwdev = to_iwdev(ibpd->device); | |
380 | ||
381 | i40iw_rem_pdusecount(iwpd, iwdev); | |
382 | return 0; | |
383 | } | |
384 | ||
d3749841 FL |
385 | /** |
386 | * i40iw_get_pbl - Retrieve pbl from a list given a virtual | |
387 | * address | |
388 | * @va: user virtual address | |
389 | * @pbl_list: pbl list to search in (QP's or CQ's) | |
390 | */ | |
391 | static struct i40iw_pbl *i40iw_get_pbl(unsigned long va, | |
392 | struct list_head *pbl_list) | |
393 | { | |
394 | struct i40iw_pbl *iwpbl; | |
395 | ||
396 | list_for_each_entry(iwpbl, pbl_list, list) { | |
397 | if (iwpbl->user_base == va) { | |
a75895b1 | 398 | iwpbl->on_list = false; |
d3749841 FL |
399 | list_del(&iwpbl->list); |
400 | return iwpbl; | |
401 | } | |
402 | } | |
403 | return NULL; | |
404 | } | |
405 | ||
406 | /** | |
407 | * i40iw_free_qp_resources - free up memory resources for qp | |
408 | * @iwdev: iwarp device | |
409 | * @iwqp: qp ptr (user or kernel) | |
410 | * @qp_num: qp number assigned | |
411 | */ | |
412 | void i40iw_free_qp_resources(struct i40iw_device *iwdev, | |
413 | struct i40iw_qp *iwqp, | |
414 | u32 qp_num) | |
415 | { | |
af56e53c TN |
416 | struct i40iw_pbl *iwpbl = &iwqp->iwpbl; |
417 | ||
f20d4295 | 418 | i40iw_ieq_cleanup_qp(iwdev->vsi.ieq, &iwqp->sc_qp); |
d3749841 FL |
419 | i40iw_dealloc_push_page(iwdev, &iwqp->sc_qp); |
420 | if (qp_num) | |
421 | i40iw_free_resource(iwdev, iwdev->allocated_qps, qp_num); | |
af56e53c TN |
422 | if (iwpbl->pbl_allocated) |
423 | i40iw_free_pble(iwdev->pble_rsrc, &iwpbl->pble_alloc); | |
d3749841 FL |
424 | i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->q2_ctx_mem); |
425 | i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->kqp.dma_mem); | |
426 | kfree(iwqp->kqp.wrid_mem); | |
427 | iwqp->kqp.wrid_mem = NULL; | |
428 | kfree(iwqp->allocated_buffer); | |
d3749841 FL |
429 | } |
430 | ||
431 | /** | |
432 | * i40iw_clean_cqes - clean cq entries for qp | |
433 | * @iwqp: qp ptr (user or kernel) | |
434 | * @iwcq: cq ptr | |
435 | */ | |
436 | static void i40iw_clean_cqes(struct i40iw_qp *iwqp, struct i40iw_cq *iwcq) | |
437 | { | |
438 | struct i40iw_cq_uk *ukcq = &iwcq->sc_cq.cq_uk; | |
439 | ||
440 | ukcq->ops.iw_cq_clean(&iwqp->sc_qp.qp_uk, ukcq); | |
441 | } | |
442 | ||
443 | /** | |
444 | * i40iw_destroy_qp - destroy qp | |
445 | * @ibqp: qp's ib pointer also to get to device's qp address | |
446 | */ | |
447 | static int i40iw_destroy_qp(struct ib_qp *ibqp) | |
448 | { | |
449 | struct i40iw_qp *iwqp = to_iwqp(ibqp); | |
450 | ||
451 | iwqp->destroyed = 1; | |
452 | ||
453 | if (iwqp->ibqp_state >= IB_QPS_INIT && iwqp->ibqp_state < IB_QPS_RTS) | |
454 | i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 0, 0, 0); | |
455 | ||
456 | if (!iwqp->user_mode) { | |
457 | if (iwqp->iwscq) { | |
458 | i40iw_clean_cqes(iwqp, iwqp->iwscq); | |
459 | if (iwqp->iwrcq != iwqp->iwscq) | |
460 | i40iw_clean_cqes(iwqp, iwqp->iwrcq); | |
461 | } | |
462 | } | |
463 | ||
464 | i40iw_rem_ref(&iwqp->ibqp); | |
465 | return 0; | |
466 | } | |
467 | ||
468 | /** | |
469 | * i40iw_setup_virt_qp - setup for allocation of virtual qp | |
470 | * @dev: iwarp device | |
471 | * @qp: qp ptr | |
472 | * @init_info: initialize info to return | |
473 | */ | |
474 | static int i40iw_setup_virt_qp(struct i40iw_device *iwdev, | |
475 | struct i40iw_qp *iwqp, | |
476 | struct i40iw_qp_init_info *init_info) | |
477 | { | |
af56e53c | 478 | struct i40iw_pbl *iwpbl = &iwqp->iwpbl; |
d3749841 FL |
479 | struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr; |
480 | ||
481 | iwqp->page = qpmr->sq_page; | |
482 | init_info->shadow_area_pa = cpu_to_le64(qpmr->shadow); | |
483 | if (iwpbl->pbl_allocated) { | |
484 | init_info->virtual_map = true; | |
485 | init_info->sq_pa = qpmr->sq_pbl.idx; | |
486 | init_info->rq_pa = qpmr->rq_pbl.idx; | |
487 | } else { | |
488 | init_info->sq_pa = qpmr->sq_pbl.addr; | |
489 | init_info->rq_pa = qpmr->rq_pbl.addr; | |
490 | } | |
491 | return 0; | |
492 | } | |
493 | ||
494 | /** | |
495 | * i40iw_setup_kmode_qp - setup initialization for kernel mode qp | |
496 | * @iwdev: iwarp device | |
497 | * @iwqp: qp ptr (user or kernel) | |
498 | * @info: initialize info to return | |
499 | */ | |
500 | static int i40iw_setup_kmode_qp(struct i40iw_device *iwdev, | |
501 | struct i40iw_qp *iwqp, | |
502 | struct i40iw_qp_init_info *info) | |
503 | { | |
504 | struct i40iw_dma_mem *mem = &iwqp->kqp.dma_mem; | |
505 | u32 sqdepth, rqdepth; | |
61f51b7b | 506 | u8 sqshift; |
d3749841 FL |
507 | u32 size; |
508 | enum i40iw_status_code status; | |
509 | struct i40iw_qp_uk_init_info *ukinfo = &info->qp_uk_init_info; | |
510 | ||
11969238 SS |
511 | i40iw_get_wqe_shift(ukinfo->max_sq_frag_cnt, ukinfo->max_inline_data, &sqshift); |
512 | status = i40iw_get_sqdepth(ukinfo->sq_size, sqshift, &sqdepth); | |
d3749841 | 513 | if (status) |
fe5d6e62 | 514 | return -ENOMEM; |
d3749841 | 515 | |
11969238 SS |
516 | status = i40iw_get_rqdepth(ukinfo->rq_size, I40IW_MAX_RQ_WQE_SHIFT, &rqdepth); |
517 | if (status) | |
518 | return -ENOMEM; | |
d3749841 FL |
519 | |
520 | size = sqdepth * sizeof(struct i40iw_sq_uk_wr_trk_info) + (rqdepth << 3); | |
521 | iwqp->kqp.wrid_mem = kzalloc(size, GFP_KERNEL); | |
522 | ||
523 | ukinfo->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)iwqp->kqp.wrid_mem; | |
524 | if (!ukinfo->sq_wrtrk_array) | |
525 | return -ENOMEM; | |
526 | ||
527 | ukinfo->rq_wrid_array = (u64 *)&ukinfo->sq_wrtrk_array[sqdepth]; | |
528 | ||
529 | size = (sqdepth + rqdepth) * I40IW_QP_WQE_MIN_SIZE; | |
530 | size += (I40IW_SHADOW_AREA_SIZE << 3); | |
531 | ||
532 | status = i40iw_allocate_dma_mem(iwdev->sc_dev.hw, mem, size, 256); | |
533 | if (status) { | |
534 | kfree(ukinfo->sq_wrtrk_array); | |
535 | ukinfo->sq_wrtrk_array = NULL; | |
536 | return -ENOMEM; | |
537 | } | |
538 | ||
539 | ukinfo->sq = mem->va; | |
540 | info->sq_pa = mem->pa; | |
541 | ||
542 | ukinfo->rq = &ukinfo->sq[sqdepth]; | |
543 | info->rq_pa = info->sq_pa + (sqdepth * I40IW_QP_WQE_MIN_SIZE); | |
544 | ||
545 | ukinfo->shadow_area = ukinfo->rq[rqdepth].elem; | |
546 | info->shadow_area_pa = info->rq_pa + (rqdepth * I40IW_QP_WQE_MIN_SIZE); | |
547 | ||
11969238 SS |
548 | ukinfo->sq_size = sqdepth >> sqshift; |
549 | ukinfo->rq_size = rqdepth >> I40IW_MAX_RQ_WQE_SHIFT; | |
d3749841 FL |
550 | ukinfo->qp_id = iwqp->ibqp.qp_num; |
551 | return 0; | |
552 | } | |
553 | ||
554 | /** | |
555 | * i40iw_create_qp - create qp | |
556 | * @ibpd: ptr of pd | |
557 | * @init_attr: attributes for qp | |
558 | * @udata: user data for create qp | |
559 | */ | |
560 | static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd, | |
561 | struct ib_qp_init_attr *init_attr, | |
562 | struct ib_udata *udata) | |
563 | { | |
564 | struct i40iw_pd *iwpd = to_iwpd(ibpd); | |
565 | struct i40iw_device *iwdev = to_iwdev(ibpd->device); | |
566 | struct i40iw_cqp *iwcqp = &iwdev->cqp; | |
567 | struct i40iw_qp *iwqp; | |
568 | struct i40iw_ucontext *ucontext; | |
569 | struct i40iw_create_qp_req req; | |
570 | struct i40iw_create_qp_resp uresp; | |
571 | u32 qp_num = 0; | |
572 | void *mem; | |
573 | enum i40iw_status_code ret; | |
574 | int err_code; | |
575 | int sq_size; | |
576 | int rq_size; | |
577 | struct i40iw_sc_qp *qp; | |
578 | struct i40iw_sc_dev *dev = &iwdev->sc_dev; | |
579 | struct i40iw_qp_init_info init_info; | |
580 | struct i40iw_create_qp_info *qp_info; | |
581 | struct i40iw_cqp_request *cqp_request; | |
582 | struct cqp_commands_info *cqp_info; | |
583 | ||
584 | struct i40iw_qp_host_ctx_info *ctx_info; | |
585 | struct i40iwarp_offload_info *iwarp_info; | |
586 | unsigned long flags; | |
587 | ||
d5965934 MI |
588 | if (iwdev->closing) |
589 | return ERR_PTR(-ENODEV); | |
590 | ||
d3749841 FL |
591 | if (init_attr->create_flags) |
592 | return ERR_PTR(-EINVAL); | |
593 | if (init_attr->cap.max_inline_data > I40IW_MAX_INLINE_DATA_SIZE) | |
594 | init_attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE; | |
595 | ||
23ef48ad IM |
596 | if (init_attr->cap.max_send_sge > I40IW_MAX_WQ_FRAGMENT_COUNT) |
597 | init_attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT; | |
598 | ||
01d0b367 HO |
599 | if (init_attr->cap.max_recv_sge > I40IW_MAX_WQ_FRAGMENT_COUNT) |
600 | init_attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT; | |
601 | ||
d3749841 FL |
602 | memset(&init_info, 0, sizeof(init_info)); |
603 | ||
604 | sq_size = init_attr->cap.max_send_wr; | |
605 | rq_size = init_attr->cap.max_recv_wr; | |
606 | ||
d6f7bbcc | 607 | init_info.vsi = &iwdev->vsi; |
d3749841 FL |
608 | init_info.qp_uk_init_info.sq_size = sq_size; |
609 | init_info.qp_uk_init_info.rq_size = rq_size; | |
610 | init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge; | |
611 | init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge; | |
23ef48ad | 612 | init_info.qp_uk_init_info.max_inline_data = init_attr->cap.max_inline_data; |
d3749841 FL |
613 | |
614 | mem = kzalloc(sizeof(*iwqp), GFP_KERNEL); | |
615 | if (!mem) | |
616 | return ERR_PTR(-ENOMEM); | |
617 | ||
618 | iwqp = (struct i40iw_qp *)mem; | |
5a7189d5 | 619 | iwqp->allocated_buffer = mem; |
d3749841 FL |
620 | qp = &iwqp->sc_qp; |
621 | qp->back_qp = (void *)iwqp; | |
622 | qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX; | |
623 | ||
624 | iwqp->ctx_info.iwarp_info = &iwqp->iwarp_info; | |
625 | ||
626 | if (i40iw_allocate_dma_mem(dev->hw, | |
627 | &iwqp->q2_ctx_mem, | |
628 | I40IW_Q2_BUFFER_SIZE + I40IW_QP_CTX_SIZE, | |
629 | 256)) { | |
630 | i40iw_pr_err("dma_mem failed\n"); | |
631 | err_code = -ENOMEM; | |
632 | goto error; | |
633 | } | |
634 | ||
635 | init_info.q2 = iwqp->q2_ctx_mem.va; | |
636 | init_info.q2_pa = iwqp->q2_ctx_mem.pa; | |
637 | ||
638 | init_info.host_ctx = (void *)init_info.q2 + I40IW_Q2_BUFFER_SIZE; | |
639 | init_info.host_ctx_pa = init_info.q2_pa + I40IW_Q2_BUFFER_SIZE; | |
640 | ||
641 | err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_qps, iwdev->max_qp, | |
642 | &qp_num, &iwdev->next_qp); | |
643 | if (err_code) { | |
644 | i40iw_pr_err("qp resource\n"); | |
645 | goto error; | |
646 | } | |
647 | ||
d3749841 FL |
648 | iwqp->iwdev = iwdev; |
649 | iwqp->iwpd = iwpd; | |
650 | iwqp->ibqp.qp_num = qp_num; | |
651 | qp = &iwqp->sc_qp; | |
652 | iwqp->iwscq = to_iwcq(init_attr->send_cq); | |
653 | iwqp->iwrcq = to_iwcq(init_attr->recv_cq); | |
654 | ||
655 | iwqp->host_ctx.va = init_info.host_ctx; | |
656 | iwqp->host_ctx.pa = init_info.host_ctx_pa; | |
657 | iwqp->host_ctx.size = I40IW_QP_CTX_SIZE; | |
658 | ||
659 | init_info.pd = &iwpd->sc_pd; | |
660 | init_info.qp_uk_init_info.qp_id = iwqp->ibqp.qp_num; | |
661 | iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp; | |
662 | ||
663 | if (init_attr->qp_type != IB_QPT_RC) { | |
fe5d6e62 | 664 | err_code = -EINVAL; |
d3749841 FL |
665 | goto error; |
666 | } | |
667 | if (iwdev->push_mode) | |
668 | i40iw_alloc_push_page(iwdev, qp); | |
669 | if (udata) { | |
670 | err_code = ib_copy_from_udata(&req, udata, sizeof(req)); | |
671 | if (err_code) { | |
672 | i40iw_pr_err("ib_copy_from_data\n"); | |
673 | goto error; | |
674 | } | |
675 | iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx; | |
676 | if (ibpd->uobject && ibpd->uobject->context) { | |
677 | iwqp->user_mode = 1; | |
678 | ucontext = to_ucontext(ibpd->uobject->context); | |
679 | ||
680 | if (req.user_wqe_buffers) { | |
af56e53c TN |
681 | struct i40iw_pbl *iwpbl; |
682 | ||
d3749841 FL |
683 | spin_lock_irqsave( |
684 | &ucontext->qp_reg_mem_list_lock, flags); | |
af56e53c | 685 | iwpbl = i40iw_get_pbl( |
d3749841 FL |
686 | (unsigned long)req.user_wqe_buffers, |
687 | &ucontext->qp_reg_mem_list); | |
688 | spin_unlock_irqrestore( | |
689 | &ucontext->qp_reg_mem_list_lock, flags); | |
690 | ||
af56e53c | 691 | if (!iwpbl) { |
d3749841 FL |
692 | err_code = -ENODATA; |
693 | i40iw_pr_err("no pbl info\n"); | |
694 | goto error; | |
695 | } | |
af56e53c | 696 | memcpy(&iwqp->iwpbl, iwpbl, sizeof(iwqp->iwpbl)); |
d3749841 FL |
697 | } |
698 | } | |
699 | err_code = i40iw_setup_virt_qp(iwdev, iwqp, &init_info); | |
700 | } else { | |
701 | err_code = i40iw_setup_kmode_qp(iwdev, iwqp, &init_info); | |
702 | } | |
703 | ||
704 | if (err_code) { | |
705 | i40iw_pr_err("setup qp failed\n"); | |
706 | goto error; | |
707 | } | |
708 | ||
709 | init_info.type = I40IW_QP_TYPE_IWARP; | |
710 | ret = dev->iw_priv_qp_ops->qp_init(qp, &init_info); | |
711 | if (ret) { | |
712 | err_code = -EPROTO; | |
713 | i40iw_pr_err("qp_init fail\n"); | |
714 | goto error; | |
715 | } | |
716 | ctx_info = &iwqp->ctx_info; | |
717 | iwarp_info = &iwqp->iwarp_info; | |
718 | iwarp_info->rd_enable = true; | |
719 | iwarp_info->wr_rdresp_en = true; | |
b7aee855 IM |
720 | if (!iwqp->user_mode) { |
721 | iwarp_info->fast_reg_en = true; | |
d3749841 | 722 | iwarp_info->priv_mode_en = true; |
b7aee855 | 723 | } |
d3749841 FL |
724 | iwarp_info->ddp_ver = 1; |
725 | iwarp_info->rdmap_ver = 1; | |
726 | ||
727 | ctx_info->iwarp_info_valid = true; | |
728 | ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id; | |
729 | ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id; | |
730 | if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX) { | |
731 | ctx_info->push_mode_en = false; | |
732 | } else { | |
733 | ctx_info->push_mode_en = true; | |
734 | ctx_info->push_idx = qp->push_idx; | |
735 | } | |
736 | ||
737 | ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp, | |
738 | (u64 *)iwqp->host_ctx.va, | |
739 | ctx_info); | |
740 | ctx_info->iwarp_info_valid = false; | |
741 | cqp_request = i40iw_get_cqp_request(iwcqp, true); | |
742 | if (!cqp_request) { | |
743 | err_code = -ENOMEM; | |
744 | goto error; | |
745 | } | |
746 | cqp_info = &cqp_request->info; | |
747 | qp_info = &cqp_request->info.in.u.qp_create.info; | |
748 | ||
749 | memset(qp_info, 0, sizeof(*qp_info)); | |
750 | ||
751 | qp_info->cq_num_valid = true; | |
752 | qp_info->next_iwarp_state = I40IW_QP_STATE_IDLE; | |
753 | ||
754 | cqp_info->cqp_cmd = OP_QP_CREATE; | |
755 | cqp_info->post_sq = 1; | |
756 | cqp_info->in.u.qp_create.qp = qp; | |
757 | cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request; | |
758 | ret = i40iw_handle_cqp_op(iwdev, cqp_request); | |
759 | if (ret) { | |
760 | i40iw_pr_err("CQP-OP QP create fail"); | |
761 | err_code = -EACCES; | |
762 | goto error; | |
763 | } | |
764 | ||
765 | i40iw_add_ref(&iwqp->ibqp); | |
766 | spin_lock_init(&iwqp->lock); | |
767 | iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0; | |
768 | iwdev->qp_table[qp_num] = iwqp; | |
769 | i40iw_add_pdusecount(iwqp->iwpd); | |
d5965934 | 770 | i40iw_add_devusecount(iwdev); |
d3749841 FL |
771 | if (ibpd->uobject && udata) { |
772 | memset(&uresp, 0, sizeof(uresp)); | |
773 | uresp.actual_sq_size = sq_size; | |
774 | uresp.actual_rq_size = rq_size; | |
775 | uresp.qp_id = qp_num; | |
776 | uresp.push_idx = qp->push_idx; | |
777 | err_code = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); | |
778 | if (err_code) { | |
779 | i40iw_pr_err("copy_to_udata failed\n"); | |
780 | i40iw_destroy_qp(&iwqp->ibqp); | |
781 | /* let the completion of the qp destroy free the qp */ | |
782 | return ERR_PTR(err_code); | |
783 | } | |
784 | } | |
c2b75ef7 IM |
785 | init_completion(&iwqp->sq_drained); |
786 | init_completion(&iwqp->rq_drained); | |
d3749841 FL |
787 | |
788 | return &iwqp->ibqp; | |
789 | error: | |
790 | i40iw_free_qp_resources(iwdev, iwqp, qp_num); | |
d3749841 FL |
791 | return ERR_PTR(err_code); |
792 | } | |
793 | ||
794 | /** | |
795 | * i40iw_query - query qp attributes | |
796 | * @ibqp: qp pointer | |
797 | * @attr: attributes pointer | |
798 | * @attr_mask: Not used | |
799 | * @init_attr: qp attributes to return | |
800 | */ | |
801 | static int i40iw_query_qp(struct ib_qp *ibqp, | |
802 | struct ib_qp_attr *attr, | |
803 | int attr_mask, | |
804 | struct ib_qp_init_attr *init_attr) | |
805 | { | |
806 | struct i40iw_qp *iwqp = to_iwqp(ibqp); | |
807 | struct i40iw_sc_qp *qp = &iwqp->sc_qp; | |
808 | ||
809 | attr->qp_access_flags = 0; | |
810 | attr->cap.max_send_wr = qp->qp_uk.sq_size; | |
811 | attr->cap.max_recv_wr = qp->qp_uk.rq_size; | |
d3749841 | 812 | attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE; |
01d0b367 HO |
813 | attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT; |
814 | attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT; | |
789f903f | 815 | attr->port_num = 1; |
d3749841 FL |
816 | init_attr->event_handler = iwqp->ibqp.event_handler; |
817 | init_attr->qp_context = iwqp->ibqp.qp_context; | |
818 | init_attr->send_cq = iwqp->ibqp.send_cq; | |
819 | init_attr->recv_cq = iwqp->ibqp.recv_cq; | |
820 | init_attr->srq = iwqp->ibqp.srq; | |
821 | init_attr->cap = attr->cap; | |
789f903f | 822 | init_attr->port_num = 1; |
d3749841 FL |
823 | return 0; |
824 | } | |
825 | ||
826 | /** | |
827 | * i40iw_hw_modify_qp - setup cqp for modify qp | |
828 | * @iwdev: iwarp device | |
829 | * @iwqp: qp ptr (user or kernel) | |
830 | * @info: info for modify qp | |
831 | * @wait: flag to wait or not for modify qp completion | |
832 | */ | |
833 | void i40iw_hw_modify_qp(struct i40iw_device *iwdev, struct i40iw_qp *iwqp, | |
834 | struct i40iw_modify_qp_info *info, bool wait) | |
835 | { | |
d3749841 FL |
836 | struct i40iw_cqp_request *cqp_request; |
837 | struct cqp_commands_info *cqp_info; | |
838 | struct i40iw_modify_qp_info *m_info; | |
546b1452 | 839 | struct i40iw_gen_ae_info ae_info; |
d3749841 FL |
840 | |
841 | cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait); | |
842 | if (!cqp_request) | |
843 | return; | |
844 | ||
845 | cqp_info = &cqp_request->info; | |
846 | m_info = &cqp_info->in.u.qp_modify.info; | |
847 | memcpy(m_info, info, sizeof(*m_info)); | |
848 | cqp_info->cqp_cmd = OP_QP_MODIFY; | |
849 | cqp_info->post_sq = 1; | |
850 | cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp; | |
851 | cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request; | |
546b1452 HO |
852 | if (!i40iw_handle_cqp_op(iwdev, cqp_request)) |
853 | return; | |
854 | ||
855 | switch (m_info->next_iwarp_state) { | |
856 | case I40IW_QP_STATE_RTS: | |
857 | if (iwqp->iwarp_state == I40IW_QP_STATE_IDLE) | |
858 | i40iw_send_reset(iwqp->cm_node); | |
859 | /* fall through */ | |
860 | case I40IW_QP_STATE_IDLE: | |
861 | case I40IW_QP_STATE_TERMINATE: | |
862 | case I40IW_QP_STATE_CLOSING: | |
863 | ae_info.ae_code = I40IW_AE_BAD_CLOSE; | |
864 | ae_info.ae_source = 0; | |
865 | i40iw_gen_ae(iwdev, &iwqp->sc_qp, &ae_info, false); | |
866 | break; | |
867 | case I40IW_QP_STATE_ERROR: | |
868 | default: | |
869 | break; | |
870 | } | |
d3749841 FL |
871 | } |
872 | ||
873 | /** | |
874 | * i40iw_modify_qp - modify qp request | |
875 | * @ibqp: qp's pointer for modify | |
876 | * @attr: access attributes | |
877 | * @attr_mask: state mask | |
878 | * @udata: user data | |
879 | */ | |
880 | int i40iw_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
881 | int attr_mask, struct ib_udata *udata) | |
882 | { | |
883 | struct i40iw_qp *iwqp = to_iwqp(ibqp); | |
884 | struct i40iw_device *iwdev = iwqp->iwdev; | |
885 | struct i40iw_qp_host_ctx_info *ctx_info; | |
886 | struct i40iwarp_offload_info *iwarp_info; | |
887 | struct i40iw_modify_qp_info info; | |
888 | u8 issue_modify_qp = 0; | |
889 | u8 dont_wait = 0; | |
890 | u32 err; | |
891 | unsigned long flags; | |
892 | ||
893 | memset(&info, 0, sizeof(info)); | |
894 | ctx_info = &iwqp->ctx_info; | |
895 | iwarp_info = &iwqp->iwarp_info; | |
896 | ||
897 | spin_lock_irqsave(&iwqp->lock, flags); | |
898 | ||
899 | if (attr_mask & IB_QP_STATE) { | |
d5965934 MI |
900 | if (iwdev->closing && attr->qp_state != IB_QPS_ERR) { |
901 | err = -EINVAL; | |
902 | goto exit; | |
903 | } | |
904 | ||
d3749841 FL |
905 | switch (attr->qp_state) { |
906 | case IB_QPS_INIT: | |
907 | case IB_QPS_RTR: | |
908 | if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_IDLE) { | |
909 | err = -EINVAL; | |
910 | goto exit; | |
911 | } | |
912 | if (iwqp->iwarp_state == I40IW_QP_STATE_INVALID) { | |
913 | info.next_iwarp_state = I40IW_QP_STATE_IDLE; | |
914 | issue_modify_qp = 1; | |
915 | } | |
916 | break; | |
917 | case IB_QPS_RTS: | |
918 | if ((iwqp->iwarp_state > (u32)I40IW_QP_STATE_RTS) || | |
919 | (!iwqp->cm_id)) { | |
920 | err = -EINVAL; | |
921 | goto exit; | |
922 | } | |
923 | ||
924 | issue_modify_qp = 1; | |
925 | iwqp->hw_tcp_state = I40IW_TCP_STATE_ESTABLISHED; | |
926 | iwqp->hte_added = 1; | |
927 | info.next_iwarp_state = I40IW_QP_STATE_RTS; | |
928 | info.tcp_ctx_valid = true; | |
929 | info.ord_valid = true; | |
930 | info.arp_cache_idx_valid = true; | |
931 | info.cq_num_valid = true; | |
932 | break; | |
933 | case IB_QPS_SQD: | |
934 | if (iwqp->hw_iwarp_state > (u32)I40IW_QP_STATE_RTS) { | |
935 | err = 0; | |
936 | goto exit; | |
937 | } | |
938 | if ((iwqp->iwarp_state == (u32)I40IW_QP_STATE_CLOSING) || | |
939 | (iwqp->iwarp_state < (u32)I40IW_QP_STATE_RTS)) { | |
940 | err = 0; | |
941 | goto exit; | |
942 | } | |
943 | if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_CLOSING) { | |
944 | err = -EINVAL; | |
945 | goto exit; | |
946 | } | |
947 | info.next_iwarp_state = I40IW_QP_STATE_CLOSING; | |
948 | issue_modify_qp = 1; | |
949 | break; | |
950 | case IB_QPS_SQE: | |
951 | if (iwqp->iwarp_state >= (u32)I40IW_QP_STATE_TERMINATE) { | |
952 | err = -EINVAL; | |
953 | goto exit; | |
954 | } | |
955 | info.next_iwarp_state = I40IW_QP_STATE_TERMINATE; | |
956 | issue_modify_qp = 1; | |
957 | break; | |
958 | case IB_QPS_ERR: | |
959 | case IB_QPS_RESET: | |
960 | if (iwqp->iwarp_state == (u32)I40IW_QP_STATE_ERROR) { | |
961 | err = -EINVAL; | |
962 | goto exit; | |
963 | } | |
964 | if (iwqp->sc_qp.term_flags) | |
d627b506 | 965 | i40iw_terminate_del_timer(&iwqp->sc_qp); |
d3749841 FL |
966 | info.next_iwarp_state = I40IW_QP_STATE_ERROR; |
967 | if ((iwqp->hw_tcp_state > I40IW_TCP_STATE_CLOSED) && | |
968 | iwdev->iw_status && | |
969 | (iwqp->hw_tcp_state != I40IW_TCP_STATE_TIME_WAIT)) | |
970 | info.reset_tcp_conn = true; | |
971 | else | |
972 | dont_wait = 1; | |
973 | issue_modify_qp = 1; | |
974 | info.next_iwarp_state = I40IW_QP_STATE_ERROR; | |
975 | break; | |
976 | default: | |
977 | err = -EINVAL; | |
978 | goto exit; | |
979 | } | |
980 | ||
981 | iwqp->ibqp_state = attr->qp_state; | |
982 | ||
d3749841 FL |
983 | } |
984 | if (attr_mask & IB_QP_ACCESS_FLAGS) { | |
985 | ctx_info->iwarp_info_valid = true; | |
986 | if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE) | |
987 | iwarp_info->wr_rdresp_en = true; | |
988 | if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) | |
989 | iwarp_info->wr_rdresp_en = true; | |
990 | if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) | |
991 | iwarp_info->rd_enable = true; | |
992 | if (attr->qp_access_flags & IB_ACCESS_MW_BIND) | |
993 | iwarp_info->bind_en = true; | |
994 | ||
995 | if (iwqp->user_mode) { | |
996 | iwarp_info->rd_enable = true; | |
997 | iwarp_info->wr_rdresp_en = true; | |
998 | iwarp_info->priv_mode_en = false; | |
999 | } | |
1000 | } | |
1001 | ||
1002 | if (ctx_info->iwarp_info_valid) { | |
1003 | struct i40iw_sc_dev *dev = &iwdev->sc_dev; | |
1004 | int ret; | |
1005 | ||
1006 | ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id; | |
1007 | ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id; | |
1008 | ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp, | |
1009 | (u64 *)iwqp->host_ctx.va, | |
1010 | ctx_info); | |
1011 | if (ret) { | |
1012 | i40iw_pr_err("setting QP context\n"); | |
1013 | err = -EINVAL; | |
1014 | goto exit; | |
1015 | } | |
1016 | } | |
1017 | ||
1018 | spin_unlock_irqrestore(&iwqp->lock, flags); | |
1019 | ||
546b1452 | 1020 | if (issue_modify_qp) { |
d3749841 FL |
1021 | i40iw_hw_modify_qp(iwdev, iwqp, &info, true); |
1022 | ||
546b1452 HO |
1023 | spin_lock_irqsave(&iwqp->lock, flags); |
1024 | iwqp->iwarp_state = info.next_iwarp_state; | |
1025 | spin_unlock_irqrestore(&iwqp->lock, flags); | |
1026 | } | |
1027 | ||
d3749841 FL |
1028 | if (issue_modify_qp && (iwqp->ibqp_state > IB_QPS_RTS)) { |
1029 | if (dont_wait) { | |
1030 | if (iwqp->cm_id && iwqp->hw_tcp_state) { | |
1031 | spin_lock_irqsave(&iwqp->lock, flags); | |
1032 | iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSED; | |
1033 | iwqp->last_aeq = I40IW_AE_RESET_SENT; | |
1034 | spin_unlock_irqrestore(&iwqp->lock, flags); | |
471b370d | 1035 | i40iw_cm_disconn(iwqp); |
d3749841 | 1036 | } |
471b370d SS |
1037 | } else { |
1038 | spin_lock_irqsave(&iwqp->lock, flags); | |
1039 | if (iwqp->cm_id) { | |
1040 | if (atomic_inc_return(&iwqp->close_timer_started) == 1) { | |
1041 | iwqp->cm_id->add_ref(iwqp->cm_id); | |
1042 | i40iw_schedule_cm_timer(iwqp->cm_node, | |
1043 | (struct i40iw_puda_buf *)iwqp, | |
1044 | I40IW_TIMER_TYPE_CLOSE, 1, 0); | |
1045 | } | |
1046 | } | |
1047 | spin_unlock_irqrestore(&iwqp->lock, flags); | |
d3749841 FL |
1048 | } |
1049 | } | |
1050 | return 0; | |
1051 | exit: | |
1052 | spin_unlock_irqrestore(&iwqp->lock, flags); | |
1053 | return err; | |
1054 | } | |
1055 | ||
1056 | /** | |
1057 | * cq_free_resources - free up recources for cq | |
1058 | * @iwdev: iwarp device | |
1059 | * @iwcq: cq ptr | |
1060 | */ | |
1061 | static void cq_free_resources(struct i40iw_device *iwdev, struct i40iw_cq *iwcq) | |
1062 | { | |
1063 | struct i40iw_sc_cq *cq = &iwcq->sc_cq; | |
1064 | ||
1065 | if (!iwcq->user_mode) | |
1066 | i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwcq->kmem); | |
1067 | i40iw_free_resource(iwdev, iwdev->allocated_cqs, cq->cq_uk.cq_id); | |
1068 | } | |
1069 | ||
1070 | /** | |
d6f7bbcc | 1071 | * i40iw_cq_wq_destroy - send cq destroy cqp |
d3749841 FL |
1072 | * @iwdev: iwarp device |
1073 | * @cq: hardware control cq | |
1074 | */ | |
d6f7bbcc | 1075 | void i40iw_cq_wq_destroy(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq) |
d3749841 FL |
1076 | { |
1077 | enum i40iw_status_code status; | |
1078 | struct i40iw_cqp_request *cqp_request; | |
1079 | struct cqp_commands_info *cqp_info; | |
1080 | ||
1081 | cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true); | |
1082 | if (!cqp_request) | |
1083 | return; | |
1084 | ||
1085 | cqp_info = &cqp_request->info; | |
1086 | ||
1087 | cqp_info->cqp_cmd = OP_CQ_DESTROY; | |
1088 | cqp_info->post_sq = 1; | |
1089 | cqp_info->in.u.cq_destroy.cq = cq; | |
1090 | cqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request; | |
1091 | status = i40iw_handle_cqp_op(iwdev, cqp_request); | |
1092 | if (status) | |
1093 | i40iw_pr_err("CQP-OP Destroy QP fail"); | |
1094 | } | |
1095 | ||
1096 | /** | |
1097 | * i40iw_destroy_cq - destroy cq | |
1098 | * @ib_cq: cq pointer | |
1099 | */ | |
1100 | static int i40iw_destroy_cq(struct ib_cq *ib_cq) | |
1101 | { | |
1102 | struct i40iw_cq *iwcq; | |
1103 | struct i40iw_device *iwdev; | |
1104 | struct i40iw_sc_cq *cq; | |
1105 | ||
1106 | if (!ib_cq) { | |
1107 | i40iw_pr_err("ib_cq == NULL\n"); | |
1108 | return 0; | |
1109 | } | |
1110 | ||
1111 | iwcq = to_iwcq(ib_cq); | |
1112 | iwdev = to_iwdev(ib_cq->device); | |
1113 | cq = &iwcq->sc_cq; | |
d6f7bbcc | 1114 | i40iw_cq_wq_destroy(iwdev, cq); |
d3749841 FL |
1115 | cq_free_resources(iwdev, iwcq); |
1116 | kfree(iwcq); | |
d5965934 | 1117 | i40iw_rem_devusecount(iwdev); |
d3749841 FL |
1118 | return 0; |
1119 | } | |
1120 | ||
1121 | /** | |
1122 | * i40iw_create_cq - create cq | |
1123 | * @ibdev: device pointer from stack | |
1124 | * @attr: attributes for cq | |
1125 | * @context: user context created during alloc | |
1126 | * @udata: user data | |
1127 | */ | |
1128 | static struct ib_cq *i40iw_create_cq(struct ib_device *ibdev, | |
1129 | const struct ib_cq_init_attr *attr, | |
1130 | struct ib_ucontext *context, | |
1131 | struct ib_udata *udata) | |
1132 | { | |
1133 | struct i40iw_device *iwdev = to_iwdev(ibdev); | |
1134 | struct i40iw_cq *iwcq; | |
1135 | struct i40iw_pbl *iwpbl; | |
1136 | u32 cq_num = 0; | |
1137 | struct i40iw_sc_cq *cq; | |
1138 | struct i40iw_sc_dev *dev = &iwdev->sc_dev; | |
1139 | struct i40iw_cq_init_info info; | |
1140 | enum i40iw_status_code status; | |
1141 | struct i40iw_cqp_request *cqp_request; | |
1142 | struct cqp_commands_info *cqp_info; | |
1143 | struct i40iw_cq_uk_init_info *ukinfo = &info.cq_uk_init_info; | |
1144 | unsigned long flags; | |
1145 | int err_code; | |
1146 | int entries = attr->cqe; | |
1147 | ||
d5965934 MI |
1148 | if (iwdev->closing) |
1149 | return ERR_PTR(-ENODEV); | |
1150 | ||
d3749841 FL |
1151 | if (entries > iwdev->max_cqe) |
1152 | return ERR_PTR(-EINVAL); | |
1153 | ||
1154 | iwcq = kzalloc(sizeof(*iwcq), GFP_KERNEL); | |
1155 | if (!iwcq) | |
1156 | return ERR_PTR(-ENOMEM); | |
1157 | ||
1158 | memset(&info, 0, sizeof(info)); | |
1159 | ||
1160 | err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_cqs, | |
1161 | iwdev->max_cq, &cq_num, | |
1162 | &iwdev->next_cq); | |
1163 | if (err_code) | |
1164 | goto error; | |
1165 | ||
1166 | cq = &iwcq->sc_cq; | |
1167 | cq->back_cq = (void *)iwcq; | |
1168 | spin_lock_init(&iwcq->lock); | |
1169 | ||
1170 | info.dev = dev; | |
1171 | ukinfo->cq_size = max(entries, 4); | |
1172 | ukinfo->cq_id = cq_num; | |
1173 | iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size; | |
1174 | info.ceqe_mask = 0; | |
e69c5093 HO |
1175 | if (attr->comp_vector < iwdev->ceqs_count) |
1176 | info.ceq_id = attr->comp_vector; | |
d3749841 FL |
1177 | info.ceq_id_valid = true; |
1178 | info.ceqe_mask = 1; | |
1179 | info.type = I40IW_CQ_TYPE_IWARP; | |
1180 | if (context) { | |
1181 | struct i40iw_ucontext *ucontext; | |
1182 | struct i40iw_create_cq_req req; | |
1183 | struct i40iw_cq_mr *cqmr; | |
1184 | ||
1185 | memset(&req, 0, sizeof(req)); | |
1186 | iwcq->user_mode = true; | |
1187 | ucontext = to_ucontext(context); | |
6031e079 DC |
1188 | if (ib_copy_from_udata(&req, udata, sizeof(struct i40iw_create_cq_req))) { |
1189 | err_code = -EFAULT; | |
d3749841 | 1190 | goto cq_free_resources; |
6031e079 | 1191 | } |
d3749841 FL |
1192 | |
1193 | spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags); | |
1194 | iwpbl = i40iw_get_pbl((unsigned long)req.user_cq_buffer, | |
1195 | &ucontext->cq_reg_mem_list); | |
1196 | spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags); | |
1197 | if (!iwpbl) { | |
1198 | err_code = -EPROTO; | |
1199 | goto cq_free_resources; | |
1200 | } | |
1201 | ||
1202 | iwcq->iwpbl = iwpbl; | |
1203 | iwcq->cq_mem_size = 0; | |
1204 | cqmr = &iwpbl->cq_mr; | |
1205 | info.shadow_area_pa = cpu_to_le64(cqmr->shadow); | |
1206 | if (iwpbl->pbl_allocated) { | |
1207 | info.virtual_map = true; | |
1208 | info.pbl_chunk_size = 1; | |
1209 | info.first_pm_pbl_idx = cqmr->cq_pbl.idx; | |
1210 | } else { | |
1211 | info.cq_base_pa = cqmr->cq_pbl.addr; | |
1212 | } | |
1213 | } else { | |
1214 | /* Kmode allocations */ | |
1215 | int rsize; | |
1216 | int shadow; | |
1217 | ||
1218 | rsize = info.cq_uk_init_info.cq_size * sizeof(struct i40iw_cqe); | |
1219 | rsize = round_up(rsize, 256); | |
1220 | shadow = I40IW_SHADOW_AREA_SIZE << 3; | |
1221 | status = i40iw_allocate_dma_mem(dev->hw, &iwcq->kmem, | |
1222 | rsize + shadow, 256); | |
1223 | if (status) { | |
1224 | err_code = -ENOMEM; | |
1225 | goto cq_free_resources; | |
1226 | } | |
1227 | ukinfo->cq_base = iwcq->kmem.va; | |
1228 | info.cq_base_pa = iwcq->kmem.pa; | |
1229 | info.shadow_area_pa = info.cq_base_pa + rsize; | |
1230 | ukinfo->shadow_area = iwcq->kmem.va + rsize; | |
1231 | } | |
1232 | ||
1233 | if (dev->iw_priv_cq_ops->cq_init(cq, &info)) { | |
1234 | i40iw_pr_err("init cq fail\n"); | |
1235 | err_code = -EPROTO; | |
1236 | goto cq_free_resources; | |
1237 | } | |
1238 | ||
1239 | cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true); | |
1240 | if (!cqp_request) { | |
1241 | err_code = -ENOMEM; | |
1242 | goto cq_free_resources; | |
1243 | } | |
1244 | ||
1245 | cqp_info = &cqp_request->info; | |
1246 | cqp_info->cqp_cmd = OP_CQ_CREATE; | |
1247 | cqp_info->post_sq = 1; | |
1248 | cqp_info->in.u.cq_create.cq = cq; | |
1249 | cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request; | |
1250 | status = i40iw_handle_cqp_op(iwdev, cqp_request); | |
1251 | if (status) { | |
1252 | i40iw_pr_err("CQP-OP Create QP fail"); | |
1253 | err_code = -EPROTO; | |
1254 | goto cq_free_resources; | |
1255 | } | |
1256 | ||
1257 | if (context) { | |
1258 | struct i40iw_create_cq_resp resp; | |
1259 | ||
1260 | memset(&resp, 0, sizeof(resp)); | |
1261 | resp.cq_id = info.cq_uk_init_info.cq_id; | |
1262 | resp.cq_size = info.cq_uk_init_info.cq_size; | |
1263 | if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { | |
1264 | i40iw_pr_err("copy to user data\n"); | |
1265 | err_code = -EPROTO; | |
1266 | goto cq_destroy; | |
1267 | } | |
1268 | } | |
1269 | ||
d5965934 | 1270 | i40iw_add_devusecount(iwdev); |
d3749841 FL |
1271 | return (struct ib_cq *)iwcq; |
1272 | ||
1273 | cq_destroy: | |
d6f7bbcc | 1274 | i40iw_cq_wq_destroy(iwdev, cq); |
d3749841 FL |
1275 | cq_free_resources: |
1276 | cq_free_resources(iwdev, iwcq); | |
1277 | error: | |
1278 | kfree(iwcq); | |
1279 | return ERR_PTR(err_code); | |
1280 | } | |
1281 | ||
1282 | /** | |
1283 | * i40iw_get_user_access - get hw access from IB access | |
1284 | * @acc: IB access to return hw access | |
1285 | */ | |
1286 | static inline u16 i40iw_get_user_access(int acc) | |
1287 | { | |
1288 | u16 access = 0; | |
1289 | ||
1290 | access |= (acc & IB_ACCESS_LOCAL_WRITE) ? I40IW_ACCESS_FLAGS_LOCALWRITE : 0; | |
1291 | access |= (acc & IB_ACCESS_REMOTE_WRITE) ? I40IW_ACCESS_FLAGS_REMOTEWRITE : 0; | |
1292 | access |= (acc & IB_ACCESS_REMOTE_READ) ? I40IW_ACCESS_FLAGS_REMOTEREAD : 0; | |
1293 | access |= (acc & IB_ACCESS_MW_BIND) ? I40IW_ACCESS_FLAGS_BIND_WINDOW : 0; | |
1294 | return access; | |
1295 | } | |
1296 | ||
1297 | /** | |
1298 | * i40iw_free_stag - free stag resource | |
1299 | * @iwdev: iwarp device | |
1300 | * @stag: stag to free | |
1301 | */ | |
1302 | static void i40iw_free_stag(struct i40iw_device *iwdev, u32 stag) | |
1303 | { | |
1304 | u32 stag_idx; | |
1305 | ||
1306 | stag_idx = (stag & iwdev->mr_stagmask) >> I40IW_CQPSQ_STAG_IDX_SHIFT; | |
1307 | i40iw_free_resource(iwdev, iwdev->allocated_mrs, stag_idx); | |
d5965934 | 1308 | i40iw_rem_devusecount(iwdev); |
d3749841 FL |
1309 | } |
1310 | ||
1311 | /** | |
1312 | * i40iw_create_stag - create random stag | |
1313 | * @iwdev: iwarp device | |
1314 | */ | |
1315 | static u32 i40iw_create_stag(struct i40iw_device *iwdev) | |
1316 | { | |
1317 | u32 stag = 0; | |
1318 | u32 stag_index = 0; | |
1319 | u32 next_stag_index; | |
1320 | u32 driver_key; | |
1321 | u32 random; | |
1322 | u8 consumer_key; | |
1323 | int ret; | |
1324 | ||
1325 | get_random_bytes(&random, sizeof(random)); | |
1326 | consumer_key = (u8)random; | |
1327 | ||
1328 | driver_key = random & ~iwdev->mr_stagmask; | |
1329 | next_stag_index = (random & iwdev->mr_stagmask) >> 8; | |
1330 | next_stag_index %= iwdev->max_mr; | |
1331 | ||
1332 | ret = i40iw_alloc_resource(iwdev, | |
1333 | iwdev->allocated_mrs, iwdev->max_mr, | |
1334 | &stag_index, &next_stag_index); | |
1335 | if (!ret) { | |
1336 | stag = stag_index << I40IW_CQPSQ_STAG_IDX_SHIFT; | |
1337 | stag |= driver_key; | |
1338 | stag += (u32)consumer_key; | |
d5965934 | 1339 | i40iw_add_devusecount(iwdev); |
d3749841 FL |
1340 | } |
1341 | return stag; | |
1342 | } | |
1343 | ||
1344 | /** | |
1345 | * i40iw_next_pbl_addr - Get next pbl address | |
d3749841 FL |
1346 | * @pbl: pointer to a pble |
1347 | * @pinfo: info pointer | |
1348 | * @idx: index | |
1349 | */ | |
f26c7c83 | 1350 | static inline u64 *i40iw_next_pbl_addr(u64 *pbl, |
d3749841 FL |
1351 | struct i40iw_pble_info **pinfo, |
1352 | u32 *idx) | |
1353 | { | |
1354 | *idx += 1; | |
1355 | if ((!(*pinfo)) || (*idx != (*pinfo)->cnt)) | |
1356 | return ++pbl; | |
1357 | *idx = 0; | |
1358 | (*pinfo)++; | |
1359 | return (u64 *)(*pinfo)->addr; | |
1360 | } | |
1361 | ||
1362 | /** | |
1363 | * i40iw_copy_user_pgaddrs - copy user page address to pble's os locally | |
1364 | * @iwmr: iwmr for IB's user page addresses | |
1365 | * @pbl: ple pointer to save 1 level or 0 level pble | |
1366 | * @level: indicated level 0, 1 or 2 | |
1367 | */ | |
1368 | static void i40iw_copy_user_pgaddrs(struct i40iw_mr *iwmr, | |
1369 | u64 *pbl, | |
1370 | enum i40iw_pble_level level) | |
1371 | { | |
1372 | struct ib_umem *region = iwmr->region; | |
1373 | struct i40iw_pbl *iwpbl = &iwmr->iwpbl; | |
3e7e1193 | 1374 | int chunk_pages, entry, i; |
d3749841 FL |
1375 | struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc; |
1376 | struct i40iw_pble_info *pinfo; | |
1377 | struct scatterlist *sg; | |
f26c7c83 | 1378 | u64 pg_addr = 0; |
d3749841 FL |
1379 | u32 idx = 0; |
1380 | ||
1381 | pinfo = (level == I40IW_LEVEL_1) ? NULL : palloc->level2.leaf; | |
f26c7c83 | 1382 | |
d3749841 | 1383 | for_each_sg(region->sg_head.sgl, sg, region->nmap, entry) { |
3e7e1193 | 1384 | chunk_pages = sg_dma_len(sg) >> region->page_shift; |
d3749841 FL |
1385 | if ((iwmr->type == IW_MEMREG_TYPE_QP) && |
1386 | !iwpbl->qp_mr.sq_page) | |
1387 | iwpbl->qp_mr.sq_page = sg_page(sg); | |
1388 | for (i = 0; i < chunk_pages; i++) { | |
3e7e1193 AK |
1389 | pg_addr = sg_dma_address(sg) + |
1390 | (i << region->page_shift); | |
f26c7c83 HO |
1391 | |
1392 | if ((entry + i) == 0) | |
1393 | *pbl = cpu_to_le64(pg_addr & iwmr->page_msk); | |
1394 | else if (!(pg_addr & ~iwmr->page_msk)) | |
1395 | *pbl = cpu_to_le64(pg_addr); | |
1396 | else | |
1397 | continue; | |
1398 | pbl = i40iw_next_pbl_addr(pbl, &pinfo, &idx); | |
d3749841 FL |
1399 | } |
1400 | } | |
1401 | } | |
1402 | ||
f26c7c83 HO |
1403 | /** |
1404 | * i40iw_set_hugetlb_params - set MR pg size and mask to huge pg values. | |
1405 | * @addr: virtual address | |
1406 | * @iwmr: mr pointer for this memory registration | |
1407 | */ | |
1408 | static void i40iw_set_hugetlb_values(u64 addr, struct i40iw_mr *iwmr) | |
1409 | { | |
1410 | struct vm_area_struct *vma; | |
1411 | struct hstate *h; | |
1412 | ||
5d9a2b0e | 1413 | down_read(¤t->mm->mmap_sem); |
f26c7c83 HO |
1414 | vma = find_vma(current->mm, addr); |
1415 | if (vma && is_vm_hugetlb_page(vma)) { | |
1416 | h = hstate_vma(vma); | |
1417 | if (huge_page_size(h) == 0x200000) { | |
1418 | iwmr->page_size = huge_page_size(h); | |
1419 | iwmr->page_msk = huge_page_mask(h); | |
d3749841 FL |
1420 | } |
1421 | } | |
5d9a2b0e | 1422 | up_read(¤t->mm->mmap_sem); |
d3749841 FL |
1423 | } |
1424 | ||
b6a529da HO |
1425 | /** |
1426 | * i40iw_check_mem_contiguous - check if pbls stored in arr are contiguous | |
1427 | * @arr: lvl1 pbl array | |
1428 | * @npages: page count | |
1429 | * pg_size: page size | |
1430 | * | |
1431 | */ | |
1432 | static bool i40iw_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size) | |
1433 | { | |
1434 | u32 pg_idx; | |
1435 | ||
1436 | for (pg_idx = 0; pg_idx < npages; pg_idx++) { | |
1437 | if ((*arr + (pg_size * pg_idx)) != arr[pg_idx]) | |
1438 | return false; | |
1439 | } | |
1440 | return true; | |
1441 | } | |
1442 | ||
1443 | /** | |
1444 | * i40iw_check_mr_contiguous - check if MR is physically contiguous | |
1445 | * @palloc: pbl allocation struct | |
1446 | * pg_size: page size | |
1447 | */ | |
1448 | static bool i40iw_check_mr_contiguous(struct i40iw_pble_alloc *palloc, u32 pg_size) | |
1449 | { | |
1450 | struct i40iw_pble_level2 *lvl2 = &palloc->level2; | |
1451 | struct i40iw_pble_info *leaf = lvl2->leaf; | |
1452 | u64 *arr = NULL; | |
1453 | u64 *start_addr = NULL; | |
1454 | int i; | |
1455 | bool ret; | |
1456 | ||
1457 | if (palloc->level == I40IW_LEVEL_1) { | |
1458 | arr = (u64 *)palloc->level1.addr; | |
1459 | ret = i40iw_check_mem_contiguous(arr, palloc->total_cnt, pg_size); | |
1460 | return ret; | |
1461 | } | |
1462 | ||
1463 | start_addr = (u64 *)leaf->addr; | |
1464 | ||
1465 | for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) { | |
1466 | arr = (u64 *)leaf->addr; | |
1467 | if ((*start_addr + (i * pg_size * PBLE_PER_PAGE)) != *arr) | |
1468 | return false; | |
1469 | ret = i40iw_check_mem_contiguous(arr, leaf->cnt, pg_size); | |
1470 | if (!ret) | |
1471 | return false; | |
1472 | } | |
1473 | ||
1474 | return true; | |
1475 | } | |
1476 | ||
d3749841 FL |
1477 | /** |
1478 | * i40iw_setup_pbles - copy user pg address to pble's | |
1479 | * @iwdev: iwarp device | |
1480 | * @iwmr: mr pointer for this memory registration | |
b6a529da | 1481 | * @use_pbles: flag if to use pble's |
d3749841 FL |
1482 | */ |
1483 | static int i40iw_setup_pbles(struct i40iw_device *iwdev, | |
1484 | struct i40iw_mr *iwmr, | |
1485 | bool use_pbles) | |
1486 | { | |
1487 | struct i40iw_pbl *iwpbl = &iwmr->iwpbl; | |
1488 | struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc; | |
1489 | struct i40iw_pble_info *pinfo; | |
1490 | u64 *pbl; | |
1491 | enum i40iw_status_code status; | |
1492 | enum i40iw_pble_level level = I40IW_LEVEL_1; | |
1493 | ||
d3749841 FL |
1494 | if (use_pbles) { |
1495 | mutex_lock(&iwdev->pbl_mutex); | |
1496 | status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt); | |
1497 | mutex_unlock(&iwdev->pbl_mutex); | |
1498 | if (status) | |
1499 | return -ENOMEM; | |
1500 | ||
1501 | iwpbl->pbl_allocated = true; | |
1502 | level = palloc->level; | |
1503 | pinfo = (level == I40IW_LEVEL_1) ? &palloc->level1 : palloc->level2.leaf; | |
1504 | pbl = (u64 *)pinfo->addr; | |
1505 | } else { | |
1506 | pbl = iwmr->pgaddrmem; | |
1507 | } | |
1508 | ||
1509 | i40iw_copy_user_pgaddrs(iwmr, pbl, level); | |
b6a529da HO |
1510 | |
1511 | if (use_pbles) | |
1512 | iwmr->pgaddrmem[0] = *pbl; | |
1513 | ||
d3749841 FL |
1514 | return 0; |
1515 | } | |
1516 | ||
1517 | /** | |
1518 | * i40iw_handle_q_mem - handle memory for qp and cq | |
1519 | * @iwdev: iwarp device | |
1520 | * @req: information for q memory management | |
1521 | * @iwpbl: pble struct | |
1522 | * @use_pbles: flag to use pble | |
1523 | */ | |
1524 | static int i40iw_handle_q_mem(struct i40iw_device *iwdev, | |
1525 | struct i40iw_mem_reg_req *req, | |
1526 | struct i40iw_pbl *iwpbl, | |
1527 | bool use_pbles) | |
1528 | { | |
1529 | struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc; | |
1530 | struct i40iw_mr *iwmr = iwpbl->iwmr; | |
1531 | struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr; | |
1532 | struct i40iw_cq_mr *cqmr = &iwpbl->cq_mr; | |
1533 | struct i40iw_hmc_pble *hmc_p; | |
1534 | u64 *arr = iwmr->pgaddrmem; | |
b6a529da | 1535 | u32 pg_size; |
d3749841 FL |
1536 | int err; |
1537 | int total; | |
b6a529da | 1538 | bool ret = true; |
d3749841 FL |
1539 | |
1540 | total = req->sq_pages + req->rq_pages + req->cq_pages; | |
f26c7c83 | 1541 | pg_size = iwmr->page_size; |
d3749841 FL |
1542 | |
1543 | err = i40iw_setup_pbles(iwdev, iwmr, use_pbles); | |
1544 | if (err) | |
1545 | return err; | |
b6a529da | 1546 | |
d3749841 FL |
1547 | if (use_pbles && (palloc->level != I40IW_LEVEL_1)) { |
1548 | i40iw_free_pble(iwdev->pble_rsrc, palloc); | |
1549 | iwpbl->pbl_allocated = false; | |
1550 | return -ENOMEM; | |
1551 | } | |
1552 | ||
1553 | if (use_pbles) | |
1554 | arr = (u64 *)palloc->level1.addr; | |
b6a529da HO |
1555 | |
1556 | if (iwmr->type == IW_MEMREG_TYPE_QP) { | |
d3749841 FL |
1557 | hmc_p = &qpmr->sq_pbl; |
1558 | qpmr->shadow = (dma_addr_t)arr[total]; | |
b6a529da | 1559 | |
d3749841 | 1560 | if (use_pbles) { |
b6a529da HO |
1561 | ret = i40iw_check_mem_contiguous(arr, req->sq_pages, pg_size); |
1562 | if (ret) | |
1563 | ret = i40iw_check_mem_contiguous(&arr[req->sq_pages], req->rq_pages, pg_size); | |
1564 | } | |
1565 | ||
1566 | if (!ret) { | |
d3749841 FL |
1567 | hmc_p->idx = palloc->level1.idx; |
1568 | hmc_p = &qpmr->rq_pbl; | |
1569 | hmc_p->idx = palloc->level1.idx + req->sq_pages; | |
1570 | } else { | |
1571 | hmc_p->addr = arr[0]; | |
1572 | hmc_p = &qpmr->rq_pbl; | |
b6a529da | 1573 | hmc_p->addr = arr[req->sq_pages]; |
d3749841 FL |
1574 | } |
1575 | } else { /* CQ */ | |
1576 | hmc_p = &cqmr->cq_pbl; | |
1577 | cqmr->shadow = (dma_addr_t)arr[total]; | |
b6a529da | 1578 | |
d3749841 | 1579 | if (use_pbles) |
b6a529da HO |
1580 | ret = i40iw_check_mem_contiguous(arr, req->cq_pages, pg_size); |
1581 | ||
1582 | if (!ret) | |
d3749841 FL |
1583 | hmc_p->idx = palloc->level1.idx; |
1584 | else | |
1585 | hmc_p->addr = arr[0]; | |
1586 | } | |
b6a529da HO |
1587 | |
1588 | if (use_pbles && ret) { | |
1589 | i40iw_free_pble(iwdev->pble_rsrc, palloc); | |
1590 | iwpbl->pbl_allocated = false; | |
1591 | } | |
1592 | ||
d3749841 FL |
1593 | return err; |
1594 | } | |
1595 | ||
b7aee855 IM |
1596 | /** |
1597 | * i40iw_hw_alloc_stag - cqp command to allocate stag | |
1598 | * @iwdev: iwarp device | |
1599 | * @iwmr: iwarp mr pointer | |
1600 | */ | |
1601 | static int i40iw_hw_alloc_stag(struct i40iw_device *iwdev, struct i40iw_mr *iwmr) | |
1602 | { | |
1603 | struct i40iw_allocate_stag_info *info; | |
1604 | struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd); | |
1605 | enum i40iw_status_code status; | |
1606 | int err = 0; | |
1607 | struct i40iw_cqp_request *cqp_request; | |
1608 | struct cqp_commands_info *cqp_info; | |
1609 | ||
1610 | cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true); | |
1611 | if (!cqp_request) | |
1612 | return -ENOMEM; | |
1613 | ||
1614 | cqp_info = &cqp_request->info; | |
1615 | info = &cqp_info->in.u.alloc_stag.info; | |
1616 | memset(info, 0, sizeof(*info)); | |
1617 | info->page_size = PAGE_SIZE; | |
1618 | info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT; | |
1619 | info->pd_id = iwpd->sc_pd.pd_id; | |
1620 | info->total_len = iwmr->length; | |
8e0e7aed | 1621 | info->remote_access = true; |
b7aee855 IM |
1622 | cqp_info->cqp_cmd = OP_ALLOC_STAG; |
1623 | cqp_info->post_sq = 1; | |
1624 | cqp_info->in.u.alloc_stag.dev = &iwdev->sc_dev; | |
1625 | cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request; | |
1626 | ||
1627 | status = i40iw_handle_cqp_op(iwdev, cqp_request); | |
1628 | if (status) { | |
1629 | err = -ENOMEM; | |
1630 | i40iw_pr_err("CQP-OP MR Reg fail"); | |
1631 | } | |
1632 | return err; | |
1633 | } | |
1634 | ||
1635 | /** | |
1636 | * i40iw_alloc_mr - register stag for fast memory registration | |
1637 | * @pd: ibpd pointer | |
1638 | * @mr_type: memory for stag registrion | |
1639 | * @max_num_sg: man number of pages | |
1640 | */ | |
1641 | static struct ib_mr *i40iw_alloc_mr(struct ib_pd *pd, | |
1642 | enum ib_mr_type mr_type, | |
1643 | u32 max_num_sg) | |
1644 | { | |
1645 | struct i40iw_pd *iwpd = to_iwpd(pd); | |
1646 | struct i40iw_device *iwdev = to_iwdev(pd->device); | |
1647 | struct i40iw_pble_alloc *palloc; | |
1648 | struct i40iw_pbl *iwpbl; | |
1649 | struct i40iw_mr *iwmr; | |
1650 | enum i40iw_status_code status; | |
1651 | u32 stag; | |
1652 | int err_code = -ENOMEM; | |
1653 | ||
1654 | iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL); | |
1655 | if (!iwmr) | |
1656 | return ERR_PTR(-ENOMEM); | |
1657 | ||
1658 | stag = i40iw_create_stag(iwdev); | |
1659 | if (!stag) { | |
1660 | err_code = -EOVERFLOW; | |
1661 | goto err; | |
1662 | } | |
6376e926 | 1663 | stag &= ~I40IW_CQPSQ_STAG_KEY_MASK; |
b7aee855 IM |
1664 | iwmr->stag = stag; |
1665 | iwmr->ibmr.rkey = stag; | |
1666 | iwmr->ibmr.lkey = stag; | |
1667 | iwmr->ibmr.pd = pd; | |
1668 | iwmr->ibmr.device = pd->device; | |
1669 | iwpbl = &iwmr->iwpbl; | |
1670 | iwpbl->iwmr = iwmr; | |
1671 | iwmr->type = IW_MEMREG_TYPE_MEM; | |
1672 | palloc = &iwpbl->pble_alloc; | |
1673 | iwmr->page_cnt = max_num_sg; | |
1674 | mutex_lock(&iwdev->pbl_mutex); | |
1675 | status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt); | |
1676 | mutex_unlock(&iwdev->pbl_mutex); | |
ee23abd7 | 1677 | if (status) |
b7aee855 IM |
1678 | goto err1; |
1679 | ||
1680 | if (palloc->level != I40IW_LEVEL_1) | |
1681 | goto err2; | |
1682 | err_code = i40iw_hw_alloc_stag(iwdev, iwmr); | |
1683 | if (err_code) | |
1684 | goto err2; | |
1685 | iwpbl->pbl_allocated = true; | |
1686 | i40iw_add_pdusecount(iwpd); | |
1687 | return &iwmr->ibmr; | |
1688 | err2: | |
1689 | i40iw_free_pble(iwdev->pble_rsrc, palloc); | |
1690 | err1: | |
1691 | i40iw_free_stag(iwdev, stag); | |
1692 | err: | |
1693 | kfree(iwmr); | |
1694 | return ERR_PTR(err_code); | |
1695 | } | |
1696 | ||
1697 | /** | |
1698 | * i40iw_set_page - populate pbl list for fmr | |
1699 | * @ibmr: ib mem to access iwarp mr pointer | |
1700 | * @addr: page dma address fro pbl list | |
1701 | */ | |
1702 | static int i40iw_set_page(struct ib_mr *ibmr, u64 addr) | |
1703 | { | |
1704 | struct i40iw_mr *iwmr = to_iwmr(ibmr); | |
1705 | struct i40iw_pbl *iwpbl = &iwmr->iwpbl; | |
1706 | struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc; | |
1707 | u64 *pbl; | |
1708 | ||
1709 | if (unlikely(iwmr->npages == iwmr->page_cnt)) | |
1710 | return -ENOMEM; | |
1711 | ||
1712 | pbl = (u64 *)palloc->level1.addr; | |
1713 | pbl[iwmr->npages++] = cpu_to_le64(addr); | |
1714 | return 0; | |
1715 | } | |
1716 | ||
1717 | /** | |
1718 | * i40iw_map_mr_sg - map of sg list for fmr | |
1719 | * @ibmr: ib mem to access iwarp mr pointer | |
1720 | * @sg: scatter gather list for fmr | |
1721 | * @sg_nents: number of sg pages | |
1722 | */ | |
ff2ba993 | 1723 | static int i40iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, |
9aa8b321 | 1724 | int sg_nents, unsigned int *sg_offset) |
b7aee855 IM |
1725 | { |
1726 | struct i40iw_mr *iwmr = to_iwmr(ibmr); | |
1727 | ||
1728 | iwmr->npages = 0; | |
ff2ba993 | 1729 | return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, i40iw_set_page); |
b7aee855 IM |
1730 | } |
1731 | ||
c2b75ef7 IM |
1732 | /** |
1733 | * i40iw_drain_sq - drain the send queue | |
1734 | * @ibqp: ib qp pointer | |
1735 | */ | |
1736 | static void i40iw_drain_sq(struct ib_qp *ibqp) | |
1737 | { | |
1738 | struct i40iw_qp *iwqp = to_iwqp(ibqp); | |
1739 | struct i40iw_sc_qp *qp = &iwqp->sc_qp; | |
1740 | ||
1741 | if (I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring)) | |
1742 | wait_for_completion(&iwqp->sq_drained); | |
1743 | } | |
1744 | ||
1745 | /** | |
1746 | * i40iw_drain_rq - drain the receive queue | |
1747 | * @ibqp: ib qp pointer | |
1748 | */ | |
1749 | static void i40iw_drain_rq(struct ib_qp *ibqp) | |
1750 | { | |
1751 | struct i40iw_qp *iwqp = to_iwqp(ibqp); | |
1752 | struct i40iw_sc_qp *qp = &iwqp->sc_qp; | |
1753 | ||
1754 | if (I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring)) | |
1755 | wait_for_completion(&iwqp->rq_drained); | |
1756 | } | |
1757 | ||
d3749841 FL |
1758 | /** |
1759 | * i40iw_hwreg_mr - send cqp command for memory registration | |
1760 | * @iwdev: iwarp device | |
1761 | * @iwmr: iwarp mr pointer | |
1762 | * @access: access for MR | |
1763 | */ | |
1764 | static int i40iw_hwreg_mr(struct i40iw_device *iwdev, | |
1765 | struct i40iw_mr *iwmr, | |
1766 | u16 access) | |
1767 | { | |
1768 | struct i40iw_pbl *iwpbl = &iwmr->iwpbl; | |
1769 | struct i40iw_reg_ns_stag_info *stag_info; | |
1770 | struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd); | |
1771 | struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc; | |
1772 | enum i40iw_status_code status; | |
1773 | int err = 0; | |
1774 | struct i40iw_cqp_request *cqp_request; | |
1775 | struct cqp_commands_info *cqp_info; | |
1776 | ||
1777 | cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true); | |
1778 | if (!cqp_request) | |
1779 | return -ENOMEM; | |
1780 | ||
1781 | cqp_info = &cqp_request->info; | |
1782 | stag_info = &cqp_info->in.u.mr_reg_non_shared.info; | |
1783 | memset(stag_info, 0, sizeof(*stag_info)); | |
1784 | stag_info->va = (void *)(unsigned long)iwpbl->user_base; | |
1785 | stag_info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT; | |
1786 | stag_info->stag_key = (u8)iwmr->stag; | |
1787 | stag_info->total_len = iwmr->length; | |
1788 | stag_info->access_rights = access; | |
1789 | stag_info->pd_id = iwpd->sc_pd.pd_id; | |
1790 | stag_info->addr_type = I40IW_ADDR_TYPE_VA_BASED; | |
f26c7c83 | 1791 | stag_info->page_size = iwmr->page_size; |
d3749841 | 1792 | |
b6a529da | 1793 | if (iwpbl->pbl_allocated) { |
d3749841 FL |
1794 | if (palloc->level == I40IW_LEVEL_1) { |
1795 | stag_info->first_pm_pbl_index = palloc->level1.idx; | |
1796 | stag_info->chunk_size = 1; | |
1797 | } else { | |
1798 | stag_info->first_pm_pbl_index = palloc->level2.root.idx; | |
1799 | stag_info->chunk_size = 3; | |
1800 | } | |
1801 | } else { | |
1802 | stag_info->reg_addr_pa = iwmr->pgaddrmem[0]; | |
1803 | } | |
1804 | ||
1805 | cqp_info->cqp_cmd = OP_MR_REG_NON_SHARED; | |
1806 | cqp_info->post_sq = 1; | |
1807 | cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->sc_dev; | |
1808 | cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request; | |
1809 | ||
1810 | status = i40iw_handle_cqp_op(iwdev, cqp_request); | |
1811 | if (status) { | |
1812 | err = -ENOMEM; | |
1813 | i40iw_pr_err("CQP-OP MR Reg fail"); | |
1814 | } | |
1815 | return err; | |
1816 | } | |
1817 | ||
1818 | /** | |
1819 | * i40iw_reg_user_mr - Register a user memory region | |
1820 | * @pd: ptr of pd | |
1821 | * @start: virtual start address | |
1822 | * @length: length of mr | |
1823 | * @virt: virtual address | |
1824 | * @acc: access of mr | |
1825 | * @udata: user data | |
1826 | */ | |
1827 | static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd, | |
1828 | u64 start, | |
1829 | u64 length, | |
1830 | u64 virt, | |
1831 | int acc, | |
1832 | struct ib_udata *udata) | |
1833 | { | |
1834 | struct i40iw_pd *iwpd = to_iwpd(pd); | |
1835 | struct i40iw_device *iwdev = to_iwdev(pd->device); | |
1836 | struct i40iw_ucontext *ucontext; | |
1837 | struct i40iw_pble_alloc *palloc; | |
1838 | struct i40iw_pbl *iwpbl; | |
1839 | struct i40iw_mr *iwmr; | |
1840 | struct ib_umem *region; | |
1841 | struct i40iw_mem_reg_req req; | |
6b900365 | 1842 | u64 pbl_depth = 0; |
d3749841 FL |
1843 | u32 stag = 0; |
1844 | u16 access; | |
6b900365 | 1845 | u64 region_length; |
d3749841 FL |
1846 | bool use_pbles = false; |
1847 | unsigned long flags; | |
1848 | int err = -ENOSYS; | |
b6a529da | 1849 | int ret; |
f26c7c83 | 1850 | int pg_shift; |
d3749841 | 1851 | |
d5965934 MI |
1852 | if (iwdev->closing) |
1853 | return ERR_PTR(-ENODEV); | |
d3749841 | 1854 | |
6b900365 IM |
1855 | if (length > I40IW_MAX_MR_SIZE) |
1856 | return ERR_PTR(-EINVAL); | |
d3749841 FL |
1857 | region = ib_umem_get(pd->uobject->context, start, length, acc, 0); |
1858 | if (IS_ERR(region)) | |
1859 | return (struct ib_mr *)region; | |
1860 | ||
1861 | if (ib_copy_from_udata(&req, udata, sizeof(req))) { | |
1862 | ib_umem_release(region); | |
1863 | return ERR_PTR(-EFAULT); | |
1864 | } | |
1865 | ||
1866 | iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL); | |
1867 | if (!iwmr) { | |
1868 | ib_umem_release(region); | |
1869 | return ERR_PTR(-ENOMEM); | |
1870 | } | |
1871 | ||
1872 | iwpbl = &iwmr->iwpbl; | |
1873 | iwpbl->iwmr = iwmr; | |
1874 | iwmr->region = region; | |
1875 | iwmr->ibmr.pd = pd; | |
1876 | iwmr->ibmr.device = pd->device; | |
1877 | ucontext = to_ucontext(pd->uobject->context); | |
f26c7c83 | 1878 | |
3e7e1193 | 1879 | iwmr->page_size = PAGE_SIZE; |
f26c7c83 HO |
1880 | iwmr->page_msk = PAGE_MASK; |
1881 | ||
1882 | if (region->hugetlb && (req.reg_type == IW_MEMREG_TYPE_MEM)) | |
1883 | i40iw_set_hugetlb_values(start, iwmr); | |
1884 | ||
1885 | region_length = region->length + (start & (iwmr->page_size - 1)); | |
1886 | pg_shift = ffs(iwmr->page_size) - 1; | |
1887 | pbl_depth = region_length >> pg_shift; | |
1888 | pbl_depth += (region_length & (iwmr->page_size - 1)) ? 1 : 0; | |
d3749841 FL |
1889 | iwmr->length = region->length; |
1890 | ||
1891 | iwpbl->user_base = virt; | |
1892 | palloc = &iwpbl->pble_alloc; | |
1893 | ||
1894 | iwmr->type = req.reg_type; | |
6b900365 | 1895 | iwmr->page_cnt = (u32)pbl_depth; |
d3749841 FL |
1896 | |
1897 | switch (req.reg_type) { | |
1898 | case IW_MEMREG_TYPE_QP: | |
1899 | use_pbles = ((req.sq_pages + req.rq_pages) > 2); | |
1900 | err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles); | |
1901 | if (err) | |
1902 | goto error; | |
1903 | spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags); | |
1904 | list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list); | |
a75895b1 | 1905 | iwpbl->on_list = true; |
d3749841 FL |
1906 | spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags); |
1907 | break; | |
1908 | case IW_MEMREG_TYPE_CQ: | |
1909 | use_pbles = (req.cq_pages > 1); | |
1910 | err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles); | |
1911 | if (err) | |
1912 | goto error; | |
1913 | ||
1914 | spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags); | |
1915 | list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list); | |
a75895b1 | 1916 | iwpbl->on_list = true; |
d3749841 FL |
1917 | spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags); |
1918 | break; | |
1919 | case IW_MEMREG_TYPE_MEM: | |
b6a529da | 1920 | use_pbles = (iwmr->page_cnt != 1); |
d3749841 FL |
1921 | access = I40IW_ACCESS_FLAGS_LOCALREAD; |
1922 | ||
d3749841 FL |
1923 | err = i40iw_setup_pbles(iwdev, iwmr, use_pbles); |
1924 | if (err) | |
1925 | goto error; | |
1926 | ||
b6a529da | 1927 | if (use_pbles) { |
f26c7c83 | 1928 | ret = i40iw_check_mr_contiguous(palloc, iwmr->page_size); |
b6a529da HO |
1929 | if (ret) { |
1930 | i40iw_free_pble(iwdev->pble_rsrc, palloc); | |
1931 | iwpbl->pbl_allocated = false; | |
1932 | } | |
1933 | } | |
1934 | ||
d3749841 FL |
1935 | access |= i40iw_get_user_access(acc); |
1936 | stag = i40iw_create_stag(iwdev); | |
1937 | if (!stag) { | |
1938 | err = -ENOMEM; | |
1939 | goto error; | |
1940 | } | |
1941 | ||
1942 | iwmr->stag = stag; | |
1943 | iwmr->ibmr.rkey = stag; | |
1944 | iwmr->ibmr.lkey = stag; | |
1945 | ||
1946 | err = i40iw_hwreg_mr(iwdev, iwmr, access); | |
1947 | if (err) { | |
1948 | i40iw_free_stag(iwdev, stag); | |
1949 | goto error; | |
1950 | } | |
f26c7c83 | 1951 | |
d3749841 FL |
1952 | break; |
1953 | default: | |
1954 | goto error; | |
1955 | } | |
1956 | ||
1957 | iwmr->type = req.reg_type; | |
1958 | if (req.reg_type == IW_MEMREG_TYPE_MEM) | |
1959 | i40iw_add_pdusecount(iwpd); | |
1960 | return &iwmr->ibmr; | |
1961 | ||
1962 | error: | |
b6a529da | 1963 | if (palloc->level != I40IW_LEVEL_0 && iwpbl->pbl_allocated) |
d3749841 FL |
1964 | i40iw_free_pble(iwdev->pble_rsrc, palloc); |
1965 | ib_umem_release(region); | |
1966 | kfree(iwmr); | |
1967 | return ERR_PTR(err); | |
1968 | } | |
1969 | ||
1970 | /** | |
1971 | * i40iw_reg_phys_mr - register kernel physical memory | |
1972 | * @pd: ibpd pointer | |
1973 | * @addr: physical address of memory to register | |
1974 | * @size: size of memory to register | |
1975 | * @acc: Access rights | |
1976 | * @iova_start: start of virtual address for physical buffers | |
1977 | */ | |
1978 | struct ib_mr *i40iw_reg_phys_mr(struct ib_pd *pd, | |
1979 | u64 addr, | |
1980 | u64 size, | |
1981 | int acc, | |
1982 | u64 *iova_start) | |
1983 | { | |
1984 | struct i40iw_pd *iwpd = to_iwpd(pd); | |
1985 | struct i40iw_device *iwdev = to_iwdev(pd->device); | |
1986 | struct i40iw_pbl *iwpbl; | |
1987 | struct i40iw_mr *iwmr; | |
1988 | enum i40iw_status_code status; | |
1989 | u32 stag; | |
1990 | u16 access = I40IW_ACCESS_FLAGS_LOCALREAD; | |
1991 | int ret; | |
1992 | ||
1993 | iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL); | |
1994 | if (!iwmr) | |
1995 | return ERR_PTR(-ENOMEM); | |
1996 | iwmr->ibmr.pd = pd; | |
1997 | iwmr->ibmr.device = pd->device; | |
1998 | iwpbl = &iwmr->iwpbl; | |
1999 | iwpbl->iwmr = iwmr; | |
2000 | iwmr->type = IW_MEMREG_TYPE_MEM; | |
2001 | iwpbl->user_base = *iova_start; | |
2002 | stag = i40iw_create_stag(iwdev); | |
2003 | if (!stag) { | |
2004 | ret = -EOVERFLOW; | |
2005 | goto err; | |
2006 | } | |
2007 | access |= i40iw_get_user_access(acc); | |
2008 | iwmr->stag = stag; | |
2009 | iwmr->ibmr.rkey = stag; | |
2010 | iwmr->ibmr.lkey = stag; | |
2011 | iwmr->page_cnt = 1; | |
2012 | iwmr->pgaddrmem[0] = addr; | |
342c387b | 2013 | iwmr->length = size; |
d3749841 FL |
2014 | status = i40iw_hwreg_mr(iwdev, iwmr, access); |
2015 | if (status) { | |
2016 | i40iw_free_stag(iwdev, stag); | |
2017 | ret = -ENOMEM; | |
2018 | goto err; | |
2019 | } | |
2020 | ||
2021 | i40iw_add_pdusecount(iwpd); | |
2022 | return &iwmr->ibmr; | |
2023 | err: | |
2024 | kfree(iwmr); | |
2025 | return ERR_PTR(ret); | |
2026 | } | |
2027 | ||
2028 | /** | |
2029 | * i40iw_get_dma_mr - register physical mem | |
2030 | * @pd: ptr of pd | |
2031 | * @acc: access for memory | |
2032 | */ | |
2033 | static struct ib_mr *i40iw_get_dma_mr(struct ib_pd *pd, int acc) | |
2034 | { | |
2035 | u64 kva = 0; | |
2036 | ||
342c387b | 2037 | return i40iw_reg_phys_mr(pd, 0, 0, acc, &kva); |
d3749841 FL |
2038 | } |
2039 | ||
2040 | /** | |
2041 | * i40iw_del_mem_list - Deleting pbl list entries for CQ/QP | |
2042 | * @iwmr: iwmr for IB's user page addresses | |
2043 | * @ucontext: ptr to user context | |
2044 | */ | |
2045 | static void i40iw_del_memlist(struct i40iw_mr *iwmr, | |
2046 | struct i40iw_ucontext *ucontext) | |
2047 | { | |
2048 | struct i40iw_pbl *iwpbl = &iwmr->iwpbl; | |
2049 | unsigned long flags; | |
2050 | ||
2051 | switch (iwmr->type) { | |
2052 | case IW_MEMREG_TYPE_CQ: | |
2053 | spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags); | |
a75895b1 AB |
2054 | if (iwpbl->on_list) { |
2055 | iwpbl->on_list = false; | |
d3749841 | 2056 | list_del(&iwpbl->list); |
a75895b1 | 2057 | } |
d3749841 FL |
2058 | spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags); |
2059 | break; | |
2060 | case IW_MEMREG_TYPE_QP: | |
2061 | spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags); | |
a75895b1 AB |
2062 | if (iwpbl->on_list) { |
2063 | iwpbl->on_list = false; | |
d3749841 | 2064 | list_del(&iwpbl->list); |
a75895b1 | 2065 | } |
d3749841 FL |
2066 | spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags); |
2067 | break; | |
2068 | default: | |
2069 | break; | |
2070 | } | |
2071 | } | |
2072 | ||
2073 | /** | |
2074 | * i40iw_dereg_mr - deregister mr | |
2075 | * @ib_mr: mr ptr for dereg | |
2076 | */ | |
2077 | static int i40iw_dereg_mr(struct ib_mr *ib_mr) | |
2078 | { | |
2079 | struct ib_pd *ibpd = ib_mr->pd; | |
2080 | struct i40iw_pd *iwpd = to_iwpd(ibpd); | |
2081 | struct i40iw_mr *iwmr = to_iwmr(ib_mr); | |
2082 | struct i40iw_device *iwdev = to_iwdev(ib_mr->device); | |
2083 | enum i40iw_status_code status; | |
2084 | struct i40iw_dealloc_stag_info *info; | |
2085 | struct i40iw_pbl *iwpbl = &iwmr->iwpbl; | |
2086 | struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc; | |
2087 | struct i40iw_cqp_request *cqp_request; | |
2088 | struct cqp_commands_info *cqp_info; | |
2089 | u32 stag_idx; | |
2090 | ||
2091 | if (iwmr->region) | |
2092 | ib_umem_release(iwmr->region); | |
2093 | ||
2094 | if (iwmr->type != IW_MEMREG_TYPE_MEM) { | |
2095 | if (ibpd->uobject) { | |
2096 | struct i40iw_ucontext *ucontext; | |
2097 | ||
2098 | ucontext = to_ucontext(ibpd->uobject->context); | |
2099 | i40iw_del_memlist(iwmr, ucontext); | |
2100 | } | |
af56e53c | 2101 | if (iwpbl->pbl_allocated && iwmr->type != IW_MEMREG_TYPE_QP) |
d3749841 | 2102 | i40iw_free_pble(iwdev->pble_rsrc, palloc); |
433c5813 | 2103 | kfree(iwmr); |
d3749841 FL |
2104 | return 0; |
2105 | } | |
2106 | ||
2107 | cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true); | |
2108 | if (!cqp_request) | |
2109 | return -ENOMEM; | |
2110 | ||
2111 | cqp_info = &cqp_request->info; | |
2112 | info = &cqp_info->in.u.dealloc_stag.info; | |
2113 | memset(info, 0, sizeof(*info)); | |
2114 | ||
2115 | info->pd_id = cpu_to_le32(iwpd->sc_pd.pd_id & 0x00007fff); | |
2116 | info->stag_idx = RS_64_1(ib_mr->rkey, I40IW_CQPSQ_STAG_IDX_SHIFT); | |
2117 | stag_idx = info->stag_idx; | |
2118 | info->mr = true; | |
2119 | if (iwpbl->pbl_allocated) | |
2120 | info->dealloc_pbl = true; | |
2121 | ||
2122 | cqp_info->cqp_cmd = OP_DEALLOC_STAG; | |
2123 | cqp_info->post_sq = 1; | |
2124 | cqp_info->in.u.dealloc_stag.dev = &iwdev->sc_dev; | |
2125 | cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request; | |
2126 | status = i40iw_handle_cqp_op(iwdev, cqp_request); | |
2127 | if (status) | |
2128 | i40iw_pr_err("CQP-OP dealloc failed for stag_idx = 0x%x\n", stag_idx); | |
2129 | i40iw_rem_pdusecount(iwpd, iwdev); | |
2130 | i40iw_free_stag(iwdev, iwmr->stag); | |
2131 | if (iwpbl->pbl_allocated) | |
2132 | i40iw_free_pble(iwdev->pble_rsrc, palloc); | |
2133 | kfree(iwmr); | |
2134 | return 0; | |
2135 | } | |
2136 | ||
2137 | /** | |
2138 | * i40iw_show_rev | |
2139 | */ | |
2140 | static ssize_t i40iw_show_rev(struct device *dev, | |
2141 | struct device_attribute *attr, char *buf) | |
2142 | { | |
2143 | struct i40iw_ib_device *iwibdev = container_of(dev, | |
2144 | struct i40iw_ib_device, | |
2145 | ibdev.dev); | |
2146 | u32 hw_rev = iwibdev->iwdev->sc_dev.hw_rev; | |
2147 | ||
2148 | return sprintf(buf, "%x\n", hw_rev); | |
2149 | } | |
2150 | ||
d3749841 FL |
2151 | /** |
2152 | * i40iw_show_hca | |
2153 | */ | |
2154 | static ssize_t i40iw_show_hca(struct device *dev, | |
2155 | struct device_attribute *attr, char *buf) | |
2156 | { | |
2157 | return sprintf(buf, "I40IW\n"); | |
2158 | } | |
2159 | ||
2160 | /** | |
2161 | * i40iw_show_board | |
2162 | */ | |
2163 | static ssize_t i40iw_show_board(struct device *dev, | |
2164 | struct device_attribute *attr, | |
2165 | char *buf) | |
2166 | { | |
2167 | return sprintf(buf, "%.*s\n", 32, "I40IW Board ID"); | |
2168 | } | |
2169 | ||
2170 | static DEVICE_ATTR(hw_rev, S_IRUGO, i40iw_show_rev, NULL); | |
d3749841 FL |
2171 | static DEVICE_ATTR(hca_type, S_IRUGO, i40iw_show_hca, NULL); |
2172 | static DEVICE_ATTR(board_id, S_IRUGO, i40iw_show_board, NULL); | |
2173 | ||
2174 | static struct device_attribute *i40iw_dev_attributes[] = { | |
2175 | &dev_attr_hw_rev, | |
d3749841 FL |
2176 | &dev_attr_hca_type, |
2177 | &dev_attr_board_id | |
2178 | }; | |
2179 | ||
2180 | /** | |
2181 | * i40iw_copy_sg_list - copy sg list for qp | |
2182 | * @sg_list: copied into sg_list | |
2183 | * @sgl: copy from sgl | |
2184 | * @num_sges: count of sg entries | |
2185 | */ | |
2186 | static void i40iw_copy_sg_list(struct i40iw_sge *sg_list, struct ib_sge *sgl, int num_sges) | |
2187 | { | |
2188 | unsigned int i; | |
2189 | ||
2190 | for (i = 0; (i < num_sges) && (i < I40IW_MAX_WQ_FRAGMENT_COUNT); i++) { | |
2191 | sg_list[i].tag_off = sgl[i].addr; | |
2192 | sg_list[i].len = sgl[i].length; | |
2193 | sg_list[i].stag = sgl[i].lkey; | |
2194 | } | |
2195 | } | |
2196 | ||
2197 | /** | |
2198 | * i40iw_post_send - kernel application wr | |
2199 | * @ibqp: qp ptr for wr | |
2200 | * @ib_wr: work request ptr | |
2201 | * @bad_wr: return of bad wr if err | |
2202 | */ | |
2203 | static int i40iw_post_send(struct ib_qp *ibqp, | |
d34ac5cd BVA |
2204 | const struct ib_send_wr *ib_wr, |
2205 | const struct ib_send_wr **bad_wr) | |
d3749841 FL |
2206 | { |
2207 | struct i40iw_qp *iwqp; | |
2208 | struct i40iw_qp_uk *ukqp; | |
2209 | struct i40iw_post_sq_info info; | |
2210 | enum i40iw_status_code ret; | |
2211 | int err = 0; | |
2212 | unsigned long flags; | |
b7aee855 | 2213 | bool inv_stag; |
d3749841 FL |
2214 | |
2215 | iwqp = (struct i40iw_qp *)ibqp; | |
2216 | ukqp = &iwqp->sc_qp.qp_uk; | |
2217 | ||
2218 | spin_lock_irqsave(&iwqp->lock, flags); | |
40837273 SS |
2219 | |
2220 | if (iwqp->flush_issued) { | |
2221 | err = -EINVAL; | |
2222 | goto out; | |
2223 | } | |
2224 | ||
d3749841 | 2225 | while (ib_wr) { |
b7aee855 | 2226 | inv_stag = false; |
d3749841 FL |
2227 | memset(&info, 0, sizeof(info)); |
2228 | info.wr_id = (u64)(ib_wr->wr_id); | |
2229 | if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all) | |
2230 | info.signaled = true; | |
2231 | if (ib_wr->send_flags & IB_SEND_FENCE) | |
2232 | info.read_fence = true; | |
2233 | ||
2234 | switch (ib_wr->opcode) { | |
2235 | case IB_WR_SEND: | |
b7aee855 IM |
2236 | /* fall-through */ |
2237 | case IB_WR_SEND_WITH_INV: | |
2238 | if (ib_wr->opcode == IB_WR_SEND) { | |
2239 | if (ib_wr->send_flags & IB_SEND_SOLICITED) | |
2240 | info.op_type = I40IW_OP_TYPE_SEND_SOL; | |
2241 | else | |
2242 | info.op_type = I40IW_OP_TYPE_SEND; | |
2243 | } else { | |
2244 | if (ib_wr->send_flags & IB_SEND_SOLICITED) | |
2245 | info.op_type = I40IW_OP_TYPE_SEND_SOL_INV; | |
2246 | else | |
2247 | info.op_type = I40IW_OP_TYPE_SEND_INV; | |
2248 | } | |
d3749841 FL |
2249 | |
2250 | if (ib_wr->send_flags & IB_SEND_INLINE) { | |
2251 | info.op.inline_send.data = (void *)(unsigned long)ib_wr->sg_list[0].addr; | |
2252 | info.op.inline_send.len = ib_wr->sg_list[0].length; | |
b7aee855 | 2253 | ret = ukqp->ops.iw_inline_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false); |
d3749841 FL |
2254 | } else { |
2255 | info.op.send.num_sges = ib_wr->num_sge; | |
2256 | info.op.send.sg_list = (struct i40iw_sge *)ib_wr->sg_list; | |
b7aee855 | 2257 | ret = ukqp->ops.iw_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false); |
d3749841 FL |
2258 | } |
2259 | ||
fe5d6e62 SS |
2260 | if (ret) { |
2261 | if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED) | |
2262 | err = -ENOMEM; | |
2263 | else | |
2264 | err = -EINVAL; | |
2265 | } | |
d3749841 FL |
2266 | break; |
2267 | case IB_WR_RDMA_WRITE: | |
2268 | info.op_type = I40IW_OP_TYPE_RDMA_WRITE; | |
2269 | ||
2270 | if (ib_wr->send_flags & IB_SEND_INLINE) { | |
2271 | info.op.inline_rdma_write.data = (void *)(unsigned long)ib_wr->sg_list[0].addr; | |
2272 | info.op.inline_rdma_write.len = ib_wr->sg_list[0].length; | |
2273 | info.op.inline_rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr; | |
2274 | info.op.inline_rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey; | |
d3749841 FL |
2275 | ret = ukqp->ops.iw_inline_rdma_write(ukqp, &info, false); |
2276 | } else { | |
2277 | info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list; | |
2278 | info.op.rdma_write.num_lo_sges = ib_wr->num_sge; | |
2279 | info.op.rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr; | |
2280 | info.op.rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey; | |
d3749841 FL |
2281 | ret = ukqp->ops.iw_rdma_write(ukqp, &info, false); |
2282 | } | |
2283 | ||
fe5d6e62 SS |
2284 | if (ret) { |
2285 | if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED) | |
2286 | err = -ENOMEM; | |
2287 | else | |
2288 | err = -EINVAL; | |
2289 | } | |
d3749841 | 2290 | break; |
b7aee855 IM |
2291 | case IB_WR_RDMA_READ_WITH_INV: |
2292 | inv_stag = true; | |
2293 | /* fall-through*/ | |
d3749841 | 2294 | case IB_WR_RDMA_READ: |
6c2f7619 SS |
2295 | if (ib_wr->num_sge > I40IW_MAX_SGE_RD) { |
2296 | err = -EINVAL; | |
2297 | break; | |
2298 | } | |
d3749841 FL |
2299 | info.op_type = I40IW_OP_TYPE_RDMA_READ; |
2300 | info.op.rdma_read.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr; | |
2301 | info.op.rdma_read.rem_addr.stag = rdma_wr(ib_wr)->rkey; | |
d3749841 FL |
2302 | info.op.rdma_read.lo_addr.tag_off = ib_wr->sg_list->addr; |
2303 | info.op.rdma_read.lo_addr.stag = ib_wr->sg_list->lkey; | |
2304 | info.op.rdma_read.lo_addr.len = ib_wr->sg_list->length; | |
b7aee855 | 2305 | ret = ukqp->ops.iw_rdma_read(ukqp, &info, inv_stag, false); |
fe5d6e62 SS |
2306 | if (ret) { |
2307 | if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED) | |
2308 | err = -ENOMEM; | |
2309 | else | |
2310 | err = -EINVAL; | |
2311 | } | |
d3749841 | 2312 | break; |
b7aee855 IM |
2313 | case IB_WR_LOCAL_INV: |
2314 | info.op_type = I40IW_OP_TYPE_INV_STAG; | |
2315 | info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey; | |
2316 | ret = ukqp->ops.iw_stag_local_invalidate(ukqp, &info, true); | |
2317 | if (ret) | |
fe5d6e62 | 2318 | err = -ENOMEM; |
b7aee855 IM |
2319 | break; |
2320 | case IB_WR_REG_MR: | |
2321 | { | |
2322 | struct i40iw_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr); | |
b7aee855 IM |
2323 | int flags = reg_wr(ib_wr)->access; |
2324 | struct i40iw_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc; | |
2325 | struct i40iw_sc_dev *dev = &iwqp->iwdev->sc_dev; | |
2326 | struct i40iw_fast_reg_stag_info info; | |
2327 | ||
7748e499 | 2328 | memset(&info, 0, sizeof(info)); |
b7aee855 IM |
2329 | info.access_rights = I40IW_ACCESS_FLAGS_LOCALREAD; |
2330 | info.access_rights |= i40iw_get_user_access(flags); | |
2331 | info.stag_key = reg_wr(ib_wr)->key & 0xff; | |
2332 | info.stag_idx = reg_wr(ib_wr)->key >> 8; | |
e6779185 | 2333 | info.page_size = reg_wr(ib_wr)->mr->page_size; |
b7aee855 IM |
2334 | info.wr_id = ib_wr->wr_id; |
2335 | ||
2336 | info.addr_type = I40IW_ADDR_TYPE_VA_BASED; | |
2337 | info.va = (void *)(uintptr_t)iwmr->ibmr.iova; | |
2338 | info.total_len = iwmr->ibmr.length; | |
7748e499 | 2339 | info.reg_addr_pa = *(u64 *)palloc->level1.addr; |
b7aee855 IM |
2340 | info.first_pm_pbl_index = palloc->level1.idx; |
2341 | info.local_fence = ib_wr->send_flags & IB_SEND_FENCE; | |
2342 | info.signaled = ib_wr->send_flags & IB_SEND_SIGNALED; | |
2343 | ||
7748e499 SS |
2344 | if (iwmr->npages > I40IW_MIN_PAGES_PER_FMR) |
2345 | info.chunk_size = 1; | |
2346 | ||
b7aee855 IM |
2347 | ret = dev->iw_priv_qp_ops->iw_mr_fast_register(&iwqp->sc_qp, &info, true); |
2348 | if (ret) | |
fe5d6e62 | 2349 | err = -ENOMEM; |
b7aee855 IM |
2350 | break; |
2351 | } | |
d3749841 FL |
2352 | default: |
2353 | err = -EINVAL; | |
2354 | i40iw_pr_err(" upost_send bad opcode = 0x%x\n", | |
2355 | ib_wr->opcode); | |
2356 | break; | |
2357 | } | |
2358 | ||
2359 | if (err) | |
2360 | break; | |
2361 | ib_wr = ib_wr->next; | |
2362 | } | |
2363 | ||
40837273 | 2364 | out: |
d3749841 FL |
2365 | if (err) |
2366 | *bad_wr = ib_wr; | |
2367 | else | |
2368 | ukqp->ops.iw_qp_post_wr(ukqp); | |
2369 | spin_unlock_irqrestore(&iwqp->lock, flags); | |
2370 | ||
2371 | return err; | |
2372 | } | |
2373 | ||
2374 | /** | |
2375 | * i40iw_post_recv - post receive wr for kernel application | |
2376 | * @ibqp: ib qp pointer | |
2377 | * @ib_wr: work request for receive | |
2378 | * @bad_wr: bad wr caused an error | |
2379 | */ | |
d34ac5cd BVA |
2380 | static int i40iw_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *ib_wr, |
2381 | const struct ib_recv_wr **bad_wr) | |
d3749841 FL |
2382 | { |
2383 | struct i40iw_qp *iwqp; | |
2384 | struct i40iw_qp_uk *ukqp; | |
2385 | struct i40iw_post_rq_info post_recv; | |
2386 | struct i40iw_sge sg_list[I40IW_MAX_WQ_FRAGMENT_COUNT]; | |
2387 | enum i40iw_status_code ret = 0; | |
2388 | unsigned long flags; | |
fe5d6e62 | 2389 | int err = 0; |
d3749841 FL |
2390 | |
2391 | iwqp = (struct i40iw_qp *)ibqp; | |
2392 | ukqp = &iwqp->sc_qp.qp_uk; | |
2393 | ||
2394 | memset(&post_recv, 0, sizeof(post_recv)); | |
2395 | spin_lock_irqsave(&iwqp->lock, flags); | |
40837273 SS |
2396 | |
2397 | if (iwqp->flush_issued) { | |
2398 | err = -EINVAL; | |
2399 | goto out; | |
2400 | } | |
2401 | ||
d3749841 FL |
2402 | while (ib_wr) { |
2403 | post_recv.num_sges = ib_wr->num_sge; | |
2404 | post_recv.wr_id = ib_wr->wr_id; | |
2405 | i40iw_copy_sg_list(sg_list, ib_wr->sg_list, ib_wr->num_sge); | |
2406 | post_recv.sg_list = sg_list; | |
2407 | ret = ukqp->ops.iw_post_receive(ukqp, &post_recv); | |
2408 | if (ret) { | |
2409 | i40iw_pr_err(" post_recv err %d\n", ret); | |
fe5d6e62 SS |
2410 | if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED) |
2411 | err = -ENOMEM; | |
2412 | else | |
2413 | err = -EINVAL; | |
d3749841 FL |
2414 | *bad_wr = ib_wr; |
2415 | goto out; | |
2416 | } | |
2417 | ib_wr = ib_wr->next; | |
2418 | } | |
2419 | out: | |
2420 | spin_unlock_irqrestore(&iwqp->lock, flags); | |
fe5d6e62 | 2421 | return err; |
d3749841 FL |
2422 | } |
2423 | ||
2424 | /** | |
2425 | * i40iw_poll_cq - poll cq for completion (kernel apps) | |
2426 | * @ibcq: cq to poll | |
2427 | * @num_entries: number of entries to poll | |
2428 | * @entry: wr of entry completed | |
2429 | */ | |
2430 | static int i40iw_poll_cq(struct ib_cq *ibcq, | |
2431 | int num_entries, | |
2432 | struct ib_wc *entry) | |
2433 | { | |
2434 | struct i40iw_cq *iwcq; | |
2435 | int cqe_count = 0; | |
2436 | struct i40iw_cq_poll_info cq_poll_info; | |
2437 | enum i40iw_status_code ret; | |
2438 | struct i40iw_cq_uk *ukcq; | |
2439 | struct i40iw_sc_qp *qp; | |
c2b75ef7 | 2440 | struct i40iw_qp *iwqp; |
d3749841 FL |
2441 | unsigned long flags; |
2442 | ||
2443 | iwcq = (struct i40iw_cq *)ibcq; | |
2444 | ukcq = &iwcq->sc_cq.cq_uk; | |
2445 | ||
2446 | spin_lock_irqsave(&iwcq->lock, flags); | |
2447 | while (cqe_count < num_entries) { | |
b54143be | 2448 | ret = ukcq->ops.iw_cq_poll_completion(ukcq, &cq_poll_info); |
d3749841 FL |
2449 | if (ret == I40IW_ERR_QUEUE_EMPTY) { |
2450 | break; | |
f8a4e76c TN |
2451 | } else if (ret == I40IW_ERR_QUEUE_DESTROYED) { |
2452 | continue; | |
d3749841 FL |
2453 | } else if (ret) { |
2454 | if (!cqe_count) | |
2455 | cqe_count = -1; | |
2456 | break; | |
2457 | } | |
2458 | entry->wc_flags = 0; | |
2459 | entry->wr_id = cq_poll_info.wr_id; | |
df35630a | 2460 | if (cq_poll_info.error) { |
d3749841 | 2461 | entry->status = IB_WC_WR_FLUSH_ERR; |
df35630a IM |
2462 | entry->vendor_err = cq_poll_info.major_err << 16 | cq_poll_info.minor_err; |
2463 | } else { | |
2464 | entry->status = IB_WC_SUCCESS; | |
2465 | } | |
d3749841 FL |
2466 | |
2467 | switch (cq_poll_info.op_type) { | |
2468 | case I40IW_OP_TYPE_RDMA_WRITE: | |
2469 | entry->opcode = IB_WC_RDMA_WRITE; | |
2470 | break; | |
2471 | case I40IW_OP_TYPE_RDMA_READ_INV_STAG: | |
2472 | case I40IW_OP_TYPE_RDMA_READ: | |
2473 | entry->opcode = IB_WC_RDMA_READ; | |
2474 | break; | |
2475 | case I40IW_OP_TYPE_SEND_SOL: | |
2476 | case I40IW_OP_TYPE_SEND_SOL_INV: | |
2477 | case I40IW_OP_TYPE_SEND_INV: | |
2478 | case I40IW_OP_TYPE_SEND: | |
2479 | entry->opcode = IB_WC_SEND; | |
2480 | break; | |
2481 | case I40IW_OP_TYPE_REC: | |
2482 | entry->opcode = IB_WC_RECV; | |
2483 | break; | |
2484 | default: | |
2485 | entry->opcode = IB_WC_RECV; | |
2486 | break; | |
2487 | } | |
2488 | ||
d3749841 FL |
2489 | entry->ex.imm_data = 0; |
2490 | qp = (struct i40iw_sc_qp *)cq_poll_info.qp_handle; | |
2491 | entry->qp = (struct ib_qp *)qp->back_qp; | |
2492 | entry->src_qp = cq_poll_info.qp_id; | |
c2b75ef7 IM |
2493 | iwqp = (struct i40iw_qp *)qp->back_qp; |
2494 | if (iwqp->iwarp_state > I40IW_QP_STATE_RTS) { | |
2495 | if (!I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring)) | |
2496 | complete(&iwqp->sq_drained); | |
2497 | if (!I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring)) | |
2498 | complete(&iwqp->rq_drained); | |
2499 | } | |
d3749841 FL |
2500 | entry->byte_len = cq_poll_info.bytes_xfered; |
2501 | entry++; | |
2502 | cqe_count++; | |
2503 | } | |
2504 | spin_unlock_irqrestore(&iwcq->lock, flags); | |
2505 | return cqe_count; | |
2506 | } | |
2507 | ||
2508 | /** | |
2509 | * i40iw_req_notify_cq - arm cq kernel application | |
2510 | * @ibcq: cq to arm | |
2511 | * @notify_flags: notofication flags | |
2512 | */ | |
2513 | static int i40iw_req_notify_cq(struct ib_cq *ibcq, | |
2514 | enum ib_cq_notify_flags notify_flags) | |
2515 | { | |
2516 | struct i40iw_cq *iwcq; | |
2517 | struct i40iw_cq_uk *ukcq; | |
747f1c6d SS |
2518 | unsigned long flags; |
2519 | enum i40iw_completion_notify cq_notify = IW_CQ_COMPL_EVENT; | |
d3749841 FL |
2520 | |
2521 | iwcq = (struct i40iw_cq *)ibcq; | |
2522 | ukcq = &iwcq->sc_cq.cq_uk; | |
747f1c6d SS |
2523 | if (notify_flags == IB_CQ_SOLICITED) |
2524 | cq_notify = IW_CQ_COMPL_SOLICITED; | |
2525 | spin_lock_irqsave(&iwcq->lock, flags); | |
d3749841 | 2526 | ukcq->ops.iw_cq_request_notification(ukcq, cq_notify); |
747f1c6d | 2527 | spin_unlock_irqrestore(&iwcq->lock, flags); |
d3749841 FL |
2528 | return 0; |
2529 | } | |
2530 | ||
2531 | /** | |
2532 | * i40iw_port_immutable - return port's immutable data | |
2533 | * @ibdev: ib dev struct | |
2534 | * @port_num: port number | |
2535 | * @immutable: immutable data for the port return | |
2536 | */ | |
2537 | static int i40iw_port_immutable(struct ib_device *ibdev, u8 port_num, | |
2538 | struct ib_port_immutable *immutable) | |
2539 | { | |
2540 | struct ib_port_attr attr; | |
2541 | int err; | |
2542 | ||
c4550c63 OG |
2543 | immutable->core_cap_flags = RDMA_CORE_PORT_IWARP; |
2544 | ||
2545 | err = ib_query_port(ibdev, port_num, &attr); | |
d3749841 FL |
2546 | |
2547 | if (err) | |
2548 | return err; | |
2549 | ||
2550 | immutable->pkey_tbl_len = attr.pkey_tbl_len; | |
2551 | immutable->gid_tbl_len = attr.gid_tbl_len; | |
d3749841 FL |
2552 | |
2553 | return 0; | |
2554 | } | |
2555 | ||
b40f4757 CL |
2556 | static const char * const i40iw_hw_stat_names[] = { |
2557 | // 32bit names | |
2558 | [I40IW_HW_STAT_INDEX_IP4RXDISCARD] = "ip4InDiscards", | |
2559 | [I40IW_HW_STAT_INDEX_IP4RXTRUNC] = "ip4InTruncatedPkts", | |
2560 | [I40IW_HW_STAT_INDEX_IP4TXNOROUTE] = "ip4OutNoRoutes", | |
2561 | [I40IW_HW_STAT_INDEX_IP6RXDISCARD] = "ip6InDiscards", | |
2562 | [I40IW_HW_STAT_INDEX_IP6RXTRUNC] = "ip6InTruncatedPkts", | |
2563 | [I40IW_HW_STAT_INDEX_IP6TXNOROUTE] = "ip6OutNoRoutes", | |
2564 | [I40IW_HW_STAT_INDEX_TCPRTXSEG] = "tcpRetransSegs", | |
2565 | [I40IW_HW_STAT_INDEX_TCPRXOPTERR] = "tcpInOptErrors", | |
2566 | [I40IW_HW_STAT_INDEX_TCPRXPROTOERR] = "tcpInProtoErrors", | |
2567 | // 64bit names | |
2568 | [I40IW_HW_STAT_INDEX_IP4RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2569 | "ip4InOctets", | |
2570 | [I40IW_HW_STAT_INDEX_IP4RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2571 | "ip4InPkts", | |
2572 | [I40IW_HW_STAT_INDEX_IP4RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2573 | "ip4InReasmRqd", | |
2574 | [I40IW_HW_STAT_INDEX_IP4RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2575 | "ip4InMcastPkts", | |
2576 | [I40IW_HW_STAT_INDEX_IP4TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2577 | "ip4OutOctets", | |
2578 | [I40IW_HW_STAT_INDEX_IP4TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2579 | "ip4OutPkts", | |
2580 | [I40IW_HW_STAT_INDEX_IP4TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2581 | "ip4OutSegRqd", | |
2582 | [I40IW_HW_STAT_INDEX_IP4TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2583 | "ip4OutMcastPkts", | |
2584 | [I40IW_HW_STAT_INDEX_IP6RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2585 | "ip6InOctets", | |
2586 | [I40IW_HW_STAT_INDEX_IP6RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2587 | "ip6InPkts", | |
2588 | [I40IW_HW_STAT_INDEX_IP6RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2589 | "ip6InReasmRqd", | |
2590 | [I40IW_HW_STAT_INDEX_IP6RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2591 | "ip6InMcastPkts", | |
2592 | [I40IW_HW_STAT_INDEX_IP6TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2593 | "ip6OutOctets", | |
2594 | [I40IW_HW_STAT_INDEX_IP6TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2595 | "ip6OutPkts", | |
2596 | [I40IW_HW_STAT_INDEX_IP6TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2597 | "ip6OutSegRqd", | |
2598 | [I40IW_HW_STAT_INDEX_IP6TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2599 | "ip6OutMcastPkts", | |
2600 | [I40IW_HW_STAT_INDEX_TCPRXSEGS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2601 | "tcpInSegs", | |
2602 | [I40IW_HW_STAT_INDEX_TCPTXSEG + I40IW_HW_STAT_INDEX_MAX_32] = | |
2603 | "tcpOutSegs", | |
2604 | [I40IW_HW_STAT_INDEX_RDMARXRDS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2605 | "iwInRdmaReads", | |
2606 | [I40IW_HW_STAT_INDEX_RDMARXSNDS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2607 | "iwInRdmaSends", | |
2608 | [I40IW_HW_STAT_INDEX_RDMARXWRS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2609 | "iwInRdmaWrites", | |
2610 | [I40IW_HW_STAT_INDEX_RDMATXRDS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2611 | "iwOutRdmaReads", | |
2612 | [I40IW_HW_STAT_INDEX_RDMATXSNDS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2613 | "iwOutRdmaSends", | |
2614 | [I40IW_HW_STAT_INDEX_RDMATXWRS + I40IW_HW_STAT_INDEX_MAX_32] = | |
2615 | "iwOutRdmaWrites", | |
2616 | [I40IW_HW_STAT_INDEX_RDMAVBND + I40IW_HW_STAT_INDEX_MAX_32] = | |
2617 | "iwRdmaBnd", | |
2618 | [I40IW_HW_STAT_INDEX_RDMAVINV + I40IW_HW_STAT_INDEX_MAX_32] = | |
2619 | "iwRdmaInv" | |
2620 | }; | |
2621 | ||
9abb0d1b | 2622 | static void i40iw_get_dev_fw_str(struct ib_device *dev, char *str) |
f65c52ca IW |
2623 | { |
2624 | u32 firmware_version = I40IW_FW_VERSION; | |
2625 | ||
9abb0d1b LR |
2626 | snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u", firmware_version, |
2627 | (firmware_version & 0x000000ff)); | |
f65c52ca IW |
2628 | } |
2629 | ||
d3749841 | 2630 | /** |
b40f4757 CL |
2631 | * i40iw_alloc_hw_stats - Allocate a hw stats structure |
2632 | * @ibdev: device pointer from stack | |
2633 | * @port_num: port number | |
d3749841 | 2634 | */ |
b40f4757 CL |
2635 | static struct rdma_hw_stats *i40iw_alloc_hw_stats(struct ib_device *ibdev, |
2636 | u8 port_num) | |
2637 | { | |
2638 | struct i40iw_device *iwdev = to_iwdev(ibdev); | |
2639 | struct i40iw_sc_dev *dev = &iwdev->sc_dev; | |
2640 | int num_counters = I40IW_HW_STAT_INDEX_MAX_32 + | |
2641 | I40IW_HW_STAT_INDEX_MAX_64; | |
2642 | unsigned long lifespan = RDMA_HW_STATS_DEFAULT_LIFESPAN; | |
2643 | ||
2644 | BUILD_BUG_ON(ARRAY_SIZE(i40iw_hw_stat_names) != | |
2645 | (I40IW_HW_STAT_INDEX_MAX_32 + | |
2646 | I40IW_HW_STAT_INDEX_MAX_64)); | |
2647 | ||
2648 | /* | |
2649 | * PFs get the default update lifespan, but VFs only update once | |
2650 | * per second | |
2651 | */ | |
2652 | if (!dev->is_pf) | |
2653 | lifespan = 1000; | |
2654 | return rdma_alloc_hw_stats_struct(i40iw_hw_stat_names, num_counters, | |
2655 | lifespan); | |
2656 | } | |
2657 | ||
2658 | /** | |
2659 | * i40iw_get_hw_stats - Populates the rdma_hw_stats structure | |
2660 | * @ibdev: device pointer from stack | |
2661 | * @stats: stats pointer from stack | |
2662 | * @port_num: port number | |
2663 | * @index: which hw counter the stack is requesting we update | |
2664 | */ | |
2665 | static int i40iw_get_hw_stats(struct ib_device *ibdev, | |
2666 | struct rdma_hw_stats *stats, | |
2667 | u8 port_num, int index) | |
d3749841 FL |
2668 | { |
2669 | struct i40iw_device *iwdev = to_iwdev(ibdev); | |
2670 | struct i40iw_sc_dev *dev = &iwdev->sc_dev; | |
d6f7bbcc | 2671 | struct i40iw_vsi_pestat *devstat = iwdev->vsi.pestat; |
d3749841 | 2672 | struct i40iw_dev_hw_stats *hw_stats = &devstat->hw_stats; |
d3749841 | 2673 | |
d3749841 | 2674 | if (dev->is_pf) { |
d6f7bbcc | 2675 | i40iw_hw_stats_read_all(devstat, &devstat->hw_stats); |
d3749841 | 2676 | } else { |
b40f4757 CL |
2677 | if (i40iw_vchnl_vf_get_pe_stats(dev, &devstat->hw_stats)) |
2678 | return -ENOSYS; | |
d3749841 FL |
2679 | } |
2680 | ||
91c42b72 | 2681 | memcpy(&stats->value[0], hw_stats, sizeof(*hw_stats)); |
b40f4757 CL |
2682 | |
2683 | return stats->num_counters; | |
d3749841 FL |
2684 | } |
2685 | ||
2686 | /** | |
2687 | * i40iw_query_gid - Query port GID | |
2688 | * @ibdev: device pointer from stack | |
2689 | * @port: port number | |
2690 | * @index: Entry index | |
2691 | * @gid: Global ID | |
2692 | */ | |
2693 | static int i40iw_query_gid(struct ib_device *ibdev, | |
2694 | u8 port, | |
2695 | int index, | |
2696 | union ib_gid *gid) | |
2697 | { | |
2698 | struct i40iw_device *iwdev = to_iwdev(ibdev); | |
2699 | ||
2700 | memset(gid->raw, 0, sizeof(gid->raw)); | |
2701 | ether_addr_copy(gid->raw, iwdev->netdev->dev_addr); | |
2702 | return 0; | |
2703 | } | |
2704 | ||
d3749841 FL |
2705 | /** |
2706 | * i40iw_query_pkey - Query partition key | |
2707 | * @ibdev: device pointer from stack | |
2708 | * @port: port number | |
2709 | * @index: index of pkey | |
2710 | * @pkey: pointer to store the pkey | |
2711 | */ | |
2712 | static int i40iw_query_pkey(struct ib_device *ibdev, | |
2713 | u8 port, | |
2714 | u16 index, | |
2715 | u16 *pkey) | |
2716 | { | |
2717 | *pkey = 0; | |
2718 | return 0; | |
2719 | } | |
2720 | ||
7e952b19 SS |
2721 | /** |
2722 | * i40iw_get_vector_affinity - report IRQ affinity mask | |
2723 | * @ibdev: IB device | |
2724 | * @comp_vector: completion vector index | |
2725 | */ | |
2726 | static const struct cpumask *i40iw_get_vector_affinity(struct ib_device *ibdev, | |
2727 | int comp_vector) | |
2728 | { | |
2729 | struct i40iw_device *iwdev = to_iwdev(ibdev); | |
2730 | struct i40iw_msix_vector *msix_vec; | |
2731 | ||
2732 | if (iwdev->msix_shared) | |
2733 | msix_vec = &iwdev->iw_msixtbl[comp_vector]; | |
2734 | else | |
2735 | msix_vec = &iwdev->iw_msixtbl[comp_vector + 1]; | |
2736 | ||
2737 | return irq_get_affinity_mask(msix_vec->irq); | |
2738 | } | |
2739 | ||
d3749841 FL |
2740 | /** |
2741 | * i40iw_init_rdma_device - initialization of iwarp device | |
2742 | * @iwdev: iwarp device | |
2743 | */ | |
2744 | static struct i40iw_ib_device *i40iw_init_rdma_device(struct i40iw_device *iwdev) | |
2745 | { | |
2746 | struct i40iw_ib_device *iwibdev; | |
2747 | struct net_device *netdev = iwdev->netdev; | |
2748 | struct pci_dev *pcidev = (struct pci_dev *)iwdev->hw.dev_context; | |
2749 | ||
2750 | iwibdev = (struct i40iw_ib_device *)ib_alloc_device(sizeof(*iwibdev)); | |
2751 | if (!iwibdev) { | |
2752 | i40iw_pr_err("iwdev == NULL\n"); | |
2753 | return NULL; | |
2754 | } | |
2755 | strlcpy(iwibdev->ibdev.name, "i40iw%d", IB_DEVICE_NAME_MAX); | |
2756 | iwibdev->ibdev.owner = THIS_MODULE; | |
2757 | iwdev->iwibdev = iwibdev; | |
2758 | iwibdev->iwdev = iwdev; | |
2759 | ||
2760 | iwibdev->ibdev.node_type = RDMA_NODE_RNIC; | |
2761 | ether_addr_copy((u8 *)&iwibdev->ibdev.node_guid, netdev->dev_addr); | |
2762 | ||
2763 | iwibdev->ibdev.uverbs_cmd_mask = | |
2764 | (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | | |
2765 | (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | | |
2766 | (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | | |
2767 | (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | | |
2768 | (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | | |
2769 | (1ull << IB_USER_VERBS_CMD_REG_MR) | | |
2770 | (1ull << IB_USER_VERBS_CMD_DEREG_MR) | | |
2771 | (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | | |
2772 | (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | | |
2773 | (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | | |
2774 | (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) | | |
2775 | (1ull << IB_USER_VERBS_CMD_CREATE_QP) | | |
2776 | (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | | |
2777 | (1ull << IB_USER_VERBS_CMD_QUERY_QP) | | |
2778 | (1ull << IB_USER_VERBS_CMD_POLL_CQ) | | |
2779 | (1ull << IB_USER_VERBS_CMD_CREATE_AH) | | |
2780 | (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | | |
2781 | (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | | |
2782 | (1ull << IB_USER_VERBS_CMD_POST_RECV) | | |
2783 | (1ull << IB_USER_VERBS_CMD_POST_SEND); | |
2784 | iwibdev->ibdev.phys_port_cnt = 1; | |
e69c5093 | 2785 | iwibdev->ibdev.num_comp_vectors = iwdev->ceqs_count; |
d3749841 FL |
2786 | iwibdev->ibdev.dev.parent = &pcidev->dev; |
2787 | iwibdev->ibdev.query_port = i40iw_query_port; | |
d3749841 FL |
2788 | iwibdev->ibdev.query_pkey = i40iw_query_pkey; |
2789 | iwibdev->ibdev.query_gid = i40iw_query_gid; | |
2790 | iwibdev->ibdev.alloc_ucontext = i40iw_alloc_ucontext; | |
2791 | iwibdev->ibdev.dealloc_ucontext = i40iw_dealloc_ucontext; | |
2792 | iwibdev->ibdev.mmap = i40iw_mmap; | |
2793 | iwibdev->ibdev.alloc_pd = i40iw_alloc_pd; | |
2794 | iwibdev->ibdev.dealloc_pd = i40iw_dealloc_pd; | |
2795 | iwibdev->ibdev.create_qp = i40iw_create_qp; | |
2796 | iwibdev->ibdev.modify_qp = i40iw_modify_qp; | |
2797 | iwibdev->ibdev.query_qp = i40iw_query_qp; | |
2798 | iwibdev->ibdev.destroy_qp = i40iw_destroy_qp; | |
2799 | iwibdev->ibdev.create_cq = i40iw_create_cq; | |
2800 | iwibdev->ibdev.destroy_cq = i40iw_destroy_cq; | |
2801 | iwibdev->ibdev.get_dma_mr = i40iw_get_dma_mr; | |
2802 | iwibdev->ibdev.reg_user_mr = i40iw_reg_user_mr; | |
2803 | iwibdev->ibdev.dereg_mr = i40iw_dereg_mr; | |
b40f4757 CL |
2804 | iwibdev->ibdev.alloc_hw_stats = i40iw_alloc_hw_stats; |
2805 | iwibdev->ibdev.get_hw_stats = i40iw_get_hw_stats; | |
d3749841 | 2806 | iwibdev->ibdev.query_device = i40iw_query_device; |
c2b75ef7 IM |
2807 | iwibdev->ibdev.drain_sq = i40iw_drain_sq; |
2808 | iwibdev->ibdev.drain_rq = i40iw_drain_rq; | |
b7aee855 IM |
2809 | iwibdev->ibdev.alloc_mr = i40iw_alloc_mr; |
2810 | iwibdev->ibdev.map_mr_sg = i40iw_map_mr_sg; | |
d3749841 FL |
2811 | iwibdev->ibdev.iwcm = kzalloc(sizeof(*iwibdev->ibdev.iwcm), GFP_KERNEL); |
2812 | if (!iwibdev->ibdev.iwcm) { | |
2813 | ib_dealloc_device(&iwibdev->ibdev); | |
d3749841 FL |
2814 | return NULL; |
2815 | } | |
2816 | ||
2817 | iwibdev->ibdev.iwcm->add_ref = i40iw_add_ref; | |
2818 | iwibdev->ibdev.iwcm->rem_ref = i40iw_rem_ref; | |
2819 | iwibdev->ibdev.iwcm->get_qp = i40iw_get_qp; | |
2820 | iwibdev->ibdev.iwcm->connect = i40iw_connect; | |
2821 | iwibdev->ibdev.iwcm->accept = i40iw_accept; | |
2822 | iwibdev->ibdev.iwcm->reject = i40iw_reject; | |
2823 | iwibdev->ibdev.iwcm->create_listen = i40iw_create_listen; | |
2824 | iwibdev->ibdev.iwcm->destroy_listen = i40iw_destroy_listen; | |
8d8cd0bf FL |
2825 | memcpy(iwibdev->ibdev.iwcm->ifname, netdev->name, |
2826 | sizeof(iwibdev->ibdev.iwcm->ifname)); | |
d3749841 | 2827 | iwibdev->ibdev.get_port_immutable = i40iw_port_immutable; |
f65c52ca | 2828 | iwibdev->ibdev.get_dev_fw_str = i40iw_get_dev_fw_str; |
d3749841 FL |
2829 | iwibdev->ibdev.poll_cq = i40iw_poll_cq; |
2830 | iwibdev->ibdev.req_notify_cq = i40iw_req_notify_cq; | |
2831 | iwibdev->ibdev.post_send = i40iw_post_send; | |
2832 | iwibdev->ibdev.post_recv = i40iw_post_recv; | |
7e952b19 | 2833 | iwibdev->ibdev.get_vector_affinity = i40iw_get_vector_affinity; |
8d8cd0bf | 2834 | |
d3749841 FL |
2835 | return iwibdev; |
2836 | } | |
2837 | ||
2838 | /** | |
2839 | * i40iw_port_ibevent - indicate port event | |
2840 | * @iwdev: iwarp device | |
2841 | */ | |
2842 | void i40iw_port_ibevent(struct i40iw_device *iwdev) | |
2843 | { | |
2844 | struct i40iw_ib_device *iwibdev = iwdev->iwibdev; | |
2845 | struct ib_event event; | |
2846 | ||
2847 | event.device = &iwibdev->ibdev; | |
2848 | event.element.port_num = 1; | |
2849 | event.event = iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; | |
2850 | ib_dispatch_event(&event); | |
2851 | } | |
2852 | ||
2853 | /** | |
2854 | * i40iw_unregister_rdma_device - unregister of iwarp from IB | |
2855 | * @iwibdev: rdma device ptr | |
2856 | */ | |
2857 | static void i40iw_unregister_rdma_device(struct i40iw_ib_device *iwibdev) | |
2858 | { | |
2859 | int i; | |
2860 | ||
2861 | for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i) | |
2862 | device_remove_file(&iwibdev->ibdev.dev, | |
2863 | i40iw_dev_attributes[i]); | |
2864 | ib_unregister_device(&iwibdev->ibdev); | |
2865 | } | |
2866 | ||
2867 | /** | |
2868 | * i40iw_destroy_rdma_device - destroy rdma device and free resources | |
2869 | * @iwibdev: IB device ptr | |
2870 | */ | |
2871 | void i40iw_destroy_rdma_device(struct i40iw_ib_device *iwibdev) | |
2872 | { | |
2873 | if (!iwibdev) | |
2874 | return; | |
2875 | ||
2876 | i40iw_unregister_rdma_device(iwibdev); | |
2877 | kfree(iwibdev->ibdev.iwcm); | |
2878 | iwibdev->ibdev.iwcm = NULL; | |
d5965934 MI |
2879 | wait_event_timeout(iwibdev->iwdev->close_wq, |
2880 | !atomic64_read(&iwibdev->iwdev->use_count), | |
2881 | I40IW_EVENT_TIMEOUT); | |
d3749841 FL |
2882 | ib_dealloc_device(&iwibdev->ibdev); |
2883 | } | |
2884 | ||
2885 | /** | |
2886 | * i40iw_register_rdma_device - register iwarp device to IB | |
2887 | * @iwdev: iwarp device | |
2888 | */ | |
2889 | int i40iw_register_rdma_device(struct i40iw_device *iwdev) | |
2890 | { | |
2891 | int i, ret; | |
2892 | struct i40iw_ib_device *iwibdev; | |
2893 | ||
2894 | iwdev->iwibdev = i40iw_init_rdma_device(iwdev); | |
2895 | if (!iwdev->iwibdev) | |
fe5d6e62 | 2896 | return -ENOMEM; |
d3749841 FL |
2897 | iwibdev = iwdev->iwibdev; |
2898 | ||
0ede73bc | 2899 | iwibdev->ibdev.driver_id = RDMA_DRIVER_I40IW; |
d3749841 FL |
2900 | ret = ib_register_device(&iwibdev->ibdev, NULL); |
2901 | if (ret) | |
2902 | goto error; | |
2903 | ||
2904 | for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i) { | |
2905 | ret = | |
2906 | device_create_file(&iwibdev->ibdev.dev, | |
2907 | i40iw_dev_attributes[i]); | |
2908 | if (ret) { | |
2909 | while (i > 0) { | |
2910 | i--; | |
2911 | device_remove_file(&iwibdev->ibdev.dev, i40iw_dev_attributes[i]); | |
2912 | } | |
2913 | ib_unregister_device(&iwibdev->ibdev); | |
2914 | goto error; | |
2915 | } | |
2916 | } | |
2917 | return 0; | |
2918 | error: | |
2919 | kfree(iwdev->iwibdev->ibdev.iwcm); | |
2920 | iwdev->iwibdev->ibdev.iwcm = NULL; | |
2921 | ib_dealloc_device(&iwdev->iwibdev->ibdev); | |
fe5d6e62 | 2922 | return ret; |
d3749841 | 2923 | } |