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RDMA/hns: Program the tclass and flow label into the hardware
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v2.c
CommitLineData
dd74282d
WHX		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/acpi.h>
34#include <linux/etherdevice.h>
35#include <linux/interrupt.h>
36#include <linux/kernel.h>
0b25c9cc 37#include <linux/types.h>
d4994d2f 38#include <net/addrconf.h>
610b8967 39#include <rdma/ib_addr.h>
dd74282d
WHX		 40#include <rdma/ib_umem.h>
41
42#include "hnae3.h"
43#include "hns_roce_common.h"
44#include "hns_roce_device.h"
45#include "hns_roce_cmd.h"
46#include "hns_roce_hem.h"
a04ff739 47#include "hns_roce_hw_v2.h"
dd74282d 48
2d407888
WHX		 49static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
50 struct ib_sge *sg)
51{
52 dseg->lkey = cpu_to_le32(sg->lkey);
53 dseg->addr = cpu_to_le64(sg->addr);
54 dseg->len = cpu_to_le32(sg->length);
55}
56
f696bf6d 57static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
0b25c9cc
WHX		 58 unsigned int *sge_ind)
59{
60 struct hns_roce_v2_wqe_data_seg *dseg;
61 struct ib_sge *sg;
62 int num_in_wqe = 0;
63 int extend_sge_num;
64 int fi_sge_num;
65 int se_sge_num;
66 int shift;
67 int i;
68
69 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC)
70 num_in_wqe = HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE;
71 extend_sge_num = wr->num_sge - num_in_wqe;
72 sg = wr->sg_list + num_in_wqe;
73 shift = qp->hr_buf.page_shift;
74
75 /*
76 * Check whether wr->num_sge sges are in the same page. If not, we
77 * should calculate how many sges in the first page and the second
78 * page.
79 */
80 dseg = get_send_extend_sge(qp, (*sge_ind) & (qp->sge.sge_cnt - 1));
81 fi_sge_num = (round_up((uintptr_t)dseg, 1 << shift) -
82 (uintptr_t)dseg) /
83 sizeof(struct hns_roce_v2_wqe_data_seg);
84 if (extend_sge_num > fi_sge_num) {
85 se_sge_num = extend_sge_num - fi_sge_num;
86 for (i = 0; i < fi_sge_num; i++) {
87 set_data_seg_v2(dseg++, sg + i);
88 (*sge_ind)++;
89 }
90 dseg = get_send_extend_sge(qp,
91 (*sge_ind) & (qp->sge.sge_cnt - 1));
92 for (i = 0; i < se_sge_num; i++) {
93 set_data_seg_v2(dseg++, sg + fi_sge_num + i);
94 (*sge_ind)++;
95 }
96 } else {
97 for (i = 0; i < extend_sge_num; i++) {
98 set_data_seg_v2(dseg++, sg + i);
99 (*sge_ind)++;
100 }
101 }
102}
103
f696bf6d 104static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
7bdee415 105 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
106 void *wqe, unsigned int *sge_ind,
d34ac5cd 107 const struct ib_send_wr **bad_wr)
7bdee415 108{
109 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
110 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
111 struct hns_roce_qp *qp = to_hr_qp(ibqp);
112 int i;
113
114 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
8b9b8d14 115 if (le32_to_cpu(rc_sq_wqe->msg_len) >
116 hr_dev->caps.max_sq_inline) {
7bdee415 117 *bad_wr = wr;
118 dev_err(hr_dev->dev, "inline len(1-%d)=%d, illegal",
119 rc_sq_wqe->msg_len, hr_dev->caps.max_sq_inline);
120 return -EINVAL;
121 }
122
328d405b 123 if (wr->opcode == IB_WR_RDMA_READ) {
124 dev_err(hr_dev->dev, "Not support inline data!\n");
125 return -EINVAL;
126 }
127
7bdee415 128 for (i = 0; i < wr->num_sge; i++) {
129 memcpy(wqe, ((void *)wr->sg_list[i].addr),
130 wr->sg_list[i].length);
131 wqe += wr->sg_list[i].length;
132 }
133
134 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S,
135 1);
136 } else {
0b25c9cc 137 if (wr->num_sge <= HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) {
7bdee415 138 for (i = 0; i < wr->num_sge; i++) {
139 if (likely(wr->sg_list[i].length)) {
140 set_data_seg_v2(dseg, wr->sg_list + i);
141 dseg++;
142 }
143 }
144 } else {
145 roce_set_field(rc_sq_wqe->byte_20,
146 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
147 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
148 (*sge_ind) & (qp->sge.sge_cnt - 1));
149
0b25c9cc 150 for (i = 0; i < HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE; i++) {
7bdee415 151 if (likely(wr->sg_list[i].length)) {
152 set_data_seg_v2(dseg, wr->sg_list + i);
153 dseg++;
154 }
155 }
156
0b25c9cc 157 set_extend_sge(qp, wr, sge_ind);
7bdee415 158 }
159
160 roce_set_field(rc_sq_wqe->byte_16,
161 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
162 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, wr->num_sge);
163 }
164
165 return 0;
166}
167
d34ac5cd
BVA		 168static int hns_roce_v2_post_send(struct ib_qp *ibqp,
169 const struct ib_send_wr *wr,
170 const struct ib_send_wr **bad_wr)
2d407888
WHX		 171{
172 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
7bdee415 173 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
174 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe;
2d407888
WHX		 175 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe;
176 struct hns_roce_qp *qp = to_hr_qp(ibqp);
2d407888
WHX		 177 struct device *dev = hr_dev->dev;
178 struct hns_roce_v2_db sq_db;
179 unsigned int sge_ind = 0;
e8d18533 180 unsigned int owner_bit;
2d407888
WHX		 181 unsigned long flags;
182 unsigned int ind;
183 void *wqe = NULL;
7bdee415 184 bool loopback;
55ba49cb 185 u32 tmp_len;
2d407888 186 int ret = 0;
7bdee415 187 u8 *smac;
2d407888
WHX		 188 int nreq;
189 int i;
190
7bdee415 191 if (unlikely(ibqp->qp_type != IB_QPT_RC &&
192 ibqp->qp_type != IB_QPT_GSI &&
193 ibqp->qp_type != IB_QPT_UD)) {
2d407888 194 dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type);
137ae320 195 *bad_wr = wr;
2d407888
WHX		 196 return -EOPNOTSUPP;
197 }
198
10bd2ade
YL		 199 if (unlikely(qp->state == IB_QPS_RESET || qp->state == IB_QPS_INIT ||
200 qp->state == IB_QPS_RTR)) {
2d407888
WHX		 201 dev_err(dev, "Post WQE fail, QP state %d err!\n", qp->state);
202 *bad_wr = wr;
203 return -EINVAL;
204 }
205
206 spin_lock_irqsave(&qp->sq.lock, flags);
207 ind = qp->sq_next_wqe;
208 sge_ind = qp->next_sge;
209
210 for (nreq = 0; wr; ++nreq, wr = wr->next) {
211 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
212 ret = -ENOMEM;
213 *bad_wr = wr;
214 goto out;
215 }
216
217 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
218 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
219 wr->num_sge, qp->sq.max_gs);
220 ret = -EINVAL;
221 *bad_wr = wr;
222 goto out;
223 }
224
225 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
226 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
227 wr->wr_id;
228
634f6390 229 owner_bit =
230 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
55ba49cb 231 tmp_len = 0;
2d407888 232
7bdee415 233 /* Corresponding to the QP type, wqe process separately */
234 if (ibqp->qp_type == IB_QPT_GSI) {
235 ud_sq_wqe = wqe;
236 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe));
237
238 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M,
239 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]);
240 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M,
241 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]);
242 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M,
243 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]);
244 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M,
245 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]);
246 roce_set_field(ud_sq_wqe->byte_48,
247 V2_UD_SEND_WQE_BYTE_48_DMAC_4_M,
248 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S,
249 ah->av.mac[4]);
250 roce_set_field(ud_sq_wqe->byte_48,
251 V2_UD_SEND_WQE_BYTE_48_DMAC_5_M,
252 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S,
253 ah->av.mac[5]);
254
255 /* MAC loopback */
256 smac = (u8 *)hr_dev->dev_addr[qp->port];
257 loopback = ether_addr_equal_unaligned(ah->av.mac,
258 smac) ? 1 : 0;
259
260 roce_set_bit(ud_sq_wqe->byte_40,
261 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback);
262
263 roce_set_field(ud_sq_wqe->byte_4,
264 V2_UD_SEND_WQE_BYTE_4_OPCODE_M,
265 V2_UD_SEND_WQE_BYTE_4_OPCODE_S,
266 HNS_ROCE_V2_WQE_OP_SEND);
2d407888 267
7bdee415 268 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 269 tmp_len += wr->sg_list[i].length;
492b2bd0 270
8b9b8d14 271 ud_sq_wqe->msg_len =
272 cpu_to_le32(le32_to_cpu(ud_sq_wqe->msg_len) + tmp_len);
273
274 switch (wr->opcode) {
275 case IB_WR_SEND_WITH_IMM:
276 case IB_WR_RDMA_WRITE_WITH_IMM:
0c4a0e29
LO		 277 ud_sq_wqe->immtdata =
278 cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
8b9b8d14 279 break;
280 default:
281 ud_sq_wqe->immtdata = 0;
282 break;
283 }
651487c2 284
7bdee415 285 /* Set sig attr */
286 roce_set_bit(ud_sq_wqe->byte_4,
287 V2_UD_SEND_WQE_BYTE_4_CQE_S,
288 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
a49d761f 289
7bdee415 290 /* Set se attr */
291 roce_set_bit(ud_sq_wqe->byte_4,
292 V2_UD_SEND_WQE_BYTE_4_SE_S,
293 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
e8d18533 294
7bdee415 295 roce_set_bit(ud_sq_wqe->byte_4,
296 V2_UD_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
297
298 roce_set_field(ud_sq_wqe->byte_16,
299 V2_UD_SEND_WQE_BYTE_16_PD_M,
300 V2_UD_SEND_WQE_BYTE_16_PD_S,
301 to_hr_pd(ibqp->pd)->pdn);
302
303 roce_set_field(ud_sq_wqe->byte_16,
304 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M,
305 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S,
306 wr->num_sge);
307
308 roce_set_field(ud_sq_wqe->byte_20,
309 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
310 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
311 sge_ind & (qp->sge.sge_cnt - 1));
312
313 roce_set_field(ud_sq_wqe->byte_24,
314 V2_UD_SEND_WQE_BYTE_24_UDPSPN_M,
315 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0);
316 ud_sq_wqe->qkey =
8b9b8d14 317 cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
318 qp->qkey : ud_wr(wr)->remote_qkey);
7bdee415 319 roce_set_field(ud_sq_wqe->byte_32,
320 V2_UD_SEND_WQE_BYTE_32_DQPN_M,
321 V2_UD_SEND_WQE_BYTE_32_DQPN_S,
322 ud_wr(wr)->remote_qpn);
323
324 roce_set_field(ud_sq_wqe->byte_36,
325 V2_UD_SEND_WQE_BYTE_36_VLAN_M,
326 V2_UD_SEND_WQE_BYTE_36_VLAN_S,
8b9b8d14 327 le16_to_cpu(ah->av.vlan));
7bdee415 328 roce_set_field(ud_sq_wqe->byte_36,
329 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
330 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S,
331 ah->av.hop_limit);
332 roce_set_field(ud_sq_wqe->byte_36,
333 V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
334 V2_UD_SEND_WQE_BYTE_36_TCLASS_S,
cdfa4ad5
LO		 335 ah->av.sl_tclass_flowlabel >>
336 HNS_ROCE_TCLASS_SHIFT);
7bdee415 337 roce_set_field(ud_sq_wqe->byte_40,
338 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
cdfa4ad5
LO		 339 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S,
340 ah->av.sl_tclass_flowlabel &
341 HNS_ROCE_FLOW_LABEL_MASK);
7bdee415 342 roce_set_field(ud_sq_wqe->byte_40,
343 V2_UD_SEND_WQE_BYTE_40_SL_M,
344 V2_UD_SEND_WQE_BYTE_40_SL_S,
8b9b8d14 345 le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
346 HNS_ROCE_SL_SHIFT);
7bdee415 347 roce_set_field(ud_sq_wqe->byte_40,
348 V2_UD_SEND_WQE_BYTE_40_PORTN_M,
349 V2_UD_SEND_WQE_BYTE_40_PORTN_S,
350 qp->port);
351
352 roce_set_field(ud_sq_wqe->byte_48,
353 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M,
354 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S,
355 hns_get_gid_index(hr_dev, qp->phy_port,
356 ah->av.gid_index));
357
358 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0],
359 GID_LEN_V2);
360
0b25c9cc 361 set_extend_sge(qp, wr, &sge_ind);
7bdee415 362 ind++;
363 } else if (ibqp->qp_type == IB_QPT_RC) {
364 rc_sq_wqe = wqe;
365 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
366 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 367 tmp_len += wr->sg_list[i].length;
368
369 rc_sq_wqe->msg_len =
370 cpu_to_le32(le32_to_cpu(rc_sq_wqe->msg_len) + tmp_len);
7bdee415 371
8b9b8d14 372 switch (wr->opcode) {
373 case IB_WR_SEND_WITH_IMM:
374 case IB_WR_RDMA_WRITE_WITH_IMM:
0c4a0e29
LO		 375 rc_sq_wqe->immtdata =
376 cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
8b9b8d14 377 break;
378 case IB_WR_SEND_WITH_INV:
379 rc_sq_wqe->inv_key =
380 cpu_to_le32(wr->ex.invalidate_rkey);
381 break;
382 default:
383 rc_sq_wqe->immtdata = 0;
384 break;
385 }
7bdee415 386
387 roce_set_bit(rc_sq_wqe->byte_4,
388 V2_RC_SEND_WQE_BYTE_4_FENCE_S,
389 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
390
391 roce_set_bit(rc_sq_wqe->byte_4,
392 V2_RC_SEND_WQE_BYTE_4_SE_S,
393 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
394
395 roce_set_bit(rc_sq_wqe->byte_4,
396 V2_RC_SEND_WQE_BYTE_4_CQE_S,
397 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
398
399 roce_set_bit(rc_sq_wqe->byte_4,
400 V2_RC_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
401
402 switch (wr->opcode) {
403 case IB_WR_RDMA_READ:
404 roce_set_field(rc_sq_wqe->byte_4,
405 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
406 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
407 HNS_ROCE_V2_WQE_OP_RDMA_READ);
408 rc_sq_wqe->rkey =
409 cpu_to_le32(rdma_wr(wr)->rkey);
410 rc_sq_wqe->va =
411 cpu_to_le64(rdma_wr(wr)->remote_addr);
412 break;
413 case IB_WR_RDMA_WRITE:
414 roce_set_field(rc_sq_wqe->byte_4,
415 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
416 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
417 HNS_ROCE_V2_WQE_OP_RDMA_WRITE);
418 rc_sq_wqe->rkey =
419 cpu_to_le32(rdma_wr(wr)->rkey);
420 rc_sq_wqe->va =
421 cpu_to_le64(rdma_wr(wr)->remote_addr);
422 break;
423 case IB_WR_RDMA_WRITE_WITH_IMM:
424 roce_set_field(rc_sq_wqe->byte_4,
2d407888
WHX		 425 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
426 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
427 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM);
7bdee415 428 rc_sq_wqe->rkey =
429 cpu_to_le32(rdma_wr(wr)->rkey);
430 rc_sq_wqe->va =
431 cpu_to_le64(rdma_wr(wr)->remote_addr);
432 break;
433 case IB_WR_SEND:
434 roce_set_field(rc_sq_wqe->byte_4,
435 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
436 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
437 HNS_ROCE_V2_WQE_OP_SEND);
438 break;
439 case IB_WR_SEND_WITH_INV:
440 roce_set_field(rc_sq_wqe->byte_4,
2d407888
WHX		 441 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
442 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
443 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV);
7bdee415 444 break;
445 case IB_WR_SEND_WITH_IMM:
446 roce_set_field(rc_sq_wqe->byte_4,
447 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
448 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
449 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM);
450 break;
451 case IB_WR_LOCAL_INV:
452 roce_set_field(rc_sq_wqe->byte_4,
453 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
454 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
455 HNS_ROCE_V2_WQE_OP_LOCAL_INV);
456 break;
457 case IB_WR_ATOMIC_CMP_AND_SWP:
458 roce_set_field(rc_sq_wqe->byte_4,
459 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
460 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
461 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP);
462 break;
463 case IB_WR_ATOMIC_FETCH_AND_ADD:
464 roce_set_field(rc_sq_wqe->byte_4,
465 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
466 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
467 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD);
468 break;
469 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
470 roce_set_field(rc_sq_wqe->byte_4,
2d407888
WHX		 471 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
472 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
473 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP);
7bdee415 474 break;
475 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
476 roce_set_field(rc_sq_wqe->byte_4,
2d407888
WHX		 477 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
478 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
479 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD);
7bdee415 480 break;
481 default:
482 roce_set_field(rc_sq_wqe->byte_4,
483 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
484 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
485 HNS_ROCE_V2_WQE_OP_MASK);
486 break;
2d407888
WHX		 487 }
488
7bdee415 489 wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
2d407888 490
7bdee415 491 ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe, wqe,
492 &sge_ind, bad_wr);
493 if (ret)
494 goto out;
495 ind++;
2d407888 496 } else {
7bdee415 497 dev_err(dev, "Illegal qp_type(0x%x)\n", ibqp->qp_type);
498 spin_unlock_irqrestore(&qp->sq.lock, flags);
137ae320 499 *bad_wr = wr;
7bdee415 500 return -EOPNOTSUPP;
2d407888 501 }
2d407888
WHX		 502 }
503
504out:
505 if (likely(nreq)) {
506 qp->sq.head += nreq;
507 /* Memory barrier */
508 wmb();
509
510 sq_db.byte_4 = 0;
511 sq_db.parameter = 0;
512
513 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M,
514 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn);
515 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M,
516 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB);
cc3391cb 517 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M,
518 V2_DB_PARAMETER_IDX_S,
2d407888
WHX		 519 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1));
520 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M,
521 V2_DB_PARAMETER_SL_S, qp->sl);
522
8b9b8d14 523 hns_roce_write64_k((__le32 *)&sq_db, qp->sq.db_reg_l);
2d407888
WHX		 524
525 qp->sq_next_wqe = ind;
526 qp->next_sge = sge_ind;
527 }
528
529 spin_unlock_irqrestore(&qp->sq.lock, flags);
530
531 return ret;
532}
533
d34ac5cd
BVA		 534static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
535 const struct ib_recv_wr *wr,
536 const struct ib_recv_wr **bad_wr)
2d407888
WHX		 537{
538 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
539 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
540 struct hns_roce_v2_wqe_data_seg *dseg;
0009c2db 541 struct hns_roce_rinl_sge *sge_list;
2d407888 542 struct device *dev = hr_dev->dev;
2d407888
WHX		 543 unsigned long flags;
544 void *wqe = NULL;
545 int ret = 0;
546 int nreq;
547 int ind;
548 int i;
549
550 spin_lock_irqsave(&hr_qp->rq.lock, flags);
551 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
552
ced07769 553 if (hr_qp->state == IB_QPS_RESET) {
2d407888
WHX		 554 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
555 *bad_wr = wr;
556 return -EINVAL;
557 }
558
559 for (nreq = 0; wr; ++nreq, wr = wr->next) {
560 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
561 hr_qp->ibqp.recv_cq)) {
562 ret = -ENOMEM;
563 *bad_wr = wr;
564 goto out;
565 }
566
567 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
568 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
569 wr->num_sge, hr_qp->rq.max_gs);
570 ret = -EINVAL;
571 *bad_wr = wr;
572 goto out;
573 }
574
575 wqe = get_recv_wqe(hr_qp, ind);
576 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
577 for (i = 0; i < wr->num_sge; i++) {
578 if (!wr->sg_list[i].length)
579 continue;
580 set_data_seg_v2(dseg, wr->sg_list + i);
581 dseg++;
582 }
583
584 if (i < hr_qp->rq.max_gs) {
778cc5a8 585 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
586 dseg->addr = 0;
2d407888
WHX		 587 }
588
0009c2db 589 /* rq support inline data */
ecaaf1e2 590 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
591 sge_list = hr_qp->rq_inl_buf.wqe_list[ind].sg_list;
592 hr_qp->rq_inl_buf.wqe_list[ind].sge_cnt =
593 (u32)wr->num_sge;
594 for (i = 0; i < wr->num_sge; i++) {
595 sge_list[i].addr =
596 (void *)(u64)wr->sg_list[i].addr;
597 sge_list[i].len = wr->sg_list[i].length;
598 }
0009c2db 599 }
600
2d407888
WHX		 601 hr_qp->rq.wrid[ind] = wr->wr_id;
602
603 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
604 }
605
606out:
607 if (likely(nreq)) {
608 hr_qp->rq.head += nreq;
609 /* Memory barrier */
610 wmb();
611
472bc0fb 612 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff;
2d407888
WHX		 613 }
614 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
615
616 return ret;
617}
618
a04ff739
WHX		 619static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring)
620{
621 int ntu = ring->next_to_use;
622 int ntc = ring->next_to_clean;
623 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
624
625 return ring->desc_num - used - 1;
626}
627
628static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
629 struct hns_roce_v2_cmq_ring *ring)
630{
631 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
632
633 ring->desc = kzalloc(size, GFP_KERNEL);
634 if (!ring->desc)
635 return -ENOMEM;
636
637 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
638 DMA_BIDIRECTIONAL);
639 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
640 ring->desc_dma_addr = 0;
641 kfree(ring->desc);
642 ring->desc = NULL;
643 return -ENOMEM;
644 }
645
646 return 0;
647}
648
649static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
650 struct hns_roce_v2_cmq_ring *ring)
651{
652 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
653 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
654 DMA_BIDIRECTIONAL);
90e7a4d5 655
656 ring->desc_dma_addr = 0;
a04ff739
WHX		 657 kfree(ring->desc);
658}
659
660static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
661{
662 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
663 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
664 &priv->cmq.csq : &priv->cmq.crq;
665
666 ring->flag = ring_type;
667 ring->next_to_clean = 0;
668 ring->next_to_use = 0;
669
670 return hns_roce_alloc_cmq_desc(hr_dev, ring);
671}
672
673static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
674{
675 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
676 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
677 &priv->cmq.csq : &priv->cmq.crq;
678 dma_addr_t dma = ring->desc_dma_addr;
679
680 if (ring_type == TYPE_CSQ) {
681 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
682 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
683 upper_32_bits(dma));
684 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
685 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
686 HNS_ROCE_CMQ_ENABLE);
687 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
688 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
689 } else {
690 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
691 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
692 upper_32_bits(dma));
693 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
694 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
695 HNS_ROCE_CMQ_ENABLE);
696 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
697 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
698 }
699}
700
701static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
702{
703 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
704 int ret;
705
706 /* Setup the queue entries for command queue */
426c4146
LO		 707 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM;
708 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM;
a04ff739
WHX		 709
710 /* Setup the lock for command queue */
711 spin_lock_init(&priv->cmq.csq.lock);
712 spin_lock_init(&priv->cmq.crq.lock);
713
714 /* Setup Tx write back timeout */
715 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
716
717 /* Init CSQ */
718 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
719 if (ret) {
720 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret);
721 return ret;
722 }
723
724 /* Init CRQ */
725 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
726 if (ret) {
727 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret);
728 goto err_crq;
729 }
730
731 /* Init CSQ REG */
732 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
733
734 /* Init CRQ REG */
735 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
736
737 return 0;
738
739err_crq:
740 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
741
742 return ret;
743}
744
745static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
746{
747 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
748
749 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
750 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
751}
752
281d0ccf
CIK		 753static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
754 enum hns_roce_opcode_type opcode,
755 bool is_read)
a04ff739
WHX		 756{
757 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
758 desc->opcode = cpu_to_le16(opcode);
759 desc->flag =
760 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
761 if (is_read)
762 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
763 else
764 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
765}
766
767static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
768{
769 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
770 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
771
772 return head == priv->cmq.csq.next_to_use;
773}
774
775static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev)
776{
777 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
778 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
779 struct hns_roce_cmq_desc *desc;
780 u16 ntc = csq->next_to_clean;
781 u32 head;
782 int clean = 0;
783
784 desc = &csq->desc[ntc];
785 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
786 while (head != ntc) {
787 memset(desc, 0, sizeof(*desc));
788 ntc++;
789 if (ntc == csq->desc_num)
790 ntc = 0;
791 desc = &csq->desc[ntc];
792 clean++;
793 }
794 csq->next_to_clean = ntc;
795
796 return clean;
797}
798
281d0ccf
CIK		 799static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
800 struct hns_roce_cmq_desc *desc, int num)
a04ff739
WHX		 801{
802 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
803 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
804 struct hns_roce_cmq_desc *desc_to_use;
805 bool complete = false;
806 u32 timeout = 0;
807 int handle = 0;
808 u16 desc_ret;
809 int ret = 0;
810 int ntc;
811
cb7a94c9
WHX		 812 if (hr_dev->is_reset)
813 return 0;
814
a04ff739
WHX		 815 spin_lock_bh(&csq->lock);
816
817 if (num > hns_roce_cmq_space(csq)) {
818 spin_unlock_bh(&csq->lock);
819 return -EBUSY;
820 }
821
822 /*
823 * Record the location of desc in the cmq for this time
824 * which will be use for hardware to write back
825 */
826 ntc = csq->next_to_use;
827
828 while (handle < num) {
829 desc_to_use = &csq->desc[csq->next_to_use];
830 *desc_to_use = desc[handle];
831 dev_dbg(hr_dev->dev, "set cmq desc:\n");
832 csq->next_to_use++;
833 if (csq->next_to_use == csq->desc_num)
834 csq->next_to_use = 0;
835 handle++;
836 }
837
838 /* Write to hardware */
839 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
840
841 /*
842 * If the command is sync, wait for the firmware to write back,
843 * if multi descriptors to be sent, use the first one to check
844 */
845 if ((desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
846 do {
847 if (hns_roce_cmq_csq_done(hr_dev))
848 break;
988e175b 849 udelay(1);
a04ff739
WHX		 850 timeout++;
851 } while (timeout < priv->cmq.tx_timeout);
852 }
853
854 if (hns_roce_cmq_csq_done(hr_dev)) {
855 complete = true;
856 handle = 0;
857 while (handle < num) {
858 /* get the result of hardware write back */
859 desc_to_use = &csq->desc[ntc];
860 desc[handle] = *desc_to_use;
861 dev_dbg(hr_dev->dev, "Get cmq desc:\n");
862 desc_ret = desc[handle].retval;
863 if (desc_ret == CMD_EXEC_SUCCESS)
864 ret = 0;
865 else
866 ret = -EIO;
867 priv->cmq.last_status = desc_ret;
868 ntc++;
869 handle++;
870 if (ntc == csq->desc_num)
871 ntc = 0;
872 }
873 }
874
875 if (!complete)
876 ret = -EAGAIN;
877
878 /* clean the command send queue */
879 handle = hns_roce_cmq_csq_clean(hr_dev);
880 if (handle != num)
881 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n",
882 handle, num);
883
884 spin_unlock_bh(&csq->lock);
885
886 return ret;
887}
888
281d0ccf 889static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
cfc85f3e
WHX		 890{
891 struct hns_roce_query_version *resp;
892 struct hns_roce_cmq_desc desc;
893 int ret;
894
895 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
896 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
897 if (ret)
898 return ret;
899
900 resp = (struct hns_roce_query_version *)desc.data;
901 hr_dev->hw_rev = le32_to_cpu(resp->rocee_hw_version);
902 hr_dev->vendor_id = le32_to_cpu(resp->rocee_vendor_id);
903
904 return 0;
905}
906
907static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
908{
909 struct hns_roce_cfg_global_param *req;
910 struct hns_roce_cmq_desc desc;
911
912 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
913 false);
914
915 req = (struct hns_roce_cfg_global_param *)desc.data;
916 memset(req, 0, sizeof(*req));
917 roce_set_field(req->time_cfg_udp_port,
918 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M,
919 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8);
920 roce_set_field(req->time_cfg_udp_port,
921 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M,
922 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7);
923
924 return hns_roce_cmq_send(hr_dev, &desc, 1);
925}
926
927static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
928{
929 struct hns_roce_cmq_desc desc[2];
6b63597d 930 struct hns_roce_pf_res_a *req_a;
931 struct hns_roce_pf_res_b *req_b;
cfc85f3e
WHX		 932 int ret;
933 int i;
934
935 for (i = 0; i < 2; i++) {
936 hns_roce_cmq_setup_basic_desc(&desc[i],
937 HNS_ROCE_OPC_QUERY_PF_RES, true);
938
939 if (i == 0)
940 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
941 else
942 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
943 }
944
945 ret = hns_roce_cmq_send(hr_dev, desc, 2);
946 if (ret)
947 return ret;
948
6b63597d 949 req_a = (struct hns_roce_pf_res_a *)desc[0].data;
950 req_b = (struct hns_roce_pf_res_b *)desc[1].data;
cfc85f3e 951
6b63597d 952 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num,
cfc85f3e
WHX		 953 PF_RES_DATA_1_PF_QPC_BT_NUM_M,
954 PF_RES_DATA_1_PF_QPC_BT_NUM_S);
6b63597d 955 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num,
cfc85f3e
WHX		 956 PF_RES_DATA_2_PF_SRQC_BT_NUM_M,
957 PF_RES_DATA_2_PF_SRQC_BT_NUM_S);
6b63597d 958 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num,
cfc85f3e
WHX		 959 PF_RES_DATA_3_PF_CQC_BT_NUM_M,
960 PF_RES_DATA_3_PF_CQC_BT_NUM_S);
6b63597d 961 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num,
cfc85f3e
WHX		 962 PF_RES_DATA_4_PF_MPT_BT_NUM_M,
963 PF_RES_DATA_4_PF_MPT_BT_NUM_S);
964
6b63597d 965 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num,
966 PF_RES_DATA_3_PF_SL_NUM_M,
967 PF_RES_DATA_3_PF_SL_NUM_S);
968
cfc85f3e
WHX		 969 return 0;
970}
971
972static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
973{
974 struct hns_roce_cmq_desc desc[2];
975 struct hns_roce_vf_res_a *req_a;
976 struct hns_roce_vf_res_b *req_b;
977 int i;
978
979 req_a = (struct hns_roce_vf_res_a *)desc[0].data;
980 req_b = (struct hns_roce_vf_res_b *)desc[1].data;
981 memset(req_a, 0, sizeof(*req_a));
982 memset(req_b, 0, sizeof(*req_b));
983 for (i = 0; i < 2; i++) {
984 hns_roce_cmq_setup_basic_desc(&desc[i],
985 HNS_ROCE_OPC_ALLOC_VF_RES, false);
986
987 if (i == 0)
988 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
989 else
990 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
991
992 if (i == 0) {
993 roce_set_field(req_a->vf_qpc_bt_idx_num,
994 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M,
995 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0);
996 roce_set_field(req_a->vf_qpc_bt_idx_num,
997 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M,
998 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S,
999 HNS_ROCE_VF_QPC_BT_NUM);
1000
1001 roce_set_field(req_a->vf_srqc_bt_idx_num,
1002 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M,
1003 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0);
1004 roce_set_field(req_a->vf_srqc_bt_idx_num,
1005 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M,
1006 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S,
1007 HNS_ROCE_VF_SRQC_BT_NUM);
1008
1009 roce_set_field(req_a->vf_cqc_bt_idx_num,
1010 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M,
1011 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0);
1012 roce_set_field(req_a->vf_cqc_bt_idx_num,
1013 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M,
1014 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S,
1015 HNS_ROCE_VF_CQC_BT_NUM);
1016
1017 roce_set_field(req_a->vf_mpt_bt_idx_num,
1018 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M,
1019 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0);
1020 roce_set_field(req_a->vf_mpt_bt_idx_num,
1021 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M,
1022 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S,
1023 HNS_ROCE_VF_MPT_BT_NUM);
1024
1025 roce_set_field(req_a->vf_eqc_bt_idx_num,
1026 VF_RES_A_DATA_5_VF_EQC_IDX_M,
1027 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0);
1028 roce_set_field(req_a->vf_eqc_bt_idx_num,
1029 VF_RES_A_DATA_5_VF_EQC_NUM_M,
1030 VF_RES_A_DATA_5_VF_EQC_NUM_S,
1031 HNS_ROCE_VF_EQC_NUM);
1032 } else {
1033 roce_set_field(req_b->vf_smac_idx_num,
1034 VF_RES_B_DATA_1_VF_SMAC_IDX_M,
1035 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0);
1036 roce_set_field(req_b->vf_smac_idx_num,
1037 VF_RES_B_DATA_1_VF_SMAC_NUM_M,
1038 VF_RES_B_DATA_1_VF_SMAC_NUM_S,
1039 HNS_ROCE_VF_SMAC_NUM);
1040
1041 roce_set_field(req_b->vf_sgid_idx_num,
1042 VF_RES_B_DATA_2_VF_SGID_IDX_M,
1043 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0);
1044 roce_set_field(req_b->vf_sgid_idx_num,
1045 VF_RES_B_DATA_2_VF_SGID_NUM_M,
1046 VF_RES_B_DATA_2_VF_SGID_NUM_S,
1047 HNS_ROCE_VF_SGID_NUM);
1048
1049 roce_set_field(req_b->vf_qid_idx_sl_num,
1050 VF_RES_B_DATA_3_VF_QID_IDX_M,
1051 VF_RES_B_DATA_3_VF_QID_IDX_S, 0);
1052 roce_set_field(req_b->vf_qid_idx_sl_num,
1053 VF_RES_B_DATA_3_VF_SL_NUM_M,
1054 VF_RES_B_DATA_3_VF_SL_NUM_S,
1055 HNS_ROCE_VF_SL_NUM);
1056 }
1057 }
1058
1059 return hns_roce_cmq_send(hr_dev, desc, 2);
1060}
1061
a81fba28
WHX		 1062static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1063{
1064 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num;
1065 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;
1066 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;
1067 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;
1068 struct hns_roce_cfg_bt_attr *req;
1069 struct hns_roce_cmq_desc desc;
1070
1071 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1072 req = (struct hns_roce_cfg_bt_attr *)desc.data;
1073 memset(req, 0, sizeof(*req));
1074
1075 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
1076 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
5e6e78db 1077 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1078 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
1079 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
5e6e78db 1080 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1081 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
1082 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
1083 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
1084
1085 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
1086 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
5e6e78db 1087 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1088 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
1089 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
5e6e78db 1090 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1091 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
1092 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
1093 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
1094
1095 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
1096 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
5e6e78db 1097 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1098 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
1099 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
5e6e78db 1100 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1101 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
1102 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
1103 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
1104
1105 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
1106 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
5e6e78db 1107 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1108 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
1109 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
5e6e78db 1110 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1111 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
1112 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
1113 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
1114
1115 return hns_roce_cmq_send(hr_dev, &desc, 1);
1116}
1117
cfc85f3e
WHX		 1118static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
1119{
1120 struct hns_roce_caps *caps = &hr_dev->caps;
1121 int ret;
1122
1123 ret = hns_roce_cmq_query_hw_info(hr_dev);
1124 if (ret) {
1125 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n",
1126 ret);
1127 return ret;
1128 }
1129
1130 ret = hns_roce_config_global_param(hr_dev);
1131 if (ret) {
1132 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n",
1133 ret);
2349fdd4 1134 return ret;
cfc85f3e
WHX		 1135 }
1136
1137 /* Get pf resource owned by every pf */
1138 ret = hns_roce_query_pf_resource(hr_dev);
1139 if (ret) {
1140 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n",
1141 ret);
1142 return ret;
1143 }
1144
1145 ret = hns_roce_alloc_vf_resource(hr_dev);
1146 if (ret) {
1147 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n",
1148 ret);
1149 return ret;
1150 }
1151
1152 hr_dev->vendor_part_id = 0;
1153 hr_dev->sys_image_guid = 0;
1154
1155 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
1156 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
1157 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
1158 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
1159 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
1160 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1161 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
1162 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
1163 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
a5073d60
YL		 1164 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM;
1165 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM;
1166 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
cfc85f3e
WHX		 1167 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
1168 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1169 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
1170 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
1171 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1172 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1173 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1174 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1175 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
1176 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ;
1177 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
e92f2c18 1178 caps->trrl_entry_sz = HNS_ROCE_V2_TRRL_ENTRY_SZ;
cfc85f3e
WHX		 1179 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
1180 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1181 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
1182 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE;
1183 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1184 caps->reserved_lkey = 0;
1185 caps->reserved_pds = 0;
1186 caps->reserved_mrws = 1;
1187 caps->reserved_uars = 0;
1188 caps->reserved_cqs = 0;
1189
a25d13cb
SX		 1190 caps->qpc_ba_pg_sz = 0;
1191 caps->qpc_buf_pg_sz = 0;
1192 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1193 caps->srqc_ba_pg_sz = 0;
1194 caps->srqc_buf_pg_sz = 0;
1195 caps->srqc_hop_num = HNS_ROCE_HOP_NUM_0;
1196 caps->cqc_ba_pg_sz = 0;
1197 caps->cqc_buf_pg_sz = 0;
1198 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1199 caps->mpt_ba_pg_sz = 0;
1200 caps->mpt_buf_pg_sz = 0;
1201 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
ff795f71
WHX		 1202 caps->pbl_ba_pg_sz = 0;
1203 caps->pbl_buf_pg_sz = 0;
1204 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
6a93c77a
SX		 1205 caps->mtt_ba_pg_sz = 0;
1206 caps->mtt_buf_pg_sz = 0;
1207 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
1208 caps->cqe_ba_pg_sz = 0;
1209 caps->cqe_buf_pg_sz = 0;
1210 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
a5073d60
YL		 1211 caps->eqe_ba_pg_sz = 0;
1212 caps->eqe_buf_pg_sz = 0;
1213 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
6b63597d 1214 caps->tsq_buf_pg_sz = 0;
29a1fe5d 1215 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
a25d13cb 1216
023c1477 1217 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
0009c2db 1218 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
e088a685
YL		 1219 HNS_ROCE_CAP_FLAG_RQ_INLINE |
1220 HNS_ROCE_CAP_FLAG_RECORD_DB;
cfc85f3e 1221 caps->pkey_table_len[0] = 1;
b5ff0f61 1222 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
a5073d60
YL		 1223 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
1224 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
cfc85f3e
WHX		 1225 caps->local_ca_ack_delay = 0;
1226 caps->max_mtu = IB_MTU_4096;
1227
a81fba28
WHX		 1228 ret = hns_roce_v2_set_bt(hr_dev);
1229 if (ret)
1230 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n",
1231 ret);
1232
1233 return ret;
cfc85f3e
WHX		 1234}
1235
6b63597d 1236static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev,
1237 enum hns_roce_link_table_type type)
1238{
1239 struct hns_roce_cmq_desc desc[2];
1240 struct hns_roce_cfg_llm_a *req_a =
1241 (struct hns_roce_cfg_llm_a *)desc[0].data;
1242 struct hns_roce_cfg_llm_b *req_b =
1243 (struct hns_roce_cfg_llm_b *)desc[1].data;
1244 struct hns_roce_v2_priv *priv = hr_dev->priv;
1245 struct hns_roce_link_table *link_tbl;
1246 struct hns_roce_link_table_entry *entry;
1247 enum hns_roce_opcode_type opcode;
1248 u32 page_num;
1249 int i;
1250
1251 switch (type) {
1252 case TSQ_LINK_TABLE:
1253 link_tbl = &priv->tsq;
1254 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
1255 break;
ded58ff9 1256 case TPQ_LINK_TABLE:
1257 link_tbl = &priv->tpq;
1258 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM;
1259 break;
6b63597d 1260 default:
1261 return -EINVAL;
1262 }
1263
1264 page_num = link_tbl->npages;
1265 entry = link_tbl->table.buf;
1266 memset(req_a, 0, sizeof(*req_a));
1267 memset(req_b, 0, sizeof(*req_b));
1268
1269 for (i = 0; i < 2; i++) {
1270 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false);
1271
1272 if (i == 0)
1273 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1274 else
1275 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1276
1277 if (i == 0) {
1278 req_a->base_addr_l = link_tbl->table.map & 0xffffffff;
1279 req_a->base_addr_h = (link_tbl->table.map >> 32) &
1280 0xffffffff;
1281 roce_set_field(req_a->depth_pgsz_init_en,
1282 CFG_LLM_QUE_DEPTH_M,
1283 CFG_LLM_QUE_DEPTH_S,
1284 link_tbl->npages);
1285 roce_set_field(req_a->depth_pgsz_init_en,
1286 CFG_LLM_QUE_PGSZ_M,
1287 CFG_LLM_QUE_PGSZ_S,
1288 link_tbl->pg_sz);
1289 req_a->head_ba_l = entry[0].blk_ba0;
1290 req_a->head_ba_h_nxtptr = entry[0].blk_ba1_nxt_ptr;
1291 roce_set_field(req_a->head_ptr,
1292 CFG_LLM_HEAD_PTR_M,
1293 CFG_LLM_HEAD_PTR_S, 0);
1294 } else {
1295 req_b->tail_ba_l = entry[page_num - 1].blk_ba0;
1296 roce_set_field(req_b->tail_ba_h,
1297 CFG_LLM_TAIL_BA_H_M,
1298 CFG_LLM_TAIL_BA_H_S,
1299 entry[page_num - 1].blk_ba1_nxt_ptr &
1300 HNS_ROCE_LINK_TABLE_BA1_M);
1301 roce_set_field(req_b->tail_ptr,
1302 CFG_LLM_TAIL_PTR_M,
1303 CFG_LLM_TAIL_PTR_S,
1304 (entry[page_num - 2].blk_ba1_nxt_ptr &
1305 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >>
1306 HNS_ROCE_LINK_TABLE_NXT_PTR_S);
1307 }
1308 }
1309 roce_set_field(req_a->depth_pgsz_init_en,
1310 CFG_LLM_INIT_EN_M, CFG_LLM_INIT_EN_S, 1);
1311
1312 return hns_roce_cmq_send(hr_dev, desc, 2);
1313}
1314
1315static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev,
1316 enum hns_roce_link_table_type type)
1317{
1318 struct hns_roce_v2_priv *priv = hr_dev->priv;
1319 struct hns_roce_link_table *link_tbl;
1320 struct hns_roce_link_table_entry *entry;
1321 struct device *dev = hr_dev->dev;
1322 u32 buf_chk_sz;
1323 dma_addr_t t;
ded58ff9 1324 int func_num = 1;
6b63597d 1325 int pg_num_a;
1326 int pg_num_b;
1327 int pg_num;
1328 int size;
1329 int i;
1330
1331 switch (type) {
1332 case TSQ_LINK_TABLE:
1333 link_tbl = &priv->tsq;
1334 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT);
1335 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz;
1336 pg_num_b = hr_dev->caps.sl_num * 4 + 2;
1337 break;
ded58ff9 1338 case TPQ_LINK_TABLE:
1339 link_tbl = &priv->tpq;
1340 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT);
1341 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz;
1342 pg_num_b = 2 * 4 * func_num + 2;
1343 break;
6b63597d 1344 default:
1345 return -EINVAL;
1346 }
1347
1348 pg_num = max(pg_num_a, pg_num_b);
1349 size = pg_num * sizeof(struct hns_roce_link_table_entry);
1350
1351 link_tbl->table.buf = dma_alloc_coherent(dev, size,
1352 &link_tbl->table.map,
1353 GFP_KERNEL);
1354 if (!link_tbl->table.buf)
1355 goto out;
1356
1357 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list),
1358 GFP_KERNEL);
1359 if (!link_tbl->pg_list)
1360 goto err_kcalloc_failed;
1361
1362 entry = link_tbl->table.buf;
1363 for (i = 0; i < pg_num; ++i) {
1364 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz,
1365 &t, GFP_KERNEL);
1366 if (!link_tbl->pg_list[i].buf)
1367 goto err_alloc_buf_failed;
1368
1369 link_tbl->pg_list[i].map = t;
1370 memset(link_tbl->pg_list[i].buf, 0, buf_chk_sz);
1371
1372 entry[i].blk_ba0 = (t >> 12) & 0xffffffff;
1373 roce_set_field(entry[i].blk_ba1_nxt_ptr,
1374 HNS_ROCE_LINK_TABLE_BA1_M,
1375 HNS_ROCE_LINK_TABLE_BA1_S,
1376 t >> 44);
1377
1378 if (i < (pg_num - 1))
1379 roce_set_field(entry[i].blk_ba1_nxt_ptr,
1380 HNS_ROCE_LINK_TABLE_NXT_PTR_M,
1381 HNS_ROCE_LINK_TABLE_NXT_PTR_S,
1382 i + 1);
1383 }
1384 link_tbl->npages = pg_num;
1385 link_tbl->pg_sz = buf_chk_sz;
1386
1387 return hns_roce_config_link_table(hr_dev, type);
1388
1389err_alloc_buf_failed:
1390 for (i -= 1; i >= 0; i--)
1391 dma_free_coherent(dev, buf_chk_sz,
1392 link_tbl->pg_list[i].buf,
1393 link_tbl->pg_list[i].map);
1394 kfree(link_tbl->pg_list);
1395
1396err_kcalloc_failed:
1397 dma_free_coherent(dev, size, link_tbl->table.buf,
1398 link_tbl->table.map);
1399
1400out:
1401 return -ENOMEM;
1402}
1403
1404static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev,
1405 struct hns_roce_link_table *link_tbl)
1406{
1407 struct device *dev = hr_dev->dev;
1408 int size;
1409 int i;
1410
1411 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry);
1412
1413 for (i = 0; i < link_tbl->npages; ++i)
1414 if (link_tbl->pg_list[i].buf)
1415 dma_free_coherent(dev, link_tbl->pg_sz,
1416 link_tbl->pg_list[i].buf,
1417 link_tbl->pg_list[i].map);
1418 kfree(link_tbl->pg_list);
1419
1420 dma_free_coherent(dev, size, link_tbl->table.buf,
1421 link_tbl->table.map);
1422}
1423
1424static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
1425{
ded58ff9 1426 struct hns_roce_v2_priv *priv = hr_dev->priv;
6b63597d 1427 int ret;
1428
1429 /* TSQ includes SQ doorbell and ack doorbell */
1430 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE);
ded58ff9 1431 if (ret) {
6b63597d 1432 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret);
ded58ff9 1433 return ret;
1434 }
1435
1436 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE);
1437 if (ret) {
1438 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret);
1439 goto err_tpq_init_failed;
1440 }
1441
1442 return 0;
1443
1444err_tpq_init_failed:
1445 hns_roce_free_link_table(hr_dev, &priv->tsq);
6b63597d 1446
1447 return ret;
1448}
1449
1450static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
1451{
1452 struct hns_roce_v2_priv *priv = hr_dev->priv;
1453
ded58ff9 1454 hns_roce_free_link_table(hr_dev, &priv->tpq);
6b63597d 1455 hns_roce_free_link_table(hr_dev, &priv->tsq);
1456}
1457
a680f2f3
WHX		 1458static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
1459{
1460 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG);
1461
1462 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
1463}
1464
1465static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
1466{
1467 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG);
1468
1469 return status & HNS_ROCE_HW_MB_STATUS_MASK;
1470}
1471
1472static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1473 u64 out_param, u32 in_modifier, u8 op_modifier,
1474 u16 op, u16 token, int event)
1475{
1476 struct device *dev = hr_dev->dev;
cc4ed08b
BVA		 1477 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base +
1478 ROCEE_VF_MB_CFG0_REG);
a680f2f3
WHX		 1479 unsigned long end;
1480 u32 val0 = 0;
1481 u32 val1 = 0;
1482
1483 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
1484 while (hns_roce_v2_cmd_pending(hr_dev)) {
1485 if (time_after(jiffies, end)) {
1486 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
1487 (int)end);
1488 return -EAGAIN;
1489 }
1490 cond_resched();
1491 }
1492
1493 roce_set_field(val0, HNS_ROCE_VF_MB4_TAG_MASK,
1494 HNS_ROCE_VF_MB4_TAG_SHIFT, in_modifier);
1495 roce_set_field(val0, HNS_ROCE_VF_MB4_CMD_MASK,
1496 HNS_ROCE_VF_MB4_CMD_SHIFT, op);
1497 roce_set_field(val1, HNS_ROCE_VF_MB5_EVENT_MASK,
1498 HNS_ROCE_VF_MB5_EVENT_SHIFT, event);
1499 roce_set_field(val1, HNS_ROCE_VF_MB5_TOKEN_MASK,
1500 HNS_ROCE_VF_MB5_TOKEN_SHIFT, token);
1501
71591d12
AS		 1502 writeq(in_param, hcr + 0);
1503 writeq(out_param, hcr + 2);
a680f2f3
WHX		 1504
1505 /* Memory barrier */
1506 wmb();
1507
71591d12
AS		 1508 writel(val0, hcr + 4);
1509 writel(val1, hcr + 5);
a680f2f3
WHX		 1510
1511 mmiowb();
1512
1513 return 0;
1514}
1515
1516static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
1517 unsigned long timeout)
1518{
1519 struct device *dev = hr_dev->dev;
1520 unsigned long end = 0;
1521 u32 status;
1522
1523 end = msecs_to_jiffies(timeout) + jiffies;
1524 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
1525 cond_resched();
1526
1527 if (hns_roce_v2_cmd_pending(hr_dev)) {
1528 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1529 return -ETIMEDOUT;
1530 }
1531
1532 status = hns_roce_v2_cmd_complete(hr_dev);
1533 if (status != 0x1) {
1534 dev_err(dev, "mailbox status 0x%x!\n", status);
1535 return -EBUSY;
1536 }
1537
1538 return 0;
1539}
1540
4db134a3 1541static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev,
1542 int gid_index, const union ib_gid *gid,
1543 enum hns_roce_sgid_type sgid_type)
1544{
1545 struct hns_roce_cmq_desc desc;
1546 struct hns_roce_cfg_sgid_tb *sgid_tb =
1547 (struct hns_roce_cfg_sgid_tb *)desc.data;
1548 u32 *p;
1549
1550 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
1551
1552 roce_set_field(sgid_tb->table_idx_rsv,
1553 CFG_SGID_TB_TABLE_IDX_M,
1554 CFG_SGID_TB_TABLE_IDX_S, gid_index);
1555 roce_set_field(sgid_tb->vf_sgid_type_rsv,
1556 CFG_SGID_TB_VF_SGID_TYPE_M,
1557 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type);
1558
1559 p = (u32 *)&gid->raw[0];
1560 sgid_tb->vf_sgid_l = cpu_to_le32(*p);
1561
1562 p = (u32 *)&gid->raw[4];
1563 sgid_tb->vf_sgid_ml = cpu_to_le32(*p);
1564
1565 p = (u32 *)&gid->raw[8];
1566 sgid_tb->vf_sgid_mh = cpu_to_le32(*p);
1567
1568 p = (u32 *)&gid->raw[0xc];
1569 sgid_tb->vf_sgid_h = cpu_to_le32(*p);
1570
1571 return hns_roce_cmq_send(hr_dev, &desc, 1);
1572}
1573
b5ff0f61 1574static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
f4df9a7c 1575 int gid_index, const union ib_gid *gid,
b5ff0f61 1576 const struct ib_gid_attr *attr)
7afddafa 1577{
b5ff0f61 1578 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
4db134a3 1579 int ret;
7afddafa 1580
b5ff0f61
WHX		 1581 if (!gid || !attr)
1582 return -EINVAL;
1583
1584 if (attr->gid_type == IB_GID_TYPE_ROCE)
1585 sgid_type = GID_TYPE_FLAG_ROCE_V1;
1586
1587 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
1588 if (ipv6_addr_v4mapped((void *)gid))
1589 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
1590 else
1591 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
1592 }
1593
4db134a3 1594 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type);
1595 if (ret)
1596 dev_err(hr_dev->dev, "Configure sgid table failed(%d)!\n", ret);
b5ff0f61 1597
4db134a3 1598 return ret;
7afddafa
WHX		 1599}
1600
a74dc41d
WHX		 1601static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1602 u8 *addr)
7afddafa 1603{
e8e8b652 1604 struct hns_roce_cmq_desc desc;
1605 struct hns_roce_cfg_smac_tb *smac_tb =
1606 (struct hns_roce_cfg_smac_tb *)desc.data;
7afddafa
WHX		 1607 u16 reg_smac_h;
1608 u32 reg_smac_l;
e8e8b652 1609
1610 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
7afddafa
WHX		 1611
1612 reg_smac_l = *(u32 *)(&addr[0]);
e8e8b652 1613 reg_smac_h = *(u16 *)(&addr[4]);
7afddafa 1614
e8e8b652 1615 memset(smac_tb, 0, sizeof(*smac_tb));
1616 roce_set_field(smac_tb->tb_idx_rsv,
1617 CFG_SMAC_TB_IDX_M,
1618 CFG_SMAC_TB_IDX_S, phy_port);
1619 roce_set_field(smac_tb->vf_smac_h_rsv,
1620 CFG_SMAC_TB_VF_SMAC_H_M,
1621 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h);
1622 smac_tb->vf_smac_l = reg_smac_l;
a74dc41d 1623
e8e8b652 1624 return hns_roce_cmq_send(hr_dev, &desc, 1);
7afddafa
WHX		 1625}
1626
3958cc56
WHX		 1627static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1628 unsigned long mtpt_idx)
1629{
1630 struct hns_roce_v2_mpt_entry *mpt_entry;
1631 struct scatterlist *sg;
db270c41 1632 u64 page_addr;
3958cc56 1633 u64 *pages;
db270c41
WHX		 1634 int i, j;
1635 int len;
3958cc56 1636 int entry;
3958cc56
WHX		 1637
1638 mpt_entry = mb_buf;
1639 memset(mpt_entry, 0, sizeof(*mpt_entry));
1640
1641 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
1642 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
1643 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
1644 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num ==
1645 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
1646 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1647 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
5e6e78db
YL		 1648 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
1649 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3958cc56
WHX		 1650 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1651 V2_MPT_BYTE_4_PD_S, mr->pd);
1652 mpt_entry->byte_4_pd_hop_st = cpu_to_le32(mpt_entry->byte_4_pd_hop_st);
1653
1654 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
1655 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
1656 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 0);
1657 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S,
1658 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1659 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S, 0);
1660 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
1661 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1662 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
1663 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1664 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
1665 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1666 mpt_entry->byte_8_mw_cnt_en = cpu_to_le32(mpt_entry->byte_8_mw_cnt_en);
1667
1668 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
1669 mr->type == MR_TYPE_MR ? 0 : 1);
85e0274d 1670 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S,
1671 1);
3958cc56
WHX		 1672 mpt_entry->byte_12_mw_pa = cpu_to_le32(mpt_entry->byte_12_mw_pa);
1673
1674 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
1675 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
1676 mpt_entry->lkey = cpu_to_le32(mr->key);
1677 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
1678 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
1679
1680 if (mr->type == MR_TYPE_DMA)
1681 return 0;
1682
1683 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1684
1685 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1686 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
1687 V2_MPT_BYTE_48_PBL_BA_H_S,
1688 upper_32_bits(mr->pbl_ba >> 3));
1689 mpt_entry->byte_48_mode_ba = cpu_to_le32(mpt_entry->byte_48_mode_ba);
1690
1691 pages = (u64 *)__get_free_page(GFP_KERNEL);
1692 if (!pages)
1693 return -ENOMEM;
1694
1695 i = 0;
1696 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
db270c41
WHX		 1697 len = sg_dma_len(sg) >> PAGE_SHIFT;
1698 for (j = 0; j < len; ++j) {
1699 page_addr = sg_dma_address(sg) +
1700 (j << mr->umem->page_shift);
1701 pages[i] = page_addr >> 6;
1702
1703 /* Record the first 2 entry directly to MTPT table */
1704 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
1705 goto found;
1706 i++;
1707 }
3958cc56
WHX		 1708 }
1709
db270c41 1710found:
3958cc56
WHX		 1711 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
1712 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
1713 V2_MPT_BYTE_56_PA0_H_S,
1714 upper_32_bits(pages[0]));
1715 mpt_entry->byte_56_pa0_h = cpu_to_le32(mpt_entry->byte_56_pa0_h);
1716
1717 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
1718 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
1719 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
1720
1721 free_page((unsigned long)pages);
1722
1723 roce_set_field(mpt_entry->byte_64_buf_pa1,
1724 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
5e6e78db
YL		 1725 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
1726 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
3958cc56
WHX		 1727 mpt_entry->byte_64_buf_pa1 = cpu_to_le32(mpt_entry->byte_64_buf_pa1);
1728
1729 return 0;
1730}
1731
a2c80b7b
WHX		 1732static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
1733 struct hns_roce_mr *mr, int flags,
1734 u32 pdn, int mr_access_flags, u64 iova,
1735 u64 size, void *mb_buf)
1736{
1737 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
1738
1739 if (flags & IB_MR_REREG_PD) {
1740 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1741 V2_MPT_BYTE_4_PD_S, pdn);
1742 mr->pd = pdn;
1743 }
1744
1745 if (flags & IB_MR_REREG_ACCESS) {
1746 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
1747 V2_MPT_BYTE_8_BIND_EN_S,
1748 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
1749 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
1750 V2_MPT_BYTE_8_ATOMIC_EN_S,
1751 (mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0));
1752 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
1753 (mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0));
1754 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
1755 (mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1756 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
1757 (mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1758 }
1759
1760 if (flags & IB_MR_REREG_TRANS) {
1761 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova));
1762 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova));
1763 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
1764 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
1765
1766 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1767 mpt_entry->pbl_ba_l =
1768 cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1769 roce_set_field(mpt_entry->byte_48_mode_ba,
1770 V2_MPT_BYTE_48_PBL_BA_H_M,
1771 V2_MPT_BYTE_48_PBL_BA_H_S,
1772 upper_32_bits(mr->pbl_ba >> 3));
1773 mpt_entry->byte_48_mode_ba =
1774 cpu_to_le32(mpt_entry->byte_48_mode_ba);
1775
1776 mr->iova = iova;
1777 mr->size = size;
1778 }
1779
1780 return 0;
1781}
1782
93aa2187
WHX		 1783static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
1784{
1785 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
1786 n * HNS_ROCE_V2_CQE_ENTRY_SIZE);
1787}
1788
1789static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
1790{
1791 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
1792
1793 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1794 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^
1795 !!(n & (hr_cq->ib_cq.cqe + 1))) ? cqe : NULL;
1796}
1797
1798static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq)
1799{
1800 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
1801}
1802
1803static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1804{
86188a88 1805 *hr_cq->set_ci_db = cons_index & 0xffffff;
93aa2187
WHX		 1806}
1807
926a01dc
WHX		 1808static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1809 struct hns_roce_srq *srq)
1810{
1811 struct hns_roce_v2_cqe *cqe, *dest;
1812 u32 prod_index;
1813 int nfreed = 0;
1814 u8 owner_bit;
1815
1816 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
1817 ++prod_index) {
1818 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
1819 break;
1820 }
1821
1822 /*
1823 * Now backwards through the CQ, removing CQ entries
1824 * that match our QP by overwriting them with next entries.
1825 */
1826 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1827 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1828 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
1829 V2_CQE_BYTE_16_LCL_QPN_S) &
1830 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) {
1831 /* In v1 engine, not support SRQ */
1832 ++nfreed;
1833 } else if (nfreed) {
1834 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
1835 hr_cq->ib_cq.cqe);
1836 owner_bit = roce_get_bit(dest->byte_4,
1837 V2_CQE_BYTE_4_OWNER_S);
1838 memcpy(dest, cqe, sizeof(*cqe));
1839 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S,
1840 owner_bit);
1841 }
1842 }
1843
1844 if (nfreed) {
1845 hr_cq->cons_index += nfreed;
1846 /*
1847 * Make sure update of buffer contents is done before
1848 * updating consumer index.
1849 */
1850 wmb();
1851 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
1852 }
1853}
1854
1855static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1856 struct hns_roce_srq *srq)
1857{
1858 spin_lock_irq(&hr_cq->lock);
1859 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
1860 spin_unlock_irq(&hr_cq->lock);
1861}
1862
93aa2187
WHX		 1863static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
1864 struct hns_roce_cq *hr_cq, void *mb_buf,
1865 u64 *mtts, dma_addr_t dma_handle, int nent,
1866 u32 vector)
1867{
1868 struct hns_roce_v2_cq_context *cq_context;
1869
1870 cq_context = mb_buf;
1871 memset(cq_context, 0, sizeof(*cq_context));
1872
1873 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M,
1874 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID);
a5073d60
YL		 1875 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M,
1876 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE);
93aa2187
WHX		 1877 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M,
1878 V2_CQC_BYTE_4_SHIFT_S, ilog2((unsigned int)nent));
1879 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M,
1880 V2_CQC_BYTE_4_CEQN_S, vector);
1881 cq_context->byte_4_pg_ceqn = cpu_to_le32(cq_context->byte_4_pg_ceqn);
1882
1883 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
1884 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
1885
1886 cq_context->cqe_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
1887 cq_context->cqe_cur_blk_addr =
1888 cpu_to_le32(cq_context->cqe_cur_blk_addr);
1889
1890 roce_set_field(cq_context->byte_16_hop_addr,
1891 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M,
1892 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S,
1893 cpu_to_le32((mtts[0]) >> (32 + PAGE_ADDR_SHIFT)));
1894 roce_set_field(cq_context->byte_16_hop_addr,
1895 V2_CQC_BYTE_16_CQE_HOP_NUM_M,
1896 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num ==
1897 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
1898
1899 cq_context->cqe_nxt_blk_addr = (u32)(mtts[1] >> PAGE_ADDR_SHIFT);
1900 roce_set_field(cq_context->byte_24_pgsz_addr,
1901 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M,
1902 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S,
1903 cpu_to_le32((mtts[1]) >> (32 + PAGE_ADDR_SHIFT)));
1904 roce_set_field(cq_context->byte_24_pgsz_addr,
1905 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
1906 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
5e6e78db 1907 hr_dev->caps.cqe_ba_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 1908 roce_set_field(cq_context->byte_24_pgsz_addr,
1909 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
1910 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
5e6e78db 1911 hr_dev->caps.cqe_buf_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 1912
1913 cq_context->cqe_ba = (u32)(dma_handle >> 3);
1914
1915 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
1916 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
a5073d60 1917
9b44703d
YL		 1918 if (hr_cq->db_en)
1919 roce_set_bit(cq_context->byte_44_db_record,
1920 V2_CQC_BYTE_44_DB_RECORD_EN_S, 1);
1921
1922 roce_set_field(cq_context->byte_44_db_record,
1923 V2_CQC_BYTE_44_DB_RECORD_ADDR_M,
1924 V2_CQC_BYTE_44_DB_RECORD_ADDR_S,
1925 ((u32)hr_cq->db.dma) >> 1);
1926 cq_context->db_record_addr = hr_cq->db.dma >> 32;
1927
a5073d60
YL		 1928 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
1929 V2_CQC_BYTE_56_CQ_MAX_CNT_M,
1930 V2_CQC_BYTE_56_CQ_MAX_CNT_S,
1931 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
1932 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
1933 V2_CQC_BYTE_56_CQ_PERIOD_M,
1934 V2_CQC_BYTE_56_CQ_PERIOD_S,
1935 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
93aa2187
WHX		 1936}
1937
1938static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
1939 enum ib_cq_notify_flags flags)
1940{
1941 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
1942 u32 notification_flag;
1943 u32 doorbell[2];
1944
1945 doorbell[0] = 0;
1946 doorbell[1] = 0;
1947
1948 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
1949 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
1950 /*
1951 * flags = 0; Notification Flag = 1, next
1952 * flags = 1; Notification Flag = 0, solocited
1953 */
1954 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S,
1955 hr_cq->cqn);
1956 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S,
1957 HNS_ROCE_V2_CQ_DB_NTR);
1958 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M,
1959 V2_CQ_DB_PARAMETER_CONS_IDX_S,
1960 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
1961 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M,
26beb85f 1962 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3);
93aa2187
WHX		 1963 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S,
1964 notification_flag);
1965
1966 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
1967
1968 return 0;
1969}
1970
0009c2db 1971static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
1972 struct hns_roce_qp **cur_qp,
1973 struct ib_wc *wc)
1974{
1975 struct hns_roce_rinl_sge *sge_list;
1976 u32 wr_num, wr_cnt, sge_num;
1977 u32 sge_cnt, data_len, size;
1978 void *wqe_buf;
1979
1980 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M,
1981 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff;
1982 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1);
1983
1984 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list;
1985 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
1986 wqe_buf = get_recv_wqe(*cur_qp, wr_cnt);
1987 data_len = wc->byte_len;
1988
1989 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
1990 size = min(sge_list[sge_cnt].len, data_len);
1991 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
1992
1993 data_len -= size;
1994 wqe_buf += size;
1995 }
1996
1997 if (data_len) {
1998 wc->status = IB_WC_LOC_LEN_ERR;
1999 return -EAGAIN;
2000 }
2001
2002 return 0;
2003}
2004
93aa2187
WHX		 2005static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
2006 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2007{
2008 struct hns_roce_dev *hr_dev;
2009 struct hns_roce_v2_cqe *cqe;
2010 struct hns_roce_qp *hr_qp;
2011 struct hns_roce_wq *wq;
2012 int is_send;
2013 u16 wqe_ctr;
2014 u32 opcode;
2015 u32 status;
2016 int qpn;
0009c2db 2017 int ret;
93aa2187
WHX		 2018
2019 /* Find cqe according to consumer index */
2020 cqe = next_cqe_sw_v2(hr_cq);
2021 if (!cqe)
2022 return -EAGAIN;
2023
2024 ++hr_cq->cons_index;
2025 /* Memory barrier */
2026 rmb();
2027
2028 /* 0->SQ, 1->RQ */
2029 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
2030
2031 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2032 V2_CQE_BYTE_16_LCL_QPN_S);
2033
2034 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2035 hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2036 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2037 if (unlikely(!hr_qp)) {
2038 dev_err(hr_dev->dev, "CQ %06lx with entry for unknown QPN %06x\n",
2039 hr_cq->cqn, (qpn & HNS_ROCE_V2_CQE_QPN_MASK));
2040 return -EINVAL;
2041 }
2042 *cur_qp = hr_qp;
2043 }
2044
2045 wc->qp = &(*cur_qp)->ibqp;
2046 wc->vendor_err = 0;
2047
2048 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M,
2049 V2_CQE_BYTE_4_STATUS_S);
2050 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) {
2051 case HNS_ROCE_CQE_V2_SUCCESS:
2052 wc->status = IB_WC_SUCCESS;
2053 break;
2054 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR:
2055 wc->status = IB_WC_LOC_LEN_ERR;
2056 break;
2057 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR:
2058 wc->status = IB_WC_LOC_QP_OP_ERR;
2059 break;
2060 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR:
2061 wc->status = IB_WC_LOC_PROT_ERR;
2062 break;
2063 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR:
2064 wc->status = IB_WC_WR_FLUSH_ERR;
2065 break;
2066 case HNS_ROCE_CQE_V2_MW_BIND_ERR:
2067 wc->status = IB_WC_MW_BIND_ERR;
2068 break;
2069 case HNS_ROCE_CQE_V2_BAD_RESP_ERR:
2070 wc->status = IB_WC_BAD_RESP_ERR;
2071 break;
2072 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR:
2073 wc->status = IB_WC_LOC_ACCESS_ERR;
2074 break;
2075 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR:
2076 wc->status = IB_WC_REM_INV_REQ_ERR;
2077 break;
2078 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR:
2079 wc->status = IB_WC_REM_ACCESS_ERR;
2080 break;
2081 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR:
2082 wc->status = IB_WC_REM_OP_ERR;
2083 break;
2084 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR:
2085 wc->status = IB_WC_RETRY_EXC_ERR;
2086 break;
2087 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR:
2088 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2089 break;
2090 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR:
2091 wc->status = IB_WC_REM_ABORT_ERR;
2092 break;
2093 default:
2094 wc->status = IB_WC_GENERAL_ERR;
2095 break;
2096 }
2097
2098 /* CQE status error, directly return */
2099 if (wc->status != IB_WC_SUCCESS)
2100 return 0;
2101
2102 if (is_send) {
2103 wc->wc_flags = 0;
2104 /* SQ corresponding to CQE */
2105 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
2106 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
2107 case HNS_ROCE_SQ_OPCODE_SEND:
2108 wc->opcode = IB_WC_SEND;
2109 break;
2110 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV:
2111 wc->opcode = IB_WC_SEND;
2112 break;
2113 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM:
2114 wc->opcode = IB_WC_SEND;
2115 wc->wc_flags |= IB_WC_WITH_IMM;
2116 break;
2117 case HNS_ROCE_SQ_OPCODE_RDMA_READ:
2118 wc->opcode = IB_WC_RDMA_READ;
2119 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2120 break;
2121 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE:
2122 wc->opcode = IB_WC_RDMA_WRITE;
2123 break;
2124 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM:
2125 wc->opcode = IB_WC_RDMA_WRITE;
2126 wc->wc_flags |= IB_WC_WITH_IMM;
2127 break;
2128 case HNS_ROCE_SQ_OPCODE_LOCAL_INV:
2129 wc->opcode = IB_WC_LOCAL_INV;
2130 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2131 break;
2132 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP:
2133 wc->opcode = IB_WC_COMP_SWAP;
2134 wc->byte_len = 8;
2135 break;
2136 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD:
2137 wc->opcode = IB_WC_FETCH_ADD;
2138 wc->byte_len = 8;
2139 break;
2140 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP:
2141 wc->opcode = IB_WC_MASKED_COMP_SWAP;
2142 wc->byte_len = 8;
2143 break;
2144 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD:
2145 wc->opcode = IB_WC_MASKED_FETCH_ADD;
2146 wc->byte_len = 8;
2147 break;
2148 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR:
2149 wc->opcode = IB_WC_REG_MR;
2150 break;
2151 case HNS_ROCE_SQ_OPCODE_BIND_MW:
2152 wc->opcode = IB_WC_REG_MR;
2153 break;
2154 default:
2155 wc->status = IB_WC_GENERAL_ERR;
2156 break;
2157 }
2158
2159 wq = &(*cur_qp)->sq;
2160 if ((*cur_qp)->sq_signal_bits) {
2161 /*
2162 * If sg_signal_bit is 1,
2163 * firstly tail pointer updated to wqe
2164 * which current cqe correspond to
2165 */
2166 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
2167 V2_CQE_BYTE_4_WQE_INDX_M,
2168 V2_CQE_BYTE_4_WQE_INDX_S);
2169 wq->tail += (wqe_ctr - (u16)wq->tail) &
2170 (wq->wqe_cnt - 1);
2171 }
2172
2173 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2174 ++wq->tail;
2175 } else {
2176 /* RQ correspond to CQE */
2177 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2178
2179 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
2180 V2_CQE_BYTE_4_OPCODE_S);
2181 switch (opcode & 0x1f) {
2182 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
2183 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2184 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 2185 wc->ex.imm_data =
2186 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 2187 break;
2188 case HNS_ROCE_V2_OPCODE_SEND:
2189 wc->opcode = IB_WC_RECV;
2190 wc->wc_flags = 0;
2191 break;
2192 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
2193 wc->opcode = IB_WC_RECV;
2194 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 2195 wc->ex.imm_data =
2196 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 2197 break;
2198 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
2199 wc->opcode = IB_WC_RECV;
2200 wc->wc_flags = IB_WC_WITH_INVALIDATE;
ccb8a29e 2201 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
93aa2187
WHX		 2202 break;
2203 default:
2204 wc->status = IB_WC_GENERAL_ERR;
2205 break;
2206 }
2207
0009c2db 2208 if ((wc->qp->qp_type == IB_QPT_RC ||
2209 wc->qp->qp_type == IB_QPT_UC) &&
2210 (opcode == HNS_ROCE_V2_OPCODE_SEND ||
2211 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
2212 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
2213 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) {
2214 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc);
2215 if (ret)
2216 return -EAGAIN;
2217 }
2218
93aa2187
WHX		 2219 /* Update tail pointer, record wr_id */
2220 wq = &(*cur_qp)->rq;
2221 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2222 ++wq->tail;
2223
2224 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
2225 V2_CQE_BYTE_32_SL_S);
2226 wc->src_qp = (u8)roce_get_field(cqe->byte_32,
2227 V2_CQE_BYTE_32_RMT_QPN_M,
2228 V2_CQE_BYTE_32_RMT_QPN_S);
2229 wc->wc_flags |= (roce_get_bit(cqe->byte_32,
2230 V2_CQE_BYTE_32_GRH_S) ?
2231 IB_WC_GRH : 0);
6c1f08b3 2232 wc->port_num = roce_get_field(cqe->byte_32,
2233 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S);
2234 wc->pkey_index = 0;
2eade675 2235 memcpy(wc->smac, cqe->smac, 4);
2236 wc->smac[4] = roce_get_field(cqe->byte_28,
2237 V2_CQE_BYTE_28_SMAC_4_M,
2238 V2_CQE_BYTE_28_SMAC_4_S);
2239 wc->smac[5] = roce_get_field(cqe->byte_28,
2240 V2_CQE_BYTE_28_SMAC_5_M,
2241 V2_CQE_BYTE_28_SMAC_5_S);
2242 wc->vlan_id = 0xffff;
2243 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
2244 wc->network_hdr_type = roce_get_field(cqe->byte_28,
2245 V2_CQE_BYTE_28_PORT_TYPE_M,
2246 V2_CQE_BYTE_28_PORT_TYPE_S);
93aa2187
WHX		 2247 }
2248
2249 return 0;
2250}
2251
2252static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
2253 struct ib_wc *wc)
2254{
2255 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2256 struct hns_roce_qp *cur_qp = NULL;
2257 unsigned long flags;
2258 int npolled;
2259
2260 spin_lock_irqsave(&hr_cq->lock, flags);
2261
2262 for (npolled = 0; npolled < num_entries; ++npolled) {
2263 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
2264 break;
2265 }
2266
2267 if (npolled) {
2268 /* Memory barrier */
2269 wmb();
2270 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2271 }
2272
2273 spin_unlock_irqrestore(&hr_cq->lock, flags);
2274
2275 return npolled;
2276}
2277
a81fba28
WHX		 2278static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
2279 struct hns_roce_hem_table *table, int obj,
2280 int step_idx)
2281{
2282 struct device *dev = hr_dev->dev;
2283 struct hns_roce_cmd_mailbox *mailbox;
2284 struct hns_roce_hem_iter iter;
2285 struct hns_roce_hem_mhop mhop;
2286 struct hns_roce_hem *hem;
2287 unsigned long mhop_obj = obj;
2288 int i, j, k;
2289 int ret = 0;
2290 u64 hem_idx = 0;
2291 u64 l1_idx = 0;
2292 u64 bt_ba = 0;
2293 u32 chunk_ba_num;
2294 u32 hop_num;
2295 u16 op = 0xff;
2296
2297 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
2298 return 0;
2299
2300 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
2301 i = mhop.l0_idx;
2302 j = mhop.l1_idx;
2303 k = mhop.l2_idx;
2304 hop_num = mhop.hop_num;
2305 chunk_ba_num = mhop.bt_chunk_size / 8;
2306
2307 if (hop_num == 2) {
2308 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
2309 k;
2310 l1_idx = i * chunk_ba_num + j;
2311 } else if (hop_num == 1) {
2312 hem_idx = i * chunk_ba_num + j;
2313 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
2314 hem_idx = i;
2315 }
2316
2317 switch (table->type) {
2318 case HEM_TYPE_QPC:
2319 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
2320 break;
2321 case HEM_TYPE_MTPT:
2322 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
2323 break;
2324 case HEM_TYPE_CQC:
2325 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
2326 break;
2327 case HEM_TYPE_SRQC:
2328 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
2329 break;
2330 default:
2331 dev_warn(dev, "Table %d not to be written by mailbox!\n",
2332 table->type);
2333 return 0;
2334 }
2335 op += step_idx;
2336
2337 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2338 if (IS_ERR(mailbox))
2339 return PTR_ERR(mailbox);
2340
2341 if (check_whether_last_step(hop_num, step_idx)) {
2342 hem = table->hem[hem_idx];
2343 for (hns_roce_hem_first(hem, &iter);
2344 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
2345 bt_ba = hns_roce_hem_addr(&iter);
2346
2347 /* configure the ba, tag, and op */
2348 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma,
2349 obj, 0, op,
2350 HNS_ROCE_CMD_TIMEOUT_MSECS);
2351 }
2352 } else {
2353 if (step_idx == 0)
2354 bt_ba = table->bt_l0_dma_addr[i];
2355 else if (step_idx == 1 && hop_num == 2)
2356 bt_ba = table->bt_l1_dma_addr[l1_idx];
2357
2358 /* configure the ba, tag, and op */
2359 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,
2360 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);
2361 }
2362
2363 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2364 return ret;
2365}
2366
2367static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
2368 struct hns_roce_hem_table *table, int obj,
2369 int step_idx)
2370{
2371 struct device *dev = hr_dev->dev;
2372 struct hns_roce_cmd_mailbox *mailbox;
2373 int ret = 0;
2374 u16 op = 0xff;
2375
2376 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
2377 return 0;
2378
2379 switch (table->type) {
2380 case HEM_TYPE_QPC:
2381 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
2382 break;
2383 case HEM_TYPE_MTPT:
2384 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
2385 break;
2386 case HEM_TYPE_CQC:
2387 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
2388 break;
2389 case HEM_TYPE_SRQC:
2390 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
2391 break;
2392 default:
2393 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n",
2394 table->type);
2395 return 0;
2396 }
2397 op += step_idx;
2398
2399 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2400 if (IS_ERR(mailbox))
2401 return PTR_ERR(mailbox);
2402
2403 /* configure the tag and op */
2404 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
2405 HNS_ROCE_CMD_TIMEOUT_MSECS);
2406
2407 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2408 return ret;
2409}
2410
926a01dc
WHX		 2411static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
2412 struct hns_roce_mtt *mtt,
2413 enum ib_qp_state cur_state,
2414 enum ib_qp_state new_state,
2415 struct hns_roce_v2_qp_context *context,
2416 struct hns_roce_qp *hr_qp)
2417{
2418 struct hns_roce_cmd_mailbox *mailbox;
2419 int ret;
2420
2421 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2422 if (IS_ERR(mailbox))
2423 return PTR_ERR(mailbox);
2424
2425 memcpy(mailbox->buf, context, sizeof(*context) * 2);
2426
2427 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2428 HNS_ROCE_CMD_MODIFY_QPC,
2429 HNS_ROCE_CMD_TIMEOUT_MSECS);
2430
2431 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2432
2433 return ret;
2434}
2435
ace1c541 2436static void set_access_flags(struct hns_roce_qp *hr_qp,
2437 struct hns_roce_v2_qp_context *context,
2438 struct hns_roce_v2_qp_context *qpc_mask,
2439 const struct ib_qp_attr *attr, int attr_mask)
2440{
2441 u8 dest_rd_atomic;
2442 u32 access_flags;
2443
c2799119 2444 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
ace1c541 2445 attr->max_dest_rd_atomic : hr_qp->resp_depth;
2446
c2799119 2447 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
ace1c541 2448 attr->qp_access_flags : hr_qp->atomic_rd_en;
2449
2450 if (!dest_rd_atomic)
2451 access_flags &= IB_ACCESS_REMOTE_WRITE;
2452
2453 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2454 !!(access_flags & IB_ACCESS_REMOTE_READ));
2455 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0);
2456
2457 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2458 !!(access_flags & IB_ACCESS_REMOTE_WRITE));
2459 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0);
2460
2461 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2462 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
2463 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0);
2464}
2465
926a01dc
WHX		 2466static void modify_qp_reset_to_init(struct ib_qp *ibqp,
2467 const struct ib_qp_attr *attr,
0fa95a9a 2468 int attr_mask,
926a01dc
WHX		 2469 struct hns_roce_v2_qp_context *context,
2470 struct hns_roce_v2_qp_context *qpc_mask)
2471{
ecaaf1e2 2472 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
926a01dc
WHX		 2473 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2474
2475 /*
2476 * In v2 engine, software pass context and context mask to hardware
2477 * when modifying qp. If software need modify some fields in context,
2478 * we should set all bits of the relevant fields in context mask to
2479 * 0 at the same time, else set them to 0x1.
2480 */
2481 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2482 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
2483 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2484 V2_QPC_BYTE_4_TST_S, 0);
2485
0fa95a9a 2486 if (ibqp->qp_type == IB_QPT_GSI)
2487 roce_set_field(context->byte_4_sqpn_tst,
2488 V2_QPC_BYTE_4_SGE_SHIFT_M,
2489 V2_QPC_BYTE_4_SGE_SHIFT_S,
2490 ilog2((unsigned int)hr_qp->sge.sge_cnt));
2491 else
2492 roce_set_field(context->byte_4_sqpn_tst,
2493 V2_QPC_BYTE_4_SGE_SHIFT_M,
2494 V2_QPC_BYTE_4_SGE_SHIFT_S,
2495 hr_qp->sq.max_gs > 2 ?
2496 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
2497
926a01dc
WHX		 2498 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
2499 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
2500
2501 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2502 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
2503 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2504 V2_QPC_BYTE_4_SQPN_S, 0);
2505
2506 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2507 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
2508 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2509 V2_QPC_BYTE_16_PD_S, 0);
2510
2511 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
2512 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs));
2513 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
2514 V2_QPC_BYTE_20_RQWS_S, 0);
2515
2516 roce_set_field(context->byte_20_smac_sgid_idx,
2517 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
2518 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2519 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2520 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
2521
2522 roce_set_field(context->byte_20_smac_sgid_idx,
2523 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
2524 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2525 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2526 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
2527
2528 /* No VLAN need to set 0xFFF */
c8e46f8d
LO		 2529 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
2530 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff);
2531 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
2532 V2_QPC_BYTE_24_VLAN_ID_S, 0);
926a01dc
WHX		 2533
2534 /*
2535 * Set some fields in context to zero, Because the default values
2536 * of all fields in context are zero, we need not set them to 0 again.
2537 * but we should set the relevant fields of context mask to 0.
2538 */
2539 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_TX_ERR_S, 0);
2540 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_RX_ERR_S, 0);
2541 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_TX_ERR_S, 0);
2542 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_RX_ERR_S, 0);
2543
2544 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_MAPID_M,
2545 V2_QPC_BYTE_60_MAPID_S, 0);
2546
2547 roce_set_bit(qpc_mask->byte_60_qpst_mapid,
2548 V2_QPC_BYTE_60_INNER_MAP_IND_S, 0);
2549 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_MAP_IND_S,
2550 0);
2551 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_RQ_MAP_IND_S,
2552 0);
2553 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_EXT_MAP_IND_S,
2554 0);
2555 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_RLS_IND_S,
2556 0);
2557 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_EXT_IND_S,
2558 0);
2559 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CNP_TX_FLAG_S, 0);
2560 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CE_FLAG_S, 0);
2561
0fa95a9a 2562 if (attr_mask & IB_QP_QKEY) {
2563 context->qkey_xrcd = attr->qkey;
2564 qpc_mask->qkey_xrcd = 0;
2565 hr_qp->qkey = attr->qkey;
2566 }
2567
e088a685
YL		 2568 if (hr_qp->rdb_en) {
2569 roce_set_bit(context->byte_68_rq_db,
2570 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1);
2571 roce_set_bit(qpc_mask->byte_68_rq_db,
2572 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 0);
2573 }
2574
2575 roce_set_field(context->byte_68_rq_db,
2576 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
2577 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S,
2578 ((u32)hr_qp->rdb.dma) >> 1);
2579 roce_set_field(qpc_mask->byte_68_rq_db,
2580 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
2581 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 0);
2582 context->rq_db_record_addr = hr_qp->rdb.dma >> 32;
2583 qpc_mask->rq_db_record_addr = 0;
2584
ecaaf1e2 2585 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
2586 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
926a01dc
WHX		 2587 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 0);
2588
2589 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2590 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
2591 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2592 V2_QPC_BYTE_80_RX_CQN_S, 0);
2593 if (ibqp->srq) {
2594 roce_set_field(context->byte_76_srqn_op_en,
2595 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
2596 to_hr_srq(ibqp->srq)->srqn);
2597 roce_set_field(qpc_mask->byte_76_srqn_op_en,
2598 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
2599 roce_set_bit(context->byte_76_srqn_op_en,
2600 V2_QPC_BYTE_76_SRQ_EN_S, 1);
2601 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
2602 V2_QPC_BYTE_76_SRQ_EN_S, 0);
2603 }
2604
2605 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
2606 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
2607 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
2608 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
2609 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
2610 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
2611
2612 roce_set_field(qpc_mask->byte_92_srq_info, V2_QPC_BYTE_92_SRQ_INFO_M,
2613 V2_QPC_BYTE_92_SRQ_INFO_S, 0);
2614
2615 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
2616 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
2617
2618 roce_set_field(qpc_mask->byte_104_rq_sge,
2619 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M,
2620 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S, 0);
2621
2622 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
2623 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
2624 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
2625 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
2626 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
2627 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
2628 V2_QPC_BYTE_108_RX_REQ_RNR_S, 0);
2629
2630 qpc_mask->rq_rnr_timer = 0;
2631 qpc_mask->rx_msg_len = 0;
2632 qpc_mask->rx_rkey_pkt_info = 0;
2633 qpc_mask->rx_va = 0;
2634
2635 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
2636 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
2637 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
2638 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
2639
2640 roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RSVD_RAQ_MAP_S, 0);
2641 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M,
2642 V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S, 0);
2643 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M,
2644 V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S, 0);
2645
2646 roce_set_field(qpc_mask->byte_144_raq,
2647 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M,
2648 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S, 0);
2649 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S,
2650 0);
2651 roce_set_field(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_CREDIT_M,
2652 V2_QPC_BYTE_144_RAQ_CREDIT_S, 0);
2653 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RESP_RTY_FLG_S, 0);
2654
2655 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RQ_MSN_M,
2656 V2_QPC_BYTE_148_RQ_MSN_S, 0);
2657 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RAQ_SYNDROME_M,
2658 V2_QPC_BYTE_148_RAQ_SYNDROME_S, 0);
2659
2660 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
2661 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
2662 roce_set_field(qpc_mask->byte_152_raq,
2663 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M,
2664 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S, 0);
2665
2666 roce_set_field(qpc_mask->byte_156_raq, V2_QPC_BYTE_156_RAQ_USE_PKTN_M,
2667 V2_QPC_BYTE_156_RAQ_USE_PKTN_S, 0);
2668
2669 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
2670 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
2671 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
2672 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
2673 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M,
2674 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S, 0);
2675
2676 roce_set_field(context->byte_168_irrl_idx,
2677 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2678 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S,
2679 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2680 roce_set_field(qpc_mask->byte_168_irrl_idx,
2681 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2682 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0);
2683
2684 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2685 V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0);
b5fddb7c 2686 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2687 V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0);
926a01dc
WHX		 2688 roce_set_field(qpc_mask->byte_168_irrl_idx,
2689 V2_QPC_BYTE_168_IRRL_IDX_LSB_M,
2690 V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0);
2691
2692 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
2693 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4);
2694 roce_set_field(qpc_mask->byte_172_sq_psn,
2695 V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
2696 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0);
2697
2698 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_MSG_RNR_FLG_S,
2699 0);
2700
2701 roce_set_field(qpc_mask->byte_176_msg_pktn,
2702 V2_QPC_BYTE_176_MSG_USE_PKTN_M,
2703 V2_QPC_BYTE_176_MSG_USE_PKTN_S, 0);
2704 roce_set_field(qpc_mask->byte_176_msg_pktn,
2705 V2_QPC_BYTE_176_IRRL_HEAD_PRE_M,
2706 V2_QPC_BYTE_176_IRRL_HEAD_PRE_S, 0);
2707
2708 roce_set_field(qpc_mask->byte_184_irrl_idx,
2709 V2_QPC_BYTE_184_IRRL_IDX_MSB_M,
2710 V2_QPC_BYTE_184_IRRL_IDX_MSB_S, 0);
2711
2712 qpc_mask->cur_sge_offset = 0;
2713
2714 roce_set_field(qpc_mask->byte_192_ext_sge,
2715 V2_QPC_BYTE_192_CUR_SGE_IDX_M,
2716 V2_QPC_BYTE_192_CUR_SGE_IDX_S, 0);
2717 roce_set_field(qpc_mask->byte_192_ext_sge,
2718 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M,
2719 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S, 0);
2720
2721 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
2722 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
2723
2724 roce_set_field(qpc_mask->byte_200_sq_max, V2_QPC_BYTE_200_SQ_MAX_IDX_M,
2725 V2_QPC_BYTE_200_SQ_MAX_IDX_S, 0);
2726 roce_set_field(qpc_mask->byte_200_sq_max,
2727 V2_QPC_BYTE_200_LCL_OPERATED_CNT_M,
2728 V2_QPC_BYTE_200_LCL_OPERATED_CNT_S, 0);
2729
2730 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RNR_FLG_S, 0);
2731 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RTY_FLG_S, 0);
2732
2733 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
2734 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
2735
2736 qpc_mask->sq_timer = 0;
2737
2738 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
2739 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
2740 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
2741 roce_set_field(qpc_mask->byte_232_irrl_sge,
2742 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
2743 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
2744
2745 qpc_mask->irrl_cur_sge_offset = 0;
2746
2747 roce_set_field(qpc_mask->byte_240_irrl_tail,
2748 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
2749 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
2750 roce_set_field(qpc_mask->byte_240_irrl_tail,
2751 V2_QPC_BYTE_240_IRRL_TAIL_RD_M,
2752 V2_QPC_BYTE_240_IRRL_TAIL_RD_S, 0);
2753 roce_set_field(qpc_mask->byte_240_irrl_tail,
2754 V2_QPC_BYTE_240_RX_ACK_MSN_M,
2755 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
2756
2757 roce_set_field(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_M,
2758 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
2759 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_ACK_PSN_ERR_S,
2760 0);
2761 roce_set_field(qpc_mask->byte_248_ack_psn,
2762 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
2763 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
2764 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_VLD_S,
2765 0);
2766 roce_set_bit(qpc_mask->byte_248_ack_psn,
2767 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
2768 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_CQ_ERR_IND_S,
2769 0);
2770
2771 hr_qp->access_flags = attr->qp_access_flags;
2772 hr_qp->pkey_index = attr->pkey_index;
2773 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2774 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
2775 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2776 V2_QPC_BYTE_252_TX_CQN_S, 0);
2777
2778 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_ERR_TYPE_M,
2779 V2_QPC_BYTE_252_ERR_TYPE_S, 0);
2780
2781 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
2782 V2_QPC_BYTE_256_RQ_CQE_IDX_M,
2783 V2_QPC_BYTE_256_RQ_CQE_IDX_S, 0);
2784 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
2785 V2_QPC_BYTE_256_SQ_FLUSH_IDX_M,
2786 V2_QPC_BYTE_256_SQ_FLUSH_IDX_S, 0);
2787}
2788
2789static void modify_qp_init_to_init(struct ib_qp *ibqp,
2790 const struct ib_qp_attr *attr, int attr_mask,
2791 struct hns_roce_v2_qp_context *context,
2792 struct hns_roce_v2_qp_context *qpc_mask)
2793{
2794 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2795
2796 /*
2797 * In v2 engine, software pass context and context mask to hardware
2798 * when modifying qp. If software need modify some fields in context,
2799 * we should set all bits of the relevant fields in context mask to
2800 * 0 at the same time, else set them to 0x1.
2801 */
2802 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2803 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
2804 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2805 V2_QPC_BYTE_4_TST_S, 0);
2806
0fa95a9a 2807 if (ibqp->qp_type == IB_QPT_GSI)
2808 roce_set_field(context->byte_4_sqpn_tst,
2809 V2_QPC_BYTE_4_SGE_SHIFT_M,
2810 V2_QPC_BYTE_4_SGE_SHIFT_S,
2811 ilog2((unsigned int)hr_qp->sge.sge_cnt));
2812 else
2813 roce_set_field(context->byte_4_sqpn_tst,
2814 V2_QPC_BYTE_4_SGE_SHIFT_M,
2815 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ?
2816 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
2817
926a01dc
WHX		 2818 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
2819 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
2820
2821 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2822 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2823 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2824 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2825 0);
2826
2827 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2828 !!(attr->qp_access_flags &
2829 IB_ACCESS_REMOTE_WRITE));
2830 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2831 0);
2832
2833 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2834 !!(attr->qp_access_flags &
2835 IB_ACCESS_REMOTE_ATOMIC));
2836 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2837 0);
2838 } else {
2839 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2840 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ));
2841 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2842 0);
2843
2844 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2845 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE));
2846 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2847 0);
2848
2849 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2850 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
2851 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2852 0);
2853 }
2854
2855 roce_set_field(context->byte_20_smac_sgid_idx,
2856 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
2857 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2858 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2859 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
2860
2861 roce_set_field(context->byte_20_smac_sgid_idx,
2862 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
2863 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2864 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2865 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
2866
2867 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2868 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
2869 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2870 V2_QPC_BYTE_16_PD_S, 0);
2871
2872 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2873 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
2874 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2875 V2_QPC_BYTE_80_RX_CQN_S, 0);
2876
2877 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
6d13b869 2878 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 2879 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2880 V2_QPC_BYTE_252_TX_CQN_S, 0);
2881
2882 if (ibqp->srq) {
2883 roce_set_bit(context->byte_76_srqn_op_en,
2884 V2_QPC_BYTE_76_SRQ_EN_S, 1);
2885 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
2886 V2_QPC_BYTE_76_SRQ_EN_S, 0);
2887 roce_set_field(context->byte_76_srqn_op_en,
2888 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
2889 to_hr_srq(ibqp->srq)->srqn);
2890 roce_set_field(qpc_mask->byte_76_srqn_op_en,
2891 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
2892 }
2893
0fa95a9a 2894 if (attr_mask & IB_QP_QKEY) {
2895 context->qkey_xrcd = attr->qkey;
2896 qpc_mask->qkey_xrcd = 0;
2897 }
926a01dc
WHX		 2898
2899 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2900 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
2901 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2902 V2_QPC_BYTE_4_SQPN_S, 0);
2903
b6dd9b34 2904 if (attr_mask & IB_QP_DEST_QPN) {
2905 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
2906 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn);
2907 roce_set_field(qpc_mask->byte_56_dqpn_err,
2908 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
2909 }
926a01dc
WHX		 2910 roce_set_field(context->byte_168_irrl_idx,
2911 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2912 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S,
2913 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2914 roce_set_field(qpc_mask->byte_168_irrl_idx,
2915 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2916 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0);
2917}
2918
2919static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
2920 const struct ib_qp_attr *attr, int attr_mask,
2921 struct hns_roce_v2_qp_context *context,
2922 struct hns_roce_v2_qp_context *qpc_mask)
2923{
2924 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2925 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2926 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2927 struct device *dev = hr_dev->dev;
e92f2c18 2928 dma_addr_t dma_handle_3;
926a01dc
WHX		 2929 dma_addr_t dma_handle_2;
2930 dma_addr_t dma_handle;
2931 u32 page_size;
2932 u8 port_num;
e92f2c18 2933 u64 *mtts_3;
926a01dc
WHX		 2934 u64 *mtts_2;
2935 u64 *mtts;
2936 u8 *dmac;
2937 u8 *smac;
2938 int port;
2939
2940 /* Search qp buf's mtts */
2941 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2942 hr_qp->mtt.first_seg, &dma_handle);
2943 if (!mtts) {
2944 dev_err(dev, "qp buf pa find failed\n");
2945 return -EINVAL;
2946 }
2947
2948 /* Search IRRL's mtts */
2949 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2950 hr_qp->qpn, &dma_handle_2);
2951 if (!mtts_2) {
2952 dev_err(dev, "qp irrl_table find failed\n");
2953 return -EINVAL;
2954 }
2955
e92f2c18 2956 /* Search TRRL's mtts */
2957 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
2958 hr_qp->qpn, &dma_handle_3);
2959 if (!mtts_3) {
2960 dev_err(dev, "qp trrl_table find failed\n");
2961 return -EINVAL;
2962 }
2963
734f3863 2964 if (attr_mask & IB_QP_ALT_PATH) {
926a01dc
WHX		 2965 dev_err(dev, "INIT2RTR attr_mask (0x%x) error\n", attr_mask);
2966 return -EINVAL;
2967 }
2968
2969 dmac = (u8 *)attr->ah_attr.roce.dmac;
2970 context->wqe_sge_ba = (u32)(dma_handle >> 3);
2971 qpc_mask->wqe_sge_ba = 0;
2972
2973 /*
2974 * In v2 engine, software pass context and context mask to hardware
2975 * when modifying qp. If software need modify some fields in context,
2976 * we should set all bits of the relevant fields in context mask to
2977 * 0 at the same time, else set them to 0x1.
2978 */
2979 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
2980 V2_QPC_BYTE_12_WQE_SGE_BA_S, dma_handle >> (32 + 3));
2981 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
2982 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0);
2983
2984 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
2985 V2_QPC_BYTE_12_SQ_HOP_NUM_S,
2986 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
2987 0 : hr_dev->caps.mtt_hop_num);
2988 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
2989 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0);
2990
2991 roce_set_field(context->byte_20_smac_sgid_idx,
2992 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
2993 V2_QPC_BYTE_20_SGE_HOP_NUM_S,
0fa95a9a 2994 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
2995 hr_dev->caps.mtt_hop_num : 0);
926a01dc
WHX		 2996 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2997 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
2998 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0);
2999
3000 roce_set_field(context->byte_20_smac_sgid_idx,
3001 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3002 V2_QPC_BYTE_20_RQ_HOP_NUM_S,
3003 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
3004 0 : hr_dev->caps.mtt_hop_num);
3005 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3006 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3007 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0);
3008
3009 roce_set_field(context->byte_16_buf_ba_pg_sz,
3010 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3011 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
5e6e78db 3012 hr_dev->caps.mtt_ba_pg_sz + PG_SHIFT_OFFSET);
926a01dc
WHX		 3013 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3014 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3015 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
3016
3017 roce_set_field(context->byte_16_buf_ba_pg_sz,
3018 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3019 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
5e6e78db 3020 hr_dev->caps.mtt_buf_pg_sz + PG_SHIFT_OFFSET);
926a01dc
WHX		 3021 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3022 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3023 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
3024
3025 roce_set_field(context->byte_80_rnr_rx_cqn,
3026 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3027 V2_QPC_BYTE_80_MIN_RNR_TIME_S, attr->min_rnr_timer);
3028 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn,
3029 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3030 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0);
3031
3032 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
3033 context->rq_cur_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size]
3034 >> PAGE_ADDR_SHIFT);
3035 qpc_mask->rq_cur_blk_addr = 0;
3036
3037 roce_set_field(context->byte_92_srq_info,
3038 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3039 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S,
3040 mtts[hr_qp->rq.offset / page_size]
3041 >> (32 + PAGE_ADDR_SHIFT));
3042 roce_set_field(qpc_mask->byte_92_srq_info,
3043 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3044 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0);
3045
3046 context->rq_nxt_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size + 1]
3047 >> PAGE_ADDR_SHIFT);
3048 qpc_mask->rq_nxt_blk_addr = 0;
3049
3050 roce_set_field(context->byte_104_rq_sge,
3051 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3052 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S,
3053 mtts[hr_qp->rq.offset / page_size + 1]
3054 >> (32 + PAGE_ADDR_SHIFT));
3055 roce_set_field(qpc_mask->byte_104_rq_sge,
3056 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3057 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0);
3058
3059 roce_set_field(context->byte_108_rx_reqepsn,
3060 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3061 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn);
3062 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3063 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3064 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);
3065
e92f2c18 3066 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3067 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4);
3068 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3069 V2_QPC_BYTE_132_TRRL_BA_S, 0);
3070 context->trrl_ba = (u32)(dma_handle_3 >> (16 + 4));
3071 qpc_mask->trrl_ba = 0;
3072 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3073 V2_QPC_BYTE_140_TRRL_BA_S,
3074 (u32)(dma_handle_3 >> (32 + 16 + 4)));
3075 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3076 V2_QPC_BYTE_140_TRRL_BA_S, 0);
3077
d5514246 3078 context->irrl_ba = (u32)(dma_handle_2 >> 6);
926a01dc
WHX		 3079 qpc_mask->irrl_ba = 0;
3080 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3081 V2_QPC_BYTE_208_IRRL_BA_S,
d5514246 3082 dma_handle_2 >> (32 + 6));
926a01dc
WHX		 3083 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3084 V2_QPC_BYTE_208_IRRL_BA_S, 0);
3085
3086 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1);
3087 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0);
3088
3089 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3090 hr_qp->sq_signal_bits);
3091 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3092 0);
3093
3094 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
3095
3096 smac = (u8 *)hr_dev->dev_addr[port];
3097 /* when dmac equals smac or loop_idc is 1, it should loopback */
3098 if (ether_addr_equal_unaligned(dmac, smac) ||
3099 hr_dev->loop_idc == 0x1) {
3100 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1);
3101 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0);
3102 }
3103
4f3f7a70 3104 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
3105 attr->max_dest_rd_atomic) {
3106 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
3107 V2_QPC_BYTE_140_RR_MAX_S,
3108 fls(attr->max_dest_rd_atomic - 1));
3109 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
3110 V2_QPC_BYTE_140_RR_MAX_S, 0);
3111 }
926a01dc 3112
b6dd9b34 3113 if (attr_mask & IB_QP_DEST_QPN) {
3114 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3115 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num);
3116 roce_set_field(qpc_mask->byte_56_dqpn_err,
3117 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3118 }
926a01dc
WHX		 3119
3120 /* Configure GID index */
3121 port_num = rdma_ah_get_port_num(&attr->ah_attr);
3122 roce_set_field(context->byte_20_smac_sgid_idx,
3123 V2_QPC_BYTE_20_SGID_IDX_M,
3124 V2_QPC_BYTE_20_SGID_IDX_S,
3125 hns_get_gid_index(hr_dev, port_num - 1,
3126 grh->sgid_index));
3127 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3128 V2_QPC_BYTE_20_SGID_IDX_M,
3129 V2_QPC_BYTE_20_SGID_IDX_S, 0);
3130 memcpy(&(context->dmac), dmac, 4);
3131 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3132 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
3133 qpc_mask->dmac = 0;
3134 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3135 V2_QPC_BYTE_52_DMAC_S, 0);
3136
3137 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3138 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4);
3139 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3140 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
3141
0fa95a9a 3142 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
3143 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3144 V2_QPC_BYTE_24_MTU_S, IB_MTU_4096);
6852af86 3145 else if (attr_mask & IB_QP_PATH_MTU)
0fa95a9a 3146 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3147 V2_QPC_BYTE_24_MTU_S, attr->path_mtu);
3148
926a01dc
WHX		 3149 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3150 V2_QPC_BYTE_24_MTU_S, 0);
3151
926a01dc
WHX		 3152 roce_set_field(context->byte_84_rq_ci_pi,
3153 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3154 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head);
3155 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3156 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3157 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3158
3159 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3160 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
3161 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
3162 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
3163 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
3164 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
3165 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
3166 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3167 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
3168 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
3169
3170 context->rq_rnr_timer = 0;
3171 qpc_mask->rq_rnr_timer = 0;
3172
3173 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
3174 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1);
3175 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
3176 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
3177
3178 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
3179 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
3180 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
3181 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
3182
3183 roce_set_field(context->byte_168_irrl_idx,
3184 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3185 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3);
3186 roce_set_field(qpc_mask->byte_168_irrl_idx,
3187 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3188 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0);
3189
926a01dc
WHX		 3190 return 0;
3191}
3192
3193static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
3194 const struct ib_qp_attr *attr, int attr_mask,
3195 struct hns_roce_v2_qp_context *context,
3196 struct hns_roce_v2_qp_context *qpc_mask)
3197{
3198 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3199 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3200 struct device *dev = hr_dev->dev;
3201 dma_addr_t dma_handle;
befb63b4 3202 u32 page_size;
926a01dc
WHX		 3203 u64 *mtts;
3204
3205 /* Search qp buf's mtts */
3206 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
3207 hr_qp->mtt.first_seg, &dma_handle);
3208 if (!mtts) {
3209 dev_err(dev, "qp buf pa find failed\n");
3210 return -EINVAL;
3211 }
3212
734f3863 3213 /* Not support alternate path and path migration */
3214 if ((attr_mask & IB_QP_ALT_PATH) ||
3215 (attr_mask & IB_QP_PATH_MIG_STATE)) {
926a01dc
WHX		 3216 dev_err(dev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
3217 return -EINVAL;
3218 }
3219
3220 /*
3221 * In v2 engine, software pass context and context mask to hardware
3222 * when modifying qp. If software need modify some fields in context,
3223 * we should set all bits of the relevant fields in context mask to
3224 * 0 at the same time, else set them to 0x1.
3225 */
3226 roce_set_field(context->byte_60_qpst_mapid,
3227 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M,
3228 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, attr->retry_cnt);
3229 roce_set_field(qpc_mask->byte_60_qpst_mapid,
3230 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M,
3231 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, 0);
3232
3233 context->sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
3234 roce_set_field(context->byte_168_irrl_idx,
3235 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3236 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S,
3237 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
3238 qpc_mask->sq_cur_blk_addr = 0;
3239 roce_set_field(qpc_mask->byte_168_irrl_idx,
3240 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3241 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);
3242
befb63b4 3243 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
0fa95a9a 3244 context->sq_cur_sge_blk_addr =
3245 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
befb63b4 3246 ((u32)(mtts[hr_qp->sge.offset / page_size]
3247 >> PAGE_ADDR_SHIFT)) : 0;
3248 roce_set_field(context->byte_184_irrl_idx,
3249 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3250 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,
0fa95a9a 3251 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
befb63b4 3252 (mtts[hr_qp->sge.offset / page_size] >>
3253 (32 + PAGE_ADDR_SHIFT)) : 0);
3254 qpc_mask->sq_cur_sge_blk_addr = 0;
3255 roce_set_field(qpc_mask->byte_184_irrl_idx,
3256 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3257 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);
3258
926a01dc
WHX		 3259 context->rx_sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
3260 roce_set_field(context->byte_232_irrl_sge,
3261 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3262 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S,
3263 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
3264 qpc_mask->rx_sq_cur_blk_addr = 0;
3265 roce_set_field(qpc_mask->byte_232_irrl_sge,
3266 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3267 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0);
3268
3269 /*
3270 * Set some fields in context to zero, Because the default values
3271 * of all fields in context are zero, we need not set them to 0 again.
3272 * but we should set the relevant fields of context mask to 0.
3273 */
3274 roce_set_field(qpc_mask->byte_232_irrl_sge,
3275 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
3276 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
3277
3278 roce_set_field(qpc_mask->byte_240_irrl_tail,
3279 V2_QPC_BYTE_240_RX_ACK_MSN_M,
3280 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
3281
3282 roce_set_field(context->byte_244_rnr_rxack,
3283 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
3284 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn);
3285 roce_set_field(qpc_mask->byte_244_rnr_rxack,
3286 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
3287 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0);
3288
3289 roce_set_field(qpc_mask->byte_248_ack_psn,
3290 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
3291 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
3292 roce_set_bit(qpc_mask->byte_248_ack_psn,
3293 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0);
3294 roce_set_field(qpc_mask->byte_248_ack_psn,
3295 V2_QPC_BYTE_248_IRRL_PSN_M,
3296 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
3297
3298 roce_set_field(qpc_mask->byte_240_irrl_tail,
3299 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
3300 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
3301
3302 roce_set_field(context->byte_220_retry_psn_msn,
3303 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
3304 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn);
3305 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3306 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
3307 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0);
3308
3309 roce_set_field(context->byte_224_retry_msg,
3310 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
3311 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, attr->sq_psn >> 16);
3312 roce_set_field(qpc_mask->byte_224_retry_msg,
3313 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
3314 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0);
3315
3316 roce_set_field(context->byte_224_retry_msg,
3317 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
3318 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, attr->sq_psn);
3319 roce_set_field(qpc_mask->byte_224_retry_msg,
3320 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
3321 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0);
3322
3323 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3324 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
3325 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
3326
3327 roce_set_bit(qpc_mask->byte_248_ack_psn,
3328 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
3329
3330 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
3331 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
3332
3333 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
3334 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt);
3335 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
3336 V2_QPC_BYTE_212_RETRY_CNT_S, 0);
3337
3338 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
3339 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, attr->retry_cnt);
3340 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
3341 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0);
3342
3343 roce_set_field(context->byte_244_rnr_rxack,
3344 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
3345 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry);
3346 roce_set_field(qpc_mask->byte_244_rnr_rxack,
3347 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
3348 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0);
3349
3350 roce_set_field(context->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
3351 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry);
3352 roce_set_field(qpc_mask->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
3353 V2_QPC_BYTE_244_RNR_CNT_S, 0);
3354
3355 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
3356 V2_QPC_BYTE_212_LSN_S, 0x100);
3357 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
3358 V2_QPC_BYTE_212_LSN_S, 0);
3359
28726461 3360 if (attr_mask & IB_QP_TIMEOUT) {
926a01dc
WHX		 3361 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_AT_M,
3362 V2_QPC_BYTE_28_AT_S, attr->timeout);
28726461 3363 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_AT_M,
3364 V2_QPC_BYTE_28_AT_S, 0);
3365 }
926a01dc 3366
926a01dc
WHX		 3367 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3368 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn);
3369 roce_set_field(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3370 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0);
3371
3372 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
3373 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
3374 roce_set_field(context->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
3375 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn);
3376 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
3377 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0);
3378
4f3f7a70 3379 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
3380 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
3381 V2_QPC_BYTE_208_SR_MAX_S,
3382 fls(attr->max_rd_atomic - 1));
3383 roce_set_field(qpc_mask->byte_208_irrl,
3384 V2_QPC_BYTE_208_SR_MAX_M,
3385 V2_QPC_BYTE_208_SR_MAX_S, 0);
3386 }
926a01dc
WHX		 3387 return 0;
3388}
3389
3390static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
3391 const struct ib_qp_attr *attr,
3392 int attr_mask, enum ib_qp_state cur_state,
3393 enum ib_qp_state new_state)
3394{
3395 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3396 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3397 struct hns_roce_v2_qp_context *context;
3398 struct hns_roce_v2_qp_context *qpc_mask;
3399 struct device *dev = hr_dev->dev;
3400 int ret = -EINVAL;
3401
6396bb22 3402 context = kcalloc(2, sizeof(*context), GFP_KERNEL);
926a01dc
WHX		 3403 if (!context)
3404 return -ENOMEM;
3405
3406 qpc_mask = context + 1;
3407 /*
3408 * In v2 engine, software pass context and context mask to hardware
3409 * when modifying qp. If software need modify some fields in context,
3410 * we should set all bits of the relevant fields in context mask to
3411 * 0 at the same time, else set them to 0x1.
3412 */
3413 memset(qpc_mask, 0xff, sizeof(*qpc_mask));
3414 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0fa95a9a 3415 modify_qp_reset_to_init(ibqp, attr, attr_mask, context,
3416 qpc_mask);
926a01dc
WHX		 3417 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3418 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
3419 qpc_mask);
3420 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3421 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
3422 qpc_mask);
3423 if (ret)
3424 goto out;
3425 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3426 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
3427 qpc_mask);
3428 if (ret)
3429 goto out;
3430 } else if ((cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) ||
3431 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS) ||
3432 (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD) ||
3433 (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD) ||
3434 (cur_state == IB_QPS_SQD && new_state == IB_QPS_RTS) ||
3435 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
3436 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3437 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3438 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
3439 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3440 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3441 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3442 (cur_state == IB_QPS_SQD && new_state == IB_QPS_ERR) ||
6e1a7094 3443 (cur_state == IB_QPS_SQE && new_state == IB_QPS_ERR) ||
3444 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR)) {
926a01dc
WHX		 3445 /* Nothing */
3446 ;
3447 } else {
3448 dev_err(dev, "Illegal state for QP!\n");
ac7cbf96 3449 ret = -EINVAL;
926a01dc
WHX		 3450 goto out;
3451 }
3452
610b8967
LO		 3453 if (attr_mask & IB_QP_AV) {
3454 const struct ib_global_route *grh =
3455 rdma_ah_read_grh(&attr->ah_attr);
3456 const struct ib_gid_attr *gid_attr = NULL;
3457 u8 src_mac[ETH_ALEN];
3458 int is_roce_protocol;
3459 u16 vlan = 0xffff;
3460 u8 ib_port;
3461 u8 hr_port;
3462
3463 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num :
3464 hr_qp->port + 1;
3465 hr_port = ib_port - 1;
3466 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
3467 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
3468
3469 if (is_roce_protocol) {
3470 gid_attr = attr->ah_attr.grh.sgid_attr;
3471 vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev);
3472 memcpy(src_mac, gid_attr->ndev->dev_addr, ETH_ALEN);
3473 }
3474
c8e46f8d
LO		 3475 roce_set_field(context->byte_24_mtu_tc,
3476 V2_QPC_BYTE_24_VLAN_ID_M,
3477 V2_QPC_BYTE_24_VLAN_ID_S, vlan);
3478 roce_set_field(qpc_mask->byte_24_mtu_tc,
3479 V2_QPC_BYTE_24_VLAN_ID_M,
3480 V2_QPC_BYTE_24_VLAN_ID_S, 0);
3481
610b8967
LO		 3482 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
3483 dev_err(hr_dev->dev,
3484 "sgid_index(%u) too large. max is %d\n",
3485 grh->sgid_index,
3486 hr_dev->caps.gid_table_len[hr_port]);
3487 ret = -EINVAL;
3488 goto out;
3489 }
3490
3491 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
3492 dev_err(hr_dev->dev, "ah attr is not RDMA roce type\n");
3493 ret = -EINVAL;
3494 goto out;
3495 }
3496
3497 roce_set_field(context->byte_52_udpspn_dmac,
3498 V2_QPC_BYTE_52_UDPSPN_M, V2_QPC_BYTE_52_UDPSPN_S,
3499 (gid_attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3500 0 : 0x12b7);
3501
3502 roce_set_field(qpc_mask->byte_52_udpspn_dmac,
3503 V2_QPC_BYTE_52_UDPSPN_M,
3504 V2_QPC_BYTE_52_UDPSPN_S, 0);
3505
3506 roce_set_field(context->byte_20_smac_sgid_idx,
3507 V2_QPC_BYTE_20_SGID_IDX_M,
3508 V2_QPC_BYTE_20_SGID_IDX_S, grh->sgid_index);
3509
3510 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3511 V2_QPC_BYTE_20_SGID_IDX_M,
3512 V2_QPC_BYTE_20_SGID_IDX_S, 0);
3513
3514 roce_set_field(context->byte_24_mtu_tc,
3515 V2_QPC_BYTE_24_HOP_LIMIT_M,
3516 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit);
3517 roce_set_field(qpc_mask->byte_24_mtu_tc,
3518 V2_QPC_BYTE_24_HOP_LIMIT_M,
3519 V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
3520
3521 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
3522 V2_QPC_BYTE_24_TC_S, grh->traffic_class);
3523 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
3524 V2_QPC_BYTE_24_TC_S, 0);
3525 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
3526 V2_QPC_BYTE_28_FL_S, grh->flow_label);
3527 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
3528 V2_QPC_BYTE_28_FL_S, 0);
3529 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
3530 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
3531 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
3532 V2_QPC_BYTE_28_SL_S,
3533 rdma_ah_get_sl(&attr->ah_attr));
3534 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
3535 V2_QPC_BYTE_28_SL_S, 0);
3536 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3537 }
3538
ace1c541 3539 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3540 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
3541
926a01dc
WHX		 3542 /* Every status migrate must change state */
3543 roce_set_field(context->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M,
3544 V2_QPC_BYTE_60_QP_ST_S, new_state);
3545 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M,
3546 V2_QPC_BYTE_60_QP_ST_S, 0);
3547
3548 /* SW pass context to HW */
3549 ret = hns_roce_v2_qp_modify(hr_dev, &hr_qp->mtt, cur_state, new_state,
3550 context, hr_qp);
3551 if (ret) {
3552 dev_err(dev, "hns_roce_qp_modify failed(%d)\n", ret);
3553 goto out;
3554 }
3555
3556 hr_qp->state = new_state;
3557
ace1c541 3558 if (attr_mask & IB_QP_ACCESS_FLAGS)
3559 hr_qp->atomic_rd_en = attr->qp_access_flags;
3560
926a01dc
WHX		 3561 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3562 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3563 if (attr_mask & IB_QP_PORT) {
3564 hr_qp->port = attr->port_num - 1;
3565 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3566 }
3567
3568 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3569 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3570 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3571 if (ibqp->send_cq != ibqp->recv_cq)
3572 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
3573 hr_qp->qpn, NULL);
3574
3575 hr_qp->rq.head = 0;
3576 hr_qp->rq.tail = 0;
3577 hr_qp->sq.head = 0;
3578 hr_qp->sq.tail = 0;
3579 hr_qp->sq_next_wqe = 0;
3580 hr_qp->next_sge = 0;
e088a685
YL		 3581 if (hr_qp->rq.wqe_cnt)
3582 *hr_qp->rdb.db_record = 0;
926a01dc
WHX		 3583 }
3584
3585out:
3586 kfree(context);
3587 return ret;
3588}
3589
3590static inline enum ib_qp_state to_ib_qp_st(enum hns_roce_v2_qp_state state)
3591{
3592 switch (state) {
3593 case HNS_ROCE_QP_ST_RST: return IB_QPS_RESET;
3594 case HNS_ROCE_QP_ST_INIT: return IB_QPS_INIT;
3595 case HNS_ROCE_QP_ST_RTR: return IB_QPS_RTR;
3596 case HNS_ROCE_QP_ST_RTS: return IB_QPS_RTS;
3597 case HNS_ROCE_QP_ST_SQ_DRAINING:
3598 case HNS_ROCE_QP_ST_SQD: return IB_QPS_SQD;
3599 case HNS_ROCE_QP_ST_SQER: return IB_QPS_SQE;
3600 case HNS_ROCE_QP_ST_ERR: return IB_QPS_ERR;
3601 default: return -1;
3602 }
3603}
3604
3605static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
3606 struct hns_roce_qp *hr_qp,
3607 struct hns_roce_v2_qp_context *hr_context)
3608{
3609 struct hns_roce_cmd_mailbox *mailbox;
3610 int ret;
3611
3612 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3613 if (IS_ERR(mailbox))
3614 return PTR_ERR(mailbox);
3615
3616 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3617 HNS_ROCE_CMD_QUERY_QPC,
3618 HNS_ROCE_CMD_TIMEOUT_MSECS);
3619 if (ret) {
3620 dev_err(hr_dev->dev, "QUERY QP cmd process error\n");
3621 goto out;
3622 }
3623
3624 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3625
3626out:
3627 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3628 return ret;
3629}
3630
3631static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3632 int qp_attr_mask,
3633 struct ib_qp_init_attr *qp_init_attr)
3634{
3635 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3636 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3637 struct hns_roce_v2_qp_context *context;
3638 struct device *dev = hr_dev->dev;
3639 int tmp_qp_state;
3640 int state;
3641 int ret;
3642
3643 context = kzalloc(sizeof(*context), GFP_KERNEL);
3644 if (!context)
3645 return -ENOMEM;
3646
3647 memset(qp_attr, 0, sizeof(*qp_attr));
3648 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3649
3650 mutex_lock(&hr_qp->mutex);
3651
3652 if (hr_qp->state == IB_QPS_RESET) {
3653 qp_attr->qp_state = IB_QPS_RESET;
63ea641f 3654 ret = 0;
926a01dc
WHX		 3655 goto done;
3656 }
3657
3658 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, context);
3659 if (ret) {
3660 dev_err(dev, "query qpc error\n");
3661 ret = -EINVAL;
3662 goto out;
3663 }
3664
3665 state = roce_get_field(context->byte_60_qpst_mapid,
3666 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
3667 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
3668 if (tmp_qp_state == -1) {
3669 dev_err(dev, "Illegal ib_qp_state\n");
3670 ret = -EINVAL;
3671 goto out;
3672 }
3673 hr_qp->state = (u8)tmp_qp_state;
3674 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3675 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->byte_24_mtu_tc,
3676 V2_QPC_BYTE_24_MTU_M,
3677 V2_QPC_BYTE_24_MTU_S);
3678 qp_attr->path_mig_state = IB_MIG_ARMED;
2bf910d4 3679 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
926a01dc
WHX		 3680 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3681 qp_attr->qkey = V2_QKEY_VAL;
3682
3683 qp_attr->rq_psn = roce_get_field(context->byte_108_rx_reqepsn,
3684 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3685 V2_QPC_BYTE_108_RX_REQ_EPSN_S);
3686 qp_attr->sq_psn = (u32)roce_get_field(context->byte_172_sq_psn,
3687 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3688 V2_QPC_BYTE_172_SQ_CUR_PSN_S);
3689 qp_attr->dest_qp_num = (u8)roce_get_field(context->byte_56_dqpn_err,
3690 V2_QPC_BYTE_56_DQPN_M,
3691 V2_QPC_BYTE_56_DQPN_S);
3692 qp_attr->qp_access_flags = ((roce_get_bit(context->byte_76_srqn_op_en,
3693 V2_QPC_BYTE_76_RRE_S)) << 2) |
3694 ((roce_get_bit(context->byte_76_srqn_op_en,
3695 V2_QPC_BYTE_76_RWE_S)) << 1) |
3696 ((roce_get_bit(context->byte_76_srqn_op_en,
3697 V2_QPC_BYTE_76_ATE_S)) << 3);
3698 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3699 hr_qp->ibqp.qp_type == IB_QPT_UC) {
3700 struct ib_global_route *grh =
3701 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3702
3703 rdma_ah_set_sl(&qp_attr->ah_attr,
3704 roce_get_field(context->byte_28_at_fl,
3705 V2_QPC_BYTE_28_SL_M,
3706 V2_QPC_BYTE_28_SL_S));
3707 grh->flow_label = roce_get_field(context->byte_28_at_fl,
3708 V2_QPC_BYTE_28_FL_M,
3709 V2_QPC_BYTE_28_FL_S);
3710 grh->sgid_index = roce_get_field(context->byte_20_smac_sgid_idx,
3711 V2_QPC_BYTE_20_SGID_IDX_M,
3712 V2_QPC_BYTE_20_SGID_IDX_S);
3713 grh->hop_limit = roce_get_field(context->byte_24_mtu_tc,
3714 V2_QPC_BYTE_24_HOP_LIMIT_M,
3715 V2_QPC_BYTE_24_HOP_LIMIT_S);
3716 grh->traffic_class = roce_get_field(context->byte_24_mtu_tc,
3717 V2_QPC_BYTE_24_TC_M,
3718 V2_QPC_BYTE_24_TC_S);
3719
3720 memcpy(grh->dgid.raw, context->dgid, sizeof(grh->dgid.raw));
3721 }
3722
3723 qp_attr->port_num = hr_qp->port + 1;
3724 qp_attr->sq_draining = 0;
3725 qp_attr->max_rd_atomic = 1 << roce_get_field(context->byte_208_irrl,
3726 V2_QPC_BYTE_208_SR_MAX_M,
3727 V2_QPC_BYTE_208_SR_MAX_S);
3728 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->byte_140_raq,
3729 V2_QPC_BYTE_140_RR_MAX_M,
3730 V2_QPC_BYTE_140_RR_MAX_S);
3731 qp_attr->min_rnr_timer = (u8)roce_get_field(context->byte_80_rnr_rx_cqn,
3732 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3733 V2_QPC_BYTE_80_MIN_RNR_TIME_S);
3734 qp_attr->timeout = (u8)roce_get_field(context->byte_28_at_fl,
3735 V2_QPC_BYTE_28_AT_M,
3736 V2_QPC_BYTE_28_AT_S);
3737 qp_attr->retry_cnt = roce_get_field(context->byte_212_lsn,
3738 V2_QPC_BYTE_212_RETRY_CNT_M,
3739 V2_QPC_BYTE_212_RETRY_CNT_S);
3740 qp_attr->rnr_retry = context->rq_rnr_timer;
3741
3742done:
3743 qp_attr->cur_qp_state = qp_attr->qp_state;
3744 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3745 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3746
3747 if (!ibqp->uobject) {
3748 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3749 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3750 } else {
3751 qp_attr->cap.max_send_wr = 0;
3752 qp_attr->cap.max_send_sge = 0;
3753 }
3754
3755 qp_init_attr->cap = qp_attr->cap;
3756
3757out:
3758 mutex_unlock(&hr_qp->mutex);
3759 kfree(context);
3760 return ret;
3761}
3762
3763static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
3764 struct hns_roce_qp *hr_qp,
3765 int is_user)
3766{
3767 struct hns_roce_cq *send_cq, *recv_cq;
3768 struct device *dev = hr_dev->dev;
3769 int ret;
3770
3771 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
3772 /* Modify qp to reset before destroying qp */
3773 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
3774 hr_qp->state, IB_QPS_RESET);
3775 if (ret) {
3776 dev_err(dev, "modify QP %06lx to ERR failed.\n",
3777 hr_qp->qpn);
3778 return ret;
3779 }
3780 }
3781
3782 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3783 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3784
3785 hns_roce_lock_cqs(send_cq, recv_cq);
3786
3787 if (!is_user) {
3788 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3789 to_hr_srq(hr_qp->ibqp.srq) : NULL);
3790 if (send_cq != recv_cq)
3791 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
3792 }
3793
3794 hns_roce_qp_remove(hr_dev, hr_qp);
3795
3796 hns_roce_unlock_cqs(send_cq, recv_cq);
3797
3798 hns_roce_qp_free(hr_dev, hr_qp);
3799
3800 /* Not special_QP, free their QPN */
3801 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) ||
3802 (hr_qp->ibqp.qp_type == IB_QPT_UC) ||
3803 (hr_qp->ibqp.qp_type == IB_QPT_UD))
3804 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3805
3806 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3807
3808 if (is_user) {
e088a685
YL		 3809 if (hr_qp->rq.wqe_cnt && (hr_qp->rdb_en == 1))
3810 hns_roce_db_unmap_user(
3811 to_hr_ucontext(hr_qp->ibqp.uobject->context),
3812 &hr_qp->rdb);
926a01dc
WHX		 3813 ib_umem_release(hr_qp->umem);
3814 } else {
3815 kfree(hr_qp->sq.wrid);
3816 kfree(hr_qp->rq.wrid);
3817 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
472bc0fb
YL		 3818 if (hr_qp->rq.wqe_cnt)
3819 hns_roce_free_db(hr_dev, &hr_qp->rdb);
926a01dc
WHX		 3820 }
3821
0009c2db 3822 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
3823 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list);
3824 kfree(hr_qp->rq_inl_buf.wqe_list);
3825 }
3826
926a01dc
WHX		 3827 return 0;
3828}
3829
3830static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp)
3831{
3832 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3833 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3834 int ret;
3835
3836 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, !!ibqp->pd->uobject);
3837 if (ret) {
3838 dev_err(hr_dev->dev, "Destroy qp failed(%d)\n", ret);
3839 return ret;
3840 }
3841
3842 if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
3843 kfree(hr_to_hr_sqp(hr_qp));
3844 else
3845 kfree(hr_qp);
3846
3847 return 0;
3848}
3849
b156269d 3850static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
3851{
3852 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
3853 struct hns_roce_v2_cq_context *cq_context;
3854 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
3855 struct hns_roce_v2_cq_context *cqc_mask;
3856 struct hns_roce_cmd_mailbox *mailbox;
3857 int ret;
3858
3859 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3860 if (IS_ERR(mailbox))
3861 return PTR_ERR(mailbox);
3862
3863 cq_context = mailbox->buf;
3864 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
3865
3866 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
3867
3868 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
3869 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
3870 cq_count);
3871 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
3872 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
3873 0);
3874 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
3875 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
3876 cq_period);
3877 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
3878 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
3879 0);
3880
3881 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
3882 HNS_ROCE_CMD_MODIFY_CQC,
3883 HNS_ROCE_CMD_TIMEOUT_MSECS);
3884 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3885 if (ret)
3886 dev_err(hr_dev->dev, "MODIFY CQ Failed to cmd mailbox.\n");
3887
3888 return ret;
3889}
3890
a5073d60
YL		 3891static void set_eq_cons_index_v2(struct hns_roce_eq *eq)
3892{
3893 u32 doorbell[2];
3894
3895 doorbell[0] = 0;
3896 doorbell[1] = 0;
3897
3898 if (eq->type_flag == HNS_ROCE_AEQ) {
3899 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
3900 HNS_ROCE_V2_EQ_DB_CMD_S,
3901 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
3902 HNS_ROCE_EQ_DB_CMD_AEQ :
3903 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
3904 } else {
3905 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M,
3906 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn);
3907
3908 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
3909 HNS_ROCE_V2_EQ_DB_CMD_S,
3910 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
3911 HNS_ROCE_EQ_DB_CMD_CEQ :
3912 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
3913 }
3914
3915 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M,
3916 HNS_ROCE_V2_EQ_DB_PARA_S,
3917 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M));
3918
3919 hns_roce_write64_k(doorbell, eq->doorbell);
a5073d60
YL		 3920}
3921
3922static void hns_roce_v2_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
3923 struct hns_roce_aeqe *aeqe,
3924 u32 qpn)
3925{
3926 struct device *dev = hr_dev->dev;
3927 int sub_type;
3928
3929 dev_warn(dev, "Local work queue catastrophic error.\n");
3930 sub_type = roce_get_field(aeqe->asyn, HNS_ROCE_V2_AEQE_SUB_TYPE_M,
3931 HNS_ROCE_V2_AEQE_SUB_TYPE_S);
3932 switch (sub_type) {
3933 case HNS_ROCE_LWQCE_QPC_ERROR:
3934 dev_warn(dev, "QP %d, QPC error.\n", qpn);
3935 break;
3936 case HNS_ROCE_LWQCE_MTU_ERROR:
3937 dev_warn(dev, "QP %d, MTU error.\n", qpn);
3938 break;
3939 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
3940 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn);
3941 break;
3942 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
3943 dev_warn(dev, "QP %d, WQE addr error.\n", qpn);
3944 break;
3945 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
3946 dev_warn(dev, "QP %d, WQE shift error.\n", qpn);
3947 break;
3948 default:
3949 dev_err(dev, "Unhandled sub_event type %d.\n", sub_type);
3950 break;
3951 }
3952}
3953
3954static void hns_roce_v2_local_wq_access_err_handle(struct hns_roce_dev *hr_dev,
3955 struct hns_roce_aeqe *aeqe, u32 qpn)
3956{
3957 struct device *dev = hr_dev->dev;
3958 int sub_type;
3959
3960 dev_warn(dev, "Local access violation work queue error.\n");
3961 sub_type = roce_get_field(aeqe->asyn, HNS_ROCE_V2_AEQE_SUB_TYPE_M,
3962 HNS_ROCE_V2_AEQE_SUB_TYPE_S);
3963 switch (sub_type) {
3964 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
3965 dev_warn(dev, "QP %d, R_key violation.\n", qpn);
3966 break;
3967 case HNS_ROCE_LAVWQE_LENGTH_ERROR:
3968 dev_warn(dev, "QP %d, length error.\n", qpn);
3969 break;
3970 case HNS_ROCE_LAVWQE_VA_ERROR:
3971 dev_warn(dev, "QP %d, VA error.\n", qpn);
3972 break;
3973 case HNS_ROCE_LAVWQE_PD_ERROR:
3974 dev_err(dev, "QP %d, PD error.\n", qpn);
3975 break;
3976 case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
3977 dev_warn(dev, "QP %d, rw acc error.\n", qpn);
3978 break;
3979 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
3980 dev_warn(dev, "QP %d, key state error.\n", qpn);
3981 break;
3982 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
3983 dev_warn(dev, "QP %d, MR operation error.\n", qpn);
3984 break;
3985 default:
3986 dev_err(dev, "Unhandled sub_event type %d.\n", sub_type);
3987 break;
3988 }
3989}
3990
3991static void hns_roce_v2_qp_err_handle(struct hns_roce_dev *hr_dev,
3992 struct hns_roce_aeqe *aeqe,
3993 int event_type)
3994{
3995 struct device *dev = hr_dev->dev;
3996 u32 qpn;
3997
3998 qpn = roce_get_field(aeqe->event.qp_event.qp,
3999 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4000 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
4001
4002 switch (event_type) {
4003 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4004 dev_warn(dev, "Communication established.\n");
4005 break;
4006 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4007 dev_warn(dev, "Send queue drained.\n");
4008 break;
4009 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
4010 hns_roce_v2_wq_catas_err_handle(hr_dev, aeqe, qpn);
4011 break;
4012 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4013 dev_warn(dev, "Invalid request local work queue error.\n");
4014 break;
4015 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
4016 hns_roce_v2_local_wq_access_err_handle(hr_dev, aeqe, qpn);
4017 break;
4018 default:
4019 break;
4020 }
4021
4022 hns_roce_qp_event(hr_dev, qpn, event_type);
4023}
4024
4025static void hns_roce_v2_cq_err_handle(struct hns_roce_dev *hr_dev,
4026 struct hns_roce_aeqe *aeqe,
4027 int event_type)
4028{
4029 struct device *dev = hr_dev->dev;
4030 u32 cqn;
4031
4032 cqn = roce_get_field(aeqe->event.cq_event.cq,
4033 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4034 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
4035
4036 switch (event_type) {
4037 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4038 dev_warn(dev, "CQ 0x%x access err.\n", cqn);
4039 break;
4040 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4041 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
4042 break;
4043 default:
4044 break;
4045 }
4046
4047 hns_roce_cq_event(hr_dev, cqn, event_type);
4048}
4049
4050static struct hns_roce_aeqe *get_aeqe_v2(struct hns_roce_eq *eq, u32 entry)
4051{
4052 u32 buf_chk_sz;
4053 unsigned long off;
4054
4055 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4056 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE;
4057
4058 return (struct hns_roce_aeqe *)((char *)(eq->buf_list->buf) +
4059 off % buf_chk_sz);
4060}
4061
4062static struct hns_roce_aeqe *mhop_get_aeqe(struct hns_roce_eq *eq, u32 entry)
4063{
4064 u32 buf_chk_sz;
4065 unsigned long off;
4066
4067 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4068
4069 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE;
4070
4071 if (eq->hop_num == HNS_ROCE_HOP_NUM_0)
4072 return (struct hns_roce_aeqe *)((u8 *)(eq->bt_l0) +
4073 off % buf_chk_sz);
4074 else
4075 return (struct hns_roce_aeqe *)((u8 *)
4076 (eq->buf[off / buf_chk_sz]) + off % buf_chk_sz);
4077}
4078
4079static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
4080{
4081 struct hns_roce_aeqe *aeqe;
4082
4083 if (!eq->hop_num)
4084 aeqe = get_aeqe_v2(eq, eq->cons_index);
4085 else
4086 aeqe = mhop_get_aeqe(eq, eq->cons_index);
4087
4088 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
4089 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
4090}
4091
4092static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
4093 struct hns_roce_eq *eq)
4094{
4095 struct device *dev = hr_dev->dev;
4096 struct hns_roce_aeqe *aeqe;
4097 int aeqe_found = 0;
4098 int event_type;
4099
4100 while ((aeqe = next_aeqe_sw_v2(eq))) {
4044a3f4
YL		 4101
4102 /* Make sure we read AEQ entry after we have checked the
4103 * ownership bit
4104 */
4105 dma_rmb();
a5073d60
YL		 4106
4107 event_type = roce_get_field(aeqe->asyn,
4108 HNS_ROCE_V2_AEQE_EVENT_TYPE_M,
4109 HNS_ROCE_V2_AEQE_EVENT_TYPE_S);
4110
4111 switch (event_type) {
4112 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
4113 dev_warn(dev, "Path migrated succeeded.\n");
4114 break;
4115 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
4116 dev_warn(dev, "Path migration failed.\n");
4117 break;
4118 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4119 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4120 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
4121 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4122 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
4123 hns_roce_v2_qp_err_handle(hr_dev, aeqe, event_type);
4124 break;
4125 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4126 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4127 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
4128 dev_warn(dev, "SRQ not support.\n");
4129 break;
4130 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4131 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4132 hns_roce_v2_cq_err_handle(hr_dev, aeqe, event_type);
4133 break;
4134 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
4135 dev_warn(dev, "DB overflow.\n");
4136 break;
4137 case HNS_ROCE_EVENT_TYPE_MB:
4138 hns_roce_cmd_event(hr_dev,
4139 le16_to_cpu(aeqe->event.cmd.token),
4140 aeqe->event.cmd.status,
4141 le64_to_cpu(aeqe->event.cmd.out_param));
4142 break;
4143 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
4144 dev_warn(dev, "CEQ overflow.\n");
4145 break;
4146 case HNS_ROCE_EVENT_TYPE_FLR:
4147 dev_warn(dev, "Function level reset.\n");
4148 break;
4149 default:
4150 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n",
4151 event_type, eq->eqn, eq->cons_index);
4152 break;
4153 };
4154
4155 ++eq->cons_index;
4156 aeqe_found = 1;
4157
4158 if (eq->cons_index > (2 * eq->entries - 1)) {
4159 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4160 eq->cons_index = 0;
4161 }
4162 }
4163
4164 set_eq_cons_index_v2(eq);
4165 return aeqe_found;
4166}
4167
4168static struct hns_roce_ceqe *get_ceqe_v2(struct hns_roce_eq *eq, u32 entry)
4169{
4170 u32 buf_chk_sz;
4171 unsigned long off;
4172
4173 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4174 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE;
4175
4176 return (struct hns_roce_ceqe *)((char *)(eq->buf_list->buf) +
4177 off % buf_chk_sz);
4178}
4179
4180static struct hns_roce_ceqe *mhop_get_ceqe(struct hns_roce_eq *eq, u32 entry)
4181{
4182 u32 buf_chk_sz;
4183 unsigned long off;
4184
4185 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4186
4187 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE;
4188
4189 if (eq->hop_num == HNS_ROCE_HOP_NUM_0)
4190 return (struct hns_roce_ceqe *)((u8 *)(eq->bt_l0) +
4191 off % buf_chk_sz);
4192 else
4193 return (struct hns_roce_ceqe *)((u8 *)(eq->buf[off /
4194 buf_chk_sz]) + off % buf_chk_sz);
4195}
4196
4197static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
4198{
4199 struct hns_roce_ceqe *ceqe;
4200
4201 if (!eq->hop_num)
4202 ceqe = get_ceqe_v2(eq, eq->cons_index);
4203 else
4204 ceqe = mhop_get_ceqe(eq, eq->cons_index);
4205
4206 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
4207 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
4208}
4209
4210static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
4211 struct hns_roce_eq *eq)
4212{
4213 struct device *dev = hr_dev->dev;
4214 struct hns_roce_ceqe *ceqe;
4215 int ceqe_found = 0;
4216 u32 cqn;
4217
4218 while ((ceqe = next_ceqe_sw_v2(eq))) {
4219
4044a3f4
YL		 4220 /* Make sure we read CEQ entry after we have checked the
4221 * ownership bit
4222 */
4223 dma_rmb();
4224
a5073d60
YL		 4225 cqn = roce_get_field(ceqe->comp,
4226 HNS_ROCE_V2_CEQE_COMP_CQN_M,
4227 HNS_ROCE_V2_CEQE_COMP_CQN_S);
4228
4229 hns_roce_cq_completion(hr_dev, cqn);
4230
4231 ++eq->cons_index;
4232 ceqe_found = 1;
4233
4234 if (eq->cons_index > (2 * eq->entries - 1)) {
4235 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4236 eq->cons_index = 0;
4237 }
4238 }
4239
4240 set_eq_cons_index_v2(eq);
4241
4242 return ceqe_found;
4243}
4244
4245static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
4246{
4247 struct hns_roce_eq *eq = eq_ptr;
4248 struct hns_roce_dev *hr_dev = eq->hr_dev;
4249 int int_work = 0;
4250
4251 if (eq->type_flag == HNS_ROCE_CEQ)
4252 /* Completion event interrupt */
4253 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
4254 else
4255 /* Asychronous event interrupt */
4256 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
4257
4258 return IRQ_RETVAL(int_work);
4259}
4260
4261static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
4262{
4263 struct hns_roce_dev *hr_dev = dev_id;
4264 struct device *dev = hr_dev->dev;
4265 int int_work = 0;
4266 u32 int_st;
4267 u32 int_en;
4268
4269 /* Abnormal interrupt */
4270 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
4271 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
4272
4273 if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
4274 dev_err(dev, "AEQ overflow!\n");
4275
4276 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S, 1);
4277 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4278
a5073d60
YL		 4279 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4280 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4281
4282 int_work = 1;
4283 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) {
4284 dev_err(dev, "BUS ERR!\n");
4285
4286 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S, 1);
4287 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4288
a5073d60
YL		 4289 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4290 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4291
4292 int_work = 1;
4293 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) {
4294 dev_err(dev, "OTHER ERR!\n");
4295
4296 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S, 1);
4297 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4298
a5073d60
YL		 4299 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4300 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4301
4302 int_work = 1;
4303 } else
4304 dev_err(dev, "There is no abnormal irq found!\n");
4305
4306 return IRQ_RETVAL(int_work);
4307}
4308
4309static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
4310 int eq_num, int enable_flag)
4311{
4312 int i;
4313
4314 if (enable_flag == EQ_ENABLE) {
4315 for (i = 0; i < eq_num; i++)
4316 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
4317 i * EQ_REG_OFFSET,
4318 HNS_ROCE_V2_VF_EVENT_INT_EN_M);
4319
4320 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
4321 HNS_ROCE_V2_VF_ABN_INT_EN_M);
4322 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
4323 HNS_ROCE_V2_VF_ABN_INT_CFG_M);
4324 } else {
4325 for (i = 0; i < eq_num; i++)
4326 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
4327 i * EQ_REG_OFFSET,
4328 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0);
4329
4330 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
4331 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0);
4332 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
4333 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0);
4334 }
4335}
4336
4337static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
4338{
4339 struct device *dev = hr_dev->dev;
4340 int ret;
4341
4342 if (eqn < hr_dev->caps.num_comp_vectors)
4343 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
4344 0, HNS_ROCE_CMD_DESTROY_CEQC,
4345 HNS_ROCE_CMD_TIMEOUT_MSECS);
4346 else
4347 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
4348 0, HNS_ROCE_CMD_DESTROY_AEQC,
4349 HNS_ROCE_CMD_TIMEOUT_MSECS);
4350 if (ret)
4351 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
4352}
4353
4354static void hns_roce_mhop_free_eq(struct hns_roce_dev *hr_dev,
4355 struct hns_roce_eq *eq)
4356{
4357 struct device *dev = hr_dev->dev;
4358 u64 idx;
4359 u64 size;
4360 u32 buf_chk_sz;
4361 u32 bt_chk_sz;
4362 u32 mhop_num;
4363 int eqe_alloc;
a5073d60
YL		 4364 int i = 0;
4365 int j = 0;
4366
4367 mhop_num = hr_dev->caps.eqe_hop_num;
4368 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
4369 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT);
a5073d60
YL		 4370
4371 /* hop_num = 0 */
4372 if (mhop_num == HNS_ROCE_HOP_NUM_0) {
4373 dma_free_coherent(dev, (unsigned int)(eq->entries *
4374 eq->eqe_size), eq->bt_l0, eq->l0_dma);
4375 return;
4376 }
4377
4378 /* hop_num = 1 or hop = 2 */
4379 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
4380 if (mhop_num == 1) {
4381 for (i = 0; i < eq->l0_last_num; i++) {
4382 if (i == eq->l0_last_num - 1) {
4383 eqe_alloc = i * (buf_chk_sz / eq->eqe_size);
4384 size = (eq->entries - eqe_alloc) * eq->eqe_size;
4385 dma_free_coherent(dev, size, eq->buf[i],
4386 eq->buf_dma[i]);
4387 break;
4388 }
4389 dma_free_coherent(dev, buf_chk_sz, eq->buf[i],
4390 eq->buf_dma[i]);
4391 }
4392 } else if (mhop_num == 2) {
4393 for (i = 0; i < eq->l0_last_num; i++) {
4394 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
4395 eq->l1_dma[i]);
4396
4397 for (j = 0; j < bt_chk_sz / 8; j++) {
4398 idx = i * (bt_chk_sz / 8) + j;
4399 if ((i == eq->l0_last_num - 1)
4400 && j == eq->l1_last_num - 1) {
4401 eqe_alloc = (buf_chk_sz / eq->eqe_size)
4402 * idx;
4403 size = (eq->entries - eqe_alloc)
4404 * eq->eqe_size;
4405 dma_free_coherent(dev, size,
4406 eq->buf[idx],
4407 eq->buf_dma[idx]);
4408 break;
4409 }
4410 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx],
4411 eq->buf_dma[idx]);
4412 }
4413 }
4414 }
4415 kfree(eq->buf_dma);
4416 kfree(eq->buf);
4417 kfree(eq->l1_dma);
4418 kfree(eq->bt_l1);
4419 eq->buf_dma = NULL;
4420 eq->buf = NULL;
4421 eq->l1_dma = NULL;
4422 eq->bt_l1 = NULL;
4423}
4424
4425static void hns_roce_v2_free_eq(struct hns_roce_dev *hr_dev,
4426 struct hns_roce_eq *eq)
4427{
4428 u32 buf_chk_sz;
4429
4430 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4431
4432 if (hr_dev->caps.eqe_hop_num) {
4433 hns_roce_mhop_free_eq(hr_dev, eq);
4434 return;
4435 }
4436
4437 if (eq->buf_list)
4438 dma_free_coherent(hr_dev->dev, buf_chk_sz,
4439 eq->buf_list->buf, eq->buf_list->map);
4440}
4441
4442static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev,
4443 struct hns_roce_eq *eq,
4444 void *mb_buf)
4445{
4446 struct hns_roce_eq_context *eqc;
4447
4448 eqc = mb_buf;
4449 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
4450
4451 /* init eqc */
4452 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
4453 eq->hop_num = hr_dev->caps.eqe_hop_num;
4454 eq->cons_index = 0;
4455 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
4456 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
4457 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
4458 eq->eqe_ba_pg_sz = hr_dev->caps.eqe_ba_pg_sz;
4459 eq->eqe_buf_pg_sz = hr_dev->caps.eqe_buf_pg_sz;
4460 eq->shift = ilog2((unsigned int)eq->entries);
4461
4462 if (!eq->hop_num)
4463 eq->eqe_ba = eq->buf_list->map;
4464 else
4465 eq->eqe_ba = eq->l0_dma;
4466
4467 /* set eqc state */
4468 roce_set_field(eqc->byte_4,
4469 HNS_ROCE_EQC_EQ_ST_M,
4470 HNS_ROCE_EQC_EQ_ST_S,
4471 HNS_ROCE_V2_EQ_STATE_VALID);
4472
4473 /* set eqe hop num */
4474 roce_set_field(eqc->byte_4,
4475 HNS_ROCE_EQC_HOP_NUM_M,
4476 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num);
4477
4478 /* set eqc over_ignore */
4479 roce_set_field(eqc->byte_4,
4480 HNS_ROCE_EQC_OVER_IGNORE_M,
4481 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore);
4482
4483 /* set eqc coalesce */
4484 roce_set_field(eqc->byte_4,
4485 HNS_ROCE_EQC_COALESCE_M,
4486 HNS_ROCE_EQC_COALESCE_S, eq->coalesce);
4487
4488 /* set eqc arm_state */
4489 roce_set_field(eqc->byte_4,
4490 HNS_ROCE_EQC_ARM_ST_M,
4491 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st);
4492
4493 /* set eqn */
4494 roce_set_field(eqc->byte_4,
4495 HNS_ROCE_EQC_EQN_M,
4496 HNS_ROCE_EQC_EQN_S, eq->eqn);
4497
4498 /* set eqe_cnt */
4499 roce_set_field(eqc->byte_4,
4500 HNS_ROCE_EQC_EQE_CNT_M,
4501 HNS_ROCE_EQC_EQE_CNT_S,
4502 HNS_ROCE_EQ_INIT_EQE_CNT);
4503
4504 /* set eqe_ba_pg_sz */
4505 roce_set_field(eqc->byte_8,
4506 HNS_ROCE_EQC_BA_PG_SZ_M,
5e6e78db
YL		 4507 HNS_ROCE_EQC_BA_PG_SZ_S,
4508 eq->eqe_ba_pg_sz + PG_SHIFT_OFFSET);
a5073d60
YL		 4509
4510 /* set eqe_buf_pg_sz */
4511 roce_set_field(eqc->byte_8,
4512 HNS_ROCE_EQC_BUF_PG_SZ_M,
5e6e78db
YL		 4513 HNS_ROCE_EQC_BUF_PG_SZ_S,
4514 eq->eqe_buf_pg_sz + PG_SHIFT_OFFSET);
a5073d60
YL		 4515
4516 /* set eq_producer_idx */
4517 roce_set_field(eqc->byte_8,
4518 HNS_ROCE_EQC_PROD_INDX_M,
4519 HNS_ROCE_EQC_PROD_INDX_S,
4520 HNS_ROCE_EQ_INIT_PROD_IDX);
4521
4522 /* set eq_max_cnt */
4523 roce_set_field(eqc->byte_12,
4524 HNS_ROCE_EQC_MAX_CNT_M,
4525 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt);
4526
4527 /* set eq_period */
4528 roce_set_field(eqc->byte_12,
4529 HNS_ROCE_EQC_PERIOD_M,
4530 HNS_ROCE_EQC_PERIOD_S, eq->eq_period);
4531
4532 /* set eqe_report_timer */
4533 roce_set_field(eqc->eqe_report_timer,
4534 HNS_ROCE_EQC_REPORT_TIMER_M,
4535 HNS_ROCE_EQC_REPORT_TIMER_S,
4536 HNS_ROCE_EQ_INIT_REPORT_TIMER);
4537
4538 /* set eqe_ba [34:3] */
4539 roce_set_field(eqc->eqe_ba0,
4540 HNS_ROCE_EQC_EQE_BA_L_M,
4541 HNS_ROCE_EQC_EQE_BA_L_S, eq->eqe_ba >> 3);
4542
4543 /* set eqe_ba [64:35] */
4544 roce_set_field(eqc->eqe_ba1,
4545 HNS_ROCE_EQC_EQE_BA_H_M,
4546 HNS_ROCE_EQC_EQE_BA_H_S, eq->eqe_ba >> 35);
4547
4548 /* set eq shift */
4549 roce_set_field(eqc->byte_28,
4550 HNS_ROCE_EQC_SHIFT_M,
4551 HNS_ROCE_EQC_SHIFT_S, eq->shift);
4552
4553 /* set eq MSI_IDX */
4554 roce_set_field(eqc->byte_28,
4555 HNS_ROCE_EQC_MSI_INDX_M,
4556 HNS_ROCE_EQC_MSI_INDX_S,
4557 HNS_ROCE_EQ_INIT_MSI_IDX);
4558
4559 /* set cur_eqe_ba [27:12] */
4560 roce_set_field(eqc->byte_28,
4561 HNS_ROCE_EQC_CUR_EQE_BA_L_M,
4562 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eq->cur_eqe_ba >> 12);
4563
4564 /* set cur_eqe_ba [59:28] */
4565 roce_set_field(eqc->byte_32,
4566 HNS_ROCE_EQC_CUR_EQE_BA_M_M,
4567 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eq->cur_eqe_ba >> 28);
4568
4569 /* set cur_eqe_ba [63:60] */
4570 roce_set_field(eqc->byte_36,
4571 HNS_ROCE_EQC_CUR_EQE_BA_H_M,
4572 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eq->cur_eqe_ba >> 60);
4573
4574 /* set eq consumer idx */
4575 roce_set_field(eqc->byte_36,
4576 HNS_ROCE_EQC_CONS_INDX_M,
4577 HNS_ROCE_EQC_CONS_INDX_S,
4578 HNS_ROCE_EQ_INIT_CONS_IDX);
4579
4580 /* set nex_eqe_ba[43:12] */
4581 roce_set_field(eqc->nxt_eqe_ba0,
4582 HNS_ROCE_EQC_NXT_EQE_BA_L_M,
4583 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eq->nxt_eqe_ba >> 12);
4584
4585 /* set nex_eqe_ba[63:44] */
4586 roce_set_field(eqc->nxt_eqe_ba1,
4587 HNS_ROCE_EQC_NXT_EQE_BA_H_M,
4588 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eq->nxt_eqe_ba >> 44);
4589}
4590
4591static int hns_roce_mhop_alloc_eq(struct hns_roce_dev *hr_dev,
4592 struct hns_roce_eq *eq)
4593{
4594 struct device *dev = hr_dev->dev;
4595 int eq_alloc_done = 0;
4596 int eq_buf_cnt = 0;
4597 int eqe_alloc;
4598 u32 buf_chk_sz;
4599 u32 bt_chk_sz;
4600 u32 mhop_num;
4601 u64 size;
4602 u64 idx;
4603 int ba_num;
4604 int bt_num;
4605 int record_i;
4606 int record_j;
4607 int i = 0;
4608 int j = 0;
4609
4610 mhop_num = hr_dev->caps.eqe_hop_num;
4611 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
4612 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT);
4613
4614 ba_num = (PAGE_ALIGN(eq->entries * eq->eqe_size) + buf_chk_sz - 1)
4615 / buf_chk_sz;
4616 bt_num = (ba_num + bt_chk_sz / 8 - 1) / (bt_chk_sz / 8);
4617
4618 /* hop_num = 0 */
4619 if (mhop_num == HNS_ROCE_HOP_NUM_0) {
4620 if (eq->entries > buf_chk_sz / eq->eqe_size) {
4621 dev_err(dev, "eq entries %d is larger than buf_pg_sz!",
4622 eq->entries);
4623 return -EINVAL;
4624 }
4625 eq->bt_l0 = dma_alloc_coherent(dev, eq->entries * eq->eqe_size,
4626 &(eq->l0_dma), GFP_KERNEL);
4627 if (!eq->bt_l0)
4628 return -ENOMEM;
4629
4630 eq->cur_eqe_ba = eq->l0_dma;
4631 eq->nxt_eqe_ba = 0;
4632
4633 memset(eq->bt_l0, 0, eq->entries * eq->eqe_size);
4634
4635 return 0;
4636 }
4637
4638 eq->buf_dma = kcalloc(ba_num, sizeof(*eq->buf_dma), GFP_KERNEL);
4639 if (!eq->buf_dma)
4640 return -ENOMEM;
4641 eq->buf = kcalloc(ba_num, sizeof(*eq->buf), GFP_KERNEL);
4642 if (!eq->buf)
4643 goto err_kcalloc_buf;
4644
4645 if (mhop_num == 2) {
4646 eq->l1_dma = kcalloc(bt_num, sizeof(*eq->l1_dma), GFP_KERNEL);
4647 if (!eq->l1_dma)
4648 goto err_kcalloc_l1_dma;
4649
4650 eq->bt_l1 = kcalloc(bt_num, sizeof(*eq->bt_l1), GFP_KERNEL);
4651 if (!eq->bt_l1)
4652 goto err_kcalloc_bt_l1;
4653 }
4654
4655 /* alloc L0 BT */
4656 eq->bt_l0 = dma_alloc_coherent(dev, bt_chk_sz, &eq->l0_dma, GFP_KERNEL);
4657 if (!eq->bt_l0)
4658 goto err_dma_alloc_l0;
4659
4660 if (mhop_num == 1) {
4661 if (ba_num > (bt_chk_sz / 8))
4662 dev_err(dev, "ba_num %d is too large for 1 hop\n",
4663 ba_num);
4664
4665 /* alloc buf */
4666 for (i = 0; i < bt_chk_sz / 8; i++) {
4667 if (eq_buf_cnt + 1 < ba_num) {
4668 size = buf_chk_sz;
4669 } else {
4670 eqe_alloc = i * (buf_chk_sz / eq->eqe_size);
4671 size = (eq->entries - eqe_alloc) * eq->eqe_size;
4672 }
4673 eq->buf[i] = dma_alloc_coherent(dev, size,
4674 &(eq->buf_dma[i]),
4675 GFP_KERNEL);
4676 if (!eq->buf[i])
4677 goto err_dma_alloc_buf;
4678
4679 memset(eq->buf[i], 0, size);
4680 *(eq->bt_l0 + i) = eq->buf_dma[i];
4681
4682 eq_buf_cnt++;
4683 if (eq_buf_cnt >= ba_num)
4684 break;
4685 }
4686 eq->cur_eqe_ba = eq->buf_dma[0];
4687 eq->nxt_eqe_ba = eq->buf_dma[1];
4688
4689 } else if (mhop_num == 2) {
4690 /* alloc L1 BT and buf */
4691 for (i = 0; i < bt_chk_sz / 8; i++) {
4692 eq->bt_l1[i] = dma_alloc_coherent(dev, bt_chk_sz,
4693 &(eq->l1_dma[i]),
4694 GFP_KERNEL);
4695 if (!eq->bt_l1[i])
4696 goto err_dma_alloc_l1;
4697 *(eq->bt_l0 + i) = eq->l1_dma[i];
4698
4699 for (j = 0; j < bt_chk_sz / 8; j++) {
4700 idx = i * bt_chk_sz / 8 + j;
4701 if (eq_buf_cnt + 1 < ba_num) {
4702 size = buf_chk_sz;
4703 } else {
4704 eqe_alloc = (buf_chk_sz / eq->eqe_size)
4705 * idx;
4706 size = (eq->entries - eqe_alloc)
4707 * eq->eqe_size;
4708 }
4709 eq->buf[idx] = dma_alloc_coherent(dev, size,
4710 &(eq->buf_dma[idx]),
4711 GFP_KERNEL);
4712 if (!eq->buf[idx])
4713 goto err_dma_alloc_buf;
4714
4715 memset(eq->buf[idx], 0, size);
4716 *(eq->bt_l1[i] + j) = eq->buf_dma[idx];
4717
4718 eq_buf_cnt++;
4719 if (eq_buf_cnt >= ba_num) {
4720 eq_alloc_done = 1;
4721 break;
4722 }
4723 }
4724
4725 if (eq_alloc_done)
4726 break;
4727 }
4728 eq->cur_eqe_ba = eq->buf_dma[0];
4729 eq->nxt_eqe_ba = eq->buf_dma[1];
4730 }
4731
4732 eq->l0_last_num = i + 1;
4733 if (mhop_num == 2)
4734 eq->l1_last_num = j + 1;
4735
4736 return 0;
4737
4738err_dma_alloc_l1:
4739 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
4740 eq->bt_l0 = NULL;
4741 eq->l0_dma = 0;
4742 for (i -= 1; i >= 0; i--) {
4743 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
4744 eq->l1_dma[i]);
4745
4746 for (j = 0; j < bt_chk_sz / 8; j++) {
4747 idx = i * bt_chk_sz / 8 + j;
4748 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx],
4749 eq->buf_dma[idx]);
4750 }
4751 }
4752 goto err_dma_alloc_l0;
4753
4754err_dma_alloc_buf:
4755 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
4756 eq->bt_l0 = NULL;
4757 eq->l0_dma = 0;
4758
4759 if (mhop_num == 1)
38759d61 4760 for (i -= 1; i >= 0; i--)
a5073d60
YL		 4761 dma_free_coherent(dev, buf_chk_sz, eq->buf[i],
4762 eq->buf_dma[i]);
4763 else if (mhop_num == 2) {
4764 record_i = i;
4765 record_j = j;
4766 for (; i >= 0; i--) {
4767 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
4768 eq->l1_dma[i]);
4769
4770 for (j = 0; j < bt_chk_sz / 8; j++) {
4771 if (i == record_i && j >= record_j)
4772 break;
4773
4774 idx = i * bt_chk_sz / 8 + j;
4775 dma_free_coherent(dev, buf_chk_sz,
4776 eq->buf[idx],
4777 eq->buf_dma[idx]);
4778 }
4779 }
4780 }
4781
4782err_dma_alloc_l0:
4783 kfree(eq->bt_l1);
4784 eq->bt_l1 = NULL;
4785
4786err_kcalloc_bt_l1:
4787 kfree(eq->l1_dma);
4788 eq->l1_dma = NULL;
4789
4790err_kcalloc_l1_dma:
4791 kfree(eq->buf);
4792 eq->buf = NULL;
4793
4794err_kcalloc_buf:
4795 kfree(eq->buf_dma);
4796 eq->buf_dma = NULL;
4797
4798 return -ENOMEM;
4799}
4800
4801static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
4802 struct hns_roce_eq *eq,
4803 unsigned int eq_cmd)
4804{
4805 struct device *dev = hr_dev->dev;
4806 struct hns_roce_cmd_mailbox *mailbox;
4807 u32 buf_chk_sz = 0;
4808 int ret;
4809
4810 /* Allocate mailbox memory */
4811 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4812 if (IS_ERR(mailbox))
4813 return PTR_ERR(mailbox);
4814
4815 if (!hr_dev->caps.eqe_hop_num) {
4816 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
4817
4818 eq->buf_list = kzalloc(sizeof(struct hns_roce_buf_list),
4819 GFP_KERNEL);
4820 if (!eq->buf_list) {
4821 ret = -ENOMEM;
4822 goto free_cmd_mbox;
4823 }
4824
4825 eq->buf_list->buf = dma_alloc_coherent(dev, buf_chk_sz,
4826 &(eq->buf_list->map),
4827 GFP_KERNEL);
4828 if (!eq->buf_list->buf) {
4829 ret = -ENOMEM;
4830 goto err_alloc_buf;
4831 }
4832
4833 memset(eq->buf_list->buf, 0, buf_chk_sz);
4834 } else {
4835 ret = hns_roce_mhop_alloc_eq(hr_dev, eq);
4836 if (ret) {
4837 ret = -ENOMEM;
4838 goto free_cmd_mbox;
4839 }
4840 }
4841
4842 hns_roce_config_eqc(hr_dev, eq, mailbox->buf);
4843
4844 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0,
4845 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS);
4846 if (ret) {
ab178849 4847 dev_err(dev, "[mailbox cmd] create eqc failed.\n");
a5073d60
YL		 4848 goto err_cmd_mbox;
4849 }
4850
4851 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4852
4853 return 0;
4854
4855err_cmd_mbox:
4856 if (!hr_dev->caps.eqe_hop_num)
4857 dma_free_coherent(dev, buf_chk_sz, eq->buf_list->buf,
4858 eq->buf_list->map);
4859 else {
4860 hns_roce_mhop_free_eq(hr_dev, eq);
4861 goto free_cmd_mbox;
4862 }
4863
4864err_alloc_buf:
4865 kfree(eq->buf_list);
4866
4867free_cmd_mbox:
4868 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4869
4870 return ret;
4871}
4872
4873static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
4874{
4875 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4876 struct device *dev = hr_dev->dev;
4877 struct hns_roce_eq *eq;
4878 unsigned int eq_cmd;
4879 int irq_num;
4880 int eq_num;
4881 int other_num;
4882 int comp_num;
4883 int aeq_num;
4884 int i, j, k;
4885 int ret;
4886
4887 other_num = hr_dev->caps.num_other_vectors;
4888 comp_num = hr_dev->caps.num_comp_vectors;
4889 aeq_num = hr_dev->caps.num_aeq_vectors;
4890
4891 eq_num = comp_num + aeq_num;
4892 irq_num = eq_num + other_num;
4893
4894 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
4895 if (!eq_table->eq)
4896 return -ENOMEM;
4897
4898 for (i = 0; i < irq_num; i++) {
4899 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
4900 GFP_KERNEL);
4901 if (!hr_dev->irq_names[i]) {
4902 ret = -ENOMEM;
4903 goto err_failed_kzalloc;
4904 }
4905 }
4906
4907 /* create eq */
4908 for (j = 0; j < eq_num; j++) {
4909 eq = &eq_table->eq[j];
4910 eq->hr_dev = hr_dev;
4911 eq->eqn = j;
4912 if (j < comp_num) {
4913 /* CEQ */
4914 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
4915 eq->type_flag = HNS_ROCE_CEQ;
4916 eq->entries = hr_dev->caps.ceqe_depth;
4917 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
4918 eq->irq = hr_dev->irq[j + other_num + aeq_num];
4919 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
4920 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
4921 } else {
4922 /* AEQ */
4923 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
4924 eq->type_flag = HNS_ROCE_AEQ;
4925 eq->entries = hr_dev->caps.aeqe_depth;
4926 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
4927 eq->irq = hr_dev->irq[j - comp_num + other_num];
4928 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
4929 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
4930 }
4931
4932 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
4933 if (ret) {
4934 dev_err(dev, "eq create failed.\n");
4935 goto err_create_eq_fail;
4936 }
4937 }
4938
4939 /* enable irq */
4940 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
4941
4942 /* irq contains: abnormal + AEQ + CEQ*/
4943 for (k = 0; k < irq_num; k++)
4944 if (k < other_num)
4945 snprintf((char *)hr_dev->irq_names[k],
4946 HNS_ROCE_INT_NAME_LEN, "hns-abn-%d", k);
4947 else if (k < (other_num + aeq_num))
4948 snprintf((char *)hr_dev->irq_names[k],
4949 HNS_ROCE_INT_NAME_LEN, "hns-aeq-%d",
4950 k - other_num);
4951 else
4952 snprintf((char *)hr_dev->irq_names[k],
4953 HNS_ROCE_INT_NAME_LEN, "hns-ceq-%d",
4954 k - other_num - aeq_num);
4955
4956 for (k = 0; k < irq_num; k++) {
4957 if (k < other_num)
4958 ret = request_irq(hr_dev->irq[k],
4959 hns_roce_v2_msix_interrupt_abn,
4960 0, hr_dev->irq_names[k], hr_dev);
4961
4962 else if (k < (other_num + comp_num))
4963 ret = request_irq(eq_table->eq[k - other_num].irq,
4964 hns_roce_v2_msix_interrupt_eq,
4965 0, hr_dev->irq_names[k + aeq_num],
4966 &eq_table->eq[k - other_num]);
4967 else
4968 ret = request_irq(eq_table->eq[k - other_num].irq,
4969 hns_roce_v2_msix_interrupt_eq,
4970 0, hr_dev->irq_names[k - comp_num],
4971 &eq_table->eq[k - other_num]);
4972 if (ret) {
4973 dev_err(dev, "Request irq error!\n");
4974 goto err_request_irq_fail;
4975 }
4976 }
4977
4978 return 0;
4979
4980err_request_irq_fail:
4981 for (k -= 1; k >= 0; k--)
4982 if (k < other_num)
4983 free_irq(hr_dev->irq[k], hr_dev);
4984 else
4985 free_irq(eq_table->eq[k - other_num].irq,
4986 &eq_table->eq[k - other_num]);
4987
4988err_create_eq_fail:
4989 for (j -= 1; j >= 0; j--)
4990 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[j]);
4991
4992err_failed_kzalloc:
4993 for (i -= 1; i >= 0; i--)
4994 kfree(hr_dev->irq_names[i]);
4995 kfree(eq_table->eq);
4996
4997 return ret;
4998}
4999
5000static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
5001{
5002 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5003 int irq_num;
5004 int eq_num;
5005 int i;
5006
5007 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
5008 irq_num = eq_num + hr_dev->caps.num_other_vectors;
5009
5010 /* Disable irq */
5011 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
5012
5013 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
5014 free_irq(hr_dev->irq[i], hr_dev);
5015
5016 for (i = 0; i < eq_num; i++) {
5017 hns_roce_v2_destroy_eqc(hr_dev, i);
5018
5019 free_irq(eq_table->eq[i].irq, &eq_table->eq[i]);
5020
5021 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[i]);
5022 }
5023
5024 for (i = 0; i < irq_num; i++)
5025 kfree(hr_dev->irq_names[i]);
5026
5027 kfree(eq_table->eq);
5028}
5029
a04ff739
WHX		 5030static const struct hns_roce_hw hns_roce_hw_v2 = {
5031 .cmq_init = hns_roce_v2_cmq_init,
5032 .cmq_exit = hns_roce_v2_cmq_exit,
cfc85f3e 5033 .hw_profile = hns_roce_v2_profile,
6b63597d 5034 .hw_init = hns_roce_v2_init,
5035 .hw_exit = hns_roce_v2_exit,
a680f2f3
WHX		 5036 .post_mbox = hns_roce_v2_post_mbox,
5037 .chk_mbox = hns_roce_v2_chk_mbox,
7afddafa
WHX		 5038 .set_gid = hns_roce_v2_set_gid,
5039 .set_mac = hns_roce_v2_set_mac,
3958cc56 5040 .write_mtpt = hns_roce_v2_write_mtpt,
a2c80b7b 5041 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
93aa2187 5042 .write_cqc = hns_roce_v2_write_cqc,
a81fba28
WHX		 5043 .set_hem = hns_roce_v2_set_hem,
5044 .clear_hem = hns_roce_v2_clear_hem,
926a01dc
WHX		 5045 .modify_qp = hns_roce_v2_modify_qp,
5046 .query_qp = hns_roce_v2_query_qp,
5047 .destroy_qp = hns_roce_v2_destroy_qp,
b156269d 5048 .modify_cq = hns_roce_v2_modify_cq,
2d407888
WHX		 5049 .post_send = hns_roce_v2_post_send,
5050 .post_recv = hns_roce_v2_post_recv,
93aa2187
WHX		 5051 .req_notify_cq = hns_roce_v2_req_notify_cq,
5052 .poll_cq = hns_roce_v2_poll_cq,
a5073d60
YL		 5053 .init_eq = hns_roce_v2_init_eq_table,
5054 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
a04ff739 5055};
dd74282d
WHX		 5056
5057static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
5058 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
5059 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
aaa31567
LO		 5060 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
5061 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
dd74282d
WHX		 5062 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
5063 /* required last entry */
5064 {0, }
5065};
5066
f97a62c3 5067MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
5068
dd74282d
WHX		 5069static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
5070 struct hnae3_handle *handle)
5071{
5072 const struct pci_device_id *id;
a5073d60 5073 int i;
dd74282d
WHX		 5074
5075 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
5076 if (!id) {
5077 dev_err(hr_dev->dev, "device is not compatible!\n");
5078 return -ENXIO;
5079 }
5080
5081 hr_dev->hw = &hns_roce_hw_v2;
2d407888
WHX		 5082 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
5083 hr_dev->odb_offset = hr_dev->sdb_offset;
dd74282d
WHX		 5084
5085 /* Get info from NIC driver. */
5086 hr_dev->reg_base = handle->rinfo.roce_io_base;
5087 hr_dev->caps.num_ports = 1;
5088 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
5089 hr_dev->iboe.phy_port[0] = 0;
5090
d4994d2f 5091 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
5092 hr_dev->iboe.netdevs[0]->dev_addr);
5093
a5073d60
YL		 5094 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++)
5095 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
5096 i + handle->rinfo.base_vector);
5097
dd74282d 5098 /* cmd issue mode: 0 is poll, 1 is event */
a5073d60 5099 hr_dev->cmd_mod = 1;
dd74282d
WHX		 5100 hr_dev->loop_idc = 0;
5101
5102 return 0;
5103}
5104
5105static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
5106{
5107 struct hns_roce_dev *hr_dev;
5108 int ret;
5109
5110 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
5111 if (!hr_dev)
5112 return -ENOMEM;
5113
a04ff739
WHX		 5114 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
5115 if (!hr_dev->priv) {
5116 ret = -ENOMEM;
5117 goto error_failed_kzalloc;
5118 }
5119
dd74282d
WHX		 5120 hr_dev->pci_dev = handle->pdev;
5121 hr_dev->dev = &handle->pdev->dev;
5122 handle->priv = hr_dev;
5123
5124 ret = hns_roce_hw_v2_get_cfg(hr_dev, handle);
5125 if (ret) {
5126 dev_err(hr_dev->dev, "Get Configuration failed!\n");
5127 goto error_failed_get_cfg;
5128 }
5129
5130 ret = hns_roce_init(hr_dev);
5131 if (ret) {
5132 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
5133 goto error_failed_get_cfg;
5134 }
5135
5136 return 0;
5137
5138error_failed_get_cfg:
a04ff739
WHX		 5139 kfree(hr_dev->priv);
5140
5141error_failed_kzalloc:
dd74282d
WHX		 5142 ib_dealloc_device(&hr_dev->ib_dev);
5143
5144 return ret;
5145}
5146
5147static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
5148 bool reset)
5149{
5150 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
5151
cb7a94c9
WHX		 5152 if (!hr_dev)
5153 return;
5154
dd74282d 5155 hns_roce_exit(hr_dev);
a04ff739 5156 kfree(hr_dev->priv);
dd74282d
WHX		 5157 ib_dealloc_device(&hr_dev->ib_dev);
5158}
5159
cb7a94c9
WHX		 5160static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
5161{
5162 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
5163 struct ib_event event;
5164
5165 if (!hr_dev) {
5166 dev_err(&handle->pdev->dev,
5167 "Input parameter handle->priv is NULL!\n");
5168 return -EINVAL;
5169 }
5170
5171 hr_dev->active = false;
5172 hr_dev->is_reset = true;
5173
5174 event.event = IB_EVENT_DEVICE_FATAL;
5175 event.device = &hr_dev->ib_dev;
5176 event.element.port_num = 1;
5177 ib_dispatch_event(&event);
5178
5179 return 0;
5180}
5181
5182static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
5183{
5184 int ret;
5185
5186 ret = hns_roce_hw_v2_init_instance(handle);
5187 if (ret) {
5188 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
5189 * callback function, RoCE Engine reinitialize. If RoCE reinit
5190 * failed, we should inform NIC driver.
5191 */
5192 handle->priv = NULL;
5193 dev_err(&handle->pdev->dev,
5194 "In reset process RoCE reinit failed %d.\n", ret);
5195 }
5196
5197 return ret;
5198}
5199
5200static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
5201{
5202 msleep(100);
5203 hns_roce_hw_v2_uninit_instance(handle, false);
5204 return 0;
5205}
5206
5207static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
5208 enum hnae3_reset_notify_type type)
5209{
5210 int ret = 0;
5211
5212 switch (type) {
5213 case HNAE3_DOWN_CLIENT:
5214 ret = hns_roce_hw_v2_reset_notify_down(handle);
5215 break;
5216 case HNAE3_INIT_CLIENT:
5217 ret = hns_roce_hw_v2_reset_notify_init(handle);
5218 break;
5219 case HNAE3_UNINIT_CLIENT:
5220 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
5221 break;
5222 default:
5223 break;
5224 }
5225
5226 return ret;
5227}
5228
dd74282d
WHX		 5229static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
5230 .init_instance = hns_roce_hw_v2_init_instance,
5231 .uninit_instance = hns_roce_hw_v2_uninit_instance,
cb7a94c9 5232 .reset_notify = hns_roce_hw_v2_reset_notify,
dd74282d
WHX		 5233};
5234
5235static struct hnae3_client hns_roce_hw_v2_client = {
5236 .name = "hns_roce_hw_v2",
5237 .type = HNAE3_CLIENT_ROCE,
5238 .ops = &hns_roce_hw_v2_ops,
5239};
5240
5241static int __init hns_roce_hw_v2_init(void)
5242{
5243 return hnae3_register_client(&hns_roce_hw_v2_client);
5244}
5245
5246static void __exit hns_roce_hw_v2_exit(void)
5247{
5248 hnae3_unregister_client(&hns_roce_hw_v2_client);
5249}
5250
5251module_init(hns_roce_hw_v2_init);
5252module_exit(hns_roce_hw_v2_exit);
5253
5254MODULE_LICENSE("Dual BSD/GPL");
5255MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
5256MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
5257MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
5258MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)