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RDMA/cxgb4: Use correct QID in insert_recv_cqe()
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / qp.c
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#include "iw_cxgb4.h"
33
a9c77198 34static int ocqp_support = 1;
c6d7b267 35module_param(ocqp_support, int, 0644);
a9c77198 36MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
c6d7b267 37
2f5b48c3
SW		 38static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
39{
40 unsigned long flag;
41 spin_lock_irqsave(&qhp->lock, flag);
42 qhp->attr.state = state;
43 spin_unlock_irqrestore(&qhp->lock, flag);
44}
45
c6d7b267
SW		 46static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
47{
48 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
49}
50
51static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
52{
53 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
54 pci_unmap_addr(sq, mapping));
55}
56
57static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
58{
59 if (t4_sq_onchip(sq))
60 dealloc_oc_sq(rdev, sq);
61 else
62 dealloc_host_sq(rdev, sq);
63}
64
65static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
66{
67 if (!ocqp_support || !t4_ocqp_supported())
68 return -ENOSYS;
69 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
70 if (!sq->dma_addr)
71 return -ENOMEM;
72 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
73 rdev->lldi.vr->ocq.start;
74 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
75 rdev->lldi.vr->ocq.start);
76 sq->flags |= T4_SQ_ONCHIP;
77 return 0;
78}
79
80static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
81{
82 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
83 &(sq->dma_addr), GFP_KERNEL);
84 if (!sq->queue)
85 return -ENOMEM;
86 sq->phys_addr = virt_to_phys(sq->queue);
87 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
88 return 0;
89}
90
cfdda9d7
SW		 91static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
92 struct c4iw_dev_ucontext *uctx)
93{
94 /*
95 * uP clears EQ contexts when the connection exits rdma mode,
96 * so no need to post a RESET WR for these EQs.
97 */
98 dma_free_coherent(&(rdev->lldi.pdev->dev),
99 wq->rq.memsize, wq->rq.queue,
f38926aa 100 dma_unmap_addr(&wq->rq, mapping));
c6d7b267 101 dealloc_sq(rdev, &wq->sq);
cfdda9d7
SW		 102 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
103 kfree(wq->rq.sw_rq);
104 kfree(wq->sq.sw_sq);
105 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
106 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
107 return 0;
108}
109
110static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
111 struct t4_cq *rcq, struct t4_cq *scq,
112 struct c4iw_dev_ucontext *uctx)
113{
114 int user = (uctx != &rdev->uctx);
115 struct fw_ri_res_wr *res_wr;
116 struct fw_ri_res *res;
117 int wr_len;
118 struct c4iw_wr_wait wr_wait;
119 struct sk_buff *skb;
120 int ret;
121 int eqsize;
122
123 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
124 if (!wq->sq.qid)
125 return -ENOMEM;
126
127 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
128 if (!wq->rq.qid)
129 goto err1;
130
131 if (!user) {
132 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
133 GFP_KERNEL);
134 if (!wq->sq.sw_sq)
135 goto err2;
136
137 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
138 GFP_KERNEL);
139 if (!wq->rq.sw_rq)
140 goto err3;
141 }
142
143 /*
144 * RQT must be a power of 2.
145 */
146 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
147 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
148 if (!wq->rq.rqt_hwaddr)
149 goto err4;
150
c6d7b267
SW		 151 if (user) {
152 if (alloc_oc_sq(rdev, &wq->sq) && alloc_host_sq(rdev, &wq->sq))
153 goto err5;
154 } else
155 if (alloc_host_sq(rdev, &wq->sq))
156 goto err5;
cfdda9d7 157 memset(wq->sq.queue, 0, wq->sq.memsize);
f38926aa 158 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
cfdda9d7
SW		 159
160 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
161 wq->rq.memsize, &(wq->rq.dma_addr),
162 GFP_KERNEL);
163 if (!wq->rq.queue)
164 goto err6;
165 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
166 __func__, wq->sq.queue,
167 (unsigned long long)virt_to_phys(wq->sq.queue),
168 wq->rq.queue,
169 (unsigned long long)virt_to_phys(wq->rq.queue));
170 memset(wq->rq.queue, 0, wq->rq.memsize);
f38926aa 171 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
cfdda9d7
SW		 172
173 wq->db = rdev->lldi.db_reg;
174 wq->gts = rdev->lldi.gts_reg;
175 if (user) {
176 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
177 (wq->sq.qid << rdev->qpshift);
178 wq->sq.udb &= PAGE_MASK;
179 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
180 (wq->rq.qid << rdev->qpshift);
181 wq->rq.udb &= PAGE_MASK;
182 }
183 wq->rdev = rdev;
184 wq->rq.msn = 1;
185
186 /* build fw_ri_res_wr */
187 wr_len = sizeof *res_wr + 2 * sizeof *res;
188
d3c814e8 189 skb = alloc_skb(wr_len, GFP_KERNEL);
cfdda9d7
SW		 190 if (!skb) {
191 ret = -ENOMEM;
192 goto err7;
193 }
194 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
195
196 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
197 memset(res_wr, 0, wr_len);
198 res_wr->op_nres = cpu_to_be32(
199 FW_WR_OP(FW_RI_RES_WR) |
200 V_FW_RI_RES_WR_NRES(2) |
201 FW_WR_COMPL(1));
202 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
c8e081a1 203 res_wr->cookie = (unsigned long) &wr_wait;
cfdda9d7
SW		 204 res = res_wr->res;
205 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
206 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
207
208 /*
209 * eqsize is the number of 64B entries plus the status page size.
210 */
211 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
212
213 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
214 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
215 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
216 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
85d215b0 217 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
cfdda9d7
SW		 218 V_FW_RI_RES_WR_IQID(scq->cqid));
219 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
220 V_FW_RI_RES_WR_DCAEN(0) |
221 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 222 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 223 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 224 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
225 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
226 V_FW_RI_RES_WR_EQSIZE(eqsize));
227 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
228 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
229 res++;
230 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
231 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
232
233 /*
234 * eqsize is the number of 64B entries plus the status page size.
235 */
236 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
237 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
238 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
239 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
240 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
241 V_FW_RI_RES_WR_IQID(rcq->cqid));
242 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
243 V_FW_RI_RES_WR_DCAEN(0) |
244 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 245 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 246 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 247 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
248 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
249 V_FW_RI_RES_WR_EQSIZE(eqsize));
250 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
251 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
252
253 c4iw_init_wr_wait(&wr_wait);
254
255 ret = c4iw_ofld_send(rdev, skb);
256 if (ret)
257 goto err7;
aadc4df3 258 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
cfdda9d7
SW		 259 if (ret)
260 goto err7;
261
262 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
263 __func__, wq->sq.qid, wq->rq.qid, wq->db,
264 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
265
266 return 0;
267err7:
268 dma_free_coherent(&(rdev->lldi.pdev->dev),
269 wq->rq.memsize, wq->rq.queue,
f38926aa 270 dma_unmap_addr(&wq->rq, mapping));
cfdda9d7 271err6:
c6d7b267 272 dealloc_sq(rdev, &wq->sq);
cfdda9d7
SW		 273err5:
274 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
275err4:
276 kfree(wq->rq.sw_rq);
277err3:
278 kfree(wq->sq.sw_sq);
279err2:
280 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
281err1:
282 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
283 return -ENOMEM;
284}
285
d37ac31d
SW		 286static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
287 struct ib_send_wr *wr, int max, u32 *plenp)
cfdda9d7 288{
d37ac31d
SW		 289 u8 *dstp, *srcp;
290 u32 plen = 0;
cfdda9d7 291 int i;
d37ac31d
SW		 292 int rem, len;
293
294 dstp = (u8 *)immdp->data;
295 for (i = 0; i < wr->num_sge; i++) {
296 if ((plen + wr->sg_list[i].length) > max)
297 return -EMSGSIZE;
298 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
299 plen += wr->sg_list[i].length;
300 rem = wr->sg_list[i].length;
301 while (rem) {
302 if (dstp == (u8 *)&sq->queue[sq->size])
303 dstp = (u8 *)sq->queue;
304 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
305 len = rem;
306 else
307 len = (u8 *)&sq->queue[sq->size] - dstp;
308 memcpy(dstp, srcp, len);
309 dstp += len;
310 srcp += len;
311 rem -= len;
312 }
313 }
13fecb83
SW		 314 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
315 if (len)
316 memset(dstp, 0, len);
d37ac31d
SW		 317 immdp->op = FW_RI_DATA_IMMD;
318 immdp->r1 = 0;
319 immdp->r2 = 0;
320 immdp->immdlen = cpu_to_be32(plen);
321 *plenp = plen;
322 return 0;
323}
324
325static int build_isgl(__be64 *queue_start, __be64 *queue_end,
326 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
327 int num_sge, u32 *plenp)
328
329{
330 int i;
331 u32 plen = 0;
332 __be64 *flitp = (__be64 *)isglp->sge;
333
334 for (i = 0; i < num_sge; i++) {
335 if ((plen + sg_list[i].length) < plen)
336 return -EMSGSIZE;
337 plen += sg_list[i].length;
338 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
339 sg_list[i].length);
340 if (++flitp == queue_end)
341 flitp = queue_start;
342 *flitp = cpu_to_be64(sg_list[i].addr);
343 if (++flitp == queue_end)
344 flitp = queue_start;
345 }
13fecb83 346 *flitp = (__force __be64)0;
d37ac31d
SW		 347 isglp->op = FW_RI_DATA_ISGL;
348 isglp->r1 = 0;
349 isglp->nsge = cpu_to_be16(num_sge);
350 isglp->r2 = 0;
351 if (plenp)
352 *plenp = plen;
353 return 0;
354}
355
356static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
357 struct ib_send_wr *wr, u8 *len16)
358{
cfdda9d7
SW		 359 u32 plen;
360 int size;
d37ac31d 361 int ret;
cfdda9d7
SW		 362
363 if (wr->num_sge > T4_MAX_SEND_SGE)
364 return -EINVAL;
365 switch (wr->opcode) {
366 case IB_WR_SEND:
367 if (wr->send_flags & IB_SEND_SOLICITED)
368 wqe->send.sendop_pkd = cpu_to_be32(
369 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
370 else
371 wqe->send.sendop_pkd = cpu_to_be32(
372 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
373 wqe->send.stag_inv = 0;
374 break;
375 case IB_WR_SEND_WITH_INV:
376 if (wr->send_flags & IB_SEND_SOLICITED)
377 wqe->send.sendop_pkd = cpu_to_be32(
378 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
379 else
380 wqe->send.sendop_pkd = cpu_to_be32(
381 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
382 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
383 break;
384
385 default:
386 return -EINVAL;
387 }
d37ac31d 388
cfdda9d7
SW		 389 plen = 0;
390 if (wr->num_sge) {
391 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 392 ret = build_immd(sq, wqe->send.u.immd_src, wr,
393 T4_MAX_SEND_INLINE, &plen);
394 if (ret)
395 return ret;
cfdda9d7
SW		 396 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
397 plen;
398 } else {
d37ac31d
SW		 399 ret = build_isgl((__be64 *)sq->queue,
400 (__be64 *)&sq->queue[sq->size],
401 wqe->send.u.isgl_src,
402 wr->sg_list, wr->num_sge, &plen);
403 if (ret)
404 return ret;
cfdda9d7
SW		 405 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
406 wr->num_sge * sizeof(struct fw_ri_sge);
407 }
408 } else {
409 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
410 wqe->send.u.immd_src[0].r1 = 0;
411 wqe->send.u.immd_src[0].r2 = 0;
412 wqe->send.u.immd_src[0].immdlen = 0;
413 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
d37ac31d 414 plen = 0;
cfdda9d7
SW		 415 }
416 *len16 = DIV_ROUND_UP(size, 16);
417 wqe->send.plen = cpu_to_be32(plen);
418 return 0;
419}
420
d37ac31d
SW		 421static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
422 struct ib_send_wr *wr, u8 *len16)
cfdda9d7 423{
cfdda9d7
SW		 424 u32 plen;
425 int size;
d37ac31d 426 int ret;
cfdda9d7 427
d37ac31d 428 if (wr->num_sge > T4_MAX_SEND_SGE)
cfdda9d7
SW		 429 return -EINVAL;
430 wqe->write.r2 = 0;
431 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
432 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
cfdda9d7
SW		 433 if (wr->num_sge) {
434 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 435 ret = build_immd(sq, wqe->write.u.immd_src, wr,
436 T4_MAX_WRITE_INLINE, &plen);
437 if (ret)
438 return ret;
cfdda9d7
SW		 439 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
440 plen;
441 } else {
d37ac31d
SW		 442 ret = build_isgl((__be64 *)sq->queue,
443 (__be64 *)&sq->queue[sq->size],
444 wqe->write.u.isgl_src,
445 wr->sg_list, wr->num_sge, &plen);
446 if (ret)
447 return ret;
cfdda9d7
SW		 448 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
449 wr->num_sge * sizeof(struct fw_ri_sge);
450 }
451 } else {
452 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
453 wqe->write.u.immd_src[0].r1 = 0;
454 wqe->write.u.immd_src[0].r2 = 0;
455 wqe->write.u.immd_src[0].immdlen = 0;
456 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
d37ac31d 457 plen = 0;
cfdda9d7
SW		 458 }
459 *len16 = DIV_ROUND_UP(size, 16);
460 wqe->write.plen = cpu_to_be32(plen);
461 return 0;
462}
463
464static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
465{
466 if (wr->num_sge > 1)
467 return -EINVAL;
468 if (wr->num_sge) {
469 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
470 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
471 >> 32));
472 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
473 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
474 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
475 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
476 >> 32));
477 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
478 } else {
479 wqe->read.stag_src = cpu_to_be32(2);
480 wqe->read.to_src_hi = 0;
481 wqe->read.to_src_lo = 0;
482 wqe->read.stag_sink = cpu_to_be32(2);
483 wqe->read.plen = 0;
484 wqe->read.to_sink_hi = 0;
485 wqe->read.to_sink_lo = 0;
486 }
487 wqe->read.r2 = 0;
488 wqe->read.r5 = 0;
489 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
490 return 0;
491}
492
493static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
494 struct ib_recv_wr *wr, u8 *len16)
495{
d37ac31d 496 int ret;
cfdda9d7 497
d37ac31d
SW		 498 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
499 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
500 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
501 if (ret)
502 return ret;
cfdda9d7
SW		 503 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
504 wr->num_sge * sizeof(struct fw_ri_sge), 16);
505 return 0;
506}
507
40dbf6ee
SW		 508static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
509 struct ib_send_wr *wr, u8 *len16)
cfdda9d7
SW		 510{
511
512 struct fw_ri_immd *imdp;
513 __be64 *p;
514 int i;
515 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
40dbf6ee 516 int rem;
cfdda9d7
SW		 517
518 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
519 return -EINVAL;
520
521 wqe->fr.qpbinde_to_dcacpu = 0;
522 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
523 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
524 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
525 wqe->fr.len_hi = 0;
526 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
527 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
528 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
529 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
530 0xffffffff);
40dbf6ee
SW		 531 WARN_ON(pbllen > T4_MAX_FR_IMMD);
532 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
533 imdp->op = FW_RI_DATA_IMMD;
534 imdp->r1 = 0;
535 imdp->r2 = 0;
536 imdp->immdlen = cpu_to_be32(pbllen);
537 p = (__be64 *)(imdp + 1);
538 rem = pbllen;
539 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
540 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]);
541 rem -= sizeof *p;
542 if (++p == (__be64 *)&sq->queue[sq->size])
543 p = (__be64 *)sq->queue;
544 }
545 BUG_ON(rem < 0);
546 while (rem) {
547 *p = 0;
548 rem -= sizeof *p;
549 if (++p == (__be64 *)&sq->queue[sq->size])
550 p = (__be64 *)sq->queue;
cfdda9d7 551 }
40dbf6ee 552 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16);
cfdda9d7
SW		 553 return 0;
554}
555
556static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
557 u8 *len16)
558{
559 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
560 wqe->inv.r2 = 0;
561 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
562 return 0;
563}
564
565void c4iw_qp_add_ref(struct ib_qp *qp)
566{
567 PDBG("%s ib_qp %p\n", __func__, qp);
568 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
569}
570
571void c4iw_qp_rem_ref(struct ib_qp *qp)
572{
573 PDBG("%s ib_qp %p\n", __func__, qp);
574 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
575 wake_up(&(to_c4iw_qp(qp)->wait));
576}
577
578int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
579 struct ib_send_wr **bad_wr)
580{
581 int err = 0;
582 u8 len16 = 0;
583 enum fw_wr_opcodes fw_opcode = 0;
584 enum fw_ri_wr_flags fw_flags;
585 struct c4iw_qp *qhp;
586 union t4_wr *wqe;
587 u32 num_wrs;
588 struct t4_swsqe *swsqe;
589 unsigned long flag;
590 u16 idx = 0;
591
592 qhp = to_c4iw_qp(ibqp);
593 spin_lock_irqsave(&qhp->lock, flag);
594 if (t4_wq_in_error(&qhp->wq)) {
595 spin_unlock_irqrestore(&qhp->lock, flag);
596 return -EINVAL;
597 }
598 num_wrs = t4_sq_avail(&qhp->wq);
599 if (num_wrs == 0) {
600 spin_unlock_irqrestore(&qhp->lock, flag);
601 return -ENOMEM;
602 }
603 while (wr) {
604 if (num_wrs == 0) {
605 err = -ENOMEM;
606 *bad_wr = wr;
607 break;
608 }
d37ac31d
SW		 609 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
610 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
611
cfdda9d7
SW		 612 fw_flags = 0;
613 if (wr->send_flags & IB_SEND_SOLICITED)
614 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
615 if (wr->send_flags & IB_SEND_SIGNALED)
616 fw_flags |= FW_RI_COMPLETION_FLAG;
617 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
618 switch (wr->opcode) {
619 case IB_WR_SEND_WITH_INV:
620 case IB_WR_SEND:
621 if (wr->send_flags & IB_SEND_FENCE)
622 fw_flags |= FW_RI_READ_FENCE_FLAG;
623 fw_opcode = FW_RI_SEND_WR;
624 if (wr->opcode == IB_WR_SEND)
625 swsqe->opcode = FW_RI_SEND;
626 else
627 swsqe->opcode = FW_RI_SEND_WITH_INV;
d37ac31d 628 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 629 break;
630 case IB_WR_RDMA_WRITE:
631 fw_opcode = FW_RI_RDMA_WRITE_WR;
632 swsqe->opcode = FW_RI_RDMA_WRITE;
d37ac31d 633 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 634 break;
635 case IB_WR_RDMA_READ:
2f1fb507 636 case IB_WR_RDMA_READ_WITH_INV:
cfdda9d7
SW		 637 fw_opcode = FW_RI_RDMA_READ_WR;
638 swsqe->opcode = FW_RI_READ_REQ;
2f1fb507 639 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
410ade4c 640 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
2f1fb507
SW		 641 else
642 fw_flags = 0;
cfdda9d7
SW		 643 err = build_rdma_read(wqe, wr, &len16);
644 if (err)
645 break;
646 swsqe->read_len = wr->sg_list[0].length;
647 if (!qhp->wq.sq.oldest_read)
648 qhp->wq.sq.oldest_read = swsqe;
649 break;
650 case IB_WR_FAST_REG_MR:
651 fw_opcode = FW_RI_FR_NSMR_WR;
652 swsqe->opcode = FW_RI_FAST_REGISTER;
40dbf6ee 653 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 654 break;
655 case IB_WR_LOCAL_INV:
4ab1eb9c
SW		 656 if (wr->send_flags & IB_SEND_FENCE)
657 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
cfdda9d7
SW		 658 fw_opcode = FW_RI_INV_LSTAG_WR;
659 swsqe->opcode = FW_RI_LOCAL_INV;
660 err = build_inv_stag(wqe, wr, &len16);
661 break;
662 default:
663 PDBG("%s post of type=%d TBD!\n", __func__,
664 wr->opcode);
665 err = -EINVAL;
666 }
667 if (err) {
668 *bad_wr = wr;
669 break;
670 }
671 swsqe->idx = qhp->wq.sq.pidx;
672 swsqe->complete = 0;
673 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
674 swsqe->wr_id = wr->wr_id;
675
676 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
677
678 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
679 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
680 swsqe->opcode, swsqe->read_len);
681 wr = wr->next;
682 num_wrs--;
d37ac31d
SW		 683 t4_sq_produce(&qhp->wq, len16);
684 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 685 }
686 if (t4_wq_db_enabled(&qhp->wq))
687 t4_ring_sq_db(&qhp->wq, idx);
688 spin_unlock_irqrestore(&qhp->lock, flag);
689 return err;
690}
691
692int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
693 struct ib_recv_wr **bad_wr)
694{
695 int err = 0;
696 struct c4iw_qp *qhp;
697 union t4_recv_wr *wqe;
698 u32 num_wrs;
699 u8 len16 = 0;
700 unsigned long flag;
701 u16 idx = 0;
702
703 qhp = to_c4iw_qp(ibqp);
704 spin_lock_irqsave(&qhp->lock, flag);
705 if (t4_wq_in_error(&qhp->wq)) {
706 spin_unlock_irqrestore(&qhp->lock, flag);
707 return -EINVAL;
708 }
709 num_wrs = t4_rq_avail(&qhp->wq);
710 if (num_wrs == 0) {
711 spin_unlock_irqrestore(&qhp->lock, flag);
712 return -ENOMEM;
713 }
714 while (wr) {
715 if (wr->num_sge > T4_MAX_RECV_SGE) {
716 err = -EINVAL;
717 *bad_wr = wr;
718 break;
719 }
d37ac31d
SW		 720 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
721 qhp->wq.rq.wq_pidx *
722 T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 723 if (num_wrs)
724 err = build_rdma_recv(qhp, wqe, wr, &len16);
725 else
726 err = -ENOMEM;
727 if (err) {
728 *bad_wr = wr;
729 break;
730 }
731
732 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
733
734 wqe->recv.opcode = FW_RI_RECV_WR;
735 wqe->recv.r1 = 0;
736 wqe->recv.wrid = qhp->wq.rq.pidx;
737 wqe->recv.r2[0] = 0;
738 wqe->recv.r2[1] = 0;
739 wqe->recv.r2[2] = 0;
740 wqe->recv.len16 = len16;
cfdda9d7
SW		 741 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
742 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
d37ac31d
SW		 743 t4_rq_produce(&qhp->wq, len16);
744 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 745 wr = wr->next;
746 num_wrs--;
cfdda9d7
SW		 747 }
748 if (t4_wq_db_enabled(&qhp->wq))
749 t4_ring_rq_db(&qhp->wq, idx);
750 spin_unlock_irqrestore(&qhp->lock, flag);
751 return err;
752}
753
754int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
755{
756 return -ENOSYS;
757}
758
759static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
760 u8 *ecode)
761{
762 int status;
763 int tagged;
764 int opcode;
765 int rqtype;
766 int send_inv;
767
768 if (!err_cqe) {
769 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
770 *ecode = 0;
771 return;
772 }
773
774 status = CQE_STATUS(err_cqe);
775 opcode = CQE_OPCODE(err_cqe);
776 rqtype = RQ_TYPE(err_cqe);
777 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
778 (opcode == FW_RI_SEND_WITH_SE_INV);
779 tagged = (opcode == FW_RI_RDMA_WRITE) ||
780 (rqtype && (opcode == FW_RI_READ_RESP));
781
782 switch (status) {
783 case T4_ERR_STAG:
784 if (send_inv) {
785 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
786 *ecode = RDMAP_CANT_INV_STAG;
787 } else {
788 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
789 *ecode = RDMAP_INV_STAG;
790 }
791 break;
792 case T4_ERR_PDID:
793 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
794 if ((opcode == FW_RI_SEND_WITH_INV) ||
795 (opcode == FW_RI_SEND_WITH_SE_INV))
796 *ecode = RDMAP_CANT_INV_STAG;
797 else
798 *ecode = RDMAP_STAG_NOT_ASSOC;
799 break;
800 case T4_ERR_QPID:
801 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
802 *ecode = RDMAP_STAG_NOT_ASSOC;
803 break;
804 case T4_ERR_ACCESS:
805 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
806 *ecode = RDMAP_ACC_VIOL;
807 break;
808 case T4_ERR_WRAP:
809 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
810 *ecode = RDMAP_TO_WRAP;
811 break;
812 case T4_ERR_BOUND:
813 if (tagged) {
814 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
815 *ecode = DDPT_BASE_BOUNDS;
816 } else {
817 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
818 *ecode = RDMAP_BASE_BOUNDS;
819 }
820 break;
821 case T4_ERR_INVALIDATE_SHARED_MR:
822 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
823 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
824 *ecode = RDMAP_CANT_INV_STAG;
825 break;
826 case T4_ERR_ECC:
827 case T4_ERR_ECC_PSTAG:
828 case T4_ERR_INTERNAL_ERR:
829 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
830 *ecode = 0;
831 break;
832 case T4_ERR_OUT_OF_RQE:
833 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
834 *ecode = DDPU_INV_MSN_NOBUF;
835 break;
836 case T4_ERR_PBL_ADDR_BOUND:
837 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
838 *ecode = DDPT_BASE_BOUNDS;
839 break;
840 case T4_ERR_CRC:
841 *layer_type = LAYER_MPA|DDP_LLP;
842 *ecode = MPA_CRC_ERR;
843 break;
844 case T4_ERR_MARKER:
845 *layer_type = LAYER_MPA|DDP_LLP;
846 *ecode = MPA_MARKER_ERR;
847 break;
848 case T4_ERR_PDU_LEN_ERR:
849 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
850 *ecode = DDPU_MSG_TOOBIG;
851 break;
852 case T4_ERR_DDP_VERSION:
853 if (tagged) {
854 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
855 *ecode = DDPT_INV_VERS;
856 } else {
857 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
858 *ecode = DDPU_INV_VERS;
859 }
860 break;
861 case T4_ERR_RDMA_VERSION:
862 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
863 *ecode = RDMAP_INV_VERS;
864 break;
865 case T4_ERR_OPCODE:
866 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
867 *ecode = RDMAP_INV_OPCODE;
868 break;
869 case T4_ERR_DDP_QUEUE_NUM:
870 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
871 *ecode = DDPU_INV_QN;
872 break;
873 case T4_ERR_MSN:
874 case T4_ERR_MSN_GAP:
875 case T4_ERR_MSN_RANGE:
876 case T4_ERR_IRD_OVERFLOW:
877 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
878 *ecode = DDPU_INV_MSN_RANGE;
879 break;
880 case T4_ERR_TBIT:
881 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
882 *ecode = 0;
883 break;
884 case T4_ERR_MO:
885 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
886 *ecode = DDPU_INV_MO;
887 break;
888 default:
889 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
890 *ecode = 0;
891 break;
892 }
893}
894
be4c9bad
RD		 895static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
896 gfp_t gfp)
cfdda9d7
SW		 897{
898 struct fw_ri_wr *wqe;
899 struct sk_buff *skb;
900 struct terminate_message *term;
901
902 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
903 qhp->ep->hwtid);
904
be4c9bad 905 skb = alloc_skb(sizeof *wqe, gfp);
cfdda9d7 906 if (!skb)
be4c9bad 907 return;
cfdda9d7
SW		 908 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
909
910 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
911 memset(wqe, 0, sizeof *wqe);
912 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
913 wqe->flowid_len16 = cpu_to_be32(
914 FW_WR_FLOWID(qhp->ep->hwtid) |
915 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
916
917 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
918 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
919 term = (struct terminate_message *)wqe->u.terminate.termmsg;
920 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
be4c9bad 921 c4iw_ofld_send(&qhp->rhp->rdev, skb);
cfdda9d7
SW		 922}
923
924/*
925 * Assumes qhp lock is held.
926 */
927static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
2f5b48c3 928 struct c4iw_cq *schp)
cfdda9d7
SW		 929{
930 int count;
931 int flushed;
2f5b48c3 932 unsigned long flag;
cfdda9d7
SW		 933
934 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
cfdda9d7 935
732bee7a 936 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 937 spin_lock_irqsave(&rchp->lock, flag);
cfdda9d7
SW		 938 spin_lock(&qhp->lock);
939 c4iw_flush_hw_cq(&rchp->cq);
940 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
941 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
942 spin_unlock(&qhp->lock);
2f5b48c3 943 spin_unlock_irqrestore(&rchp->lock, flag);
cfdda9d7
SW		 944 if (flushed)
945 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
946
732bee7a 947 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 948 spin_lock_irqsave(&schp->lock, flag);
cfdda9d7
SW		 949 spin_lock(&qhp->lock);
950 c4iw_flush_hw_cq(&schp->cq);
951 c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
952 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
953 spin_unlock(&qhp->lock);
2f5b48c3 954 spin_unlock_irqrestore(&schp->lock, flag);
cfdda9d7
SW		 955 if (flushed)
956 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
cfdda9d7
SW		 957}
958
2f5b48c3 959static void flush_qp(struct c4iw_qp *qhp)
cfdda9d7
SW		 960{
961 struct c4iw_cq *rchp, *schp;
962
963 rchp = get_chp(qhp->rhp, qhp->attr.rcq);
964 schp = get_chp(qhp->rhp, qhp->attr.scq);
965
966 if (qhp->ibqp.uobject) {
967 t4_set_wq_in_error(&qhp->wq);
968 t4_set_cq_in_error(&rchp->cq);
01e7da6b
KS		 969 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
970 if (schp != rchp) {
cfdda9d7 971 t4_set_cq_in_error(&schp->cq);
01e7da6b
KS		 972 (*schp->ibcq.comp_handler)(&schp->ibcq,
973 schp->ibcq.cq_context);
974 }
cfdda9d7
SW		 975 return;
976 }
2f5b48c3 977 __flush_qp(qhp, rchp, schp);
cfdda9d7
SW		 978}
979
73d6fcad
SW		 980static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
981 struct c4iw_ep *ep)
cfdda9d7
SW		 982{
983 struct fw_ri_wr *wqe;
984 int ret;
cfdda9d7
SW		 985 struct sk_buff *skb;
986
987 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
73d6fcad 988 ep->hwtid);
cfdda9d7 989
d3c814e8 990 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 991 if (!skb)
992 return -ENOMEM;
73d6fcad 993 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
cfdda9d7
SW		 994
995 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
996 memset(wqe, 0, sizeof *wqe);
997 wqe->op_compl = cpu_to_be32(
998 FW_WR_OP(FW_RI_INIT_WR) |
999 FW_WR_COMPL(1));
1000 wqe->flowid_len16 = cpu_to_be32(
73d6fcad 1001 FW_WR_FLOWID(ep->hwtid) |
cfdda9d7 1002 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
2f5b48c3 1003 wqe->cookie = (unsigned long) &ep->com.wr_wait;
cfdda9d7
SW		 1004
1005 wqe->u.fini.type = FW_RI_TYPE_FINI;
cfdda9d7
SW		 1006 ret = c4iw_ofld_send(&rhp->rdev, skb);
1007 if (ret)
1008 goto out;
1009
2f5b48c3 1010 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
aadc4df3 1011 qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1012out:
1013 PDBG("%s ret %d\n", __func__, ret);
1014 return ret;
1015}
1016
1017static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1018{
1019 memset(&init->u, 0, sizeof init->u);
1020 switch (p2p_type) {
1021 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1022 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1023 init->u.write.stag_sink = cpu_to_be32(1);
1024 init->u.write.to_sink = cpu_to_be64(1);
1025 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1026 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1027 sizeof(struct fw_ri_immd),
1028 16);
1029 break;
1030 case FW_RI_INIT_P2PTYPE_READ_REQ:
1031 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1032 init->u.read.stag_src = cpu_to_be32(1);
1033 init->u.read.to_src_lo = cpu_to_be32(1);
1034 init->u.read.stag_sink = cpu_to_be32(1);
1035 init->u.read.to_sink_lo = cpu_to_be32(1);
1036 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1037 break;
1038 }
1039}
1040
1041static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1042{
1043 struct fw_ri_wr *wqe;
1044 int ret;
cfdda9d7
SW		 1045 struct sk_buff *skb;
1046
1047 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1048 qhp->ep->hwtid);
1049
d3c814e8 1050 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1051 if (!skb)
1052 return -ENOMEM;
1053 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1054
1055 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1056 memset(wqe, 0, sizeof *wqe);
1057 wqe->op_compl = cpu_to_be32(
1058 FW_WR_OP(FW_RI_INIT_WR) |
1059 FW_WR_COMPL(1));
1060 wqe->flowid_len16 = cpu_to_be32(
1061 FW_WR_FLOWID(qhp->ep->hwtid) |
1062 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1063
2f5b48c3 1064 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
cfdda9d7
SW		 1065
1066 wqe->u.init.type = FW_RI_TYPE_INIT;
1067 wqe->u.init.mpareqbit_p2ptype =
1068 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1069 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1070 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1071 if (qhp->attr.mpa_attr.recv_marker_enabled)
1072 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1073 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1074 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1075 if (qhp->attr.mpa_attr.crc_enabled)
1076 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1077
1078 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1079 FW_RI_QP_RDMA_WRITE_ENABLE |
1080 FW_RI_QP_BIND_ENABLE;
1081 if (!qhp->ibqp.uobject)
1082 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1083 FW_RI_QP_STAG0_ENABLE;
1084 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1085 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1086 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1087 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1088 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1089 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1090 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1091 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1092 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1093 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1094 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1095 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1096 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1097 rhp->rdev.lldi.vr->rq.start);
1098 if (qhp->attr.mpa_attr.initiator)
1099 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1100
cfdda9d7
SW		 1101 ret = c4iw_ofld_send(&rhp->rdev, skb);
1102 if (ret)
1103 goto out;
1104
2f5b48c3
SW		 1105 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1106 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1107out:
1108 PDBG("%s ret %d\n", __func__, ret);
1109 return ret;
1110}
1111
1112int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1113 enum c4iw_qp_attr_mask mask,
1114 struct c4iw_qp_attributes *attrs,
1115 int internal)
1116{
1117 int ret = 0;
1118 struct c4iw_qp_attributes newattr = qhp->attr;
cfdda9d7
SW		 1119 int disconnect = 0;
1120 int terminate = 0;
1121 int abort = 0;
1122 int free = 0;
1123 struct c4iw_ep *ep = NULL;
1124
1125 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1126 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1127 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1128
2f5b48c3 1129 mutex_lock(&qhp->mutex);
cfdda9d7
SW		 1130
1131 /* Process attr changes if in IDLE */
1132 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1133 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1134 ret = -EIO;
1135 goto out;
1136 }
1137 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1138 newattr.enable_rdma_read = attrs->enable_rdma_read;
1139 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1140 newattr.enable_rdma_write = attrs->enable_rdma_write;
1141 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1142 newattr.enable_bind = attrs->enable_bind;
1143 if (mask & C4IW_QP_ATTR_MAX_ORD) {
be4c9bad 1144 if (attrs->max_ord > c4iw_max_read_depth) {
cfdda9d7
SW		 1145 ret = -EINVAL;
1146 goto out;
1147 }
1148 newattr.max_ord = attrs->max_ord;
1149 }
1150 if (mask & C4IW_QP_ATTR_MAX_IRD) {
be4c9bad 1151 if (attrs->max_ird > c4iw_max_read_depth) {
cfdda9d7
SW		 1152 ret = -EINVAL;
1153 goto out;
1154 }
1155 newattr.max_ird = attrs->max_ird;
1156 }
1157 qhp->attr = newattr;
1158 }
1159
1160 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1161 goto out;
1162 if (qhp->attr.state == attrs->next_state)
1163 goto out;
1164
1165 switch (qhp->attr.state) {
1166 case C4IW_QP_STATE_IDLE:
1167 switch (attrs->next_state) {
1168 case C4IW_QP_STATE_RTS:
1169 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1170 ret = -EINVAL;
1171 goto out;
1172 }
1173 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1174 ret = -EINVAL;
1175 goto out;
1176 }
1177 qhp->attr.mpa_attr = attrs->mpa_attr;
1178 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1179 qhp->ep = qhp->attr.llp_stream_handle;
2f5b48c3 1180 set_state(qhp, C4IW_QP_STATE_RTS);
cfdda9d7
SW		 1181
1182 /*
1183 * Ref the endpoint here and deref when we
1184 * disassociate the endpoint from the QP. This
1185 * happens in CLOSING->IDLE transition or *->ERROR
1186 * transition.
1187 */
1188 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1189 ret = rdma_init(rhp, qhp);
cfdda9d7
SW		 1190 if (ret)
1191 goto err;
1192 break;
1193 case C4IW_QP_STATE_ERROR:
2f5b48c3
SW		 1194 set_state(qhp, C4IW_QP_STATE_ERROR);
1195 flush_qp(qhp);
cfdda9d7
SW		 1196 break;
1197 default:
1198 ret = -EINVAL;
1199 goto out;
1200 }
1201 break;
1202 case C4IW_QP_STATE_RTS:
1203 switch (attrs->next_state) {
1204 case C4IW_QP_STATE_CLOSING:
1205 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
2f5b48c3 1206 set_state(qhp, C4IW_QP_STATE_CLOSING);
73d6fcad 1207 ep = qhp->ep;
cfdda9d7
SW		 1208 if (!internal) {
1209 abort = 0;
1210 disconnect = 1;
2f5b48c3 1211 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1212 }
73d6fcad 1213 ret = rdma_fini(rhp, qhp, ep);
8da7e7a5 1214 if (ret)
cfdda9d7 1215 goto err;
cfdda9d7
SW		 1216 break;
1217 case C4IW_QP_STATE_TERMINATE:
2f5b48c3 1218 set_state(qhp, C4IW_QP_STATE_TERMINATE);
cfdda9d7
SW		 1219 if (qhp->ibqp.uobject)
1220 t4_set_wq_in_error(&qhp->wq);
be4c9bad 1221 ep = qhp->ep;
0e42c1f4
SW		 1222 if (!internal)
1223 terminate = 1;
be4c9bad 1224 disconnect = 1;
2f5b48c3 1225 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1226 break;
1227 case C4IW_QP_STATE_ERROR:
2f5b48c3 1228 set_state(qhp, C4IW_QP_STATE_ERROR);
cfdda9d7
SW		 1229 if (!internal) {
1230 abort = 1;
1231 disconnect = 1;
1232 ep = qhp->ep;
2f5b48c3 1233 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1234 }
1235 goto err;
1236 break;
1237 default:
1238 ret = -EINVAL;
1239 goto out;
1240 }
1241 break;
1242 case C4IW_QP_STATE_CLOSING:
1243 if (!internal) {
1244 ret = -EINVAL;
1245 goto out;
1246 }
1247 switch (attrs->next_state) {
1248 case C4IW_QP_STATE_IDLE:
2f5b48c3
SW		 1249 flush_qp(qhp);
1250 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1251 qhp->attr.llp_stream_handle = NULL;
1252 c4iw_put_ep(&qhp->ep->com);
1253 qhp->ep = NULL;
1254 wake_up(&qhp->wait);
1255 break;
1256 case C4IW_QP_STATE_ERROR:
1257 goto err;
1258 default:
1259 ret = -EINVAL;
1260 goto err;
1261 }
1262 break;
1263 case C4IW_QP_STATE_ERROR:
1264 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1265 ret = -EINVAL;
1266 goto out;
1267 }
1268 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1269 ret = -EINVAL;
1270 goto out;
1271 }
2f5b48c3 1272 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1273 break;
1274 case C4IW_QP_STATE_TERMINATE:
1275 if (!internal) {
1276 ret = -EINVAL;
1277 goto out;
1278 }
1279 goto err;
1280 break;
1281 default:
1282 printk(KERN_ERR "%s in a bad state %d\n",
1283 __func__, qhp->attr.state);
1284 ret = -EINVAL;
1285 goto err;
1286 break;
1287 }
1288 goto out;
1289err:
1290 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1291 qhp->wq.sq.qid);
1292
1293 /* disassociate the LLP connection */
1294 qhp->attr.llp_stream_handle = NULL;
af93fb5d
SW		 1295 if (!ep)
1296 ep = qhp->ep;
cfdda9d7 1297 qhp->ep = NULL;
2f5b48c3 1298 set_state(qhp, C4IW_QP_STATE_ERROR);
cfdda9d7
SW		 1299 free = 1;
1300 wake_up(&qhp->wait);
1301 BUG_ON(!ep);
2f5b48c3 1302 flush_qp(qhp);
cfdda9d7 1303out:
2f5b48c3 1304 mutex_unlock(&qhp->mutex);
cfdda9d7
SW		 1305
1306 if (terminate)
be4c9bad 1307 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
cfdda9d7
SW		 1308
1309 /*
1310 * If disconnect is 1, then we need to initiate a disconnect
1311 * on the EP. This can be a normal close (RTS->CLOSING) or
1312 * an abnormal close (RTS/CLOSING->ERROR).
1313 */
1314 if (disconnect) {
be4c9bad
RD		 1315 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1316 GFP_KERNEL);
cfdda9d7
SW		 1317 c4iw_put_ep(&ep->com);
1318 }
1319
1320 /*
1321 * If free is 1, then we've disassociated the EP from the QP
1322 * and we need to dereference the EP.
1323 */
1324 if (free)
1325 c4iw_put_ep(&ep->com);
cfdda9d7
SW		 1326 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1327 return ret;
1328}
1329
1330int c4iw_destroy_qp(struct ib_qp *ib_qp)
1331{
1332 struct c4iw_dev *rhp;
1333 struct c4iw_qp *qhp;
1334 struct c4iw_qp_attributes attrs;
1335 struct c4iw_ucontext *ucontext;
1336
1337 qhp = to_c4iw_qp(ib_qp);
1338 rhp = qhp->rhp;
1339
1340 attrs.next_state = C4IW_QP_STATE_ERROR;
1341 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1342 wait_event(qhp->wait, !qhp->ep);
1343
1344 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
cfdda9d7
SW		 1345 atomic_dec(&qhp->refcnt);
1346 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1347
1348 ucontext = ib_qp->uobject ?
1349 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1350 destroy_qp(&rhp->rdev, &qhp->wq,
1351 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1352
1353 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1354 kfree(qhp);
1355 return 0;
1356}
1357
1358struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1359 struct ib_udata *udata)
1360{
1361 struct c4iw_dev *rhp;
1362 struct c4iw_qp *qhp;
1363 struct c4iw_pd *php;
1364 struct c4iw_cq *schp;
1365 struct c4iw_cq *rchp;
1366 struct c4iw_create_qp_resp uresp;
1367 int sqsize, rqsize;
1368 struct c4iw_ucontext *ucontext;
1369 int ret;
c6d7b267 1370 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
cfdda9d7
SW		 1371
1372 PDBG("%s ib_pd %p\n", __func__, pd);
1373
1374 if (attrs->qp_type != IB_QPT_RC)
1375 return ERR_PTR(-EINVAL);
1376
1377 php = to_c4iw_pd(pd);
1378 rhp = php->rhp;
1379 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1380 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1381 if (!schp || !rchp)
1382 return ERR_PTR(-EINVAL);
1383
1384 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1385 return ERR_PTR(-EINVAL);
1386
1387 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1388 if (rqsize > T4_MAX_RQ_SIZE)
1389 return ERR_PTR(-E2BIG);
1390
1391 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1392 if (sqsize > T4_MAX_SQ_SIZE)
1393 return ERR_PTR(-E2BIG);
1394
1395 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1396
1397
1398 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1399 if (!qhp)
1400 return ERR_PTR(-ENOMEM);
1401 qhp->wq.sq.size = sqsize;
1402 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1403 qhp->wq.rq.size = rqsize;
1404 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1405
1406 if (ucontext) {
1407 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1408 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1409 }
1410
1411 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1412 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1413
1414 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1415 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1416 if (ret)
1417 goto err1;
1418
1419 attrs->cap.max_recv_wr = rqsize - 1;
1420 attrs->cap.max_send_wr = sqsize - 1;
1421 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1422
1423 qhp->rhp = rhp;
1424 qhp->attr.pd = php->pdid;
1425 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1426 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1427 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1428 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1429 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1430 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1431 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1432 qhp->attr.state = C4IW_QP_STATE_IDLE;
1433 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1434 qhp->attr.enable_rdma_read = 1;
1435 qhp->attr.enable_rdma_write = 1;
1436 qhp->attr.enable_bind = 1;
1437 qhp->attr.max_ord = 1;
1438 qhp->attr.max_ird = 1;
1439 spin_lock_init(&qhp->lock);
2f5b48c3 1440 mutex_init(&qhp->mutex);
cfdda9d7
SW		 1441 init_waitqueue_head(&qhp->wait);
1442 atomic_set(&qhp->refcnt, 1);
1443
1444 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1445 if (ret)
1446 goto err2;
1447
cfdda9d7
SW		 1448 if (udata) {
1449 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1450 if (!mm1) {
1451 ret = -ENOMEM;
30a6a62f 1452 goto err3;
cfdda9d7
SW		 1453 }
1454 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1455 if (!mm2) {
1456 ret = -ENOMEM;
30a6a62f 1457 goto err4;
cfdda9d7
SW		 1458 }
1459 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1460 if (!mm3) {
1461 ret = -ENOMEM;
30a6a62f 1462 goto err5;
cfdda9d7
SW		 1463 }
1464 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1465 if (!mm4) {
1466 ret = -ENOMEM;
30a6a62f 1467 goto err6;
cfdda9d7 1468 }
c6d7b267
SW		 1469 if (t4_sq_onchip(&qhp->wq.sq)) {
1470 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1471 if (!mm5) {
1472 ret = -ENOMEM;
1473 goto err7;
1474 }
1475 uresp.flags = C4IW_QPF_ONCHIP;
1476 } else
1477 uresp.flags = 0;
cfdda9d7
SW		 1478 uresp.qid_mask = rhp->rdev.qpmask;
1479 uresp.sqid = qhp->wq.sq.qid;
1480 uresp.sq_size = qhp->wq.sq.size;
1481 uresp.sq_memsize = qhp->wq.sq.memsize;
1482 uresp.rqid = qhp->wq.rq.qid;
1483 uresp.rq_size = qhp->wq.rq.size;
1484 uresp.rq_memsize = qhp->wq.rq.memsize;
1485 spin_lock(&ucontext->mmap_lock);
c6d7b267
SW		 1486 if (mm5) {
1487 uresp.ma_sync_key = ucontext->key;
1488 ucontext->key += PAGE_SIZE;
1489 }
cfdda9d7
SW		 1490 uresp.sq_key = ucontext->key;
1491 ucontext->key += PAGE_SIZE;
1492 uresp.rq_key = ucontext->key;
1493 ucontext->key += PAGE_SIZE;
1494 uresp.sq_db_gts_key = ucontext->key;
1495 ucontext->key += PAGE_SIZE;
1496 uresp.rq_db_gts_key = ucontext->key;
1497 ucontext->key += PAGE_SIZE;
1498 spin_unlock(&ucontext->mmap_lock);
1499 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1500 if (ret)
c6d7b267 1501 goto err8;
cfdda9d7 1502 mm1->key = uresp.sq_key;
c6d7b267 1503 mm1->addr = qhp->wq.sq.phys_addr;
cfdda9d7
SW		 1504 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1505 insert_mmap(ucontext, mm1);
1506 mm2->key = uresp.rq_key;
1507 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1508 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1509 insert_mmap(ucontext, mm2);
1510 mm3->key = uresp.sq_db_gts_key;
1511 mm3->addr = qhp->wq.sq.udb;
1512 mm3->len = PAGE_SIZE;
1513 insert_mmap(ucontext, mm3);
1514 mm4->key = uresp.rq_db_gts_key;
1515 mm4->addr = qhp->wq.rq.udb;
1516 mm4->len = PAGE_SIZE;
1517 insert_mmap(ucontext, mm4);
c6d7b267
SW		 1518 if (mm5) {
1519 mm5->key = uresp.ma_sync_key;
1520 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1521 + A_PCIE_MA_SYNC) & PAGE_MASK;
1522 mm5->len = PAGE_SIZE;
1523 insert_mmap(ucontext, mm5);
1524 }
cfdda9d7
SW		 1525 }
1526 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1527 init_timer(&(qhp->timer));
1528 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1529 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1530 qhp->wq.sq.qid);
1531 return &qhp->ibqp;
c6d7b267
SW		 1532err8:
1533 kfree(mm5);
cfdda9d7 1534err7:
30a6a62f 1535 kfree(mm4);
cfdda9d7 1536err6:
30a6a62f 1537 kfree(mm3);
cfdda9d7 1538err5:
30a6a62f 1539 kfree(mm2);
cfdda9d7 1540err4:
30a6a62f 1541 kfree(mm1);
cfdda9d7
SW		 1542err3:
1543 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1544err2:
1545 destroy_qp(&rhp->rdev, &qhp->wq,
1546 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1547err1:
1548 kfree(qhp);
1549 return ERR_PTR(ret);
1550}
1551
1552int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1553 int attr_mask, struct ib_udata *udata)
1554{
1555 struct c4iw_dev *rhp;
1556 struct c4iw_qp *qhp;
1557 enum c4iw_qp_attr_mask mask = 0;
1558 struct c4iw_qp_attributes attrs;
1559
1560 PDBG("%s ib_qp %p\n", __func__, ibqp);
1561
1562 /* iwarp does not support the RTR state */
1563 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1564 attr_mask &= ~IB_QP_STATE;
1565
1566 /* Make sure we still have something left to do */
1567 if (!attr_mask)
1568 return 0;
1569
1570 memset(&attrs, 0, sizeof attrs);
1571 qhp = to_c4iw_qp(ibqp);
1572 rhp = qhp->rhp;
1573
1574 attrs.next_state = c4iw_convert_state(attr->qp_state);
1575 attrs.enable_rdma_read = (attr->qp_access_flags &
1576 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1577 attrs.enable_rdma_write = (attr->qp_access_flags &
1578 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1579 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1580
1581
1582 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1583 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1584 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1585 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1586 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1587
1588 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1589}
1590
1591struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1592{
1593 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1594 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1595}
Linux 6.x block layer and io_uring tree(s)