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iw_cxgb4: log detailed warnings for negative advice
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / qp.c
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
e4dd23d7
PG		 32
33#include <linux/module.h>
34
cfdda9d7
SW		 35#include "iw_cxgb4.h"
36
2c974781
VP		 37static int db_delay_usecs = 1;
38module_param(db_delay_usecs, int, 0644);
39MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
40
a9c77198 41static int ocqp_support = 1;
c6d7b267 42module_param(ocqp_support, int, 0644);
a9c77198 43MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
c6d7b267 44
3cbdb928 45int db_fc_threshold = 1000;
422eea0a 46module_param(db_fc_threshold, int, 0644);
3cbdb928
VP		 47MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
50
51int db_coalescing_threshold;
52module_param(db_coalescing_threshold, int, 0644);
53MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
422eea0a 56
42b6a949
VP		 57static int max_fr_immd = T4_MAX_FR_IMMD;
58module_param(max_fr_immd, int, 0644);
59MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
60
4c2c5763
HS		 61static int alloc_ird(struct c4iw_dev *dev, u32 ird)
62{
63 int ret = 0;
64
65 spin_lock_irq(&dev->lock);
66 if (ird <= dev->avail_ird)
67 dev->avail_ird -= ird;
68 else
69 ret = -ENOMEM;
70 spin_unlock_irq(&dev->lock);
71
72 if (ret)
73 dev_warn(&dev->rdev.lldi.pdev->dev,
74 "device IRD resources exhausted\n");
75
76 return ret;
77}
78
79static void free_ird(struct c4iw_dev *dev, int ird)
80{
81 spin_lock_irq(&dev->lock);
82 dev->avail_ird += ird;
83 spin_unlock_irq(&dev->lock);
84}
85
2f5b48c3
SW		 86static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
87{
88 unsigned long flag;
89 spin_lock_irqsave(&qhp->lock, flag);
90 qhp->attr.state = state;
91 spin_unlock_irqrestore(&qhp->lock, flag);
92}
93
c6d7b267
SW		 94static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
95{
96 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
97}
98
99static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
100{
101 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
102 pci_unmap_addr(sq, mapping));
103}
104
105static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
106{
107 if (t4_sq_onchip(sq))
108 dealloc_oc_sq(rdev, sq);
109 else
110 dealloc_host_sq(rdev, sq);
111}
112
113static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
114{
f079af7a 115 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
c6d7b267
SW		 116 return -ENOSYS;
117 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
118 if (!sq->dma_addr)
119 return -ENOMEM;
120 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
121 rdev->lldi.vr->ocq.start;
122 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
123 rdev->lldi.vr->ocq.start);
124 sq->flags |= T4_SQ_ONCHIP;
125 return 0;
126}
127
128static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
129{
130 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
131 &(sq->dma_addr), GFP_KERNEL);
132 if (!sq->queue)
133 return -ENOMEM;
134 sq->phys_addr = virt_to_phys(sq->queue);
135 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
136 return 0;
137}
138
5b0c2759
TLSC		 139static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
140{
141 int ret = -ENOSYS;
142 if (user)
143 ret = alloc_oc_sq(rdev, sq);
144 if (ret)
145 ret = alloc_host_sq(rdev, sq);
146 return ret;
147}
148
cfdda9d7
SW		 149static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
150 struct c4iw_dev_ucontext *uctx)
151{
152 /*
153 * uP clears EQ contexts when the connection exits rdma mode,
154 * so no need to post a RESET WR for these EQs.
155 */
156 dma_free_coherent(&(rdev->lldi.pdev->dev),
157 wq->rq.memsize, wq->rq.queue,
f38926aa 158 dma_unmap_addr(&wq->rq, mapping));
c6d7b267 159 dealloc_sq(rdev, &wq->sq);
cfdda9d7
SW		 160 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
161 kfree(wq->rq.sw_rq);
162 kfree(wq->sq.sw_sq);
163 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
164 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
165 return 0;
166}
167
168static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
169 struct t4_cq *rcq, struct t4_cq *scq,
170 struct c4iw_dev_ucontext *uctx)
171{
172 int user = (uctx != &rdev->uctx);
173 struct fw_ri_res_wr *res_wr;
174 struct fw_ri_res *res;
175 int wr_len;
176 struct c4iw_wr_wait wr_wait;
177 struct sk_buff *skb;
9919d5bd 178 int ret = 0;
cfdda9d7
SW		 179 int eqsize;
180
181 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
182 if (!wq->sq.qid)
183 return -ENOMEM;
184
185 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
c079c287
EG		 186 if (!wq->rq.qid) {
187 ret = -ENOMEM;
188 goto free_sq_qid;
189 }
cfdda9d7
SW		 190
191 if (!user) {
192 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
193 GFP_KERNEL);
c079c287
EG		 194 if (!wq->sq.sw_sq) {
195 ret = -ENOMEM;
196 goto free_rq_qid;
197 }
cfdda9d7
SW		 198
199 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
200 GFP_KERNEL);
c079c287
EG		 201 if (!wq->rq.sw_rq) {
202 ret = -ENOMEM;
203 goto free_sw_sq;
204 }
cfdda9d7
SW		 205 }
206
207 /*
208 * RQT must be a power of 2.
209 */
210 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
211 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
c079c287
EG		 212 if (!wq->rq.rqt_hwaddr) {
213 ret = -ENOMEM;
214 goto free_sw_rq;
215 }
cfdda9d7 216
5b0c2759
TLSC		 217 ret = alloc_sq(rdev, &wq->sq, user);
218 if (ret)
219 goto free_hwaddr;
cfdda9d7 220 memset(wq->sq.queue, 0, wq->sq.memsize);
f38926aa 221 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
cfdda9d7
SW		 222
223 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
224 wq->rq.memsize, &(wq->rq.dma_addr),
225 GFP_KERNEL);
55e57a78
WY		 226 if (!wq->rq.queue) {
227 ret = -ENOMEM;
c079c287 228 goto free_sq;
55e57a78 229 }
cfdda9d7
SW		 230 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
231 __func__, wq->sq.queue,
232 (unsigned long long)virt_to_phys(wq->sq.queue),
233 wq->rq.queue,
234 (unsigned long long)virt_to_phys(wq->rq.queue));
235 memset(wq->rq.queue, 0, wq->rq.memsize);
f38926aa 236 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
cfdda9d7
SW		 237
238 wq->db = rdev->lldi.db_reg;
239 wq->gts = rdev->lldi.gts_reg;
fa658a98
SW		 240 if (user || is_t5(rdev->lldi.adapter_type)) {
241 u32 off;
242
243 off = (wq->sq.qid << rdev->qpshift) & PAGE_MASK;
244 if (user) {
245 wq->sq.udb = (u64 __iomem *)(rdev->bar2_pa + off);
246 } else {
247 off += 128 * (wq->sq.qid & rdev->qpmask) + 8;
248 wq->sq.udb = (u64 __iomem *)(rdev->bar2_kva + off);
249 }
250 off = (wq->rq.qid << rdev->qpshift) & PAGE_MASK;
251 if (user) {
252 wq->rq.udb = (u64 __iomem *)(rdev->bar2_pa + off);
253 } else {
254 off += 128 * (wq->rq.qid & rdev->qpmask) + 8;
255 wq->rq.udb = (u64 __iomem *)(rdev->bar2_kva + off);
256 }
cfdda9d7
SW		 257 }
258 wq->rdev = rdev;
259 wq->rq.msn = 1;
260
261 /* build fw_ri_res_wr */
262 wr_len = sizeof *res_wr + 2 * sizeof *res;
263
d3c814e8 264 skb = alloc_skb(wr_len, GFP_KERNEL);
cfdda9d7
SW		 265 if (!skb) {
266 ret = -ENOMEM;
c079c287 267 goto free_dma;
cfdda9d7
SW		 268 }
269 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
270
271 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
272 memset(res_wr, 0, wr_len);
273 res_wr->op_nres = cpu_to_be32(
274 FW_WR_OP(FW_RI_RES_WR) |
275 V_FW_RI_RES_WR_NRES(2) |
276 FW_WR_COMPL(1));
277 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
c8e081a1 278 res_wr->cookie = (unsigned long) &wr_wait;
cfdda9d7
SW		 279 res = res_wr->res;
280 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
281 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
282
283 /*
284 * eqsize is the number of 64B entries plus the status page size.
285 */
04e10e21
HS		 286 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
287 rdev->hw_queue.t4_eq_status_entries;
cfdda9d7
SW		 288
289 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
290 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
291 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
292 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
85d215b0 293 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
cfdda9d7
SW		 294 V_FW_RI_RES_WR_IQID(scq->cqid));
295 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
296 V_FW_RI_RES_WR_DCAEN(0) |
297 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 298 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 299 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 300 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
301 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
302 V_FW_RI_RES_WR_EQSIZE(eqsize));
303 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
304 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
305 res++;
306 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
307 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
308
309 /*
310 * eqsize is the number of 64B entries plus the status page size.
311 */
04e10e21
HS		 312 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
313 rdev->hw_queue.t4_eq_status_entries;
cfdda9d7
SW		 314 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
315 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
316 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
317 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
318 V_FW_RI_RES_WR_IQID(rcq->cqid));
319 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
320 V_FW_RI_RES_WR_DCAEN(0) |
321 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 322 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 323 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 324 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
325 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
326 V_FW_RI_RES_WR_EQSIZE(eqsize));
327 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
328 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
329
330 c4iw_init_wr_wait(&wr_wait);
331
332 ret = c4iw_ofld_send(rdev, skb);
333 if (ret)
c079c287 334 goto free_dma;
aadc4df3 335 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
cfdda9d7 336 if (ret)
c079c287 337 goto free_dma;
cfdda9d7 338
fa658a98 339 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%lx rqudb 0x%lx\n",
cfdda9d7 340 __func__, wq->sq.qid, wq->rq.qid, wq->db,
fa658a98
SW		 341 (__force unsigned long) wq->sq.udb,
342 (__force unsigned long) wq->rq.udb);
cfdda9d7
SW		 343
344 return 0;
c079c287 345free_dma:
cfdda9d7
SW		 346 dma_free_coherent(&(rdev->lldi.pdev->dev),
347 wq->rq.memsize, wq->rq.queue,
f38926aa 348 dma_unmap_addr(&wq->rq, mapping));
c079c287 349free_sq:
c6d7b267 350 dealloc_sq(rdev, &wq->sq);
c079c287 351free_hwaddr:
cfdda9d7 352 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
c079c287 353free_sw_rq:
cfdda9d7 354 kfree(wq->rq.sw_rq);
c079c287 355free_sw_sq:
cfdda9d7 356 kfree(wq->sq.sw_sq);
c079c287 357free_rq_qid:
cfdda9d7 358 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
c079c287 359free_sq_qid:
cfdda9d7 360 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
c079c287 361 return ret;
cfdda9d7
SW		 362}
363
d37ac31d
SW		 364static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
365 struct ib_send_wr *wr, int max, u32 *plenp)
cfdda9d7 366{
d37ac31d
SW		 367 u8 *dstp, *srcp;
368 u32 plen = 0;
cfdda9d7 369 int i;
d37ac31d
SW		 370 int rem, len;
371
372 dstp = (u8 *)immdp->data;
373 for (i = 0; i < wr->num_sge; i++) {
374 if ((plen + wr->sg_list[i].length) > max)
375 return -EMSGSIZE;
376 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
377 plen += wr->sg_list[i].length;
378 rem = wr->sg_list[i].length;
379 while (rem) {
380 if (dstp == (u8 *)&sq->queue[sq->size])
381 dstp = (u8 *)sq->queue;
382 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
383 len = rem;
384 else
385 len = (u8 *)&sq->queue[sq->size] - dstp;
386 memcpy(dstp, srcp, len);
387 dstp += len;
388 srcp += len;
389 rem -= len;
390 }
391 }
13fecb83
SW		 392 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
393 if (len)
394 memset(dstp, 0, len);
d37ac31d
SW		 395 immdp->op = FW_RI_DATA_IMMD;
396 immdp->r1 = 0;
397 immdp->r2 = 0;
398 immdp->immdlen = cpu_to_be32(plen);
399 *plenp = plen;
400 return 0;
401}
402
403static int build_isgl(__be64 *queue_start, __be64 *queue_end,
404 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
405 int num_sge, u32 *plenp)
406
407{
408 int i;
409 u32 plen = 0;
410 __be64 *flitp = (__be64 *)isglp->sge;
411
412 for (i = 0; i < num_sge; i++) {
413 if ((plen + sg_list[i].length) < plen)
414 return -EMSGSIZE;
415 plen += sg_list[i].length;
416 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
417 sg_list[i].length);
418 if (++flitp == queue_end)
419 flitp = queue_start;
420 *flitp = cpu_to_be64(sg_list[i].addr);
421 if (++flitp == queue_end)
422 flitp = queue_start;
423 }
13fecb83 424 *flitp = (__force __be64)0;
d37ac31d
SW		 425 isglp->op = FW_RI_DATA_ISGL;
426 isglp->r1 = 0;
427 isglp->nsge = cpu_to_be16(num_sge);
428 isglp->r2 = 0;
429 if (plenp)
430 *plenp = plen;
431 return 0;
432}
433
434static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
435 struct ib_send_wr *wr, u8 *len16)
436{
cfdda9d7
SW		 437 u32 plen;
438 int size;
d37ac31d 439 int ret;
cfdda9d7
SW		 440
441 if (wr->num_sge > T4_MAX_SEND_SGE)
442 return -EINVAL;
443 switch (wr->opcode) {
444 case IB_WR_SEND:
445 if (wr->send_flags & IB_SEND_SOLICITED)
446 wqe->send.sendop_pkd = cpu_to_be32(
447 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
448 else
449 wqe->send.sendop_pkd = cpu_to_be32(
450 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
451 wqe->send.stag_inv = 0;
452 break;
453 case IB_WR_SEND_WITH_INV:
454 if (wr->send_flags & IB_SEND_SOLICITED)
455 wqe->send.sendop_pkd = cpu_to_be32(
456 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
457 else
458 wqe->send.sendop_pkd = cpu_to_be32(
459 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
460 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
461 break;
462
463 default:
464 return -EINVAL;
465 }
c3f98fa2
SW		 466 wqe->send.r3 = 0;
467 wqe->send.r4 = 0;
d37ac31d 468
cfdda9d7
SW		 469 plen = 0;
470 if (wr->num_sge) {
471 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 472 ret = build_immd(sq, wqe->send.u.immd_src, wr,
473 T4_MAX_SEND_INLINE, &plen);
474 if (ret)
475 return ret;
cfdda9d7
SW		 476 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
477 plen;
478 } else {
d37ac31d
SW		 479 ret = build_isgl((__be64 *)sq->queue,
480 (__be64 *)&sq->queue[sq->size],
481 wqe->send.u.isgl_src,
482 wr->sg_list, wr->num_sge, &plen);
483 if (ret)
484 return ret;
cfdda9d7
SW		 485 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
486 wr->num_sge * sizeof(struct fw_ri_sge);
487 }
488 } else {
489 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
490 wqe->send.u.immd_src[0].r1 = 0;
491 wqe->send.u.immd_src[0].r2 = 0;
492 wqe->send.u.immd_src[0].immdlen = 0;
493 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
d37ac31d 494 plen = 0;
cfdda9d7
SW		 495 }
496 *len16 = DIV_ROUND_UP(size, 16);
497 wqe->send.plen = cpu_to_be32(plen);
498 return 0;
499}
500
d37ac31d
SW		 501static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
502 struct ib_send_wr *wr, u8 *len16)
cfdda9d7 503{
cfdda9d7
SW		 504 u32 plen;
505 int size;
d37ac31d 506 int ret;
cfdda9d7 507
d37ac31d 508 if (wr->num_sge > T4_MAX_SEND_SGE)
cfdda9d7
SW		 509 return -EINVAL;
510 wqe->write.r2 = 0;
511 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
512 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
cfdda9d7
SW		 513 if (wr->num_sge) {
514 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 515 ret = build_immd(sq, wqe->write.u.immd_src, wr,
516 T4_MAX_WRITE_INLINE, &plen);
517 if (ret)
518 return ret;
cfdda9d7
SW		 519 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
520 plen;
521 } else {
d37ac31d
SW		 522 ret = build_isgl((__be64 *)sq->queue,
523 (__be64 *)&sq->queue[sq->size],
524 wqe->write.u.isgl_src,
525 wr->sg_list, wr->num_sge, &plen);
526 if (ret)
527 return ret;
cfdda9d7
SW		 528 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
529 wr->num_sge * sizeof(struct fw_ri_sge);
530 }
531 } else {
532 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
533 wqe->write.u.immd_src[0].r1 = 0;
534 wqe->write.u.immd_src[0].r2 = 0;
535 wqe->write.u.immd_src[0].immdlen = 0;
536 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
d37ac31d 537 plen = 0;
cfdda9d7
SW		 538 }
539 *len16 = DIV_ROUND_UP(size, 16);
540 wqe->write.plen = cpu_to_be32(plen);
541 return 0;
542}
543
544static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
545{
546 if (wr->num_sge > 1)
547 return -EINVAL;
548 if (wr->num_sge) {
549 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
550 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
551 >> 32));
552 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
553 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
554 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
555 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
556 >> 32));
557 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
558 } else {
559 wqe->read.stag_src = cpu_to_be32(2);
560 wqe->read.to_src_hi = 0;
561 wqe->read.to_src_lo = 0;
562 wqe->read.stag_sink = cpu_to_be32(2);
563 wqe->read.plen = 0;
564 wqe->read.to_sink_hi = 0;
565 wqe->read.to_sink_lo = 0;
566 }
567 wqe->read.r2 = 0;
568 wqe->read.r5 = 0;
569 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
570 return 0;
571}
572
573static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
574 struct ib_recv_wr *wr, u8 *len16)
575{
d37ac31d 576 int ret;
cfdda9d7 577
d37ac31d
SW		 578 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
579 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
580 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
581 if (ret)
582 return ret;
cfdda9d7
SW		 583 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
584 wr->num_sge * sizeof(struct fw_ri_sge), 16);
585 return 0;
586}
587
40dbf6ee 588static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
42b6a949 589 struct ib_send_wr *wr, u8 *len16, u8 t5dev)
cfdda9d7
SW		 590{
591
592 struct fw_ri_immd *imdp;
593 __be64 *p;
594 int i;
595 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
40dbf6ee 596 int rem;
cfdda9d7 597
a03d9f94
SW		 598 if (wr->wr.fast_reg.page_list_len >
599 t4_max_fr_depth(use_dsgl))
cfdda9d7
SW		 600 return -EINVAL;
601
602 wqe->fr.qpbinde_to_dcacpu = 0;
603 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
604 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
605 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
606 wqe->fr.len_hi = 0;
607 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
608 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
609 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
610 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
611 0xffffffff);
42b6a949
VP		 612
613 if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
614 struct c4iw_fr_page_list *c4pl =
615 to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
616 struct fw_ri_dsgl *sglp;
617
618 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
619 wr->wr.fast_reg.page_list->page_list[i] = (__force u64)
620 cpu_to_be64((u64)
621 wr->wr.fast_reg.page_list->page_list[i]);
622 }
623
624 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
625 sglp->op = FW_RI_DATA_DSGL;
626 sglp->r1 = 0;
627 sglp->nsge = cpu_to_be16(1);
628 sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
629 sglp->len0 = cpu_to_be32(pbllen);
630
631 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
632 } else {
633 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
634 imdp->op = FW_RI_DATA_IMMD;
635 imdp->r1 = 0;
636 imdp->r2 = 0;
637 imdp->immdlen = cpu_to_be32(pbllen);
638 p = (__be64 *)(imdp + 1);
639 rem = pbllen;
640 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
641 *p = cpu_to_be64(
642 (u64)wr->wr.fast_reg.page_list->page_list[i]);
643 rem -= sizeof(*p);
644 if (++p == (__be64 *)&sq->queue[sq->size])
645 p = (__be64 *)sq->queue;
646 }
647 BUG_ON(rem < 0);
648 while (rem) {
649 *p = 0;
650 rem -= sizeof(*p);
651 if (++p == (__be64 *)&sq->queue[sq->size])
652 p = (__be64 *)sq->queue;
653 }
654 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
655 + pbllen, 16);
cfdda9d7
SW		 656 }
657 return 0;
658}
659
660static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
661 u8 *len16)
662{
663 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
664 wqe->inv.r2 = 0;
665 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
666 return 0;
667}
668
669void c4iw_qp_add_ref(struct ib_qp *qp)
670{
671 PDBG("%s ib_qp %p\n", __func__, qp);
672 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
673}
674
675void c4iw_qp_rem_ref(struct ib_qp *qp)
676{
677 PDBG("%s ib_qp %p\n", __func__, qp);
678 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
679 wake_up(&(to_c4iw_qp(qp)->wait));
680}
681
05eb2389
SW		 682static void add_to_fc_list(struct list_head *head, struct list_head *entry)
683{
684 if (list_empty(entry))
685 list_add_tail(entry, head);
686}
687
688static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
689{
690 unsigned long flags;
691
692 spin_lock_irqsave(&qhp->rhp->lock, flags);
693 spin_lock(&qhp->lock);
fa658a98
SW		 694 if (qhp->rhp->db_state == NORMAL)
695 t4_ring_sq_db(&qhp->wq, inc,
696 is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL);
697 else {
05eb2389
SW		 698 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
699 qhp->wq.sq.wq_pidx_inc += inc;
700 }
701 spin_unlock(&qhp->lock);
702 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
703 return 0;
704}
705
706static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
707{
708 unsigned long flags;
709
710 spin_lock_irqsave(&qhp->rhp->lock, flags);
711 spin_lock(&qhp->lock);
fa658a98
SW		 712 if (qhp->rhp->db_state == NORMAL)
713 t4_ring_rq_db(&qhp->wq, inc,
714 is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL);
715 else {
05eb2389
SW		 716 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
717 qhp->wq.rq.wq_pidx_inc += inc;
718 }
719 spin_unlock(&qhp->lock);
720 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
721 return 0;
722}
723
cfdda9d7
SW		 724int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
725 struct ib_send_wr **bad_wr)
726{
727 int err = 0;
728 u8 len16 = 0;
729 enum fw_wr_opcodes fw_opcode = 0;
730 enum fw_ri_wr_flags fw_flags;
731 struct c4iw_qp *qhp;
fa658a98 732 union t4_wr *wqe = NULL;
cfdda9d7
SW		 733 u32 num_wrs;
734 struct t4_swsqe *swsqe;
735 unsigned long flag;
736 u16 idx = 0;
737
738 qhp = to_c4iw_qp(ibqp);
739 spin_lock_irqsave(&qhp->lock, flag);
740 if (t4_wq_in_error(&qhp->wq)) {
741 spin_unlock_irqrestore(&qhp->lock, flag);
742 return -EINVAL;
743 }
744 num_wrs = t4_sq_avail(&qhp->wq);
745 if (num_wrs == 0) {
746 spin_unlock_irqrestore(&qhp->lock, flag);
747 return -ENOMEM;
748 }
749 while (wr) {
750 if (num_wrs == 0) {
751 err = -ENOMEM;
752 *bad_wr = wr;
753 break;
754 }
d37ac31d
SW		 755 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
756 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
757
cfdda9d7
SW		 758 fw_flags = 0;
759 if (wr->send_flags & IB_SEND_SOLICITED)
760 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
ba32de9d 761 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
cfdda9d7
SW		 762 fw_flags |= FW_RI_COMPLETION_FLAG;
763 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
764 switch (wr->opcode) {
765 case IB_WR_SEND_WITH_INV:
766 case IB_WR_SEND:
767 if (wr->send_flags & IB_SEND_FENCE)
768 fw_flags |= FW_RI_READ_FENCE_FLAG;
769 fw_opcode = FW_RI_SEND_WR;
770 if (wr->opcode == IB_WR_SEND)
771 swsqe->opcode = FW_RI_SEND;
772 else
773 swsqe->opcode = FW_RI_SEND_WITH_INV;
d37ac31d 774 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 775 break;
776 case IB_WR_RDMA_WRITE:
777 fw_opcode = FW_RI_RDMA_WRITE_WR;
778 swsqe->opcode = FW_RI_RDMA_WRITE;
d37ac31d 779 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 780 break;
781 case IB_WR_RDMA_READ:
2f1fb507 782 case IB_WR_RDMA_READ_WITH_INV:
cfdda9d7
SW		 783 fw_opcode = FW_RI_RDMA_READ_WR;
784 swsqe->opcode = FW_RI_READ_REQ;
2f1fb507 785 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
410ade4c 786 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
2f1fb507
SW		 787 else
788 fw_flags = 0;
cfdda9d7
SW		 789 err = build_rdma_read(wqe, wr, &len16);
790 if (err)
791 break;
792 swsqe->read_len = wr->sg_list[0].length;
793 if (!qhp->wq.sq.oldest_read)
794 qhp->wq.sq.oldest_read = swsqe;
795 break;
796 case IB_WR_FAST_REG_MR:
797 fw_opcode = FW_RI_FR_NSMR_WR;
798 swsqe->opcode = FW_RI_FAST_REGISTER;
42b6a949
VP		 799 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16,
800 is_t5(
801 qhp->rhp->rdev.lldi.adapter_type) ?
802 1 : 0);
cfdda9d7
SW		 803 break;
804 case IB_WR_LOCAL_INV:
4ab1eb9c
SW		 805 if (wr->send_flags & IB_SEND_FENCE)
806 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
cfdda9d7
SW		 807 fw_opcode = FW_RI_INV_LSTAG_WR;
808 swsqe->opcode = FW_RI_LOCAL_INV;
809 err = build_inv_stag(wqe, wr, &len16);
810 break;
811 default:
812 PDBG("%s post of type=%d TBD!\n", __func__,
813 wr->opcode);
814 err = -EINVAL;
815 }
816 if (err) {
817 *bad_wr = wr;
818 break;
819 }
820 swsqe->idx = qhp->wq.sq.pidx;
821 swsqe->complete = 0;
ba32de9d
SW		 822 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
823 qhp->sq_sig_all;
1cf24dce 824 swsqe->flushed = 0;
cfdda9d7 825 swsqe->wr_id = wr->wr_id;
7730b4c7
HS		 826 if (c4iw_wr_log) {
827 swsqe->sge_ts = cxgb4_read_sge_timestamp(
828 qhp->rhp->rdev.lldi.ports[0]);
829 getnstimeofday(&swsqe->host_ts);
830 }
cfdda9d7
SW		 831
832 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
833
834 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
835 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
836 swsqe->opcode, swsqe->read_len);
837 wr = wr->next;
838 num_wrs--;
d37ac31d
SW		 839 t4_sq_produce(&qhp->wq, len16);
840 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7 841 }
05eb2389 842 if (!qhp->rhp->rdev.status_page->db_off) {
fa658a98
SW		 843 t4_ring_sq_db(&qhp->wq, idx,
844 is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe);
05eb2389
SW		 845 spin_unlock_irqrestore(&qhp->lock, flag);
846 } else {
847 spin_unlock_irqrestore(&qhp->lock, flag);
848 ring_kernel_sq_db(qhp, idx);
849 }
cfdda9d7
SW		 850 return err;
851}
852
853int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
854 struct ib_recv_wr **bad_wr)
855{
856 int err = 0;
857 struct c4iw_qp *qhp;
fa658a98 858 union t4_recv_wr *wqe = NULL;
cfdda9d7
SW		 859 u32 num_wrs;
860 u8 len16 = 0;
861 unsigned long flag;
862 u16 idx = 0;
863
864 qhp = to_c4iw_qp(ibqp);
865 spin_lock_irqsave(&qhp->lock, flag);
866 if (t4_wq_in_error(&qhp->wq)) {
867 spin_unlock_irqrestore(&qhp->lock, flag);
868 return -EINVAL;
869 }
870 num_wrs = t4_rq_avail(&qhp->wq);
871 if (num_wrs == 0) {
872 spin_unlock_irqrestore(&qhp->lock, flag);
873 return -ENOMEM;
874 }
875 while (wr) {
876 if (wr->num_sge > T4_MAX_RECV_SGE) {
877 err = -EINVAL;
878 *bad_wr = wr;
879 break;
880 }
d37ac31d
SW		 881 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
882 qhp->wq.rq.wq_pidx *
883 T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 884 if (num_wrs)
885 err = build_rdma_recv(qhp, wqe, wr, &len16);
886 else
887 err = -ENOMEM;
888 if (err) {
889 *bad_wr = wr;
890 break;
891 }
892
893 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
7730b4c7
HS		 894 if (c4iw_wr_log) {
895 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts =
896 cxgb4_read_sge_timestamp(
897 qhp->rhp->rdev.lldi.ports[0]);
898 getnstimeofday(
899 &qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_ts);
900 }
cfdda9d7
SW		 901
902 wqe->recv.opcode = FW_RI_RECV_WR;
903 wqe->recv.r1 = 0;
904 wqe->recv.wrid = qhp->wq.rq.pidx;
905 wqe->recv.r2[0] = 0;
906 wqe->recv.r2[1] = 0;
907 wqe->recv.r2[2] = 0;
908 wqe->recv.len16 = len16;
cfdda9d7
SW		 909 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
910 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
d37ac31d
SW		 911 t4_rq_produce(&qhp->wq, len16);
912 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 913 wr = wr->next;
914 num_wrs--;
cfdda9d7 915 }
05eb2389 916 if (!qhp->rhp->rdev.status_page->db_off) {
fa658a98
SW		 917 t4_ring_rq_db(&qhp->wq, idx,
918 is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe);
05eb2389
SW		 919 spin_unlock_irqrestore(&qhp->lock, flag);
920 } else {
921 spin_unlock_irqrestore(&qhp->lock, flag);
922 ring_kernel_rq_db(qhp, idx);
923 }
cfdda9d7
SW		 924 return err;
925}
926
927int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
928{
929 return -ENOSYS;
930}
931
932static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
933 u8 *ecode)
934{
935 int status;
936 int tagged;
937 int opcode;
938 int rqtype;
939 int send_inv;
940
941 if (!err_cqe) {
942 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
943 *ecode = 0;
944 return;
945 }
946
947 status = CQE_STATUS(err_cqe);
948 opcode = CQE_OPCODE(err_cqe);
949 rqtype = RQ_TYPE(err_cqe);
950 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
951 (opcode == FW_RI_SEND_WITH_SE_INV);
952 tagged = (opcode == FW_RI_RDMA_WRITE) ||
953 (rqtype && (opcode == FW_RI_READ_RESP));
954
955 switch (status) {
956 case T4_ERR_STAG:
957 if (send_inv) {
958 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
959 *ecode = RDMAP_CANT_INV_STAG;
960 } else {
961 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
962 *ecode = RDMAP_INV_STAG;
963 }
964 break;
965 case T4_ERR_PDID:
966 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
967 if ((opcode == FW_RI_SEND_WITH_INV) ||
968 (opcode == FW_RI_SEND_WITH_SE_INV))
969 *ecode = RDMAP_CANT_INV_STAG;
970 else
971 *ecode = RDMAP_STAG_NOT_ASSOC;
972 break;
973 case T4_ERR_QPID:
974 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
975 *ecode = RDMAP_STAG_NOT_ASSOC;
976 break;
977 case T4_ERR_ACCESS:
978 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
979 *ecode = RDMAP_ACC_VIOL;
980 break;
981 case T4_ERR_WRAP:
982 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
983 *ecode = RDMAP_TO_WRAP;
984 break;
985 case T4_ERR_BOUND:
986 if (tagged) {
987 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
988 *ecode = DDPT_BASE_BOUNDS;
989 } else {
990 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
991 *ecode = RDMAP_BASE_BOUNDS;
992 }
993 break;
994 case T4_ERR_INVALIDATE_SHARED_MR:
995 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
996 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
997 *ecode = RDMAP_CANT_INV_STAG;
998 break;
999 case T4_ERR_ECC:
1000 case T4_ERR_ECC_PSTAG:
1001 case T4_ERR_INTERNAL_ERR:
1002 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
1003 *ecode = 0;
1004 break;
1005 case T4_ERR_OUT_OF_RQE:
1006 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1007 *ecode = DDPU_INV_MSN_NOBUF;
1008 break;
1009 case T4_ERR_PBL_ADDR_BOUND:
1010 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1011 *ecode = DDPT_BASE_BOUNDS;
1012 break;
1013 case T4_ERR_CRC:
1014 *layer_type = LAYER_MPA|DDP_LLP;
1015 *ecode = MPA_CRC_ERR;
1016 break;
1017 case T4_ERR_MARKER:
1018 *layer_type = LAYER_MPA|DDP_LLP;
1019 *ecode = MPA_MARKER_ERR;
1020 break;
1021 case T4_ERR_PDU_LEN_ERR:
1022 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1023 *ecode = DDPU_MSG_TOOBIG;
1024 break;
1025 case T4_ERR_DDP_VERSION:
1026 if (tagged) {
1027 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1028 *ecode = DDPT_INV_VERS;
1029 } else {
1030 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1031 *ecode = DDPU_INV_VERS;
1032 }
1033 break;
1034 case T4_ERR_RDMA_VERSION:
1035 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1036 *ecode = RDMAP_INV_VERS;
1037 break;
1038 case T4_ERR_OPCODE:
1039 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1040 *ecode = RDMAP_INV_OPCODE;
1041 break;
1042 case T4_ERR_DDP_QUEUE_NUM:
1043 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1044 *ecode = DDPU_INV_QN;
1045 break;
1046 case T4_ERR_MSN:
1047 case T4_ERR_MSN_GAP:
1048 case T4_ERR_MSN_RANGE:
1049 case T4_ERR_IRD_OVERFLOW:
1050 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1051 *ecode = DDPU_INV_MSN_RANGE;
1052 break;
1053 case T4_ERR_TBIT:
1054 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1055 *ecode = 0;
1056 break;
1057 case T4_ERR_MO:
1058 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1059 *ecode = DDPU_INV_MO;
1060 break;
1061 default:
1062 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1063 *ecode = 0;
1064 break;
1065 }
1066}
1067
be4c9bad
RD		 1068static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1069 gfp_t gfp)
cfdda9d7
SW		 1070{
1071 struct fw_ri_wr *wqe;
1072 struct sk_buff *skb;
1073 struct terminate_message *term;
1074
1075 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1076 qhp->ep->hwtid);
1077
be4c9bad 1078 skb = alloc_skb(sizeof *wqe, gfp);
cfdda9d7 1079 if (!skb)
be4c9bad 1080 return;
cfdda9d7
SW		 1081 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1082
1083 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1084 memset(wqe, 0, sizeof *wqe);
1085 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
1086 wqe->flowid_len16 = cpu_to_be32(
1087 FW_WR_FLOWID(qhp->ep->hwtid) |
1088 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1089
1090 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1091 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1092 term = (struct terminate_message *)wqe->u.terminate.termmsg;
d2fe99e8
KS		 1093 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1094 term->layer_etype = qhp->attr.layer_etype;
1095 term->ecode = qhp->attr.ecode;
1096 } else
1097 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
be4c9bad 1098 c4iw_ofld_send(&qhp->rhp->rdev, skb);
cfdda9d7
SW		 1099}
1100
1101/*
1102 * Assumes qhp lock is held.
1103 */
1104static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
2f5b48c3 1105 struct c4iw_cq *schp)
cfdda9d7
SW		 1106{
1107 int count;
1108 int flushed;
2f5b48c3 1109 unsigned long flag;
cfdda9d7
SW		 1110
1111 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
cfdda9d7 1112
732bee7a 1113 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 1114 spin_lock_irqsave(&rchp->lock, flag);
cfdda9d7 1115 spin_lock(&qhp->lock);
1cf24dce
SW		 1116
1117 if (qhp->wq.flushed) {
1118 spin_unlock(&qhp->lock);
1119 spin_unlock_irqrestore(&rchp->lock, flag);
1120 return;
1121 }
1122 qhp->wq.flushed = 1;
1123
1124 c4iw_flush_hw_cq(rchp);
cfdda9d7
SW		 1125 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1126 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1127 spin_unlock(&qhp->lock);
2f5b48c3 1128 spin_unlock_irqrestore(&rchp->lock, flag);
581bbe2c
KS		 1129 if (flushed) {
1130 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
cfdda9d7 1131 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
581bbe2c
KS		 1132 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1133 }
cfdda9d7 1134
732bee7a 1135 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 1136 spin_lock_irqsave(&schp->lock, flag);
cfdda9d7 1137 spin_lock(&qhp->lock);
1cf24dce
SW		 1138 if (schp != rchp)
1139 c4iw_flush_hw_cq(schp);
1140 flushed = c4iw_flush_sq(qhp);
cfdda9d7 1141 spin_unlock(&qhp->lock);
2f5b48c3 1142 spin_unlock_irqrestore(&schp->lock, flag);
581bbe2c
KS		 1143 if (flushed) {
1144 spin_lock_irqsave(&schp->comp_handler_lock, flag);
cfdda9d7 1145 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
581bbe2c
KS		 1146 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1147 }
cfdda9d7
SW		 1148}
1149
2f5b48c3 1150static void flush_qp(struct c4iw_qp *qhp)
cfdda9d7
SW		 1151{
1152 struct c4iw_cq *rchp, *schp;
581bbe2c 1153 unsigned long flag;
cfdda9d7 1154
1cf24dce
SW		 1155 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1156 schp = to_c4iw_cq(qhp->ibqp.send_cq);
cfdda9d7 1157
1cf24dce 1158 t4_set_wq_in_error(&qhp->wq);
cfdda9d7 1159 if (qhp->ibqp.uobject) {
cfdda9d7 1160 t4_set_cq_in_error(&rchp->cq);
581bbe2c 1161 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
01e7da6b 1162 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
581bbe2c 1163 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
01e7da6b 1164 if (schp != rchp) {
cfdda9d7 1165 t4_set_cq_in_error(&schp->cq);
581bbe2c 1166 spin_lock_irqsave(&schp->comp_handler_lock, flag);
01e7da6b
KS		 1167 (*schp->ibcq.comp_handler)(&schp->ibcq,
1168 schp->ibcq.cq_context);
581bbe2c 1169 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
01e7da6b 1170 }
cfdda9d7
SW		 1171 return;
1172 }
2f5b48c3 1173 __flush_qp(qhp, rchp, schp);
cfdda9d7
SW		 1174}
1175
73d6fcad
SW		 1176static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1177 struct c4iw_ep *ep)
cfdda9d7
SW		 1178{
1179 struct fw_ri_wr *wqe;
1180 int ret;
cfdda9d7
SW		 1181 struct sk_buff *skb;
1182
1183 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
73d6fcad 1184 ep->hwtid);
cfdda9d7 1185
d3c814e8 1186 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1187 if (!skb)
1188 return -ENOMEM;
73d6fcad 1189 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
cfdda9d7
SW		 1190
1191 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1192 memset(wqe, 0, sizeof *wqe);
1193 wqe->op_compl = cpu_to_be32(
1194 FW_WR_OP(FW_RI_INIT_WR) |
1195 FW_WR_COMPL(1));
1196 wqe->flowid_len16 = cpu_to_be32(
73d6fcad 1197 FW_WR_FLOWID(ep->hwtid) |
cfdda9d7 1198 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
2f5b48c3 1199 wqe->cookie = (unsigned long) &ep->com.wr_wait;
cfdda9d7
SW		 1200
1201 wqe->u.fini.type = FW_RI_TYPE_FINI;
cfdda9d7
SW		 1202 ret = c4iw_ofld_send(&rhp->rdev, skb);
1203 if (ret)
1204 goto out;
1205
2f5b48c3 1206 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
aadc4df3 1207 qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1208out:
1209 PDBG("%s ret %d\n", __func__, ret);
1210 return ret;
1211}
1212
1213static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1214{
d2fe99e8 1215 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
cfdda9d7
SW		 1216 memset(&init->u, 0, sizeof init->u);
1217 switch (p2p_type) {
1218 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1219 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1220 init->u.write.stag_sink = cpu_to_be32(1);
1221 init->u.write.to_sink = cpu_to_be64(1);
1222 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1223 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1224 sizeof(struct fw_ri_immd),
1225 16);
1226 break;
1227 case FW_RI_INIT_P2PTYPE_READ_REQ:
1228 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1229 init->u.read.stag_src = cpu_to_be32(1);
1230 init->u.read.to_src_lo = cpu_to_be32(1);
1231 init->u.read.stag_sink = cpu_to_be32(1);
1232 init->u.read.to_sink_lo = cpu_to_be32(1);
1233 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1234 break;
1235 }
1236}
1237
1238static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1239{
1240 struct fw_ri_wr *wqe;
1241 int ret;
cfdda9d7
SW		 1242 struct sk_buff *skb;
1243
4c2c5763
HS		 1244 PDBG("%s qhp %p qid 0x%x tid %u ird %u ord %u\n", __func__, qhp,
1245 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord);
cfdda9d7 1246
d3c814e8 1247 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
4c2c5763
HS		 1248 if (!skb) {
1249 ret = -ENOMEM;
1250 goto out;
1251 }
1252 ret = alloc_ird(rhp, qhp->attr.max_ird);
1253 if (ret) {
1254 qhp->attr.max_ird = 0;
1255 kfree_skb(skb);
1256 goto out;
1257 }
cfdda9d7
SW		 1258 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1259
1260 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1261 memset(wqe, 0, sizeof *wqe);
1262 wqe->op_compl = cpu_to_be32(
1263 FW_WR_OP(FW_RI_INIT_WR) |
1264 FW_WR_COMPL(1));
1265 wqe->flowid_len16 = cpu_to_be32(
1266 FW_WR_FLOWID(qhp->ep->hwtid) |
1267 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1268
2f5b48c3 1269 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
cfdda9d7
SW		 1270
1271 wqe->u.init.type = FW_RI_TYPE_INIT;
1272 wqe->u.init.mpareqbit_p2ptype =
1273 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1274 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1275 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1276 if (qhp->attr.mpa_attr.recv_marker_enabled)
1277 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1278 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1279 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1280 if (qhp->attr.mpa_attr.crc_enabled)
1281 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1282
1283 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1284 FW_RI_QP_RDMA_WRITE_ENABLE |
1285 FW_RI_QP_BIND_ENABLE;
1286 if (!qhp->ibqp.uobject)
1287 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1288 FW_RI_QP_STAG0_ENABLE;
1289 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1290 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1291 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1292 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1293 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1294 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1295 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1296 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1297 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1298 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1299 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1300 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1301 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1302 rhp->rdev.lldi.vr->rq.start);
1303 if (qhp->attr.mpa_attr.initiator)
1304 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1305
cfdda9d7
SW		 1306 ret = c4iw_ofld_send(&rhp->rdev, skb);
1307 if (ret)
4c2c5763 1308 goto err1;
cfdda9d7 1309
2f5b48c3
SW		 1310 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1311 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
4c2c5763
HS		 1312 if (!ret)
1313 goto out;
1314err1:
1315 free_ird(rhp, qhp->attr.max_ird);
cfdda9d7
SW		 1316out:
1317 PDBG("%s ret %d\n", __func__, ret);
1318 return ret;
1319}
1320
1321int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1322 enum c4iw_qp_attr_mask mask,
1323 struct c4iw_qp_attributes *attrs,
1324 int internal)
1325{
1326 int ret = 0;
1327 struct c4iw_qp_attributes newattr = qhp->attr;
cfdda9d7
SW		 1328 int disconnect = 0;
1329 int terminate = 0;
1330 int abort = 0;
1331 int free = 0;
1332 struct c4iw_ep *ep = NULL;
1333
1334 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1335 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1336 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1337
2f5b48c3 1338 mutex_lock(&qhp->mutex);
cfdda9d7
SW		 1339
1340 /* Process attr changes if in IDLE */
1341 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1342 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1343 ret = -EIO;
1344 goto out;
1345 }
1346 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1347 newattr.enable_rdma_read = attrs->enable_rdma_read;
1348 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1349 newattr.enable_rdma_write = attrs->enable_rdma_write;
1350 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1351 newattr.enable_bind = attrs->enable_bind;
1352 if (mask & C4IW_QP_ATTR_MAX_ORD) {
be4c9bad 1353 if (attrs->max_ord > c4iw_max_read_depth) {
cfdda9d7
SW		 1354 ret = -EINVAL;
1355 goto out;
1356 }
1357 newattr.max_ord = attrs->max_ord;
1358 }
1359 if (mask & C4IW_QP_ATTR_MAX_IRD) {
4c2c5763 1360 if (attrs->max_ird > cur_max_read_depth(rhp)) {
cfdda9d7
SW		 1361 ret = -EINVAL;
1362 goto out;
1363 }
1364 newattr.max_ird = attrs->max_ird;
1365 }
1366 qhp->attr = newattr;
1367 }
1368
2c974781 1369 if (mask & C4IW_QP_ATTR_SQ_DB) {
05eb2389 1370 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
2c974781
VP		 1371 goto out;
1372 }
1373 if (mask & C4IW_QP_ATTR_RQ_DB) {
05eb2389 1374 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
2c974781
VP		 1375 goto out;
1376 }
1377
cfdda9d7
SW		 1378 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1379 goto out;
1380 if (qhp->attr.state == attrs->next_state)
1381 goto out;
1382
1383 switch (qhp->attr.state) {
1384 case C4IW_QP_STATE_IDLE:
1385 switch (attrs->next_state) {
1386 case C4IW_QP_STATE_RTS:
1387 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1388 ret = -EINVAL;
1389 goto out;
1390 }
1391 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1392 ret = -EINVAL;
1393 goto out;
1394 }
1395 qhp->attr.mpa_attr = attrs->mpa_attr;
1396 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1397 qhp->ep = qhp->attr.llp_stream_handle;
2f5b48c3 1398 set_state(qhp, C4IW_QP_STATE_RTS);
cfdda9d7
SW		 1399
1400 /*
1401 * Ref the endpoint here and deref when we
1402 * disassociate the endpoint from the QP. This
1403 * happens in CLOSING->IDLE transition or *->ERROR
1404 * transition.
1405 */
1406 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1407 ret = rdma_init(rhp, qhp);
cfdda9d7
SW		 1408 if (ret)
1409 goto err;
1410 break;
1411 case C4IW_QP_STATE_ERROR:
2f5b48c3
SW		 1412 set_state(qhp, C4IW_QP_STATE_ERROR);
1413 flush_qp(qhp);
cfdda9d7
SW		 1414 break;
1415 default:
1416 ret = -EINVAL;
1417 goto out;
1418 }
1419 break;
1420 case C4IW_QP_STATE_RTS:
1421 switch (attrs->next_state) {
1422 case C4IW_QP_STATE_CLOSING:
1423 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
b4e2901c 1424 t4_set_wq_in_error(&qhp->wq);
2f5b48c3 1425 set_state(qhp, C4IW_QP_STATE_CLOSING);
73d6fcad 1426 ep = qhp->ep;
cfdda9d7
SW		 1427 if (!internal) {
1428 abort = 0;
1429 disconnect = 1;
2f5b48c3 1430 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1431 }
73d6fcad 1432 ret = rdma_fini(rhp, qhp, ep);
8da7e7a5 1433 if (ret)
cfdda9d7 1434 goto err;
cfdda9d7
SW		 1435 break;
1436 case C4IW_QP_STATE_TERMINATE:
b4e2901c 1437 t4_set_wq_in_error(&qhp->wq);
2f5b48c3 1438 set_state(qhp, C4IW_QP_STATE_TERMINATE);
d2fe99e8
KS		 1439 qhp->attr.layer_etype = attrs->layer_etype;
1440 qhp->attr.ecode = attrs->ecode;
be4c9bad 1441 ep = qhp->ep;
cc18b939
SW		 1442 if (!internal) {
1443 c4iw_get_ep(&qhp->ep->com);
0e42c1f4 1444 terminate = 1;
cc18b939
SW		 1445 disconnect = 1;
1446 } else {
1447 terminate = qhp->attr.send_term;
09992579
SW		 1448 ret = rdma_fini(rhp, qhp, ep);
1449 if (ret)
1450 goto err;
1451 }
cfdda9d7
SW		 1452 break;
1453 case C4IW_QP_STATE_ERROR:
1cf24dce 1454 t4_set_wq_in_error(&qhp->wq);
b4e2901c 1455 set_state(qhp, C4IW_QP_STATE_ERROR);
cfdda9d7
SW		 1456 if (!internal) {
1457 abort = 1;
1458 disconnect = 1;
1459 ep = qhp->ep;
2f5b48c3 1460 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1461 }
1462 goto err;
1463 break;
1464 default:
1465 ret = -EINVAL;
1466 goto out;
1467 }
1468 break;
1469 case C4IW_QP_STATE_CLOSING:
1470 if (!internal) {
1471 ret = -EINVAL;
1472 goto out;
1473 }
1474 switch (attrs->next_state) {
1475 case C4IW_QP_STATE_IDLE:
2f5b48c3
SW		 1476 flush_qp(qhp);
1477 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1478 qhp->attr.llp_stream_handle = NULL;
1479 c4iw_put_ep(&qhp->ep->com);
1480 qhp->ep = NULL;
1481 wake_up(&qhp->wait);
1482 break;
1483 case C4IW_QP_STATE_ERROR:
1484 goto err;
1485 default:
1486 ret = -EINVAL;
1487 goto err;
1488 }
1489 break;
1490 case C4IW_QP_STATE_ERROR:
1491 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1492 ret = -EINVAL;
1493 goto out;
1494 }
1495 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1496 ret = -EINVAL;
1497 goto out;
1498 }
2f5b48c3 1499 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1500 break;
1501 case C4IW_QP_STATE_TERMINATE:
1502 if (!internal) {
1503 ret = -EINVAL;
1504 goto out;
1505 }
1506 goto err;
1507 break;
1508 default:
1509 printk(KERN_ERR "%s in a bad state %d\n",
1510 __func__, qhp->attr.state);
1511 ret = -EINVAL;
1512 goto err;
1513 break;
1514 }
1515 goto out;
1516err:
1517 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1518 qhp->wq.sq.qid);
1519
1520 /* disassociate the LLP connection */
1521 qhp->attr.llp_stream_handle = NULL;
af93fb5d
SW		 1522 if (!ep)
1523 ep = qhp->ep;
cfdda9d7 1524 qhp->ep = NULL;
2f5b48c3 1525 set_state(qhp, C4IW_QP_STATE_ERROR);
cfdda9d7 1526 free = 1;
91e9c071 1527 abort = 1;
cfdda9d7
SW		 1528 wake_up(&qhp->wait);
1529 BUG_ON(!ep);
2f5b48c3 1530 flush_qp(qhp);
cfdda9d7 1531out:
2f5b48c3 1532 mutex_unlock(&qhp->mutex);
cfdda9d7
SW		 1533
1534 if (terminate)
be4c9bad 1535 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
cfdda9d7
SW		 1536
1537 /*
1538 * If disconnect is 1, then we need to initiate a disconnect
1539 * on the EP. This can be a normal close (RTS->CLOSING) or
1540 * an abnormal close (RTS/CLOSING->ERROR).
1541 */
1542 if (disconnect) {
be4c9bad
RD		 1543 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1544 GFP_KERNEL);
cfdda9d7
SW		 1545 c4iw_put_ep(&ep->com);
1546 }
1547
1548 /*
1549 * If free is 1, then we've disassociated the EP from the QP
1550 * and we need to dereference the EP.
1551 */
1552 if (free)
1553 c4iw_put_ep(&ep->com);
cfdda9d7
SW		 1554 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1555 return ret;
1556}
1557
1558int c4iw_destroy_qp(struct ib_qp *ib_qp)
1559{
1560 struct c4iw_dev *rhp;
1561 struct c4iw_qp *qhp;
1562 struct c4iw_qp_attributes attrs;
1563 struct c4iw_ucontext *ucontext;
1564
1565 qhp = to_c4iw_qp(ib_qp);
1566 rhp = qhp->rhp;
1567
1568 attrs.next_state = C4IW_QP_STATE_ERROR;
d2fe99e8
KS		 1569 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1570 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1571 else
1572 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
cfdda9d7
SW		 1573 wait_event(qhp->wait, !qhp->ep);
1574
05eb2389 1575 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
cfdda9d7
SW		 1576 atomic_dec(&qhp->refcnt);
1577 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1578
05eb2389
SW		 1579 spin_lock_irq(&rhp->lock);
1580 if (!list_empty(&qhp->db_fc_entry))
1581 list_del_init(&qhp->db_fc_entry);
1582 spin_unlock_irq(&rhp->lock);
4c2c5763 1583 free_ird(rhp, qhp->attr.max_ird);
05eb2389 1584
cfdda9d7
SW		 1585 ucontext = ib_qp->uobject ?
1586 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1587 destroy_qp(&rhp->rdev, &qhp->wq,
1588 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1589
1590 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1591 kfree(qhp);
1592 return 0;
1593}
1594
1595struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1596 struct ib_udata *udata)
1597{
1598 struct c4iw_dev *rhp;
1599 struct c4iw_qp *qhp;
1600 struct c4iw_pd *php;
1601 struct c4iw_cq *schp;
1602 struct c4iw_cq *rchp;
1603 struct c4iw_create_qp_resp uresp;
ff1706f4 1604 unsigned int sqsize, rqsize;
cfdda9d7
SW		 1605 struct c4iw_ucontext *ucontext;
1606 int ret;
c6d7b267 1607 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
cfdda9d7
SW		 1608
1609 PDBG("%s ib_pd %p\n", __func__, pd);
1610
1611 if (attrs->qp_type != IB_QPT_RC)
1612 return ERR_PTR(-EINVAL);
1613
1614 php = to_c4iw_pd(pd);
1615 rhp = php->rhp;
1616 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1617 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1618 if (!schp || !rchp)
1619 return ERR_PTR(-EINVAL);
1620
1621 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1622 return ERR_PTR(-EINVAL);
1623
1624 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
04e10e21 1625 if (rqsize > rhp->rdev.hw_queue.t4_max_rq_size)
cfdda9d7
SW		 1626 return ERR_PTR(-E2BIG);
1627
1628 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
04e10e21 1629 if (sqsize > rhp->rdev.hw_queue.t4_max_sq_size)
cfdda9d7
SW		 1630 return ERR_PTR(-E2BIG);
1631
1632 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1633
cfdda9d7
SW		 1634 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1635 if (!qhp)
1636 return ERR_PTR(-ENOMEM);
1637 qhp->wq.sq.size = sqsize;
1638 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1cf24dce 1639 qhp->wq.sq.flush_cidx = -1;
cfdda9d7
SW		 1640 qhp->wq.rq.size = rqsize;
1641 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1642
1643 if (ucontext) {
1644 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1645 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1646 }
1647
1648 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1649 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1650
1651 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1652 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1653 if (ret)
1654 goto err1;
1655
1656 attrs->cap.max_recv_wr = rqsize - 1;
1657 attrs->cap.max_send_wr = sqsize - 1;
1658 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1659
1660 qhp->rhp = rhp;
1661 qhp->attr.pd = php->pdid;
1662 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1663 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1664 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1665 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1666 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1667 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1668 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1669 qhp->attr.state = C4IW_QP_STATE_IDLE;
1670 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1671 qhp->attr.enable_rdma_read = 1;
1672 qhp->attr.enable_rdma_write = 1;
1673 qhp->attr.enable_bind = 1;
4c2c5763
HS		 1674 qhp->attr.max_ord = 0;
1675 qhp->attr.max_ird = 0;
ba32de9d 1676 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
cfdda9d7 1677 spin_lock_init(&qhp->lock);
2f5b48c3 1678 mutex_init(&qhp->mutex);
cfdda9d7
SW		 1679 init_waitqueue_head(&qhp->wait);
1680 atomic_set(&qhp->refcnt, 1);
1681
05eb2389 1682 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
cfdda9d7
SW		 1683 if (ret)
1684 goto err2;
1685
cfdda9d7
SW		 1686 if (udata) {
1687 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1688 if (!mm1) {
1689 ret = -ENOMEM;
30a6a62f 1690 goto err3;
cfdda9d7
SW		 1691 }
1692 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1693 if (!mm2) {
1694 ret = -ENOMEM;
30a6a62f 1695 goto err4;
cfdda9d7
SW		 1696 }
1697 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1698 if (!mm3) {
1699 ret = -ENOMEM;
30a6a62f 1700 goto err5;
cfdda9d7
SW		 1701 }
1702 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1703 if (!mm4) {
1704 ret = -ENOMEM;
30a6a62f 1705 goto err6;
cfdda9d7 1706 }
c6d7b267
SW		 1707 if (t4_sq_onchip(&qhp->wq.sq)) {
1708 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1709 if (!mm5) {
1710 ret = -ENOMEM;
1711 goto err7;
1712 }
1713 uresp.flags = C4IW_QPF_ONCHIP;
1714 } else
1715 uresp.flags = 0;
cfdda9d7
SW		 1716 uresp.qid_mask = rhp->rdev.qpmask;
1717 uresp.sqid = qhp->wq.sq.qid;
1718 uresp.sq_size = qhp->wq.sq.size;
1719 uresp.sq_memsize = qhp->wq.sq.memsize;
1720 uresp.rqid = qhp->wq.rq.qid;
1721 uresp.rq_size = qhp->wq.rq.size;
1722 uresp.rq_memsize = qhp->wq.rq.memsize;
1723 spin_lock(&ucontext->mmap_lock);
c6d7b267
SW		 1724 if (mm5) {
1725 uresp.ma_sync_key = ucontext->key;
1726 ucontext->key += PAGE_SIZE;
ae1fe07f
DC		 1727 } else {
1728 uresp.ma_sync_key = 0;
c6d7b267 1729 }
cfdda9d7
SW		 1730 uresp.sq_key = ucontext->key;
1731 ucontext->key += PAGE_SIZE;
1732 uresp.rq_key = ucontext->key;
1733 ucontext->key += PAGE_SIZE;
1734 uresp.sq_db_gts_key = ucontext->key;
1735 ucontext->key += PAGE_SIZE;
1736 uresp.rq_db_gts_key = ucontext->key;
1737 ucontext->key += PAGE_SIZE;
1738 spin_unlock(&ucontext->mmap_lock);
1739 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1740 if (ret)
c6d7b267 1741 goto err8;
cfdda9d7 1742 mm1->key = uresp.sq_key;
c6d7b267 1743 mm1->addr = qhp->wq.sq.phys_addr;
cfdda9d7
SW		 1744 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1745 insert_mmap(ucontext, mm1);
1746 mm2->key = uresp.rq_key;
1747 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1748 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1749 insert_mmap(ucontext, mm2);
1750 mm3->key = uresp.sq_db_gts_key;
fa658a98 1751 mm3->addr = (__force unsigned long) qhp->wq.sq.udb;
cfdda9d7
SW		 1752 mm3->len = PAGE_SIZE;
1753 insert_mmap(ucontext, mm3);
1754 mm4->key = uresp.rq_db_gts_key;
fa658a98 1755 mm4->addr = (__force unsigned long) qhp->wq.rq.udb;
cfdda9d7
SW		 1756 mm4->len = PAGE_SIZE;
1757 insert_mmap(ucontext, mm4);
c6d7b267
SW		 1758 if (mm5) {
1759 mm5->key = uresp.ma_sync_key;
1760 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1761 + A_PCIE_MA_SYNC) & PAGE_MASK;
1762 mm5->len = PAGE_SIZE;
1763 insert_mmap(ucontext, mm5);
1764 }
cfdda9d7
SW		 1765 }
1766 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1767 init_timer(&(qhp->timer));
05eb2389 1768 INIT_LIST_HEAD(&qhp->db_fc_entry);
cfdda9d7
SW		 1769 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1770 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1771 qhp->wq.sq.qid);
1772 return &qhp->ibqp;
c6d7b267
SW		 1773err8:
1774 kfree(mm5);
cfdda9d7 1775err7:
30a6a62f 1776 kfree(mm4);
cfdda9d7 1777err6:
30a6a62f 1778 kfree(mm3);
cfdda9d7 1779err5:
30a6a62f 1780 kfree(mm2);
cfdda9d7 1781err4:
30a6a62f 1782 kfree(mm1);
cfdda9d7
SW		 1783err3:
1784 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1785err2:
1786 destroy_qp(&rhp->rdev, &qhp->wq,
1787 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1788err1:
1789 kfree(qhp);
1790 return ERR_PTR(ret);
1791}
1792
1793int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1794 int attr_mask, struct ib_udata *udata)
1795{
1796 struct c4iw_dev *rhp;
1797 struct c4iw_qp *qhp;
1798 enum c4iw_qp_attr_mask mask = 0;
1799 struct c4iw_qp_attributes attrs;
1800
1801 PDBG("%s ib_qp %p\n", __func__, ibqp);
1802
1803 /* iwarp does not support the RTR state */
1804 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1805 attr_mask &= ~IB_QP_STATE;
1806
1807 /* Make sure we still have something left to do */
1808 if (!attr_mask)
1809 return 0;
1810
1811 memset(&attrs, 0, sizeof attrs);
1812 qhp = to_c4iw_qp(ibqp);
1813 rhp = qhp->rhp;
1814
1815 attrs.next_state = c4iw_convert_state(attr->qp_state);
1816 attrs.enable_rdma_read = (attr->qp_access_flags &
1817 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1818 attrs.enable_rdma_write = (attr->qp_access_flags &
1819 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1820 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1821
1822
1823 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1824 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1825 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1826 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1827 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1828
2c974781
VP		 1829 /*
1830 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1831 * ringing the queue db when we're in DB_FULL mode.
c2f9da92 1832 * Only allow this on T4 devices.
2c974781
VP		 1833 */
1834 attrs.sq_db_inc = attr->sq_psn;
1835 attrs.rq_db_inc = attr->rq_psn;
1836 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1837 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
c2f9da92
SW		 1838 if (is_t5(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) &&
1839 (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB)))
1840 return -EINVAL;
2c974781 1841
cfdda9d7
SW		 1842 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1843}
1844
1845struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1846{
1847 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1848 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1849}
67bbc055
VP		 1850
1851int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1852 int attr_mask, struct ib_qp_init_attr *init_attr)
1853{
1854 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1855
1856 memset(attr, 0, sizeof *attr);
1857 memset(init_attr, 0, sizeof *init_attr);
1858 attr->qp_state = to_ib_qp_state(qhp->attr.state);
1859 return 0;
1860}
Linux 6.x block layer and io_uring tree(s)