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RDMA/cxgb4: Support on-chip SQs
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / qp.c
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#include "iw_cxgb4.h"
33
c6d7b267
SW		 34static int ocqp_support;
35module_param(ocqp_support, int, 0644);
36MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=0)");
37
38static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
39{
40 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
41}
42
43static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
44{
45 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
46 pci_unmap_addr(sq, mapping));
47}
48
49static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
50{
51 if (t4_sq_onchip(sq))
52 dealloc_oc_sq(rdev, sq);
53 else
54 dealloc_host_sq(rdev, sq);
55}
56
57static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
58{
59 if (!ocqp_support || !t4_ocqp_supported())
60 return -ENOSYS;
61 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
62 if (!sq->dma_addr)
63 return -ENOMEM;
64 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
65 rdev->lldi.vr->ocq.start;
66 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
67 rdev->lldi.vr->ocq.start);
68 sq->flags |= T4_SQ_ONCHIP;
69 return 0;
70}
71
72static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
73{
74 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
75 &(sq->dma_addr), GFP_KERNEL);
76 if (!sq->queue)
77 return -ENOMEM;
78 sq->phys_addr = virt_to_phys(sq->queue);
79 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
80 return 0;
81}
82
cfdda9d7
SW		 83static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
84 struct c4iw_dev_ucontext *uctx)
85{
86 /*
87 * uP clears EQ contexts when the connection exits rdma mode,
88 * so no need to post a RESET WR for these EQs.
89 */
90 dma_free_coherent(&(rdev->lldi.pdev->dev),
91 wq->rq.memsize, wq->rq.queue,
f38926aa 92 dma_unmap_addr(&wq->rq, mapping));
c6d7b267 93 dealloc_sq(rdev, &wq->sq);
cfdda9d7
SW		 94 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
95 kfree(wq->rq.sw_rq);
96 kfree(wq->sq.sw_sq);
97 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
98 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
99 return 0;
100}
101
102static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
103 struct t4_cq *rcq, struct t4_cq *scq,
104 struct c4iw_dev_ucontext *uctx)
105{
106 int user = (uctx != &rdev->uctx);
107 struct fw_ri_res_wr *res_wr;
108 struct fw_ri_res *res;
109 int wr_len;
110 struct c4iw_wr_wait wr_wait;
111 struct sk_buff *skb;
112 int ret;
113 int eqsize;
114
115 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
116 if (!wq->sq.qid)
117 return -ENOMEM;
118
119 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
120 if (!wq->rq.qid)
121 goto err1;
122
123 if (!user) {
124 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
125 GFP_KERNEL);
126 if (!wq->sq.sw_sq)
127 goto err2;
128
129 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
130 GFP_KERNEL);
131 if (!wq->rq.sw_rq)
132 goto err3;
133 }
134
135 /*
136 * RQT must be a power of 2.
137 */
138 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
139 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
140 if (!wq->rq.rqt_hwaddr)
141 goto err4;
142
c6d7b267
SW		 143 if (user) {
144 if (alloc_oc_sq(rdev, &wq->sq) && alloc_host_sq(rdev, &wq->sq))
145 goto err5;
146 } else
147 if (alloc_host_sq(rdev, &wq->sq))
148 goto err5;
cfdda9d7 149 memset(wq->sq.queue, 0, wq->sq.memsize);
f38926aa 150 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
cfdda9d7
SW		 151
152 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
153 wq->rq.memsize, &(wq->rq.dma_addr),
154 GFP_KERNEL);
155 if (!wq->rq.queue)
156 goto err6;
157 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
158 __func__, wq->sq.queue,
159 (unsigned long long)virt_to_phys(wq->sq.queue),
160 wq->rq.queue,
161 (unsigned long long)virt_to_phys(wq->rq.queue));
162 memset(wq->rq.queue, 0, wq->rq.memsize);
f38926aa 163 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
cfdda9d7
SW		 164
165 wq->db = rdev->lldi.db_reg;
166 wq->gts = rdev->lldi.gts_reg;
167 if (user) {
168 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
169 (wq->sq.qid << rdev->qpshift);
170 wq->sq.udb &= PAGE_MASK;
171 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
172 (wq->rq.qid << rdev->qpshift);
173 wq->rq.udb &= PAGE_MASK;
174 }
175 wq->rdev = rdev;
176 wq->rq.msn = 1;
177
178 /* build fw_ri_res_wr */
179 wr_len = sizeof *res_wr + 2 * sizeof *res;
180
d3c814e8 181 skb = alloc_skb(wr_len, GFP_KERNEL);
cfdda9d7
SW		 182 if (!skb) {
183 ret = -ENOMEM;
184 goto err7;
185 }
186 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
187
188 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
189 memset(res_wr, 0, wr_len);
190 res_wr->op_nres = cpu_to_be32(
191 FW_WR_OP(FW_RI_RES_WR) |
192 V_FW_RI_RES_WR_NRES(2) |
193 FW_WR_COMPL(1));
194 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
c8e081a1 195 res_wr->cookie = (unsigned long) &wr_wait;
cfdda9d7
SW		 196 res = res_wr->res;
197 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
198 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
199
200 /*
201 * eqsize is the number of 64B entries plus the status page size.
202 */
203 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
204
205 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
206 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
207 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
208 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
c6d7b267 209 t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0 |
cfdda9d7
SW		 210 V_FW_RI_RES_WR_IQID(scq->cqid));
211 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
212 V_FW_RI_RES_WR_DCAEN(0) |
213 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 214 V_FW_RI_RES_WR_FBMIN(2) |
cfdda9d7
SW		 215 V_FW_RI_RES_WR_FBMAX(3) |
216 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
217 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
218 V_FW_RI_RES_WR_EQSIZE(eqsize));
219 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
220 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
221 res++;
222 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
223 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
224
225 /*
226 * eqsize is the number of 64B entries plus the status page size.
227 */
228 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
229 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
230 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
231 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
232 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
233 V_FW_RI_RES_WR_IQID(rcq->cqid));
234 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
235 V_FW_RI_RES_WR_DCAEN(0) |
236 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 237 V_FW_RI_RES_WR_FBMIN(2) |
cfdda9d7
SW		 238 V_FW_RI_RES_WR_FBMAX(3) |
239 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
240 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
241 V_FW_RI_RES_WR_EQSIZE(eqsize));
242 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
243 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
244
245 c4iw_init_wr_wait(&wr_wait);
246
247 ret = c4iw_ofld_send(rdev, skb);
248 if (ret)
249 goto err7;
aadc4df3 250 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
cfdda9d7
SW		 251 if (ret)
252 goto err7;
253
254 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
255 __func__, wq->sq.qid, wq->rq.qid, wq->db,
256 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
257
258 return 0;
259err7:
260 dma_free_coherent(&(rdev->lldi.pdev->dev),
261 wq->rq.memsize, wq->rq.queue,
f38926aa 262 dma_unmap_addr(&wq->rq, mapping));
cfdda9d7 263err6:
c6d7b267 264 dealloc_sq(rdev, &wq->sq);
cfdda9d7
SW		 265err5:
266 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
267err4:
268 kfree(wq->rq.sw_rq);
269err3:
270 kfree(wq->sq.sw_sq);
271err2:
272 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
273err1:
274 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
275 return -ENOMEM;
276}
277
d37ac31d
SW		 278static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
279 struct ib_send_wr *wr, int max, u32 *plenp)
cfdda9d7 280{
d37ac31d
SW		 281 u8 *dstp, *srcp;
282 u32 plen = 0;
cfdda9d7 283 int i;
d37ac31d
SW		 284 int rem, len;
285
286 dstp = (u8 *)immdp->data;
287 for (i = 0; i < wr->num_sge; i++) {
288 if ((plen + wr->sg_list[i].length) > max)
289 return -EMSGSIZE;
290 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
291 plen += wr->sg_list[i].length;
292 rem = wr->sg_list[i].length;
293 while (rem) {
294 if (dstp == (u8 *)&sq->queue[sq->size])
295 dstp = (u8 *)sq->queue;
296 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
297 len = rem;
298 else
299 len = (u8 *)&sq->queue[sq->size] - dstp;
300 memcpy(dstp, srcp, len);
301 dstp += len;
302 srcp += len;
303 rem -= len;
304 }
305 }
13fecb83
SW		 306 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
307 if (len)
308 memset(dstp, 0, len);
d37ac31d
SW		 309 immdp->op = FW_RI_DATA_IMMD;
310 immdp->r1 = 0;
311 immdp->r2 = 0;
312 immdp->immdlen = cpu_to_be32(plen);
313 *plenp = plen;
314 return 0;
315}
316
317static int build_isgl(__be64 *queue_start, __be64 *queue_end,
318 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
319 int num_sge, u32 *plenp)
320
321{
322 int i;
323 u32 plen = 0;
324 __be64 *flitp = (__be64 *)isglp->sge;
325
326 for (i = 0; i < num_sge; i++) {
327 if ((plen + sg_list[i].length) < plen)
328 return -EMSGSIZE;
329 plen += sg_list[i].length;
330 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
331 sg_list[i].length);
332 if (++flitp == queue_end)
333 flitp = queue_start;
334 *flitp = cpu_to_be64(sg_list[i].addr);
335 if (++flitp == queue_end)
336 flitp = queue_start;
337 }
13fecb83 338 *flitp = (__force __be64)0;
d37ac31d
SW		 339 isglp->op = FW_RI_DATA_ISGL;
340 isglp->r1 = 0;
341 isglp->nsge = cpu_to_be16(num_sge);
342 isglp->r2 = 0;
343 if (plenp)
344 *plenp = plen;
345 return 0;
346}
347
348static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
349 struct ib_send_wr *wr, u8 *len16)
350{
cfdda9d7
SW		 351 u32 plen;
352 int size;
d37ac31d 353 int ret;
cfdda9d7
SW		 354
355 if (wr->num_sge > T4_MAX_SEND_SGE)
356 return -EINVAL;
357 switch (wr->opcode) {
358 case IB_WR_SEND:
359 if (wr->send_flags & IB_SEND_SOLICITED)
360 wqe->send.sendop_pkd = cpu_to_be32(
361 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
362 else
363 wqe->send.sendop_pkd = cpu_to_be32(
364 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
365 wqe->send.stag_inv = 0;
366 break;
367 case IB_WR_SEND_WITH_INV:
368 if (wr->send_flags & IB_SEND_SOLICITED)
369 wqe->send.sendop_pkd = cpu_to_be32(
370 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
371 else
372 wqe->send.sendop_pkd = cpu_to_be32(
373 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
374 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
375 break;
376
377 default:
378 return -EINVAL;
379 }
d37ac31d 380
cfdda9d7
SW		 381 plen = 0;
382 if (wr->num_sge) {
383 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 384 ret = build_immd(sq, wqe->send.u.immd_src, wr,
385 T4_MAX_SEND_INLINE, &plen);
386 if (ret)
387 return ret;
cfdda9d7
SW		 388 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
389 plen;
390 } else {
d37ac31d
SW		 391 ret = build_isgl((__be64 *)sq->queue,
392 (__be64 *)&sq->queue[sq->size],
393 wqe->send.u.isgl_src,
394 wr->sg_list, wr->num_sge, &plen);
395 if (ret)
396 return ret;
cfdda9d7
SW		 397 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
398 wr->num_sge * sizeof(struct fw_ri_sge);
399 }
400 } else {
401 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
402 wqe->send.u.immd_src[0].r1 = 0;
403 wqe->send.u.immd_src[0].r2 = 0;
404 wqe->send.u.immd_src[0].immdlen = 0;
405 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
d37ac31d 406 plen = 0;
cfdda9d7
SW		 407 }
408 *len16 = DIV_ROUND_UP(size, 16);
409 wqe->send.plen = cpu_to_be32(plen);
410 return 0;
411}
412
d37ac31d
SW		 413static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
414 struct ib_send_wr *wr, u8 *len16)
cfdda9d7 415{
cfdda9d7
SW		 416 u32 plen;
417 int size;
d37ac31d 418 int ret;
cfdda9d7 419
d37ac31d 420 if (wr->num_sge > T4_MAX_SEND_SGE)
cfdda9d7
SW		 421 return -EINVAL;
422 wqe->write.r2 = 0;
423 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
424 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
cfdda9d7
SW		 425 if (wr->num_sge) {
426 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 427 ret = build_immd(sq, wqe->write.u.immd_src, wr,
428 T4_MAX_WRITE_INLINE, &plen);
429 if (ret)
430 return ret;
cfdda9d7
SW		 431 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
432 plen;
433 } else {
d37ac31d
SW		 434 ret = build_isgl((__be64 *)sq->queue,
435 (__be64 *)&sq->queue[sq->size],
436 wqe->write.u.isgl_src,
437 wr->sg_list, wr->num_sge, &plen);
438 if (ret)
439 return ret;
cfdda9d7
SW		 440 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
441 wr->num_sge * sizeof(struct fw_ri_sge);
442 }
443 } else {
444 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
445 wqe->write.u.immd_src[0].r1 = 0;
446 wqe->write.u.immd_src[0].r2 = 0;
447 wqe->write.u.immd_src[0].immdlen = 0;
448 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
d37ac31d 449 plen = 0;
cfdda9d7
SW		 450 }
451 *len16 = DIV_ROUND_UP(size, 16);
452 wqe->write.plen = cpu_to_be32(plen);
453 return 0;
454}
455
456static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
457{
458 if (wr->num_sge > 1)
459 return -EINVAL;
460 if (wr->num_sge) {
461 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
462 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
463 >> 32));
464 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
465 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
466 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
467 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
468 >> 32));
469 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
470 } else {
471 wqe->read.stag_src = cpu_to_be32(2);
472 wqe->read.to_src_hi = 0;
473 wqe->read.to_src_lo = 0;
474 wqe->read.stag_sink = cpu_to_be32(2);
475 wqe->read.plen = 0;
476 wqe->read.to_sink_hi = 0;
477 wqe->read.to_sink_lo = 0;
478 }
479 wqe->read.r2 = 0;
480 wqe->read.r5 = 0;
481 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
482 return 0;
483}
484
485static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
486 struct ib_recv_wr *wr, u8 *len16)
487{
d37ac31d 488 int ret;
cfdda9d7 489
d37ac31d
SW		 490 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
491 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
492 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
493 if (ret)
494 return ret;
cfdda9d7
SW		 495 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
496 wr->num_sge * sizeof(struct fw_ri_sge), 16);
497 return 0;
498}
499
500static int build_fastreg(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
501{
502
503 struct fw_ri_immd *imdp;
504 __be64 *p;
505 int i;
506 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
507
508 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
509 return -EINVAL;
510
511 wqe->fr.qpbinde_to_dcacpu = 0;
512 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
513 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
514 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
515 wqe->fr.len_hi = 0;
516 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
517 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
518 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
519 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
520 0xffffffff);
521 if (pbllen > T4_MAX_FR_IMMD) {
522 struct c4iw_fr_page_list *c4pl =
523 to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
524 struct fw_ri_dsgl *sglp;
525
526 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
527 sglp->op = FW_RI_DATA_DSGL;
528 sglp->r1 = 0;
529 sglp->nsge = cpu_to_be16(1);
530 sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
531 sglp->len0 = cpu_to_be32(pbllen);
532
533 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *sglp, 16);
534 } else {
535 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
536 imdp->op = FW_RI_DATA_IMMD;
537 imdp->r1 = 0;
538 imdp->r2 = 0;
539 imdp->immdlen = cpu_to_be32(pbllen);
540 p = (__be64 *)(imdp + 1);
541 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++, p++)
542 *p = cpu_to_be64(
543 (u64)wr->wr.fast_reg.page_list->page_list[i]);
544 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen,
545 16);
546 }
547 return 0;
548}
549
550static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
551 u8 *len16)
552{
553 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
554 wqe->inv.r2 = 0;
555 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
556 return 0;
557}
558
559void c4iw_qp_add_ref(struct ib_qp *qp)
560{
561 PDBG("%s ib_qp %p\n", __func__, qp);
562 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
563}
564
565void c4iw_qp_rem_ref(struct ib_qp *qp)
566{
567 PDBG("%s ib_qp %p\n", __func__, qp);
568 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
569 wake_up(&(to_c4iw_qp(qp)->wait));
570}
571
572int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
573 struct ib_send_wr **bad_wr)
574{
575 int err = 0;
576 u8 len16 = 0;
577 enum fw_wr_opcodes fw_opcode = 0;
578 enum fw_ri_wr_flags fw_flags;
579 struct c4iw_qp *qhp;
580 union t4_wr *wqe;
581 u32 num_wrs;
582 struct t4_swsqe *swsqe;
583 unsigned long flag;
584 u16 idx = 0;
585
586 qhp = to_c4iw_qp(ibqp);
587 spin_lock_irqsave(&qhp->lock, flag);
588 if (t4_wq_in_error(&qhp->wq)) {
589 spin_unlock_irqrestore(&qhp->lock, flag);
590 return -EINVAL;
591 }
592 num_wrs = t4_sq_avail(&qhp->wq);
593 if (num_wrs == 0) {
594 spin_unlock_irqrestore(&qhp->lock, flag);
595 return -ENOMEM;
596 }
597 while (wr) {
598 if (num_wrs == 0) {
599 err = -ENOMEM;
600 *bad_wr = wr;
601 break;
602 }
d37ac31d
SW		 603 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
604 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
605
cfdda9d7
SW		 606 fw_flags = 0;
607 if (wr->send_flags & IB_SEND_SOLICITED)
608 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
609 if (wr->send_flags & IB_SEND_SIGNALED)
610 fw_flags |= FW_RI_COMPLETION_FLAG;
611 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
612 switch (wr->opcode) {
613 case IB_WR_SEND_WITH_INV:
614 case IB_WR_SEND:
615 if (wr->send_flags & IB_SEND_FENCE)
616 fw_flags |= FW_RI_READ_FENCE_FLAG;
617 fw_opcode = FW_RI_SEND_WR;
618 if (wr->opcode == IB_WR_SEND)
619 swsqe->opcode = FW_RI_SEND;
620 else
621 swsqe->opcode = FW_RI_SEND_WITH_INV;
d37ac31d 622 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 623 break;
624 case IB_WR_RDMA_WRITE:
625 fw_opcode = FW_RI_RDMA_WRITE_WR;
626 swsqe->opcode = FW_RI_RDMA_WRITE;
d37ac31d 627 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 628 break;
629 case IB_WR_RDMA_READ:
2f1fb507 630 case IB_WR_RDMA_READ_WITH_INV:
cfdda9d7
SW		 631 fw_opcode = FW_RI_RDMA_READ_WR;
632 swsqe->opcode = FW_RI_READ_REQ;
2f1fb507
SW		 633 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
634 fw_flags |= FW_RI_RDMA_READ_INVALIDATE;
635 else
636 fw_flags = 0;
cfdda9d7
SW		 637 err = build_rdma_read(wqe, wr, &len16);
638 if (err)
639 break;
640 swsqe->read_len = wr->sg_list[0].length;
641 if (!qhp->wq.sq.oldest_read)
642 qhp->wq.sq.oldest_read = swsqe;
643 break;
644 case IB_WR_FAST_REG_MR:
645 fw_opcode = FW_RI_FR_NSMR_WR;
646 swsqe->opcode = FW_RI_FAST_REGISTER;
647 err = build_fastreg(wqe, wr, &len16);
648 break;
649 case IB_WR_LOCAL_INV:
4ab1eb9c
SW		 650 if (wr->send_flags & IB_SEND_FENCE)
651 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
cfdda9d7
SW		 652 fw_opcode = FW_RI_INV_LSTAG_WR;
653 swsqe->opcode = FW_RI_LOCAL_INV;
654 err = build_inv_stag(wqe, wr, &len16);
655 break;
656 default:
657 PDBG("%s post of type=%d TBD!\n", __func__,
658 wr->opcode);
659 err = -EINVAL;
660 }
661 if (err) {
662 *bad_wr = wr;
663 break;
664 }
665 swsqe->idx = qhp->wq.sq.pidx;
666 swsqe->complete = 0;
667 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
668 swsqe->wr_id = wr->wr_id;
669
670 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
671
672 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
673 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
674 swsqe->opcode, swsqe->read_len);
675 wr = wr->next;
676 num_wrs--;
d37ac31d
SW		 677 t4_sq_produce(&qhp->wq, len16);
678 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 679 }
680 if (t4_wq_db_enabled(&qhp->wq))
681 t4_ring_sq_db(&qhp->wq, idx);
682 spin_unlock_irqrestore(&qhp->lock, flag);
683 return err;
684}
685
686int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
687 struct ib_recv_wr **bad_wr)
688{
689 int err = 0;
690 struct c4iw_qp *qhp;
691 union t4_recv_wr *wqe;
692 u32 num_wrs;
693 u8 len16 = 0;
694 unsigned long flag;
695 u16 idx = 0;
696
697 qhp = to_c4iw_qp(ibqp);
698 spin_lock_irqsave(&qhp->lock, flag);
699 if (t4_wq_in_error(&qhp->wq)) {
700 spin_unlock_irqrestore(&qhp->lock, flag);
701 return -EINVAL;
702 }
703 num_wrs = t4_rq_avail(&qhp->wq);
704 if (num_wrs == 0) {
705 spin_unlock_irqrestore(&qhp->lock, flag);
706 return -ENOMEM;
707 }
708 while (wr) {
709 if (wr->num_sge > T4_MAX_RECV_SGE) {
710 err = -EINVAL;
711 *bad_wr = wr;
712 break;
713 }
d37ac31d
SW		 714 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
715 qhp->wq.rq.wq_pidx *
716 T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 717 if (num_wrs)
718 err = build_rdma_recv(qhp, wqe, wr, &len16);
719 else
720 err = -ENOMEM;
721 if (err) {
722 *bad_wr = wr;
723 break;
724 }
725
726 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
727
728 wqe->recv.opcode = FW_RI_RECV_WR;
729 wqe->recv.r1 = 0;
730 wqe->recv.wrid = qhp->wq.rq.pidx;
731 wqe->recv.r2[0] = 0;
732 wqe->recv.r2[1] = 0;
733 wqe->recv.r2[2] = 0;
734 wqe->recv.len16 = len16;
cfdda9d7
SW		 735 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
736 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
d37ac31d
SW		 737 t4_rq_produce(&qhp->wq, len16);
738 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 739 wr = wr->next;
740 num_wrs--;
cfdda9d7
SW		 741 }
742 if (t4_wq_db_enabled(&qhp->wq))
743 t4_ring_rq_db(&qhp->wq, idx);
744 spin_unlock_irqrestore(&qhp->lock, flag);
745 return err;
746}
747
748int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
749{
750 return -ENOSYS;
751}
752
753static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
754 u8 *ecode)
755{
756 int status;
757 int tagged;
758 int opcode;
759 int rqtype;
760 int send_inv;
761
762 if (!err_cqe) {
763 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
764 *ecode = 0;
765 return;
766 }
767
768 status = CQE_STATUS(err_cqe);
769 opcode = CQE_OPCODE(err_cqe);
770 rqtype = RQ_TYPE(err_cqe);
771 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
772 (opcode == FW_RI_SEND_WITH_SE_INV);
773 tagged = (opcode == FW_RI_RDMA_WRITE) ||
774 (rqtype && (opcode == FW_RI_READ_RESP));
775
776 switch (status) {
777 case T4_ERR_STAG:
778 if (send_inv) {
779 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
780 *ecode = RDMAP_CANT_INV_STAG;
781 } else {
782 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
783 *ecode = RDMAP_INV_STAG;
784 }
785 break;
786 case T4_ERR_PDID:
787 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
788 if ((opcode == FW_RI_SEND_WITH_INV) ||
789 (opcode == FW_RI_SEND_WITH_SE_INV))
790 *ecode = RDMAP_CANT_INV_STAG;
791 else
792 *ecode = RDMAP_STAG_NOT_ASSOC;
793 break;
794 case T4_ERR_QPID:
795 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
796 *ecode = RDMAP_STAG_NOT_ASSOC;
797 break;
798 case T4_ERR_ACCESS:
799 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
800 *ecode = RDMAP_ACC_VIOL;
801 break;
802 case T4_ERR_WRAP:
803 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
804 *ecode = RDMAP_TO_WRAP;
805 break;
806 case T4_ERR_BOUND:
807 if (tagged) {
808 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
809 *ecode = DDPT_BASE_BOUNDS;
810 } else {
811 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
812 *ecode = RDMAP_BASE_BOUNDS;
813 }
814 break;
815 case T4_ERR_INVALIDATE_SHARED_MR:
816 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
817 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
818 *ecode = RDMAP_CANT_INV_STAG;
819 break;
820 case T4_ERR_ECC:
821 case T4_ERR_ECC_PSTAG:
822 case T4_ERR_INTERNAL_ERR:
823 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
824 *ecode = 0;
825 break;
826 case T4_ERR_OUT_OF_RQE:
827 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
828 *ecode = DDPU_INV_MSN_NOBUF;
829 break;
830 case T4_ERR_PBL_ADDR_BOUND:
831 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
832 *ecode = DDPT_BASE_BOUNDS;
833 break;
834 case T4_ERR_CRC:
835 *layer_type = LAYER_MPA|DDP_LLP;
836 *ecode = MPA_CRC_ERR;
837 break;
838 case T4_ERR_MARKER:
839 *layer_type = LAYER_MPA|DDP_LLP;
840 *ecode = MPA_MARKER_ERR;
841 break;
842 case T4_ERR_PDU_LEN_ERR:
843 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
844 *ecode = DDPU_MSG_TOOBIG;
845 break;
846 case T4_ERR_DDP_VERSION:
847 if (tagged) {
848 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
849 *ecode = DDPT_INV_VERS;
850 } else {
851 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
852 *ecode = DDPU_INV_VERS;
853 }
854 break;
855 case T4_ERR_RDMA_VERSION:
856 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
857 *ecode = RDMAP_INV_VERS;
858 break;
859 case T4_ERR_OPCODE:
860 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
861 *ecode = RDMAP_INV_OPCODE;
862 break;
863 case T4_ERR_DDP_QUEUE_NUM:
864 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
865 *ecode = DDPU_INV_QN;
866 break;
867 case T4_ERR_MSN:
868 case T4_ERR_MSN_GAP:
869 case T4_ERR_MSN_RANGE:
870 case T4_ERR_IRD_OVERFLOW:
871 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
872 *ecode = DDPU_INV_MSN_RANGE;
873 break;
874 case T4_ERR_TBIT:
875 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
876 *ecode = 0;
877 break;
878 case T4_ERR_MO:
879 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
880 *ecode = DDPU_INV_MO;
881 break;
882 default:
883 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
884 *ecode = 0;
885 break;
886 }
887}
888
889int c4iw_post_zb_read(struct c4iw_qp *qhp)
890{
891 union t4_wr *wqe;
892 struct sk_buff *skb;
893 u8 len16;
894
895 PDBG("%s enter\n", __func__);
896 skb = alloc_skb(40, GFP_KERNEL);
897 if (!skb) {
898 printk(KERN_ERR "%s cannot send zb_read!!\n", __func__);
899 return -ENOMEM;
900 }
901 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
902
903 wqe = (union t4_wr *)skb_put(skb, sizeof wqe->read);
904 memset(wqe, 0, sizeof wqe->read);
905 wqe->read.r2 = cpu_to_be64(0);
906 wqe->read.stag_sink = cpu_to_be32(1);
907 wqe->read.to_sink_hi = cpu_to_be32(0);
908 wqe->read.to_sink_lo = cpu_to_be32(1);
909 wqe->read.stag_src = cpu_to_be32(1);
910 wqe->read.plen = cpu_to_be32(0);
911 wqe->read.to_src_hi = cpu_to_be32(0);
912 wqe->read.to_src_lo = cpu_to_be32(1);
913 len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
914 init_wr_hdr(wqe, 0, FW_RI_RDMA_READ_WR, FW_RI_COMPLETION_FLAG, len16);
915
916 return c4iw_ofld_send(&qhp->rhp->rdev, skb);
917}
918
be4c9bad
RD		 919static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
920 gfp_t gfp)
cfdda9d7
SW		 921{
922 struct fw_ri_wr *wqe;
923 struct sk_buff *skb;
924 struct terminate_message *term;
925
926 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
927 qhp->ep->hwtid);
928
be4c9bad 929 skb = alloc_skb(sizeof *wqe, gfp);
cfdda9d7 930 if (!skb)
be4c9bad 931 return;
cfdda9d7
SW		 932 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
933
934 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
935 memset(wqe, 0, sizeof *wqe);
936 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
937 wqe->flowid_len16 = cpu_to_be32(
938 FW_WR_FLOWID(qhp->ep->hwtid) |
939 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
940
941 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
942 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
943 term = (struct terminate_message *)wqe->u.terminate.termmsg;
944 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
be4c9bad 945 c4iw_ofld_send(&qhp->rhp->rdev, skb);
cfdda9d7
SW		 946}
947
948/*
949 * Assumes qhp lock is held.
950 */
951static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
952 struct c4iw_cq *schp, unsigned long *flag)
953{
954 int count;
955 int flushed;
956
957 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
958 /* take a ref on the qhp since we must release the lock */
959 atomic_inc(&qhp->refcnt);
960 spin_unlock_irqrestore(&qhp->lock, *flag);
961
732bee7a 962 /* locking hierarchy: cq lock first, then qp lock. */
cfdda9d7
SW		 963 spin_lock_irqsave(&rchp->lock, *flag);
964 spin_lock(&qhp->lock);
965 c4iw_flush_hw_cq(&rchp->cq);
966 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
967 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
968 spin_unlock(&qhp->lock);
969 spin_unlock_irqrestore(&rchp->lock, *flag);
970 if (flushed)
971 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
972
732bee7a 973 /* locking hierarchy: cq lock first, then qp lock. */
cfdda9d7
SW		 974 spin_lock_irqsave(&schp->lock, *flag);
975 spin_lock(&qhp->lock);
976 c4iw_flush_hw_cq(&schp->cq);
977 c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
978 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
979 spin_unlock(&qhp->lock);
980 spin_unlock_irqrestore(&schp->lock, *flag);
981 if (flushed)
982 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
983
984 /* deref */
985 if (atomic_dec_and_test(&qhp->refcnt))
986 wake_up(&qhp->wait);
987
988 spin_lock_irqsave(&qhp->lock, *flag);
989}
990
991static void flush_qp(struct c4iw_qp *qhp, unsigned long *flag)
992{
993 struct c4iw_cq *rchp, *schp;
994
995 rchp = get_chp(qhp->rhp, qhp->attr.rcq);
996 schp = get_chp(qhp->rhp, qhp->attr.scq);
997
998 if (qhp->ibqp.uobject) {
999 t4_set_wq_in_error(&qhp->wq);
1000 t4_set_cq_in_error(&rchp->cq);
1001 if (schp != rchp)
1002 t4_set_cq_in_error(&schp->cq);
1003 return;
1004 }
1005 __flush_qp(qhp, rchp, schp, flag);
1006}
1007
73d6fcad
SW		 1008static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1009 struct c4iw_ep *ep)
cfdda9d7
SW		 1010{
1011 struct fw_ri_wr *wqe;
1012 int ret;
1013 struct c4iw_wr_wait wr_wait;
1014 struct sk_buff *skb;
1015
1016 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
73d6fcad 1017 ep->hwtid);
cfdda9d7 1018
d3c814e8 1019 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1020 if (!skb)
1021 return -ENOMEM;
73d6fcad 1022 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
cfdda9d7
SW		 1023
1024 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1025 memset(wqe, 0, sizeof *wqe);
1026 wqe->op_compl = cpu_to_be32(
1027 FW_WR_OP(FW_RI_INIT_WR) |
1028 FW_WR_COMPL(1));
1029 wqe->flowid_len16 = cpu_to_be32(
73d6fcad 1030 FW_WR_FLOWID(ep->hwtid) |
cfdda9d7 1031 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
c8e081a1 1032 wqe->cookie = (unsigned long) &wr_wait;
cfdda9d7
SW		 1033
1034 wqe->u.fini.type = FW_RI_TYPE_FINI;
1035 c4iw_init_wr_wait(&wr_wait);
1036 ret = c4iw_ofld_send(&rhp->rdev, skb);
1037 if (ret)
1038 goto out;
1039
aadc4df3
SW		 1040 ret = c4iw_wait_for_reply(&rhp->rdev, &wr_wait, qhp->ep->hwtid,
1041 qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1042out:
1043 PDBG("%s ret %d\n", __func__, ret);
1044 return ret;
1045}
1046
1047static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1048{
1049 memset(&init->u, 0, sizeof init->u);
1050 switch (p2p_type) {
1051 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1052 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1053 init->u.write.stag_sink = cpu_to_be32(1);
1054 init->u.write.to_sink = cpu_to_be64(1);
1055 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1056 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1057 sizeof(struct fw_ri_immd),
1058 16);
1059 break;
1060 case FW_RI_INIT_P2PTYPE_READ_REQ:
1061 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1062 init->u.read.stag_src = cpu_to_be32(1);
1063 init->u.read.to_src_lo = cpu_to_be32(1);
1064 init->u.read.stag_sink = cpu_to_be32(1);
1065 init->u.read.to_sink_lo = cpu_to_be32(1);
1066 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1067 break;
1068 }
1069}
1070
1071static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1072{
1073 struct fw_ri_wr *wqe;
1074 int ret;
1075 struct c4iw_wr_wait wr_wait;
1076 struct sk_buff *skb;
1077
1078 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1079 qhp->ep->hwtid);
1080
d3c814e8 1081 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1082 if (!skb)
1083 return -ENOMEM;
1084 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1085
1086 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1087 memset(wqe, 0, sizeof *wqe);
1088 wqe->op_compl = cpu_to_be32(
1089 FW_WR_OP(FW_RI_INIT_WR) |
1090 FW_WR_COMPL(1));
1091 wqe->flowid_len16 = cpu_to_be32(
1092 FW_WR_FLOWID(qhp->ep->hwtid) |
1093 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1094
c8e081a1 1095 wqe->cookie = (unsigned long) &wr_wait;
cfdda9d7
SW		 1096
1097 wqe->u.init.type = FW_RI_TYPE_INIT;
1098 wqe->u.init.mpareqbit_p2ptype =
1099 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1100 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1101 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1102 if (qhp->attr.mpa_attr.recv_marker_enabled)
1103 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1104 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1105 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1106 if (qhp->attr.mpa_attr.crc_enabled)
1107 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1108
1109 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1110 FW_RI_QP_RDMA_WRITE_ENABLE |
1111 FW_RI_QP_BIND_ENABLE;
1112 if (!qhp->ibqp.uobject)
1113 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1114 FW_RI_QP_STAG0_ENABLE;
1115 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1116 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1117 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1118 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1119 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1120 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1121 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1122 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1123 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1124 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1125 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1126 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1127 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1128 rhp->rdev.lldi.vr->rq.start);
1129 if (qhp->attr.mpa_attr.initiator)
1130 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1131
1132 c4iw_init_wr_wait(&wr_wait);
1133 ret = c4iw_ofld_send(&rhp->rdev, skb);
1134 if (ret)
1135 goto out;
1136
aadc4df3
SW		 1137 ret = c4iw_wait_for_reply(&rhp->rdev, &wr_wait, qhp->ep->hwtid,
1138 qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1139out:
1140 PDBG("%s ret %d\n", __func__, ret);
1141 return ret;
1142}
1143
1144int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1145 enum c4iw_qp_attr_mask mask,
1146 struct c4iw_qp_attributes *attrs,
1147 int internal)
1148{
1149 int ret = 0;
1150 struct c4iw_qp_attributes newattr = qhp->attr;
1151 unsigned long flag;
1152 int disconnect = 0;
1153 int terminate = 0;
1154 int abort = 0;
1155 int free = 0;
1156 struct c4iw_ep *ep = NULL;
1157
1158 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1159 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1160 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1161
1162 spin_lock_irqsave(&qhp->lock, flag);
1163
1164 /* Process attr changes if in IDLE */
1165 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1166 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1167 ret = -EIO;
1168 goto out;
1169 }
1170 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1171 newattr.enable_rdma_read = attrs->enable_rdma_read;
1172 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1173 newattr.enable_rdma_write = attrs->enable_rdma_write;
1174 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1175 newattr.enable_bind = attrs->enable_bind;
1176 if (mask & C4IW_QP_ATTR_MAX_ORD) {
be4c9bad 1177 if (attrs->max_ord > c4iw_max_read_depth) {
cfdda9d7
SW		 1178 ret = -EINVAL;
1179 goto out;
1180 }
1181 newattr.max_ord = attrs->max_ord;
1182 }
1183 if (mask & C4IW_QP_ATTR_MAX_IRD) {
be4c9bad 1184 if (attrs->max_ird > c4iw_max_read_depth) {
cfdda9d7
SW		 1185 ret = -EINVAL;
1186 goto out;
1187 }
1188 newattr.max_ird = attrs->max_ird;
1189 }
1190 qhp->attr = newattr;
1191 }
1192
1193 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1194 goto out;
1195 if (qhp->attr.state == attrs->next_state)
1196 goto out;
1197
1198 switch (qhp->attr.state) {
1199 case C4IW_QP_STATE_IDLE:
1200 switch (attrs->next_state) {
1201 case C4IW_QP_STATE_RTS:
1202 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1203 ret = -EINVAL;
1204 goto out;
1205 }
1206 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1207 ret = -EINVAL;
1208 goto out;
1209 }
1210 qhp->attr.mpa_attr = attrs->mpa_attr;
1211 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1212 qhp->ep = qhp->attr.llp_stream_handle;
1213 qhp->attr.state = C4IW_QP_STATE_RTS;
1214
1215 /*
1216 * Ref the endpoint here and deref when we
1217 * disassociate the endpoint from the QP. This
1218 * happens in CLOSING->IDLE transition or *->ERROR
1219 * transition.
1220 */
1221 c4iw_get_ep(&qhp->ep->com);
1222 spin_unlock_irqrestore(&qhp->lock, flag);
1223 ret = rdma_init(rhp, qhp);
1224 spin_lock_irqsave(&qhp->lock, flag);
1225 if (ret)
1226 goto err;
1227 break;
1228 case C4IW_QP_STATE_ERROR:
1229 qhp->attr.state = C4IW_QP_STATE_ERROR;
1230 flush_qp(qhp, &flag);
1231 break;
1232 default:
1233 ret = -EINVAL;
1234 goto out;
1235 }
1236 break;
1237 case C4IW_QP_STATE_RTS:
1238 switch (attrs->next_state) {
1239 case C4IW_QP_STATE_CLOSING:
1240 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1241 qhp->attr.state = C4IW_QP_STATE_CLOSING;
73d6fcad 1242 ep = qhp->ep;
cfdda9d7
SW		 1243 if (!internal) {
1244 abort = 0;
1245 disconnect = 1;
cfdda9d7
SW		 1246 c4iw_get_ep(&ep->com);
1247 }
1248 spin_unlock_irqrestore(&qhp->lock, flag);
73d6fcad 1249 ret = rdma_fini(rhp, qhp, ep);
cfdda9d7
SW		 1250 spin_lock_irqsave(&qhp->lock, flag);
1251 if (ret) {
cfdda9d7
SW		 1252 c4iw_get_ep(&ep->com);
1253 disconnect = abort = 1;
1254 goto err;
1255 }
1256 break;
1257 case C4IW_QP_STATE_TERMINATE:
1258 qhp->attr.state = C4IW_QP_STATE_TERMINATE;
1259 if (qhp->ibqp.uobject)
1260 t4_set_wq_in_error(&qhp->wq);
be4c9bad
RD		 1261 ep = qhp->ep;
1262 c4iw_get_ep(&ep->com);
0e42c1f4
SW		 1263 if (!internal)
1264 terminate = 1;
be4c9bad 1265 disconnect = 1;
cfdda9d7
SW		 1266 break;
1267 case C4IW_QP_STATE_ERROR:
1268 qhp->attr.state = C4IW_QP_STATE_ERROR;
1269 if (!internal) {
1270 abort = 1;
1271 disconnect = 1;
1272 ep = qhp->ep;
1273 c4iw_get_ep(&ep->com);
1274 }
1275 goto err;
1276 break;
1277 default:
1278 ret = -EINVAL;
1279 goto out;
1280 }
1281 break;
1282 case C4IW_QP_STATE_CLOSING:
1283 if (!internal) {
1284 ret = -EINVAL;
1285 goto out;
1286 }
1287 switch (attrs->next_state) {
1288 case C4IW_QP_STATE_IDLE:
1289 flush_qp(qhp, &flag);
1290 qhp->attr.state = C4IW_QP_STATE_IDLE;
1291 qhp->attr.llp_stream_handle = NULL;
1292 c4iw_put_ep(&qhp->ep->com);
1293 qhp->ep = NULL;
1294 wake_up(&qhp->wait);
1295 break;
1296 case C4IW_QP_STATE_ERROR:
1297 goto err;
1298 default:
1299 ret = -EINVAL;
1300 goto err;
1301 }
1302 break;
1303 case C4IW_QP_STATE_ERROR:
1304 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1305 ret = -EINVAL;
1306 goto out;
1307 }
1308 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1309 ret = -EINVAL;
1310 goto out;
1311 }
1312 qhp->attr.state = C4IW_QP_STATE_IDLE;
1313 break;
1314 case C4IW_QP_STATE_TERMINATE:
1315 if (!internal) {
1316 ret = -EINVAL;
1317 goto out;
1318 }
1319 goto err;
1320 break;
1321 default:
1322 printk(KERN_ERR "%s in a bad state %d\n",
1323 __func__, qhp->attr.state);
1324 ret = -EINVAL;
1325 goto err;
1326 break;
1327 }
1328 goto out;
1329err:
1330 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1331 qhp->wq.sq.qid);
1332
1333 /* disassociate the LLP connection */
1334 qhp->attr.llp_stream_handle = NULL;
af93fb5d
SW		 1335 if (!ep)
1336 ep = qhp->ep;
cfdda9d7
SW		 1337 qhp->ep = NULL;
1338 qhp->attr.state = C4IW_QP_STATE_ERROR;
1339 free = 1;
1340 wake_up(&qhp->wait);
1341 BUG_ON(!ep);
1342 flush_qp(qhp, &flag);
1343out:
1344 spin_unlock_irqrestore(&qhp->lock, flag);
1345
1346 if (terminate)
be4c9bad 1347 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
cfdda9d7
SW		 1348
1349 /*
1350 * If disconnect is 1, then we need to initiate a disconnect
1351 * on the EP. This can be a normal close (RTS->CLOSING) or
1352 * an abnormal close (RTS/CLOSING->ERROR).
1353 */
1354 if (disconnect) {
be4c9bad
RD		 1355 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1356 GFP_KERNEL);
cfdda9d7
SW		 1357 c4iw_put_ep(&ep->com);
1358 }
1359
1360 /*
1361 * If free is 1, then we've disassociated the EP from the QP
1362 * and we need to dereference the EP.
1363 */
1364 if (free)
1365 c4iw_put_ep(&ep->com);
1366
1367 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1368 return ret;
1369}
1370
1371int c4iw_destroy_qp(struct ib_qp *ib_qp)
1372{
1373 struct c4iw_dev *rhp;
1374 struct c4iw_qp *qhp;
1375 struct c4iw_qp_attributes attrs;
1376 struct c4iw_ucontext *ucontext;
1377
1378 qhp = to_c4iw_qp(ib_qp);
1379 rhp = qhp->rhp;
1380
1381 attrs.next_state = C4IW_QP_STATE_ERROR;
1382 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1383 wait_event(qhp->wait, !qhp->ep);
1384
1385 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
cfdda9d7
SW		 1386 atomic_dec(&qhp->refcnt);
1387 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1388
1389 ucontext = ib_qp->uobject ?
1390 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1391 destroy_qp(&rhp->rdev, &qhp->wq,
1392 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1393
1394 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1395 kfree(qhp);
1396 return 0;
1397}
1398
1399struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1400 struct ib_udata *udata)
1401{
1402 struct c4iw_dev *rhp;
1403 struct c4iw_qp *qhp;
1404 struct c4iw_pd *php;
1405 struct c4iw_cq *schp;
1406 struct c4iw_cq *rchp;
1407 struct c4iw_create_qp_resp uresp;
1408 int sqsize, rqsize;
1409 struct c4iw_ucontext *ucontext;
1410 int ret;
c6d7b267 1411 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
cfdda9d7
SW		 1412
1413 PDBG("%s ib_pd %p\n", __func__, pd);
1414
1415 if (attrs->qp_type != IB_QPT_RC)
1416 return ERR_PTR(-EINVAL);
1417
1418 php = to_c4iw_pd(pd);
1419 rhp = php->rhp;
1420 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1421 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1422 if (!schp || !rchp)
1423 return ERR_PTR(-EINVAL);
1424
1425 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1426 return ERR_PTR(-EINVAL);
1427
1428 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1429 if (rqsize > T4_MAX_RQ_SIZE)
1430 return ERR_PTR(-E2BIG);
1431
1432 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1433 if (sqsize > T4_MAX_SQ_SIZE)
1434 return ERR_PTR(-E2BIG);
1435
1436 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1437
1438
1439 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1440 if (!qhp)
1441 return ERR_PTR(-ENOMEM);
1442 qhp->wq.sq.size = sqsize;
1443 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1444 qhp->wq.rq.size = rqsize;
1445 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1446
1447 if (ucontext) {
1448 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1449 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1450 }
1451
1452 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1453 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1454
1455 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1456 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1457 if (ret)
1458 goto err1;
1459
1460 attrs->cap.max_recv_wr = rqsize - 1;
1461 attrs->cap.max_send_wr = sqsize - 1;
1462 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1463
1464 qhp->rhp = rhp;
1465 qhp->attr.pd = php->pdid;
1466 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1467 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1468 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1469 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1470 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1471 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1472 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1473 qhp->attr.state = C4IW_QP_STATE_IDLE;
1474 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1475 qhp->attr.enable_rdma_read = 1;
1476 qhp->attr.enable_rdma_write = 1;
1477 qhp->attr.enable_bind = 1;
1478 qhp->attr.max_ord = 1;
1479 qhp->attr.max_ird = 1;
1480 spin_lock_init(&qhp->lock);
1481 init_waitqueue_head(&qhp->wait);
1482 atomic_set(&qhp->refcnt, 1);
1483
1484 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1485 if (ret)
1486 goto err2;
1487
cfdda9d7
SW		 1488 if (udata) {
1489 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1490 if (!mm1) {
1491 ret = -ENOMEM;
30a6a62f 1492 goto err3;
cfdda9d7
SW		 1493 }
1494 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1495 if (!mm2) {
1496 ret = -ENOMEM;
30a6a62f 1497 goto err4;
cfdda9d7
SW		 1498 }
1499 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1500 if (!mm3) {
1501 ret = -ENOMEM;
30a6a62f 1502 goto err5;
cfdda9d7
SW		 1503 }
1504 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1505 if (!mm4) {
1506 ret = -ENOMEM;
30a6a62f 1507 goto err6;
cfdda9d7 1508 }
c6d7b267
SW		 1509 if (t4_sq_onchip(&qhp->wq.sq)) {
1510 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1511 if (!mm5) {
1512 ret = -ENOMEM;
1513 goto err7;
1514 }
1515 uresp.flags = C4IW_QPF_ONCHIP;
1516 } else
1517 uresp.flags = 0;
cfdda9d7
SW		 1518 uresp.qid_mask = rhp->rdev.qpmask;
1519 uresp.sqid = qhp->wq.sq.qid;
1520 uresp.sq_size = qhp->wq.sq.size;
1521 uresp.sq_memsize = qhp->wq.sq.memsize;
1522 uresp.rqid = qhp->wq.rq.qid;
1523 uresp.rq_size = qhp->wq.rq.size;
1524 uresp.rq_memsize = qhp->wq.rq.memsize;
1525 spin_lock(&ucontext->mmap_lock);
c6d7b267
SW		 1526 if (mm5) {
1527 uresp.ma_sync_key = ucontext->key;
1528 ucontext->key += PAGE_SIZE;
1529 }
cfdda9d7
SW		 1530 uresp.sq_key = ucontext->key;
1531 ucontext->key += PAGE_SIZE;
1532 uresp.rq_key = ucontext->key;
1533 ucontext->key += PAGE_SIZE;
1534 uresp.sq_db_gts_key = ucontext->key;
1535 ucontext->key += PAGE_SIZE;
1536 uresp.rq_db_gts_key = ucontext->key;
1537 ucontext->key += PAGE_SIZE;
1538 spin_unlock(&ucontext->mmap_lock);
1539 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1540 if (ret)
c6d7b267 1541 goto err8;
cfdda9d7 1542 mm1->key = uresp.sq_key;
c6d7b267 1543 mm1->addr = qhp->wq.sq.phys_addr;
cfdda9d7
SW		 1544 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1545 insert_mmap(ucontext, mm1);
1546 mm2->key = uresp.rq_key;
1547 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1548 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1549 insert_mmap(ucontext, mm2);
1550 mm3->key = uresp.sq_db_gts_key;
1551 mm3->addr = qhp->wq.sq.udb;
1552 mm3->len = PAGE_SIZE;
1553 insert_mmap(ucontext, mm3);
1554 mm4->key = uresp.rq_db_gts_key;
1555 mm4->addr = qhp->wq.rq.udb;
1556 mm4->len = PAGE_SIZE;
1557 insert_mmap(ucontext, mm4);
c6d7b267
SW		 1558 if (mm5) {
1559 mm5->key = uresp.ma_sync_key;
1560 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1561 + A_PCIE_MA_SYNC) & PAGE_MASK;
1562 mm5->len = PAGE_SIZE;
1563 insert_mmap(ucontext, mm5);
1564 }
cfdda9d7
SW		 1565 }
1566 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1567 init_timer(&(qhp->timer));
1568 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1569 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1570 qhp->wq.sq.qid);
1571 return &qhp->ibqp;
c6d7b267
SW		 1572err8:
1573 kfree(mm5);
cfdda9d7 1574err7:
30a6a62f 1575 kfree(mm4);
cfdda9d7 1576err6:
30a6a62f 1577 kfree(mm3);
cfdda9d7 1578err5:
30a6a62f 1579 kfree(mm2);
cfdda9d7 1580err4:
30a6a62f 1581 kfree(mm1);
cfdda9d7
SW		 1582err3:
1583 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1584err2:
1585 destroy_qp(&rhp->rdev, &qhp->wq,
1586 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1587err1:
1588 kfree(qhp);
1589 return ERR_PTR(ret);
1590}
1591
1592int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1593 int attr_mask, struct ib_udata *udata)
1594{
1595 struct c4iw_dev *rhp;
1596 struct c4iw_qp *qhp;
1597 enum c4iw_qp_attr_mask mask = 0;
1598 struct c4iw_qp_attributes attrs;
1599
1600 PDBG("%s ib_qp %p\n", __func__, ibqp);
1601
1602 /* iwarp does not support the RTR state */
1603 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1604 attr_mask &= ~IB_QP_STATE;
1605
1606 /* Make sure we still have something left to do */
1607 if (!attr_mask)
1608 return 0;
1609
1610 memset(&attrs, 0, sizeof attrs);
1611 qhp = to_c4iw_qp(ibqp);
1612 rhp = qhp->rhp;
1613
1614 attrs.next_state = c4iw_convert_state(attr->qp_state);
1615 attrs.enable_rdma_read = (attr->qp_access_flags &
1616 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1617 attrs.enable_rdma_write = (attr->qp_access_flags &
1618 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1619 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1620
1621
1622 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1623 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1624 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1625 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1626 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1627
1628 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1629}
1630
1631struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1632{
1633 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1634 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1635}
Linux 6.x block layer and io_uring tree(s)