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RDMA/cxgb4: Use pr_warn_ratelimited
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / qp.c
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
e4dd23d7
PG		 32
33#include <linux/module.h>
34
cfdda9d7
SW		 35#include "iw_cxgb4.h"
36
2c974781
VP		 37static int db_delay_usecs = 1;
38module_param(db_delay_usecs, int, 0644);
39MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
40
a9c77198 41static int ocqp_support = 1;
c6d7b267 42module_param(ocqp_support, int, 0644);
a9c77198 43MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
c6d7b267 44
3cbdb928 45int db_fc_threshold = 1000;
422eea0a 46module_param(db_fc_threshold, int, 0644);
3cbdb928
VP		 47MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
50
51int db_coalescing_threshold;
52module_param(db_coalescing_threshold, int, 0644);
53MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
422eea0a 56
42b6a949
VP		 57static int max_fr_immd = T4_MAX_FR_IMMD;
58module_param(max_fr_immd, int, 0644);
59MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
60
2f5b48c3
SW		 61static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
62{
63 unsigned long flag;
64 spin_lock_irqsave(&qhp->lock, flag);
65 qhp->attr.state = state;
66 spin_unlock_irqrestore(&qhp->lock, flag);
67}
68
c6d7b267
SW		 69static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
70{
71 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
72}
73
74static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
75{
76 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
77 pci_unmap_addr(sq, mapping));
78}
79
80static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
81{
82 if (t4_sq_onchip(sq))
83 dealloc_oc_sq(rdev, sq);
84 else
85 dealloc_host_sq(rdev, sq);
86}
87
88static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
89{
f079af7a 90 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
c6d7b267
SW		 91 return -ENOSYS;
92 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
93 if (!sq->dma_addr)
94 return -ENOMEM;
95 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
96 rdev->lldi.vr->ocq.start;
97 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
98 rdev->lldi.vr->ocq.start);
99 sq->flags |= T4_SQ_ONCHIP;
100 return 0;
101}
102
103static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
104{
105 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
106 &(sq->dma_addr), GFP_KERNEL);
107 if (!sq->queue)
108 return -ENOMEM;
109 sq->phys_addr = virt_to_phys(sq->queue);
110 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
111 return 0;
112}
113
5b0c2759
TLSC		 114static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
115{
116 int ret = -ENOSYS;
117 if (user)
118 ret = alloc_oc_sq(rdev, sq);
119 if (ret)
120 ret = alloc_host_sq(rdev, sq);
121 return ret;
122}
123
cfdda9d7
SW		 124static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
125 struct c4iw_dev_ucontext *uctx)
126{
127 /*
128 * uP clears EQ contexts when the connection exits rdma mode,
129 * so no need to post a RESET WR for these EQs.
130 */
131 dma_free_coherent(&(rdev->lldi.pdev->dev),
132 wq->rq.memsize, wq->rq.queue,
f38926aa 133 dma_unmap_addr(&wq->rq, mapping));
c6d7b267 134 dealloc_sq(rdev, &wq->sq);
cfdda9d7
SW		 135 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
136 kfree(wq->rq.sw_rq);
137 kfree(wq->sq.sw_sq);
138 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
139 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
140 return 0;
141}
142
143static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
144 struct t4_cq *rcq, struct t4_cq *scq,
145 struct c4iw_dev_ucontext *uctx)
146{
147 int user = (uctx != &rdev->uctx);
148 struct fw_ri_res_wr *res_wr;
149 struct fw_ri_res *res;
150 int wr_len;
151 struct c4iw_wr_wait wr_wait;
152 struct sk_buff *skb;
9919d5bd 153 int ret = 0;
cfdda9d7
SW		 154 int eqsize;
155
156 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
157 if (!wq->sq.qid)
158 return -ENOMEM;
159
160 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
c079c287
EG		 161 if (!wq->rq.qid) {
162 ret = -ENOMEM;
163 goto free_sq_qid;
164 }
cfdda9d7
SW		 165
166 if (!user) {
167 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
168 GFP_KERNEL);
c079c287
EG		 169 if (!wq->sq.sw_sq) {
170 ret = -ENOMEM;
171 goto free_rq_qid;
172 }
cfdda9d7
SW		 173
174 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
175 GFP_KERNEL);
c079c287
EG		 176 if (!wq->rq.sw_rq) {
177 ret = -ENOMEM;
178 goto free_sw_sq;
179 }
cfdda9d7
SW		 180 }
181
182 /*
183 * RQT must be a power of 2.
184 */
185 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
186 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
c079c287
EG		 187 if (!wq->rq.rqt_hwaddr) {
188 ret = -ENOMEM;
189 goto free_sw_rq;
190 }
cfdda9d7 191
5b0c2759
TLSC		 192 ret = alloc_sq(rdev, &wq->sq, user);
193 if (ret)
194 goto free_hwaddr;
cfdda9d7 195 memset(wq->sq.queue, 0, wq->sq.memsize);
f38926aa 196 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
cfdda9d7
SW		 197
198 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
199 wq->rq.memsize, &(wq->rq.dma_addr),
200 GFP_KERNEL);
55e57a78
WY		 201 if (!wq->rq.queue) {
202 ret = -ENOMEM;
c079c287 203 goto free_sq;
55e57a78 204 }
cfdda9d7
SW		 205 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
206 __func__, wq->sq.queue,
207 (unsigned long long)virt_to_phys(wq->sq.queue),
208 wq->rq.queue,
209 (unsigned long long)virt_to_phys(wq->rq.queue));
210 memset(wq->rq.queue, 0, wq->rq.memsize);
f38926aa 211 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
cfdda9d7
SW		 212
213 wq->db = rdev->lldi.db_reg;
214 wq->gts = rdev->lldi.gts_reg;
fa658a98
SW		 215 if (user || is_t5(rdev->lldi.adapter_type)) {
216 u32 off;
217
218 off = (wq->sq.qid << rdev->qpshift) & PAGE_MASK;
219 if (user) {
220 wq->sq.udb = (u64 __iomem *)(rdev->bar2_pa + off);
221 } else {
222 off += 128 * (wq->sq.qid & rdev->qpmask) + 8;
223 wq->sq.udb = (u64 __iomem *)(rdev->bar2_kva + off);
224 }
225 off = (wq->rq.qid << rdev->qpshift) & PAGE_MASK;
226 if (user) {
227 wq->rq.udb = (u64 __iomem *)(rdev->bar2_pa + off);
228 } else {
229 off += 128 * (wq->rq.qid & rdev->qpmask) + 8;
230 wq->rq.udb = (u64 __iomem *)(rdev->bar2_kva + off);
231 }
cfdda9d7
SW		 232 }
233 wq->rdev = rdev;
234 wq->rq.msn = 1;
235
236 /* build fw_ri_res_wr */
237 wr_len = sizeof *res_wr + 2 * sizeof *res;
238
d3c814e8 239 skb = alloc_skb(wr_len, GFP_KERNEL);
cfdda9d7
SW		 240 if (!skb) {
241 ret = -ENOMEM;
c079c287 242 goto free_dma;
cfdda9d7
SW		 243 }
244 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
245
246 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
247 memset(res_wr, 0, wr_len);
248 res_wr->op_nres = cpu_to_be32(
249 FW_WR_OP(FW_RI_RES_WR) |
250 V_FW_RI_RES_WR_NRES(2) |
251 FW_WR_COMPL(1));
252 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
c8e081a1 253 res_wr->cookie = (unsigned long) &wr_wait;
cfdda9d7
SW		 254 res = res_wr->res;
255 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
256 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
257
258 /*
259 * eqsize is the number of 64B entries plus the status page size.
260 */
261 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
262
263 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
264 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
265 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
266 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
85d215b0 267 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
cfdda9d7
SW		 268 V_FW_RI_RES_WR_IQID(scq->cqid));
269 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
270 V_FW_RI_RES_WR_DCAEN(0) |
271 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 272 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 273 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 274 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
275 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
276 V_FW_RI_RES_WR_EQSIZE(eqsize));
277 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
278 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
279 res++;
280 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
281 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
282
283 /*
284 * eqsize is the number of 64B entries plus the status page size.
285 */
286 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
287 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
288 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
289 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
290 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
291 V_FW_RI_RES_WR_IQID(rcq->cqid));
292 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
293 V_FW_RI_RES_WR_DCAEN(0) |
294 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 295 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 296 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 297 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
298 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
299 V_FW_RI_RES_WR_EQSIZE(eqsize));
300 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
301 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
302
303 c4iw_init_wr_wait(&wr_wait);
304
305 ret = c4iw_ofld_send(rdev, skb);
306 if (ret)
c079c287 307 goto free_dma;
aadc4df3 308 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
cfdda9d7 309 if (ret)
c079c287 310 goto free_dma;
cfdda9d7 311
fa658a98 312 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%lx rqudb 0x%lx\n",
cfdda9d7 313 __func__, wq->sq.qid, wq->rq.qid, wq->db,
fa658a98
SW		 314 (__force unsigned long) wq->sq.udb,
315 (__force unsigned long) wq->rq.udb);
cfdda9d7
SW		 316
317 return 0;
c079c287 318free_dma:
cfdda9d7
SW		 319 dma_free_coherent(&(rdev->lldi.pdev->dev),
320 wq->rq.memsize, wq->rq.queue,
f38926aa 321 dma_unmap_addr(&wq->rq, mapping));
c079c287 322free_sq:
c6d7b267 323 dealloc_sq(rdev, &wq->sq);
c079c287 324free_hwaddr:
cfdda9d7 325 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
c079c287 326free_sw_rq:
cfdda9d7 327 kfree(wq->rq.sw_rq);
c079c287 328free_sw_sq:
cfdda9d7 329 kfree(wq->sq.sw_sq);
c079c287 330free_rq_qid:
cfdda9d7 331 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
c079c287 332free_sq_qid:
cfdda9d7 333 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
c079c287 334 return ret;
cfdda9d7
SW		 335}
336
d37ac31d
SW		 337static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
338 struct ib_send_wr *wr, int max, u32 *plenp)
cfdda9d7 339{
d37ac31d
SW		 340 u8 *dstp, *srcp;
341 u32 plen = 0;
cfdda9d7 342 int i;
d37ac31d
SW		 343 int rem, len;
344
345 dstp = (u8 *)immdp->data;
346 for (i = 0; i < wr->num_sge; i++) {
347 if ((plen + wr->sg_list[i].length) > max)
348 return -EMSGSIZE;
349 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
350 plen += wr->sg_list[i].length;
351 rem = wr->sg_list[i].length;
352 while (rem) {
353 if (dstp == (u8 *)&sq->queue[sq->size])
354 dstp = (u8 *)sq->queue;
355 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
356 len = rem;
357 else
358 len = (u8 *)&sq->queue[sq->size] - dstp;
359 memcpy(dstp, srcp, len);
360 dstp += len;
361 srcp += len;
362 rem -= len;
363 }
364 }
13fecb83
SW		 365 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
366 if (len)
367 memset(dstp, 0, len);
d37ac31d
SW		 368 immdp->op = FW_RI_DATA_IMMD;
369 immdp->r1 = 0;
370 immdp->r2 = 0;
371 immdp->immdlen = cpu_to_be32(plen);
372 *plenp = plen;
373 return 0;
374}
375
376static int build_isgl(__be64 *queue_start, __be64 *queue_end,
377 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
378 int num_sge, u32 *plenp)
379
380{
381 int i;
382 u32 plen = 0;
383 __be64 *flitp = (__be64 *)isglp->sge;
384
385 for (i = 0; i < num_sge; i++) {
386 if ((plen + sg_list[i].length) < plen)
387 return -EMSGSIZE;
388 plen += sg_list[i].length;
389 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
390 sg_list[i].length);
391 if (++flitp == queue_end)
392 flitp = queue_start;
393 *flitp = cpu_to_be64(sg_list[i].addr);
394 if (++flitp == queue_end)
395 flitp = queue_start;
396 }
13fecb83 397 *flitp = (__force __be64)0;
d37ac31d
SW		 398 isglp->op = FW_RI_DATA_ISGL;
399 isglp->r1 = 0;
400 isglp->nsge = cpu_to_be16(num_sge);
401 isglp->r2 = 0;
402 if (plenp)
403 *plenp = plen;
404 return 0;
405}
406
407static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
408 struct ib_send_wr *wr, u8 *len16)
409{
cfdda9d7
SW		 410 u32 plen;
411 int size;
d37ac31d 412 int ret;
cfdda9d7
SW		 413
414 if (wr->num_sge > T4_MAX_SEND_SGE)
415 return -EINVAL;
416 switch (wr->opcode) {
417 case IB_WR_SEND:
418 if (wr->send_flags & IB_SEND_SOLICITED)
419 wqe->send.sendop_pkd = cpu_to_be32(
420 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
421 else
422 wqe->send.sendop_pkd = cpu_to_be32(
423 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
424 wqe->send.stag_inv = 0;
425 break;
426 case IB_WR_SEND_WITH_INV:
427 if (wr->send_flags & IB_SEND_SOLICITED)
428 wqe->send.sendop_pkd = cpu_to_be32(
429 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
430 else
431 wqe->send.sendop_pkd = cpu_to_be32(
432 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
433 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
434 break;
435
436 default:
437 return -EINVAL;
438 }
d37ac31d 439
cfdda9d7
SW		 440 plen = 0;
441 if (wr->num_sge) {
442 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 443 ret = build_immd(sq, wqe->send.u.immd_src, wr,
444 T4_MAX_SEND_INLINE, &plen);
445 if (ret)
446 return ret;
cfdda9d7
SW		 447 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
448 plen;
449 } else {
d37ac31d
SW		 450 ret = build_isgl((__be64 *)sq->queue,
451 (__be64 *)&sq->queue[sq->size],
452 wqe->send.u.isgl_src,
453 wr->sg_list, wr->num_sge, &plen);
454 if (ret)
455 return ret;
cfdda9d7
SW		 456 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
457 wr->num_sge * sizeof(struct fw_ri_sge);
458 }
459 } else {
460 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
461 wqe->send.u.immd_src[0].r1 = 0;
462 wqe->send.u.immd_src[0].r2 = 0;
463 wqe->send.u.immd_src[0].immdlen = 0;
464 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
d37ac31d 465 plen = 0;
cfdda9d7
SW		 466 }
467 *len16 = DIV_ROUND_UP(size, 16);
468 wqe->send.plen = cpu_to_be32(plen);
469 return 0;
470}
471
d37ac31d
SW		 472static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
473 struct ib_send_wr *wr, u8 *len16)
cfdda9d7 474{
cfdda9d7
SW		 475 u32 plen;
476 int size;
d37ac31d 477 int ret;
cfdda9d7 478
d37ac31d 479 if (wr->num_sge > T4_MAX_SEND_SGE)
cfdda9d7
SW		 480 return -EINVAL;
481 wqe->write.r2 = 0;
482 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
483 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
cfdda9d7
SW		 484 if (wr->num_sge) {
485 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 486 ret = build_immd(sq, wqe->write.u.immd_src, wr,
487 T4_MAX_WRITE_INLINE, &plen);
488 if (ret)
489 return ret;
cfdda9d7
SW		 490 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
491 plen;
492 } else {
d37ac31d
SW		 493 ret = build_isgl((__be64 *)sq->queue,
494 (__be64 *)&sq->queue[sq->size],
495 wqe->write.u.isgl_src,
496 wr->sg_list, wr->num_sge, &plen);
497 if (ret)
498 return ret;
cfdda9d7
SW		 499 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
500 wr->num_sge * sizeof(struct fw_ri_sge);
501 }
502 } else {
503 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
504 wqe->write.u.immd_src[0].r1 = 0;
505 wqe->write.u.immd_src[0].r2 = 0;
506 wqe->write.u.immd_src[0].immdlen = 0;
507 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
d37ac31d 508 plen = 0;
cfdda9d7
SW		 509 }
510 *len16 = DIV_ROUND_UP(size, 16);
511 wqe->write.plen = cpu_to_be32(plen);
512 return 0;
513}
514
515static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
516{
517 if (wr->num_sge > 1)
518 return -EINVAL;
519 if (wr->num_sge) {
520 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
521 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
522 >> 32));
523 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
524 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
525 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
526 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
527 >> 32));
528 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
529 } else {
530 wqe->read.stag_src = cpu_to_be32(2);
531 wqe->read.to_src_hi = 0;
532 wqe->read.to_src_lo = 0;
533 wqe->read.stag_sink = cpu_to_be32(2);
534 wqe->read.plen = 0;
535 wqe->read.to_sink_hi = 0;
536 wqe->read.to_sink_lo = 0;
537 }
538 wqe->read.r2 = 0;
539 wqe->read.r5 = 0;
540 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
541 return 0;
542}
543
544static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
545 struct ib_recv_wr *wr, u8 *len16)
546{
d37ac31d 547 int ret;
cfdda9d7 548
d37ac31d
SW		 549 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
550 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
551 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
552 if (ret)
553 return ret;
cfdda9d7
SW		 554 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
555 wr->num_sge * sizeof(struct fw_ri_sge), 16);
556 return 0;
557}
558
40dbf6ee 559static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
42b6a949 560 struct ib_send_wr *wr, u8 *len16, u8 t5dev)
cfdda9d7
SW		 561{
562
563 struct fw_ri_immd *imdp;
564 __be64 *p;
565 int i;
566 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
40dbf6ee 567 int rem;
cfdda9d7 568
a03d9f94
SW		 569 if (wr->wr.fast_reg.page_list_len >
570 t4_max_fr_depth(use_dsgl))
cfdda9d7
SW		 571 return -EINVAL;
572
573 wqe->fr.qpbinde_to_dcacpu = 0;
574 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
575 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
576 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
577 wqe->fr.len_hi = 0;
578 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
579 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
580 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
581 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
582 0xffffffff);
42b6a949
VP		 583
584 if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
585 struct c4iw_fr_page_list *c4pl =
586 to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
587 struct fw_ri_dsgl *sglp;
588
589 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
590 wr->wr.fast_reg.page_list->page_list[i] = (__force u64)
591 cpu_to_be64((u64)
592 wr->wr.fast_reg.page_list->page_list[i]);
593 }
594
595 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
596 sglp->op = FW_RI_DATA_DSGL;
597 sglp->r1 = 0;
598 sglp->nsge = cpu_to_be16(1);
599 sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
600 sglp->len0 = cpu_to_be32(pbllen);
601
602 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
603 } else {
604 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
605 imdp->op = FW_RI_DATA_IMMD;
606 imdp->r1 = 0;
607 imdp->r2 = 0;
608 imdp->immdlen = cpu_to_be32(pbllen);
609 p = (__be64 *)(imdp + 1);
610 rem = pbllen;
611 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
612 *p = cpu_to_be64(
613 (u64)wr->wr.fast_reg.page_list->page_list[i]);
614 rem -= sizeof(*p);
615 if (++p == (__be64 *)&sq->queue[sq->size])
616 p = (__be64 *)sq->queue;
617 }
618 BUG_ON(rem < 0);
619 while (rem) {
620 *p = 0;
621 rem -= sizeof(*p);
622 if (++p == (__be64 *)&sq->queue[sq->size])
623 p = (__be64 *)sq->queue;
624 }
625 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
626 + pbllen, 16);
cfdda9d7
SW		 627 }
628 return 0;
629}
630
631static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
632 u8 *len16)
633{
634 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
635 wqe->inv.r2 = 0;
636 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
637 return 0;
638}
639
640void c4iw_qp_add_ref(struct ib_qp *qp)
641{
642 PDBG("%s ib_qp %p\n", __func__, qp);
643 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
644}
645
646void c4iw_qp_rem_ref(struct ib_qp *qp)
647{
648 PDBG("%s ib_qp %p\n", __func__, qp);
649 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
650 wake_up(&(to_c4iw_qp(qp)->wait));
651}
652
05eb2389
SW		 653static void add_to_fc_list(struct list_head *head, struct list_head *entry)
654{
655 if (list_empty(entry))
656 list_add_tail(entry, head);
657}
658
659static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
660{
661 unsigned long flags;
662
663 spin_lock_irqsave(&qhp->rhp->lock, flags);
664 spin_lock(&qhp->lock);
fa658a98
SW		 665 if (qhp->rhp->db_state == NORMAL)
666 t4_ring_sq_db(&qhp->wq, inc,
667 is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL);
668 else {
05eb2389
SW		 669 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
670 qhp->wq.sq.wq_pidx_inc += inc;
671 }
672 spin_unlock(&qhp->lock);
673 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
674 return 0;
675}
676
677static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
678{
679 unsigned long flags;
680
681 spin_lock_irqsave(&qhp->rhp->lock, flags);
682 spin_lock(&qhp->lock);
fa658a98
SW		 683 if (qhp->rhp->db_state == NORMAL)
684 t4_ring_rq_db(&qhp->wq, inc,
685 is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL);
686 else {
05eb2389
SW		 687 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
688 qhp->wq.rq.wq_pidx_inc += inc;
689 }
690 spin_unlock(&qhp->lock);
691 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
692 return 0;
693}
694
cfdda9d7
SW		 695int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
696 struct ib_send_wr **bad_wr)
697{
698 int err = 0;
699 u8 len16 = 0;
700 enum fw_wr_opcodes fw_opcode = 0;
701 enum fw_ri_wr_flags fw_flags;
702 struct c4iw_qp *qhp;
fa658a98 703 union t4_wr *wqe = NULL;
cfdda9d7
SW		 704 u32 num_wrs;
705 struct t4_swsqe *swsqe;
706 unsigned long flag;
707 u16 idx = 0;
708
709 qhp = to_c4iw_qp(ibqp);
710 spin_lock_irqsave(&qhp->lock, flag);
711 if (t4_wq_in_error(&qhp->wq)) {
712 spin_unlock_irqrestore(&qhp->lock, flag);
713 return -EINVAL;
714 }
715 num_wrs = t4_sq_avail(&qhp->wq);
716 if (num_wrs == 0) {
717 spin_unlock_irqrestore(&qhp->lock, flag);
718 return -ENOMEM;
719 }
720 while (wr) {
721 if (num_wrs == 0) {
722 err = -ENOMEM;
723 *bad_wr = wr;
724 break;
725 }
d37ac31d
SW		 726 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
727 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
728
cfdda9d7
SW		 729 fw_flags = 0;
730 if (wr->send_flags & IB_SEND_SOLICITED)
731 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
ba32de9d 732 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
cfdda9d7
SW		 733 fw_flags |= FW_RI_COMPLETION_FLAG;
734 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
735 switch (wr->opcode) {
736 case IB_WR_SEND_WITH_INV:
737 case IB_WR_SEND:
738 if (wr->send_flags & IB_SEND_FENCE)
739 fw_flags |= FW_RI_READ_FENCE_FLAG;
740 fw_opcode = FW_RI_SEND_WR;
741 if (wr->opcode == IB_WR_SEND)
742 swsqe->opcode = FW_RI_SEND;
743 else
744 swsqe->opcode = FW_RI_SEND_WITH_INV;
d37ac31d 745 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 746 break;
747 case IB_WR_RDMA_WRITE:
748 fw_opcode = FW_RI_RDMA_WRITE_WR;
749 swsqe->opcode = FW_RI_RDMA_WRITE;
d37ac31d 750 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 751 break;
752 case IB_WR_RDMA_READ:
2f1fb507 753 case IB_WR_RDMA_READ_WITH_INV:
cfdda9d7
SW		 754 fw_opcode = FW_RI_RDMA_READ_WR;
755 swsqe->opcode = FW_RI_READ_REQ;
2f1fb507 756 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
410ade4c 757 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
2f1fb507
SW		 758 else
759 fw_flags = 0;
cfdda9d7
SW		 760 err = build_rdma_read(wqe, wr, &len16);
761 if (err)
762 break;
763 swsqe->read_len = wr->sg_list[0].length;
764 if (!qhp->wq.sq.oldest_read)
765 qhp->wq.sq.oldest_read = swsqe;
766 break;
767 case IB_WR_FAST_REG_MR:
768 fw_opcode = FW_RI_FR_NSMR_WR;
769 swsqe->opcode = FW_RI_FAST_REGISTER;
42b6a949
VP		 770 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16,
771 is_t5(
772 qhp->rhp->rdev.lldi.adapter_type) ?
773 1 : 0);
cfdda9d7
SW		 774 break;
775 case IB_WR_LOCAL_INV:
4ab1eb9c
SW		 776 if (wr->send_flags & IB_SEND_FENCE)
777 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
cfdda9d7
SW		 778 fw_opcode = FW_RI_INV_LSTAG_WR;
779 swsqe->opcode = FW_RI_LOCAL_INV;
780 err = build_inv_stag(wqe, wr, &len16);
781 break;
782 default:
783 PDBG("%s post of type=%d TBD!\n", __func__,
784 wr->opcode);
785 err = -EINVAL;
786 }
787 if (err) {
788 *bad_wr = wr;
789 break;
790 }
791 swsqe->idx = qhp->wq.sq.pidx;
792 swsqe->complete = 0;
ba32de9d
SW		 793 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
794 qhp->sq_sig_all;
1cf24dce 795 swsqe->flushed = 0;
cfdda9d7
SW		 796 swsqe->wr_id = wr->wr_id;
797
798 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
799
800 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
801 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
802 swsqe->opcode, swsqe->read_len);
803 wr = wr->next;
804 num_wrs--;
d37ac31d
SW		 805 t4_sq_produce(&qhp->wq, len16);
806 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7 807 }
05eb2389 808 if (!qhp->rhp->rdev.status_page->db_off) {
fa658a98
SW		 809 t4_ring_sq_db(&qhp->wq, idx,
810 is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe);
05eb2389
SW		 811 spin_unlock_irqrestore(&qhp->lock, flag);
812 } else {
813 spin_unlock_irqrestore(&qhp->lock, flag);
814 ring_kernel_sq_db(qhp, idx);
815 }
cfdda9d7
SW		 816 return err;
817}
818
819int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
820 struct ib_recv_wr **bad_wr)
821{
822 int err = 0;
823 struct c4iw_qp *qhp;
fa658a98 824 union t4_recv_wr *wqe = NULL;
cfdda9d7
SW		 825 u32 num_wrs;
826 u8 len16 = 0;
827 unsigned long flag;
828 u16 idx = 0;
829
830 qhp = to_c4iw_qp(ibqp);
831 spin_lock_irqsave(&qhp->lock, flag);
832 if (t4_wq_in_error(&qhp->wq)) {
833 spin_unlock_irqrestore(&qhp->lock, flag);
834 return -EINVAL;
835 }
836 num_wrs = t4_rq_avail(&qhp->wq);
837 if (num_wrs == 0) {
838 spin_unlock_irqrestore(&qhp->lock, flag);
839 return -ENOMEM;
840 }
841 while (wr) {
842 if (wr->num_sge > T4_MAX_RECV_SGE) {
843 err = -EINVAL;
844 *bad_wr = wr;
845 break;
846 }
d37ac31d
SW		 847 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
848 qhp->wq.rq.wq_pidx *
849 T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 850 if (num_wrs)
851 err = build_rdma_recv(qhp, wqe, wr, &len16);
852 else
853 err = -ENOMEM;
854 if (err) {
855 *bad_wr = wr;
856 break;
857 }
858
859 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
860
861 wqe->recv.opcode = FW_RI_RECV_WR;
862 wqe->recv.r1 = 0;
863 wqe->recv.wrid = qhp->wq.rq.pidx;
864 wqe->recv.r2[0] = 0;
865 wqe->recv.r2[1] = 0;
866 wqe->recv.r2[2] = 0;
867 wqe->recv.len16 = len16;
cfdda9d7
SW		 868 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
869 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
d37ac31d
SW		 870 t4_rq_produce(&qhp->wq, len16);
871 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 872 wr = wr->next;
873 num_wrs--;
cfdda9d7 874 }
05eb2389 875 if (!qhp->rhp->rdev.status_page->db_off) {
fa658a98
SW		 876 t4_ring_rq_db(&qhp->wq, idx,
877 is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe);
05eb2389
SW		 878 spin_unlock_irqrestore(&qhp->lock, flag);
879 } else {
880 spin_unlock_irqrestore(&qhp->lock, flag);
881 ring_kernel_rq_db(qhp, idx);
882 }
cfdda9d7
SW		 883 return err;
884}
885
886int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
887{
888 return -ENOSYS;
889}
890
891static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
892 u8 *ecode)
893{
894 int status;
895 int tagged;
896 int opcode;
897 int rqtype;
898 int send_inv;
899
900 if (!err_cqe) {
901 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
902 *ecode = 0;
903 return;
904 }
905
906 status = CQE_STATUS(err_cqe);
907 opcode = CQE_OPCODE(err_cqe);
908 rqtype = RQ_TYPE(err_cqe);
909 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
910 (opcode == FW_RI_SEND_WITH_SE_INV);
911 tagged = (opcode == FW_RI_RDMA_WRITE) ||
912 (rqtype && (opcode == FW_RI_READ_RESP));
913
914 switch (status) {
915 case T4_ERR_STAG:
916 if (send_inv) {
917 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
918 *ecode = RDMAP_CANT_INV_STAG;
919 } else {
920 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
921 *ecode = RDMAP_INV_STAG;
922 }
923 break;
924 case T4_ERR_PDID:
925 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
926 if ((opcode == FW_RI_SEND_WITH_INV) ||
927 (opcode == FW_RI_SEND_WITH_SE_INV))
928 *ecode = RDMAP_CANT_INV_STAG;
929 else
930 *ecode = RDMAP_STAG_NOT_ASSOC;
931 break;
932 case T4_ERR_QPID:
933 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
934 *ecode = RDMAP_STAG_NOT_ASSOC;
935 break;
936 case T4_ERR_ACCESS:
937 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
938 *ecode = RDMAP_ACC_VIOL;
939 break;
940 case T4_ERR_WRAP:
941 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
942 *ecode = RDMAP_TO_WRAP;
943 break;
944 case T4_ERR_BOUND:
945 if (tagged) {
946 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
947 *ecode = DDPT_BASE_BOUNDS;
948 } else {
949 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
950 *ecode = RDMAP_BASE_BOUNDS;
951 }
952 break;
953 case T4_ERR_INVALIDATE_SHARED_MR:
954 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
955 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
956 *ecode = RDMAP_CANT_INV_STAG;
957 break;
958 case T4_ERR_ECC:
959 case T4_ERR_ECC_PSTAG:
960 case T4_ERR_INTERNAL_ERR:
961 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
962 *ecode = 0;
963 break;
964 case T4_ERR_OUT_OF_RQE:
965 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
966 *ecode = DDPU_INV_MSN_NOBUF;
967 break;
968 case T4_ERR_PBL_ADDR_BOUND:
969 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
970 *ecode = DDPT_BASE_BOUNDS;
971 break;
972 case T4_ERR_CRC:
973 *layer_type = LAYER_MPA|DDP_LLP;
974 *ecode = MPA_CRC_ERR;
975 break;
976 case T4_ERR_MARKER:
977 *layer_type = LAYER_MPA|DDP_LLP;
978 *ecode = MPA_MARKER_ERR;
979 break;
980 case T4_ERR_PDU_LEN_ERR:
981 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
982 *ecode = DDPU_MSG_TOOBIG;
983 break;
984 case T4_ERR_DDP_VERSION:
985 if (tagged) {
986 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
987 *ecode = DDPT_INV_VERS;
988 } else {
989 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
990 *ecode = DDPU_INV_VERS;
991 }
992 break;
993 case T4_ERR_RDMA_VERSION:
994 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
995 *ecode = RDMAP_INV_VERS;
996 break;
997 case T4_ERR_OPCODE:
998 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
999 *ecode = RDMAP_INV_OPCODE;
1000 break;
1001 case T4_ERR_DDP_QUEUE_NUM:
1002 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1003 *ecode = DDPU_INV_QN;
1004 break;
1005 case T4_ERR_MSN:
1006 case T4_ERR_MSN_GAP:
1007 case T4_ERR_MSN_RANGE:
1008 case T4_ERR_IRD_OVERFLOW:
1009 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1010 *ecode = DDPU_INV_MSN_RANGE;
1011 break;
1012 case T4_ERR_TBIT:
1013 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1014 *ecode = 0;
1015 break;
1016 case T4_ERR_MO:
1017 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1018 *ecode = DDPU_INV_MO;
1019 break;
1020 default:
1021 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1022 *ecode = 0;
1023 break;
1024 }
1025}
1026
be4c9bad
RD		 1027static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1028 gfp_t gfp)
cfdda9d7
SW		 1029{
1030 struct fw_ri_wr *wqe;
1031 struct sk_buff *skb;
1032 struct terminate_message *term;
1033
1034 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1035 qhp->ep->hwtid);
1036
be4c9bad 1037 skb = alloc_skb(sizeof *wqe, gfp);
cfdda9d7 1038 if (!skb)
be4c9bad 1039 return;
cfdda9d7
SW		 1040 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1041
1042 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1043 memset(wqe, 0, sizeof *wqe);
1044 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
1045 wqe->flowid_len16 = cpu_to_be32(
1046 FW_WR_FLOWID(qhp->ep->hwtid) |
1047 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1048
1049 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1050 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1051 term = (struct terminate_message *)wqe->u.terminate.termmsg;
d2fe99e8
KS		 1052 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1053 term->layer_etype = qhp->attr.layer_etype;
1054 term->ecode = qhp->attr.ecode;
1055 } else
1056 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
be4c9bad 1057 c4iw_ofld_send(&qhp->rhp->rdev, skb);
cfdda9d7
SW		 1058}
1059
1060/*
1061 * Assumes qhp lock is held.
1062 */
1063static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
2f5b48c3 1064 struct c4iw_cq *schp)
cfdda9d7
SW		 1065{
1066 int count;
1067 int flushed;
2f5b48c3 1068 unsigned long flag;
cfdda9d7
SW		 1069
1070 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
cfdda9d7 1071
732bee7a 1072 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 1073 spin_lock_irqsave(&rchp->lock, flag);
cfdda9d7 1074 spin_lock(&qhp->lock);
1cf24dce
SW		 1075
1076 if (qhp->wq.flushed) {
1077 spin_unlock(&qhp->lock);
1078 spin_unlock_irqrestore(&rchp->lock, flag);
1079 return;
1080 }
1081 qhp->wq.flushed = 1;
1082
1083 c4iw_flush_hw_cq(rchp);
cfdda9d7
SW		 1084 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1085 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1086 spin_unlock(&qhp->lock);
2f5b48c3 1087 spin_unlock_irqrestore(&rchp->lock, flag);
581bbe2c
KS		 1088 if (flushed) {
1089 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
cfdda9d7 1090 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
581bbe2c
KS		 1091 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1092 }
cfdda9d7 1093
732bee7a 1094 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 1095 spin_lock_irqsave(&schp->lock, flag);
cfdda9d7 1096 spin_lock(&qhp->lock);
1cf24dce
SW		 1097 if (schp != rchp)
1098 c4iw_flush_hw_cq(schp);
1099 flushed = c4iw_flush_sq(qhp);
cfdda9d7 1100 spin_unlock(&qhp->lock);
2f5b48c3 1101 spin_unlock_irqrestore(&schp->lock, flag);
581bbe2c
KS		 1102 if (flushed) {
1103 spin_lock_irqsave(&schp->comp_handler_lock, flag);
cfdda9d7 1104 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
581bbe2c
KS		 1105 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1106 }
cfdda9d7
SW		 1107}
1108
2f5b48c3 1109static void flush_qp(struct c4iw_qp *qhp)
cfdda9d7
SW		 1110{
1111 struct c4iw_cq *rchp, *schp;
581bbe2c 1112 unsigned long flag;
cfdda9d7 1113
1cf24dce
SW		 1114 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1115 schp = to_c4iw_cq(qhp->ibqp.send_cq);
cfdda9d7 1116
1cf24dce 1117 t4_set_wq_in_error(&qhp->wq);
cfdda9d7 1118 if (qhp->ibqp.uobject) {
cfdda9d7 1119 t4_set_cq_in_error(&rchp->cq);
581bbe2c 1120 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
01e7da6b 1121 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
581bbe2c 1122 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
01e7da6b 1123 if (schp != rchp) {
cfdda9d7 1124 t4_set_cq_in_error(&schp->cq);
581bbe2c 1125 spin_lock_irqsave(&schp->comp_handler_lock, flag);
01e7da6b
KS		 1126 (*schp->ibcq.comp_handler)(&schp->ibcq,
1127 schp->ibcq.cq_context);
581bbe2c 1128 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
01e7da6b 1129 }
cfdda9d7
SW		 1130 return;
1131 }
2f5b48c3 1132 __flush_qp(qhp, rchp, schp);
cfdda9d7
SW		 1133}
1134
73d6fcad
SW		 1135static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1136 struct c4iw_ep *ep)
cfdda9d7
SW		 1137{
1138 struct fw_ri_wr *wqe;
1139 int ret;
cfdda9d7
SW		 1140 struct sk_buff *skb;
1141
1142 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
73d6fcad 1143 ep->hwtid);
cfdda9d7 1144
d3c814e8 1145 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1146 if (!skb)
1147 return -ENOMEM;
73d6fcad 1148 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
cfdda9d7
SW		 1149
1150 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1151 memset(wqe, 0, sizeof *wqe);
1152 wqe->op_compl = cpu_to_be32(
1153 FW_WR_OP(FW_RI_INIT_WR) |
1154 FW_WR_COMPL(1));
1155 wqe->flowid_len16 = cpu_to_be32(
73d6fcad 1156 FW_WR_FLOWID(ep->hwtid) |
cfdda9d7 1157 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
2f5b48c3 1158 wqe->cookie = (unsigned long) &ep->com.wr_wait;
cfdda9d7
SW		 1159
1160 wqe->u.fini.type = FW_RI_TYPE_FINI;
cfdda9d7
SW		 1161 ret = c4iw_ofld_send(&rhp->rdev, skb);
1162 if (ret)
1163 goto out;
1164
2f5b48c3 1165 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
aadc4df3 1166 qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1167out:
1168 PDBG("%s ret %d\n", __func__, ret);
1169 return ret;
1170}
1171
1172static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1173{
d2fe99e8 1174 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
cfdda9d7
SW		 1175 memset(&init->u, 0, sizeof init->u);
1176 switch (p2p_type) {
1177 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1178 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1179 init->u.write.stag_sink = cpu_to_be32(1);
1180 init->u.write.to_sink = cpu_to_be64(1);
1181 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1182 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1183 sizeof(struct fw_ri_immd),
1184 16);
1185 break;
1186 case FW_RI_INIT_P2PTYPE_READ_REQ:
1187 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1188 init->u.read.stag_src = cpu_to_be32(1);
1189 init->u.read.to_src_lo = cpu_to_be32(1);
1190 init->u.read.stag_sink = cpu_to_be32(1);
1191 init->u.read.to_sink_lo = cpu_to_be32(1);
1192 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1193 break;
1194 }
1195}
1196
1197static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1198{
1199 struct fw_ri_wr *wqe;
1200 int ret;
cfdda9d7
SW		 1201 struct sk_buff *skb;
1202
1203 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1204 qhp->ep->hwtid);
1205
d3c814e8 1206 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1207 if (!skb)
1208 return -ENOMEM;
1209 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1210
1211 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1212 memset(wqe, 0, sizeof *wqe);
1213 wqe->op_compl = cpu_to_be32(
1214 FW_WR_OP(FW_RI_INIT_WR) |
1215 FW_WR_COMPL(1));
1216 wqe->flowid_len16 = cpu_to_be32(
1217 FW_WR_FLOWID(qhp->ep->hwtid) |
1218 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1219
2f5b48c3 1220 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
cfdda9d7
SW		 1221
1222 wqe->u.init.type = FW_RI_TYPE_INIT;
1223 wqe->u.init.mpareqbit_p2ptype =
1224 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1225 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1226 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1227 if (qhp->attr.mpa_attr.recv_marker_enabled)
1228 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1229 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1230 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1231 if (qhp->attr.mpa_attr.crc_enabled)
1232 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1233
1234 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1235 FW_RI_QP_RDMA_WRITE_ENABLE |
1236 FW_RI_QP_BIND_ENABLE;
1237 if (!qhp->ibqp.uobject)
1238 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1239 FW_RI_QP_STAG0_ENABLE;
1240 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1241 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1242 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1243 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1244 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1245 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1246 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1247 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1248 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1249 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1250 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1251 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1252 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1253 rhp->rdev.lldi.vr->rq.start);
1254 if (qhp->attr.mpa_attr.initiator)
1255 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1256
cfdda9d7
SW		 1257 ret = c4iw_ofld_send(&rhp->rdev, skb);
1258 if (ret)
1259 goto out;
1260
2f5b48c3
SW		 1261 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1262 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1263out:
1264 PDBG("%s ret %d\n", __func__, ret);
1265 return ret;
1266}
1267
1268int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1269 enum c4iw_qp_attr_mask mask,
1270 struct c4iw_qp_attributes *attrs,
1271 int internal)
1272{
1273 int ret = 0;
1274 struct c4iw_qp_attributes newattr = qhp->attr;
cfdda9d7
SW		 1275 int disconnect = 0;
1276 int terminate = 0;
1277 int abort = 0;
1278 int free = 0;
1279 struct c4iw_ep *ep = NULL;
1280
1281 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1282 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1283 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1284
2f5b48c3 1285 mutex_lock(&qhp->mutex);
cfdda9d7
SW		 1286
1287 /* Process attr changes if in IDLE */
1288 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1289 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1290 ret = -EIO;
1291 goto out;
1292 }
1293 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1294 newattr.enable_rdma_read = attrs->enable_rdma_read;
1295 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1296 newattr.enable_rdma_write = attrs->enable_rdma_write;
1297 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1298 newattr.enable_bind = attrs->enable_bind;
1299 if (mask & C4IW_QP_ATTR_MAX_ORD) {
be4c9bad 1300 if (attrs->max_ord > c4iw_max_read_depth) {
cfdda9d7
SW		 1301 ret = -EINVAL;
1302 goto out;
1303 }
1304 newattr.max_ord = attrs->max_ord;
1305 }
1306 if (mask & C4IW_QP_ATTR_MAX_IRD) {
be4c9bad 1307 if (attrs->max_ird > c4iw_max_read_depth) {
cfdda9d7
SW		 1308 ret = -EINVAL;
1309 goto out;
1310 }
1311 newattr.max_ird = attrs->max_ird;
1312 }
1313 qhp->attr = newattr;
1314 }
1315
2c974781 1316 if (mask & C4IW_QP_ATTR_SQ_DB) {
05eb2389 1317 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
2c974781
VP		 1318 goto out;
1319 }
1320 if (mask & C4IW_QP_ATTR_RQ_DB) {
05eb2389 1321 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
2c974781
VP		 1322 goto out;
1323 }
1324
cfdda9d7
SW		 1325 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1326 goto out;
1327 if (qhp->attr.state == attrs->next_state)
1328 goto out;
1329
1330 switch (qhp->attr.state) {
1331 case C4IW_QP_STATE_IDLE:
1332 switch (attrs->next_state) {
1333 case C4IW_QP_STATE_RTS:
1334 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1335 ret = -EINVAL;
1336 goto out;
1337 }
1338 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1339 ret = -EINVAL;
1340 goto out;
1341 }
1342 qhp->attr.mpa_attr = attrs->mpa_attr;
1343 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1344 qhp->ep = qhp->attr.llp_stream_handle;
2f5b48c3 1345 set_state(qhp, C4IW_QP_STATE_RTS);
cfdda9d7
SW		 1346
1347 /*
1348 * Ref the endpoint here and deref when we
1349 * disassociate the endpoint from the QP. This
1350 * happens in CLOSING->IDLE transition or *->ERROR
1351 * transition.
1352 */
1353 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1354 ret = rdma_init(rhp, qhp);
cfdda9d7
SW		 1355 if (ret)
1356 goto err;
1357 break;
1358 case C4IW_QP_STATE_ERROR:
2f5b48c3
SW		 1359 set_state(qhp, C4IW_QP_STATE_ERROR);
1360 flush_qp(qhp);
cfdda9d7
SW		 1361 break;
1362 default:
1363 ret = -EINVAL;
1364 goto out;
1365 }
1366 break;
1367 case C4IW_QP_STATE_RTS:
1368 switch (attrs->next_state) {
1369 case C4IW_QP_STATE_CLOSING:
1370 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
b4e2901c 1371 t4_set_wq_in_error(&qhp->wq);
2f5b48c3 1372 set_state(qhp, C4IW_QP_STATE_CLOSING);
73d6fcad 1373 ep = qhp->ep;
cfdda9d7
SW		 1374 if (!internal) {
1375 abort = 0;
1376 disconnect = 1;
2f5b48c3 1377 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1378 }
73d6fcad 1379 ret = rdma_fini(rhp, qhp, ep);
8da7e7a5 1380 if (ret)
cfdda9d7 1381 goto err;
cfdda9d7
SW		 1382 break;
1383 case C4IW_QP_STATE_TERMINATE:
b4e2901c 1384 t4_set_wq_in_error(&qhp->wq);
2f5b48c3 1385 set_state(qhp, C4IW_QP_STATE_TERMINATE);
d2fe99e8
KS		 1386 qhp->attr.layer_etype = attrs->layer_etype;
1387 qhp->attr.ecode = attrs->ecode;
be4c9bad 1388 ep = qhp->ep;
09992579 1389 disconnect = 1;
0e42c1f4
SW		 1390 if (!internal)
1391 terminate = 1;
09992579
SW		 1392 else {
1393 ret = rdma_fini(rhp, qhp, ep);
1394 if (ret)
1395 goto err;
1396 }
2f5b48c3 1397 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1398 break;
1399 case C4IW_QP_STATE_ERROR:
1cf24dce 1400 t4_set_wq_in_error(&qhp->wq);
b4e2901c 1401 set_state(qhp, C4IW_QP_STATE_ERROR);
cfdda9d7
SW		 1402 if (!internal) {
1403 abort = 1;
1404 disconnect = 1;
1405 ep = qhp->ep;
2f5b48c3 1406 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1407 }
1408 goto err;
1409 break;
1410 default:
1411 ret = -EINVAL;
1412 goto out;
1413 }
1414 break;
1415 case C4IW_QP_STATE_CLOSING:
1416 if (!internal) {
1417 ret = -EINVAL;
1418 goto out;
1419 }
1420 switch (attrs->next_state) {
1421 case C4IW_QP_STATE_IDLE:
2f5b48c3
SW		 1422 flush_qp(qhp);
1423 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1424 qhp->attr.llp_stream_handle = NULL;
1425 c4iw_put_ep(&qhp->ep->com);
1426 qhp->ep = NULL;
1427 wake_up(&qhp->wait);
1428 break;
1429 case C4IW_QP_STATE_ERROR:
1430 goto err;
1431 default:
1432 ret = -EINVAL;
1433 goto err;
1434 }
1435 break;
1436 case C4IW_QP_STATE_ERROR:
1437 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1438 ret = -EINVAL;
1439 goto out;
1440 }
1441 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1442 ret = -EINVAL;
1443 goto out;
1444 }
2f5b48c3 1445 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1446 break;
1447 case C4IW_QP_STATE_TERMINATE:
1448 if (!internal) {
1449 ret = -EINVAL;
1450 goto out;
1451 }
1452 goto err;
1453 break;
1454 default:
1455 printk(KERN_ERR "%s in a bad state %d\n",
1456 __func__, qhp->attr.state);
1457 ret = -EINVAL;
1458 goto err;
1459 break;
1460 }
1461 goto out;
1462err:
1463 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1464 qhp->wq.sq.qid);
1465
1466 /* disassociate the LLP connection */
1467 qhp->attr.llp_stream_handle = NULL;
af93fb5d
SW		 1468 if (!ep)
1469 ep = qhp->ep;
cfdda9d7 1470 qhp->ep = NULL;
2f5b48c3 1471 set_state(qhp, C4IW_QP_STATE_ERROR);
cfdda9d7 1472 free = 1;
91e9c071 1473 abort = 1;
cfdda9d7
SW		 1474 wake_up(&qhp->wait);
1475 BUG_ON(!ep);
2f5b48c3 1476 flush_qp(qhp);
cfdda9d7 1477out:
2f5b48c3 1478 mutex_unlock(&qhp->mutex);
cfdda9d7
SW		 1479
1480 if (terminate)
be4c9bad 1481 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
cfdda9d7
SW		 1482
1483 /*
1484 * If disconnect is 1, then we need to initiate a disconnect
1485 * on the EP. This can be a normal close (RTS->CLOSING) or
1486 * an abnormal close (RTS/CLOSING->ERROR).
1487 */
1488 if (disconnect) {
be4c9bad
RD		 1489 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1490 GFP_KERNEL);
cfdda9d7
SW		 1491 c4iw_put_ep(&ep->com);
1492 }
1493
1494 /*
1495 * If free is 1, then we've disassociated the EP from the QP
1496 * and we need to dereference the EP.
1497 */
1498 if (free)
1499 c4iw_put_ep(&ep->com);
cfdda9d7
SW		 1500 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1501 return ret;
1502}
1503
1504int c4iw_destroy_qp(struct ib_qp *ib_qp)
1505{
1506 struct c4iw_dev *rhp;
1507 struct c4iw_qp *qhp;
1508 struct c4iw_qp_attributes attrs;
1509 struct c4iw_ucontext *ucontext;
1510
1511 qhp = to_c4iw_qp(ib_qp);
1512 rhp = qhp->rhp;
1513
1514 attrs.next_state = C4IW_QP_STATE_ERROR;
d2fe99e8
KS		 1515 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1516 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1517 else
1518 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
cfdda9d7
SW		 1519 wait_event(qhp->wait, !qhp->ep);
1520
05eb2389 1521 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
cfdda9d7
SW		 1522 atomic_dec(&qhp->refcnt);
1523 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1524
05eb2389
SW		 1525 spin_lock_irq(&rhp->lock);
1526 if (!list_empty(&qhp->db_fc_entry))
1527 list_del_init(&qhp->db_fc_entry);
1528 spin_unlock_irq(&rhp->lock);
1529
cfdda9d7
SW		 1530 ucontext = ib_qp->uobject ?
1531 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1532 destroy_qp(&rhp->rdev, &qhp->wq,
1533 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1534
1535 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1536 kfree(qhp);
1537 return 0;
1538}
1539
1540struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1541 struct ib_udata *udata)
1542{
1543 struct c4iw_dev *rhp;
1544 struct c4iw_qp *qhp;
1545 struct c4iw_pd *php;
1546 struct c4iw_cq *schp;
1547 struct c4iw_cq *rchp;
1548 struct c4iw_create_qp_resp uresp;
ff1706f4 1549 unsigned int sqsize, rqsize;
cfdda9d7
SW		 1550 struct c4iw_ucontext *ucontext;
1551 int ret;
c6d7b267 1552 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
cfdda9d7
SW		 1553
1554 PDBG("%s ib_pd %p\n", __func__, pd);
1555
1556 if (attrs->qp_type != IB_QPT_RC)
1557 return ERR_PTR(-EINVAL);
1558
1559 php = to_c4iw_pd(pd);
1560 rhp = php->rhp;
1561 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1562 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1563 if (!schp || !rchp)
1564 return ERR_PTR(-EINVAL);
1565
1566 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1567 return ERR_PTR(-EINVAL);
1568
1569 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1570 if (rqsize > T4_MAX_RQ_SIZE)
1571 return ERR_PTR(-E2BIG);
1572
1573 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1574 if (sqsize > T4_MAX_SQ_SIZE)
1575 return ERR_PTR(-E2BIG);
1576
1577 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1578
cfdda9d7
SW		 1579 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1580 if (!qhp)
1581 return ERR_PTR(-ENOMEM);
1582 qhp->wq.sq.size = sqsize;
1583 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1cf24dce 1584 qhp->wq.sq.flush_cidx = -1;
cfdda9d7
SW		 1585 qhp->wq.rq.size = rqsize;
1586 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1587
1588 if (ucontext) {
1589 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1590 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1591 }
1592
1593 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1594 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1595
1596 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1597 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1598 if (ret)
1599 goto err1;
1600
1601 attrs->cap.max_recv_wr = rqsize - 1;
1602 attrs->cap.max_send_wr = sqsize - 1;
1603 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1604
1605 qhp->rhp = rhp;
1606 qhp->attr.pd = php->pdid;
1607 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1608 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1609 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1610 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1611 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1612 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1613 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1614 qhp->attr.state = C4IW_QP_STATE_IDLE;
1615 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1616 qhp->attr.enable_rdma_read = 1;
1617 qhp->attr.enable_rdma_write = 1;
1618 qhp->attr.enable_bind = 1;
1619 qhp->attr.max_ord = 1;
1620 qhp->attr.max_ird = 1;
ba32de9d 1621 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
cfdda9d7 1622 spin_lock_init(&qhp->lock);
2f5b48c3 1623 mutex_init(&qhp->mutex);
cfdda9d7
SW		 1624 init_waitqueue_head(&qhp->wait);
1625 atomic_set(&qhp->refcnt, 1);
1626
05eb2389 1627 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
cfdda9d7
SW		 1628 if (ret)
1629 goto err2;
1630
cfdda9d7
SW		 1631 if (udata) {
1632 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1633 if (!mm1) {
1634 ret = -ENOMEM;
30a6a62f 1635 goto err3;
cfdda9d7
SW		 1636 }
1637 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1638 if (!mm2) {
1639 ret = -ENOMEM;
30a6a62f 1640 goto err4;
cfdda9d7
SW		 1641 }
1642 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1643 if (!mm3) {
1644 ret = -ENOMEM;
30a6a62f 1645 goto err5;
cfdda9d7
SW		 1646 }
1647 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1648 if (!mm4) {
1649 ret = -ENOMEM;
30a6a62f 1650 goto err6;
cfdda9d7 1651 }
c6d7b267
SW		 1652 if (t4_sq_onchip(&qhp->wq.sq)) {
1653 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1654 if (!mm5) {
1655 ret = -ENOMEM;
1656 goto err7;
1657 }
1658 uresp.flags = C4IW_QPF_ONCHIP;
1659 } else
1660 uresp.flags = 0;
cfdda9d7
SW		 1661 uresp.qid_mask = rhp->rdev.qpmask;
1662 uresp.sqid = qhp->wq.sq.qid;
1663 uresp.sq_size = qhp->wq.sq.size;
1664 uresp.sq_memsize = qhp->wq.sq.memsize;
1665 uresp.rqid = qhp->wq.rq.qid;
1666 uresp.rq_size = qhp->wq.rq.size;
1667 uresp.rq_memsize = qhp->wq.rq.memsize;
1668 spin_lock(&ucontext->mmap_lock);
c6d7b267
SW		 1669 if (mm5) {
1670 uresp.ma_sync_key = ucontext->key;
1671 ucontext->key += PAGE_SIZE;
ae1fe07f
DC		 1672 } else {
1673 uresp.ma_sync_key = 0;
c6d7b267 1674 }
cfdda9d7
SW		 1675 uresp.sq_key = ucontext->key;
1676 ucontext->key += PAGE_SIZE;
1677 uresp.rq_key = ucontext->key;
1678 ucontext->key += PAGE_SIZE;
1679 uresp.sq_db_gts_key = ucontext->key;
1680 ucontext->key += PAGE_SIZE;
1681 uresp.rq_db_gts_key = ucontext->key;
1682 ucontext->key += PAGE_SIZE;
1683 spin_unlock(&ucontext->mmap_lock);
1684 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1685 if (ret)
c6d7b267 1686 goto err8;
cfdda9d7 1687 mm1->key = uresp.sq_key;
c6d7b267 1688 mm1->addr = qhp->wq.sq.phys_addr;
cfdda9d7
SW		 1689 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1690 insert_mmap(ucontext, mm1);
1691 mm2->key = uresp.rq_key;
1692 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1693 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1694 insert_mmap(ucontext, mm2);
1695 mm3->key = uresp.sq_db_gts_key;
fa658a98 1696 mm3->addr = (__force unsigned long) qhp->wq.sq.udb;
cfdda9d7
SW		 1697 mm3->len = PAGE_SIZE;
1698 insert_mmap(ucontext, mm3);
1699 mm4->key = uresp.rq_db_gts_key;
fa658a98 1700 mm4->addr = (__force unsigned long) qhp->wq.rq.udb;
cfdda9d7
SW		 1701 mm4->len = PAGE_SIZE;
1702 insert_mmap(ucontext, mm4);
c6d7b267
SW		 1703 if (mm5) {
1704 mm5->key = uresp.ma_sync_key;
1705 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1706 + A_PCIE_MA_SYNC) & PAGE_MASK;
1707 mm5->len = PAGE_SIZE;
1708 insert_mmap(ucontext, mm5);
1709 }
cfdda9d7
SW		 1710 }
1711 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1712 init_timer(&(qhp->timer));
05eb2389 1713 INIT_LIST_HEAD(&qhp->db_fc_entry);
cfdda9d7
SW		 1714 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1715 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1716 qhp->wq.sq.qid);
1717 return &qhp->ibqp;
c6d7b267
SW		 1718err8:
1719 kfree(mm5);
cfdda9d7 1720err7:
30a6a62f 1721 kfree(mm4);
cfdda9d7 1722err6:
30a6a62f 1723 kfree(mm3);
cfdda9d7 1724err5:
30a6a62f 1725 kfree(mm2);
cfdda9d7 1726err4:
30a6a62f 1727 kfree(mm1);
cfdda9d7
SW		 1728err3:
1729 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1730err2:
1731 destroy_qp(&rhp->rdev, &qhp->wq,
1732 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1733err1:
1734 kfree(qhp);
1735 return ERR_PTR(ret);
1736}
1737
1738int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1739 int attr_mask, struct ib_udata *udata)
1740{
1741 struct c4iw_dev *rhp;
1742 struct c4iw_qp *qhp;
1743 enum c4iw_qp_attr_mask mask = 0;
1744 struct c4iw_qp_attributes attrs;
1745
1746 PDBG("%s ib_qp %p\n", __func__, ibqp);
1747
1748 /* iwarp does not support the RTR state */
1749 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1750 attr_mask &= ~IB_QP_STATE;
1751
1752 /* Make sure we still have something left to do */
1753 if (!attr_mask)
1754 return 0;
1755
1756 memset(&attrs, 0, sizeof attrs);
1757 qhp = to_c4iw_qp(ibqp);
1758 rhp = qhp->rhp;
1759
1760 attrs.next_state = c4iw_convert_state(attr->qp_state);
1761 attrs.enable_rdma_read = (attr->qp_access_flags &
1762 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1763 attrs.enable_rdma_write = (attr->qp_access_flags &
1764 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1765 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1766
1767
1768 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1769 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1770 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1771 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1772 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1773
2c974781
VP		 1774 /*
1775 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1776 * ringing the queue db when we're in DB_FULL mode.
1777 */
1778 attrs.sq_db_inc = attr->sq_psn;
1779 attrs.rq_db_inc = attr->rq_psn;
1780 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1781 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1782
cfdda9d7
SW		 1783 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1784}
1785
1786struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1787{
1788 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1789 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1790}
67bbc055
VP		 1791
1792int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1793 int attr_mask, struct ib_qp_init_attr *init_attr)
1794{
1795 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1796
1797 memset(attr, 0, sizeof *attr);
1798 memset(init_attr, 0, sizeof *init_attr);
1799 attr->qp_state = to_ib_qp_state(qhp->attr.state);
1800 return 0;
1801}
Linux 6.x block layer and io_uring tree(s)